MC-242444F9-B95-BT3_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

MC-242444

MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND MOBILE SPECIFIED RAM

32M-BIT FLASH MEMORY AND 16M-BIT CMOS MOBILE SPECIFIED RAM

Description

The MC-242444 is a stacked type MCP (Multi-Chip Package) of 33,554,432 bits (BYTE mode : 4,194,304 words by 8

bits, WORD mode : 2,097,152 words by 16 bits) flash memory and 16,777,216 bits (1,048,576 words by 16 bits)

Mobile specified RAM.

The MC-242444 is packaged in a 77-pin TAPE FBGA and 71-pin TAPE FBGA.

Features

General Features

• Fast access time : t^ACC= 90 ns (MAX.), 85 ns (MAX.) (V^CCf ≥ 2.7 V) (Flash Memory)

t^AA= 80, 90, 100 ns (MAX.) (Mobile specified RAM)

• Supply voltage : V^CCf / V^CCm = 2.6 to 3.0 V

• Wide operating temperature : T^A= −20 to +70 °C

Flash Memory Features

• Two bank organization enabling simultaneous execution of erase / program and read

• Bank organization : 2 banks (16M bits + 16M bits)

• Memory organization : 4,194,304 words × 8 bits (BYTE mode)

2,097,152 words × 16 bits (WORD mode)

• Sector organization : 71 sectors (8K bytes / 4K words × 8 sectors, 64K bytes / 32K words × 63 sectors)

• Boot sector allocated to the highest address (sector)

• 3-state output

• Automatic program

• Program suspend / resume

• Unlock bypass program

• Automatic erase

• Chip erase

• Sector erase (sectors can be combined freely)

• Erase suspend / resume

• Program / Erase completion detection

• Detection through data polling and toggle bits

• Detection through RY (/BY) pin

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15411EJ4V0DS00 (4th edition)

Date Published July 2001 NS CP (K)

Printed in Japan

The mark ★ shows major revised points.

2001

©

MC-242444

• Sector group protection

• Any sector can be protected

• Any protected sector can be temporary unprotected

• Sectors can be used for boot application

• Hardware reset and standby using /RESET pin

• Automatic sleep mode

• Boot block sector protect by /WP (ACC) pin

• Conforms to common flash memory interface (CFI)

• Extra One Time Protect Sector provided

Mobile specified RAM Features

• Memory organization : 1,048,576 words by 16 bits

• Supply current :At operating : 35 mA (MAX.)

At Standby Mode 1 : 100 µA (MAX.)

At Standby Mode 2 : 10 µA (MAX.)

• Chip Enable inputs : /CEm

• Byte data control : /LB, /UB

• Standby Mode input : MODE

• Standby Mode 1 : Normal standby (Memory cell data hold valid)

• Standby Mode 2 : Memory cell data hold invalid

Ordering Information

Part number

Flash Memory

Boot sector

Flash Memory

Access time

ns (MAX.)

Mobile specified RAM

Access time

Package

ns (MAX.)

MC-242444F9-B90-BT3

MC-242444F9-B95-BT3^Note

MC-242444F9-B10-BT3

MC-242444F9-B90-BS1^Note

MC-242444F9-B95-BS1^Note

MC-242444F9-B10-BS1^Note

Highest address (sector)

(T type)

90

80

90

77-pin TAPE FBGA

85 (V^CCf ≥ 2.7 V)

(12 × 7)

100

80

71-pin TAPE FBGA

90

(11 × 7)

100

Note Under development

Data Sheet M15411EJ4V0DS

2

MC-242444

Pin Configurations

/xxx indicates active low signal.

77-pin TAPE FBGA (12 × 7)

Top View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

8

7

6

5

4

3

2

1

NC

A15

A12

A19

IC

A13

A9

IC

A16

CIOf

V

SS

NC

A11

A8

A14

A10

NC I/O15, A-1 I/O7

I/O14

I/O5

NC

I/O6

I/O13 I/O12

/WE MODE A20

I/O4

I/O3

VCCm

/WP(ACC) /RESET RY(/BY)

V

CC

f

I/O11

I/O2

I/O8

NC

/LB

A7

/UB

A6

A18

A5

A17

A4

I/O1

I/O9 I/O10

/OE

I/O0

/CEf /CEm

NC

V

SS

NC

A3

A2

A1

A0

NC

71-pin TAPE FBGA (11 × 7)

Top View

A

B

C

D

E

F

G

H

J

K

L

M

NC

8

7

6

5

4

3

2

1

A15

A12

A19

NC

A13

A9

IC

A16

CIOf

Vss

A11

A8

A14

A10

NC I/O15, A-1 I/O7 I/O14

I/O6 I/O13 I/O12 I/O5

/WE MODE A20

I/O4

I/O3

I/O9

/OE

/CEf

V

CCm

NC

/WP(ACC)/RESET RY(/BY)

VCC

f

I/O11

/LB

A7

/UB

A6

A18

A5

A17

A4

I/O1

Vss

A0

I/O10 I/O2

I/O0

I/O8

NC

A3

A2

A1

/CEm

NC

Common Pins

A0 - A19 : Address inputs

I/O0 - I/O15 : Data inputs / outputs

Flash Memory Pins

A20 : Address inputs

I/O15, A−1 : Data inputs / outputs 15 (WORD mode)

/OE

: Output Enable

: Write Enable

: Ground

LSB address input (BYTE mode)

/WE

/CEf

: Chip Enable

VSS

RY (/BY)

/RESET

V^CCf

: Ready (Busy) output

: Hardware reset input

: Supply Voltage

NC ^{Note 1}

IC ^{Note 2}

: No Connection

: Internal Connection

/WP(ACC) : Hardware Write Protect (Acceleration)

CIOf : Selects 8-bit or 16-bit mode

Mobile specified RAM Pins

/CEm : Chip Enable

MODE : Standby mode select

V^CCm : Supply Voltage

/LB, /UB : Byte data select

Note1. Some signals can be applied because this pin is not internally connected.

2. Leave this pin connected to V^SSor unconnected (Recommended to connected to V^SS).

Remark Refer to Package Drawings for the index mark.

Data Sheet M15411EJ4V0DS

3

MC-242444

Block Diagram

V

CCf

V

SS

A0 - A20

RY (/BY)

32 M-bit Flash Memory

/RESET

/CEf

4,194,304 words by 8 bits

2,097,152 words by 16 bits

CIOf

/WP(ACC)

V

CCm

V

SS

I/O0 - I/O15, A-1

A0 - A19

/WE

/OE

16 M-bit Mobile Specified RAM

(1,048,576 words by 16 bits)

/CEm

MODE

/LB

/UB

Data Sheet M15411EJ4V0DS

4

MC-242444

Bus Operations Table

Operation

Flash Memory

Mobile specified RAM

Common

/RESET /CEf CIOf /WP(ACC) /CEm MODE /LB /UB

/OE

/WE

I/O0 - I/O7 I/O8-I/O15

Full standby Standby Mode 1

Standby Mode 2

H

×

H

L

H

×

Hi-Z

L

Output disable

H

L

×

L

×

H

L

H

Hi-Z

Read (Flash

Memory ^{Note 1}

Write (Flash

Memory)

BYTE mode

WORD mode

BYTE mode

WORD mode

Note 2

Data Out

Data In

Hi-Z or

)

H

L

Data Out

Hi-Z

H

L

×

Note 2

H

L

H

×

Data In

Hi-Z or

Temporary sector group

unprotect

V^ID

×

Data In/Out Data In/Out

Hi-Z or Hi-Z or

Data In/Out Data In/Out

Boot block sector protect

×

L

×

Flash Memory hardware reset

Read

L

×

L

×

Hi-Z

Data Out

Hi-Z

Note 3

L

H

L

H

Data Out

(Mobile specified RAM)

H

L

H

L

Hi-Z

Data Out

Data In

Hi-Z

Write

Note 3

L

H

L

×

L

Data In

(Mobile specified RAM)

H

L

H

Hi-Z

Data In

Caution Other operations except for indicated in this table are inhibited.

Notes 1. When /OE = V^IL, V^ILcan be applied to /WE. When /OE = V^IH, a write operation is started.

2. Mobile specified RAM should be Standby.

3. Flash Memory should be Standby or Hardware reset.

Remarks 1. H : V^IH, L : V^IL, × : V^IHor V^IL

2. Sector group protection and read the product ID are using a command.

3. MODE pin must be fixed to H during active operation.

4. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for the

flash memory bus operations.

Data Sheet M15411EJ4V0DS

5

MC-242444

Sector Organization / Sector Address Table (Flash Memory)

Flash Memory top boot

(1/2)

Bank

Sector

Organization

K bytes / K words

Address

Sectors

Address

Sector Address Table

Bank Address Table

A20 A19 A18 A17 A16 A15 A14 A13 A12

BYTE mode WORD mode

Bank 1

8/4

3FFFFFH

3FE000H

3FDFFFH

3FC000H

3FBFFFH

3FA000H

3F9FFFH

3F8000H

3F7FFFH

3F6000H

3F5FFFH

3F4000H

3F3FFFH

3F2000H

3F1FFFH

3F0000H

3EFFFFH

3E0000H

3DFFFFH

3D0000H

3CFFFFH

3C0000H

3BFFFFH

3B0000H

3AFFFFH

3A0000H

39FFFFH

390000H

38FFFFH

380000H

37FFFFH

370000H

36FFFFH

360000H

35FFFFH

350000H

34FFFFH

340000H

33FFFFH

330000H

32FFFFH

320000H

31FFFFH

310000H

30FFFFH

300000H

2FFFFFH

2F0000H

2EFFFFH

2E0000H

2DFFFFH

2D0000H

2CFFFFH

2C0000H

2BFFFFH

2B0000H

2AFFFFH

2A0000H

29FFFFH

290000H

28FFFFH

280000H

27FFFFH

270000H

1FFFFFH

1FF000H

1FEFFFH

1FE000H

1FDFFFH

1FD000H

1FCFFFH

1FC000H

1FBFFFH

1FB000H

1FAFFFH

1FA000H

1F9FFFH

1F9000H

1F8FFFH

1F8000H

1F7FFFH

1F0000H

1EFFFFH

1E8000H

1E7FFFH

1E0000H

1DFFFFH

1D8000H

1D7FFFH

1D0000H

1CFFFFH

1C8000H

1C7FFFH

1C0000H

1BFFFFH

1B8000H

1B7FFFH

1B0000H

1AFFFFH

1A8000H

1A7FFFH

1A0000H

19FFFFH

198000H

197FFFH

190000H

18FFFFH

188000H

187FFFH

180000H

17FFFFH

178000H

177FFFH

170000H

16FFFFH

168000H

167FFFH

160000H

15FFFFH

158000H

157FFFH

150000H

14FFFFH

148000H

147FFFH

140000H

13FFFFH

138000H

FSA70

FSA69

FSA68

FSA67

FSA66

FSA65

FSA64

FSA63

FSA62

FSA61

FSA60

FSA59

FSA58

FSA57

FSA56

FSA55

FSA54

FSA53

FSA52

FSA51

FSA50

FSA49

FSA48

FSA47

FSA46

FSA45

FSA44

FSA43

FSA42

FSA41

FSA40

FSA39

FSA38

FSA37

FSA36

FSA35

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

x

1

0

1

0

x

1

0

1

0

1

0

1

0

x

8/4

64/32

26FFFFH

260000H

25FFFFH

250000H

24FFFFH

240000H

23FFFFH

230000H

137FFFH

130000H

12FFFFH

128000H

127FFFH

120000H

11FFFFH

118000H

Data Sheet M15411EJ4V0DS

6

MC-242444

(2/2)

Bank

Sector

Organization

K bytes / K words

Address

Sectors

Address

Sector Address Table

Bank Address Table

A20 A19 A18 A17 A16 A15 A14 A13 A12

BYTE mode WORD mode

Bank 1

64/32

22FFFFH

220000H

21FFFFH

210000H

20FFFFH

200000H

1FFFFFH

1F0000H

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

117FFFH

110000H

10FFFFH

108000H

107FFFH

100000H

0FFFFFH

0F8000H

0F7FFFH

0F0000H

0EFFFFH

0E8000H

0E7FFFH

0E0000H

0DFFFFH

0D8000H

0D7FFFH

0D0000H

0CFFFFH

0C8000H

0C7FFFH

0C0000H

0BFFFFH

0B8000H

0B7FFFH

0B0000H

0AFFFFH

0A8000H

0A7FFFH

0A0000H

09FFFFH

098000H

097FFFH

090000H

08FFFFH

088000H

087FFFH

080000H

07FFFFH

078000H

077FFFH

070000H

06FFFFH

068000H

067FFFH

060000H

05FFFFH

058000H

057FFFH

050000H

04FFFFH

048000H

047FFFH

040000H

03FFFFH

038000H

037FFFH

030000H

02FFFFH

028000H

027FFFH

020000H

01FFFFH

018000H

FSA34

FSA33

FSA32

FSA31

FSA30

FSA29

FSA28

FSA27

FSA26

FSA25

FSA24

FSA23

FSA22

FSA21

FSA20

FSA19

FSA18

FSA17

FSA16

FSA15

FSA14

FSA13

FSA12

FSA11

FSA10

FSA9

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

x

Bank 2

FSA8

FSA7

FSA6

FSA5

FSA4

FSA3

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

017FFFH

010000H

00FFFFH

008000H

007FFFH

000000H

FSA2

FSA1

64/32

FSA0

0

x

Data Sheet M15411EJ4V0DS

7

MC-242444

Sector Group Address Table (Flash Memory)

Sector group

SGA0

A20

0

A19

0

A18

0

A17

0

A16

0

1

×

0

1

A15

0

1

0

1

×

0

1

0

1

A14

×

A13

×

A12

×

Size

Sector

FSA0

64 KB (1 Sector)

192 KB (3 Sectors)

SGA1

0

×

FSA1–FSA3

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

×

256 KB (4 Sectors)

192 KB (3 Sectors)

FSA4–FSA7

FSA8–FSA11

FSA12–FSA15

FSA16–FSA19

FSA20–FSA23

FSA24–FSA27

FSA28–FSA31

FSA32–FSA35

FSA36–FSA39

FSA40–FSA43

FSA44–FSA47

FSA48–FSA51

FSA52–FSA55

FSA56–FSA59

FSA60–FSA62

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 KB (1 Sector)

FSA63

FSA64

FSA65

FSA66

FSA67

FSA68

FSA69

FSA70

Remark × : V^IHor V^IL

Data Sheet M15411EJ4V0DS

8

MC-242444

Command Sequence (Flash Memory)

Command sequence

Bus

1st bus Cycle

2nd bus Cycle

3rd bus Cycle

4th bus Cycle

5th bus Cycle

6th bus Cycle

Cycle Address Data Address Data Address Data Address Data Address Data Address Data

Read / Reset ^Note1

1

3

×××H

AAAH

555H

AAAH

555H

BA

F0H

AAH

RA

555H

2AAH

555H

2AAH

–

RD

–

Read / Reset ^Note1

BYTE mode

WORD mode

BYTE mode

WORD mode

55H

AAAH

555H

AAAH

555H

–

F0H

RA

RD

Program

4

AAH

55H

A0H

PA

PD

–

Program Suspend ^{Note 2}

Program Resume ^{Note 3}

Chip Erase

1

6

B0H

30H

AAH

–

BA

–

BYTE mode

WORD mode

BYTE mode

WORD mode

AAAH

555H

AAAH

555H

BA

555H

2AAH

555H

2AAH

–

55H

AAAH

555H

AAAH

555H

–

80H

AAAH

555H

AAAH

555H

–

AAH

555H

2AAH

555H

2AAH

–

55H

AAAH

555H

FSA

10H

Sector Erase

6

AAH

55H

80H

AAH

55H

30H

Sector Erase Suspend ^{Note 4}

1

3

B0H

30H

AAH

–

Sector Erase Resume ^{Note 5}

Unlock Bypass Set BYTE mode

WORD mode

BA

–

AAAH

555H

×××H

BA

555H

2AAH

PA

55H

AAAH

555H

–

20H

–

Unlock Bypass Program ^{Note 6}

Unlock Bypass Reset ^{Note 6}

2

3

A0H

90H

AAH

PD

–

×××H 00H^Note11

–

Product ID

BYTE mode

AAAH

555H

55H

(BA)

AAAH

(BA)

555H

SPA

SUA

–

90H

IA

ID

WORD mode

555H

2AAH

Sector Group Protection ^{Note 7}

Sector Group Unprotect ^{Note 8}

4

1

×××H

AAH

60H

98H

SPA

SUA

–

60H

–

40H

–

SPA

SUA

–

SD

–

Query ^{Note 9}

BYTE mode

WORD mode

Extra One Time Protect BYTE mode

Sector Entry WORD mode

Extra One Time Protect BYTE mode

Sector Program ^{Note 10}

WORD mode

Extra One Time Protect BYTE mode

Sector Erase ^{Note 10}

WORD mode

Extra One Time Protect BYTE mode

Sector Reset ^{Note 10}

WORD mode

55H

3

4

6

4

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

×××H

AAH

60H

555H

2AAH

555H

55H

60H

AAAH

555H

88H

A0H

80H

90H

40H

–

AAAH

555H

PA

PD

–

2AAH

555H

AAAH

555H

AAAH

555H

xxxH

AAH

00H

SD

555H

2AAH

–

55H

–

30H

–

EOTPSA

2AAH

555H

AAAH

555H

–

2AAH

EOTPSA

Extra One Time Protect Sector

Protection ^{Note 10}

–

EOTPSA

Data Sheet M15411EJ4V0DS

9

MC-242444

Notes 1. Both these read / reset commands reset the device to the read mode.

2. Programming is suspended if B0H is input to the bank address being programmed to in a program

operation.

3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend

operation.

4. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.

5. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend

operation.

6. Valid only in the unlock bypass mode.

7. Valid only when /RESET = V^ID(except in the Extra One Time Protect Sector mode).

8. The command sequence that protects a sector group is excluded.

9. Only A0 to A6 are valid as an address.

10. Valid only in the Extra One Time Protect Sector mode.

11. This command can be used even if this data is F0H.

Remarks 1. Specify address 555H (A10 to A0) in the WORD mode, and AAAH (A10 to A0, A-1) in the BYTE mode.

2. RA : Read address

RD : Read data

IA : Address input

xx00H (to read the manufacturer code)

xx02H (to read the device code in the BYTE mode)

xx01H (to read the device code in the WORD mode)

ID : Code output. Refer to the Product ID code (Manufacturer code / Device code) (Flash

Memory).

PA : Program address

PD : Program data

FSA: Erase sector address. The sector to be erased is selected by the combination of this address.

Refer to the Sector Organization / Sector Address Table (Flash Memory).

BA : Bank address. Refer to the Sector Organization / Sector Address Table (Flash Memory).

SPA : Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) =

(V^IL, V^IH, V^IL). For the sector group address, refer to the Sector Group Address Table (Flash

Memory).

SUA : Unprotect sector group address. Set sector group address (SGA) and (A6, A1, A0) = (V^IH, V^IH,

V^IL). For the sector group address, refer to the Sector Group Address Table (Flash Memory).

SD : Data for verifying whether sector groups read from the address specified by SPA, SUA, and

EOTPSA are protected.

EOTPSA : Extra One Time Protect Sector area addresses.

BYTE mode : 3F0000H to 3FFFFFH, WORD mode : 1F8000H to 1FFFFFH

3. The sector group address is don't care except when a program / erase address or read address are

selected.

4. For the operation of the bus, refer to Bus Operations Table.

5. × of address bit indicates V^IHor V^IL.

6. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for the

flash memory commands.

Data Sheet M15411EJ4V0DS

10

MC-242444

Product ID Code (Manufacturer Code / Device Code) (Flash Memory)

Product ID Code

Address inputs

Output

Hex

A6

L

A1

L

A0

L

Manufacturer Code

Device code

10H

L

H

5CH (BYTE mode),

225CH (WORD mode)

Product ID Code

Code outputs

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Hex

15 14 13 12 11 10

9

0

x

1

8

0

x

0

7

0

6

0

1

5

0

4

1

3

0

1

2

0

1

0

Manufacturer Code

Device code BYTE mode

WORD mode

0

A-1

0

x

0

x

1

0

x

0

x

0

x

0

10H

5CH

225CH

Remark H : V^IH, L : V^IL, x : Hi-Z

Hardware Sequence Flags, Hardware Data Protection (Flash Memory)

Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E).

Data Sheet M15411EJ4V0DS

11

MC-242444

Initialization (Mobile specified RAM)

The MC-242444 is initialized in the power-on sequence according to the following.

(1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any

signal toggling.

(2) After the wait time, read operation must be performed at least 8 times. After that, it can be normal operation.

Figure 1. Initialization Timing Chart

VCCm (MIN.)

VCCm

Address (Input)

V

IH (MIN.)

MODE (Input)

/CEm (Input)

t

RC

t

CP

Power On Wait Time

200

Read Operation 8 times

Normal

Operation

µ

s

Cautions 1. Following power application, make MODE and /CEm high level during the wait time interval.

2. Following power application, make MODE high level during the wait time and eight read

operations.

3. The read operation must satisfy the specs described on page 21 (Read Cycle (Mobile specified

RAM)).

4. The address is don’t care (V^IHor V^IL) during read operation.

5. Read operation must be executed with toggled the /CEm pin.

6. To prevent bus contention, it is recommended to set /OE to high level. However, do not input

data to the I/O pins if /OE is low level during a read operation.

Data Sheet M15411EJ4V0DS

12

MC-242444

Standby Mode (Flash Memory)

Standby Mode 1 and Standby Mode 2 differ as shown below.

Table 1. Standby Mode Characteristics

Memory Cell Data Hold Standby Supply Current (µA)

Standby Mode

Mode 1

Valid

100 (I^SB1)

10 (I^SB2)

Mode 2

Invalid

Standby Mode State Machine (Flash Memory)

(1) From Active

To shift from this state to Standby Mode 1, change /CEm from V^ILto V^IH.

To shift from this state to Standby Mode 2, change /CEm from V^ILto V^IHand change MODE from V^IHto V^IL.

(2) From Standby Mode 1

To shift from this state to Active, change /CEm from V^IHto V^IL.

To shift from this state to Standby Mode 2, change MODE from V^IHto V^IL.

(3) From Standby Mode 2

When shifting from this state to the Active state or to Standby Mode 1, it is necessary to set MODE to V^IHand

perform a Dummy Read operation 8 times after waiting for 200 µs, in the same way as at power application.

Refer to Figure 35. Standby Mode 2 entry and recovery Timing Chart (Mobile specified RAM).

After shifting to Active state, change /CEm to V^IL.

After shifting to Standby Mode 1, do not change either MODE or /CEm.

Figure 2. Standby Mode State Machine

Power On

/CEm = VIH

,

MODE = V^IH

Wait 200

µ

s,

Dummy Read (8 times)

Initial State

/CEm = VIL

/CEm = VIH

MODE = VIH

,

MODE = VIH

Active

/CEm = VIH

,

/CEm = VIH

,

MODE = V^IH

MODE = V^IL

/CEm = VIL

,

MODE = V^IH

/CEm = VIH, MODE = VIL

Standby Mode 1

Standby Mode 2

Data Sheet M15411EJ4V0DS

13

MC-242444

Electrical Specifications

Before turning on power, input V^SS± 0.2 V to the /RESET pin until V^CCf ≥ V^CCf (MIN.).

Absolute Maximum Ratings

Parameter

Supply voltage

Symbol

V^CCf

Condition

Rating

Unit

V

with respect to V^SS

–0.5 to +4.0

V^CCm with respect to V^SS

–0.5 to +4.0

Input / Output voltage

V^T

with respect /WP(ACC), /RESET

–0.5 ^{Note 1}to +13.0

V

except /WP(ACC), /RESET –0.5^{Note 1}to V^CCf, V^CCm + 0.4 (4.0 V MAX.)^{Note 2}

to V^SS

Ambient operation temperature

Storage temperature

T^A

–20 to +70

°C

T^stg

–55 to +125

Notes 1. –1.0 V (MIN.) (pulse width ≤ 20 ns)

2. V^CCf, V^CCm + 0.5 V (MAX.) (pulse width ≤ 20 ns)

Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Common

Parameter

Supply voltage

Symbol

V^CCf, V^CCm

T^A

Condition

MIN.

2.6

TYP.

MAX.

3.0

Unit

V

Ambient operation temperature

–20

+70

°C

Flash Memory

Parameter

High level input voltage

Low level input voltage

Symbol

V^IH

MIN.

2.4

MAX.

V^CCf + 0.3

+0.5

Unit

V

V^IL

−0.3

V

Mobile specified RAM

Parameter

High level input voltage

Low level input voltage

Symbol

V^IH

MIN.

MAX.

Unit

V

V^CCm x 0.8

−0.3 ^Note

V^CCm + 0.3

V^CCm x 0.2

V^IL

V

Note –0.5 V (MIN.) (Pulse width: 30 ns)

Data Sheet M15411EJ4V0DS

14

MC-242444

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

Common

Parameter

Input leakage current

Output leakage current

Symbol

I^LI

Test condition

MIN.

−1.0

TYP.

MAX.

+1.0

Unit

µA

I^LO

µA

Flash Memory

Parameter

High level output voltage

Low level output voltage

Symbol

V^OH

Test condition

MIN.

TYP.

MAX.

Unit

V

I^OH= −500 µA, V^CCf = V^CCf (MIN.)

I^OL= +1.0 mA, V^CCf = V^CCf (MIN.)

V^CCf−0.3

V^OL

0.3

16

4

V

Power

supply

current

Read

BYTE mode

I^CC1f

V^CCf = V^CCf (MAX.),

/CEf = V^IL, /OE = V^IH

t^CYCLE= 5 MHz

10

2

mA

t^CYCLE= 1 MHz

t^CYCLE= 5 MHz

t^CYCLE= 1 MHz

WORD mode

10

2

16

4

Program, Erase

Standby

I^CC2f

I^CC3f

V^CCf = V^CCf (MAX.), /CEf = V^IL, /OE = V^IH

V^CCf = V^CCf (MAX.), /CEf = /RESET =

/WP(ACC) = V^CCf ± 0.3 V, /OE = V^IL

V^CCf = V^CCf (MAX.), /RESET = V^SS± 0.2 V

V^IH= V^CCf ± 0.2 V, V^IL= V^SS± 0.2 V

/CEf = V^IL, /OE = V^IH,

15

0.2

30

5

mA

µA

Standby / Reset

Automatic sleep mode

Read during programming

Read during erasing

Programming

I^CC4f

I^CC5f

I^CC6f

I^CC7f

I^CC8f

0.2

21

5

µA

5

45

35

mA

21

17

during suspend

Automatic programming during suspend

/WP (ACC) pin

Accelerated

I^ACC

5

10

30

mA

programming

V^CCf

15

/RESET high level input voltage

Accelerated programming voltage

Low V^CCf lock-out voltage ^Note

V^ID

High Voltage is applied

11.5

8.5

12.5

9.5

1.7

V

V^ACC

V^LKO

High Voltage is applied

Note When V^CCf is equal to or lower than V^LKO, the device ignores all write cycles. Refer to DUAL OPERATION

FLASH MEMORY 32M BITS A SERIES Information (M14914E).

Mobile specified RAM

Parameter

Symbol

V^OH

Test condition

MIN.

TYP.

MAX.

Unit

V

High level output voltage

Low level output voltage

Operating supply current

Standby supply Standby Mode 1

I^OH= –0.5 mA

I^OL= 1 mA

V^CCm × 0.8

V^OL

V^CCm × 0.2

V

I^CCA

/CEm = V^IL, Minimum cycle time, I^I/O= 0 mA

/CEm ≥ V^CCm − 0.2 V, MODE ≥ V^CCm − 0.2 V

/CEm ≥ V^CCm − 0.2 V, MODE ≤ 0.2 V

35

100

10

mA

µA

I^SB1

current

Standby Mode 2

I^SB2

Data Sheet M15411EJ4V0DS

15

MC-242444

AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

AC Test Conditions

Flash Memory

Input Waveform (Rise and Fall Time ≤ 5 ns)

3.0 V

1.5 V

Test Points

1.5 V

V

SS

Output Waveform

1.5 V

Test Points

1.5 V

Output Load

1 TTL + 30 pF

Data Sheet M15411EJ4V0DS

16

MC-242444

Mobile specified RAM

Input Waveform (Rise and Fall Time ≤ 5 ns)

V m

CCm x 0.8 V

CC

V

VCCm/2 V

Test points

VCCm/2 V

V

CCm x 0.2 V

V

SS

5 ns

Output Waveform

V

CCm/2 V

Test points

VCCm/2 V

Output Load

AC characteristics directed with the note should be measured with the output load shown in Figure.

C^L: 50 pF

5 pF (t^CLZ, t^OLZ, t^BLZ, t^CHZ, t^OHZ, t^BHZ, t^WHZ, t^OW)

ZO = 50 Ω

I/O (Output)

CL

50 Ω

V

CCm/2 V

Data Sheet M15411EJ4V0DS

17

MC-242444

/CEf, /CEm Timing

Parameter

Symbol

t^CCR

Test Condition

MIN.

0

TYP.

MAX.

Unit

ns

Note

/CEf, /CEm recover time

Read Cycle (Flash Memory)

Parameter

Symbol

t^RC

MIN.

90

Unit

ns

Read cycle time

V^CCf ≥ 2.7 V

85

Address access time

/CEf access time

t^ACC

/CEf = /OE = V^IL

90

85

90

85

40

30

ns

t^CEf

/OE = V^IL

/OE access time

t^OE

t^DF

/CEf = V^IL

ns

µs

ns

Output disable time

/OE = V^ILor /CEf = V^IL

Output hold time

t^OH

0

/RESET pulse width

t^RP

500

50

/RESET hold time before read

/RESET low to read mode

/CEf low to CIOf low, high

CIOf low output disable time

CIOf high access time

t^RH

t^READY

t^ELFL/t^ELFH

t^FLQZ

t^FHQV

20

5

30

90

85

V^CCf ≥ 2.7 V

Remark

t

DF is the time from inactivation of /CEf or /OE to Hi-Z state output.

Data Sheet M15411EJ4V0DS

18

MC-242444

Write Cycle (Erase / Program) (Flash Memory)

Parameter

Write cycle time

Symbol

t^WC

MIN.

90

85

0

TYP.

MAX.

Unit

ns

Note

V^CCf ≥ 2.7 V

Address setup time (/WE to address)

Address setup time (/CEf to address)

Address hold time (/WE to address)

Address hold time (/CEf to address)

Input data setup time

t^AS

ns

0

t^AH

t^DS

t^DH

t^OEH

45

35

0

Input data hold time

/OE hold time

Read

0

Toggle bit, Data polling

10

0

Read recovery time before write (/OE to /CEf)

Read recovery time before write (/OE to /WE)

/WE setup time (/CEf to /WE)

/CEf setup time (/WE to /CEf)

/WE hold time (/CEf to /WE)

/CEf hold time (/WE to /CEf)

Write pulse width

t^GHEL

t^GHWL

t^WS

ns

µs

s

0

t^CS

0

t^WH

0

t^CH

0

t^WP

35

30

/CEf pulse width

t^CP

Write pulse width high

t^WPH

t^CPH

t^BPG

t^WPG

t^SER

t^VCS

t^RB

/CEf pulse width high

Byte programming operation time

Word programming operation time

Sector erase operation time

V^CCf setup time

9

200

5

11

0.7

1

50

0

µs

ns

µs

RY (/BY) recovery time

/RESET pulse width

t^RP

500

20

/RESET high-voltage (V^ID) hold time from high of RY(/BY)

when sector group is temporarily unprotect

/RESET hold time

t^RRB

t^RH

50

ns

From completion of automatic

t^EOE

90

85

90

program / erase to data output time

V^CCf ≥ 2.7 V

RY (/BY) delay time from valid program or erase operation

Address setup time to /OE low in toggle bit

Address hold time to /CEf or /OE high in toggle bit

/CEf pulse width high for toggle bit

/OE pulse width high for toggle bit

Voltage transition time

t^BUSY

t^ASO

ns

µs

ns

µs

15

0

t^AHT

t^CEPH

t^OEPH

t^VLHT

t^VIDR

t^VACCR

t^TOW

t^SPD

20

4

2

3

2

4

Rise time to V^ID(/RESET)

500

50

Rise time to V^ACC(/WP(ACC))

Erase timeout time

Erase suspend transition time

20

Notes 1. The preprogramming time prior to the erase operation is not included.

2. Sector group protection and accelerated mode only

3. Sector group protection only.

4. Table only.

Data Sheet M15411EJ4V0DS

19

MC-242444

Write operation (Erase / Program) Performance (Flash Memory)

Parameter

Sector erase time

Description

Excludes programming time prior to erasure

Excludes system-level overhead

Excludes system-level overhead BYTE mode

WORD mode

MIN.

TYP.

0.7

50

9

MAX.

5

Unit

s

Chip erase time

s

Byte programming time

Word programming time

Chip programming time

200

µs

s

11

40

25

7

Accelerated programming time

Erase / Program cycle

Excludes system-level overhead

150

µs

100,000

cycles

Data Sheet M15411EJ4V0DS

20

MC-242444

Read Cycle (Mobile specified RAM)

Parameter Symbol

MC-242444-B90

MC-242444-B95

MC-242444-B10

Unit

Note

MIN.

80

MAX.

10,000

10

MIN.

90

MAX.

10,000

15

MIN.

110

MAX.

10,000

20

Read cycle time

t^RC

t^RC1

t^SKEW

t^CP

ns

1

2

3

Identical address read cycle time

Address skew time

80

90

/CEm pulse width

10

Address access time

t^AA

80

35

90

40

100

50

4

5

/CEm access time

t^ACS

t^OE

/OE to output valid

/LB, /UB to output valid

t^BA

50

Output hold from address change

/CEm to output in low impedance

/OE to output in low impedance

/LB, /UB to output in low impedance

/CEm to output in high impedance

/OE to output in high impedance

/LB, /UB to output in high impedance

t^OH

10

5

10

5

10

5

t^CLZ

t^OLZ

t^BLZ

t^CHZ

t^OHZ

t^BHZ

5

25

Notes 1. One read cycle (t^RC) must satisfy the minimum value (t^RC(MIN.)) and maximum value (t^RC(MAX.)= 10 µs). t^RC

indicates the time from the /CEm low level input point or address determination point, whichever is later, to

the /CEm high level input point or the next address change start point, whichever is earlier. As a result,

there are the following four conditions for t^RC.

1) Time from address determination point to /CEm high level input point

2) Time from address determination point to next address change start point

3) Time from /CEm low level input point to next address change start point

4) Time from /CEm low level input point to /CEm high level input point

(address access)

(/CEm access)

2. The identical address read cycle time (t^RC1) is the cycle time of one read operation when performing

continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CEm low level. Perform

settings so that the sum (t^RC) of the identical address read cycle times (t^RC1) is 10 µs or less.

3. t^SKEWindicates the following three types of time depending on the condition.

1) When switching /CEm from high level to low level, t^SKEWis the time from the /CEm low level input point

until the next address is determined.

2) When switching /CEm from low level to high level, t^SKEWis the time from the address change start point to

the /CEm high level input point.

3) When /CEm is fixed to low level, t^SKEWis the time from the address change start point until the next

address is determined.

Since specs are defined for t^SKEWonly when /CEm is active, t^SKEWis not subject to limitations when /CEm is

switched from high level to low level following address determination, or when the address is changed after

/CEm is switched from low level to high level.

4. Regarding t^AAand t^ACS, only t^AAis satisfied during address access (refer to 1) and 2) of Note 1), and only

t^ACSis satisfied during /CEm access (refer to 3) of Note 1).

5. Regarding t^BAand t^OE, only t^BAis satisfied if /OE becomes active later than /UB and /LB, and only t^OEis

satisfied if /UB and /LB become active before /OE.

Data Sheet M15411EJ4V0DS

21

MC-242444

Write Cycle (Mobile specified RAM)

Parameter Symbol

MC-242444-B90

MC-242444-B95

MC-242444-B10

Unit

Note

MIN.

80

MAX.

10,000

10

MIN.

90

MAX.

10,000

15

MIN.

110

MAX.

10,000

20

Write cycle time

t^WC

t^WC1

t^SKEW

t^CW

ns

1

2

3

4

Identical address write cycle time

Address skew time

80

90

/CEm to end of write

40

30

35

30

20

10

0

50

35

45

35

20

10

0

60

40

55

40

20

10

0

/LB, /UB to end of write

Address valid to end of write

Write pulse width

t^BW

t^AW

t^WP

Write recovery time

t^WR

t^CP

5

/CEm pulse width

Address setup time

t^AS

Byte write hold time

t^BWH

t^DW

20

0

20

25

0

20

30

0

Data valid to end of write

Data hold time

t^DH

/OE to output in low impedance

/WE to output in high impedance

/OE to output in high impedance

Output active from end of write

t^OLZ

t^WHZ

t^OHZ

t^OW

5

25

5

Notes 1. One write cycle (t^WC) must satisfy the minimum value (t^WC(MIN.)) and the maximum value (t^WC(MAX.)= 10 µs).

t^WCindicates the time from the /CEm low level input point or address determination point, whichever is after,

to the /CEm high level input point or the next address change start point, whichever is earlier. As a result,

there are the following four conditions for t^WC.

1) Time from address determination point to /CEm high level input point

2) Time from address determination point to next address change start point

3) Time from /CEm low level input point to next address change start point

4) Time from /CEm low level input point to /CEm high level input point

2. The identical address read cycle time (t^WC1) is the cycle time of one write cycle when performing continuous

write operations with the address fixed and /CEm low level, changing /LB and /UB at the same time, and

toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that

the sum (t^WC) of the identical address write cycle times (t^WC1) is 10 µs or less.

3. t^SKEWindicates the following three types of time depending on the condition.

1) When switching /CEm from high level to low level, t^SKEWis the time from the /CEm low level input point until

the next address is determined.

2) When switching /CEm from low level to high level, t^SKEWis the time from the address change start point to

the /CEm high level input point.

3) When /CEm is fixed to low level, t^SKEWis the time from the address change start point until the next

address is determined.

Since specs are defined for t^SKEWonly when /CEm is active, t^SKEWis not subject to limitations when /CEm is

switched from high level to low level following address determination, or when the address is changed after

/CEm is switched from low level to high level.

Data Sheet M15411EJ4V0DS

22

MC-242444

4. Definition of write start and write end

/CEm

/WE

L

/LB, /UB

L

Status

Write start pattern 1

Write start pattern 2

Write start pattern 3

Write end pattern 1

Write end pattern 2

H to L

If /WE, /LB, /UB are low level, time when /CEm

changes from high level to low level

L

H to L

L

If /CEm, /LB, /UB are low level, time when /WE

changes from high level to low level

L

L to H

L

H to L

L

If /CEm, /WE are low level, time when /LB or /UB

changes from high level to low level

If /CEm, /WE, /LB, /UB are low level, time when

/WE changes from low level to high level

L to H

When /CEm, /WE, /LB, /UB are low level, time when

/LB or /UB changes from low level to high level

5. Definition of write end recovery time (t^WR)

1) Time from write end to address change start point, or from write end to /CEm high level input point

2) When /CEm, /LB, /UB are low level and continuously written to the identical address, time from /WE high

level input point to /WE low level input point

3) When /CEm, /WE are low level and continuously written to the identical address, time from /LB or /UB

high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier.

4) When /CEm is low level and continuously written to the identical address, time from write end to point at

which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest.

Read Write Cycle (Mobile specified RAM)

Parameter

Symbol

MC-242444-B90

MC-242444-B95

MC-242444-B10

Unit

Note

1, 2

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read write cycle time

Byte write setup time

Byte read setup time

t^RWC

t^BWS

t^BRS

10,000

ns

20

Notes 1. Make settings so that the sum (t^RWC) of the identical address read cycle time (t^RC1) and the identical

address write cycle time (t^WC1) is 10 µs or less when a write is performed at the identical address using /UB

following a read using /LB with /CEm low level, or when a write is performed using /LB following a read

using /UB.

2. Make settings so that the sum (t^RWC) of the identical address read cycle time (t^RC1) and the identical

address write cycle time (t^WC1) is 10 µs or less when a read is performed at the identical address using /UB

following a write using /LB with /CEm low level, or when a read is performed using /LB following a write

using /UB.

Data Sheet M15411EJ4V0DS

23

MC-242444

Figure 3. Alternating Mobile specified RAM to Flash Memory Timing Chart

/CEf (Input)

t

CCR

t

CCR

/CEm (Input)

Figure 4. Read Cycle Timing Chart 1 (Flash Memory)

t

RC

Address (Input)

/CEf (Input)

/OE (Input)

t

ACC

t

CEf

t

DF

t

OEH

t

OE

t

OH

/WE (Input)

I/O (Output)

Hi-Z

Data out

Figure 5. Read Cycle Timing Chart 2 (Flash Memory)

t

RC

Address (Input)

/RESET (Input)

/CEf (Input)

t

RP

t

RH

t

ACC

t

READY

t

CEf

t

OH

Hi-Z

I/O (Output)

Data out

Data Sheet M15411EJ4V0DS

24

MC-242444

Figure 6. Sector Group Protection Timing Chart (Flash Memory)

VCCf

t

VCS

V

ID

IH

t

VIDR

VLHT

WC

/RESET (Input)

t

WC

Address (Input)

SGAx

SGAy

A0 (Input)

A1 (Input)

A6 (Input)

/CEf (Input)

/OE (Input)

t

WP

TIMEOUT

/WE (Input)

t

OE

01H^Note

60H

I/O (Input/Output)

60H

40H

Note The sector group protection verification result is output.

01H : The sector group is protected.

00H : The sector group is not protected.

Figure 7. Temporary Sector Group Unprotect Timing Chart (Flash Memory)

VCCf

t

VCS

t

VLHT

t

VIDR

V

ID

IH

/RESET (Input)

t

RRB

(Program or erase command sequence)

/WE (Input)

/CEf (Input)

t

VLHT

t

VLHT

RY (/BY) (Output)

Period during which

protection is canceled

Data Sheet M15411EJ4V0DS

25

MC-242444

Figure 8. Accelerated Mode Timing Chart (Flash Memory)

VCCf

t

VCS

t

VLHT

t

VACCR

V

ACC

IH

V

/WP (ACC) (Input)

(Program or erase command sequence)

/WE (Input)

/CEf (Input)

t

VLHT

t

VLHT

RY (/BY) (Output)

Accelerated mode period

Figure 9. Dual Operation Timing Chart (Flash Memory)

t

RC

t

WC

t

RC

t

WC

t

RC

t

WC

Address (Input)

/CEf (Input)

BA1

BA2

BA1

BA2

BA1

BA2

t

AH

t

AS

t

ACC

t

AS

t

AHT

t

CEPH

t

CEf

/OE (Input)

/WE (Input)

t

GHWL

t

WP

t

OEH

t

OE

t

DF

t

DF

t

DS

t

DH

I/O (Input / Output)

Output

Input

Output

Input

Output

Status

Data Sheet M15411EJ4V0DS

26

MC-242444

Figure 10. Write Cycle Timing Chart (/WE Controlled) (Flash Memory)

(3rd and 4th write cycle)

(Data polling)

t

WC

t

AS

Address (Input)

/CEf (Input)

555H

PA

t

AH

t

RC

t

CH

t

CEf

t

GHWL

/OE (Input)

/WE (Input)

t

BPG or tWPG

t

WP

t

WPH

t

CS

t

OE

t

DH

I/O (Input / Output)

A0H

PD

/I/O7

D

OUT

DOUT

t

DS

t

OH

Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write

cycles, and data polling.

2. This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input

are different from the WORD mode. See Command Sequence (Flash Memory).

3. PA : Program address

PD : Program data

/I/O7 : The output of the complement of the data written to the device.

D^OUT: The output of the data written to the device.

Figure 11. Write Cycle Timing Chart (/CEf Controlled) (Flash Memory)

(3rd and 4th write cycle)

(Data polling)

t

WC

t

AS

Address (Input)

/CEf (Input)

555H

PA

t

AH

t

RC

t

CP

t

CPH

t

CEf

t

GHEL

/OE (Input)

/WE (Input)

t

BPG or tWPG

t

WH

t

WS

t

DS

DH

t

OE

t

I/O (Input / Output)

A0H

PD

/I/O7

D

OUT

DOUT

t

OH

Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write

cycles, and data polling.

2. This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input

are different from the WORD mode. See Command Sequence (Flash Memory).

3. PA : Program address

PD : Program data

/I/O7 : The output of the complement of the data written to the device.

D^OUT: The output of the data written to the device.

Data Sheet M15411EJ4V0DS

27

MC-242444

Figure 12. Sector / Chip Erase Timing Chart (Flash Memory)

t

WC

t

AS

FSA^Note

Address (Input)

/CEf (Input)

555H

2AAH

555H

2AAH

t

AH

t

CS

t

CH

/OE (Input)

/WE (Input)

I/O (Input)

t

WP

t

GHWL

t

WPH

t

DS

(10H for chip erase)

30H

t

DH

AAH

55H

80H

AAH

55H

t

VCS

VCCf

Note FSA is the sector address to be erased. In the case of chip erase, input 555H (WORD mode), AAAH (BYTE

mode).

Remark This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input are different from

the WORD mode. See Command Sequence (Flash Memory).

Figure 13. Data Polling Timing Chart (Flash Memory)

/CEf (Input)

t

OE

t

CH

t

DF

/OE (Input)

/WE (Input)

t

OEH

t

CEf

t

BPG,

t

WPG,

t

SER

Hi-Z

Note

I/O7 (Output)

/I/O7

D

OUT

Status data

Valid data

I/O0 - I/O6 (Output)

RY (/BY) (Output)

t

BUSY

t

EOE

Note I/O7 = D^OUT: True value of program data (indicates completion of automatic program / erase)

Data Sheet M15411EJ4V0DS

28

MC-242444

Figure 14. Toggle Bit Timing Chart (Flash Memory)

Address (Input)

/CEf (Input)

t

AHT

t

AS

t

AHT

t

ASO

t

CEPH

/WE (Input)

/OE (Input)

t

OEH

t

OEPH

t

OEH

t

DH

t

OE

t

CEf

Valid

data out

Stop

toggling^Note

I/O6, I/O2 (Input / Output)

RY (/BY) (Output)

Input data

Toggle

t

BUSY

Note I/O6 stops the toggle (indicates automatic program / erase completion).

Figure 15. I/O2 vs. I/O6 Timing Chart (Flash Memory)

Erase

suspended

Erase suspended input

of program command

Input of automatic

erase command

Erasure resumed

Erase suspended

read

Completion of

erasure

/WE (Input)

Erasure

read

Erase suspended input

of program command

I/O6 (Output)

I/O2 (Output)

Toggle

I/O2 and I/O6 (/CEf or /OE is used for toggle)

Figure 16. RY (/BY) (Ready / Busy) Timing Chart (Flash Memory)

/CEf (Input)

Rising edge of the last write pulse

Automatic program or erase

/WE (Input)

RY (/BY) (Output)

t

BUSY

Figure 17. /RESET and RY (/BY) Timing Chart (Flash Memory)

/WE (Input)

/RESET (Input)

t

RB

t

RP

RY (/BY) (Output)

t

READY

Data Sheet M15411EJ4V0DS

29

MC-242444

Figure 18. Write CIOf Timing Chart (Flash Memory)

Falling edge of last write pulse

/CEf, /WE (Input)

CIOf (Input)

Input determined

t

AH

t

AS

Figure 19. BYTE mode Switching Timing Chart (Flash Memory)

/CEf (Input)

CIOf (Input)

I/O0 - I/O14 (Output)

t

ELFL

Hi-Z

Data Output

I/O0-I/O14

Data Output

I/O0-I/O7

t

ACC

Data Output

I/O15

Address Input

I/O15 (Output), A−1 (Input)

A−1

t

FLQZ

Figure 20. WORD mode Switching Timing Chart (Flash Memory)

/CEf (Input)

CIOf (Input)

t

CEf

t

ELFH

Hi-Z

Data Output

I/O0-I/O7

Data Output

I/O0-I/O14

I/O0 - I/O14 (Output)

I/O15 (Output), A−1 (Input)

Hi-Z

Address Input

A−1

Data Output

I/O15

t

FHQV

Data Sheet M15411EJ4V0DS

30

MC-242444

Figure 21. Read Cycle Timing Chart 1 (Mobile specified RAM)

t

SKEW

t

SKEW

Address (Input)

/CEm (Input)

t

CP

t

RC

t

CP

t

ACS

t

CHZ

t

CLZ

/OE (Input)

t

OE

t

OHZ

t

OLZ

/LB, /UB (Input)

t

BA

t

BHZ

OH

t

BLZ

t

Hi-Z

I/O (Output)

Data out

t

SKEW

t

SKEW

t

RC

Address (Input)

/CEm (Input)

t

CP

t

CP

t

AA

t

CHZ

t

CLZ

/OE (Input)

t

OE

t

OHZ

t

OLZ

/LB, /UB (Input)

t

BA

t

BHZ

t

BLZ

Hi-Z

I/O (Output)

Data out

Caution If the address is changed using a value that is either lower than the minimum value or higher than

the maximum value for the read cycle time (t^RC), none of the data can be guaranteed.

Remark In read cycle, /WE should be fixed to High.

Data Sheet M15411EJ4V0DS

31

MC-242444

Figure 24. Read Cycle Timing Chart 4 (Mobile specified RAM)

t

SKEW

t

SKEW

t

RC

Address (Input)

/CEm (Input)

Note

RC1

t

RC1

t

AA

t

OE

t

OE

t

OLZ

t

OLZ

/OE (Input)

t

OHZ

t

OHZ

t

BA

t

BA

t

BLZ

t

BLZ

/LB, /UB (Input)

t

BHZ

t

BHZ

Hi-Z

Data out

I/O (Output)

Caution If the address is changed using a value that is either lower than the minimum value or higher than

the maximum value for the read cycle time (t^RC), none of the data can be guaranteed.

Note To perform a continuous read toggling /OE, /UB, and /LB with /CEm low level at an identical address, make

settings so that the sum (t^RC) of the identical address read cycle times (t^RC1) is 10 µs or less.

Remark In read cycle, /WE should be fixed to High.

Data Sheet M15411EJ4V0DS

34

MC-242444

Figure 25. Write Cycle Timing Chart 1 (Mobile specified RAM)

t

WC

tWC

t

SKEW

tSKEW

Address (Input)

/CEm (Input)

t

AW

t

AW

t

CP

t

WP

t

AS

tWP

t

WR

tWR

/WE (Input)

t

AS

t

BW

t

BW

/LB, /UB (Input)

t

DW

tDH

t

DW

tDH

Hi-Z

I/O (Intput)

Data in

t

SKEW

t

WC

tWC

t

SKEW

tSKEW

Address (Input)

/CEm (Input)

t

CW

t

CW

t

CP

t

WP

tWP

t

WR

tWR

/WE (Input)

t

BW

t

BW

/LB, /UB (Input)

t

DW

tDH

t

DW

tDH

Hi-Z

I/O (Intput)

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

35

MC-242444

Figure 26. Write Cycle Timing Chart 2 (Mobile specified RAM)

t

SKEW

t

WC

t

SKEW

t

WC

t

SKEW

t

WC

t

SKEW

tSKEW

Address (Input)

t

AW

tCP

t

AW

/CEm (Input)

/WE (Input)

t

CW

t

WR

tWR

t

WP

t

WP

t

WP

t

WR

t

AS

t

AW

t

OW

t

WHZ

/OE (Input)

t

OLZ

OHZ

t

DW

t

DH

t

DW

t

DH

t

DW

tDH

Hi-Z

Indefinite

data out

I/O (Intput / Output)

Data in

Hi-Z

t

SKEW

t

SKEW

t

WC

Address (Input)

/CEm (Input)

Note

WC1

t

WC1

t

AS

t

WP

t

WR

t

WP

tWR

/WE (Input)

t

BW

/LB, /UB (Input)

t

DW

t

DH

t

DW

tDH

Hi-Z

I/O (Intput)

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling

/WE is performed, make settings so that the sum (t^WC) of the identical address write cycle time (t^WC1) is 10 µs

or less.

Remarks 1. Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is

executed. Therefore /OE should be at High to make the I/O pins high impedance.

Data Sheet M15411EJ4V0DS

36

MC-242444

Figure 27. Write Cycle Timing Chart 3 (/CEm Controlled) (Mobile specified RAM)

Address (Input)

/CEm (Input)

t

WC

t

WC

t

AS

t

WR

t

WR

t

CW

t

AS

t

CW

/WE (Input)

/LB, /UB (Input)

I/O (Intput)

t

DW

t

DH

t

DW

t

DH

Hi-Z

Data in

Address (Input)

/CEm (Input)

t

WC

t

WC

t

AS

t

WR

t

WR

t

CW

t

AS

t

CW

/WE (Input)

/LB, /UB (Input)

I/O (Intput)

t

DW

t

DH

t

DW

t

DH

Hi-Z

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

37

MC-242444

Figure 28. Write Cycle Timing Chart 4 (/LB, /UB Controlled 1) (Mobile specified RAM)

tWC

t^WC

tSKEW

Address (Input)

/CEm (Input)

tAW

tWP

/WE (Input)

tAS

tBW

tAS

tBW

tWR

tDH

/LB, /UB (Input)

tDW

tDH

Hi-Z

I/O (Intput)

Data in

tSKEW

t^WC

tWC

tSKEW

Address (Input)

/CEm (Input)

tAW

tCW

tWP

/WE (Input)

tAS

tBW

tAS

tBW

tWR

tDH

/LB, /UB (Input)

tDW

tDH

Hi-Z

I/O (Intput)

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

38

MC-242444

Figure 29. Write Cycle Timing Chart 5 (/LB, /UB Controlled 2) (Mobile specified RAM)

t

SKEW

t

SKEW

t

WC

Address (Input)

Note

WC1

Note

WC1

t

/CEm (Input)

/WE (Input)

t

WP

t

AS

t

BW

t

WR

t

BW

t

WR

/LB, /UB (Input)

I/O (Intput)

t

DW

t

DH

t

DW

t

DH

Hi-Z

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling

/WE is performed, make settings so that the sum (t^WC) of the identical address write cycle time (t^WC1) is 10 µs

or less.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

39

MC-242444

Figure 30. Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1) (Mobile specified RAM)

t

WC

Address (Input)

Note

t

WC1

t

WC1

/CEm (Input)

/WE (Input)

/LB (Input)

/UB (Input)

t

CW

WP

t

AS

t

BW

t

WR

t

WR

t

BW

t

DW

t

DH

Hi-Z

Data in

I/O0 - 7 (Intput)

I/O8 - 15 (Intput)

t

DW

t

DH

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling

/WE is performed, make settings so that the sum (t^WC) of the identical address write cycle time (t^WC1) is 10 µs

or less.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

40

MC-242444

Figure 31. Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2) (Mobile specified RAM)

Address (Input)

/CEm (Input)

t

WC

t

CW

t

CW

t

WP

t

WP

/WE (Input)

/LB (Input)

t

BW

t

WR

t

AS

t

BWH

t

WR

t

BW

/UB (Input)

t

AS

t

DW

t

DH

Hi-Z

I/O0 - 7 (Intput)

Data in

t

DW

t

DH

Hi-Z

I/O8 - 15 (Intput)

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the write cycle time (t^WC), none of the data can be guaranteed.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

41

MC-242444

Figure 32. Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1) (Mobile specified RAM)

t

RWC

Address (Input)

Note

t

RC1

t

WC1

t

AA

/CEm (Input)

/WE (Input)

/LB (Input)

/UB (Input)

t

ACS

t

WP

t

BWS

t

WR

t

BW

t

CLZ

t

BLZ

t

BHZ

Hi-Z

I/O0 - 7 (Output)

I/O8 - 15 (Intput)

Data out

t

DW

t

DH

Data in

Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. If the address is changed using a value that is either lower than the minimum value or higher

than the maximum value for the identical address read cycle time (t^RC1) and the identical

address write cycle time (t^WC1), none of the data can be guaranteed.

Note Make settings so that the sum (t^RWC) of the identical address read cycle time (t^RC1) and the identical address

write cycle time (t^WC1) is 10 µs or less when a write is performed at the identical address using /UB following a

read using /LB with /CEm low level, or when a write is performed using /LB following a read using /UB.

Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.

Data Sheet M15411EJ4V0DS

42

MC-242444

Figure 33. Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2) (Mobile specified RAM)

t

RWC

Address (Input)

Note

WC1

Note

t

RC1

t

CW

/CEm (Input)

/WE (Input)

/LB (Input)

/UB (Input)

t

WR

t

WP

t

BW

t

AS

t

BRS

t

DW

t

DH

Hi-Z

I/O0 - 7 (Input)

Data in

t

BA

t

BHZ

t

BLZ

I/O8 - 15 (Output)