MC30280FCHP-U3 [RENESAS]
IC,MICROCONTROLLER,16-BIT,M16C CPU,CMOS,QFP,80PIN,PLASTIC;
| 型号： | MC30280FCHP-U3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,MICROCONTROLLER,16-BIT,M16C CPU,CMOS,QFP,80PIN,PLASTIC |
| 文件： | 总35页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M16C/28 Group (M16C/28, M16C/28B)
REJ03B0201-0050
Rev.0.50
SINGLE-CHIP 16-BIT CMOS MCU
2006.09.15
1. Overview
The M16C/28 Group (M16C/28 and M16C/28B) MCU are single-chip control MCU, fabricated using high-
performance silicon gate CMOS technology with the M16C/60 series CPU core. The M16C/28 Group
(M16C/28 and M16C/28B) are housed in 64-pin and 80-pin plastic molded LQFP packages and also in 85-
pin plastic molded TFLGA (Thin Fine Pitch Land Grid Array) package. With a 1-Mbyte address space, this
MCU combines advanced instruction manipulation capabilities to process complex instructions by less
bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office
automation, communication devices and other high-speed processing applications.
The M16C/28 has Normal-ver., T-ver., and V-ver.. The M16C/28B has Normal-ver. only.
This hardware manual describes the Normal-ver. only. Please contact Renesas Technology Corp. for
T-ver./V-ver. information.
1.1 Applications
Audio, cameras, office equipment, communication equipment, portable equipment, home appliances (in-
verter solution), motor control, industrial equipment, etc.
page 1
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
1.2 Performance Overview
Table 1.1 and 1.2 outline performance overview of the M16C/28 Group (M16C/28, M16C/28B).
Table 1.1 M16C/28 Group (M16C/28, M16C/28) Performance (80/85-Pin Package)
Item
Performance
CPU
Number of basic instructions 91 instructions
Minimum instruction
excution time
41.7 ns (f(BCLK) = 24 MH
50 ns (f(BCLK) = 20 MH
Z
, VCC = 4.2 V to 5.5 V) (M16C/28B)
Z
, VCC = 3.0 V to 5.5 V) (M16C/28, M16C/28B)
100 ns (f(BCLK) = 10 MH
Single chip mode
1M bytes
Z, VCC= 2.7 V to 5.5 V) (M16C/28, M16C/28B)
Operation mode
Address space
Memory capacity
I/O port
See Table 1.3
Peripheral
Function
Input/Output : 71 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
:
16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I2C bus(1), or IEbus(2)
2 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I2C bus(1)
10 bits x 24 channels
2 channels
)
A/D converter
DMAC
Watchdog timer
Interrupt
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
• Main clock (*)
• Sub-clock (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with a built-in feedback resistor
Main clock oscillation stop, re-oscillation detect function
Oscillation Stop Detect
Function
Voltage detection circuit
Power supply voltage
Available
Electrical
VCC = 4.2 V to 5.5 V (f(BCLK) = 24 MH
Z) (M16C/28B)
Characteristics
VCC = 3.0 V to 5.5 V (f(BCLK) = 20 MHZ) (M16C/28, M16C/28B)
VCC = 2.7 V to 5.5 V (f(BCLK) = 10 MHZ) (M16C/28, M16C/28B)
16 mA (VCC = 5V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3.0 µA (VCC = 3V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (VCC = 3V, in stop mode)
Power consumption
Flash Memory Program/erase supply voltage
Program and erase endurance
2.7 V to 5.5 V
100 times (all space) or 1,000 times (Blocks 0 to 5)
(3)
/10,000 times (Block A, Block B
)
Operating Ambient Temperature
-20 to 85°C/-40 to 85°C(3)
Package
NOTES:
80-pin plastic mold LQFP, 85-pin plastic mold TFLGA
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. Refer to Table 1.5 to 1.7 for number of program/erase.
4. Use PLL frequency synthesizer to use M16C/28B at f(BCLK) = 24 MHz.
page 2
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.2 M16C/28 Group (M16C/28, M16C/28) (64-Pin Package)
Item
Performance
CPU
Number of basic instructions 91 instructions
Minimum instruction
excution time
41.7 ns (f(BCLK) = 24 MHZ, VCC = 4.2 V to 5.5 V) (M16C/28B)
50 ns (f(BCLK) = 20 MHZ, VCC = 3.0V to 5.5V) (M16C/28, M16C/28B)
100 ns (f(BCLK) = 10 MHZ, VCC = 2.7V to 5.5V) (M16C/28, M16C/28B)
Single chip mode
Operation mode
Address space
Memory capacity
I/O Port
1M bytes
See Table 1.3
Peripheral
Function
Input/Output : 55 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
:
16bit base timer x 1 channel (Input/Output x 8 channels
)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I2C bus(1), or IEbus(2)
1 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I2C bus(1))
A/D converter
DMAC
10 bits x 13 channels
2 channels
Watchdog timer
Interrupt
15 bits x 1 (with prescaler)
24 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
• Main clock(*)
• Sub-clock(*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with a built-in feedback resistor
Main clock oscillation stop, re-oscillation detect function
Oscillation Stop Detect
Function
Voltage detection circuit
Power supply voltage
Available
Electrical
Characteristics
V
V
V
CC = 4.2 V to 5.5 V (f(BCLK) = 24 MH
CC = 3.0 V to 5.5 V (f(BCLK) = 20 MH
CC = 2.7 V to 5.5 V (f(BCLK) = 10 MH
Z
Z
Z
) (M16C/28)
) (M16C/28, M16C/28B)
) (M16C/28, M16C/28B)
Power consumption
16 mA (VCC = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3.0 µA (VCC = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (VCC = 3 V, in stop mode)
2.7 V to 5.5 V
Flash Memory Program/erase supply voltage
Program and erase endurance
100 times (all space) or 1,000 times (Blocks 0 to 5)
(3)
/10,000 times (Block A, Block B
-20 to 85C°/-40 to 85C°(3)
64-pin plastic mold LQFP
)
Operating Ambient Temperature
Package
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. Refer to Table 1.5 to 1.7 for number of program/erase.
4. Use PLL frequency synthesizer to use M16C/28B at f(BCLK) = 24 MHz.
page 3
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 80-pin and 85-pin package.
Figure 1.2 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 64-pin package.
8
8
8
8
I/O Ports
Port P3
Port P0
Port P1
Port P2
Internal Peripheral Functions
Timer (16 bits)
UART/clock synchronous SI/O
(8 bits x 3 channels)
System clock generator
Output (Timer A) : 5
Input (Timer B) : 3
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
Clock synchronous SI/O
(8 bits x 2 channels)
3-phase PWM
Multi-master I2C bus
Timer S
Input capture/
Output compare
Time measurement : 8 channels
Waveform generating : 8 channels
(
)
M16C/60 Series CPU Core
Memory
ROM(1)
SB
USP
ISP
INTB
PC
FLG
R0H
R1H
R0L
R1L
A/D converter
(10 bits x 24 channels)
R2
R3
RAM(2)
Watchdog timer
(15 bits)
A0
A1
FB
Multiplier
DMAC
(2 channels)
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.1 M16C/28 Group (M16C/28, M16C/28B), 80-Pin/85-Pin Block Diagram
page 4
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
4
3
8
4
I/O Ports
Port P3
Port P0
Port P1
Port P2
Internal Peripheral Functions
Timer (16 bits)
UART/Clock synchronous SI/O
(8 bits x 3 channels)
System clock generator
Output (Timer A) : 5
Input (Timer B) : 3
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
Clock synchronous SI/O
(8 bits x 1 channel)
3-phase PWM
2
Multi-master I C bus
Timer S
Input capture/
Output compare
Time measurement : 8 channels
Waveform generating : 8 channels
)
(
M16C/60 Series CPU Core
Memory
(1)
ROM
SB
R0H
R1H
R0L
R1L
A/D converter
USP
ISP
(10 bits x 13 channels)
R2
R3
(2)
RAM
INTB
PC
FLG
A0
A1
FB
Watchdog timer
(15 bits)
Multiplier
DMAC
(2 channels)
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.2 M16C/28 Group (M16C/28, M16C/28B), 64-Pin Block Diagram
page 5
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
1.4 Product Information
Tables 1.3 and 1.4 list the M16C/28 Group product information and Figure 1.3 shows the product number-
ing system. The specifications are partially different between normal-ver.and T/ V-ver..
Table 1.3 M16C/28 Product List -Normal-ver.
As of September, 2006
ROM
Capacity
RAM
Capacity
Type Number
M30280F6WG
Package Type
Remarks
Product Code
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
48 K + 4 K
64 K + 4 K
96 K + 4 K
48 K + 4 K
64 K + 4 K
96 K + 4 K
128 K + 4 K
48 K + 4 K
64 K + 4 K
96 K + 4 K
128 K + 4 K
64 K
4 K
4 K
8 K
4 K
4 K
8 K
12 K
4 K
4 K
8 K
12 K
4 K
M30280F8WG
M30280FAWG
M30280F6HP
M30280F8HP
M30280FAHP
M30280FCHP
M30281F6HP
M30281F8HP
M30281FAHP
M30281FCHP
PTLG0085JB-A (85F0G)
PLQP0080KB-A (80P6Q-A)
PLQP0064KB-A (64P6Q-A)
Flash
Memory
U3, U5, U7, U9
M30280M8-XXXHP (N)
M30280MA-XXXHP (N)
PLQP0080KB-A (80P6Q-A)
PLQP0064KB-A (64P6Q-A)
96 K
128 K
64 K
8 K
12 K
4 K
M30280MC-XXXHP (N)
M30281M8-XXXHP (N)
M30281MA-XXXHP (N)
M30281MC-XXXHP (N)
(N): New
Mask
ROM
U3, U5
96 K
8 K
128 K
12 K
Table 1.4 M16C/28B Product List -Normal-ver.
As of September, 2006
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30280FCBHP
M30281FCBHP
(D)
(D)
128 K + 4 K
128 K + 4 K
12 K
12 K
PLQP0080KB-A (80P6Q-A)
PLQP0064KB-A (64P6Q-A)
Flash
memory
U7
(D): Under development
page 6
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Type No.
M 3 0 2 8 0 F C B H P - U 7
Product code
Package type:
HP : Package PLQP0080KB-A(80P6Q-A)
PLQP0064KB-A(64P6Q-A)
WG : Package PTLG0085JB-A(85F0G)
Version
(no): M16C/28 Group Normal-ver.
B: M16C/28B Group
ROM capacity / RAM capacity
(1)
:
6 : (48K+4K) bytes / 4K bytes
8 : (64K + 4K) bytes / 4K bytes
A : (96K + 4K) bytes / 8K bytes
C : (128K + 4K) bytes / 12K bytes
Memory type:
F : Flash memory version
M : Mask ROM version
Pin count
(The value itself has no specific meaning)
M16C/28 Group, M16C/28B Group
M16C Family
NOTE:
1. "+4K bytes" is available only in flash memory ver..
Figure 1.3 Product Numbering System
page 7
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
(1)
(1)
Table 1.5 Product Code (Flash Memory-ver.) - M16C/28 Normal-ver., 64-Pin /80-Pin /85-Pin Package
Internal ROM
(User Program Space)
Internal ROM
(Data Space)
Product
Code
Operating Ambient
Temperature
Package
Lead free
Program and
Erase
Endurance
Program and
Erase
Endurance
Temperature
Range
Temperature
Range
U3
-40 to 85ºC
-20 to 85ºC
-40 to 85ºC
-20 to 85ºC
100
100
0 to 60ºC
U5
U7
U9
0 to 60ºC
-40 to 85ºC
-20 to 85ºC
1,000
10,000
NOTE:
1. The lead contained products, D3, D5, D7 and D9, are put together with U3, U5, U7 and U9 respectively. Lead-
free (Sn-Ag-Cu plating) products can be mounted by both conventional Sn-Pb paste and Lead-free paste.
Table 1.6 Product Code (Flash Memory-ver.) - M16C/28B Normal-ver., 64-Pin/85-Pin Package
Internal ROM
(User Program Space)
Internal ROM
(Data Space)
Product
Code
Operating Ambient
Temperature
Package
Lead-free
Program
Temperature
and Erase
Range
Program
and Erase
Endurance
Temperature
Range
Endurance
U7
1,000
0 to 60ºC
10,000 -40 to 85ºC
-40 to 85ºC
Table 1.7 Product Code (Mask ROM ver.) - M16C/28B Normal-ver., 64-Pin/80-Pin/85-Pin Package
Product
Code
Operating Ambient
Temperature
Package
Lead-free
U3
U5
-40 to 85ºC
-20 to 85ºC
page 8
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
(1) Flash Memory Version, PTLG0085JB-A (85F0G), Normal-ver.
Type No. M30280FAWG
M30280FA
B U5
XXXXXXX
Chip version and product code
B
: Chip version.
The first edition is shown to be blank and continues with A, B, and C.
U5: Product code. (See Table 1.5)
Date code seven digits
Manufacturing management code
(2) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver.
M16C
M30280FAHP
Type No. M30280FAHP
Chip version and product code
A U5
(1)
XXXXXXX
A
: Chip version and product code
The first edition is shown to be blank and continues with A, B and C.
U5 : Product code. (Table 1.4)
Date code seven digits
Manufacturing management code
(3) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver.
Type No. M30281FAHP
30281FA
Chip version and product code
A U5
(1)
A
: Chip version and product code
The first edition is shown to be blank and continues with A, B and C.
XXXXXXX
U5 : Product code. (Table 1.4)
Date code seven digits
Manufacturing management code
(4) Mask ROM Version, PLQP0080KB-A (80P6Q-A), Normal-ver.
Type No. M30280MAHP
M16C
M30280MA-
XXXHP A U5
XXXXXXX
Chip version and product code
XXX : ROM No.
(1)
A
: Chip version and product code
The first edition is shown to be blank and continues with A, B and C.
U5 : Product code. (Table 1.6)
Date code seven digits
Manufacturing management code
(5) Mask ROM Version, PLQP0064-KB-A (64P6Q-A), Normal-ver.
Date code seven digits
XXXXXXX
M30281MA-
XXXHP A U5
Manufacturing management code
Type No. M30281MAHP
Chip version and product code
XXX: ROM No.
(1)
A
: Chip version and product code
The first edition is shown to be blank and continues with A, B and C.
U5 : Product code. (Table 1.6)
NOTES:
1. The following functinos are not available in the first version and version A products.
-Delay trigger mode 0 of A/D conversion
-Delay trigger mode 1 of A/D conversion
Figure 1.4 Marking Diagram-M16C/28 Normal-ver.
page 9
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
1.5 Pin Assignment
Figures 1.5 to 1.7 show the pin Assignments (top view).
H
J
K
A
B
C
D
E
F
G
5
52
50
47
44
42
38
10
9
61
60
58
P06
P07
P11
P14
P17
P21
P24
P27
P61
P31
62
63
59
5
53
51
48
45
43
39
P05
P04
P10
P13
P16
P20
P23
P26
P60
P30
64
65
66
5
54
(11)
49
46
41
40
8
7
6
5
(2)
P03
P02
P01
P12
P15
(Vss)
P22
P25
P62
P63
67
68
69
37
36
35
P00
P107
P106
P32
P33
P34
70
71
(11)
34
33
32
(2)
P105
P104
(Vss)
P35
P36
P37
74
73
72
31
30
(11)
(2)
P101
P102
P103
P64
P65
(Vss)
(11)
77
76
75
29
28
27
4
3
2
(2)
VREF
P100
AVss
(Vss)
P66
P67
P70
78
79
4
9
11
14
17
26
25
24
AVcc
P97
P91
RESET
Vss
P85
P82
P71
P72
P73
80
2
5
7
12
13
16
19
23
22
P96
P93
P90
XIN
Vcc
P83
P80
P74
P75
P87/XCIN
1
3
6
8
10
13
15
18
21
20
1
P95
P92
CNVss
XOUT
Vcc
P84
P81
P76
P77
P86/XCOUT
NOTES :
1. The numbers in each grid (circle) show the pin numbers of the M30280FAHP (80P6Q-A
package)
2. Connect grids written as (Vss) to Vss(GND) or leave them open.
3. Set PACR2 to PACR0 bits in the PACR register to "0112" before you input and output it after
resetting to each pin. When the PACR register is not set, the input and output function of
some pins are disabled.
Package: PTLG0085JB-A(85F0G)
Figure 1.5 Pin Assignment (Top View) of 85-pin Package
page 10
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.8 Pin Characteristics for 85-pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Multi-master
I2C bus Pin
PLQP0080KB-A
Pin Number
Port
Timer Pin
Timer S Pin
UART Pin
Analog Pin
A1
A2
P9
5
6
CLK
S
4
AN2
5
6
1
80
78
77
74
70
67
64
62
61
3
P9
OUT4
AN2
A3 AVcc
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
VREF
P10
1
5
AN
1
5
P10
KI
1
AN
P00
P03
P05
P06
P92
P93
P97
AN0
AN0
AN0
AN0
0
3
5
6
TB2IN
AN2
4
7
2
S
IN4
AN2
79
76
73
71
68
65
63
60
6
P10
P10
P10
P10
0
2
4
7
AN
AN
AN
AN
0
2
4
7
KI
KI
0
3
P02
P04
P07
AN0
AN0
AN0
2
4
7
C1 CNVss
C2
P9
0
1
TB0IN
TB1IN
5
C3
P9
4
C4 AVss
75
72
(11)
69
66
59
58
C5
C6 Vss(1)
P10
3
6
AN
3
6
C7
P10
KI
2
AN
C8
P0
1
0
AN0
AN2
AN2
1
0
1
C9
P1
C10
P1
P8
1
6
D1
D2
X
COUT
CIN
8
7
X
P87
D3 RESET
D4 Vss(1)
D8
9
(11)
57
56
55
10
12
11
P12
P13
P14
AN2
2
3
D9
AN2
D10
E1
E2
X
OUT
IN
X
E3 Vss
page 11
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.8 Pin Characteristics for 85-pin Package (continued)
Pin
No.
Control
Pin
Interrupt
Pin
Multi-master
I2C bus Pin
PLQP0080KB-A
Pin Number
Port
Timer Pin Timer S Pin
UART Pin
Analog Pin
ADTRG
E8
P1
5
6
7
INT
INT
INT
3
4
5
IDV
54
53
E9
P1
P1
IDW
IDU
E10
INPC1
7
52
F1 Vcc
13
F2 Vcc
F3
F8 Vss(1)
13
P8
5
0
NMI
SD
ZP
14
(11)
OUTC1
INPC1
OUTC1
INPC1
0
/
/
F9
P2
0
SDAMM
SCLMM
51
1
F10
P21
P84
P83
P82
1
50
15
16
17
G1
G2
G3
INT
INT
INT
2
1
0
OUTC1
INPC1
OUTC1
INPC1
OUTC1
INPC1
2
3
4
/
/
/
G8
G9
P2
2
3
2
49
48
P2
3
G10
H1
H2
H3
H4
P24
P81
P80
P71
P66
4
47
18
TA4IN / U
TA4OUT / U
TA0IN
19
R
X
X
D
2
1
/ SCL
2
/ CLK
1
26
R
D
29
H5 Vss(1)
(11)
34
H6
H7
P3
5
2
P3
S
OUT3
37
OUTC1
INPC1
OUTC1
INPC1
OUTC1
INPC1
5
6
7
/
/
/
H8
H9
P2
5
6
5
46
45
P2
6
H10
J1
P27
P76
P74
P72
P67
7
44
21
23
25
28
TA3OUT
J2
TA2OUT / W
TA1OUT / V
J3
CLK2 / RXD1
J4
TXD1
RTS
1
/ CTS
1/ CTS
0
/
J5
J6
P6
P3
P3
P6
P6
P6
P7
P7
P7
4
6
3
2
0
1
7
5
3
CLKS
1
31
33
36
41
43
42
20
22
24
J7
J8
RXD0
J9
RTS
0
0
/ CTS
0
J10
K1
K2
K3
CLK
TA3IN
TA2IN / W
TA1IN / V
CTS
2
/ RTS
/ SDA
/ CTS
2
/ TXD1
/ RTS1 /
/ CLKS
T
X
D2
2
K4
K5
P70
P65
P37
P34
P63
P30
P31
TA0OUT
CTS
1
0
1
27
30
32
35
40
39
38
CLK
1
K6
K7
K8
TXD0
K9
CLK3
K10
SIN3
page 12
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
61
62
63
64
65
66
67
68
P6
3
/T
/CLK
/SIN
/SOUT
X
D
0
P0
P0
P0
P0
P0
6
5
4
3
2
/AN0
/AN0
/AN0
/AN0
/AN0
6
5
4
3
2
P3
0
3
38
37
36
35
34
P3
P3
P3
P3
P3
1
3
2
3
4
5
3
P0
P0
1
0
/AN0
/AN0
1
0
33
32
31
P107/AN7/KI3
P3
P3
P6
6
69
70
71
P10
6
/AN
/AN
6
/KI
2
1
0
7
P10
5
5/KI
4
/CTS
1
1
1
/RTS
1
/CTS
0
/CLKS
1
30
29
P104/AN4/KI
P6
P6
P6
5
/CLK
P10
P10
P10
3
2
1
/AN
3
2
1
72
73
74
75
76
77
78
79
80
6
7
/RxD
28
27
26
25
24
/AN
/AN
/TXD1
P7
0
/TXD
2
/SDA
2
/TA0OUT/CTS1/RTS1/CTS
0/CLKS1
AVSS
/AN
P7
1
/RXD
2/SCL
2
/TA0IN/CLK1
P10
0
0
P7
2
/CLK
2/TA1OUT/V/RxD1
V
REF
P73
/CTS
2
/RTS /TA1IN/V/TxD1
2
23
22
21
AVcc
P7
P7
4
5
/TA2OUT/W
/TA2IN/W
P9
6
7
/AN2
7
/SIN4
P9 /AN2
6
/SOUT4
P76/TA3OUT
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
NOTES:
1.Set PACR2 to PACR0 bit in the PACR register to "011
2" before you
input and output it after resetting to each pin. When the PACR
register isn't set up, the input and output function of some of the pins
are disabled.
Package: PLQP0080KB-A(80P6Q-A)
Figure 1.5 Pin Assignment (Top View) of 80-Pin Package
page 13
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
Analog Pin
M16C/28 Group (M16C/28, M16C/28B)
Table 1.9 Pin Characteristics for 80-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Multi-master
I2C bus Pin
Port
Timer Pin
Timer S Pin
UART Pin
1
2
P9
5
3
2
1
0
CLK
4
AN2
5
4
P9
P9
P9
P9
AN2
3
TB2IN
4
TB1IN
TB0IN
5
6
CNVss
7
X
CIN
P8
7
6
8
XCOUT
P8
9
RESET
10
XOUT
11 Vss
12
XIN
13 Vcc
14
P8
P8
P8
P8
P8
P8
P7
P7
P7
P7
P7
P7
P7
5
4
3
2
1
0
7
6
5
4
3
2
1
NMI
SD
ZP
15
INT
INT
INT
2
1
0
16
17
18
TA4IN / U
TA4OUT / U
TA3IN
19
20
21
TA3OUT
22
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
23
24
CTS
2
/ RTS
2
/ T
X
D1
25
CLK
2
/ R
X
D
1
2
26
RX
D2
/ SCL
/ CLK
1
T
X
D2
/ SDA
2
/ RTS
1 /
27
28
29
30
P7
P6
P6
P6
0
7
6
5
TA0OUT
CTS
1
/ CTS
0
/ CLKS1
TXD1
RXD1
CLK
1
RTS
1
/ CTS1/ CTS0 /
31
32
33
34
35
36
37
38
39
40
P6
P3
P3
P3
P3
P3
P3
P3
P3
P6
4
7
6
5
4
3
2
1
0
3
CLKS
1
S
OUT3
IN3
S
CLK
3
TXD0
page 14
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.9 Pin Characteristics for 80-Pin Package (Continued)
Pin
No.
Control
Pin
Interrupt
Pin
Multi-master
I2C bus Pin
Port
Timer Pin
Timer S Pin
UART Pin
Analog Pin
41
P6
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RXD0
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
P6
P6
P2
P2
P2
P2
P2
P2
P2
P2
P1
P1
P1
P1
P1
P1
P1
P1
P0
P0
P0
P0
P0
P0
P0
P0
CLK
0
RTS
0
/ CTS0
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
7
6
5
4
3
2
1
0
/ INPC1
/ INPC1
/ INPC1
/ INPC1
/ INPC1
/ INPC1
/ INPC1
/ INPC1
7
6
5
4
3
2
1
0
SCLMM
SDAMM
INT
INT
INT
5
4
3
IDU
INPC17
IDW
IDV
ADTRG
AN2
AN2
AN2
AN2
AN0
AN0
AN0
AN0
AN0
AN0
AN0
AN0
3
2
1
0
7
6
5
4
3
2
1
0
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
75 AVss
76
P10
0
AN0
77 VREF
78 AVcc
79
P9
7
6
S
S
IN4
OUT4
AN2
7
6
80
P9
AN2
page 15
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
32
P02/AN02
49
50
51
52
53
P3
P3
P3
0
1
2
/CLK
3
P0
1
/AN0
1
0
3
31
30
29
/SIN3
P0
0
/AN0
/SOUT3
P10
P10
P10
P10
P10
7
/AN
/AN
/AN
/AN
7
/KI
/KI
/KI
/KI
/AN
P3
3
6
6
2
28
27
26
25
24
23
22
21
20
19
18
17
P6
P6
P6
4
5
6
/CTS1/RTS1/CTS0/CLKS1
5
5
1
54
55
/CLK
1
1
4
4
0
/RxD
3
3
56
57
58
59
60
61
P6
P7
7
/TxD
1
P10
2
/AN
/AN
2
0
/TxD
2
/SDA
2
/TA0OUT/RTS1/CTS1/CTS0/CLKS1
/TA0IN/CLK1
/TA1OUT/V/RxD1
/RTS /TA1IN/V/TxD1
P10
1
1
P7
P7
1
/RxD
2
/SCL2
AVSS
2
/CLK
2
P100/AN
0
P7
3
/CTS
2
2
V
REF
P7
4
/TA2OUT/W
/TA2IN/W
AVCC
/AN2
/TB2IN
62
63
64
P7
5
P9
P9
3
4
P7
6
/TA3OUT
2
P7
7
/TA3IN
NOTES:
1.Set PACR2 to PACR0 bit in the PACR register to "010
2" before you
input and output it after resetting to each pin. When the PACR
register isn't set up, the input and output function of some of the pins
are disabled.
Package: PLQP0064KB-A(64P6Q-A)
Figure 1.6 Pin Assignment (Top View) of 64-Pin Package
page 16
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.10 Pin Characteristics for 64-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Mult-master
I2C bus Pin
Port
Timer Pin
Timer S Pin
UART Pin
Analog Pin
1
2
3
4
5
6
7
8
9
P9
1
TA1IN
P90
TB0IN
CNVss
XCIN
P8
7
6
XCOUT
P8
RESET
XOUT
Vss
XIN
10 Vcc
11
P8
P8
P8
P8
P8
P8
P7
P7
P7
P7
P7
P7
P7
5
4
3
2
1
0
7
6
5
4
3
2
1
NMI
SD
ZP
12
INT
INT
INT
2
1
0
13
14
15
TA4IN / U
TA4OUT / U
TA3IN
16
17
18
TA3OUT
19
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
20
21
CTS
CLK
2
/ RTS
2
/ T
X
D1
22
2
/ RX
D1
23
RXD2
/ SCL
2
/ CLK
1
T
XD2
/ SDA
2
/ RTS
1 /
24
25
26
27
P7
P6
P6
P6
0
7
6
5
TA0OUT
CTS
1
/ CTS
0
/ CLKS1
TXD1
RXD1
CLK
RTS
1
1
/ CTS1/ CTS0 /
28
29
30
31
32
33
34
35
36
37
38
39
40
P6
P3
P3
P3
P3
P6
P6
P6
P6
P2
P2
P2
P2
4
3
2
1
0
3
2
1
0
7
6
5
4
CLKS
1
S
S
OUT3
IN3
CLK
3
TXD0
RXD0
CLK
0
0
RTS
/ CTS
0
OUTC1
OUTC1
OUTC1
OUTC1
7
6
5
4
/ INPC1
/ INPC1
/ INPC1
/ INPC1
7
6
5
4
page 17
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
Analog Pin
M16C/28 Group (M16C/28, M16C/28B)
Table 10 Pin Characteristics for 64-Pin Package (Continued)
Pin
No.
Control
Pin
Interrupt
Pin
Multi-master
I2C bus Pin
Port
Timer Pin
Timer S Pin
UART Pin
41
P2
3
2
1
0
7
6
5
3
2
1
0
OUTC1
OUTC1
OUTC1
OUTC1
3
2
1
0
/ INPC1
/ INPC1
/ INPC1
/ INPC1
3
2
1
0
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
P2
P2
P2
P1
P1
P1
P0
P0
P0
P0
SCLMM
SDAMM
INT
INT
INT
5
4
3
IDU
INPC17
IDW
IDV
ADTRG
AN0
AN0
AN0
AN0
3
2
1
0
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
59 AVss
60
P10
0
AN0
61 VREF
62 AVcc
63
P9
3
2
AN2
4
64
P9
TB2IN
page 18
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
1.6 Pin Description
Table 1.10 Pin Description (64-Pin, 80-Pin and 85-Pin Packages)
Classification
Power Supply VCC, VSS
Symbol
I/O Type
I
Function
Apply 2.7 to 5.5V to the Vcc pin. Apply 0V to the Vss pin.
Analog Power AVCC
I
Supplies power to the A/D converter. Connect the AVCC pin to VCC and
Supply
AVSS
the AVSS pin to VSS.
____________
___________
Reset Input
CNVSS
Main Clock
Input
RESET
CNVSS
I
I
The MCU is in a reset state when "L" is applied to the RESET pin
Connect the CNVSS pin to VSS.
I/O pins for the main clock oscillation circuit. Connect a ceramic resonator
or crystal oscillator between XIN and XOUT. To apply external clock, apply
it to XIN and leave XOUT open. If XIN is not used (for external oscillator or
external clock) connect XIN pin to VCC and leave XOUT open.
I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator
between XCIN and XCOUT.
XIN
I
Main Clock
Output
XOUT
O
Sub Clock Input XCIN
Sub Clock Output XCOUT
I
O
I
______
________
INT Interrupt
INT0 to _I_N__T__5__
Input pins for the _I_N__T__ interrupt. _I_N__T__2__ can be used for Timer A Z-phase
function.
Input
_______
_______
NMI Interrupt NMI
Input
Input pin for the _N__M___I_ interrupt. _N__M___I_ cannot be used as I/O port while the three-
phase motor control is enabled. Apply a stable "H" to _N__M___I_ after setting it's
direction register to "0" when the three-phase motor control is enabled.
Input pins for the key input interrupt
I
_____
_____
Key Input Interrupt KI0 to KI3
I
Timer A
TA0OUT to
TA4OUT
TA0IN to
TA4IN
I/O pins for the timer A0 to A4
I/O
I
Input pins for the timer A0 to A4
ZP
I
I
Input pin for Z-phase
Timer B
TB0IN to
TB2IN
Input pins for the timer B0 to B2
Three-phase
U, _U__, V, _V__,
Output pins for the three-phase motor control timer
O
___
Motor Control W, W
Timer Output IDU, IDW,
Input and output pins for the three-phase motor control timer
I/O
_____
IDV, SD
_________
_________
Serial I/O
CTS0 to CTS2
Input pins for data transmission control
Output pins for data reception control
Inputs and outputs the transfer clock
Inputs serial data
I
O
_________
_________
RTS0 to RTS2
CLK0 to CLK3
RxD0 to RxD2
TxD0 to TxD2
CLKS1
I/O
I
Outputs serial data
O
O
Output pin for transfer clock
I2C Mode
SDA2
Inputs and outputs serial data
Inputs and outputs the transfer clock
Inputs and outputs serial data
Inputs and outputs the transfer clock
Applies reference voltage to the A/D converter
I/O
SCL2
Multi-master
I2C bus
SDAMM
I/O
SCLMM
Reference
Voltage Input
VREF
I
I
A/D Converter AN0 to AN7
Analog input pins for the A/D converter
AN0
0
to AN03
AN2
4
___________
ADTRG
Input pin for an external A/D trigger
I : Input
O : Output
I/O : Input and output
page 19
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.10 Pin Description (64-Pin, 80-Pin and 85-Pin Packages) (Continued)
Classification
Timer S
Symbol
I/O Type
Function
INPC1
0
to INPC1
7
I
Input pins for the time measurement function
Output pins for the waveform generating function
OUTC1
0
to OUTC1
7
O
I/O Ports
P00 to P03
P15 to P17
P20 to P27
P30 to P33
P60 to P67
P70 to P77
P80 to P87
I/O
I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available
in 4-bit units
P10
0
to P10
7
P90 to P93
I/O
I/O ports having equivalent functions to P0
I : Input
O : Output
I/O : Input and output
page 20
Rev. 0.50 Sep.15, 2006
of 33
1. Overview
M16C/28 Group (M16C/28, M16C/28B)
Table 1.10 Pin Description (80-Pin and 85-Pin Packages only) (Continued)
Classification
Symbol
I/O Type
Function
Serial I/O
CLK4
I/O
Inputs and outputs the transfer clock
SIN4
I
O
I
Inputs serial data
SOUT4
Outputs serial data
A/D Converter AN0
4
0
5
to AN0
to AN2
to AN2
7
3
7
Analog input pins for the A/D converter
AN2
AN2
I/O Ports
I : Input
P04 to P07
P10 to P14
P34 to P37
P95 to P97
I/O
I/O
I/O ports for CMOS. Each port can be programmed for input or output under the
control of the direction register. An input port can be set, by program, for a pull-
up resistor available or for no pull-up resister available in 4-bit units
I/O ports having equivalent functions to P0
O : Output
I/O : Input and output
page 21
Rev. 0.50 Sep.15, 2006
of 33
2. Central Processing Unit(CPU)
M16C/28 Group (M16C/28, M16C/28B)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of 7 registers (R0, R1, R2, R3, A0, A1
and FB) out of 13 CPU registers. Two sets of register banks are provided.
b31
b15
b8 b7
b0
R2
R3
R0H(R0's high bits)
R1H(R1's high bits)
R0L(R0's low bits)
R1L(R1's low bits)
(1)
Data registers
R2
R3
A0
A1
FB
(1)
Address registers
(1)
Frame base registers
b19
b15
b0
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
Program counter
b15
US P
User stack pointer
Interrupt stack pointer
Static base register
SB
b15
b0
b0
FL G
Flag register
b15
b8 b7
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved space
Processor interrupt priority level
Reserved space
NOTES:
1. The register bank is comprised of these registers. Two sets of register banks are provided.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0, R1, R2 and R3 registers are 16 bit registers for transfer and arithmetic/logic operations.
The R0 and R1 registers can be split into high-order bits(R0H, R1H) and low-order bits (R0L, R1L) to be
used seperately as 8-bit data registers. Conversely, R2 and R0 can be combined with R2 to be used as a
32-bit data register (R2R0). The same applies to R1 and R2.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register
relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
page 22
Rev. 0.50 Sep.15, 2006
of 33
2. Central Processing Unit(CPU)
M16C/28 Group (M16C/28, M16C/28B)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is
cleared to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write 0. When read, its content is indeterminate.
page 23
Rev. 0.50 Sep.15, 2006
of 33
3. Memory
M16C/28 Group (M16C/28, M16C/28B)
3. Memory
Figure 3.1 is a memory map of the M16C/28 Group (M16C/28, M16C/28B). M16C/28 Group provides 1-
Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses
beginning with address FFFFF16. For example, 64 Kbytes internal ROM is allocated addresses F000016 to
FFFFF16.
Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version. The
blocks are allocated addresses F00016 to FFFF16.
The fixed interrupt vector tables are allocated addresses FFFDC16 to FFFFF16. It stores the starting ad-
dress of each interrupt routine. See the section on interrupts for details.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, 4-Kbytes
internal RAM is allocated addresses 0040016 to 013FF16. Besides storing data, it becomes stacks when the
subroutine is called or an interrupt is acknowledged.
SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers is allocated addresses 0000016 to 003FF16. All blank spaces within SFR are reserved and cannot be
accessed by users.
The special page vector table is allocated to the addresses FFE0016 to FFFDB16. This vector is used by the
JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
Internal RAM area
Internal ROM area
Memory size
Memory size
XXXXX16
013FF16
01AFF16
023FF16
YYYYY16
F400016
F000016
E800016
E000016
4K bytes
6K bytes
8K bytes
12K bytes
48K bytes
64K bytes
96K bytes
128K bytes
0000016
0040016
XXXXX16
SFR Area
033FF16
Internal RAM Area
FFE0016
FFFDC16
FFFFF16
RESERVED
Special Page
Vector Table
0F00016
0FFFF16
Internal ROM Area
(1)
(data space)
Undefined Instruction
Overflow
RESERVED
BRK Instruction
Address Match
Single Step
Watchdog Timer
YYYYY16
FFFFF16
DBC
Internal ROM Area
(program space)
NMI
Reset
NOTES:
1. The block A (2K bytes) and block B (2K bytes) are shown (only flash memory).
2. Do not write to the internal ROM area in Mask ROM ver..
Figure 3.1 Memory Map
page 24
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR
information.
(1)
Table 4.1 SFR Information(1)
Address
Register
Symbol
After Reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
0016
000010002
010010002
001000002
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX002
XX0000002
Oscillation stop detection register (2)
CM2
0X0000102
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
XX16
00XXXXXX2
0016
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1 (3)
Voltage detection register 2 (3)
VCR1
VCR2
000010002
0016
PLL control register 0
PLC0
0001X0102
Processor mode register 2
Low voltage detection interrupt register
DMA0 source pointer
PM2
D4INT
SAR0
XXX000002
0016
XX16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
XX16
XX16
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
TCR0
XX16
XX16
XX16
XX16
XX16
DM0CON
SAR1
00000X002
XX16
XX16
XX16
DAR1
XX16
XX16
XX16
TCR1
XX16
XX16
DM1CON
00000X002
NOTES:
1.The blank spaces are reserved. No access is allowed.
2. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
3. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Undefined
page 25
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.2 SFR Information(2)
Register
After Reset
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Symbol
INT3 interrupt control register
INT3IC
ICOC0IC
XX00X0002
IC/OC 0 interrupt control register
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
IC/OC 1 interrupt control register, I C bus interface interrupt control register ICOC1IC,IICIC
IC/OC base timer interrupt control register, SCLSDA interrupt control register BTIC,SCLDAIC
SI/O4 interrupt control register, INT5 interrupt control register
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
XX00X000
XX00X000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00X000
XX00X000
XX00X000
2
2
2
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note 1: The blank spaces are reserved. No access is allowed.
X : Undefined
page 26
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.3 SFR Information(3)
Register
Symbol
After Reset
Address
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
Flash memory control register 4 (2)
Flash memory control register 1 (2)
Flash memory control register 0 (2)
FMR4
FMR1
FMR0
01000000
000XXX0X
00000001
2
2
2
~
~
~
~
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
Low-power Consumption Control 0
LPCC0
X00000012
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
Low-power Consumption Control 1
ROCR
PACR
PCLKR
LPCC1
X0000101
0016
2
00000011
0016
2
~
~
~
~
I2C0 data shift register
S00
XX16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
I2C0 address register
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
0016
0016
0016
00011010
00110000
0016
I2C0 control register 0
I2C0 clock control register
I2C0 start/stop condition control register
I2C0 control register 1
2
2
I2C0 control register 2
I2C0 status register
0001000X2
~
~
~
~
02FE16
02FF16
Note 1:The blank spaces are reserved. No access is allowed.
Note 2:This register is included in the flash memory version.
X : Undefined
page 27
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.4 SFR Information(4)
Register
Symbol
After Reset
Address
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
TM, WG register 0
TM, WG register 1
TM, WG register 2
TM, WG register 3
TM, WG register 4
TM, WG register 5
TM, WG register 6
TM, WG register 7
G1TM0,G1PO0
G1TM1,G1PO1
G1TM2,G1PO2
G1TM3,G1PO3
G1TM4,G1PO4
G1TM5,G1PO5
G1TM6,G1PO6
G1TM7,G1PO7
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
WG control register 0
WG control register 1
WG control register 2
WG control register 3
WG control register 4
WG control register 5
WG control register 6
WG control register 7
TM control register 0
TM control register 1
TM control register 2
TM control register 3
TM control register 4
TM control register 5
TM control register 6
TM control register 7
Base timer register
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0016
2
2
2
2
2
2
2
2
0016
0016
0016
0016
0016
0016
0016
XX16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
XX16
0016
0016
0016
0016
0016
0016
XX16
Base timer control register 0
Base timer control register 1
TM prescale register 6
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
TM prescale register 7
Function enable register
Function select register
Base timer reset register
G1FS
G1BTRR
XX16
0016
Divider register
G1DV
Interrupt request register
Interrupt enable register 0
Interrupt enable register 1
G1IR
G1IE0
G1IE1
XX16
0016
0016
NMI digital debounce register
P17 digital debounce register
NDDR
P17DDR
FF16
FF16
Note 1:The blank spaces are reserved. No access is allowed.
X : Undefined
page 28
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.5 SFR Information(5)
Register
Symbol
After Reset
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
00111111
00111111
XX16
2
2
Timer B2 interrupt occurrence frequency set counter
Position-data-retain function control register
ICTB2
PDRF
XX16
XXXX0000
2
Interrupt request cause select register 2
Interrupt request cause select register
SI/O3 transmit/receive register
IFSR2A
IFSR
S3TRR
00XXXXX02(2)
0016
XX16
SI/O3 control register
S3C
S3BRG
S4TRR
01000000
XX16
XX16
2
2
SI/O3 bit rate generator
SI/O4 transmit/receive register
SI/O4 control register
SI/O4 bit rate generator
S4C
S4BRG
01000000
XX16
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
2
X0000000
X0000000
0016
2
2
U2BRG
U2TB
XX16
XX16
XX16
UART2 transmit buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
00001000
00000010
XX16
2
2
XX16
Note 1: The blank spaces are reserved. No access is allowed.
Note 2: Write 1 to bit 0 after reset.
X : Undefined
page 29
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.6 SFR Information(6)
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
0016
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
0XXXXXXX
2
0016
0016
0016
Timer A0 register
Timer A1 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
038A16 Timer A2 register
038B16
038C16 Timer A3 register
038D16
038E16 Timer A4 register
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
039A16 Timer A4 mode register
039B16 Timer B0 mode register
039C16 Timer B1 mode register
039D16 Timer B2 mode register
039E16 Timer B2 special mode register
039F16
00XX0000
00XX0000
00XX0000
2
2
2
X0000000
2
03A016
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
XX16
XX16
XX16
03A116
03A216
03A316
03A416
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
XX16
2
2
03A516
03A616
03A716
XX16
03A816
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
U1MR
U1BRG
U1TB
0016
XX16
XX16
03A916
03AA16
03AB16
XX16
03AC16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
XX16
2
2
03AD16
03AE16
03AF16
XX16
03B016
UART transmit/receive control register 2
UCON
X00000002
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
DMA0 request cause select register
DM0SL
DM1SL
0016
0016
03B916
03BA16
DMA1 request cause select register
03BB16
03BC16
03BD16
03BE16
03BF16
Note 1:The blank spaces are reserved. No access is allowed.
X : Undefined
page 30
Rev. 0.50 Sep.15, 2006
of 33
M16C/28 Group (M16C/28, M16C/28B)
4. Special Function Register (SFR)
(1)
Table 4.7 SFR Information(7)
Address
Register
Symbol
AD0
After Reset
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A/D register 0
A/D register 1
A/D register 2
A/D register 3
A/D register 4
A/D register 5
A/D register 6
A/D register 7
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A/D trigger control register
A/D convert status register 0
A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
0016
00000X00
0016
2
A/D control register 0
A/D control register 1
ADCON0
ADCON1
00000XXX
0016
2
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
P6
P7
PD6
PD7
P8
XX16
XX16
0016
0016
XX16
XX16
0016
Port P9 register
P9
Port P8 direction register
Port P9 direction register
Port P10 register
PD8
PD9
P10
000X0000
XX16
2
Port P10 direction register
PD10
0016
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
Note 1:The blank spaces are reserved. No access is allowed.
X : Undefined
page 31
Rev. 0.50 Sep.15, 2006
of 33
Appendix 1. Package Dimensions
M16C/28 Group (M16C/28, M16C/28B)
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-LQFP64-10x10-0.50
PLQP0064KB-A
64P6Q-A / FP-64K / FP-64KV
0.3g
HD
D
*1
NOTE)
1.
2"
2.
INCLUDE TRIM OFFSET.
p
Reference
Symbol
Min Nom Max
D
E
A
10.0 10.1
10.0 10.1
9.9
9.9
Terminal cross section
HD
E
11.8 12.0 12.2
11.8 12.0
1.7
A
Z
A1
0.05
0.15
0.1
0.15 0.20
p
b1
c
F
0.18
0.09
0.20
0.145
0.125
c1
0
8
e
0.5
L
x
y
0.08
0.08
L1
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
41
NOTE)
1. DIMENSIONS " 1" AND " 2"
0
2. DIMENSION " 3" DOES NOT
INCLUDE TRIM OFFSET.
1
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
Reference
Symbol
Terminal cross section
D
E
A
HD
E
13.8 14.0 14.2
13.8 14.0 14.2
1.7
20
A1
0.1 0.2
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0
F
p
b1
c
c1
0
10
e
x
y
L
0.5
0.08
0.08
L1
ZD
ZE
L
Detail F
1.25
1.25
0.3 0.5 0.7
1.0
L1
page 32
Rev. 0.50 Sep.15, 2006
of 33
Appendix 1. Package Dimensions
M16C/28 Group (M16C/28, M16C/28B)
JEITA Package Code
P-TFLGA85-7x7-0.65
RENESAS Code
PTLG0085JB-A
Previous Code
85F0G
MASS[Typ.]
0.1g
b1
S
AB
D
w
S A
AB
A
A
K
J
H
G
F
B
E
D
C
B
A
y
S
1
2
3
4
5
6
7
8
9
10
x4
Dimension in Millimeters
Reference
Symbol
Index mark
(Laser mark)
S
Min Nom Max
Index mark
D
E
v
7.0
7.0
0.15
w
A
e
0.20
1.05
0.65
b
b1
x
0.31 0.35 0.39
0.39 0.43 0.47
0.08
y
0.10
page 33
Rev. 0.50 Sep.15, 2006
of 33
REVISION HISTORY
M16C/28 Group (M16C/28, M16C/28B) Shortsheet
Rev.
Date
Description
Summary
Page
-
0.50 09/15/06
First edition
A-1
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