MD82C284-10/883 [RENESAS]
20MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP18;
| 型号： | MD82C284-10/883 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 20MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP18 时钟 CD 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
82C284/883
Clock Generator and
Ready Interface for 80C286 Processors
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Intersil 82C284/883 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hys-
teresis.
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt Trigger
Input
- Improved Hysteresis
Ordering Information
• Uses Crystal or External Signal for Frequency Source
- Dynamically Switchable Between Two Input
Frequencies
PART NUMBER
TEMP. RANGE PACKAGE PKG. NO.
o
o
• Provides Local READY and MULTIBUS™ READY
Synchronization
MD82C284-12/883 -55 C to +125 C CERDIP
F18.3
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CERDIP Package
Functional Diagram
Pinout
RESET
RESET
82C284/883
(CERDIP)
RES
TOP VIEW
SYNCHRONIZER
ARDY
SRDY
SRDYEN
READY
EFI
1
2
3
4
5
6
7
8
9
18 VCC
17 ARDYEN
16 S1
X1
XTAL
OSC
X2
CLK
MUX
15 S0
EFI
F/C
14 NC
F/C
13 PCLK
12 RESET
11 RES
10 CLK
ARDYEN
ARDY
X1
SYNCHRONIZER
READY LOGIC
X2
GND
SRDYEN
SRDY
READY
PCLK
S1
S0
PCLK GENERATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FN2968.1
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
82C284/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance
θJA ( C/W) θJC ( C/W)
80 20
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Gates
Input, Output or I/O Voltage Applied. . . . . GND -0.1V to VCC +1.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
CERDIP Package . . . . . . . . . . . . . .
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . .-65 C to +150 C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 C
o
o
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera-
tion of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Operating Conditions
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
EFI Rise Time (From 0.8V to 3.2V). . . . . . . . . . . . . . . . . . 8ns (Max)
EFI Fall Time (From 3.2V to 0.8V) . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 82C284/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested.
GROUP A
PARAMETER
Input LOW Voltage
SYMBOL
VIL
CONDITIONS
VCC = 4.5V
SUBGROUPS
TEMPERATURE
MIN
-
MAX
UNITS
o
o
1, 2, 3
-55 C ≤ T ≤ +125 C
0.8
V
V
V
V
V
V
A
o
o
Input HIGH Voltage
EFI, F/C Input High Voltage
RES HIGH Voltage
VIH
VCC = 5.5V
VCC = 5.5V
VCC = 5.5V
VCC = 5.5V
1, 2, 3
-55 C ≤ T ≤ +125 C
2.2
3.2
-
A
o
o
VIHC
VIHR
VHYS
VOL
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
A
o
o
1, 2, 3
-55 C ≤ T ≤ +125 C VCC -0.8
A
o
o
RES Input Hysteresis
1, 2, 3
-55 C ≤ T ≤ +125 C
0.5
-
-
A
o
o
RESET, PCLKOutputLOW
Voltage
IOL = 5mA,
VCC = 4.5V, Note 2
1, 2, 3
-55 C ≤ T ≤ +125 C
0.4
A
o
o
RESET, PCLK Output
Voltage
VOH
VOLR
VOLC
VOHC
II
IOH = -1mA,
VCC = 4.5V, Note 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C VCC -0.4
-
V
V
A
o
o
READY Output LOW
Voltage
IOH = 10mA,
VCC = 4.55V, Note 2
-55 C ≤ T ≤ +125 C
-
-
0.4
0.4
-
A
o
o
CLK Output LOW Voltage
CLK Output HIGH Voltage
Input Leakage Current
IOL = 5mA,
VCC = 4.5V, Note 2
-55 C ≤ T ≤ +125 C
V
A
o
o
IOH = -5mA,
VCC = 4.5V, Note 2
-55 C ≤ T ≤ +125 C VCC -0.4
V
A
o
o
VIN = GND or VCC,
VCC = 5.5V
-55 C ≤ T ≤ +125 C
-10
10
µA
A
o
o
Active Power Supply
Current
ICCOP
82C284-10/883, Note 1
82C284-12/883, Note 1
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
48
60
mA
mA
A
o
o
-55 C ≤ T ≤ +125 C
A
NOTES:
1. ICCOP measured at 10MHz for the 82C284-10/883 and at 12.5MHz for the 82C284-12/883. VIN = GND or VCC, VCC = 5.5V, outputs
unloaded.
2. Interchanging of force and sense conditions is permitted.
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet wave-
forms, unless otherwise specified.
10MHz
12MHz
(NOTE 1)
GROUP A
PARAMETER
EFI LOW Time
EFI HIGH Time
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
ns
o
o
t1
t2
At VCC/2, Note 8
At VCC/2, Note 8
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
20
20
-
-
16
20
-
-
A
o
o
-55 C ≤ T ≤ +125 C
ns
A
2
82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet wave-
forms, unless otherwise specified. (Continued)
10MHz
12MHz
(NOTE 1)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
o
o
Status Setup Time
for Status Going
Active
t5A
9, 10, 11
-55 C ≤ T ≤ +125 C
20
20
-
18
16
-
ns
A
o
o
Status Setup Time
for Going Inactive
t5B
9, 10, 11
-55 C ≤ T ≤ +125 C
-
-
ns
A
o
o
Status Hold Time
F/C Setup Time
F/C Hold Time
t6
t7
t8
t9
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
1
-
-
-
-
1
-
-
-
-
ns
ns
ns
ns
A
o
o
-55 C ≤ T ≤ +125 C
15
15
15
15
15
15
A
o
o
-55 C ≤ T ≤ +125 C
A
o
o
SRDY or SRDYEN
Setup Time
-55 C ≤ T ≤ +125 C
A
o
o
SRDY or SRDYEN
Hold Time
t10
t11
t12
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
2
5
-
-
-
2
5
-
-
-
ns
ns
ns
A
o
o
ARDY or ARDYEN
Setup Time
Note 3
-55 C ≤ T ≤ +125 C
A
o
o
ARDY or ARDYEN
Hold Time
Note 3
-55 C ≤ T ≤ +125 C
30
25
A
o
o
RES Setup Time
RES Hold Time
CLK Period
t13
t14
t16
t17
t18
t21
Notes 3, 7
Notes 3, 7
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
20
10
50
12
16
5
-
-
-
-
-
-
18
8
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
A
o
o
-55 C ≤ T ≤ +125 C
A
o
o
-55 C ≤ T ≤ +125 C
40
11
13
5
A
o
o
CLK LOW Period
CLK HIGH Time
Notes 2, 6
Notes 2, 6
-55 C ≤ T ≤ +125 C
A
o
o
-55 C ≤ T ≤ +125 C
A
o
o
READY Inactive
Delay
At 0.8V, Note 4,
Test Condition 2
-55 C ≤ T ≤ +125 C
A
o
o
READY Active De-
lay
t22
t23
t24
t25
t26
At 0.8V, Note 4
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
-
-
-
24
20
27
-
-
-
-
18
16
26
-
ns
ns
ns
ns
ns
A
o
o
PCLK Delay
CL = 75pF,
Test Condition 1
-55 C ≤ T ≤ +125 C
A
o
o
RESET Delay
CL = 75pF,
Test Condition 3
-55 C ≤ T ≤ +125 C
A
o
o
PCLK LOW Time
PCLK HIGH Time
CL = 75pF, Note 5
-55 C ≤ T ≤ +125 C
t16-
10
t16-
10
A
o
o
CL = 75pF, Note 5
-55 C ≤ T ≤ +125 C
t16-
10
-
t16-
10
-
A
3
82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet wave-
forms, unless otherwise specified. (Continued)
10MHz
MIN MAX
12MHz
MIN MAX
(NOTE 1)
GROUP A
SUBGROUP
PARAMETER
NOTES:
1. VCC = 4.5V and 5.5V unless otherwise specified. CLK loading: CL = 100pF.
SYMBOL
CONDITIONS
TEMPERATURE
UNITS
2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2.
The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to GND, and 15pF from pin X2 to GND; for
CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND, and 15pF from X2 to GND. These recom-
mended values are ±5pF and include all stray capacitance. Decouple VCC and GND as close to the 80C284/883 as possible.
3. This is an asychronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge.
4. The pull-up resistor value for the READY pin is 620Ω with the rated 150pF load.
5. t16 refers to any allowable CLK period.
6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 re-
quirements.
7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES active, and to 4.2V on the RES waveform for RES inactive.
8. Input test waveform characteristics: VIL= 0.0V, VIH = 4.5V.
TABLE 3. 82C284/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
10MHz
12MHz
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
o
Input Capacitance
CIN
FREQ = 1MHz, All
measurementsare
referenced to de-
vice GND
1
T
= +25 C
-
10
-
10
pF
A
o
o
EFI HIGH to CLK
LOW Delay
t15A
t15B
t19
1, 2
1, 3
1
-55 C ≤ T ≤ +125 C
-
-
-
-
-
30
35
8
-
-
-
-
-
25
30
8
ns
ns
ns
ns
ns
A
o
o
EFI LOW to CLK
HIGH Delay
-55 C ≤ T ≤ +125 C
A
o
o
CLK Rise Time
CLK Fall Time
1.0V to 3.6V,
CL = 100pF
-55 C ≤ T ≤ +125 C
A
o
o
t20
3.6V to 1.0V,
CL = 100pF
1
-55 C ≤ T ≤ +125 C
8
8
A
o
o
X1 HIGH to CLK
NOTES:
t27
1, 4
-55 C ≤ T ≤ +125 C
35
30
A
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
2. Measured from 3.2V on the EFI waveform to 1.0V on the CLK.
3. Measured from 0.8V on the EFI waveform to 3.6V on the CLK.
4. Measured from 3.6V on the X1 input to 3.6V on the CLK.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
SUBGROUPS
-
Interim Test
1, 7, 9
4
82C284/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
100%
SUBGROUPS
1
PDA
Final Test
Group A
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
-
Groups C & D
Samples/5005
A.C. Test Conditions
TEST CONDITION
RL
CL
VCC
1
2
3
750Ω
620Ω
75pF
150pF
75pF
RL
CL
∞
DEVICE
OUTPUT
A.C. Specifications
3.8V
0.4V
3.2V
EFI INPUT
0.8V
t
(MAX)
DELAY
VCC - 0.4V
0.4V
3.6V
1.0V
3.6V
1.0V
CLK
OUTPUT
t
SETUP
t
HOLD
3.8V
0.4V
3.2V 3.2V
0.8V 0.8V
F/C
INPUT
VCC - 0.4V
0.4V
VCC - 0.8V
0.8V 0.8V
RES
INPUT
2.6V
0.4V
2.0V 2.0V
0.8V 0.8V
OTHER
DEVICE
INPUT
t
(MAX)
DELAY
t
(MIN)
DELAY
2.0V
0.8V
DEVICE
OUTPUT
FIGURE 1. A.C. DRIVE, SETUP, HOLD AND DELAY TIME MEASUREMENT POINTS
5
82C284/883
Timing Waveforms
t
t
16
t
2
1
EFI
t
15B
t
19
t
18
CLK
t
20
t
t
17
15A
FIGURE 2. CLK AS A FUNCTION OF EFI
NOTE: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.
t
16
CLK
t
14
(SEE
NOTE)
t
14
t
13
t
13
RES
t
t
24
24
DEPENDS ON
PREVIOUS
RESET
STATE OF RES
t
22
t
21
READY
NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
FIGURE 3. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN AND SRDY + SRDYEN HIGH
T
T
C
S
φ1
φ2
φ1
φ2
CLK
S1 • S0
t
6
t
5B
t
6
t
23
t
23
t
t
5A
26
UNDEFINED IF THIS IS
FIRST BUS CYCLE
t
25
PCLK
t
9
t
10
SRDY + SRDYEN
NOTE 1
t
12
t
12
t
t
11
11
ARDY + ARDYEN
READY
t
t
21
t
22
21
NOTE 2
NOTES:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
2. If SRDY + SRDYEN or ARDY + ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted
until the falling edge of φ2 of T .
S
FIGURE 4. READY AND PCLK TIMING WITH RES HIGH
6
82C284/883
Timing Waveforms (Continued)
φ1
φ2
φ1
φ2
φ1
φ2
CLK
PCLK
t
7
t
8
F/C
X1
t
27
CLK
φ1
φ2
φ2
φ1
φ2
φ1
PCLK
F/C
t
7
t
8
t
15B
EFI
FIGURE 5. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAMIC FREQUENCY SWITCHING
NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
7
82C284/883
Burn-In Circuit
18 LEAD CERDIP
R1
R1
R1
R1
R1
R1
R1
R1
F7
F5
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VCC
F8
R1
R1
R1
R1
R1
R1
R1
R1
F6
F9
VCC/2
F1
F10
NC
F12
VCC/2
VCC/2
F11
F0
VCC/2
GND
VCC/2
C1
VCC
NOTES:
1. Supply Voltage: VCC = 5.5V, ±0.5V, GND = 0V. Driver Voltage: VIH = 4.5V ± 10%, VIL = 0V
2. Input Voltage Limits: VIL (Max) = 0.4V, VIH (Min) = 2.6V
3. Component Values: R1 = 47kΩ, C1 = 0.1µF (Min)
4. Oven type and frequency requirements microtest, F0 through F12.
5. Approximate current per unit. ICC = 0.3mA.
6. Special requirements:
(a) Electrostatic Discharge Sensitive. Proper precautions must be used when handling units.
(b) All power supplies must be at zero volts when the boards are inserted into the ovens. After insertion, apply VCC first, then activate
the driver power supplies.
7. Oscilloscope measurements: To be on loaded boards before insertion into the oven.
8
Die Characteristics
DIE DIMENSIONS:
63 mils x 69 mils x 19 mils ± 1 mil
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 8kÅ
WORST CASE CURRENT DENSITY:
5
2
2 x 10 A/cm
Metallization Mask Layout
82C284/883
SRDY
ARDY
VCC
ARDYEN
S1
S0
SRDYEN
READY
NC
EFI
F/C
X1
PCLK
RESET
X2
GND
CLK
RES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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