PD70F3714 [RENESAS]

32-BIT SINGLE-CHIP MICROCONTROLLER;
PD70F3714
型号: PD70F3714
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

32-BIT SINGLE-CHIP MICROCONTROLLER

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中文:  中文翻译
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April 1st, 2010  
Renesas Electronics Corporation  
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Preliminary Product Information  
MOS Integrated Circuit  
V850ES/IE2  
32-BIT SINGLE-CHIP MICROCONTROLLER  
DESCRIPTION  
The V850ES/IE2 is a 32-bit single chip microcontroller of the V850ES series. 32-bit CPU, ROM, RAM, timer/counters,  
serial interface, A/D converter, Inverter control function and so on are integrated on a single chip.  
FEATURES  
V850ES core, 32-bit RISC architecture  
Instruction execution time: 50ns(min.) @20MHz , Integrated PLL(x8) circuit  
On-chip FlsahROM , RAM  
Program Memory  
(Flash Memory Size)  
Data Memory  
(RAM Size)  
Type  
Part Number  
64KB  
128KB  
6KB  
6KB  
PD70F3713  
PD70F3714  
Timer:  
16-bit timer (Type TMP)  
16-bit timer (Type TMQ)  
: 4 channels  
: 2 channels  
(The TMQ1(TimerQ1) and the TMQOP1(TMQ1 option)  
can be used as an inverter control function.  
: 1 channels  
16-bit timer (Type TMM)  
Watchdog timer  
: 1 channel  
Serial interface :  
CSI  
: 1 channel  
: 2 channels  
UART  
A/D converter : 10-bit resolution : 4 channels + 4 channels ( 2ch A/D macro )  
Operation Voltage :  
4.5V to 5.5V: 20MHz max. (OSC=2.5MHz x8)  
3.5V to 5.5V: 20MHz max. (OSC=2.5MHz x8, without A/D converter)  
Package :  
64-pin LQFP (14 x 14mm, 0.8mm pitch)  
Please note: The information in this document is subject to change without notice  
1
Document No. U18131EE1V0PM00 (1st edition)  
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Function Table  
V850ES/IE2  
Device name  
PD 70F3713  
PD 70F3714  
CPU core  
V850ES  
CPU performance  
26MIPS(@20MHz)  
64KB  
6KB  
Internal flash memory  
Internal RAM  
128KB  
6KB  
7
Interrupt Internal  
35  
sources  
External  
16-bit timer(TMP) x 4 ch  
16-bit timer(TMQ) x 2 ch  
16-bit timer(TMM) x 1 ch  
Watchdog timer x 1 ch  
CSI x 1 ch  
Timer/counter  
Serial interface  
A/D converter  
UART x 2 ch  
10-bit x 4ch, 10-bit x 4ch  
39  
Ports  
I/O  
20MHz (Resonator clock 2.5MHz)  
Operating frequency  
Power supply voltage  
4.5 to 5.5V(@20MHz)  
3.5 to 5.5V(@20MHz, without A/D converter)  
64-pin LQFP (14x14mm)  
Package  
Operating ambient  
temperature  
-40C to +85C  
2
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Timer & Serial interface functions overview  
Function  
Overview  
Transfer rate: 5Mbps to 156.25kbps (fxx=20MHz, using internal clock)  
Master mode and slave mode selectable  
8-bit to 16-bit transfer, 3-wire serial interface  
interrupt request signals (INTCB0T, INTCB0R, INTCB0RE)  
Serial clock and data phase switchable  
Transfer data length selectable in 1-bit units between 8 and 16 bits  
Transfer data MSB-first/LSB-first swichable  
CSI  
3-wire transfer SOB0  
SIB0  
: Serial data output  
: Serial data input  
SCKB0 : Serial clock input/output  
Transmission mode, reception mode, and transmission/reception  
mode specifiable  
Transfer rate : 1.25Mbps to 300bps (using internal system clock of 20MHz and  
dedicated baud rate generator)  
Full-duplex commucication: Internal UARTAn receive data register(UAnRX)  
Internal UARTAn transmit data register(UAnTX)  
2-pin configuration: TXDAn: Transmit data output pin  
RXDAn: Receive data input pin  
UART  
Interrupt sources: 3  
Reception complete interrupt(INTUAnR):  
This interrupt occurs upon transfer of receive data from the receive  
shift register to receive data register after serial transfer completion,  
in the reception enabled status.  
Transmission enable interrupt(INTUAnT):  
This interrupt occurs upon transfer of transmit data from the transmit  
data register to the transmit shift register in the transmission enabled  
status.  
Reception error interrupt(INTUAnRE)  
Parity error  
Framing error  
Overrun error  
Character length: 7, 8 bits  
Parity function: Odd, even, 0, none  
Transmission stop bit: 1, 2 bits  
On-chip dedicated baud rate generator  
MSB-/LSB-first transfer selectable  
Transmit/receive data inverted input/output possible  
Remark n = 0 to 1  
16-bit timer/event  
counter (TMP0)  
Clock selection: 8 ways  
Capture trigger input pins: 2  
External event count input pins: 1  
External trigger input pins: 1  
Timer/counters: 1  
Capture/compare registers: 2  
Capture/compare match interrupt request signals: 2  
Timer output pins: 2  
TMP0 has the following functions.  
Interval timer  
External event counter  
External trigger pulse output  
One-shot pulse output  
PWM output  
Free-running timer  
Pulse width Pulse width measurement  
3
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Timer & Serial interface functions overview  
Function  
Overview  
16-bit timer counter  
(TMP1)  
Clock selection: 8 ways  
Capture trigger input pins: non  
External event count input pins: non  
External trigger input pins: non  
Timer/counters: 1  
Compare registers: 2  
Compare match interrupt request signals: 2  
Timer output pins: non  
TMP1 has the following functions.  
Interval timer  
Free-running timer  
Timer tuning operation function (tunable with TMQ1)  
16-bit timer/event  
counter (TMP2)  
Clock selection: 8 ways  
Capture trigger input pins: 2  
External event count input pins: 1  
External trigger input pins: 1  
Timer/counters: 1  
Capture/compare registers: 2  
Capture/compare match interrupt request signals: 2  
Timer output pins: 1  
TMP0 has the following functions.  
Interval timer  
External event counter  
External trigger pulse output  
One-shot pulse output  
PWM output  
Free-running timer  
Pulse width Pulse width measurement  
16-bit timer counter  
(TMP3)  
Clock selection: 8 ways  
Capture trigger input pins: non  
External event count input pins: non  
External trigger input pins: non  
Timer/counters: 1  
Compare registers: 2  
Compare match interrupt request signals: 2  
Timer output pins: 1  
TMP0 has the following functions.  
Interval timer  
External event counter  
External trigger pulse output with software  
One-shot pulse output with software  
PWM output  
Free-running timer  
4
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Timer & Serial interface functions overview  
16-bit timer/event  
counter (TMQ0)  
Clock selection: 8 ways  
Capture/trigger input pins: 4  
External event count input pins: 1  
External trigger input pins: non  
Timer/counters: 1  
Capture/compare registers: 4  
Capture/compare match interrupt request signals: 4  
Timer output pins: 4  
TMQ0 has the following functions.  
Interval timer  
External event counter  
External trigger pulse output  
One-shot pulse output  
PWM output  
Free-running timer  
Pulse width measurement  
16-bit timer counter  
(TMQ1)  
Clock selection: 8 ways  
Capture/trigger input pins: non  
External event count input pins: non  
External trigger input pins: non  
Timer/counters: 1  
Compare registers: 4  
Compare match interrupt request signals: 4  
Timer output pins: 1  
TMQ1 has the following functions.  
6phase PWM output ( with TMQOP1)  
Interval timer  
Free-running timer  
16-bit interval timer  
(TMM)  
Interval function  
8 clocks selectable  
16-bit counter x 1  
(The 16-bit counter cannot be read during timer count operation.)  
Compare register x 1  
(The compare register cannot be written during timer counter operation.)  
Compare match interrupt x 1  
Default-stop watchdog timer  
Watchdog timer  
(WDT)  
Reset mode: Reset operation upon overflow of watchdog timer  
(generation of WDTRES signal)  
Non-maskable interrupt request mode: NMI operation upon overflow  
of watchdog timer (generation of INTWDT signal)  
Inverter control  
function  
(TMQOP1  
:TMQ option)  
The TMQ1 and the TMQOP1 can be used as an inverter control function.  
6-phase PWM output function with 16-bit accuracy (with dead-timer, for  
upper and lower arms)  
Timer tuning operation function (tunable with TMP1)  
Cycle setting function (cycle can be changed during operation of crest  
or valley interrupt)  
Compare register rewriting: Anytime rewrite, batch rewrite, or  
intermittent rewrite (selectable during TMQ1 operation)  
Interrupt and transfer culling functions  
A/D trigger timing function of A/D converters 0 and 1  
0% output and 100% output available  
Forced output stop function  
At valid edge detection by external pin input  
At main clock oscillation stop detection by clock monitor function  
5
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Other functions overview  
Function  
A/D converter  
Overview  
Two 10-bit resolution A/D converter circuits (A/D converters 0 and 1)  
Simultaneous sampling of two circuits possible  
A/D converter 0: ANI00 to ANI03 (4 channels)  
A/D converter 1: ANI10 to ANI13 (4 channels)  
A/D conversion result registers 0m and 1m  
(ADA0CRm and ADA1CRm)  
A/D conversion trigger mode  
Software trigger mode  
Hardware trigger mode  
External trigger mode  
Timer trigger mode  
Operating voltage range  
VDD = EVDD = AVDDn = AVREFn = 4.5 to 5.5 V  
Remark m = 0 to 3, n = 0, 1  
Interrupts  
Interrupt/exception  
processing  
Non-maskable interrupts: 1 sources (Internal)  
Maskable interrupts: External: 7, Internal: 35 sources  
8 levels of programmable priorities (maskable interrupts)  
Multiple interrupt control according to priority  
Masks can be specified for each maskable interrupt request.  
Exceptions  
Software exceptions: 32 sources  
Exception trap: 2 sources (illegal op code exception and debug trap)  
The power consumption of the system can be effectively reduced by using  
the standby modes in combination and selecting the appropriate mode for  
the application.  
Standby modes  
HALT mode: Mode to stop only the operating clock of the CPU  
IDLE mode: Mode to stop all the operations of the internal circuits  
except the oscillator and PLL.  
STOP mode: Mode to stop all the operations of the internal circuits  
except the oscillator.  
Clock monitor The clock monitor samples the main clock by using the internal oscillation  
clock and generates a reset request signal and turn to the 6-phase PWM  
output ports and TOP21 when oscillation of the main clock is stopped.  
Low-voltage  
Detector (LVI)  
Compares the supply voltage (VDD) and detected voltage (VLVI) and  
generates an internal interrupt signal or internal reset signal when VDD <  
VLVI.  
The level of the supply voltage to be detected can be changed by software  
(in two steps).  
Interrupt or reset signal can be selected by software.  
Can operate in STOP mode.  
6
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Pin configuration (TOP VIEW)  
64-pin plastic LQFP (14 x 14 mm, 0.8mm pitch)  
PD70F3713GC-8BS-A  
PD70F3714GC-8BS-A  
Top View  
Notes The CLMER signal is enabled only when P16 is specified as an output port or the output  
function of TOQ00. When an error (oscillator stop) is detected by the clock monitor, a low  
level is forcibly output. Low-level output is released by reset signal.  
7
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
List of Pin Functions  
(1) Port pins  
Pin Name  
Pin No.  
I/O  
Function  
Alternate Function  
INTP0/TOQH0OFF  
P00  
17  
I/O  
Port 0  
7-bit I/O port  
P01  
P02  
P03  
P04  
P05  
P06  
P10  
P11  
P12  
P13  
P14  
16  
INTP1/TOQ1OFF  
INTP2/TOP2OFF  
INTP3/TOP3OFF  
INTP4/ADTRG0  
INTP5/ADTRG1  
INTP6  
Input data read/output data write is enabled in 1-bit units.  
Use of an on-chip pull-up resistor can be specified in 1-bit  
units (the on-chip pull-up resistor can be connected only in  
the input mode of the port mode and when the alternate  
function of the pin is used).  
15  
14  
13  
12  
11  
24  
I/O  
Port 1  
TOQH01/TIQ01/TOQ01  
TIQ02/TOQ02  
7-bit I/O port  
23  
Input data read/output data write is enabled in 1-bit units.  
Use of an on-chip pull-up resistor can be specified in 1-bit  
units (the on-chip pull-up resistor can be connected only in  
the input mode of the port mode, when the input mode of  
alternate function of the pin is used, and when TOP21 and  
TOQH01 to TOQH03 pins, which function as output pins  
when their alternate function is used, go into a  
high-impedance state).  
22  
TOQH02/TIQ03/TOQ03  
TIQ00  
21  
20  
TOQH03/EVTQ0  
TOQ00 (CLMER)Note/TIP20  
P16  
(CLMER)Note  
19  
P17  
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
P30  
P31  
P32  
P33  
18  
54  
53  
52  
51  
50  
49  
46  
45  
44  
43  
42  
41  
TOP21/TIP21  
TOQ1T1  
TOQ1B1  
TOQ1T2  
TOQ1B2  
TOQ1T3  
TOQ1B3  
TOQ10  
I/O  
Port 2  
8-bit I/O port  
Input data read/output data write is enabled in 1-bit units.  
Use of an on-chip pull-up resistor can be specified in 1-bit  
units (the on-chip pull-up resistor can be connected only in  
the input mode of the port mode, or when TOQ1T1 to  
TOQ1T3 and TOQ1B1 to TOQ1B3 and TOP31 pins, which  
function as output pins when their alternate function is used,  
go into a high-impedance state).  
TOP31  
I/O  
Port 3  
RXDA0  
4-bit I/O port  
TXDA0  
Input data read/output data write is enabled in 1-bit units.  
Use of an on-chip pull-up resistor can be specified in 1-bit  
units (the on-chip pull-up resistor can be connected only in  
the input mode of the port mode and when the input mode of  
the alternate function of the pin is used).  
RXDA1  
TXDA1  
PDL0  
PDL1  
PDL2  
PDL3  
PDL4  
PDL5  
PDL6  
PDL7  
35  
34  
33  
32  
31  
30  
29  
28  
I/O  
Port DL  
8-bit I/O port  
Input data read/output data write is enabled in 1-bit units.  
An on-chip pull-up resistor can be specified in 1-bit units  
(the on-chip pull-up resistor can be connected when the  
pins are in the port mode and input mode).  
FLMD1  
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of TOQ00.  
When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output. Low-level  
output is released by reset signal.  
8
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
(2) Non-port pins  
Pin Name  
ADTRG0  
ADTRG1  
ANI00  
Pin No.  
I/O  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Function  
Alternate Function  
INTP4/P04  
INTP5/P05  
13  
12  
1
External trigger input for A/D converters 0, 1  
Analog input to A/D converters 0, 1  
2
ANI01  
3
ANI02  
4
ANI03  
58  
57  
56  
55  
63  
60  
64  
59  
62  
61  
ANI10  
ANI11  
ANI12  
ANI13  
AVDD0  
Positive power supply for A/D converters 0, 1 (same  
potential as VDD)  
AVDD1  
AVREF0  
AVREF1  
AVSS0  
Reference voltage input for A/D converters 0, 1 (same  
potential as AVDD0 and AVDD1)  
Ground potential for A/D converters 0, 1 (same potential  
as VSS)  
AVSS1  
26, 47  
27, 48  
20  
EVDD  
Positive power supply for external pin  
Ground potential for external pin  
EVSS  
EVTQ0  
FLMD0  
FLMD1  
INTP0  
Input  
Input  
Input  
Input  
External event count input of TMQ0  
Pin for setting flash memory programming mode  
TOQH03/P14  
25  
30  
PDL5  
17  
External maskable interrupt request input  
TOQH0OFF/P00  
INTP1  
16  
TOQ1OFF/P01  
INTP2  
15  
TOP2OFF/P02  
INTP3  
14  
TOP3OFF/P03  
INTP4  
13  
ADTRG0/P04  
INTP5  
12  
ADTRG1/P05  
INTP6  
11  
P06  
REGC  
RESET  
RXDA0  
RXDA1  
SCKB0  
SIB0  
10  
Regulator output stabilization capacitance connection  
System reset input  
5
Input  
Input  
44  
Serial receive data input of UARTA0, UARTA1  
P30  
P32  
P42  
P40  
P41  
42  
38  
I/O  
Serial clock I/O of CSIB0  
40  
Input  
Serial receive data input of CSIB0  
Serial transmit data output of CSIB0  
SOB0  
39  
Output  
9
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  
Preliminary Product Information  
Pin Name  
TIP00  
Pin No.  
37  
I/O  
Function  
Alternate Function  
TOP00/P43  
Input  
External timer trigger input of TMP0, TMP2  
TIP01  
TIP20  
36  
TOP01/P44  
19  
TOQ00 (CLMER)Note  
P16 (CLMER)Note  
/
TIP21  
18  
21  
24  
23  
22  
37  
36  
18  
15  
45  
14  
19  
24  
23  
22  
46  
53  
51  
49  
16  
54  
52  
50  
24  
22  
20  
17  
43  
41  
9
TOP21/P17  
TIQ00  
Input  
External timer trigger input of TMQ0  
Pulse signal output of TMP0, TMP2  
P13  
TIQ01  
TOQH01/TOQ01/P10  
TIQ02  
TOQ02/P11  
TIQ03  
TOQH02/TOQ03/P12  
TOP00  
Output  
TIP00/P43  
TOP01  
TIP01/P44  
TOP21  
TIP21/P17  
TOP2OFF  
TOP31  
Input  
Output  
Input  
High-impedance output control signal input  
Pulse signal output of TMP3  
INTP2/P02  
P27  
TOP3OFF  
TOQ00 (CLMER)Note  
TOQ01  
TOQ02  
TOQ03  
TOQ10  
TOQ1B1  
TOQ1B2  
TOQ1B3  
TOQ1OFF  
TOQ1T1  
TOQ1T2  
TOQ1T3  
TOQH01  
TOQH02  
TOQH03  
TOQH0OFF  
TXDA0  
TXDA1  
VDD  
High-impedance output control signal input  
Pulse signal output of TMQ0  
INTP3/P03  
Output  
TIP20/P16 (CLMER)Note  
TOQH01/TIQ01/P10  
TIQ02/P11  
TOQH02/TIQ03/P12  
Output  
Output  
Pulse signal output of TMQ1  
P26  
Pulse signal output for 6-phase PWM  
P21  
P23  
P25  
Input  
High-impedance output control signal input  
Pulse signal output for 6-phase PWM  
INTP1/P01  
Output  
P20  
P22  
P24  
Output  
High-impedance output by TMQ0 pulse signal output and  
valid edge of TOQH0OFF pin input  
TIQ01/TOQ01/P10  
TIQ03/TOQ03/P12  
EVTQ0/P14  
Input  
High-impedance output control signal input  
INTP0/P00  
Output  
Serial transmit data output of UARTA0, UARTA1  
P31  
P33  
Positive power supply for internal unit  
Ground potential for internal unit  
VSS  
8
X1  
6
Input  
Crystal connection pin for system clock oscillation  
X2  
7
Note The CLMER signal is enabled only when P16 is specified as an output port or the output function of TOQ00.  
When an error (oscillator stop) is detected by the clock monitor, a low level is forcibly output. Low-level  
output is released by reset signal.  
10  
V850ES/IE2 PPI (Ver. 1.0)  
NEC Electronics Corporation November 2005  

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