PD78F9232CS [RENESAS]
8-BIT SINGLE-CHIP MICROCONTROLLERS;
| 型号： | PD78F9232CS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 文件： | 总30页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics document. We appreciate your understanding.
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ
PD78F9232CS, 78F9234CS
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µ PD78F9232CS, 78F9234CS are 8-bit single-chip microcontrollers of the 78K0S microcontrollers.
These microcontrollers feature Single-voltage Self-programming Flash memory and many peripherals.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
78K0S/KB1+ User’s Manual:
U17446E
78K/0S Series Instruction User's Manual: U11047E
FEATURES
{Minimum instruction execution time selectable from high speed (0.2 µs) to low speed (3.2 µs) (with CPU clock of
10 MHz)
{General-purpose registers: 8 bits × 8 registers
{ROM and RAM capacities
Item
Program Memory (Flash Memory)
Memory (Internal High-Speed RAM)
Part number
µPD78F9232CS
µPD78F9234CS
4 KB
8 KB
256 bytes
{On-chip power-on clear (POC) circuit and low voltage detector (LVI)
{On-chip watchdog timer (operable on internal low-speed internal oscillator clock)
{I/O ports: 26
{Timer: 4 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer:
• Watchdog timer:
2 channels
1 channel
{Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel
{Multiplier: 8 bits × 8 bits = 16 bits
{10-bit resolution A/D converter: 4 channels
{Supply voltage: VDD = 2.0 to 5.5 VNote
{Operating temperature range: TA = −40 to +85°C
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
2006
Document No. U18550EJ2V0PM00 (2nd edition)
Date Published June 2007 NS CP(K)
Printed in Japan
µPD78F9232CS, 78F9234CS
APPLICATIONS
Household appliances, toys, and industrial equipment
ORDERING INFORMATION
Part Number
Package
µPD78F9232CS-CAA-A
µPD78F9234CS-CAA-A
32-pin plastic SDIP (7.62 mm (300))
32-pin plastic SDIP (7.62 mm (300))
Remark Products with -A at the end of the part number are lead-free products.
2
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
OVERVIEW OF FUNCTIONS
Item
µPD78F9232CS
µPD78F9234CS
Internal
memory
Flash memory
4 KB
8 KB
High-speed RAM
256 bytes
64 KB
Memory space
X1 input clock (oscillation frequency)
Crystal/ceramic/external clock input:
10 MHz (VDD = 2.0 to 5.5 V)
Internal
High speed (oscillation
Internal oscillation: 8 MHz (TYP.)
Internal oscillation: 240 kHz (TYP.)
8 bits × 8 registers
oscillation frequency)
clock
Low speed (for TMH1
and WDT)
General-purpose registers
Instruction execution time
Multiplier
0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (X1 input clock: fX = 10 MHz)
8 bits × 8 bits = 16 bits
I/O port
Total:
26 pins
24 pins
1 pin
CMOS I/O:
CMOS input:
CMOS output:
1 pin
Timer
• 16-bit timer/event counter: 1 channel
• 8-bit timer (timer H1):
• 8-bit timer (timer 80):
• Watchdog timer:
1 channel
1 channel
1 channel
Timer output
2 pins (PWM: 1 pin)
A/D converter
Serial interface
10-bit resolution × 4 channels
LIN-bus-supporting UART mode: 1 channel
Vectored
External
Internal
4
9
interrupt sources
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on clear
• Internal reset by low-voltage detector
VDD = 2.0 to 5.5 VNote
Supply voltage
Operating temperature range
Package
TA = −40 to +85°C
32-pin plastic SDIP
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on- clear
(POC) circuit is 2.1 V 0.1 V.
3
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
PIN CONFIGURATION (Top View)
•
32-pin plastic SDIP
P23/ANI3
P22/ANI2
P21/ANI1
P20/ANI0
AVREF
AVSS
1
P130
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
P47
3
P46
4
P45
5
P44/RxD6
P43/TxD6/INTP1
P42/TOH1
P41/INTP3
P40
6
AVSS
7
P120
8
P03
9
P02
10
11
12
13
14
15
16
P30/TI00/INTP0
P31/TI010/TO00/INTP2
P32
P01
P00
P123
P33
V
V
SS
RESET/P34
P122/X2
P121/X1
SS
V
DD
Caution Connect the AVSS pin to VSS.
ANI0 to ANI3:
AVREF:
Analog input
P130:
Port 13
Analog reference voltage
Analog ground
External interrupt input
Port 0
RESET:
RxD6:
Reset
AVSS:
Receive data
Timer input
INTP0 to INTP3:
P00 to P03:
P20 to P23:
P30 to P34:
P40 to P47:
P120 to P123:
TI000, TI010:
TO00, TOH1:
TxD6:
Timer output
Transmit data
Power supply
Ground
Port 2
Port 3
VDD:
Port 4
VSS:
Port 12
X1, X2:
Crystal oscillator (X1 input clock)
4
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
BLOCK DIAGRAM
TO00/TI010/P31
TI000/P30
4
PORT 0
PORT 2
PORT 3
PORT 4
P00-P03
P20-P23
16-bit TIMER/
EVENT COUNTER 00
4
4
8-bit TIMER 80
8-bit TIMER H1
P30-P33
P34
TOH1/P42
78K0S
CPU
CORE
FLASH
MEMORY
LOW-SPEED
INTERNAL
OSCILLATOR
8
4
P40-P47
P120-P123
P130
PORT 12
PORT 13
WATCHDOG TIMER
RxD6/P44
TxD6/P43
SERIAL
INTERFACE UART6
INTERNAL
HIGH-SPEED
RAM
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
ANI0/P20-
4
ANI3/P23
A/D CONVERTER
AVREF
AVSS
RESET CONTROL
INTP0/P30
INTP1/P43
INTP2/P31
INTP3/P41
INTERRUPT
CONTROL
RESET/P34
X1/P121
SYSTEM
CONTROL
X2/P122
HIGH-SPEED
INTERNAL
OSCILLATOR
MULTIPLIER
VDD
VSS
5
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
CONTENTS
1. PIN FUNCTIONS.................................................................................................................................. 7
1.1 Port Functions............................................................................................................................................. 7
1.2 Non-port Functions..................................................................................................................................... 8
1.3 Pin I/O Circuits and Connection of Unused Pins ..................................................................................... 9
2. ELECTRICAL SPECIFICATIONS (TARGET) ................................................................................... 11
3. PACKAGE DRAWING ....................................................................................................................... 23
APPENDIX A. RELATED DOCUMENTS ................................................................................................. 24
6
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
1. PIN FUNCTIONS
1.1 Port Functions
Pin Name
I/O
Function
After Reset
Input
Alternate-
Function Pin
P00 to P03
I/O
I/O
I/O
Port 0.
−
4-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting software.
P20 to P23
Port 2.
Input
ANI0 to ANI3
4-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting software.
P30
P31
Port 3
Can be set to input or output mode in 1- Input
TI000/INTP0
bit units.
TI010/TO00/
INTP2
An on-chip pull-up resistor can be
connected by setting software.
P32
P33
P34
P40
P41
P42
P43
P44
P45
P46
P47
P120
P121
P122
P123
P130
−
−
Input
I/O
Input only
Input
Input
RESET
Port 4.
−
8-bit I/O port.
INTP3
Can be set to input or output mode in 1-bit units.
TOH1
An on-chip pull-up resistor can be connected by setting software.
TxD6/INTP1
RxD6
−
−
−
I/O
Port 12.
Input
−
4-bit I/O port.
X1
X2
−
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected only to P120 and
P123 by setting software.
Output
Port 13.
Output
−
1-bit output-only port
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
7
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
1.2 Non-port Functions
Pin Name
I/O
Function
After Reset
Input
Alternate-
Function Pin
INTP0
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
P30/TI000
P43/TxD6
P31/TI010/TO00
P41
INTP1
INTP2
INTP3
RxD6
TxD6
Input
Serial data input for asynchronous serial interface
Serial data output for asynchronous serial interface
Input
Input
Input
P44
Output
Input
P43/INTP1
P30/INTP0
TI000
External count clock input to 16-bit timer/event counter 00.
Capture trigger input to capture registers (CR000 and CR010) of
16-bit timer/event counter 00
TI010
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
P31/TO00/INTP2
TO00
Output
Output
Input
−
16-bit timer/event counter 00 output
8-bit timer H1 output
Input
P31/TI010/INTP2
TOH1
ANI0 to ANI3
AVREF
Input
P42
Analog input of A/D converter
Input
P20 to P23
Reference voltage of A/D converter
A/D converter ground potential. Make the same potential as VSS.
System reset input
−
−
−
−
−
−
AVSS
−
RESET
X1
Input
Input
P34
Connection of crystal/ceramic resonator for system clock
P121
oscillation.
External clock input
X2
−
Connection of crystal/ceramic resonator for system clock
oscillation.
−
P122
VDD
VSS
−
−
Positive power supply
Ground potential
−
−
−
−
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
8
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
1.3 Pin I/O Circuits and Connection of Unused Pins
Table 1-1 shows I/O circuit type of each pin and the connections of unused pins.
For the configuration of the I/O circuit of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits and Connection of Unused Pins
Pin Name
P00 to P03
I/O Circuit Type
8-A
I/O
Recommended Connection of Unused Pin
I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P20/ANI0 to P23/ANI3
11
Input: Independently connect to AVREF or VSS via a resistor.
Output: Leave open.
P30/TI000/INTP0
P31/TI010/TO00/INTP2
P32 and P33
P34/RESET
P40
8-A
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
2
Input
I/O
Connect to VDD via a resistor.
8-A
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P41/INTP3
P42/TOH1
P43/TxD6/INTP1
P44/RxD6
P45 to P47
P120
P121/X1
16-B
8-A
Input: Independently connect to VSS via a resistor.
Output: Leave open.
P122/X2
P123
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P130
AVREF
AVSS
3-C
Output
Leave open.
−
−
−
Directly connect to VDD.
Directly connect to VSS.
−
9
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
Figure 1-1. Pin I/O Circuits
V
DD
Type 2
Type 11
Pull up
enable
P-ch
AVREF
P-ch
Data
IN
IN/OUT
Output
disable
N-ch
V
SS
Schmitt-triggered input with hysteresis characteristics
Comparator
P-ch
N-ch
+
-
AVSS
AVREF
(Threshold voltage)
Input
enable
Type 3-C
Type 16-B
Feedback
cut-off
P-ch
V
DD
P-ch
OSC
enable
Data
OUT
X1,
IN/OUT
X2,
IN/OUT
N-ch
V
SS
V
DD
Data
P-ch
Type 8-A
Output
disable
N-ch
V
DD
V
SS
Pull up
enable
P-ch
V
DD
Data
P-ch
N-ch
Data
P-ch
N-ch
IN/OUT
Output
Disable
Output
disable
V
SS
V
SS
10
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
2. ELECTRICAL SPECIFICATIONS (TARGET)
These specifications are only target values, and may not be satisfied by mass-produced products.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
Ratings
−0.3 to +6.5
Unit
V
VDD
VSS
−0.3 to +0.3
V
AVREF
AVSS
VI1
−0.3 to VDD + 0.3Note
V
−0.3 to +0.3
−0.3 to VDD + 0.3Note
V
Input voltage
P00 to P03, P30 to P34, P40 to P47, P120 to
P123
V
VI2
P20 to P23
−0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note
V
Output voltage
VO
−0.3 to VDD + 0.3Note
V
V
Analog input voltage
VAN
−0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note
Output current, high
Output current, low
IOH
IOL
Per pin
−10.0
−44.0
−44.0
20.0
mA
mA
mA
mA
mA
mA
°C
Total of pins other than P20 to P23
Total of P20 to P23
Per pin
Total of pins other than P20 to P23
Total of P20 to P23
44.0
44.0
Operating ambient
temperature
TA
In normal operation mode
During flash memory programming
Flash memory blank status
Flash memory programming already performed
−40 to +85
Storage temperature
Tstg
−65 to +150
−40 to +125
°C
°C
Note Must be 6.5 V or lower
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
11
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
X1 Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V)
Resonator Recommended Circuit Parameter Conditions
MIN.
2.0
TYP. MAX.
10.0
Unit
Ceramic
Oscillation
frequency (fX)Note 2
MHz
VSS X1
X2
resonator
C1
C2
C2
Crystal
Oscillation
frequency (fX)Note 2
2.0
10.0
MHz
V
SS X1
C1
X2
resonator
External
clock
X1 input
2.7 V ≤ VDD ≤ 5.5 V
2.0
2.0
10.0
5.0
MHz
X1
frequency (fX)Note 2
2.0 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
X1 input high-
/low-level width
(tXH, tXL)
0.045
0.09
0.25
0.25
µs
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V 0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
12
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
High-Speed Internal Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V)
Resonator
Parameter
Conditions
2.7 V ≤ VDD ≤ 5.5 V TA = −10 to +80°C
TA = −40 to +85°C
MIN.
TYP. MAX.
Unit
%
High-speed internal Oscillation frequency (fX = 8
3
5
oscillator
MHzNote 2) deviation
%
Oscillation frequency (fX)Note 2
2.0 V ≤ VDD < 2.7 V
5.5
MHz
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V 0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Low-Speed Internal Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote, VSS = 0 V)
Resonator
Parameter
Conditions
MIN.
120
TYP. MAX.
240 480
Unit
kHz
Low-speed internal oscillator
Oscillation frequency (fRL)
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear
(POC) circuit is 2.1 V 0.1 V.
13
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH1
Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V
P20 to P23
Total
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
–25
–15
–5
IOH2
P20 to P23
Per pin 2.0 V ≤ AVREF ≤ 5.5 V
Total 2.0 V ≤ AVREF ≤ 5.5 V
–15
10
Output current, low
IOL1
Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V
P20 to P23
Total
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
30
15
IOL2
P20 to P23
Per pin 2.0 V ≤ AVREF ≤ 5.5 V
10
Total
4.0 V ≤ AVREF ≤ 5.5 V
2.0 V ≤ AVREF < 4.0 V
30
15
Input voltage, high
Input voltage, low
Output voltage, high
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
P00 to P03, P30 to P34, P40 to P47, P120, P123
0.8VDD
VDD
P20 to P23
0.7AVREF
AVREF
VDD
V
P121, P122
0.8VDD
V
P00 to P03, P30 to P34, P40 to P47, P120, P123
0
0.2VDD
0.3AVREF
0.2VDD
V
P20 to P23
P121, P122
0
0
V
V
Total of pins other than
P20 to P23
4.0 V ≤ VDD ≤ 5.5 V
IOH1 = –5 mA
VDD − 1.0
V
IOH1 = –15 mA
IOH1 = –100 µA
2.0 V ≤ VDD < 4.0 V
VDD – 0.5
V
V
VOH2
VOL1
VOL2
Total of pins P20 to P23 4.0 V ≤ AVREF ≤ 5.5 V AVREF – 1.0
IOH2 = –10 mA
IOH2 = –5 mA
2.0 V ≤ AVREF < 4.0 V
IOH2 = –100 µA
AVREF – 0.5
V
V
Output voltage, low
Total of pins other than
P20 to P23
4.0 V ≤ VDD ≤ 5.5 V
IOL1 = 10 mA
1.3
IOL1 = 30 mA
2.0 V ≤ VDD < 4.0 V
IOL1 = 400 µA
0.4
1.3
V
V
Total of pins P20 to P23 4.0 V ≤ AVREF ≤ 5.5 V
IOL2 = 30 mA IOL2 = 10 mA
2.0 V ≤ AVREF < 4.0 V IOL2 = 400 µA
0.4
1
V
Input leakage current, high ILIH
Input leakage current, low
VI = VDD
Pins other than X1
µA
µA
µA
µA
kΩ
kΩ
ILIL
VI = 0 V
Pins other than X1
Pins other than X2
Pins other than X2
–1
1
Output leakage current, high ILOH
Output leakage current, low ILOL
VO = VDD
VO = 0 V
–1
100
100
Pull-up resistance
RPU
RPD
VI = 0 V
10
10
30
30
Pull-down resistance
P121, P122, reset status
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear
(POC) circuit is 2.1 V 0.1 V.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
14
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2)
Parameter Symbol
Conditions
MIN. TYP. MAX. Unit
6.1 12.2 mA
7.6 15.2
Note 3
IDD1
Supply
currentNote 2
Crystal/ceramic
fX = 10 MHz
VDD = 5.0 V 10%Note 4
When A/D converter is stopped
When A/D converter is operatingNote 8
When A/D converter is stopped
When A/D converter is operatingNote 8
When A/D converter is stopped
When A/D converter is operatingNote 8
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
When A/D converter is stopped
When A/D converter is operatingNote 8
oscillation, external
clock input oscillation
operating modeNote 6
fX = 6 MHz
5.5 11.0 mA
14.0
VDD = 5.0 V 10%Note 4
fX = 5 MHz
3.0
4.5
1.7
6.0
9.0
3.8
6.7
3.0
6.0
1
mA
mA
mA
mA
VDD = 3.0 V 10%Note 5
IDD2
Crystal/ceramic
oscillation, external
clock input HALT
modeNote 6
fX = 10 MHz
VDD = 5.0 V 10%Note 4
fX = 6 MHz
1.3
VDD = 5.0 V 10%Note 4
fX = 5 MHz
0.48
VDD = 3.0 V 10%Note 5
2.1
Note 3
IDD3
IDD4
IDD5
High-speed internal
oscillation operating
modeNote 7
fX = 8 MHz
5.0 10.0 mA
6.5 13.0
VDD = 5.0 V 10%Note 4
High-speed internal
oscillation HALT
modeNote 7
fX = 8 MHz
When peripheral functions are stopped
When peripheral functions are operating
1.4
3.2
5.9
mA
VDD = 5.0 V 10%Note 4
STOP mode
VDD = 5.0 V 10%
VDD = 3.0 V 10%
When low-speed internal
oscillation is stopped
3.5 20.0 µA
17.5 32.0
When low-speed internal
oscillation is operating
When low-speed internal
oscillation is stopped
3.5 15.5 µA
11.0 26.0
When low-speed internal
oscillation is operating
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V 0.1 V.
2. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
3. Peripheral operation current is included.
4. When the processor clock control register (PCC) is set to 00H.
5. When the processor clock control register (PCC) is set to 02H.
6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using
the option byte.
7. When the high-speed internal oscillation clock is selected as the system clock source using the option
byte.
8. The current that flows through the AVREF pin is included.
15
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
0.2
TYP.
MAX.
16
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Cycle time (minimum
TCY
Crystal/ceramic oscillation
4.0 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.0 V
2.0 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
2.0 V ≤ VDD < 2.7 V
instruction execution time)
clock, external clock input
0.33
0.4
16
16
1
16
High-speed internal
oscillation clock
0.23
0.47
0.95
4.22
4.22
4.22
TI000/TI010 input high-level tTIH,
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
2/fsam+
0.1Note 2
width, low-level width
tTIL
2/fsam+
0.2Note 2
µs
µs
Interrupt input high-level
width, low-level width
tINTH,
tINTL
tRSL
1
RESET input low-level
width
2
µs
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V 0.1 V.
2. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode register 00 (PRM00). Note that when selecting the TI000 or TI010 valid edge as the count clock,
fsam = fXP.
CPU Clock Frequency, Peripheral Clock Frequency
Parameter
Ceramic resonator,
Crystal resonator,
External clock
Conditions
CPU clock (fCPU)
125 kHz ≤ fCPU ≤ 10 MHz
125 kHz ≤ fCPU ≤ 6 MHz
125 kHz ≤ fCPU ≤ 5 MHz
125 kHz ≤ fCPU ≤ 2 MHz
Peripheral clock (fXP)
500 kHz ≤ fXP ≤ 10 MHz
4.0 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.0 V
2.0 V ≤ VDD < 2.7 VNote
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
2.0 V ≤ VDD < 2.7 VNote
500 kHz ≤ fXP ≤ 5 MHz
High-speed internal
oscillator
500 kHz (Typ.) ≤ fCPU ≤ 8 MHz (Typ.) 2 MHz (Typ.) ≤ fXP ≤ 8 MHz (Typ.)
500 kHz (Typ.) ≤ fCPU ≤ 4 MHz (Typ.)
500 kHz (Typ.) ≤ fCPU ≤ 2 MHz (Typ.) 2 MHz (Typ.) ≤ fXP ≤ 4 MHz (Typ.)
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear
(POC) circuit is 2.1 V 0.1 V.
16
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input)
60
16
10
µ
Guaranteed
operation range
1.0
0.4
0.33
0.1
1
2
3
4
5
6
2.7
Supply voltage VDD [V]
5.5
TCY vs. VDD (High-speed internal oscillator Clock)
60
10
µ
4.22
Guaranteed
operation range
1.0
0.95
0.47
0.23
0.1
1
2
3
4
5
6
2.7
Supply voltage VDD [V]
5.5
17
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
(2) Serial interface (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote, VSS = 0 V)
UART mode (UART6, dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
312.5
Unit
kbps
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear
(POC) circuit is 2.1 V 0.1 V.
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/f
X
t
XL
t
XH
X1 input
TI000 Timing
t
TIL
tTIH
TI000
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
18
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Overall errorNotes 1, 2
AINL
4.0 V ≤ AVREF ≤ 4.5 V
0.2
0.3
0.4
%FSR
%FSR
µs
2.7 V ≤ AVREF < 4.0 V
4.5 V ≤ AVREF ≤ 5.5 V
4.0 V ≤ AVREF < 4.5 V
2.85 V ≤ AVREF < 4.0 V
2.7 V ≤ AVREF < 2.85 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
0.6
Conversion time
tCONV
3.0
4.8
100
100
100
100
0.4
µs
6.0
µs
14.0
µs
Zero-scale errorNotes 1, 2
Ezs
Efs
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
0.6
Full-scale errorNotes 1, 2
0.4
0.6
Integral non-linearity errorNote 1
Differential non-linearity errorNote 1
Analog input voltage
ILE
2.5
4.5
DLE
VAIN
1.5
2.0
VSS
AVREF
Notes 1. Excludes quantization error ( 1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
Caution The conversion accuracy may be degraded if the level of a port that is not used for A/D conversion
is changed during A/D conversion.
19
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
POC Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VPOC
Conditions
MIN.
2.0
TYP.
2.1
MAX.
2.2
Unit
V
Power supply boot time
tPTH
VDD: 0 V → 2.1 V
1.5
µs
Response delay time 1Note 1
tPTHD
When power supply rises, after reaching
detection voltage (MAX.)
3.0
1.0
ms
Response delay time 2Note 2
Minimum pulse width
tPD
ms
ms
When power supply falls
tPW
0.2
Notes 1. Time required from voltage detection to internal reset release.
2. Time required from voltage detection to internal reset signal generation.
POC Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
t
PW
t
PTH
t
PTHD
t
PD
Time
20
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
LVI Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VLVI0
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
VLVI8
VLVI9
tLD
Conditions
MIN.
4.1
TYP.
4.3
MAX.
4.5
Unit
V
3.9
4.1
4.3
V
3.7
3.9
4.1
V
3.5
3.7
3.9
V
3.3
3.5
3.7
V
3.15
2.95
2.7
3.3
3.45
3.25
3.0
V
3.1
V
2.85
2.6
V
2.5
2.7
V
2.25
2.35
0.2
2.45
2.0
V
Response timeNote 1
ms
ms
ms
Minimum pulse width
tLW
0.2
Operation stabilization wait timeNote 2
tLWAIT
0.1
0.2
Notes 1. Time required from voltage detection to interrupt output or internal reset signal generation.
2. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9
2. VPOC < VLVIm (m = 0 to 9)
LVI Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
t
LWAIT
tLD
LVION
1
Time
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Symbol
VDDDR
tSREL
Conditions
MIN.
2.0
0
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
Release signal set time
µs
21
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
Flash Memory Programming Characteristics (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD
Conditions
MIN.
TYP.
MAX.
7.0
Unit
mA
Supply current
VDD = 5.5 V
Erasure countNote 1
(per 1 block)
NERASE
TA = −40 to +85°C
1000
Times
Chip erase time
TCERASE
TA = −10 to +85°C,
NERASE ≤ 100
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
0.8
1.0
1.2
4.8
5.2
6.1
1.6
1.8
2.0
9.1
10.1
12.3
0.4
0.5
0.6
2.6
2.8
3.3
0.9
1.0
1.1
4.9
5.4
6.6
150
6.8
27
s
s
s
TA = −10 to +85°C,
NERASE ≤ 1000
s
s
s
TA = −40 to +85°C,
NERASE ≤ 100
s
s
s
TA = −40 to +85°C,
NERASE ≤ 1000
s
s
s
Block erase time
TBERASE
TA = −10 to +85°C,
NERASE ≤ 100
s
s
s
TA = −10 to +85°C,
NERASE ≤ 1000
s
s
s
TA = −40 to +85°C,
NERASE ≤ 100
s
s
s
TA = −40 to +85°C,
NERASE ≤ 1000
s
s
s
Byte write time
Internal verify
TWRITE
TVERIFY
TA = −40 to +85°C, NERASE ≤ 1000
Per 1 block
µs
ms
µs
µs
Years
Per 1 byte
Blank check
TBLKCHK
Per 1 block
480
Retention years
TA = 85°CNote 2, NERASE ≤ 1000
10
Note 1. Depending on the erasure count (NERASE), the erase time varies. Refer to the chip erase time and block
erase time parameters.
2. When the average temperature when operating and not operating is 85°C.
Remark When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite.
22
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
3. PACKAGE DRAWING
32-PIN PLASTIC SDIP (7.62mm(300))
D
17
32
E
16
1
B
A
A2
e1
C
e
c
Z
A
θ
b2
A1
b1
b
M
x
C
A B
(UNIT:mm)
L
ITEM DIMENSIONS
28.05 0.15
6.60 0.20
3.45 0.15
0.65 0.10
2.80
D
E
A
A1
A2
e
1.778
e1
7.62
0.50
0.10
b
1.02 0.10
b1
0.75 0.10
b2
c
+ 0.10
0.25
0.05
2.86
0.25
0.20
L
x
θ
to 15°
0°
Z
0.615
P32CS-70-CAA
23
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
APPENDIX A. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
µ PD78F9232CS, 78F9234CS Preliminary Product Information
78K0S/KB1+ User’s Manual
Document No.
This manual
U17446E
78K/0S Series Instructions User’s Manual
U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U16656E
U14877E
U11623E
U16654E
U14872E
U16584E
U17287E
U16934E
RA78K0S Assembler Package
Operation
Language
Structured Assembly Language
Operation
CC78K0S C Compiler
Language
ID78K0S-NS Ver. 2.52 Integrated Debugger
ID78K0S-QB Ver. 2.81 Integrated Debugger
PM plus Ver. 5.20
Operation
Operation
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
U13549E
IE-78K0S-NS In-Circuit Emulator
IE-78K0S-NS-A In-Circuit Emulator
U15207E
QB-78K0SKX1MINI In-Circuit Emulator
QB-78K0SKX1 In-Circuit Emulator
U17272E
U17219E
QB-MINI2 On-Chip Debug Emulator with Programming Function
U18371E
Documents Related to Flash Memory Writing (User’s Manuals)
Document Name
Document No.
U15260E
PG-FP4 Flash Memory Programmer
PG-FPL2 Flash Memory Programmer
U17307E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
24
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
Other Related Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
25
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
26
Preliminary Product Information U18550EJ2V0PM
µ PD78F9232CS, 78F9234CS
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, inc.
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
• Not all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics product before using it in a particular application.
•
•
•
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5D 02. 11-1
27
Preliminary Product Information U18550EJ2V0PM
µPD78F9232CS, 78F9234CS
For further information,
please contact:
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[Asia & Oceania]
[America]
[Europe]
NEC Electronics (China) Co., Ltd
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
Tel: 010-8235-1155
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
http://www.cn.necel.com/
800-366-9782
http://www.eu.necel.com/
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NEC Electronics Shanghai Ltd.
Room 2511-2512, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai P.R. China P.C:200120
Tel: 021-5888-5400
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30177 Hannover
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81829 München
Tel: 0 89 92 10 03-0
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193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: 2886-9318
Stuttgart Office
Industriestrasse 3
70565 Stuttgart
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Tel: 0 711 99 01 0-0
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http://www.tw.necel.com/
United Kingdom Branch
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NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
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Tel: 6253-8311
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Succursale Française
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France
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Sucursal en España
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
NEC Electronics Korea Ltd.
11F., Samik Lavied’or Bldg., 720-2,
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Seoul, 135-080, Korea
Tyskland Filial
Täby Centrum
Tel: 02-558-3737
Entrance S (7th floor)
18322 Täby, Sweden
Tel: 08 638 72 00
http://www.kr.necel.com/
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The Netherlands
Tel: 040 265 40 10
G07.1A
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