R1LP0108ESA-7SI#S [RENESAS]

STANDARD SRAM;


型号：	R1LP0108ESA-7SI#S
厂家：	RENESAS TECHNOLOGY CORP
描述：	STANDARD SRAM 存储内存集成电路静态存储器光电二极管
文件：	总14页 (文件大小：196K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R1LP0108E Series

1Mb Advanced LPSRAM (128k word x 8bit)

R10DS0151EJ0100

Rev.1.00

2013.6.21

Description

The R1LP0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated

by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP0108E Series has realized higher

density, higher performance and low power consumption. The R1LP0108E Series is suitable for memory applications

where a simple interfacing, battery operating and battery backup are the important design objectives. It has been

packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP.

Features



Single 4.5~5.5V power supply

Small stand-by current: 0.6µA (5.0V, typical)

No clocks, No refresh

All inputs and outputs are TTL compatible.

Easy memory expansion by CS1# and CS2

Common Data I/O

Three-state outputs: OR-tie Capability

OE# prevents data contention on the I/O bus

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 1 of 12

R1LP0108E Series

Ordering Information

Access Temperature

Shipping

Container

Orderable Part Name

Package

Quantity

time

Range

R1LP0108ESN-5SR#B*

R1LP0108ESN-5SI#B*

R1LP0108ESN-7SR#B*

R1LP0108ESN-7SI#B*

R1LP0108ESN-5SR#S*

R1LP0108ESN-5SI#S*

R1LP0108ESN-7SR#S*

R1LP0108ESN-7SI#S*

R1LP0108ESA-5SR#B*

R1LP0108ESA-5SI#B*

R1LP0108ESA-7SR#B*

R1LP0108ESA-7SI#B*

R1LP0108ESA-5SR#S*

R1LP0108ESA-5SI#S*

R1LP0108ESA-7SR#S*

R1LP0108ESA-7SI#S*

R1LP0108ESF-5SR#B*

R1LP0108ESF-5SI#B*

R1LP0108ESF-7SR#B*

R1LP0108ESF-7SI#B*

R1LP0108ESF-5SR#S*

R1LP0108ESF-5SI#S*

R1LP0108ESF-7SR#S*

R1LP0108ESF-7SI#S*

0 ~ +70°C

55 ns

Max. 25pcs/Tube

Max. 225pcs/Inner Bag

Max. 900pcs/Inner Box

-40 ~ +85°C

0 ~ +70°C

Tube

525-mil 32-pin

plastic SOP

70 ns

55 ns

70 ns

55 ns

70 ns

55 ns

70 ns

55 ns

70 ns

55 ns

70 ns

-40 ~ +85°C

0 ~ +70°C

PRSP0032DF-A

(32P2S-A)

-40 ~ +85°C

0 ~ +70°C

Embossed

tape

1000pcs/Reel

-40 ~ +85°C

0 ~ +70°C

-40 ~ +85°C

0 ~ +70°C

Max. 234pcs/Tray

Tray

8mm×13.4mm 32-pin

plastic sTSOP

Max. 1872pcs/Inner Box

-40 ~ +85°C

0 ~ +70°C

(normal-bend type)

PTSA0032KB-A

(32P3K-B)

-40 ~ +85°C

0 ~ +70°C

Embossed

tape

1000pcs/Reel

-40 ~ +85°C

0 ~ +70°C

-40 ~ +85°C

0 ~ +70°C

Max. 156pcs/Tray

Tray

8mm×20mm 32-pin

plastic TSOP

Max. 1248pcs/Inner Box

-40 ~ +85°C

0 ~ +70°C

(normal-bend type)

PTSA0032KA-A

(32P3H-E)

-40 ~ +85°C

0 ~ +70°C

Embossed

tape

1000pcs/Reel

-40 ~ +85°C

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 2 of 12

R1LP0108E Series

Pin Arrangement

A16

A14

A12

Vcc

A15

CS2

WE#

A13

A11

OE#

A10

CS1#

DQ7

DQ6

DQ5

DQ4

DQ3

32-pin SOP

DQ0

DQ1

DQ2

GND

A11

OE#

A10

CS1#

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A13

WE#

CS2

A15

Vcc

32-pin sTSOP

A16

A14

A12

A11

OE#

A10

CS1#

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A13

WE#

CS2

A15

Vcc

32-pin TSOP

A16

A14

A12

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 3 of 12

R1LP0108E Series

Pin Description

Pin name

Vcc

Function

Power supply

Ground

Vss

A0 to A16

DQ0 to DQ7

CS1#

Address input

Data input/output

Chip select 1

Chip select 2

Write enable

Output enable

Non connection

CS2

WE#

OE#

Block Diagram

A₀

A₁

MEMORY ARRAY

128k-word x8-bit

ROW

ADDRESS

BUFFER

DECODER

A₁₆

DQ0

DQ1

BUFFER

SENSE / WRITE AMPLIFIER

COLUMN DECODER

DQ7

CLOCK

GENERATOR

Vcc

Vss

WE#

CS1#

CS2

OE#

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 4 of 12

R1LP0108E Series

Operation Table

CS1#

CS2

WE#

OE#

DQ0~7

High-Z

Din

Operation

Stand-by

Write

Dout

Read

High-Z

Output disable

Note 1. H: V_IHL:V_IL

X: V_IHor V_IL

Absolute Maximum

Parameter

Symbol

Value

unit

Power supply voltage relative to Vss

Terminal voltage on any pin relative to Vss

Power dissipation

Vcc

V_T

-0.3 to +7

-0.3^*1to Vcc+0.3^*2

0.7

P_T

R Ver.

0 to +70

Operation temperature

Topr^*3

Tstg

°C

I Ver.

-40 to +85

Storage temperature range

Storage temperature range under bias

-65 to 150

R Ver.

I Ver.

0 to +70

Tbias^*3

-40 to +85

Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)

2. Maximum voltage is +7V.

3. Ambient temperature range depends on R/I-version. Please see table on page 1.

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 5 of 12

R1LP0108E Series

DC Operating Conditions

Parameter

Symbol

Vcc

Min.

4.5

Typ.

Max.

5.5

Unit

Note

Supply voltage

5.0

Vss

Input high voltage

Input low voltage

V_IH

2.2

-0.3

Vcc+0.3

0.8

V_IL

R Ver.

I Ver.

+70

°C

Ambient temperature range

-40

+85

Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)

2. Ambient temperature range depends on R/I-version. Please see table on page 1.

DC Characteristics

Parameter

Symbol

| I_LI|

Min.

Typ.

Max.

Unit

Test conditions

Input leakage current

Output leakage current

A Vin = Vss to Vcc

CS1# =V_IHor CS2 =V_ILor

A OE# =V_IH,

VI/O =Vss to Vcc

| I_LO

I_CC1

I_CC2

Average operating current

Min. cycle, duty =100%, II/O = 0mA

CS1# =V_IL, CS2 =V_IH, Others = V_IH/V_IL

Cycle =1s, duty =100%, II/O = 0mA

mA CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V,

V_IH≥ Vcc-0.2V, V_IL≤ 0.2V

“CS2 =V_IL” or

Standby current

I_SB

mA “CS2 = V_IHand CS1# =V_IH”,

Others = Vss to Vcc

Vin = Vss to Vcc

0.6^*1

A

~+25°C

~+40°C

~+70°C

~+85°C

(1) CS2 ≤ 0.2 or

I_SB1

(2) CS1# ≥ Vcc-0.2V,

CS2 ≥ Vcc-0.2V

Output high voltage

Output low voltage

V_OH

V_OH2

V_OL

2.4

I_OH= -1mA

I_OH= -0.1mA

I_OL= 2mA

Vcc

- 0.5

0.4

Note 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta= 25ºC), and not 100% tested.

Capacitance

(Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C^*2)

Parameter

Input capacitance

Input / output capacitance

Symbol

C in

Min.

Typ.

Max.

Unit

Test conditions

Vin =0V

Note

C _I/O

VI/O =0V

Note 1. This parameter is sampled and not 100% tested.

2. Ambient temperature range depends on R/I-version. Please see table on page 1.

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 6 of 12

R1LP0108E Series

AC Characteristics

Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C^*1)



Input pulse levels: VIL = 0.6V, VIH = 2.4V

Input rise and fall time: 5ns

Input and output timing reference level: 1.5V

Output load: See figures (Including scope and jig)

1.5V

R_L= 500 ohm

C_L= 30 pF

C_L= 100 pF

( -5SI, -5SR)

( -7SI, -7SR)

Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1.

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 7 of 12

R1LP0108E Series

Read Cycle

R1LP0108E**-5**

R1LP0108E**-7**

Parameter

Symbol

Unit

Note

Min.

Max.

Min.

Max.

Read cycle time

t_RC

t_AA

Address access time

t_ACS1

t_ACS2

t_OE

Chip select access time

Output enable to output valid

Output hold from address change

t_OH

t_CLZ1

t_CLZ2

t_OLZ

t_CHZ1

t_CHZ2

t_OHZ

2,3

Chip select to output in low-Z

Output enable to output in low-Z

Chip deselect to output in high-Z

Output disable to output in high-Z

2,3

1,2,3

Write Cycle

R1LP0108E**-5**

R1LP0108E**-7**

Parameter

Symbol

Unit

Note

Min.

Max.

Min.

Max.

Write cycle time

t_WC

t_AW

t_CW

t_WP

t_AS

Address valid to end of write

Chip select to end of write

Write pulse width

Address setup time

Write recovery time

t_WR

t_DW

t_DH

Data to write time overlap

Data hold from write time

Output enable from end of write

Output disable to output in high-Z

Write to output in high-Z

t_OW

t_OHZ

t_WHZ

1,2

Note 1. t_CHZ, t_OHZand t_WHZare defined as the time at which the outputs achieve the open circuit conditions and are not

referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. At any given temperature and voltage condition, t_HZmax is less than t_LZmin both for a given device and from

device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#.

A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low.

A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high.

t_WPis measured from the beginning of write to the end of write.

5. t_CWis measured from the later of CS1# going low or CS2 going high to end of write.

6. t_ASis measured the address valid to the beginning of write.

7. t_WRis measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.

8. Don’t apply inverted phase signal externally when DQ pin is output mode.

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 8 of 12

R1LP0108E Series

Timing Waveforms

Read Cycle

t_RC

A_0~16

t_OH

t_AA

t_ACS1

CS1#

CS2

t_CLZ1

t_CHZ1

t_ACS2

t_CLZ2

t_CHZ2

V_IH

WE#

WE# = “H” level

t_OE

OE#

t_OLZ

t_OHZ

High impedance

DQ_0~7

Valid Data

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 9 of 12

R1LP0108E Series

Write Cycle (1) (WE# CLOCK)

t_WC

A_0~16

t_CW

CS1#

t_CW

CS2

t_AW

t_WP

t_AS

t_WR

WE#

OE#

t_WHZ

t_OLZ

t_OHZ

t_OW

DQ_0~7

Valid Data

t_DWt_DH

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 10 of 12

R1LP0108E Series

Write Cycle (2) (CS1#, CS2 CLOCK)

t_WC

A_0~16

t_AW

t_AS

t_CW

t_WR

CS1#

CS2

t_AS

t_CW

t_WR

t_WP

WE#

V_IH

OE#

OE# = “H” level

t_DW

t_DH

DQ_0~7

Valid Data

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 11 of 12

R1LP0108E Series

Low Vcc Data Retention Characteristics

Parameter

Symbol

Min.

Typ. Max.

Unit

Test conditions^*2

Vin ≥ 0V

(1) 0V ≤ CS2 ≤ 0.2V or

V_CCfor data retention

V_DR

2.0

5.5

(2) CS1# ≥ Vcc-0.2V,

CS2 ≥ Vcc-0.2V

0.6^*1

A

~+25°C

Vcc=3.0V, Vin ≥ 0V

~+40°C

~+70°C

~+85°C

(1) 0V ≤ CS2 ≤ 0.2V or

(2) CS1# ≥ Vcc-0.2V,

CS2 ≥ Vcc-0.2V

Data retention current

I_CCDR

Chip deselect time to data retention

Operation recovery time

t_CDR

t_R

See retention waveform.

Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.

2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data

retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.

If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input

levels (address, WE# ,OE#, DQ) can be in the high impedance state.

Low Vcc Data Retention Timing Waveforms

(1) CS1# Controlled

Vcc

4.5V

t_CDR

t_R

V_DR

2.2V

CS1# ≥ Vcc - 0.2V

CS1#

(2) CS2 Controlled

Vcc

CS2

4.5V

t_CDR

t_R

V_DR

0.2V

0V ≤ CS2 ≤ 0.2V

R10DS0151EJ0100 Rev.1.00

2013.6.21

Page 12 of 12

Revision History

R1LP0108E Series Data Sheet

Description

Summary

Rev.

1.00

Date

Page

2013.6.21

First Edition issued

All trademarks and registered trademarks are the property of their respective owners.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

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Colophon 2.2

R1LP0108ESA-7SI#S [RENESAS]

相关型号：

R1LP0108ESA-7SIB0

R1LP0108ESA-7SIS0

R1LP0108ESA-7SR

R1LP0108ESA-7SR#B

R1LP0108ESA-7SRB0

R1LP0108ESA-7SRS0

R1LP0108ESF-5SI

R1LP0108ESF-5SIB0

R1LP0108ESF-5SIS0

R1LP0108ESF-5SR

R1LP0108ESF-5SR#S

R1LP0108ESF-5SRB0