R1LV1616R [RENESAS]
16Mb superSRAM (1M wordx16bit); 16MB superSRAM （ 1M wordx16bit ）
| 型号： | R1LV1616R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16Mb superSRAM (1M wordx16bit) |
| 文件： | 总16页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1LV1616R Series
REJ03C0101-0100Z
Rev.1.00
16Mb superSRAM (1M wordx16bit)
2004.04.13
Description
The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit,
fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies.
The R1LV1616R Series is suitable for memory applications where a simple interfacing , battery operating and
battery backup are the important design objectives.
The R1LV1616R Series is packaged in a 52pin micro thin small outline mount device[µTSOP / 10.79mm x
10.49mm with the pin-pitch of 0.4mm] or a 48balls fine pitch ball grid array [f-BGA / 7.5mmx8.5mm with the ball-pitch
of 0.75mm and 6x8 array] . It gives the best solution for a compaction of mounting area as well as flexibility of wiring
pattern of printed circuit boards.
Features
• Single 2.7-3.6V power supply
• Small stand-by current:2µA (3.0V, typ.)
• Data retention supply voltage =2.0V
• No clocks, No refresh
• All inputs and outputs are TTL compatible
• Easy memory expansion by CS1#, CS2, LB# and UB#
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE# prevents data contention on the I/O bus
• Process technology: 0.15um CMOS
Rev.1.00 2004.04.13
page 1 of 16
R1LV1616R Series
Ordering Information
Type No.
Access time
Package
R1LV1616RSD-7S%
R1LV1616RSD-8S%
R1LV1616RBG-7S%
R1LV1616RBG-8S%
70 ns
85 ns
70 ns
85 ns
350-mil 52-pin plastic µ - TSOP(II)
(normal-bend type) (52PTG)
7.5mmx8.5mm f-BGA 0.75mm pitch 48ball
% - Temperature version; see table below
%
R
W
I
Temperature Range
0 ~ +70 ºC
-20 ~ +85 ºC
-40 ~ +85 ºC
Rev.1.00 2004.04.13
page 2 of 16
R1LV1616R Series
Pin Arrangement
52-pin µTSOP
48-pin fBGA
1
2
52
A15
A14
A13
A16
51
50
BYTE#
UB#
3
4
A12
A11
A10
49
48
47
46
45
44
43
42
Vss
LB#
1
LB#
2
OE#
3
A0
4
A1
5
A2
6
CS2
5
A
B
C
D
E
F
6
DQ15
7
A9
A8
DQ7
8
UB#
CS1#
DQ1
DQ3
DQ4
DQ6
DQ15
DQ0
DQ2
Vcc
Vss
DQ5
DQ7
A3
A5
A4
A6
DQ14
9
A19
DQ6
10
11
12
13
14
15
16
CS1#
WE#
NC
DQ13
DQ13 DQ14
DQ5
DQ12
DQ4
41
40
DQ12
DQ11
Vss
Vcc
A17
A7
NC
Vcc
CS2
NC
39
38
NC
Vss
or
NC
A16
A15
DQ11
DQ3
37
NC
17
36
35
DQ10
DQ2
DQ10
DQ8
DQ9 A14
A18
18
19
34
33
A17
A7
DQ9
DQ1
A19
A8
A12
A9
A13 WE#
G
H
20
21
A6
32
DQ8
DQ0
OE#
A18
A10
A11 N.C.
A5
A4
22
23
24
25
26
31
30
A3
29
28
27
Vss
NC
A2
A1
A0
Pin Description
Pin name
A0 to A19
DQ 0 to DQ15
CS1# &CS2
WE#
Function
Address input
Data input/output
Chip select
Write enable
Output enable
Lower byte select
Upper byte select
Power supply
Ground
OE#
LB#
UB#
Vcc
Vss
BYTE#
NC
Byte (x8 mode) enable input
Non connection
Rev.1.00 2004.04.13
page 3 of 16
R1LV1616R Series
Block Diagram
DQ0
Memory Array
A0
1048576 Words
x 16BITS
DQ7
DQ8
OR
2097152 Words
x 8BITS
A19
DQ15
/ A-1
CS2
CS1#
LB#
CLOCK
GENERATOR
Vcc
Vss
x8/x16
SWITCHING
CIRCUIT
UB#
BYTE#
WE#
OE#
Note. BYTE# pin supported by only TSOP type.
Rev.1.00 2004.04.13
page 4 of 16
R1LV1616R Series
Operating Table
CS1#
CS2 BYTE#
LB#
X
X
H
L
UB#
X
X
H
H
H
X
L
WE#
X
OE#
X
DQ0-7 DQ8-14
DQ15
High-Z
High-Z
High-Z
High-Z
Operation
Stand by
H
X
X
L
L
L
L
L
L
L
L
L
X
L
X
X
H
H
H
X
H
H
H
H
L
High-Z
High-Z
High-Z
Din
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
X
X
Stand by
X
H
H
H
H
H
H
H
H
H
X
X
Stand by
L
X
Write in lower byte
L
H
H
L
L
Dout
High-Z Read from lower byte
X
H
H
L
H
X
High-Z
High-Z
High-Z
Din
High-Z
Din
Output disable
Write in upper byte
Read from upper byte
Write
L
H
L
L
Dout
Dout
Din
L
X
Din
L
L
H
L
L
Dout
Dout
Dout
A-1
Read
L
L
X
Din
High-Z
High-Z
Write
L
L
L
H
L
Dout
A-1
Read
Note 1. H:VIH L:VIL X: VIH or VIL
2. BYTE# pin supported by only TSOP type. When apply BYTE# =“L” , please assign LB#=UB#=“L”.
Absolute Maximum Ratings
Parameter
Symbol
Vcc
Value
-0.5 to +4.6
-0.5*1 to Vcc+0.3*2
0.7
Unit
V
Power supply voltage relative to Vss
Terminal voltage on any pin relation toVss
Power dissipation
V
VT
W
PT
R ver.
0 to +70
ºC
ºC
ºC
ºC
ºC
ºC
ºC
Operation temperature
Topr
Tstg
W ver.
I ver.
-20 to +85
-40 to +85
Storage temperature
-65 to +150
R ver.
W ver.
I ver.
0 to +70
-20 to +85
-40 to +85
Storage temperature range under bias
Tbias
Note 1. -2.0V in case of AC (Pulse width £ 30ns)
2. Maximum voltage is +4.6V
Rev.1.00 2004.04.13
page 5 of 16
R1LV1616R Series
Recommended Operating Conditions
Parameter
Symbol
Vcc
Min.
2.7
0
Typ.
Max.
3.6
Unit
V
Note
3.0
Supply voltage
Vss
0
-
0
V
Input high voltage
Input low voltage
2.4
-0.2
0
Vcc+0.2
0.4
V
VIH
-
V
1
2
2
2
VIL
R ver.
-
+70
ºC
ºC
ºC
Ambient temperature range W ver.
I ver.
Ta
-20
-40
-
+85
-
+85
Note 1. –2.0V in case of AC (Pulse width £ 30ns)
2. Ambient temperature range depends on R/W/I-version. Please see table on page 2.
DC Characteristics
Typ.*1
Test conditions*2
Min.
Max. Unit
Parameter
Symbol
-
-
1
Input leakage current
µA Vin=Vss to Vcc
|ILI|
CS1# =VIH or CS2=VIL or
µA OE# = VIH or WE# =VIL or
LB# =UB# =VIH,VI/O=Vss to Vcc
-
-
-
1
Output leakage current
|ILo|
Icc1
Min. cycle, duty =100%
45
55
mA
I I/O = 0 mA, CS1# =VIL,
CS2=VIH Others = VIH / VIL
Average operating
current
Icc2
Cycle time = 1 µs, I I/O = 0 mA,
mA
-
-
15
10
20
15
Write
CS1#£ 0.2V, CS2 ³ VCC-0.2V
VIH ³ VCC-0.2V , VIL £ 0.2V,
Icc2
Read
Write & Read duty=100%
respectively
mA
mA
-
-
0.1
2
0.3
6
Standby current
Standby current
CS2=VIL
ISB
V in ³ 0V
µA ~+25ºC
µA ~+40ºC
µA ~+70ºC
µA ~+85ºC
(1) 0V£CS2£0.2V or
(2) CS2³ Vcc-0.2V,
CS1# ³ Vcc-0.2V or
(3)LB# =UB# ³ Vcc-0.2V,
CS2³ Vcc-0.2V,
-
-
-
4
-
12
25
40
ISB1
CS1# £0.2V
Average value
-
-
-
-
Output hige voltage
Output Low voltage
2.4
-
V
V
VOH
VOL
IOH = -1mA
IOL = 2mA
0.4
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. BYTE# pin supported by only TSOP type.
BYTE# ³ Vcc-0.2V or BYTE# £ 0.2V
Rev.1.00 2004.04.13
page 6 of 16
R1LV1616R Series
Capacitance
(Ta = +25ºC, f =1MHz)
Parameter
Input capacitance
Symbol Min.
Typ. Max.
Unit
pF
Test conditions Note
C in
-
-
-
-
10
10
V in = 0V
V I/O = 0V
1
1
Input / output capacitance
pF
C I/O
Note 1:This parameter is sampled and not 100% tested.
AC Characteristics
Test Conditions (Vcc=2.7~3.6V, Ta = 0~+70ºC / -20~+85ºC / -40~+85ºC *)
• Input pulse levels: VIL= 0.4V,VIH=2.4V
• Input rise and fall time : 5ns
• Input and output timing reference levels : 1.4V
• Output load : See figures (Including scope and jig)
1.4V
RL=500W
DQ
CL=30pF
Note: Temperature range depends on R/W/I-version. Please see table on page 2.
Rev.1.00 2004.04.13
page 7 of 16
R1LV1616R Series
Read Cycle
R1LV1616R**-7S
R1LV1616R**-8S
Unit
Notes
Parameter
Symbol
Min.
70
Max.
-
Min.
85
Max.
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
t
RC
AA
-
-
70
70
70
35
-
-
-
85
85
85
45
-
Address access time
t
t
t
ACS1
ACS2
Chip select access time
-
-
-
-
Output enable to output valid
Output hold from address change
LB#,UB# access time
t
OE
OH
10
-
10
-
t
70
-
85
-
t
BA
10
5
5
0
0
0
0
10
5
5
0
0
0
0
2,3
2,3
Chip select to output in low-Z
LB#,UB# enable to low-Z
t
CLZ
BLZ
-
-
t
Output enable to output in low-Z
-
-
2,3
t
OLZ
25
25
25
25
30
30
30
30
1,2,3
1,2,3
1,2,3
1,2,3
t
t
CHZ1
CHZ2
Chip deselect to output in high-Z
LB#,UB# disable to high-Z
t
BHZ
Output disable to output in high-Z
t
OHZ
Rev.1.00 2004.04.13
page 8 of 16
R1LV1616R Series
Write Cycle
R1LV1616R**-7S
R1LV1616R**-8S
Unit
Notes
Parameter
Symbol
Min.
70
Max.
-
Min.
85
Max.
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tWC
Address valid to end of write
Chip selection to end of write
Write pulse width
65
65
55
65
0
-
-
70
70
60
70
0
-
-
tAW
tCW
tWP
tBW
5
4
-
-
LB#,UB# valid to end of write
Address setup time
-
-
-
-
6
7
t
AS
0
-
0
-
Write recovery time
tWR
35
0
-
40
0
-
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
Write to output in high-Z
t
DW
-
-
t
DH
OW
OHZ
WHZ
5
-
5
-
2
t
0
25
25
0
30
30
1,2
1,2
t
0
0
t
Note1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. AT any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and
form device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#
going low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.1.00 2004.04.13
page 9 of 16
R1LV1616R Series
Byte enable (supported by only 52-pin µTSOP )
R1LV1616R**-7S
R1LV1616R**-8S
Unit
Notes
Parameter
Symbol
Min.
5
Max.
-
Min.
5
Max.
-
Byte setup time
ms
ms
tBS
BR
Byte recovery time
5
-
5
-
t
BYTE# Timing Waveform
CS2
CS1#
tBS
tBR
BYTE#
Rev.1.00 2004.04.13
page 10 of 16
R1LV1616R Series
Read Cycle
Timing Waveform
t
RC
A0~19
(Word Mode)
Valid address
AA
A-1~19
(Byte Mode)
t
t
OH
t
BA
LB#,UB#
t
t
BHZ
t
t
ACS1
ACS2
CS1#
CS2
CHZ1
t
CHZ2
t
OE
OE#
t
OLZ
t
OHZ
WE# = "H" level
t
t
CLZ
DQ0~15
(Word Mode)
BLZ
Valid data
DQ0~7
(Byte Mode)
Rev.1.00 2004.04.13
page 11 of 16
R1LV1616R Series
Write Cycle (1) (WE# Clock)
t
WC
A0~19
(Word Mode)
Valid address
A-1~19
(Byte Mode)
t
BW
LB#,UB#
CS1#
t
CW
t
CW
CS2
t
AW
tWR
t
WP
t
AS
t
WHZ
WE#
t
OW
t
DW
t
DH
DQ0~15
(Word Mode)
Valid data
DQ0~7
(Byte Mode)
Rev.1.00 2004.04.13
page 12 of 16
R1LV1616R Series
Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH)
tWC
A0~19
(Word Mode)
Valid address
A-1~19
(Byte Mode)
t
BW
LB#,UB#
CS1#
CS2
t
t
CW
CW
tWR
t
AS
tWP
WE#
t
DW
t
DH
DQ0~15
(Word Mode)
Valid data
DQ0~7
(Byte Mode)
Rev.1.00 2004.04.13
page 13 of 16
R1LV1616R Series
Write Cycle (3) ( LB#,UB# Clock, OE#=VIH)
tWC
A0~19
(Word Mode)
Valid address
A-1~19
(Byte Mode)
t
AS
t
t
BW
CW
tWR
LB#,UB#
CS1#
t
CW
CS2
WE#
tWP
DQ0~15
(Word Mode)
t
DW
t
DH
Valid data
0~7
DQ
(Byte Mode)
Rev.1.00 2004.04.13
page 14 of 16
R1LV1616R Series
Data Retention Characteristics
Parameter
Symbol MIn. Typ.*1 Max. Unit
Test conditions*2,3
V in ³ 0V
(1) 0V £ CS2 £ 0.2V or
(2) CS2 ³ Vcc-0.2V,
CS1# ³ Vcc-0.2V or
(3) LB# =UB# ³ Vcc-0.2V,
CS2 ³ Vcc-0.2V,
2.0
-
3.6
V
Vcc for data retention
VDR
CS1# £ 0.2V
-
-
-
-
2
4
-
6
~+25ºC
µA
µA
µA
µA
Vcc=3.0V,Vin³ 0V
(1) 0V £ CS2 £ 0.2V or
(2) CS2 ³ Vcc-0.2V,
CS1# ³ Vcc-0.2V or
(3) LB# =UB# ³ Vcc-0.2V,
CS2 ³ Vcc-0.2V,
CS1# £ 0.2V
Average value
12
25
40
~+40ºC
Data retention current
IccDR
~+70ºC
-
~+85ºC
0
5
-
-
-
-
Chip deselect to data retention time
Operation recovery time
ns
tCDR
tR
See retention waveform
ms
Note 1. Typical parameter of IccDR indicates the value for the center of distribution at Vcc=3.0V and not 100% tested.
2. BYTE# pin supported by TSOP type. BYTE# ³ Vcc-0.2V or BYTE# £ 0.2V
3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2
controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance
state. If CS1# controls data retention mode, CS2 must be CS2 ³ Vcc-0.2V or 0V £ CS2 £ 0.2V. The other input
levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
Data Retention timing Waveform (1) (LB#,UB# Controlled)
Vcc
2.70V
tCDR
tR
2.4V
2.4V
LB# =UB# ³ Vcc-0.2V
LB#
UB#
Data Retention timing Waveform (2) (CS1# Controlled)
Vcc
2.70V
tCDR
tR
2.4V
2.4V
CS1# ³ Vcc-0.2V
CS1#
Data Retention timing Waveform (3) (CS2 Controlled)
Vcc
2.70V
tCDR
tR
CS2
0.2V
0.2V
0V £ CS2 £ 0.2V
Rev.1.00 2004.04.13
page 15 of 16
R1LV1616R Series
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Rev.1.00 2004.04.13
page 16 of 16
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