R1Q4A7218RBG-60RT0 [RENESAS]
36-Mbit QDR™II SRAM 2-word Burst; 36 - Mbit的QDR ™ II SRAM的2字突发
| 型号： | R1Q4A7218RBG-60RT0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 36-Mbit QDR™II SRAM 2-word Burst |
| 文件： | 总26页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
36-Mbit QDR™II SRAM
2-word Burst
REJ03C0341-0003
Preliminary
Rev. 0.03
Apr. 11, 2008
Description
The R1Q2A3636B is a 1,048,576-word by 36-bit, the R1Q2A3618B is a 2,097,152-word by 18-bit, and the
R1Q2A3609B is a 4,194,304-word by 9-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K
and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
•
•
•
•
•
•
•
•
1.8 V 0.1 V power supply for core (VDD
1.4 V to VDD power supply for I/O (VDDQ
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR read and write operation
Two-tick burst for low DDR transaction size
)
)
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
•
•
•
•
•
•
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time: 4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Notes: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp.
Preliminary:
The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 1 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Ordering Information
Part Number
Organization Cycle
Clock
Package
Notes
time
frequency
R1Q2A3636BBG-40R
1-M word
4.0 ns
5.0 ns
6.0 ns
4.0 ns
5.0 ns
6.0 ns
4.0 ns
5.0 ns
6.0 ns
250 MHz
200 MHz
167 MHz
250 MHz
200 MHz
167 MHz
250 MHz
200 MHz
167 MHz
Plastic FBGA 165-pin
PLBG0165FB-A
× 36-bit
R1Q2A3636BBG-50R
R1Q2A3636BBG-60R
R1Q2A3618BBG-40R
R1Q2A3618BBG-50R
R1Q2A3618BBG-60R
R1Q2A3609BBG-40R
R1Q2A3609BBG-50R
R1Q2A3609BBG-60R
Notes:
2-M word
× 18-bit
4-M word
× 9-bit
1. Part Number
(0:1)
(2:3)
R1 : Renesas Memory prefix
Q2 : QDRII 2-word Burst SRAM
Q3 : QDRII 4-word Burst SRAM
Q4 : DDRII 2-word Burst SRAM
Q5 : DDRII 4-word Burst SRAM
Q6 : DDRII 2-word Burst SRAM
Separate I/O
(9)
R
A
B
BG
60
50
40
33
R
I
B
T
S
: 1stGeneration
: 2ndGeneration
: 3rdGeneration
(10:11)
(12:13)
: Package type=BGA
: Cycle time=6.0 ns
: Cycle time=5.0 ns
: Cycle time=4.0 ns
: Cycle time=3.3 ns
: Temperature range= 0°C ∼70°C
: Temperature range= -40°C ∼85°C
: Pb-free
(4)
(5:6)
A
: VDD=1.8V
36 : Density = 36Mb
72 : Density = 72Mb
36 : Organization = x36
18 : Organization = x18
09 : Organization = x9
(14)
(15)
(7:8)
: Tape&Reel
: Pb-free and Tape&Reel
: Standard (Pb and Tray)
None
(16)
0 ∼9 , A ∼Z :Renesas internal use
2. Marking Name
Marking Name(0:14) =Part Number(0:14)
------------Pb
Marking Name(0:16) =Part Number(0:14)+Bx------------Pb-free (x=0 ∼9 , A ∼Z)
(Example) R1Q2A3609BBG-60R
------------Pb
R1Q2A3609BBG-60RB0 ------------Pb-free
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 2 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Pin Arrangement
R1Q2A3636B series
1
/CQ
Q27
D27
D28
Q29
Q30
D30
/DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
3
4
5
/BW2
/BW3
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
6
7
/BW1
/BW0
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
8
9
10
NC
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
NC
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
/K
K
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
SA
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
/C
SA
TMS
(Top View)
R1Q2A3618B series
1
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
7
NC
/BW0
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
NC
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
SA
D9
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
/BW1
NC
SA
/K
K
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
SA
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
/C
(Top View)
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 3 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
R1Q2A3609B series
1
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
SA
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
4
5
6
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
NC
NC
D5
NC
NC
D6
VREF
NC
NC
Q7
NC
D8
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
/K
K
NC
/BW
SA
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
Q8
SA
VSS
SA
SA
VSS
SA
SA
NC
TCK
SA
SA
/C
TMS
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs (i.e. 72Mb → 144Mb →288Mb): (9A → 3A → 10A)
→ 2A → 7A → 5B.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 4 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Pin Description
Name
I/O type
Descriptions
Notes
SA
Input
Synchronous address inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K for READ cycles and must meet the setup
and hold times around the rising edge of /K for WRITE cycles. All transactions operate
on a burst-of-two words (one clock period of bus activity). These inputs are ignored
when device is deselected.
/R
/W
Input
Input
Input
Synchronous read: When low, this input causes the address inputs to be registered
and a READ cycle to be initiated. This input must meet setup and hold times around
the rising edge of K.
Synchronous write: When low, this input causes the address inputs to be registered
and a WRITE cycle to be initiated. This input must meet setup and hold times around
the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and /K for each of the two rising edges comprising
the WRITE cycle. See Byte Write Truth Table for signal to data relationship.
/BWx
K, /K
C, /C
Input
Input
Input clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning device output
data. The rising edge of /C is used as the output timing reference for first output data.
The rising edge of C is used as the output timing reference for second output data.
Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the
use of K and /K as the output reference clocks instead of having to provide C and /C
clocks. If tied high, C and /C must remain high and not to be toggled during device
operation. These balls cannot remain VREF level.
/DOFF
ZQ
Input
Input
DLL disable: When low, this input causes the DLL to be bypassed for /DOFF Input
stable, low frequency operation.
Output impedance matching input: This input is used to tune the device outputs to the
system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where
RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ
,
which enables the minimum impedance mode. This ball cannot be connected directly
to VSS or left unconnected.
TMS
TDI
TCK
Input
Input
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not TMS Input
connected if the JTAG function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG
function is not used TCK Input in the circuit.
Synchronous data inputs: Input data must meet setup and hold times around the rising
edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site
location of individual signals.
D0 to Dn
The ×9 device uses D0 to D8. Remaining signals are not used.
The ×18 device uses D0 to D17. Remaining signals are not used.
The ×36 device uses D0 to D35.
CQ, /CQ
Output
Synchronous echo clock outputs: The edges of these outputs are tightly matched to
the synchronous data outputs and can be used as a data valid indication. These
signals run freely and do not stop when Q tristates.
TDO
Q0 to Qn
Output
Output
IEEE 1149.1 test output: 1.8 V I/O level.
Synchronous data outputs: Output data is synchronized to the respective C and /C, or
to the respective K and /K if C and /C are tied high. This bus operates in response to
/R commands. See Pin Arrangement figures for ball site location of individual signals.
The ×9 device uses Q0 to Q8. Remaining signals are not used.
The ×18 device uses Q0 to Q17. Remaining signals are not used.
The ×36 device uses Q0 to Q35.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 5 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Name
I/O type
Descriptions
Notes
VDD
Supply
Power supply: 1.8 V nominal. See DC Characteristics and Operating VDD Supply
Conditions for range.
VDDQ
Supply
Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible.
See DC Characteristics and Operating Conditions for range.
VSS
Supply
Power supply: Ground.
VREF
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve
system noise margin. Provides a reference voltage for the HSTL input buffers.
NC
No connect: These signals are not internally connected. These signals can be left
floating or connected to ground to improve package heat dissipation.
Notes: 1. All power supply and ground balls must be connected for proper operation of the device.
Block Diagram (R1Q2A3636B / R1Q2A3618B / R1Q2A3609B series)
19/20/21
Address
Address
/R
/W
K
19/20/21
Registry
and
Logic
ZQ
/K
72
/36
/18
72
/36
/18
/W
72
/36
/18
Q
(Data out)
4/2/1
/BWx
36/18/9
Memory
Array
Data
Registry
and
36/18/9
D
(Data in)
2
Logic
CQ
/R
/CQ
K
K
C
C, /C
or
/K
K, /K
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 6 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
General Description
Power-up and Initialization Sequence
The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
After the stable power, there are three possible sequences.
1. Sequence when DLL disable (/DOFF pin fixed low)
Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations,
including JTAG functions, to become normal.
2a. Sequence controlled by /DOFF pin when DLL enable
Just after the stable power and clock (K, /K, C, /C), take /DOFF to be high.
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
If /DOFF pin is fixed high with unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.).
During stop clock stage, C pin must tie low for 30 ns (min.). C, /C, K and /K cannot remain VREF level.
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
Notes: 1. After K or C clock is stopped, clock recovery cycles (1024 NOP cycles (min.)) are required for read/write
operations to become normal.
2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL
reset again, the 1024 NOP cycles (min.) are needed to lock the DLL.
1. Sequence when DLL disable (/DOFF pin fixed low)
Unstable
Stable
Normal
Status
Power Up
NOP Stage
Clock Stage
Clock Stage
Operation
VDD
VDDQ
VREF
VIN
1024cycle min.
C, /C, K, /K
2a. Sequence controlled by /DOFF pin when DLL enable
Unstable
Stable
NOP & DLL
Normal
Status
Power Up
Clock Stage
Clock Stage
Locking Stage
Operation
VDD
VDDQ
VREF
/DOFF
1024cycle min.
C, /C, K, /K
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 7 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Unstable
Stop
NOP & DLL
Normal
Status
Power Up
Clock Stage
Clock Stage
Locking Stage
Operation
VDD
VDDQ
VREF
/DOFF
30ns min.
1024cycle min.
C, /C, K, /K
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as
TKC var.
2. The lower end of the frequency at which the DLL can operate is 119MHz.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250 Ω typical.
The total external capacitance of ZQ ball must be less than 7.5 pF.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 8 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
K Truth Table
Operation
K
/R
/W
D or Q
Write Cycle:
Load address, input write data on
consecutive K and /K rising edges
↑
×
L
Data in
Input data
Output clock
Data out
D(A+0)
D(A+1)
K(t)↑
/K(t)↑
Read Cycle:
↑
L
×
Load address, output read data on
consecutive C and /C rising edges
Output data
Output clock
Q(A+0)
/C(t+1)↑
Q(A+1)
C(t+2)↑
NOP (No operation)
↑
H
H
D = × or Q = High-Z
Standby (Clock stopped)
Stopped
×
×
Previous state
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges,
except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and
/C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 9 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Byte Write Truth Table (x36)
Operation
Write D0 to D35
K
↑
↑
↑
↑
↑
↑
/K
↑
↑
↑
↑
↑
↑
/BW0
L
L
L
L
H
H
H
H
H
H
H
H
/BW1
L
L
H
H
L
L
H
H
H
H
H
H
/BW2
L
L
H
H
H
H
L
L
H
H
H
H
/BW3
L
L
H
H
H
H
H
H
L
L
H
H
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x18)
Operation
Write D0 to D17
K
↑
↑
↑
↑
/K
↑
↑
↑
↑
/BW0
/BW1
L
L
L
L
L
H
H
L
L
H
H
Write D0 to D8
Write D9 to D17
Write nothing
L
H
H
H
H
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x9)
Operation
Write D0 to D8
K
↑
↑
/K
↑
↑
/BW
L
L
H
H
Write nothing
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 10 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Bus Cycle State Diagram
/R = H
/R = H
Always
/R = L
/R = L
Read Port NOP
Load New
Read Double
RInit = 0
Read Address
Supply voltage
provided
Power Up
Supply voltage
provided
Always
/W = L
Load New
Write Address
at /K↑
Write Double
Write Port NOP
/W = L
at /K↑
/W = H
/W = H
Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order
is always fixed as: xxx…xxx+0, xxx…xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 11 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Absolute Maximum Ratings
Parameter
Input voltage on any ball
Input/output voltage
Core supply voltage
Output supply voltage
Junction temperature
Storage temperature
Symbol
VIN
VI/O
VDD
VDDQ
Tj
Rating
−0.5 to VDD + 0.5 (2.5 V max.)
−0.5 to VDDQ + 0.5 (2.5 V max.)
−0.5 to 2.5
Unit
V
V
V
V
Notes
1, 4
1, 4
1, 4
1, 4
−0.5 to VDD
+125 (max)
−55 to +125
°C
°C
TSTG
Notes: 1. All voltage is referenced to VSS
.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables
after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the
instantaneous value of VDDQ
.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Power supply voltage --core
Power supply voltage --I/O
Input reference voltage --I/O
Input high voltage
Symbol
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
Min
1.7
1.4
0.68
REF + 0.1
Typ
1.8
1.5
0.75
Max
1.9
VDD
0.95
DDQ + 0.3
Unit
Notes
V
V
V
V
V
1
V
V
2, 3
2, 3
Input low voltage
−0.3
VREF − 0.1
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
.
2. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD
.
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than
tKHKH (min).
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS
.
3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.
DC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
−60
−40
Max
600
650
700
350
−50
Max
550
600
650
340
Parameter
Symbol
IDD
Max
500
550
600
330
Unit
mA
mA
mA
mA
Notes
Operating supply current
(×9)
(×18)
1, 2, 3
(READ / WRITE)
IDD
1, 2, 3
1, 2, 3
2, 4, 5
(×36)
IDD
Standby supply current
(NOP)
(×9 / ×18 / ×36)
ISB1
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 12 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Parameter
Symbol
ILI
ILO
VOH (Low)
VOH
Min
−2
−5
Max
Unit
µA
µA
V
V
V
Test conditions
Notes
10
11
8, 9
8, 9
8, 9
8, 9
Input leakage current
Output leakage current
Output high voltage
2
5
VDDQ
V
DDQ −0.2
VDDQ/2 −0.08
VSS
|IOH| ≤ 0.1 mA
VDDQ/2 +0.08
0.2
VDDQ/2 +0.08
Note 6
Output low voltage
VOL (Low)
VOL
I
OL ≤ 0.1 mA
VDDQ/2 −0.08
V
Note 7
Notes: 1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents are measured at 100% bus utilization.
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value (Condition=NOP currents are valid when entering NOP after all pending READ and WRITE
cycles are completed.)
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I standards.
10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Thermal Resistance
Parameter
Symbol
θJA
Typ
24.5
5.6
Unit
°C/W
°C/W
Notes
Junction to Ambient
Junction to Case
θJC
Note: These parameters are calculated under the condition of wind velocity = 1 m/s.
Capacitance
(Ta = +25°C, f=1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter
Input capacitance
Symbol
CIN
Min
Typ
2
Max
Unit
Test conditions
Notes
3
pF
VIN = 0 V
1, 2
Clock input capacitance
Input/output capacitance (D, Q, ZQ)
CCLK
CI/O
2
3
3
4.5
pF
pF
VCLK = 0 V
VI/O = 0 V
1, 2
1, 2
Notes: 1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V)
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test points
0.75 V
0.25 V
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 13 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Output waveform
VDDQ /2
Test points
VDDQ /2
Output load condition
0.75 V
VDDQ /2
VREF
50 Ω
Z0 = 50 Ω
Q
SRAM
250 Ω
ZQ
AC Operating Conditions
Parameter
Input high voltage
Input low voltage
Symbol
Min
VREF + 0.2
Typ
Max
Unit
Notes
1, 2, 3, 4
1, 2, 3, 4
VIH (AC)
VIL (AC)
REF − 0.2
V
V
V
Notes: 1. All voltages referenced to VSS (GND).
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less
than tKHKL (min) or operate at cycle rates less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)
.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 14 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
AC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
−60
−40
−50
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Average clock cycle time
(K, /K, C, /C)
tKHKH
4.00
8.40
5.00
8.40
6.00
8.40
ns
Clock phase jitter
tKC var
tKHKL
0.20
0.20
0.20
ns
ns
ns
ns
ns
ns
3
(K, /K, C, /C)
Clock high time
(K, /K, C, /C)
Clock low time
(K, /K, C, /C)
Clock to /clock
(K to /K, C to /C)
/Clock to clock
(/K to K, /C to C)
1.60
1.60
1.80
1.80
0
2.00
2.00
2.20
2.20
0
2.40
2.40
2.70
2.70
0
tKLKH
tKH/KH
t/KHKH
tKHCH
Clock to data clock
(K to C, /K to /C)
1.10
1.60
2.10
DLL lock time (K, C)
K static to DLL reset
tKC lock
tKC reset
tCHQV
1,024
30
−0.45
−0.45
−0.30
−0.45
0.35
0.45
0.45
0.30
1,024
30
−0.45
−0.45
−0.35
−0.45
0.40
0.45
0.45
0.35
1,024
30
−0.50
−0.50
−0.40
−0.50
0.50
0.50
0.50
0.40
Cycle
ns
ns
ns
ns
ns
ns
ns
ns
2
7
C, /C high to output valid
C, /C high to output hold
C, /C high to echo clock valid
C, /C high to echo clock hold
CQ, /CQ high to output valid
CQ, /CQ high to output hold
C, /C high to output high-Z
C, /C high to output low-Z
tCHQX
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
4, 7
4, 7
5
5
1
0.45
0.45
0.50
tCHQX1
tAVKH
ns
ns
Address valid to K, /K rising
edge
Control inputs valid to K rising
edge
tIVKH
0.35
0.40
0.50
ns
1
Data-in valid to K, /K rising edge
K, /K rising edge to address hold
K, /K rising edge to control
inputs hold
tDVKH
tKHAX
tKHIX
0.35
0.35
0.35
0.40
0.40
0.40
0.50
0.50
0.50
ns
ns
ns
1
1
1
K, /K rising edge to data-in hold
tKHDX
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD
and input clock are stable. It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo
clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV
7. These parameters are sampled.
.
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. If C, /C are tied high, K, /K become the references for C, /C timing parameters.
4. VDDQ is +1.5 V DC.
5. Control signals are /R, /W, /BW, /BW0, /BW1, /BW2 and /BW3.
BWn signals must operate at the same timing as Data in.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 15 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Timing Waveforms
Read and Write Timing
1
2
3
4
5
6
7
8
9
10
11
NOP
12
13
NOP
14
15
NOP
16
17
NOP
READ
READ
READ
READ
NOP
WRITE
WRITE
WRITE
WRITE
WRITE
NOP
NOP
K
/K
tKHKL
tKH/KH
t/KHKH
tKHKH
tKLKH
/R
tIVKH
tIVKH
tAVKH
tDVKH
tKHIX
/W
tKHIX
A1
A0
A2
A3
A4
A5
A6
A7
A8
Address
Data in
tKHAX
D10 D11 D30 D31 D50 D51 D70 D71 D80 D81
tDVKH
tKHDX
tKHDX
Q00 Q01 Q20 Q21 Q40 Q41 Q60 Q61
Data out
tCHQZ
-tCHQX1
tCHQV
tCHQV
tCQHQV
-tCQHQX
-tCHQX
-tCHQX
CQ
tCHCQV
-tCHCQX
/CQ
tCHCQV
-tCHCQX
C
tKHKL
tKH/KH
t/KHKH
tKHKH
tKHCH
/C
tKLKH
tKHCH
Notes: 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following
A0, i.e., A0+1.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A0 = A1, then data Q00 = D10, Q01 = D11. Write data is forwarded immediately
as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data in.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 16 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an
undriven input will produce a response identical to the application of a logic 1,and may be left unconnected. But they
may also be tied to VDD through a 1kΩ resistor.TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
Notes
TCK
2R
Test clock input. All inputs are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test mode select. This is the command input for the TAP controller state
machine.
Test data input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling edge of TCK.
This is the output side of the serial registers placed between TDI and TDO.
Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
Parameter
Input high voltage
Input low voltage
Input leakage current
Output leakage current
Symbol
VIH
Min
+1.3
−0.3
−5.0
−5.0
Typ
Max
VDD + 0.3
+0.5
+5.0
+5.0
Unit
Notes
V
V
µA
µA
VIL
ILI
ILO
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDD,
output disabled
IOLC = 100 µA
IOLT = 2 mA
|IOHC| = 100 µA
|IOHT| = 2 mA
Output low voltage
Output high voltage
VOL1
VOL2
VOH1
VOH2
1.6
1.4
0.2
0.4
V
V
V
V
Notes: 1. All voltages referenced to VSS (GND).
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms.
3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
4. ZQ: VIH = VDDQ
.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 17 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
TAP AC Test Conditions
Parameter
Temperature
Input timing measurement reference levels
Input pulse levels
Symbol
Ta
VREF
VIL, VIH
tr, tf
Conditions
0 ≤ Ta ≤ +70
0.9
0 to 1.8
≤ 1.0
0.9
0.9
See figures
Unit
°C
V
V
ns
V
Notes
Input rise/fall time
Output timing measurement reference levels
Test load termination supply voltage (VTT)
Output load
V
Input waveform
1.8 V
0.9 V
0 V
Test points
0.9 V
Output waveform
0.9 V
Test points
0.9 V
Output load condition
V
TT = 0.9 V
DUT
50 Ω
Z0 = 50 Ω
TDO
20 pF
External Load at Test
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 18 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
TAP AC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V)
Parameter
Test clock (TCK) cycle time
TCK high pulse width
TCK low pulse width
Test mode select (TMS) setup
TMS hold
Capture setup
Capture hold
TDI valid to TCK high
TCK high to TDI invalid
TCK low to TDO unknown
TCK low to TDO valid
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
Min
100
40
40
10
10
10
10
10
10
0
Typ
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
tCH
tDVTH
tTHDX
tTLQX
tTLQV
Notes: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
TDI
tMVTH
tTHMX
tTHDX
tDVTH
tTLQV
TDO
tTLQX
tCH
tCS
PI
(SRAM)
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 19 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Test Access Port Registers
Register name
Instruction register
Bypass register
ID register
Length
Symbol
IR [2:0]
BP
ID [31:0]
BS [109:1]
Notes
3 bits
1 bits
32 bits
109 bits
Boundary scan register
TAP Controller Instruction Set
IR2 IR1 IR0
Instruction
Description
The EXTEST instruction allows circuitry external to the component
Notes
0
0
0
EXTEST
1, 2, 3
package to be tested. Boundary scan register cells at output balls are
used to apply test vectors, while those at input balls capture test results.
Typically, the first test vector to be applied using the EXTEST instruction
will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the Update-IR state of EXTEST, the output
driver is turned on and the PRELOAD data is driven onto the output balls.
0
0
0
1
1
0
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID
register when the controller is in capture-DR mode and places the ID
register between the TDI and TDO balls in shift-DR mode. The IDCODE
instruction is the default instruction loaded in at power up and any time
the controller is placed in the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM
outputs are forced to an inactive drive state (high-Z), moving the TAP
controller into the capture-DR state loads the data in the RAMs input into
the boundary scan register, and the boundary scan register is connected
between TDI and TDO when the TAP controller is moved to the shift-DR
state.
SAMPLE-Z
3, 4
0
1
1
0
1
0
RESERVED
SAMPLE
The RESERVED instructions are not implemented but are reserved for
future use. Do not use these instructions.
When the SAMPLE instruction is loaded in the instruction register,
3
(/PRELOAD) moving the TAP controller into the capture-DR state loads the data in the
RAMs input and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for
the TAP to attempt to capture the I/O ring contents while the input buffers
are in transition (i.e., in a metastable state). Although allowing the TAP to
SAMPLE metastable input will not harm the device, repeatable results
cannot be expected. Moving the controller to shift-DR state then places
the boundary scan register between the TDI and TDO balls.
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
BYPASS
The BYPASS instruction is loaded in the instruction register when the
bypass register is placed between TDI and TDO. This occurs when the
TAP controller is moved to the shift-DR state. This allows the board level
scan path to be shortened to facilitate testing of other devices in the scan
path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing
the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required to return from the SAMPLE-Z instruction.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 20 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Boundary Scan Order
Signal names
Signal names
x18
SA
Bit #
1
Ball ID
6R
x9
/C
x18
/C
C
x36
/C
C
SA
SA
SA
SA
SA
SA
SA
Q0
D0
D9
Q9
Q1
D1
Bit #
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Ball ID
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
x9
SA
SA
SA
/R
NC
/BW
K
x36
SA
2
6P
C
SA
SA
/R
NC
/BW0
K
/K
NC
/BW1
/W
SA
SA
SA
VSS
/CQ
Q9
D9
NC
SA
3
4
5
6
7
8
9
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
SA
SA
SA
SA
SA
SA
SA
Q0
D0
NC
NC
NC
NC
NC
NC
Q1
D1
NC
NC
NC
NC
NC
NC
Q2
D2
ZQ
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
NC
NC
NC
NC
Q4
D4
NC
NC
CQ
SA
SA
SA
SA
SA
SA
SA
SA
SA
Q0
D0
NC
NC
Q1
D1
NC
NC
Q2
D2
NC
NC
Q3
D3
NC
NC
Q4
D4
ZQ
NC
NC
Q5
D5
NC
NC
Q6
D6
NC
NC
Q7
D7
NC
NC
Q8
D8
NC
NC
CQ
NC
SA
SA
/R
/BW1
/BW0
K
/K
/K
NC
NC
/W
/BW3
/BW2
/W
SA
SA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SA
SA
SA
VSS
/CQ
NC
NC
NC
NC
NC
NC
NC
NC
Q5
D5
NC
NC
NC
NC
NC
NC
Q6
D6
/DOFF
NC
NC
NC
NC
NC
NC
Q7
D7
NC
NC
NC
NC
NC
NC
NC
VSS
D10
Q10
Q2
/CQ
Q18
D18
D27
Q27
Q19
D19
D28
Q28
Q20
D20
D29
Q29
Q21
D21
D30
Q30
Q22
D22
/DOFF
D31
Q31
Q23
D23
D32
Q32
Q24
D24
D33
Q33
Q25
D25
D34
Q34
9N
11L
11M
9L
10L
11K
10K
9J
D2
D11
Q11
Q3
NC
Q10
D10
NC
D3
D12
Q12
Q4
NC
9K
Q11
D11
NC
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
D4
ZQ
D13
Q13
Q5
NC
Q12
D12
NC
D5
NC
D14
Q14
Q6
Q13
D13
/DOFF
NC
D6
D15
Q15
Q7
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
NC
Q14
D14
NC
D7
D16
Q16
Q8
NC
9D
Q15
D15
NC
11B
11C
9B
10B
11A
10A
9A
D8
D17
Q17
CQ
NC
SA
NC
Q16
D16
NC
NC
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 21 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Signal names
Signal names
Bit #
Ball ID
x9
Q8
D8
NC
NC
SA
SA
x18
Q17
D17
NC
NC
SA
x36
Q26
D26
D35
Q35
SA
Bit #
105
106
107
108
109
Ball ID
4P
5P
5N
5R
x9
SA
SA
SA
SA
x18
SA
SA
SA
SA
x36
SA
SA
SA
SA
99
3P
2N
2P
1P
3R
4R
100
101
102
103
104
INTERNAL INTERNAL INTERNAL
SA
SA
Notes: In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable
operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except
EXTEST, SAMPLE-Z).
4. ZQ must be driven to VDDQ supply to ensure consistent results.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 22 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
ID Register
Part
Revision number
(31:29)
Type number
(28:12)
Vendor JEDEC code
(11:1)
Start bit
(0)
0 0MMM 0WW0 10Q0 B0S0
0 0010 0110 1010 0010
0 0010 0100 1010 0010
0 0010 0000 1010 0010
1
1
R1Q2A3636B
R1Q2A3618B
R1Q2A3609B
000
000
000
0100 0100 011
0100 0100 011
0100 0100 011
1
Notes: 1. Type number
MMM :Density
011:72Mb,
11: x 36,
010:36Mb,
10: x 18,
001:18Mb
00: x 9,
WW :Organization
01: x 8
Q
B
S
:QDR/DDR
:Burst lengths
:I/O
1: QDR,
1: 4-word burst,
1: Separate I/O,
0: DDR
0: 2-word burst
0: Common I/O
TAP Controller State Diagram
1
Test Logic Reset
0
1
1
1
Select DR Scan
Select IR Scan
Run Test/Idle
0
0
0
1
1
Capture DR
Capture IR
0
0
0
0
Shift DR
Shift IR
1
1
1
1
Exit1 DR
Exit1 IR
0
0
0
0
Pause DR
Pause IR
1
1
0
0
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 23 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Package Dimensions
R1Q2A3636B/R1Q2A3618B/ R1Q2A3609B (PLBG0165FB-A)
JEITA Package Code
RENESAS Code
PLBG0165FB-A
Previous Code
BP-165A
MASS[Typ.]
0.7g
P-LBGA165-15x17-1.00
D
A
B
INDEX
y1
S
S
y
S
e
R
P
N
M
L
Dimension in Millimeters
Reference
Symbol
Min
Nom
15.00
17.00
Max
15.10
17.10
K
J
D
E
14.90
16.90
H
G
F
v
w
E
D
C
B
A
A
1.34
0.27
1.40
0.32
1.00
0.50
1.46
0.37
A1
e
b
0.45
0.55
0.20
0.15
0.25
x
1
2
3
4
5
6
7
8
9
10 11
y
φ b
φ
φ
×
M
S
A
S
B
y1
SD
SE
ZD
ZE
0.07 M
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 24 of 24
Revision History
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Data Sheet
Rev.
Date
Contents of Modification
Description
Page
0.01
0.02
Jan.31, 2008
Feb.29,2008
Initial issue
P7
DLL Constraints
2.the lower end of the frequency at which the DLL can operate is 119MHz
AC characteristics
Average clock cycle time is enlarged
P14
P2
tKHKH(-40)(max) 8.40ns, tKHKH(-50)(max) 8.40ns, tKHKH(-60)(max) 8.40ns
0.03
Apr.11,2008
Ordering Infomatuon: Adding Part Number and Marking Name
1.Part Number
(9) R: 1stGeneration,A: 2ndGeneration,B: 3rdGeneration
(10:11) BG: Package type=BGA
(12:13) 60: Cycle time=6.0 ns,50 : Cycle time=5.0 ns,40: Cycle time=4.0 ns
33: Cycle time=3.3 ns
(14) R: Temperature range= 0°C∼ 70°C,I: Temperature range= -40°C∼ 85°C
(15) B: Pb-free,T: Tape&Reel,S: Pb-free and Tape&Reel
None: Standard (Pb and Tray)
(16) 0 to 9 , A to Z: Renesas internal use
2.Marking Name
Marking Name(0:14) =Part Number (0:14)
------------Pb
Marking Name(0:16) =Part Number (0:14)+Bx------------Pb-free (0∼ 9 , A ∼Z)
(Example)
R1Q2A3609BBG-60R
------------Pb
R1Q2A3609BBG-60RB0 ------------Pb-free
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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