R1Q5A3609ABG-40R [RENESAS]
IC,SYNC SRAM,DDR,4MX9,CMOS,BGA,165PIN,PLASTIC;
| 型号： | R1Q5A3609ABG-40R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SYNC SRAM,DDR,4MX9,CMOS,BGA,165PIN,PLASTIC 双倍数据速率 静态存储器 |
| 文件： | 总26页 (文件大小：1537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1Q5A3636/R1Q5A3618/R1Q5A3609
36-Mbit DDRII SRAM
4-word Burst
REJ03C0297-0002
Preliminary
Rev. 0.02
Feb. 22, 2007
Description
The R1Q5A3636 is a 1,048,576-word by 36-bit, the R1Q5A3618 is a 2,097,152-word by 18-bit, and the R1Q5A3609 is
a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using
full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All
input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These
products are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
•
•
•
•
•
•
•
•
1.8 V 0.1 V power supply for core (VDD
1.4 V to VDD power supply for I/O (VDDQ
)
)
DLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
•
•
•
•
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/
5.0 ns (200 MHz)/6.0 ns (167 MHz)
•
•
Simple control logic for easy depth expansion
JTAG boundary scan
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications.
Rev.0.02 Feb. 22, 2007 page 1 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Ordering Information
Type No.
Organization
Cycle time
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
Clock frequency
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Package
Notes
R1Q5A3636ABG-30R
R1Q5A3636ABG-33R
R1Q5A3636ABG-40R
R1Q5A3636ABG-50R
R1Q5A3636ABG-60R
R1Q5A3618ABG-30R
R1Q5A3618ABG-33R
R1Q5A3618ABG-40R
R1Q5A3618ABG-50R
R1Q5A3618ABG-60R
R1Q5A3609ABG-30R
R1Q5A3609ABG-33R
R1Q5A3609ABG-40R
R1Q5A3609ABG-50R
R1Q5A3609ABG-60R
Notes: 1. Type No.
1-M word
× 36-bit
Plastic FBGA 165-pin
PLBG0165FB-A
2-M word
× 18-bit
4-M word
× 9-bit
(0:1) R1 : Renesas Memory prefix
(2:3) Q2 : QDRII 2-word Burst SRAM
Q3 : QDRII 4-word Burst SRAM
Q4 : DDRII 2-word Burst SRAM
Q5 : DDRII 4-word Burst SRAM
Q6 : DDRII 2-word Burst SRAM Separate I/O
A : VDD=1.8V
(4)
(5:6) 36 : Density = 36Mb
72 : Density = 72Mb
(7:8) 36 : Organization = x36
18 : Organization = x18
09 : Organization = x9
Pin Arrangement
R1Q5A3636 series
1
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
/BW2
/BW3
SA
6
7
8
9
SA
10
NC
NC
DQ17
NC
DQ15
NC
11
CQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ27
NC
DQ29
NC
DQ30
DQ31
VREF
NC
NC
DQ33
NC
DQ35
NC
TCK
SA
R-/W
SA
VSS
/K
K
/BW1
/BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
/LD
SA
VSS
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
VREF
DQ13
DQ12
NC
DQ11
NC
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
DQ9
TMS
/C
(Top View)
Rev.0.02 Feb. 22, 2007 page 2 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
R1Q5A3618 series
1
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
VSS
DQ9
NC
NC
NC
DQ12
NC
VREF
NC
NC
DQ15
NC
3
4
5
/BW1
NC
SA
6
7
NC
8
9
SA
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
SA
NC
NC
R-/W
SA
VSS
/K
K
/LD
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
/BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
DQ10
DQ11
NC
DQ13
VDDQ
NC
DQ14
NC
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
NC
NC
TCK
DQ16
DQ17
SA
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
/C
(Top View)
R1Q5A3609 series
1
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
7
8
9
SA
10
SA
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ7
NC
NC
NC
TCK
SA
R-/W
SA
VSS
NC
NC
SA
/K
K
NC
/BW
SA
/LD
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
DQ5
NC
DQ6
VDDQ
NC
NC
NC
NC
NC
DQ8
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
NC
NC
VREF
DQ2
NC
NC
NC
NC
NC
TMS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
VSS
SA
SA
SA
SA
SA
SA
/C
(Top View)
Notes: 1. Note that 7C is not SA1. The ×9 product does not permit random start address on the two least significant
address bit. SA0, SA1 = 0 at the start of each address.
:
2. Address expansion order for future higher density SRAMs (i.e. 72Mb → 144Mb →288Mb): (9A → 3A → 10A)
→ 2A → 7A → 5B.
Rev.0.02 Feb. 22, 2007 page 3 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Pin Description
Name
I/O type
Descriptions
Notes
SAx
Input
Synchronous address inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. All transactions operate on a burst-of-four
words (two clock periods of bus activity). SA0 and SA1 are used as the lowest two
address bits for burst READ and burst WRITE operations permitting a random burst
start address on ×18 and ×36 devices. These inputs are ignored when device is
deselected or once burst operation is in progress.
/LD
Input
Input
Input
Synchronous load: This input is brought low when a bus cycle sequence is to be
defined. This definition includes address and READ / WRITE direction. All
transactions operate on a burst-of-four data (two clock periods of bus activity).
Synchronous read / write Input: When /LD is low, this input designates the access
type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-
/W must meet the setup and hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and /K for each of the two rising edges comprising
the WRITE cycle. See Byte Write Truth Table for signal to data relationship.
R-/W
/BWx
K, /K
C, /C
Input
Input
Input clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning device output
data. The rising edge of /C is used as the output timing reference for first and third
output data. The rising edge of C is used as the output timing reference for second
and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may
be tied high to force the use of K and /K as the output reference clocks instead of
having to provide C and /C clocks. If tied high, C and /C must remain high and not to
be toggled during device operation. These balls cannot remain VREF level.
/DOFF
ZQ
Input
Input
DLL disable: When low, this input causes the DLL to be bypassed for stable, low
frequency operation.
Output impedance matching input: This input is used to tune the device outputs to the
system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ,
where RQ is a resistor from this ball to ground. This ball can be connected directly to
V
DDQ, which enables the minimum impedance mode. This ball cannot be connected
directly to VSS or left unconnected.
TMS
TDI
TCK
Input
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the
JTAG function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG
function is not used in the circuit.
DQ0 to
DQn
Input/
output
Synchronous data I/Os: Input data must meet setup and hold times around the rising
edges of K and /K. Output data is synchronized to the respective C and /C, or to the
respective K and /K if C and /C are tied high. The ×9 device uses DQ0 to DQ8.
Remaining signals are not used. The ×18 device uses DQ0 to DQ17. Remaining
signals are not used. The ×36 device uses DQ0 to DQ35.
CQ,
/CQ
Output
Synchronous echo clock outputs: The edges of these outputs are tightly matched to
the synchronous data outputs and can be used as a data valid indication. These
signals run freely and do not stop when DQ tristates.
TDO
VDD
Output
Supply
IEEE 1149.1 test output: 1.8 V I/O level.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for
range.
VDDQ
Supply
Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also
permissible. See DC Characteristics and Operating Conditions for range.
VSS
VREF
Supply
Power supply: Ground.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve
system noise margin. Provides a reference voltage for the HSTL input buffers.
Rev.0.02 Feb. 22, 2007 page 4 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Name
I/O type
Descriptions
Notes
NC
No connect: These signals are not internally connected. These signals can be left
floating or connected to ground to improve package heat dissipation.
Notes: 1. All power supply and ground balls must be connected for proper operation of the device.
Block Diagram (R1Q5A3636 / R1Q5A3618 series)
SA1
SA0
SA1'
SA0'
Burst
Logic
Output
Control
Logic
20/21
20/21
SA
SA0''
SA0'''
Address
Registry
and
ZQ
/LD
R-/W
K
Logic
CQ, /CQ
2
72
/36
72
/36
72
/36
R-/W
/LD
DQ
36/18
Memory
Array
4/2
Data
Registry
and
/BWx
K
Logic
/K
36/18
C,/C
or
K,/K
C
K
Block Diagram (R1Q5A3609 series)
20
20
SA
Address
Registry
and
ZQ
/LD
R-/W
K
Logic
CQ, /CQ
2
R-/W
/LD
DQ
9
18
18
18
Memory
Array
1
Data
Registry
and
/BWx
K
Logic
/K
9
C,/C
or
K,/K
C
K
Rev.0.02 Feb. 22, 2007 page 5 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
General Description
Power-up and Initialization Sequence
The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
After the stable power, there are three possible sequences.
1. Sequence when DLL disable (/DOFF pin fixed low)
Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations,
including JTAG functions, to become normal.
2a. Sequence controlled by /DOFF pin when DLL enable Just after the stable power and clock (K, /K, C, /C), take
/DOFF to be high.
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable If /DOFF pin is fixed high with
unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.).
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
Notes: 1. After K or C clock is stopped, clock recovery cycles (1024 NOP cycles (min.)) are required for read/write
operations to become normal.
2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL
reset again, the 1024 NOP cycles (min.) are needed to lock the DLL.
1. Sequence when DLL disable (/DOFF pin fixed low)
Unstable
Stable
Normal
Status
Power Up
NOP Stage
Clock Stage
Clock Stage
Operation
VDD
VDDQ
VREF
VIN
1024cycle min.
K, /K
(C, /C)
2a. Sequence controlled by /DOFF pin when DLL enable
Unstable
Stable
NOP & DLL
Normal
Status
Power Up
Clock Stage
Clock Stage
Locking Stage
Operation
VDD
VDDQ
VREF
/DOFF
1024cycle min.
K, /K
(C, /C)
Rev.0.02 Feb. 22, 2007 page 6 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Unstable
Stop
NOP & DLL
Normal
Status
Power Up
Clock Stage
Clock Stage
Locking Stage
Operation
VDD
VDDQ
VREF
/DOFF
30ns min.
1024cycle min.
K, /K
(C, /C)
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as
TKC var.
2. The lower end of the frequency at which the DLL can operate is 100MHz.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5
pF.
Burst Sequence
Linear Burst Sequence Table (R1Q5A3636 / R1Q5A3618 series)
SA1, SA0
SA1, SA0
SA1, SA0
SA1, SA0
Notes
External address
0, 0
0, 1
1, 0
1, 1
0, 1
1, 0
1, 1
0, 0
1, 0
1, 1
0, 0
0, 1
1, 1
0, 0
0, 1
1, 0
1st internal burst address
2nd internal burst address
3rd internal burst address
Rev.0.02 Feb. 22, 2007 page 7 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
K Truth Table
Operation
Write Cycle:
K
/R
/W
D or Q
↑
L
L
Data in
Load address, input write data
on consecutive K and /K rising
edges
Input
D(A1)
D(A2)
D(A3)
D(A4)
data
Output
clock
K(t+1)↑
/K(t+1)↑
K(t+2)↑
/K(t+2)↑
Read Cycle:
↑
L
H
Data out
Load address, output read
data on consecutive C and /C
rising edges
Output
Q(A1)
Q(A2)
Q(A3)
Q(A4)
data
Output
clock
/C(t+1)↑
C(t+2)↑
/C(t+2)↑
C(t+3)↑
NOP (No operation)
Standby (Clock stopped)
↑
H
×
×
×
High-Z
Previous state
Stopped
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges,
except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and
/C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refer to the 1st, 2nd and 3rd
internal burst address, respectively, in accordance with the linear burst sequence.
Byte Write Truth Table (x36)
Operation
Write D0 to D35
K
↑
↑
↑
↑
↑
↑
/K
↑
↑
↑
↑
↑
↑
/BW0
L
L
L
L
H
H
H
H
H
H
H
H
/BW1
L
L
H
H
L
L
H
H
H
H
H
H
/BW2
L
L
H
H
H
H
L
L
H
H
H
H
/BW3
L
L
H
H
H
H
H
H
L
L
H
H
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Rev.0.02 Feb. 22, 2007 page 8 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Byte Write Truth Table (x18)
Operation
Write D0 to D17
K
↑
↑
↑
↑
/K
↑
↑
↑
↑
/BW0
/BW1
L
L
L
L
L
H
H
L
L
H
H
Write D0 to D8
Write D9 to D17
Write nothing
L
H
H
H
H
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x9)
Operation
Write D0 to D8
K
↑
↑
/K
↑
↑
/BW
L
L
H
H
Write nothing
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Rev.0.02 Feb. 22, 2007 page 9 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Bus Cycle State Diagram
/LD = H & Count = 4
Count
= 2
R-/W = L
Write Double
Count
= Count + 2
Advance
Address
by Two
/LD = L
&
Count = 4
Always
/LD = H
/LD = L
Load New
Address
Count = 0
NOP
Supply
voltage
provided
Count
= 2
R-/W = H
Read Double
Count
= Count + 2
Advance
Address
by Two
/LD = L
&
Count = 4
Power
Up
Always
/LD = H & Count = 4
Notes: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated at
the end of this sequence (burst count = 4).
2. State machine control timing sequence is controlled by K.
Absolute Maximum Ratings
Parameter
Input voltage on any ball
Input/output voltage
Core supply voltage
Output supply voltage
Junction temperature
Storage temperature
Symbol
VIN
VI/O
VDD
VDDQ
Tj
Rating
−0.5 to VDD + 0.5 (2.5 V max.)
−0.5 to VDDQ + 0.5 (2.5 V max.)
−0.5 to 2.5
Unit
V
V
V
V
Notes
1, 4
1, 4
1, 4
1, 4
−0.5 to VDD
+125 (max)
−55 to +125
°C
°C
TSTG
Notes: 1. All voltage is referenced to VSS
.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables
after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the
instantaneous value of VDDQ
.
Rev.0.02 Feb. 22, 2007 page 10 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Power supply voltage --core
Power supply voltage --I/O
Input reference voltage --I/O
Input high voltage
Symbol
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
Min
1.7
1.4
0.68
REF + 0.1
Typ
1.8
1.5
0.75
Max
1.9
VDD
0.95
DDQ + 0.3
Unit
Notes
V
V
V
V
V
1
V
V
2, 3
2, 3
Input low voltage
−0.3
VREF − 0.1
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
.
2. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD
.
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH
(min).
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS
.
3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.
DC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
−60
−30
Max
700
750
800
−33
Max
650
700
750
−40
Max
600
650
700
−50
Max
550
600
650
Parameter
Symbol
IDD
Max
500
550
600
Unit
mA
mA
mA
Notes
Operating
(×9)
(×18)
(×36)
1, 2, 3
1, 2, 3
1, 2, 3
supply
IDD
IDD
current
(READ /
WRITE)
Standby
supply
current
(NOP)
(×9 /
×18 /
×36)
ISB1
350
330
300
280
260
mA
2, 4, 5
Parameter
Symbol
Min
Max
Unit
µA
µA
V
V
V
Test conditions
Notes
10
11
8, 9
8, 9
8, 9
8, 9
Input leakage current
Output leakage current
Output high voltage
ILI
ILO
VOH (Low)
VOH
VOL (Low)
VOL
−2
−5
2
5
VDDQ
V
DDQ −0.2
VDDQ/2 −0.08
VSS
|IOH| ≤ 0.1 mA
VDDQ/2 +0.08
0.2
VDDQ/2 +0.08
Note 6
Output low voltage
I
OL ≤ 0.1 mA
VDDQ/2 −0.08
V
Note 7
Notes: 1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
3. Operating supply currents are measured at 100% bus utilization.
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I standards.
10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Rev.0.02 Feb. 22, 2007 page 11 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Thermal Resistance
Parameter
Junction to Ambient
Junction to Case
Symbol
θJA
Typ
24.5
5.6
Unit
°C/W
°C/W
Notes
θJC
Note: These parameters are calculated under the condition of wind velocity = 1 m/s.
Capacitance
(Ta = +25°C, f=1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter
Input capacitance
Clock input capacitance
Symbol
CIN
CCLK
CI/O
Min
Typ
Max
Unit
Test conditions
Notes
4
5
6
5
6
7
pF
pF
pF
VIN = 0 V
VCLK = 0 V
VI/O = 0 V
1, 2
1, 2
1, 2
Input/output capacitance (D, Q, ZQ)
Notes: 1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V)
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test points
0.75 V
0.25 V
Output waveform
VDDQ /2
Test points
VDDQ /2
Output load condition
0.75 V
VDDQ /2
VREF
50 Ω
Z0 = 50 Ω
Q
SRAM
250 Ω
ZQ
Rev.0.02 Feb. 22, 2007 page 12 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
AC Operating Conditions
Parameter
Input high voltage
Input low voltage
Symbol
VIH (AC)
VIL (AC)
Min
VREF + 0.2
Typ
Max
REF − 0.2
Unit
V
V
Notes
1, 2, 3, 4
1, 2, 3, 4
V
Notes: 1. All voltages referenced to VSS (GND).
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less
than tKHKL (min) or operate at cycle rates less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)
.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
.
Rev.0.02 Feb. 22, 2007 page 13 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
AC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
-30
-33
-40
-50
-60
Parameter Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Average
clock cycle
time (K, /K,
C, /C)
tKHKH
3.00
3.47
3.30
4.20
4.00
5.25
5.00
6.30
6.00
7.88
ns
Clock
phase jitter
(K, /K, C,
/C)
tKC var
0.20
0.20
0.20
0.20
0.20
ns
3
Clock high
time (K, /K,
C, /C)
Clock low
time (K, /K,
C, /C)
Clock to
/clock (K to
/K, C to /C)
tKHKL
tKLKH
tKH/KH
t/KHKH
1.20
1.20
1.35
1.35
1.32
1.32
1.49
1.49
1.60
1.60
1.80
1.80
2.00
2.00
2.20
2.20
2.40
2.40
2.70
2.70
ns
ns
ns
ns
/Clock to
clock (/K to
K, /C to C)
Clock to
data clock
(K to C, /K
to /C)
tKHCH
0
1.30
0
1.45
0
1.80
0
2.30
0
2.80
ns
DLL lock
tKC lock
1,024
30
1,024
30
1,024
30
1,024
30
1,024
30
Cycle
ns
2
7
time (K, C)
K static to
DLL reset
tKC reset
C, /C high
to output
valid
C, /C high
to output
hold
C, /C high
to echo
clock valid
C, /C high
to echo
clock hold
CQ, /CQ
high to
output valid
CQ, /CQ
high to
output hold
C, /C high
to output
high-Z
C, /C high
to output
low-Z
tCHQV
−0.45
0.45
−0.45
0.45
−0.45
0.45
−0.45
0.45
−0.50
0.50
ns
ns
ns
ns
ns
ns
ns
ns
tCHQX
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
0.45
0.45
0.45
0.45
0.50
−0.45
−0.45
−0.45
−0.45
−0.50
0.25
0.27
0.30
0.35
0.40
4, 7
4, 7
5
−0.25
−0.27
−0.30
−0.35
−0.40
0.45
0.45
0.45
0.45
0.50
tCHQX1
−0.45
−0.45
−0.45
−0.45
−0.50
5
Rev.0.02 Feb. 22, 2007 page 14 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
-30
-33
-40
-50
-60
Parameter Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Address
valid to K
rising edge
tAVKH
0.40
0.40
0.50
0.60
0.70
ns
1
Control
inputs valid
to K rising
edge
Data-in
valid to K,
/K rising
edge
K rising
edge to
address
hold
tIVKH
0.40
0.28
0.40
0.40
0.28
0.40
0.30
0.40
0.40
0.30
0.50
0.35
0.50
0.50
0.35
0.60
0.40
0.60
0.60
0.40
0.70
0.50
0.70
0.70
0.50
ns
ns
ns
ns
ns
1
1
1
1
1
tDVKH
tKHAX
tKHIX
K rising
edge to
control
inputs hold
K, /K rising
edge to
data-in
hold
tKHDX
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD
and input clock are stable. It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo
clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV
7. These parameters are sampled.
.
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. If C, /C are tied high, K, /K become the references for C, /C timing parameters.
4. VDDQ is +1.5 V DC.
5. Control signals are /LD, R-/W, /BW, /BW0, /BW1, /BW2 and /BW3.
BWn signals must operate at the same timing as Data in.
Rev.0.02 Feb. 22, 2007 page 15 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Timing Waveforms
Read and Write Timing
Rev.0.02 Feb. 22, 2007 page 16 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Notes: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0,
etc.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32, etc. Write data is forwarded
immediately as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data in.
5. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it
may be required to prevent bus contention.
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an
undriven input will produce a response identical to the application of a logic 1,and may be left unconnected. But they
may also be tied to VDD through a 1kΩ resistor.TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
Notes
TCK
2R
Test clock input. All inputs are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test mode select. This is the command input for the TAP controller state
machine.
Test data input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling edge of TCK.
This is the output side of the serial registers placed between TDI and TDO.
Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V 0.1V)
Parameter
Input high voltage
Input low voltage
Input leakage current
Output leakage current
Symbol
VIH
Min
+1.3
−0.3
−5.0
−5.0
Typ
Max
VDD + 0.3
+0.5
Unit
Notes
V
V
VIL
ILI
ILO
+5.0
+5.0
µA
µA
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDD,
output disabled
IOLC = 100 µA
IOLT = 2 mA
|IOHC| = 100 µA
|IOHT| = 2 mA
Output low voltage
Output high voltage
VOL1
VOL2
VOH1
VOH2
1.6
1.4
0.2
0.4
V
V
V
V
Notes: 1. All voltages referenced to VSS (GND).
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms.
3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
4. ZQ: VIH = VDDQ
.
Rev.0.02 Feb. 22, 2007 page 17 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
TAP AC Test Conditions
Parameter
Temperature
Input timing measurement reference levels
Input pulse levels
Symbol
Ta
VREF
VIL, VIH
tr, tf
Conditions
0 ≤ Ta ≤ +70
0.9
0 to 1.8
≤ 1.0
0.9
0.9
See figures
Unit
°C
V
V
ns
V
Notes
Input rise/fall time
Output timing measurement reference levels
Test load termination supply voltage (VTT)
Output load
V
Input waveform
1.8 V
0.9 V
Test points
0.9 V
0 V
Output waveform
0.9 V
Test points
0.9 V
Output load condition
V
TT = 0.9 V
DUT
50 Ω
Z0 = 50 Ω
TDO
20 pF
External Load at Test
Rev.0.02 Feb. 22, 2007 page 18 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
TAP AC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V)
Parameter
Test clock (TCK) cycle time
TCK high pulse width
TCK low pulse width
Test mode select (TMS) setup
TMS hold
Capture setup
Capture hold
TDI valid to TCK high
TCK high to TDI invalid
TCK low to TDO unknown
TCK low to TDO valid
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
Min
100
40
40
10
10
10
10
10
10
0
Typ
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
tCH
tDVTH
tTHDX
tTLQX
tTLQV
Notes: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
TDI
tMVTH
tTHMX
tTHDX
tDVTH
tTLQV
TDO
tTLQX
tCH
tCS
PI
(SRAM)
Rev.0.02 Feb. 22, 2007 page 19 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Test Access Port Registers
Register name
Instruction register
Bypass register
Length
3 bits
1 bits
Symbol
IR [2:0]
BP
Notes
ID register
Boundary scan register
32 bits
109 bits
ID [31:0]
BS [109:1]
TAP Controller Instruction Set
IR2 IR1 IR0
Instruction
Description
The EXTEST instruction allows circuitry external to the component
Notes
0
0
0
EXTEST
1, 2, 3
package to be tested. Boundary scan register cells at output balls are
used to apply test vectors, while those at input balls capture test results.
Typically, the first test vector to be applied using the EXTEST instruction
will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the Update-IR state of EXTEST, the output
driver is turned on and the PRELOAD data is driven onto the output balls.
0
0
0
1
1
0
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID
register when the controller is in capture-DR mode and places the ID
register between the TDI and TDO balls in shift-DR mode. The IDCODE
instruction is the default instruction loaded in at power up and any time
the controller is placed in the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM
outputs are forced to an inactive drive state (high-Z), moving the TAP
controller into the capture-DR state loads the data in the RAMs input into
the boundary scan register, and the boundary scan register is connected
between TDI and TDO when the TAP controller is moved to the shift-DR
state.
SAMPLE-Z
3, 4
0
1
1
0
1
0
RESERVED
SAMPLE
The RESERVED instructions are not implemented but are reserved for
future use. Do not use these instructions.
When the SAMPLE instruction is loaded in the instruction register,
3
(/PRELOAD) moving the TAP controller into the capture-DR state loads the data in the
RAMs input and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for
the TAP to attempt to capture the I/O ring contents while the input buffers
are in transition (i.e., in a metastable state). Although allowing the TAP to
SAMPLE metastable input will not harm the device, repeatable results
cannot be expected. Moving the controller to shift-DR state then places
the boundary scan register between the TDI and TDO balls.
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
BYPASS
The BYPASS instruction is loaded in the instruction register when the
bypass register is placed between TDI and TDO. This occurs when the
TAP controller is moved to the shift-DR state. This allows the board level
scan path to be shortened to facilitate testing of other devices in the scan
path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing
the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required to return from the SAMPLE-Z instruction.
Rev.0.02 Feb. 22, 2007 page 20 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Boundary Scan Order Boundary Scan Order
Signal names
Signal names
x18
Bit #
1
Ball ID
6R
x9
x18
/C
C
SA
SA
SA
SA
SA
SA
x36
/C
C
SA
SA
SA
SA
SA
SA
Bit #
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Ball ID
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
x9
SA
SA
DNU
/LD
DNU
/BW
K
x36
SA
/C
SA
SA1
SA0
/LD
DNU
/BW0
K
2
6P
C
SA1
3
6N
SA
SA0
4
7P
SA
/LD
5
6
7
7N
7R
8R
SA
SA
SA
/BW1
/BW0
K
8
8P
SA
/K
/K
/K
9
9R
SA
SA
SA
DNU
DNU
R-/W
SA
SA
SA
DNU
/BW1
R-/W
SA
SA
SA
/BW3
/BW2
R-/W
SA
SA
SA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
11P
10P
10N
9P
10M
11N
9M
DQ0
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ1
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ2
DNU
ZQ
DNU
DNU
DNU
DNU
DNU
DNU
DQ3
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ4
DNU
DNU
DNU
CQ
DQ0
DNU
DNU
DNU
DQ1
DNU
DNU
DNU
DQ2
DNU
DNU
DNU
DQ3
DNU
DNU
DNU
DQ4
DNU
ZQ
DNU
DNU
DQ5
DNU
DNU
DNU
DQ6
DNU
DNU
DNU
DQ7
DNU
DNU
DNU
DQ8
DNU
DNU
DNU
CQ
DQ0
DQ9
DNU
DNU
DQ11
DQ10
DNU
DNU
DQ2
DQ1
DNU
DNU
DQ3
DQ12
DNU
DNU
DQ13
DQ4
ZQ
DNU
DNU
DQ5
DQ14
DNU
DNU
DQ6
DQ15
DNU
DNU
DQ17
DQ16
DNU
DNU
DQ8
DQ7
DNU
DNU
CQ
VSS
/CQ
VSS
/CQ
VSS
/CQ
9N
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ5
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ6
DNU
/DOFF
DNU
DNU
DNU
DNU
DNU
DNU
DQ7
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ9
DNU
DNU
DNU
DQ10
DNU
DNU
DNU
DQ11
DNU
DNU
DNU
DQ12
DNU
DNU
DNU
DQ13
DNU
/DOFF
DNU
DNU
DQ14
DNU
DNU
DNU
DQ15
DNU
DNU
DNU
DQ16
DNU
DNU
DNU
DQ27
DQ18
DNU
DNU
DQ19
DQ28
DNU
DNU
DQ20
DQ29
DNU
DNU
DQ30
DQ21
DNU
DNU
DQ22
DQ31
/DOFF
DNU
DNU
DQ23
DQ32
DNU
DNU
DQ33
DQ24
DNU
DNU
DQ25
DQ34
DNU
DNU
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
9D
11B
11C
9B
10B
11A
10A
9A
SA
SA
SA
SA
DNU
SA
Rev.0.02 Feb. 22, 2007 page 21 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Signal names
Signal names
Bit #
Ball ID
x9
x18
DQ17
DNU
DNU
DNU
SA
x36
DQ26
DQ35
DNU
DNU
SA
Bit #
105
106
107
108
109
Ball ID
4P
5P
5N
5R
x9
SA
SA
SA
SA
x18
SA
SA
SA
SA
x36
SA
SA
SA
SA
99
3P
2N
2P
1P
3R
4R
DQ8
DNU
DNU
DNU
SA
100
101
102
103
104
INTERNAL INTERNAL INTERNAL
SA
SA
SA
Notes: In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable
operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except
EXTEST, SAMPLE-Z).
4. ZQ must be driven to VDDQ supply to ensure consistent results.
Rev.0.02 Feb. 22, 2007 page 22 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
ID Register
Part
Revision number
(31:29)
Type number
(28:12)
Vendor JEDEC code
(11:1)
Start bit
(0)
0 0MMM 0WW0 10Q0 B0S0
0 0010 0110 1000 1000
0 0010 0100 1000 1000
0 0010 0000 1000 1000
1
1
R1Q5A3636
R1Q5A3618
R1Q5A3609
000
000
000
0100 0100 011
0100 0100 011
0100 0100 011
1
Notes: 1. Type number
MMM :Density
011:72Mb,
11: x 36,
010:36Mb,
10: x 18,
001:18Mb
00: x 9,
WW :Organization
01: x 8
Q
B
S
:QDR/DDR
:Burst lengths
:I/O
1: QDR,
1: 4-word burst,
1: Separate I/O,
0: DDR
0: 2-word burst
0: Common I/O
TAP Controller State Diagram Package Dimensions
1
Test Logic Reset
0
1
1
1
0
Run Test/Idle
Select DR Scan
Select IR Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
Shift IR
1
0
Shift DR
1
Exit1 DR
0
1
1
Exit1 IR
0
0
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
Rev.0.02 Feb. 22, 2007 page 23 of 24
R1Q5A3636/R1Q5A3618/R1Q5A3609
Package Dimensions
R1Q5A3636/R1Q5A3618/R1Q5A3609 (PLBG0165FB-A)
JEITA Package Code
RENESAS Code
PLBG0165FB-A
Previous Code
BP-165A
MASS[Typ.]
0.7g
P-LBGA165-15x17-1.00
D
A
B
INDEX
y1
S
S
y
S
e
R
P
N
M
L
Dimension in Millimeters
Reference
Symbol
Min
Nom
15.00
17.00
Max
15.10
17.10
K
J
D
E
14.90
16.90
H
G
F
v
w
E
D
C
B
A
A
1.34
0.27
1.40
0.32
1.00
0.50
1.46
0.37
A1
e
b
0.45
0.55
0.20
0.15
0.25
x
1
2
3
4
5
6
7
8
9
10 11
y
φ b
φ
φ
×
M
S
A
S
B
y1
SD
SE
ZD
ZE
0.07 M
Rev.0.02 Feb. 22, 2007 page 24 of 24
Revision History
R1Q5A3636/R1Q5A3618/R1Q5A3609
Data Sheet
Rev.
Date
Contents of Modification
Description
Page
0.01
0.02
Sep. 25, 2006
Feb. 22, 2007
Initial issue
24
Package Dimensions
PLBG0165FC-A to PLBG0165FB-A
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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