R1RW0416DSB-2LR [RENESAS]
4M High Speed SRAM (256-kword x 16-bit); 4M高速SRAM （ 256千字×16位）
| 型号： | R1RW0416DSB-2LR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4M High Speed SRAM (256-kword x 16-bit) |
| 文件： | 总16页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1RW0416D Series
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0107-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RW0416D is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. The R1RW0416D
is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3 V
Access time: 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
•
Operating current: 130 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 0.8 mA (max) (L-version)
•
•
•
Data retention current: 0.4 mA (max) (L-version)
Data retention voltage: 2.0 V (min) (L-version)
Center VCC and VSS type pin out
Rev.1.00, Mar.12.2004, page 1 of 14
R1RW0416D Series
Ordering Information
Type No.
Access time
12 ns
Package
R1RW0416DGE-2PR
R1RW0416DGE-2LR
R1RW0416DSB-2PR
R1RW0416DSB-2LR
400-mil 44-pin plastic SOJ (44P0K)
12 ns
12 ns
400-mil 44-pin plastic TSOPII (44P3W-H)
12 ns
Pin Arrangement
44-pin SOJ
44
44-pin TSOP
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
A17
A16
A15
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A6
A7
A8
A9
A6
A7
A8
A9
A10
A10
(Top View)
(Top View)
Rev.1.00, Mar.12.2004, page 2 of 14
R1RW0416D Series
Pin Description
Pin name
A0 to A17
I/O1 to I/O16
CS#
Function
Address input
Data input/output
Chip select
OE#
Output enable
Write enable
Upper byte select
Lower byte select
Power supply
Ground
WE#
UB#
LB#
VCC
VSS
NC
No connection
Rev.1.00, Mar.12.2004, page 3 of 14
R1RW0416D Series
Block Diagram
(LSB)
A14
A13
A12
A5
VCC
VSS
Memory matrix
1024 rows × 32 columns ×
8 blocks × 16 bit
Row
decoder
A6
A7
A11
A10
A3
(4,194,304 bits)
A1
(MSB)
CS
I/O1
.
Column I/O
.
.
Input
data
control
Column decoder
I/O8
CS
I/O9
.
.
.
I/O16
(MSB)
A8 A9 A17 A15 A16 A0 A2 A4
(LSB)
WE#
CS#
LB#
UB#
OE#
CS
Rev.1.00, Mar.12.2004, page 4 of 14
R1RW0416D Series
Operation Table
CS# OE# WE# LB# UB# Mode
VCC current
I/O1−I/O8
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
I/O9−I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
Ref. cycle
H
L
L
L
L
L
L
L
L
L
×
H
L
L
L
L
×
×
×
×
×
×
×
Standby
ISB, ISB1
ICC
H
H
H
H
H
L
×
×
Output disable
Read
L
L
ICC
Read cycle
Read cycle
Read cycle
L
H
L
Lower byte read ICC
Upper byte read ICC
ICC
H
H
L
H
L
Write
ICC
Write cycle
Write cycle
Write cycle
L
L
H
L
Lower byte write ICC
Upper byte write ICC
ICC
Input
High-Z
Input
L
H
H
High-Z
High-Z
L
H
High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
−0.5 to +4.6
−0.5*1 to VCC + 0.5*2
VT
V
PT
1.0
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
°C
°C
°C
−55 to +125
−10 to +85
Storage temperature under bias
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
VCC*3
VSS*4
VIH
Min
3.0
Typ
3.3
0
Max
3.6
0
Unit
V
Supply voltage
0
V
Input voltage
2.0
−0.5*1
VCC + 0.5*2
V
V
VIL
0.8
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
Rev.1.00, Mar.12.2004, page 5 of 14
R1RW0416D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol
|ILI|
Min
Max
2
Unit
µA
Test conditions
VIN = VSS to VCC
VIN = VSS to VCC
Input leakage current
Output leakage current
Operating power supply current
|ILO|
2
µA
ICC
130
mA
Min cycle
CS# = VIL, IOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB
40
5
mA
mA
Min cycle, CS# = VIH,
Other inputs = VIH/VIL
ISB1
f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
1
*
0.8*1
mA
V
Output voltage
VOL
VOH
0.4
IOL = 8 mA
2.4
V
IOH = −4 mA
Note: 1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
CIN
Min
Max
6
Unit
pF
Test conditions
VIN = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
8
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.1.00, Mar.12.2004, page 6 of 14
R1RW0416D Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
1.5 V
RL = 50 Ω
DOUT
319 Ω
DOUT
Zo = 50 Ω
353 Ω
5 pF
30 pF
Output load (B)
(for tCLZ, tOLZ, tBLZ, tCHZ, tOHZ
BHZ, tWHZ, and tOW
Output load (A)
,
t
)
Read Cycle
R1RW0416D
-2
Parameter
Symbol
Min
12
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
tRC
Address access time
tAA
12
12
6
Chip select access time
tACS
tOE
Output enable to output valid
Byte select to output valid
tBA
6
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Byte select to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Byte deselect to output in high-Z
tOH
3
3
0
0
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
1
1
1
1
1
1
6
6
6
Rev.1.00, Mar.12.2004, page 7 of 14
R1RW0416D Series
Write Cycle
R1RW0416D
-2
Min
12
8
Parameter
Symbol
tWC
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
8
8
7
tWP
8
Byte select to end of write
Address setup time
tBW
8
tAS
0
5
6
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
6
tDH
0
tOW
3
1
1
1
tOHZ
tWHZ
6
6
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or
after the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 8 of 14
R1RW0416D Series
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
tRC
Address
Valid address
tAA
tACS
CS#
OE#
1
1
*
tOE
tCHZ
tBA
tOHZ
*
LB#, UB#
1
tBHZ
1
*
tBLZ
*
1
tOLZ
tOH
*
1
tCLZ
*
4
4
*
*
High impedance
DOUT
Valid data
Rev.1.00, Mar.12.2004, page 9 of 14
R1RW0416D Series
Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL)
tRC
Address
Valid address
tAA
tOH
1
tCHZ
*
tACS
CS#
OE#
1
tOE
tOHZ
*
1
tOLZ
*
1
tCLZ
*
4
4
*
*
High impedance
DOUT
Valid data
Rev.1.00, Mar.12.2004, page 10 of 14
R1RW0416D Series
Write Timing Waveform (1) (WE# Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE#*3
CS#*3
tCW
OE#
tBW
LB#, UB#
tOLZ
tOW
tWHZ
tOHZ
High impedance
DOUT
2
*
tDW
tDH
Valid data
DIN
Rev.1.00, Mar.12.2004, page 11 of 14
R1RW0416D Series
Write Timing Waveform (2) (CS# Controlled)
tWC
Valid address
tAW
Address
tWR
tAS
tWP
WE# *3
CS# *3
tCW
OE#
tBW
LB#, UB#
tOLZ
tOW
tWHZ
tOHZ
4
*
High impedance
DOUT
2
*
tDW
tDH
Valid data
DIN
Rev.1.00, Mar.12.2004, page 12 of 14
R1RW0416D Series
Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH)
tWC
Address
Valid address
tAW
tWR
tWP
WE#*3
CS#*3
tCW
tBW
tAS
UB# (LB#)
LB# (UB#)
tBW
tDW
tDH
DIN-UB
(DIN-LB)
Valid data
tDW
tDH
DIN-LB
(DIN-UB)
Valid data
DOUT
High impedance
Rev.1.00, Mar.12.2004, page 13 of 14
R1RW0416D Series
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
CC for data retention
Symbol Min
Max
Unit
Test conditions
VCC ≥ CS# ≥ VCC − 0.2 V,
V
VDR
2.0
V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current
ICCDR
400
µA
VCC = 3 V
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
5
ns
See retention waveform
ms
Low VCC Data Retention Timing Waveform
Data retention mode
tR
tCDR
VCC
3.0 V
VDR
2.0 V
CS#
0 V
V
CC ≥ CS# ≥ VCC – 0.2 V
Rev.1.00, Mar.12.2004, page 14 of 14
Revision History
R1RW0416D Series Data Sheet
Rev. Date
Contents of Modification
Page Description
0.01 Sep. 30, 2003
1.00 Mar.12.2004
Initial issue
Deletion of Preliminary
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