R2A20169NP [RENESAS]

8-bit 12ch D/A Converter with Buffer Amplifiers; 8位12CH D / A转换器与缓冲放大器
R2A20169NP
型号: R2A20169NP
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

8-bit 12ch D/A Converter with Buffer Amplifiers
8位12CH D / A转换器与缓冲放大器

转换器 缓冲放大器
文件: 总10页 (文件大小:299K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Datasheet  
R2A20169NP/SA/SP  
8-bit 12ch D/A Converter with Buffer Amplifiers  
R03DS0020EJ0300  
Rev.3.00  
Jul 25, 2013  
Description  
The R2A20169 is an integrated circuit semiconductor of CMOS structure with 12 channels of built in D/A  
unnecessary and enabling configuration of a system with few component parts.  
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.  
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and  
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements  
unnecessary and enabling configuration of a system with few component parts.  
Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area.  
Features  
· Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB  
· Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD )  
· Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )  
· High output current capacity: +/-1mA or Higher  
· Very small size package line-up: QFN-20 (pin pitch: 0.5mm), TSSOP-20 (pin pitch 0.65mm)  
Application  
· Conversion from digital data to analog control data for home-use and industrial equipment.  
Block Diagram  
Number for TSSOP/SOP package  
Number for QFN package  
GND  
20  
DI  
17  
15  
CLK  
16  
14  
LD  
15  
13  
DO  
14  
12  
Ao12  
Ao11  
Vcc  
11  
9
Ao2  
19  
17  
Ao1  
18  
16  
13  
11  
12  
10  
18  
12-bit shift register  
8-bit upper  
segment R-2R  
D/A converter  
Power on  
reset  
D/A  
D/A  
D/A  
Channel  
decoder  
8
8-bit latch  
8-bit latch  
8-bit latch  
8-bit latch  
12  
8-bit latch  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit latch  
D/A  
8-bit upper  
segment R-2R  
D/A converter  
19  
20  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10  
VrefL  
Ao3  
Ao4  
Ao5  
Ao6  
Ao7  
Ao8  
Ao9  
Ao10  
VrefU  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 1 of 9  
Datasheet  
R2A20169NP/SA/SP  
Pin Arrangement  
R2A20169NP (Top view)  
R2A20169SP/SA (Top view)  
GND  
1
20  
VrefL  
Ao3 2  
Ao4  
19 Ao2  
1
2
3
4
5
15  
14  
13  
12  
Ao4  
Ao5  
Ao6  
Ao7  
Ao8  
DI  
3
18  
17  
16  
15  
14  
Ao1  
DI  
Ao5 4  
Ao6  
CLK  
LD  
Do  
5
CLK  
LD  
Ao7 6  
Ao8  
7
Do  
Ao9 8  
13 Ao12  
11 Ao12  
Ao10 9  
Ao11  
Vcc  
12  
11  
10  
VrefU  
Outline: PRSP0020DD-B[SP]  
PTSP0020JB-A [SA]  
Outline: PWQN0020KB-A [NP]  
Pin Description  
Pin No.  
Pin  
Name  
Function  
[TSSOP  
[QFN]  
/SOP]  
Serial data input terminal.  
(Input serial data with a 12-bit data length.)  
Serial data output terminal  
(Data is sequentially output from the MSB bit.)  
Serial clock input terminal  
(Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.)  
Load terminal  
15  
12  
14  
17  
14  
16  
DI  
Do  
CLK  
13  
15  
LD  
(When High level is input to LD terminal, value in 12-bit shift register is loaded  
into decoder and 8-bit latch.)  
16  
17  
20  
1
18  
19  
2
Ao1  
Ao2  
Ao3  
Ao4  
Ao5  
Ao6  
Ao7  
Ao8  
Ao9  
Ao10  
Ao11  
Ao12  
Vcc  
3
2
4
3
5
8-bit resolution D/A converter output terminals  
(After power-on, all channels are reset and DAC data 00h is output.)  
4
6
5
7
6
8
7
9
10  
11  
9
12  
13  
11  
20  
10  
1
Power supply terminal  
18  
8
GND GND terminal  
VrefU  
VrefL  
D/A converter upper reference voltage input terminal  
D/A converter lower reference voltage input terminal  
19  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 2 of 9  
Datasheet  
R2A20169NP/SA/SP  
Absolute Maximum Ratings  
(Ta= +25deg unless otherwise noted)  
Item  
Symbol  
Conditions  
Ratings  
Unit  
Vcc  
VrefU  
VrefL  
IAO  
Supply voltage  
-0.3 to +6.5  
-0.3 to +6.5  
V
V
D/A converter upper reference voltage  
D/A converter lower reference voltage  
Buffer amplifier output current  
Input voltage  
-0.3 to +6.5  
V
Continuous  
-2.0 to +2.0  
mA  
V
Vin  
-0.3 to Vcc+0.3 <+6.5  
-0.3 to Vcc+0.3 <+6.5  
290(NP) / 150(SA) / 300(SP)  
7.25(NP) / 3.75(SA) / 7.5(SP)  
-30 to +85  
Vo  
Output voltage  
V
Pd  
Power dissipation  
Ta= +85deg  
Ta> +25deg  
mW  
mW/deg  
deg  
deg  
K theta  
Topr  
Tstg  
Thermal derating factor  
Operating temperature  
Storage temperature  
-40 to +125  
Electrical Characteristics  
« Digital Part »  
( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted )  
Limits  
Item  
Symbol  
Test conditions  
Unit  
Min  
Typ  
Max  
5.5  
1.8  
10  
Supply voltage  
Supply current  
Input leak current  
Input low voltage  
Vcc  
Icc  
IILK  
VIL  
2.7  
5.0  
V
mA  
µA  
V
CLK = 1MHz, Vcc =5V, IAO =0µA  
VIN = 0 to Vcc  
-
0.6  
-10  
-
-
-
-
-
-
-
-
0.2Vcc  
-
4.0V < Vcc  
Vcc < 4.0V  
0.5Vcc  
V
Input high voltage  
VIH  
0.8Vcc  
-
V
4.0V < Vcc, IOL =2.0 mA  
Vcc < 4.0V, IOL =1.5 mA  
IOH = -400 µA  
-
0.4  
0.4  
-
V
Output low voltage  
Output high voltage  
VOL  
-
V
VOH  
trVcc  
Vcc – 0.4  
V
Supply voltage  
rise time *1  
Vcc = 0 ® 2.7V  
Vcc = 0 ® 2.7V  
100  
-
-
-
µs  
V
Internal reset  
operating voltage *1  
VccPOR  
1.5  
1.9  
Power supply restart  
interval (Power supply  
t
POR  
Vcc < 0.1V  
1
-
-
ms  
OFF à ON)  
*1  
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly,  
initialize is not operate. So, keep the time period of re-powered on (tPOR).  
(equivalent to trVcc)  
trVcc  
tPOR  
VccPOR  
GND  
Vcc  
Internal  
< 0.1V  
Reset signal  
GND  
Resetting period  
Resetting period  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 3 of 9  
Datasheet  
R2A20169NP/SA/SP  
« Analog Part »  
Item  
( Vcc,VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL=0V, Ta= -30 to +85deg, unless otherwise noted )  
Limits  
Symbol  
Test conditions  
Unit  
Min  
Typ  
Max  
VrefU=5V, VrefL=0V, IAO=0µA,  
Data condition: at maximum current  
Current dissipation  
IrefU  
-
1.5  
3.0  
mA  
Vcc 4.5V  
3.5  
0.7Vcc  
GND  
GND  
0.1  
-
-
-
-
-
-
Vcc  
D/A converter upper  
reference voltage range *2  
VrefU  
V
V
Vcc < 4.5V  
Vcc  
Vcc 4.5V  
Vcc-3.5  
0.3Vcc  
Vcc – 0.1  
Vcc – 0.2  
D/A converter lower  
reference voltage range *2  
VrefL  
Vcc < 4.5V  
IAO = +/- 100 µA  
IAO = +/- 500 µA  
V
V
Buffer amplifier output  
voltage range  
VAO  
0.2  
Upper side saturation voltage = 0.3V,  
Lower side saturation voltage = 0.2V  
Buffer amplifier output  
drive range  
IAO  
-1.0  
-
1.0  
mA  
Differential nonlinearity  
Nonlinearity  
SDL  
SL  
-0.7  
-1.0  
-2.0  
-2.0  
-
-
-
-
-
-
0.7  
1.0  
2.0  
2.0  
0.1  
LSB  
LSB  
LSB  
LSB  
µF  
VrefU = 4.79V,  
VrefL = 0.95V,  
Vcc = 5.5V (15mV/LSB),  
Without load (IAO =0µA)  
Zero code error  
SZERO  
SFULL  
Co  
Full scale error  
Output capacitive load  
Buffer amplifier output  
impedance  
Ro  
-
5.0  
-
ohm  
*2 : The output does not necessary be the value with the reference voltage setting range.  
The output value is determined by the buffer amplifier output voltage range (VAO).  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 4 of 9  
Datasheet  
R2A20169NP/SA/SP  
AC Characteristics  
( Vcc, VrefU = +5V +/-10%, Vcc >VrefU, GND=VrefL = 0V, Ta = -30 to +85deg, unless otherwise noted )  
Limits  
Test conditions  
Unit  
Item  
Symbol  
Min  
Typ  
Max  
Clock frequency  
Clock low pulse width  
Clock high pulse width  
Clock rise time  
fCLK  
tCKL  
tCKH  
tCR  
-
40  
40  
-
1.0  
10  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
-
-
-
-
-
-
-
-
-
-
200  
Clock fall time  
tCF  
-
200  
Data setup time  
Data hold time  
tDCH  
tCHD  
tCHL  
tLDC  
tLDH  
tDO  
4
-
-
30  
40  
40  
40  
-10  
LD setup time  
-
LD hold time  
-
LD high pulse width  
Data output delay time  
-
CL < 100 pF  
50  
Ta=25deg, CL<100pF, VAO: 0.5¬ ® 4.5V,  
D/A output settling time  
tLDD  
-
-
150  
µs  
The time until the output becomes the final  
value of 1/2 LSB.  
Timing Chart  
tCR  
tCKH  
tCF  
CLK  
DI  
tCKL  
tDCH  
tCHD  
tLDH  
tLDC  
tCHL  
LD  
tLDD  
D/A  
output  
tDo  
Do  
output  
(Note) Timing chart above is a schematic representation of the timing of each signal type.  
CLK signal input is High or Low regardless, LD signal High input is enabled.  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 5 of 9  
Datasheet  
R2A20169NP/SA/SP  
Digital Data Format  
Last  
LSB  
First  
MSB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
DAC data  
Channel  
select data  
Channel select data  
D10  
D8  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D11  
0
Chanel Selection  
Don’t care  
Ao1 select  
Ao2 select  
Ao3 select  
Ao4 select  
Ao5 select  
Ao6 select  
Ao7 select  
Ao8 select  
Ao9 select  
Ao10 select  
Ao11 select  
Ao12 select  
Don’t care  
Don’t care  
Don’t care  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC data  
D0  
0
D1  
0
D2  
0
D3  
0
D4  
0
D5  
0
D6  
0
D7  
D/A Output  
0
0
0
0
(VrefU – VrefL) / 256 x 1 + VrefL  
(VrefU – VrefL) / 256 x 2 + VrefL  
(VrefU – VrefL) / 256 x 3 + VrefL  
(VrefU – VrefL) / 256 x 4 + VrefL  
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(VrefU – VrefL) / 256 x 255 + VrefL  
VrefU  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 6 of 9  
Datasheet  
R2A20169NP/SA/SP  
Data Timing Chart ( Model )  
MSB  
LSB  
D0  
D11  
D10  
D9  
D8  
D7  
D2  
D1  
DI  
CLK  
Whether CLK input is “H” or “L”, high  
level input of LD signal is recognized.  
LD  
D/A  
output  
Precaution For use  
· There are three terminals (Vcc, VrefU, VrefL) that should be impressed a constant voltage. When ripple  
or spike noise is input to this terminal, there is fear that the accuracy of D/A conversion becomes lower and  
this IC malfunction. So, when use this IC, please connect capacitor between these terminals (Vcc, VrefU, VrefL)  
and GND for stable D/A conversion.  
· This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when  
connect capacitor ( 0.1µF Max ) among output to GND for every noise elimination.  
Standard Application Circuit  
Vcc  
+
Ao1  
10µF  
VrefU  
+
Ao2  
10µF  
Analog voltage  
LD  
output  
MCU  
CLK  
DI  
Ao11  
Ao12  
VrefL  
+
10µF  
GND  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 7 of 9  
Datasheet  
R2A20169NP/SA/SP  
Package Dimensions  
PWQN0020KB-A [NP]  
PRSP0020DD-B [SP]  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 8 of 9  
Datasheet  
R2A20169NP/SA/SP  
PTSP0020JB-A [SA]  
Ordering Information  
Order part No.  
R2A20169SP#W5  
R2A20169SA#W5  
R2A20169NP#W5  
Package Name Package Code Package type No.  
Packing/Quantity  
SOP-20  
TSSOP-20  
QFN-20  
PRSP0020DD-B  
RTSP0020JB-A  
PWQN0020KB-A  
SP  
SA  
NP  
Embossed Taping/2,000 pcs.  
Embossed Taping/2,000 pcs.  
Embossed Taping/2,500 pcs.  
R03DS0020EJ0300 Rev.3.00  
Jul 25, 2013  
Page 9 of 9  
Notice  
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510  
Renesas Electronics Korea Co., Ltd.  
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea  
Tel: +82-2-558-3737, Fax: +82-2-558-5141  
© 2013 Renesas Electronics Corporation. All rights reserved.  
Colophon 2.2  

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