R2J20656ANP [RENESAS]

Integrated Driver - MOS FET (DrMOS); 集成的驱动程序 - MOS场效应管(的DrMOS )
R2J20656ANP
型号: R2J20656ANP
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Integrated Driver - MOS FET (DrMOS)
集成的驱动程序 - MOS场效应管(的DrMOS )

服务器主板节能技术 驱动
文件: 总16页 (文件大小:143K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Preliminary Datasheet  
R2J20656ANP  
Integrated Driver - MOS FET (DrMOS)  
Description  
R07DS0201EJ0100  
Rev.1.00  
Jan 25, 2011  
The R2J20656ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver  
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this  
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating  
the need for an external SBD for this purpose.  
Features  
Compliant with Intel 6 6 DrMOS Specification.  
Built-in power MOS FET suitable for Notebook, Desktop, Server application.  
Low-side MOS FET with built-in SBD for lower loss and reduced ringing.  
Built-in driver circuit which matches the power MOS FET  
Built-in tri-state input function which can support a number of PWM controllers  
High-frequency operation (above 1 MHz) possible  
VIN operating-voltage range: 27 Vmax  
Large average output current (Max.35 A)  
Achieve low power dissipation  
Controllable driver: Remote on/off  
Zero current detection for a diode emulation operation  
Double thermal protection: Thermal Warning & Thermal Shutdown  
Built-in bootstrapping Switch  
Small package: QFN40 (6 mm 6 mm 0.95 mm)  
Pb-free/Halogen-Free  
Outline  
Integrated Driver-MOS FET (DrMOS)  
QFN40 package 6 mm × 6 mm  
VCIN BOOT  
MOS FET Driver  
CGND VDRV  
GH  
VIN  
1
10  
40  
11  
THWN  
Driver  
Pad  
High-side  
MOS Pad  
DISBL#  
ZCD_EN#  
PWM  
VSWH  
Low-side MOS Pad  
31  
20  
30  
21  
GL PGND  
(Bottom view)  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 1 of 15  
R2J20656ANP  
Preliminary  
Block Diagram  
Driver Chip  
VCIN  
VDRV  
BOOT  
GH  
THWN  
THDN  
Boot  
SW  
THWN  
VIN  
DISBL#  
High Side  
MOS FET  
2 μA  
UVL  
CGND  
Level Shifter  
20 k  
CGND  
VCIN  
Zero  
Current  
Det.  
160 k  
ZCD_EN#  
VSWH  
Overlap  
Protection.  
& Logic  
Low Side  
MOS FET  
VDRV  
VCIN  
Input Logic  
(TTL Level)  
(3 state in)  
PWM  
35 k  
PGND  
CGND  
GL  
Notes: 1. Truth table for the DISBL# pin  
2. Truth table for the ZCD_EN# pin  
DISBL# Input  
"L"  
Driver Chip Status  
Shutdown (GL, GH = "L")  
Shutdown (GL, GH = "L")  
ZCD_EN# Input  
"L"  
Driver Chip Status  
"Diode Emulation Mode"  
"Open"  
"H"  
"Open"  
"Continuous Conduction  
Mode"  
Enable (GL, GH = "Active")  
"H"  
"Continuous Conduction  
Mode"  
3. Output signal from the UVL block  
4. Output signal from the THWN block  
For active  
"H"  
"H"  
Thermal  
Warning  
UVL output  
Logic Level  
Normal  
operating  
For shutdown  
Thermal Warning  
Logic Level  
"L"  
VCIN  
"L"  
T
IC(°C)  
VL  
VH  
TwarnL TwarnH  
5. Truth table for the THDN block  
Driver IC Temp.  
< 150°C  
Driver Chip Status  
Enable (GL, GH = "Active")  
> 150°C  
Shutdown (GL, GH = "L")  
(latch-off)  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 2 of 15  
R2J20656ANP  
Preliminary  
Pin Arrangement  
10  
9
8
7
6
5
4
3
2
1
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
VIN  
VIN  
PWM  
DISBL#  
THWN  
CGND  
GL  
VIN  
CGND  
VIN  
VIN  
VSWH  
PGND  
PGND  
PGND  
PGND  
PGND  
VSWH  
VSWH  
VSWH  
VSWH  
VSWH  
VSWH  
21 22 23 24 25 26 27 28 29 30  
(Top view)  
Note: All die-pads (three pads in total) should be soldered to PCB.  
Pin Description  
Pin Name  
Pin No.  
Description  
Remarks  
ZCD_EN#  
1
Zero current detection enable  
When asserted "L" signal, zero crossing  
detection is enabled  
VCIN  
VDRV  
BOOT  
CGND  
GH  
2
3
4
Control input voltage (+5 V input) Driver Vcc input  
Gate supply voltage (+5 V input) 5 V gate drive  
Bootstrap voltage pin  
Control signal ground  
High-side gate signal  
Input voltage  
To be supplied +5 V through internal switch  
5, 37, Pad  
6
Should be connected to PGND externally  
Pin for monitor  
VIN  
8 to 14, Pad  
VSWH  
PGND  
GL  
7, 15, 29 to 35, Pad Phase output/Switch output  
16 to 28  
36  
Power ground  
Low-side gate signal  
Thermal warning  
Signal disable  
Pin for monitor  
THWN  
DISBL#  
38  
Thermal warning when over 115°C  
39  
Disabled when DISBL# is "L".  
This Pin is pulled low when internal IC over the  
thermal shutdown level, 150°C.  
PWM  
40  
PWM drive logic input  
5 V logic input  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 3 of 15  
R2J20656ANP  
Preliminary  
Absolute Maximum Ratings  
(Ta = 25°C)  
Item  
Symbol  
Pt(25)  
Rating  
Units  
Note  
Power dissipation  
25  
W
1
Pt(110)  
8
Average output current  
Input voltage  
Iout  
35  
A
V
VIN(DC)  
–0.3 to +27  
2
2, 4  
2
VIN(AC)  
30  
Supply voltage & Drive voltage  
Switch node voltage  
VCIN & VDRV  
VSWH(DC)  
VSWH(AC)  
VBOOT(DC)  
VBOOT(AC)  
–0.3 to +6  
V
V
27  
2
30  
2, 4  
2
BOOT voltage  
I/O voltage  
32  
36  
V
V
2, 4  
2, 5  
Vpwm, Vdisble,  
Vlsdbl, Vthwn  
–0.3 to VCIN + 0.3  
THWN/THDN current  
Ithwn, Ithdn  
Tj-opr  
0 to 1.0  
mA  
°C  
Operating junction temperature  
Storage temperature  
–40 to +150  
–55 to +150  
Tstg  
°C  
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.  
2. Rated voltages are relative to voltages on the CGND and PGND pins.  
3. For rated current, (+) indicates inflow.  
4. The specification values indicated "AC" are limited within 10 ns.  
5. VCIN + 0.3 V < 6 V  
Safe Operating Area  
45  
40  
35  
30  
25  
20  
VOUT = 1.3 V  
15  
VIN = 12 V  
10  
5
VCIN = 5 V  
L = 0.45 μH  
Fsw = 1 MHz  
0
0
25  
50  
75  
100  
125  
150  
175  
PCB Temperature (°C)  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 4 of 15  
R2J20656ANP  
Preliminary  
Note  
Recommended Operating Condition  
Item  
Symbol  
Rating  
4.5 to 22  
4.5 to 5.5  
Units  
Input voltage  
VIN  
VCIN & VDRV  
V
V
Supply voltage & Drive voltage  
Electrical Characteristics  
(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)  
Item  
Symbol  
VH  
Min  
4.1  
3.6  
Typ  
4.3  
3.8  
0.5  
49  
Max  
4.5  
4.0  
Units  
V
Test Conditions  
Supply  
VCIN start threshold  
VCIN shutdown threshold  
UVLO hysteresis  
VL  
V
dUVL  
ICIN  
V
VH – VL  
VCIN operating current  
mA  
fPWM = 1 MHz,  
Ton_pwm = 120 ns  
VCIN disable current  
ICIN-DISBL  
150  
A  
DISBL# = 0 V,  
PWM = ZCD_EN# = Open  
PWM  
input  
PWM input high level  
PWM input low level  
PWM input resistance  
PWM input tri-state range  
Shutdown hold-off time  
Enable level  
VH-PWM  
VL-PWM  
RIN-PWM  
VIN-tri  
4.0  
0.8  
25  
V
V
5.0 V PWM interface  
6.5  
1.5  
12.5  
k  
V
PWM = 1 V  
3.2  
5.0 V PWM interface  
1
tHOLD-OFF  
VENBL  
*
150  
ns  
V
DISBL#  
input  
2.0  
Disable level  
VDISBL  
0.8  
5.0  
1.0  
V
Input current  
IDISBL  
2.0  
0.5  
A  
k  
V
DISBL# = 1 V  
1
THDN on resistance  
RTHDN  
*
0.2  
2.0  
DISBL# = 0.2 V  
ZCD_EN# ZCD disable level  
ZCD enable level  
Vzcddisbl  
Vzcden  
0.8  
–12  
130  
V
Input current  
Izcden  
–52  
100  
–25  
115  
15  
A  
°C  
°C  
k  
A  
°C  
ZCD_EN# = 1 V  
1
Thermal  
warning  
Warning temperature  
Temperature hysteresis  
THWN on resistance  
THWN leakage current  
Shutdown temperature  
TTHWN  
*
Driver IC temperature  
1
THYS  
RTHWN  
ILEAK  
Tstdn *1  
*
1
*
0.2  
0.5  
1.0  
1.0  
THWN = 0.2 V  
THWN = 5 V  
Thermal  
130  
150  
Driver IC temperature  
shutdown  
Note: 1. Reference values for design. Not 100% tested in production.  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 5 of 15  
R2J20656ANP  
Preliminary  
Typical Application  
4.5 to 22 V  
+5 V  
VCIN VDRV BOOT GH  
THWN  
VIN  
DISBL# R2J20656  
VSWH  
ANP  
ZCD_EN#  
PGND  
GL  
PWM  
CGND  
VCIN VDRV BOOT GH  
THWN  
VIN  
DISBL# R2J20656  
VSWH  
ANP  
ZCD_EN#  
PGND  
GL  
PWM  
CGND  
PWM1  
+1.3 V  
PWM2  
PWM  
Control  
PWM3  
Circuit  
VCIN VDRV BOOT GH  
PWM4  
THWN  
VIN  
DISBL# R2J20656  
VSWH  
ANP  
Power GND Signal GND  
ZCD_EN#  
PGND  
GL  
PWM  
CGND  
VCIN VDRV BOOT GH  
THWN  
VIN  
DISBL# R2J20656  
VSWH  
ANP  
ZCD_EN#  
PGND  
GL  
PWM  
CGND  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 6 of 15  
R2J20656ANP  
Preliminary  
Pin Connection  
+5 V  
0.1 μF  
1.0 μF  
CGND  
ZCD_EN#able Signal INPUT  
VIN  
(4.5 to 22 V)  
CGND  
10  
9
8
7
6
5
4
3
2
1
PWM  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
PWM INPUT  
10 μF × 4  
DISBL#  
THWN  
VIN  
CGND  
PAD  
PAD  
PGND  
10 kΩ  
VIN  
CGND  
GL  
+5 V  
VSWH  
PGND  
10 kΩ  
R2J20656ANP  
VSWH  
+5 V  
VSWH  
PAD  
Thermal Shutdown  
Thermal Warning  
21 22 23 24 25 26 27 28 29 30  
0.45 μH  
Vout  
PGND  
PGND  
Power GND Signal GND  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 7 of 15  
R2J20656ANP  
Preliminary  
Test Circuit  
IIN  
A
A
Vinput  
Vcont  
VIN  
V
ICIN  
VCIN  
V
VCIN  
BOOT  
VIN  
DISBL#  
R2J20656ANP  
VDRV  
VSWH  
ZCD_EN#  
Electric  
load  
PWM  
5 V pulse  
IO  
PGND  
CGND  
GH  
GL  
Note: PIN = IIN × VIN + ICIN × VCIN  
POUT = IO × VO  
Average Output Voltage  
VO  
Averaging  
circuit  
V
Efficiency = POUT / PIN  
PLOSS(DrMOS) = PIN – POUT  
Ta = 27°C  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 8 of 15  
R2J20656ANP  
Preliminary  
Typical Data  
Power Loss vs. Output Current  
VIN = 12 V  
VCIN = VDRV = 5 V  
VOUT = 1.3 V  
Power Loss vs. Input Voltage  
9
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
VCIN = VDRV = 5 V  
VOUT = 1.3 V  
PWM = 600 kHz  
L = 0.45 μH  
IOUT = 25 A  
8
7
6
5
4
3
2
1
0
f
f
PWM = 600 kHz  
L = 0.45 μH  
0
5
10  
15  
20  
25  
30  
35  
4
6
8
10 12 14 16 18 20 22  
Input Voltage (V)  
Output Current (A)  
Power Loss vs. Output Voltage  
Power Loss vs. Switching Frequency  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
VIN = 12 V  
VCIN = VDRV = 5 V  
PWM = 600 kHz  
L = 0.45 μH  
IOUT = 25 A  
VIN = 12 V  
VCIN = VDRV = 5 V  
VOUT = 1.3 V  
L = 0.45 μH  
f
IOUT = 25 A  
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4  
250  
500  
750  
1000  
1250  
Output Voltage (V)  
Switching Frequency (kHz)  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 9 of 15  
R2J20656ANP  
Preliminary  
Power Loss vs. Output Inductance  
VIN = 12 V  
VCIN = VDRV = 5 V  
VOUT = 1.3 V  
Power Loss vs. VCIN  
1.7  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
VIN = 12 V  
VOUT = 1.3 V  
PWM = 600 kHz  
L = 0.45 μH  
IOUT = 25 A  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
f
f
PWM = 600 kHz  
IOUT = 25 A  
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0  
4.5  
5.0  
5.5  
6.0  
Output Inductance (μH)  
VCIN = VDRV (V)  
Average ICIN vs. Switching Frequency  
70  
VIN = 12 V  
VCIN = VDRV = 5 V  
VOUT = 1.3 V  
L = 0.45 μH  
60  
50  
40  
30  
20  
10  
IOUT = 0 A  
250  
500  
750  
1000  
1250  
Switching Frequency (kHz)  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 10 of 15  
R2J20656ANP  
Preliminary  
Description of Operation  
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a  
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable  
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-  
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.  
VCIN & DISBL#  
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN  
is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The  
signal on pin DISBL# also enables or disables the circuit.  
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,  
etc., to pull the DISBL# line up to VCIN are both possible.  
VCIN  
DISBL#  
Driver State  
Disable (GL, GH = L)  
Disable (GL, GH = L)  
Active  
L
L
H
H
H
H
Open  
Disable (GL, GH = L)  
The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is  
connected to the DISBL# pin. The detailed function is described in THDN section.  
PWM & ZCD_EN#  
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the  
PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is  
low.  
PWM  
GH  
L
GL  
H
L
H
H
L
The ZCD_EN# pin is the Zero Current Detection Operation Enable pin for "Diode Emulation Mode (DEM)" when  
ZCD_EN# is low. This function improves light load efficiency by preventing negative inductor current from output  
capacitor. Driver IC monitors inductor current and when inductor current crosses zero, driver IC turn off Low side MOS  
FET automatically.  
Figure 1.1 shows the Typical high side and low side gate switching and Inductor current (IL) during Continuous  
Conduction Mode (CCM), and figure 1.2 shows DEM when asserting Zero Current Detection Enable signal.  
ZCD_EN# pin is internally pulled up to VCIN with 160 kresistor. When Zero current detection function is not used,  
keep this pin open or pulled up to VCIN.  
CCM Operation (ZCD_EN# = "H" or Open mode)  
IL  
PWM  
GH  
GL  
Figure 1.1 Typical Signals during CCM  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 11 of 15  
R2J20656ANP  
Preliminary  
DEM Operation (ZCD_EN# = "L" in Light load condition)  
IL  
0 A  
PWM  
GH  
GL  
Figure 1.2 Typical Signals during DEM  
The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-  
state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in  
the input hysteresis window for 150 ns (typ.). After the tri-state mode has been entered and GH and GL have become  
low, a PWM input voltage of 4.0 V or more is required to make the circuit return to normal operation.  
150 ns (tHOLD-OFF  
)
150 ns (tHOLD-OFF)  
3.2 V  
1.5 V  
PWM  
GH  
GL  
150 ns (tHOLD-OFF  
)
150 ns (tHOLD-OFF)  
3.2 V  
1.5 V  
PWM  
GH  
GL  
Figure 2 PWM Shutdown-Hold Time Signal  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 12 of 15  
R2J20656ANP  
Preliminary  
The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal  
operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection  
signal has been driven high, the transistor M1 is turned off.  
When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is  
asserted high signal, M1 becomes ON and shifts to normal operation.  
VCIN  
M1  
14.5 k  
Tri-state  
PWM Pin  
detection signal  
Input  
Logic  
To internal control  
12.5 k  
Figure 3 Equivalent Circuit for the PWM-pin Input  
THWN & THDN  
This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.  
This Thermal Warning feature is the indication of the high temperature status.  
THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems  
with the thermal warning implementation.  
When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates.  
This signal is only indication for the system controller and does not disable DrMOS operation.  
When thermal warning function is not used, keep this pin open.  
Thermal  
warning  
"H"  
Normal  
THWN output  
Logic Level  
operating  
"L"  
TIC (°C)  
100 115  
Figure 4 THWN Trigger Temperature  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 13 of 15  
R2J20656ANP  
Preliminary  
THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.  
This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal  
high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system  
controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes  
under UVL level (3.8 V).  
Figure 5 shows the example of two types of DISBL# connection with the system controller signal.  
Driver IC Temp.  
< 150°C  
> 150°C  
Driver Chip Status  
Enable (GL, GH = "Active")  
Shutdown (GL, GH = "L")  
5 V  
10 k  
To Internal  
Logic  
To Internal  
Logic  
DISBL#  
DISBL#  
10 k  
2 μA  
2 μA  
To shutdown signal  
ON/OFF signal  
Thermal  
Shutdown  
Detection  
Thermal  
Shutdown  
Detection  
Figure 5.1 THDN Signal to the System Controller  
Figure 5.2 ON/OFF Signal from the System Controller  
MOS FET  
The MOS FETs incorporated in R2J20656ANP are highly suitable for synchronous-rectification buck conversion. For  
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the  
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 14 of 15  
R2J20656ANP  
Preliminary  
Package Dimensions  
JEITA Package Code  
RENESAS Code  
Previous Code  
MASS[Typ.]  
P-HVQFN40-p-0606-0.50  
PVQN0040KE-A  
HD  
D
HD/2  
D /2  
4-C0.50  
B
B
1pin  
1pin  
INDEX  
40  
40  
2.2  
C0.3  
A
0.7  
0.2  
1.95  
Dimension in Millimeters  
Min Nom Max  
5.95 6.00 6.05  
5.95 6.00 6.05  
Reference  
Symbol  
2-A section  
CAV No.  
Die No.  
D
E
2.05  
1.95  
A2 0.87 0.89 0.91  
f
0.20  
ZD  
A
0.865 0.91 0.95  
X 4  
e
X 4  
t
S AB  
A1 0.005 0.02 0.04  
0.17 0.22 0.27  
b1 0.16 0.20 0.24  
0.50  
Lp 0.40 0.50 0.60  
f
S AB  
b
b
x
S AB  
y1  
S
e
L1  
x
y
y1  
t
0.05  
0.05  
0.20  
0.20  
S
HD 6.15 6.20 6.25  
HE 6.15 6.20 6.25  
y
S
Lp  
ZD  
ZE  
0.75  
0.75  
L1 0.06 0.10 0.14  
c1 0.17 0.20 0.23  
c2 0.17 0.22 0.27  
Ordering Information  
Part Name  
Quantity  
Shipping Container  
Taping Reel  
R2J20656ANP#G0  
2500 pcs  
R07DS0201EJ0100 Rev.1.00  
Jan 25, 2011  
Page 15 of 15  
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Colophon 1.0  

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