R5F10RGAG_技术文档

Datasheet

R01DS0157EJ0210

Rev.2.10

RL78/L12

RENESAS MCU

Sep 30, 2016

Integrated LCD controller/driver, True Low Power Platform (as low as 62.5 µA/MHz, and 0.64 µA for RTC + LVD),

1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications

1. OUTLINE

1.1 Features

Ultra-Low Power Technology

LCD Controller/Driver

• 1.6 V to 5.5 V operation from a single supply

• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA

• Halt (RTC + LVD): 0.64 µA

• Supports snooze

• Operating: 62.5 µA/MHz

• LCD operating current (Capacitor split method): 0.12 µA

• LCD operating current (Internal voltage boost method):

0.63 µA (V^DD= 3.0 V)

• Up to 35 seg x 8 com or 39 seg x 4 com

• Supports capacitor split method, internal voltage boost

method and resistance division method

• Supports waveform types A and B

• Supports LCD contrast adjustment (16 steps)

• Supports LCD blinking

Direct Memory Access (DMA) Controller

• Up to 2 fully programmable channels

• Transfer unit: 8- or 16-bit

16-bit RL78 CPU Core

• Delivers 31 DMIPS at maximum operating frequency of

24 MHz

• Instruction Execution: 86% of instructions can be

executed in 1 to 2 clock cycles

• CISC Architecture (Harvard) with 3-stage pipeline

• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1

clock cycle

Multiple Communication Interfaces

• Up to 1 × I²C multi-master

• Up to 2 × CSI/SPI (7-, 8-bit)

• Up to 1 × UART (7-, 8-, 9-bit)

• Up to 1 × LIN

Extended-Function Timers

• MAC: 16 x 16 to 32-bit result in 2 clock cycles

• 16-bit barrel shifter for shift & rotate in 1 clock cycle

• 1-wire on-chip debug function

• Multi-function 16-bit timers: Up to 8 channels

• Real-time clock (RTC): 1 channel (full calendar and

alarm function with watch correction function)

• Interval Timer: 12-bit, 1 channel

• 15 kHz watchdog timer: 1 channel (window function)

Code Flash Memory

• Density: 8 KB to 32 KB

Rich Analog

• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs

conversion time

• Supports 1.6 V

• Internal reference voltage (1.45 V)

• On-chip temperature sensor

• Block size: 1 KB

• On-chip single voltage flash memory with protection

from block erase/writing

• Self-programming with flash shield window function

Data Flash Memory

• Data flash with background operation

• Data flash size: 2 KB size

• Erase cycles: 1 Million (typ.)

• Erase/programming voltage: 1.8 V to 5.5 V

Safety Features (IEC or UL 60730 compliance)

• Flash memory CRC calculation

• RAM parity error check

• RAM write protection

• SFR write protection

RAM

• Illegal memory access detection

• Clock frequency detection

• ADC self-test

• 1 KB and 1.5 KB size options

• Supports operands or instructions

• Back-up retention in all modes

General Purpose I/O

• 5V tolerant, high-current (up to 20 mA per pin)

• Open-Drain, Internal Pull-up support

High-speed On-chip Oscillator

• 24 MHz with +/− 1% accuracy over voltage (1.8 V to 5.5

V) and temperature (−20°C to 85°C)

• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8

Operating Ambient Temperature

• T^A: −40 °C to +85 °C (A: Consumer applications)

• T^A: −40 °C to +105 °C (G: Industrial applications)

MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz & 1 MHz

Reset and Supply Management

Package Type and Pin Count

From 7mm x 7mm to 12mm x 12mm

QFP: 32, 44, 48, 52, 64

• Power-on reset (POR) monitor/generator

• Low voltage detection (LVD) with 14 setting options

(Interrupt and/or reset function)

Page 1 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

 ROM, RAM capacities

Flash ROM Data flash

RAM

RL78/L12

48 pins

32 pins

44 pins

52 pins

64 pins

R5F10RLC

R5F10RLA

−

Note

1.5 KB

32 KB

16 KB

8KB

2 KB

R5F10RBC

R5F10RBA

R5F10RB8

R5F10RFC

R5F10RFA

R5F10RF8

R5F10RGC

R5F10RGA

R5F10RG8

R5F10RJC

R5F10RJA

R5F10RJ8

Note

1 KB

Note

Note In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash

function is used.

Remark The functions mounted depend on the product. See 1.6 Outline of Functions.

Page 2 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.2 List of Part Numbers

Figure 1-1 Part Number, Memory Size, and Package of RL78/L12

Part No. R 5 F 1 0 R L C A x x x F B

Package type:

FP : LQFP, 0.80 mm pitch

FA : LQFP, 0.65 mm pitch

FB : LQFP, 0.50 mm pitch

NB : WQFN, 0.40 mm pitch

ROM number (Omitted with blank products)

Classification:

A : Consumer applications, T

A

= -40˚C to 85˚C

G : Industrial applications, T

A

= -40˚C to 105˚C

ROM capacity:

8 : 8 KB

A : 16 KB

C : 32 KB

Pin count:

B : 32-pin

F : 44-pin

G : 48-pin

J : 52-pin

L : 64-pin

RL78/L12 group

Memory type:

F : Flash memory

Renesas MCU

Renesas semiconductor product

Page 3 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

Pin count

Package

Fields of

Part Number

Application ^Note

32-pin plastic LQFP (7 × 7)

44-pin plastic LQFP (10 × 10)

R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP

32 pins

44 pins

48 pins

52 pins

64 pins

A

R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP

R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP

R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP

R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB

R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB

R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA

R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA

R5F10RLAANB, R5F10RLCANB

G

A

G

48-pin plastic LQFP (fine pitch)

(7 × 7)

A

G

52-pin plastic LQFP (10 × 10)

A

G

64-pin plastic WQFN (8 × 8)

A

R5F10RLAGNB, R5F10RLCGNB

G

64-pin plastic LQFP (fine pitch)

(10 × 10)

R5F10RLAAFB, R5F10RLCAFB

A

R5F10RLAGFB, R5F10RLCGFB

G

64-pin plastic LQFP (12 × 12)

R5F10RLAAFA, R5F10RLCAFA

A

R5F10RLAGFA, R5F10RLCGFA

G

Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/L12.

Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering

part numbers, refer to the target product page of the Renesas Electronics website.

Page 4 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.3 Pin Configuration (Top View)

1.3.1 32-pin products

• 32-pin plastic LQFP (7 × 7)

<R>

2423222120191817

25

P21/ANI1/AV^REFM

P20/ANI0/AVREFP

P14/ANI19/SEG32

P30/TI01/TO01/SEG19

16

15

14

13

12

11

10

9

VL4

VL2

VL1

26

27

28

29

30

31

32

P13/ANI18/TI00/SEG31

RL78/L12

(Top View)

P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)

P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2)

P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)

P140/TO00/PCLBUZ0/KR3/SEG27

P126/CAPL

P127/CAPH

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1 2 3 4 5 6 7 8

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR).

Page 5 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.3.2 44-pin products

• 44-pin plastic LQFP (10 × 10)

<R>

33 32 31 30 29 28 27 26 25 24 23

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P143/ANI21/SEG34

P142/ANI20/SEG33

P14/ANI19/SEG32

22

21

20

19

18

17

16

15

14

13

12

34

35

36

37

38

39

40

41

42

43

44

P32/TI03/TO03/INTP4/SEG17

P31/INTP3/RTC1HZ/SEG18

P30/TI01/TO01/SEG19

P125/V^L3

VL4

VL2

VL1

RL78/L12

(Top View)

P13/ANI18/SEG31

P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)

P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)

P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)

P140/TO00/PCLBUZ0/KR3/SEG27

P141/TI00/PCLBUZ1/SEG26

P126/CAPL

P127/CAPH

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1 2 3 4

5 6 7 8 9 10 11

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR).

Page 6 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.3.3 48-pin products

• 48-pin plastic LQFP (fine pitch) (7 × 7)

<R>

36 35 34 33 32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

16

15

14

13

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P144/ANI22/SEG35

P143/ANI21/SEG34

P142/ANI20/SEG33

37

38

39

40

41

42

43

44

45

46

47

48

P70/KR0/SEG16

P32/TI03/TO03/INTP4/KR1/SEG17

P31/INTP3/RTC1HZ/KR2/SEG18

P30/TI01/TO01/KR3/SEG19

P125/V^L3

P14/ANI19/SEG32

P13/ANI18/SEG31

VL4

VL2

VL1

RL78/L12

(Top View)

P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)

P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)

P10/SCK00/TI07/TO07/SEG28/(INTP1)

P140/TO00/PCLBUZ0/SEG27

P141/TI00/PCLBUZ1/SEG26

P126/CAPL

P127/CAPH

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1 2 3 4

5 6 7 8 9 10 11 12

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR).

Page 7 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.3.4 52-pin products

• 52-pin plastic LQFP (10 × 10)

<R>

39 38 37 36 35 34 33 32 31 30 29 28 27

26

25

24

23

22

21

20

19

18

17

16

15

14

40

41

42

43

44

45

46

47

48

49

50

51

52

P71/KR1/SEG15

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P70/KR0/SEG16

P32/TI03/TO03/INTP4/SEG17

P31/INTP3/RTC1HZ/KR2/SEG18

P30/TI01/TO01/KR3/SEG19

P125/V^L3

P145/ANI23/SEG36

P144/ANI22/SEG35

P143/ANI21/SEG34

P142/ANI20/SEG33

RL78/L12

(Top View)

V

L4

L2

L1

P14/ANI19/SEG32

P13/ANI18/SEG31

P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)

P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)

P10/SCK00/TI07/TO07/SEG28/(INTP1)

P140/TO00/PCLBUZ0/SEG27

P141/TI00/PCLBUZ1/SEG26

P126/CAPL

P127/CAPH

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1

2

3

4

5

6

7

8 9 10 11 12 13

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR).

Page 8 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.3.5 64-pin products

• 64-pin plastic WQFN (8 × 8)

<R>

exposed die pad

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P74/SEG12

P73/KR3/SEG13

P130

P72/KR2/SEG14

P147/SEG38

P71/KR1/SEG15

P146/SEG37

P70/KR0/SEG16

P145/ANI23/SEG36

P32/TI03/TO03/INTP4/SEG17

P31/INTP3/RTC1HZ/SEG18

P30/TI01/TO01/SEG19

P125/V^L3

P144/ANI22/SEG35

P143/ANI21/SEG34

RL78/L12

(Top View)

P142/ANI20/SEG33

P14/ANI19/SEG32

VL4

VL2

VL1

P13/ANI18/SEG31

P12/SO00/TxD0/TOOLTxD/SEG30

P11/SI00/RxD0/TOOLRxD/SEG29

P10/SCK00/SEG28

P126/CAPL

P127/CAPH

P140/TO00/PCLBUZ0/SEG27/(INTP6)

P141/TI00/PCLBUZ1/SEG26/(INTP7)

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1

2

3

4

5

6 7 8 9 10 11 12 13 14 15 16

Cautions 1. Make EV^SSpin the same potential as VSS pin.

2. Make V^DDpin the same potential as EVDD pin.

3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. When using the microcontroller for an application where the noise generated inside the microcontroller

must be reduced, it is recommended to supply separate powers to the V^DDand EVDD pins and connect

the V^SSand EVSS pins to separate ground lines.

3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O

redirection register (PIOR).

Page 9 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

• 64-pin plastic LQFP (fine pitch) (10 × 10)

• 64-pin plastic LQFP (12 × 12)

<R>

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P74/SEG12

P73/KR3/SEG13

P130

P72/KR2/SEG14

P147/SEG38

P71/KR1/SEG15

P146/SEG37

P70/KR0/SEG16

P145/ANI23/SEG36

P32/TI03/TO03/INTP4/SEG17

P31/INTP3/RTC1HZ/SEG18

P30/TI01/TO01/SEG19

P125/V^L3

P144/ANI22/SEG35

P143/ANI21/SEG34

RL78/L12

(Top View)

P142/ANI20/SEG33

P14/ANI19/SEG32

VL4

VL2

VL1

P13/ANI18/SEG31

P12/SO00/TxD0/TOOLTxD/SEG30

P11/SI00/RxD0/TOOLRxD/SEG29

P10/SCK00/SEG28

P126/CAPL

P127/CAPH

P140/TO00/PCLBUZ0/SEG27/(INTP6)

P141/TI00/PCLBUZ1/SEG26/(INTP7)

P61/SDAA0/SEG20

P60/SCLA0/SEG21

1

2

3

4

5

6 7 8 9 10 11 12 13 14 15 16

Cautions 1. Make EVSS pin the same potential as VSS pin.

2. Make VDD pin the same potential as EVDD pin.

3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. When using the microcontroller for an application where the noise generated inside the microcontroller

must be reduced, it is recommended to supply separate powers to the V^DDand EVDD pins and connect

the V^SSand EVSS pins to separate ground lines.

3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O

redirection register (PIOR).

Page 10 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.4 Pin Identification

ANI0, ANI1,

ANI16 to ANI23:

AVREFM:

P130, P137:

Port 13

Port 14

Analog Input

P140 to P147:

Analog Reference

Voltage Minus

Analog Reference

Voltage Plus

PCLBUZ0, PCLBUZ1: Programmable Clock

Output/Buzzer Output

AVREFP:

REGC:

Regulator Capacitance

Reset

RESET:

RTC1HZ:

CAPH, CAPL:

COM0 to COM7,

EV^DD:

Capacitor for LCD

Real-time Clock Correction Clock

(1 Hz) Output

Power Supply for Port

Ground for Port

External Clock Input

(Main System Clock)

External Clock Input

(Subsystem Clock)

Interrupt Request From

Peripheral

RxD0:

Receive Data

EV^SS:

SCK00, SCK01:

SCLA0:

Serial Clock Input/Output

Serial Data Input/Output

LCD Segment Output

Serial Data Input

EXCLK:

SDAA0:

EXCLKS:

SEG0 to SEG38:

SI00, SI01:

SO00, SO01:

TI00 to TI07:

TO00 to TO07:

TOOL0:

INTP0 to INTP7:

Serial Data Output

Timer Input

KR0 to KR3:

P10 to P17:

P20, P21:

Key Return

Timer Output

Port 1

Data Input/Output for Tool

Port 2

TOOLRxD, TOOLTxD: Data Input/Output for External Device

P30 to P32:

P40 to P43:

P50 to P54:

P60, P61:

Port 3

TxD0:

Transmit Data

Port 4

V^DD:

Power Supply

Port 5

V^L1to VL4:

V^SS:

LCD Power Supply

Port 6

Ground

P70 to P74:

P120 to P127:

Port 7

X1, X2:

XT1, XT2:

Crystal Oscillator (Main System Clock)

Crystal Oscillator (Subsystem Clock)

Port 12

Page 11 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.5 Block Diagram

1.5.1 32-pin products

TIMER ARRAY

UNIT0 (8ch)

TI00/P13

TO00/P140

ch0

PORT 1

PORT 2

PORT 3

PORT 4

8

2

P10 to P17

P20, P21

P30

TI01/TO01/P30

ch1

ch2

ch3

TI02/TO02/P17

(TI02/TO02/P12)

2

ANI0/P20, ANI1/P21

ch4

ch5

ch6

ch7

P40

ANI18/P13, ANI19/P14

A/D CONVERTER

AVREFP/P20

AV^REFM/P21

PORT 6

2

P60, P61

TI07/TO07/P10

REAL-TIME

CLOCK

2

P126, P127

P121, P122

PORT 12

CODE FLASH MEMORY

DATA FLASH MEMORY

LOW-SPEED

ON-CHIP

OSCILLATOR

RL78

CPU

CORE

12- BIT INTERVAL

TIMER

PORT 13

PORT 14

P137

P140

WINDOW

WATCHDOG

TIMER

BUZZER OUTPUT

PCLBUZ0/P140

CLOCK OUTPUT

CONTROL

SEG0, SEG4 to SEG6,

SEG19 to SEG21, 13

SEG27 to SEG32

LCD

CONTROLLER/

DRIVER

RAM

3

KR0/P12 to KR2/P10

KR3/P140

COM0 to COM3

4

KEY RETURN

RAM SPACE

FOR LCD DATA

VL1, VL2, VL4

CAPH

CAPL

POWER ON RESET/

VOLTAGE

POR/LVD

CONTROL

SERIAL ARRAY

UNIT0 (2ch)

DETECTOR

V

DD

V

SS TOOLRxD/P11,

TOOLTxD/P12

RxD0/P11

TxD0/P12

UART0

RESET CONTROL

ON-CHIP DEBUG

SCK00/P10

SI00/P11

CSI00

SO00/P12

TOOL0/P40

DIRECT MEMORY

ACCESS CONTROL

SCK01/P15

SI01/P16

CSI01

SYSTEM

CONTROL

SO01/P17

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

OSCILLATOR

SDAA0/P61

SCLA0/P60

SERIAL

INTERFACE IICA0

MULTIPLIER&

DIVIDER,

MULITIPLY-

VOLTAGE

REGULATOR

REGC

CRC

ACCUMULATOR

INTP0/P137

INTP1/P15(INTP1/P10),

INTP2/P16(INTP2/P11)

2

INTERRUPT

CONTROL

BCD

ADJUSTMENT

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR)

Page 12 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.5.2 44-pin products

TIMER ARRAY

UNIT0 (8ch)

TI00/P141

ch0

TO00/P140

PORT 1

PORT 2

PORT 3

PORT 4

8

2

3

P10 to P17

P20, P21

P30 to P32

P40

TI01/TO01/P30

ch1

ch2

ch3

TI02/TO02/P17

(TI02/TO02/P12)

TI03/TO03/P32

2

3

2

ANI0/P20, ANI1/P21

ANI17/P120, ANI18/P13,

ANI19/P14

ch4

ch5

ch6

ch7

A/D CONVERTER

ANI20/P142, ANI21/P143

AVREFP/P20

AVREFM/P21

PORT 6

2

P60, P61

TI07/TO07/P10

RTC1HZ/P31

4

P120, P125 to P127

P121 to P124

REAL-TIME

CLOCK

PORT 12

PORT 13

CODE FLASH MEMORY

DATA FLASH MEMORY

RL78

CPU

CORE

LOW-SPEED

ON-CHIP

OSCILLATOR

P137

12- BIT INTERVAL

TIMER

PORT 14

4

P140 to P143

WINDOW

WATCHDOG

TIMER

BUZZER OUTPUT

PCLBUZ0/P140,

PCLBUZ1/P141

2

3

SEG0 to SEG6,

SEG17 to SEG21, 22

SEG25 to SEG34

CLOCK OUTPUT

CONTROL

LCD

CONTROLLER/

DRIVER

RAM

KR0/P12 to KR2/P10

KR3/P140

COM0 to COM7

8

KEY RETURN

V

L1 to VL4

CAPH

CAPL

RAM SPACE

FOR LCD DATA

POWER ON RESET/

VOLTAGE

POR/LVD

CONTROL

SERIAL ARRAY

UNIT0 (2ch)

DETECTOR

V

DD

V

SS TOOLRxD/P11,

RxD0/P11

TxD0/P12

UART0

TOOLTxD/P12

RESET CONTROL

ON-CHIP DEBUG

SCK00/P10

SI00/P11

CSI00

SO00/P12

TOOL0/P40

DIRECT MEMORY

ACCESS CONTROL

SCK01/P15

SI01/P16

CSI01

SO01/P17

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

OSCILLATOR

SDAA0/P61

SCLA0/P60

SERIAL

INTERFACE IICA0

XT1/P123

XT2/EXCLKS/P124

MULTIPLIER&

DIVIDER,

MULITIPLY-

VOLTAGE

REGULATOR

REGC

CRC

ACCUMULATOR

INTP0/P137

INTP1/P15(INTP1/P10),

INTP2/P16(INTP2/P11)

2

INTERRUPT

CONTROL

INTP3/P31,

INTP4/P32

BCD

ADJUSTMENT

2

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR)

Page 13 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.5.3 48-pin products

TIMER ARRAY

UNIT0 (8ch)

TI00/P141

TO00/P140

ch0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

8

2

3

2

P10 to P17

P20, P21

P30 to P32

P40, P41

P50

TI01/TO01/P30

ch1

ch2

ch3

TI02/TO02/P17

(TI02/TO02/P12)

TI03/TO03/P32

TI04/TO04/P41

2

4

3

ANI0/P20, ANI1/P21

ANI16/P41, ANI17/P120,

ANI18/P13, ANI19/P14

ch4

ch5

ch6

ch7

A/D CONVERTER

ANI20/P142 to ANI22/P144

AVREFP/P20

AVREFM/P21

2

P60, P61

P70

TI07/TO07/P10

RTC1HZ/P31

4

P120, P125 to P127

P121 to P124

REAL-TIME

CLOCK

PORT 12

PORT 13

CODE FLASH MEMORY

DATA FLASH MEMORY

RL78

CPU

CORE

LOW-SPEED

ON-CHIP

OSCILLATOR

P137

12- BIT INTERVAL

TIMER

PORT 14

5

2

P140 to P144

WINDOW

WATCHDOG

TIMER

BUZZER OUTPUT

PCLBUZ0/P140

(PCLBUZ0/P50),

PCLBUZ1/P141

CLOCK OUTPUT

CONTROL

SEG0 to SEG7,

SEG16 to SEG21,

SEG24 to SEG35

26

8

LCD

RAM

CONTROLLER/

DRIVER

KR0/P70

KEY RETURN

COM0 to COM7

3

KR1/P32 to KR3/P30

V

L1 to VL4

CAPH

CAPL

RAM SPACE

FOR LCD DATA

POWER ON RESET/

VOLTAGE

POR/LVD

CONTROL

DETECTOR

SERIAL ARRAY

UNIT0 (2ch)

V

DD

V

SS TOOLRxD/P11,

RxD0/P11

TxD0/P12

TOOLTxD/P12

UART0

RESET CONTROL

ON-CHIP DEBUG

SCK00/P10

SI00/P11

CSI00

SO00/P12

TOOL0/P40

DIRECT MEMORY

SCK01/P15

ACCESS CONTROL

CSI01

SI01/P16

SO01/P17

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

SDAA0/P61

SCLA0/P60

SERIAL

INTERFACE IICA0

XT1/P123

OSCILLATOR

XT2/EXCLKS/P124

MULTIPLIER&

DIVIDER,

MULITIPLY-

VOLTAGE

REGULATOR

REGC

CRC

ACCUMULATOR

INTP0/P137

INTP1/P15(INTP1/P10),

INTP2/P16(INTP2/P11)

2

INTERRUPT

CONTROL

INTP3/P31,

INTP4/P32

BCD

ADJUSTMENT

2

INTP5/P50

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR)

Page 14 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.5.4 52-pin products

TIMER ARRAY

UNIT0 (8ch)

TI00/P141

ch0

TO00/P140

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

8

2

3

2

P10 to P17

P20, P21

P30 to P32

P40 to P42

P50, P51

P60, P61

P70, P71

TI01/TO01/P30

ch1

ch2

ch3

TI02/TO02/P17

(TI02/TO02/P12)

TI03/TO03/P32

TI04/TO04/P41

TI05/TO05/P42

TI06/TO06/P51

TI07/TO07/P10

2

4

ANI0/P20, ANI1/P21

ANI16/P41, ANI17/P120,

ANI18/P13, ANI19/P14

ch4

ch5

ch6

ch7

A/D CONVERTER

ANI20/P142 to ANI23/P145

AVREFP/P20

AVREFM/P21

RTC1HZ/P31

4

P120, P125 to P127

P121 to P124

REAL-TIME

CLOCK

PORT 12

PORT 13

CODE FLASH MEMORY

DATA FLASH MEMORY

RL78

CPU

CORE

LOW-SPEED

ON-CHIP

OSCILLATOR

P137

12- BIT INTERVAL

TIMER

PORT 14

6

2

P140 to P145

WINDOW

WATCHDOG

TIMER

BUZZER OUTPUT

PCLBUZ0/P140

(PCLBUZ0/P50),

PCLBUZ1/P141

CLOCK OUTPUT

CONTROL

SEG0 to SEG8,

SEG15 to SEG21, 30

SEG23 to SEG36

LCD

CONTROLLER/

DRIVER

RAM

2

KR0/P70, KR1/P71

KR2/P31, KR3/P30

COM0 to COM7

8

KEY RETURN

V

L1 to VL4

CAPH

CAPL

RAM SPACE

FOR LCD DATA

POWER ON RESET/

VOLTAGE

POR/LVD

CONTROL

SERIAL ARRAY

UNIT0 (2ch)

DETECTOR

V

DD

V

SS TOOLRxD/P11,

TOOLTxD/P12

RxD0/P11

TxD0/P12

UART0

RESET CONTROL

ON-CHIP DEBUG

SCK00/P10

SO10/P17

SI00/P11

CSI00

SO00/P12

TOOL0/P40

DIRECT MEMORY

ACCESS CONTROL

SCK01/P15

SI01/P16

CRC

CSI01

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

SDAA0/P61

SCLA0/P60

SERIAL

INTERFACE IICA0

XT1/P123

OSCILLATOR

XT2/EXCLKS/P124

MULTIPLIER&

DIVIDER,

MULITIPLY-

VOLTAGE

REGULATOR

REGC

ACCUMULATOR

INTP0/P137

INTP1/P15(INTP1/P10),

INTP2/P16(INTP2/P11)

2

INTERRUPT

CONTROL

INTP3/P31,

INTP4/P32

BCD

ADJUSTMENT

2

INTP5/P50

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR)

Page 15 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.5.5 64-pin products

TIMER ARRAY

UNIT0 (8ch)

TI00/P141

ch0

TO00/P140

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

8

2

3

4

5

2

5

P10 to P17

TI01/TO01/P30

ch1

ch2

ch3

P20, P21

TI02/TO02/P17

(TI02/TO02/P54)

P30 to P32

P40 to P43

P50 to P54

P60, P61

TI03/TO03/P32

TI04/TO04/P41

TI05/TO05/P42

TI06/TO06/P51

TI07/TO07/P53

2

4

ANI0/P20, ANI1/P21

ANI16/P41, ANI17/P120,

ANI18/P13, ANI19/P14

ch4

ch5

ch6

ch7

A/D CONVERTER

ANI20/P142 to ANI23/P145

AVREFP/P20

AV^REFM/P21

P70 to P74

RTC1HZ/P31

REAL-TIME

CLOCK

4

P120, P125 to P127

P121 to P124

PORT 12

PORT 13

CODE FLASH MEMORY

DATA FLASH MEMORY

RL78

CPU

CORE

P130

P137

LOW-SPEED

ON-CHIP

OSCILLATOR

12- BIT INTERVAL

TIMER

PORT 14

8

2

P140 to P147

WINDOW

WATCHDOG

TIMER

BUZZER OUTPUT

PCLBUZ0/P140

(PCLBUZ0/P50),

PCLBUZ1/P141

CLOCK OUTPUT

CONTROL

LCD

CONTROLLER/

DRIVER

SEG0 to SEG38 39

COM0 to COM7

8

RAM

KR0/P70 to

KR3/P73

4

KEY RETURN

V

L1 to VL4

CAPH

CAPL

RAM SPACE

FOR LCD DATA

POWER ON RESET/

VOLTAGE

POR/LVD

CONTROL

SERIAL ARRAY

UNIT0 (2ch)

DETECTOR

RxD0/P11

TxD0/P12

V

DD

,

V

SS

,

TOOLRxD/P11,

UART0

EV^DDEV^SSTOOLTxD/P12

RESET CONTROL

ON-CHIP DEBUG

SCK00/P10

SI00/P11

CSI00

SO00/P12

TOOL0/P40

SCK01/P15

SI01/P16

DIRECT MEMORY

ACCESS CONTROL

CRC

CSI01

SO01/P17

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

SDAA0/P61

SCLA0/P60

SERIAL

INTERFACE IICA0

HIGH-SPEED

ON-CHIP

OSCILLATOR

XT1/P123

XT2/EXCLKS/P124

MULTIPLIER&

DIVIDER,

MULITIPLY-

VOLTAGE

REGULATOR

REGC

ACCUMULATOR

INTP0/P137

INTP1/P15(INTP1/P53),

INTP2/P16(INTP2/P54)

2

INTERRUPT

CONTROL

INTP3/P31,

INTP4/P32

BCD

ADJUSTMENT

2

INTP5/P50

INTP6/P52(INTP6/P140)

INTP7/P43(INTP7/P141)

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR)

Page 16 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

1.6 Outline of Functions

Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set

to 00H.

(1/2)

Item

32-pin

44-pin

48-pin

52-pin

64-pin

R5F10RBx

R5F10RFx

R5F10RGx

R5F10RJx

R5F10RLx

Code flash memory (KB)

Data flash memory (KB)

RAM (KB)

8 to 32

2

1, 1.5 ^{Note 1}

8 to 32

2

1, 1.5 ^{Note 1}

8 to 32

2

1, 1.5 ^{Note 1}

8 to 32

2

1, 1.5 ^{Note 1}

16, 32

2

1, 1.5^{Note 1}

Memory space

1 MB

Main

High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

HS (high-speed main) operation: 1 to 20 MHz (V^DD= 2.7 to 5.5 V),

HS (high-speed main) operation: 1 to 16 MHz (V^DD= 2.4 to 5.5 V),

LS (low-speed main) operation: 1 to 8 MHz (V^DD= 1.8 to 5.5 V),

<R>

system

clock

LV (low-voltage main) operation: 1 to 4 MHz (V^DD= 1.6 to 5.5 V)

High-speed on-chip

oscillator clock

HS (high-speed main) operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V),

HS (high-speed main) operation: 1 to 16 MHz (V^DD= 2.4 to 5.5 V),

LS (low-speed main) operation: 1 to 8 MHz (V^DD= 1.8 to 5.5 V),

LV (low-voltage main) operation: 1 to 4 MHz (V^DD= 1.6 to 5.5 V)

Subsystem clock

−

XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)

32.768 kHz (TYP.): V^DD= 1.6 to 5.5 V

Low-speed on-chip oscillator clock

Internal oscillation

15 kHz (TYP.): V^DD= 1.6 to 5.5 V

General-purpose register

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time 0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)

0.05 μs (High-speed system clock: fMX = 20 MHz operation)

30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)

Instruction set

• Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)

• Multiplication (8 bits × 8 bits)

• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean

operation), etc.

Total number of I/O port pins and

pins dedicated to drive an LCD

28

40

44

48

58

47

I/O

Total

20

29

33

37

port

CMOS I/O

15

3

22

5

26

5

30

5

39

5

CMOS input

CMOS output

−

1

N-ch open-drain I/O

(EV^DDtolerance)

2

Pins dedicated to drive an LCD

LCD controller/driver

8

11

Internal voltage boosting method, capacitor split method, and external resistance

division method are switchable.

22 (18) ^{Note 2}

26 (22) ^{Note 2}

30 (26) ^{Note 2}

39 (35) ^{Note 2}

Segment signal output

Common signal output

13

4

4 (8) ^{Note 2}

Notes 1. In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data

flash function is used.

2. The values in parentheses are the number of signal outputs when 8 com is used.

Page 17 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

1. OUTLINE

(2/2)

Item

32-pin

44-pin

48-pin

52-pin

64-pin

R5F10RLx

R5F10RBx

R5F10RFx

R5F10RGx

R5F10RJx

Timer

16-bit timer

8 channels

8 channels (with 1 channel remote control output function)

Watchdog timer

Real-time clock (RTC)

12-bit interval timer (IT)

Timer output

1 channel

4 channels

5 channels

6 channels

8 channels (PWM outputs: 7 ^{Note 1}

)

(PWM outputs: (PWM outputs: (PWM outputs:

3 ^{Note 1}4 ^{Note 1}5 ^{Note 1}

1

)

RTC output

−

• 1 Hz (subsystem clock: f^SUB= 32.768 kHz or )

Clock output/buzzer output

1

2

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz

(Main system clock: f^MAIN= 20 MHz operation)

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,

32.768 kHz

(Subsystem clock: f^SUB= 32.768 kHz operation)

8/10-bit resolution A/D converter

Serial interface

4 channels

• CSI: 2 channel/UART (LIN-bus supported): 1 channel

1 channel 1 channel 1 channel 1 channel

7 channels

9 channels

10 channels

1 channel

I²C bus

Multiplier and divider/multiply-

accumulator

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

DMA controller

2 channels

Vectored interrupt Internal

23

4

23

6

23

7

23

7

23

9

sources

External

Key interrupt

Reset

4

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution ^{Note 2}

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

Voltage detector

• Power-on-reset:

1.51 0.04 V

• Power-down-reset: 1.50 0.04 V

• Rising edge : 1.67 V to 4.06 V (14 stages)

• Falling edge : 1.63 V to 3.98 V (14 stages)

On-chip debug function

Power supply voltage

Provided

VDD = 1.6 to 5.5 V

TA = −40 to +85 °C

Operating ambient temperature

Notes 1. The number of PWM outputs varies depending on the setting of channels in use (the number of masters

and slaves).

2. The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip

debug emulator.

Page 18 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2. ELECTRICAL SPECIFICATIONS (A, G: T = -40 to +85°C)

A

This chapter describes the electrical specifications for the products "A: Consumer applications (T^A= -40 to +85°C)" and

"G: Industrial applications (with T^A= -40 to +85°C)".

Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and

evaluation. Do not use the on-chip debug function in products designated for mass production,

because the guaranteed number of rewritable times of the flash memory may be exceeded when

this function is used, and product reliability therefore cannot be guaranteed. Renesas

Electronics is not liable for problems occurring when the on-chip debug function is used.

2. With products not provided with an EV^DD, or EVSS pin, replace EVDD with VDD, or replace EVSS with

V^SS.

Page 19 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (T^A= 25°C)

(1/3)

Parameter

Symbols

Conditions

Ratings

Unit

V

Supply voltage

VDD

VDD = EVDD

−0.5 to +6.5

−0.5 to +0.3

EVDD

EVSS

V

REGC pin input voltage VIREGC

REGC

−0.3 to +2.8

V

and −0.3 to VDD + 0.3^{Note 1}

Input voltage

VI1

VI2

VI3

P10 to P17, P30 to P32, P40 to P43, P50 to P54,

P70 to P74, P120, P125 to P127,P140 to P147

−0.3 to EV^DD+0.3

V

and −0.3 to V^DD+ 0.3^{Note 2}

P60, P61 (N-ch open-drain)

−0.3 to EV^DD+0.3

and −0.3 to V^DD+ 0.3^{Note 2}

P20, P21, P121 to P124, P137, EXCLK,

EXCLKS, RESET

−0.3 to VDD + 0.3^{Note 2}

Output voltage

VO1

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P60, P61, P70 to P74, P120,

P125 to P127, P130, P140 to P147

P20, P21

−0.3 to EV^DD+ 0.3

V

and −0.3 to V^DD+ 0.3^{Note 2}

VO2

VAI1

−0.3 to VDD + 0.3 ^{Note 2}

−0.3 to EV^DD+ 0.3 and

V

Analog input voltage

ANI16 to ANI23

−0.3 to AV^REF(+) + 0.3

Notes 2, 3

VAI2

ANI0, ANI1

−0.3 to V^DD+ 0.3 and

V

−0.3 to AV^REF(+) + 0.3

Notes 2, 3

Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute

maximum rating of the REGC pin. Do not use this pin with voltage applied to it.

2. Must be 6.5 V or lower.

3. Do not exceed AV^REF(+)+ 0.3 V in case of A/D conversion target pin.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the

port pins.

2. AV^REF(+): + side reference voltage of the A/D converter.

3. V^SS: Reference voltage

Page 20 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Absolute Maximum Ratings (TA = 25°C)

(2/3)

Parameter

LCD voltage

Symbols

Conditions

Ratings

Unit

V

VL1

VL1 voltage^{Note 1}

−0.3 to +2.8

and −0.3 to V^L4+ 0.3

VL2

VL2 voltage^{Note 1}

VL3 voltage^{Note 1}

VL4 voltage^{Note 1}

−0.3 to VL4 + 0.3 ^{Note 2}

−0.3 to +6.5

−0.3 to VL4 + 0.3 ^{Note 2}

−0.3 to V^DD+ 0.3 ^{Note 2}

V

VL3

VL4

VLCAP

VLOUT

CAPL, CAPH voltage^{Note 1}

COM0 to COM7, External resistance division

SEG0 to

method

−0.3 to VDD + 0.3 ^{Note 2}

−0.3 to VL4 + 0.3 ^{Note 2}

SEG38,

Capacitor split method

Internal voltage boosting method

output voltage

Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3,

and V^L4pins; it does not mean that applying voltage to these pins is recommended. When using

the internal voltage boosting method or capacitance split method, connect these pins to V^SSvia a

capacitor (0.47 μ F 30%) and connect a capacitor (0.47 μ F 30%) between the CAPL and CAPH

pins.

2. Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge

of suffering physical damage, and therefore the product must be used under conditions that ensure that

the absolute maximum ratings are not exceeded.

Remark V^SS: Reference voltage

Page 21 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Absolute Maximum Ratings (TA = 25°C)

(3/3)

Parameter

Symbols

Conditions

Ratings

Unit

mA

Output current, high

IOH1

Per pin

P10 to P17, P30 to P32,

P40 to P43, P50 to P54,

P70 to P74, P120, P125 to P127,

P130, P140 to P147

−40

Total of all pins

P10 to P14, P40 to P43, P120,

P130, P140 to P147

−70

mA

−170 mA

P15 to P17, P30 to P32,

P50 to P54, P70 to P74,

P125 to P127

−100

IOH2

IOL1

Per pin

P20, P21

−0.5

−1

mA

Total of all pins

Per pin

Output current, low

P10 to P17, P30 to P32,

P40 to P43, P50 to P54, P60,

P61, P70 to P74, P120,

P125 to P127, P130,

P140 to P147

40

Total of all pins

170 mA

P10 to P14, P40 to P43, P120,

P130, P140 to P147

70

mA

P15 to P17, P30 to P32,

P50 to P54, P60, P61,

P70 to P74, P125 to P127

100

IOL2

T^A

Per pin

P20, P21

1

2

mA

°C

Total of all pins

Operating ambient

temperature

In normal operation mode

−40 to +85

In flash memory programming mode

Storage temperature

Tstg

−65 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 22 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.2 Oscillator Characteristics

2.2.1 X1, XT1 oscillator characteristics

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Resonator

Conditions

2.7 V ≤ V^DD≤ 5.5 V

MIN. TYP. MAX. Unit

X1 clock oscillation frequency Ceramic resonator/

1.0

20.0 MHz

(f^X)^Note

crystal resonator

2.4 V ≤ VDD ≤ 2.7 V

1.8 V ≤ VDD < 2.7 V

1.6 V ≤ VDD <1.8 V

16.0 MHz

8.0

4.0

MHz

kHz

XT1 clock oscillation

frequency (f^XT)^Note

Crystal resonator

32 32.768 35

Note

Indicates only permissible oscillator frequency ranges. Refer to 2.4 AC Characteristics for instruction

execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check

the oscillator characteristics.

Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1

clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)

by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation

stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time

with the resonator to be used.

2.2.2 On-chip oscillator characteristics

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Oscillators

Parameters

f^IH

Conditions

MIN.

1

TYP. MAX.

24

Unit

High-speed on-chip oscillator

clock frequency ^{Notes 1, 2}

MHz

High-speed on-chip oscillator

clock frequency accuracy

−20 to +85°C

−40 to −20°C

1.8 V ≤ V^DD≤ 5.5 V

1.6 V ≤ VDD < 1.8 V

1.8 V ≤ VDD ≤ 5.5 V

1.6 V ≤ VDD < 1.8 V

−1

−5

+1

+5

%

−1.5

−5.5

+1.5

%

+5.5

%

Low-speed on-chip oscillator

clock frequency

f^IL

15

kHz

Low-speed on-chip oscillator

clock frequency accuracy

−15

+15

%

Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of

HOCODIV register.

2. This indicates the oscillator characteristics only. Refer to 2.4 AC Characteristics for instruction execution

time.

Page 23 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.3 DC Characteristics

2.3.1 Pin characteristics

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/5)

Items

Symbol

I^OH1

Conditions

MIN.

TYP.

MAX.

Unit

mA

Output current,

high^{Note 1}

Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,

P70 to P74, P120, P125 to P127, P130, P140 to P147

−10.0

Note 2

Total of P10 to P14, P40 to P43, P120,

P130, P140 to P147

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

1.8 V ≤ EVDD < 2.7 V

1.6 V ≤ EVDD < 1.8 V

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

1.8 V ≤ EVDD < 2.7 V

1.6 V ≤ EVDD < 1.8 V

−40.0

−8.0

mA

(When duty = 70% ^{Note 3}

)

−4.0

−2.0

Total of P15 to P17, P30 to P32,

−60.0

−15.0

−8.0

P50 to P54, P70 to P74, P125 to P127

(When duty = 70% ^{Note 3}

)

−4.0

Total of all pins

−100.0

(When duty = 70%^{Note 3}

P20, P21 Per pin

Total of all pins

)

IOH2

−0.1

−0.2

mA

1.6 V ≤ VDD ≤ 5.5 V

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and

EV^DDpins to an output pin.

2. Do not exceed the total current value.

3. Specification under conditions where the duty factor ≤ 70%.

The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the

following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (I^OH× 0.7)/(n × 0.01)

<Example> Where n = 80% and IOH = −40.0 mA

Total output current of pins = (−40.0 × 0.7)/(80 × 0.01) ≅ −35.0 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 24 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(2/5)

Items

Symbol

I^OL1

Conditions

MIN.

TYP.

MAX.

Unit

Output current,

low^{Note 1}

Per pin for P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P70 to P74, P120, P125 to P127, P130,

P140 to P147

20.0

Note 2

mA

Per pin for P60, P61

15.0 ^{Note 2}

70.0

15.0

9.0

mA

Total of P10 to P14, P40 to P43,

P120, P130, P140 to P147

(When duty = 70% ^{Note 3}

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

1.8 V ≤ EVDD < 2.7 V

1.6 V ≤ EVDD < 1.8 V

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

1.8 V ≤ EVDD < 2.7 V

1.6 V ≤ EVDD < 1.8 V

)

4.5

Total of P15 to P17, P30 to P32,

P50 to P54, P60, P61, P70 to P74,

P125 to P127

(When duty = 70% ^{Note 3}

80.0

35.0

20.0

10.0

150.0

)

Total of all pins

(When duty = 70% ^{Note 3}

)

IOL2

P20, P21 Per pin

0.4

0.8

mA

Total of all pins

1.6 V ≤ VDD ≤ 5.5 V

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the V^DDand

EV^DDpins to an output pin.

2. Do not exceed the total current value.

3. Specification under conditions where the duty factor ≤ 70%.

The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the

following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (I^OH× 0.7)/(n × 0.01)

<Example> Where n = 80% and IOL = 70.0 mA

Total output current of pins = (70.0 × 0.7)/(80 × 0.01) ≅ 61.25 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 25 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(3/5)

Items

Symbol

V^IH1

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage,

high

P10 to P17, P30 to P32, P40 to P43, Normal input buffer

P50 to P54, P70 to P74, P120,

0.8EV^DD

EVDD

V

P125 to P127, P140 to P147

VIH2

P10, P11, P15, P16

TTL input buffer

4.0 V 5.5 V

TTL input buffer

3.3 V 4.0 V

TTL input buffer

1.6 V 3.3 V

2.2

2.0

EVDD

V

≤

EVDD ≤

≤

EVDD <

1.50

≤

EVDD <

VIH3

VIH4

VIH5

V^IL1

P20, P21

P60, P61

0.7VDD

0.7EVDD

0.8VDD

0

VDD

EVDD

V

P121 to P124, P137, EXCLK, EXCLKS, RESET

VDD

Input voltage,

low

P10 to P17, P30 to P32, P40 to P43, Normal input buffer

P50 to P54, P70 to P74, P120,

0.2EV^DD

P125 to P127, P140 to P147

VIL2

P10, P11, P15, P16

TTL input buffer

4.0 V 5.5 V

TTL input buffer

3.3 V 4.0 V

TTL input buffer

1.6 V 3.3 V

0

0.8

0.5

V

≤

EVDD ≤

≤

EVDD <

0.32

≤

EVDD <

VIL3

VIL4

VIL5

P20, P21

P60, P61

0

0.3VDD

0.3EVDD

0.2VDD

V

P121 to P124, P137, EXCLK, EXCLKS, RESET

Caution The maximum value of V^IHof P10, P12, P15, P17 is EVDD, even in the N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 26 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(4/5)

Items

Symbol

V^OH1

Conditions

MIN.

TYP.

MAX.

Unit

Output voltage,

high

P10 to P17, P30 to P32, P40 to P43, 4.0 V

≤

EVDD

≤

5.5 V, EV^DD−1.5

V

P50 to P54, P70 to P74, P120,

I

OH1

= −10 mA

P125 to P127, P130, P140 to P147

4.0 V

≤

EVDD

≤

5.5 V, EV^DD−0.7

5.5 V, EV^DD−0.6

5.5 V, EV^DD−0.5

I

OH1

= −3.0 mA

2.7 V

≤ EVDD ≤

I

OH1

= −2.0 mA

1.8 V

≤ EVDD ≤

I

OH1

= −1.5 mA

1.6 V

≤ EVDD ≤

I

OH1

=

−1.0 mA

1.6 V ≤ V^DD≤ 5.5 V,

−100 μ A

VOH2

P20, P21

VDD−0.5

I

OH2

=

Output voltage,

low

V^OL1

P10 to P17, P30 to P32, P40 to P43, 4.0 V

≤

EVDD

≤

5.5 V,

1.3

0.7

0.6

0.4

2.0

0.4

P50 to P54, P70 to P74, P120,

I

OL1

= 20 mA

P125 to P127, P130, P140 to P147

4.0 V

≤ EVDD

I

OL1

= 8.5 mA

2.7 V

≤ EVDD

I

OL1

= 3.0 mA

2.7 V

≤ EVDD

I

OL1

= 1.5 mA

1.8 V

≤ EVDD

I

OL1

=

0.6 mA

EVDD < 5.5 V,

0.3 mA

1.6 V ≤ V^DD≤ 5.5 V,

400 μ A

1.6 V

≤

I

OL1

=

VOL2

VOL3

P20, P21

P60, P61

I

OL2

=

4.0 V

≤

EVDD

≤

5.5 V,

I

OL3

= 15.0 mA

4.0 V

≤

EVDD

≤

I

OL3

= 5.0 mA

2.7 V

≤ EVDD

I

OL3

= 3.0 mA

1.8 V

≤ EVDD

I

OL3

=

2.0 mA

EVDD < 5.5 V,

= 1.0 mA

1.6 V

≤

I

OL3

Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 27 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(5/5)

Items

Symbol

I^LIH1

Conditions

MIN.

TYP.

MAX.

1

Unit

Input leakage

current, high

P10 to P17, P30 to P32,

V^I= EVDD

μA

P40 to P43, P50 to P54, P60,

P61, P70 to P74, P120,

P125 to P127, P140 to P147

ILIH2

ILIH3

P20, P21, P137, RESET

VI = VDD

V^I= VDD

1

μA

P121 to P124

In input port or

external clock

input

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

In resonator

connection

10

μA

Input leakage

current, low

I^LIL1

P10 to P17, P30 to P32,

P40 to P43, P50 to P54, P60,

P61, P70 to P74, P120,

V^I= EVSS

−1

P125 to P127, P140 to P147

ILIL2

ILIL3

P20, P21, P137, RESET

VI = VSS

V^I= VSS

−1

μA

P121 to P124

In input port or

external clock

input

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

In resonator

connection

−10

μA

On-chip pll-up

resistance

R^U1

VI = EVSS

SEGxx port

2.4 V

1.6 V

≤

EVDD = VDD

≤

5.5 V

10

20

30

20

100

kΩ

EVDD = VDD < 2.4 V

RU2

Ports other than above

(Except for P60, P61, and

P130)

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 28 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.3.2 Supply current characteristics

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/3)

Parameter Symbol

Conditions

f^IH= 24 MHz^{Note 3}

MIN.

TYP.

1.5

3.3

2.5

1.2

MAX.

Unit

Supply

I^DD1

Operating HS (high-

Basic

operation

VDD = 5.0 V

VDD = 3.0 V

VDD = 5.0 V

VDD = 3.0 V

VDD = 5.0 V

VDD = 3.0 V

VDD = 2.0 V

mA

current

Note 1

mode

speed main)

mode^{Note 5}

Normal

operation

5.0

3.7

1.8

fIH = 16 MHz^{Note 3}

Normal

operation

LS (low-speed f^IH= 8 MHz^{Note 3}

Normal

operation

main) mode^Note

5

LV (low-

f^IH= 4 MHz^{Note 3}

Normal

operation

VDD = 3.0 V

VDD = 2.0 V

1.2

1.7

mA

voltage main)

mode^{Note 5}

HS (high-

fMX = 20 MHz^{Note 2}

V^DD= 5.0 V

fMX = 20 MHz^{Note 2}

,

Normal

operation

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

2.8

3.0

2.8

3.0

1.8

1.1

3.5

3.6

4.4

4.6

4.4

4.6

2.6

1.7

4.9

5.0

mA

μA

speed main)

mode^{Note 5}

Normal

operation

V^DD= 3.0 V

fMX = 10 MHz^{Note 2}

V^DD= 5.0 V

fMX = 10 MHz^{Note 2}

Normal

operation

Normal

operation

V^DD= 3.0 V

LS (low-speed f^MX= 8 MHz^{Note 2}

,

Normal

operation

main) mode^Note

V^DD= 3.0 V

5

fMX = 8 MHz^{Note 2}

,

Normal

operation

V^DD= 2.0 V

Subsystem

clock

operation

f^SUB= 32.768 kHz^NoteNormal

4

operation

μA

T = −40°C

A

fSUB = 32.768 kHz^NoteNormal

Square wave input

3.6

3.7

4.9

5.0

μA

4

operation

Resonator connection

T = +25°C

A

fSUB = 32.768 kHz^NoteNormal

Square wave input

3.7

3.8

5.5

5.6

μA

4

operation

Resonator connection

T = +50°C

A

fSUB = 32.768 kHz^NoteNormal

Square wave input

3.8

3.9

6.3

6.4

μA

4

operation

Resonator connection

T = +70°C

A

fSUB = 32.768 kHz^NoteNormal

Square wave input

4.1

4.2

7.7

7.8

μA

4

operation

Resonator connection

TA = +85°C

(Notes and Remarks are listed on the next page.)

Page 29 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input

pin is fixed to V^DD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation

current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip

pull-up/pull-down resistors and the current flowing during data flash rewrite.

2. When high-speed on-chip oscillator and subsystem clock are stopped.

3. When high-speed system clock and subsystem clock are stopped.

4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low

power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer,

watchdog timer, and LCD controller/driver.

5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.

HS (high-speed main) mode: 2.7 V ≤ V^DD≤ 5.5 V@1 MHz to 24 MHz

2.4 V ≤ V^DD≤ 5.5 V@1 MHz to 16 MHz

LS (low-speed main) mode: 1.8 V ≤ V^DD≤ 5.5 V@1 MHz to 8 MHz

LV (low-voltage main) mode: 1.6 V ≤ V^DD≤ 5.5 V@1 MHz to 4 MHz

Remarks 1. f^MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f^IH: High-speed on-chip oscillator clock frequency

3. f^SUB: Subsystem clock frequency (XT1 clock oscillation frequency)

4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C

Page 30 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(2/3)

Parameter Symbol

Conditions

f^IH= 24 MHz ^{Note 4}

MIN.

TYP.

0.44

0.40

260

MAX.

1.28

1.00

530

Unit

mA

μA

Supply

current

I^DD2

HALT

mode

HS (high-

VDD = 5.0 V

VDD = 3.0 V

VDD = 5.0 V

VDD = 3.0 V

VDD = 2.0 V

Note 2

speed main)

Note 1

mode^{Note 7}

fIH = 16 MHz ^{Note 4}

f^IH= 8 MHz ^{Note 4}

LS (low-

speed main)

260

530

μA

mode^{Note 7}

LV (low-

voltage

f^IH= 4 MHz ^{Note 4}

VDD = 3.0 V

VDD = 2.0 V

420

640

μA

main) mode

Note 7

HS (high-

fMX = 20 MHz^{Note 3}

V^DD= 5.0 V

fMX = 20 MHz^{Note 3}

,

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

0.28

0.45

0.28

0.45

0.19

0.26

0.19

0.26

95

1.00

1.17

1.00

1.17

0.60

0.67

0.60

0.67

330

mA

μA

speed main)

mode^{Note 7}

V^DD= 3.0 V

fMX = 10 MHz^{Note 3}

V^DD= 5.0 V

fMX = 10 MHz^{Note 3}

V^DD= 3.0 V

LS (low-

f^MX= 8 MHz^{Note 3}

V^DD= 3.0 V

,

speed main)

145

380

mode^{Note 7}

fMX = 8 MHz^{Note 3}

,

95

330

V^DD= 2.0 V

145

380

Subsystem

clock

operation

fSUB = 32.768 kHz^{Note 5}

T^A= −40°C

fSUB = 32.768 kHz^{Note 5}

0.31

0.50

0.37

0.56

0.46

0.65

0.57

0.76

0.85

1.04

0.17

0.23

0.32

0.43

0.71

0.57

0.76

0.57

0.76

1.17

1.36

1.97

2.16

3.37

3.56

0.50

1.10

1.90

3.30

T^A= +25°C

fSUB = 32.768 kHz^{Note 5}

T^A= +50°C

fSUB = 32.768 kHz^{Note 5}

T^A= +70°C

fSUB = 32.768 kHz^{Note 5}

T^A= +85°C

Note 6

IDD3

STOP

TA = −40°C

TA = +25°C

TA = +50°C

TA = +70°C

TA = +85°C

mode ^{Note 8}

(Notes and Remarks are listed on the next page.)

Page 31 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input

pin is fixed to V^DD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation

current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip

pull-up/pull-down resistors and the current flowing during data flash rewrite.

2. During HALT instruction execution by flash memory.

3. When high-speed on-chip oscillator and subsystem clock are stopped.

4. When high-speed system clock and subsystem clock are stopped.

5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting

ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not

including the current flowing into the 12-bit interval timer, watchdog timer, and LCD controller/driver.

6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.

7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.

HS (high-speed main) mode: 2.7 V ≤ V^DD≤ 5.5 V@1 MHz to 24 MHz

2.4 V ≤ V^DD≤ 5.5 V@1 MHz to 16 MHz

LS (low-speed main) mode: 1.8 V ≤ V^DD≤ 5.5 V@1 MHz to 8 MHz

LV (low-voltage main) mode: 1.6 V ≤ V^DD≤ 5.5 V@1 MHz to 4 MHz

8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.

Remarks 1. f^MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f^IH: High-speed on-chip oscillator clock frequency

3. f^SUB: Subsystem clock frequency (XT1 clock oscillation frequency)

4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

Page 32 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(3/3)

Parameter

Symbol

Conditions

MIN.

TYP.

0.20

MAX.

Unit

Note 1

Low-speed on-

chip oscillator

operating

I^FIL

μA

current

RTC operating

current

I^RTC

f^MAINis stopped

0.08

0.24

μA

Notes 1, 2, 3

12-bit interval

timer current

I^IT

Notes 1, 2, 4

Watchdog timer I^WDT

f^IL= 15 kHz

Notes 1, 2, 5

operating

current

A/D converter

operating

current

I^ADC

Notes 1, 6

When conversion

at maximum speed

Normal mode, AV^REFP= VDD = 5.0 V

1.3

0.5

1.7

0.7

mA

Low voltage mode, AVREFP = VDD = 3.0 V

Note 1

A/D converter

reference

IADREF

75.0

μA

voltage current

Note 1

Temperature

sensor

I^TMPS

75.0

operating

current

LVD operating

current

I^LVD

0.08

2.50

μA

Notes 1, 7

mA

Self-

I^FSP

12.20

Notes 1, 9

programming

operating

current

mA

μA

BGO operating

current

I^BGO

2.00

Notes 1, 8

LCD operating

current

ILCD1

Notes 11, 12

V^DD= EVDD = 5.0 V

V^L4= 5.0 V

External resistance division method

Internal voltage boosting method

0.04

1.12

0.63

0.12

0.20

3.70

2.20

0.50

Note 11

ILCD2

VDD = EVDD = 5.0 V

V^L4= 5.1 V (VLCD = 12H)

VDD = EVDD = 3.0 V

V^L4= 3.0 V (VLCD = 04H)

VDD = EVDD = 3.0 V

V^L4= 3.0 V

Note 11

Note 1

ILCD3

Capacitor split method

SNOOZE

operating

current

I^SNOZ

ADC operation

The mode is performed ^{Note 10}

0.50

1.20

0.60

1.44

mA

The A/D conversion operations are

performed, Low voltage mode, AV^REFP= VDD

= 3.0 V

CSI/UART operation

0.70

0.84

mA

(Notes and Remarks are listed on the next page.)

Page 33 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. Current flowing to VDD.

2. When high speed on-chip oscillator and high-speed system clock are stopped.

3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip

oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of

either I^DD1or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the

low-speed on-chip oscillator is selected, I^FILshould be added. IDD2 subsystem clock operation includes the

operational current of the real-time clock.

4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip

oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of

either I^DD1or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the

low-speed on-chip oscillator is selected, IFIL should be added.

5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).

The supply current of the RL78 microcontrollers is the sum of I^DD1, IDD2 or IDD3 and IWDT when the watchdog

timer is in operation.

6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of I^DD1or

I^DD2and IADC when the A/D converter operates in an operation mode or the HALT mode.

7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of I^DD1, IDD2

or I^DD3and ILVD when the LVD circuit is in operation.

8. Current flowing only during data flash rewrite.

9. Current flowing only during self programming.

10. For shift time to the SNOOZE mod.

11. Current flowing only to the LCD controller/driver. The supply current value of the RL78 microcontrollers is the

sum of the LCD operating current (I^LCD1, ILCD2 or ILCD3) to the supply current (IDD1 or IDD2) when the LCD

controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the

LCD panel.

The TYP. value and MAX. value are following conditions.

• When f^SUBis selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H)

• 4-Time-Slice, 1/3 Bias Method

12. Not including the current that flows through the external divider resistor when the external resistance division

method is used.

Remarks 1. f^IL: Low-speed on-chip oscillator clock frequency

2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

3. f^CLK: CPU/peripheral hardware clock frequency

4. Temperature condition of the TYP. value is T^A= 25°C

Page 34 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.4 AC Characteristics

2.4.1 Basic operation

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

μs

Instruction cycle (minimum

instruction execution time)

T^CY

Main

system

clock (f^MAIN)

operation

HS (high-speed 2.7 V

≤

V

DD

≤

5.5 V 0.04167

1

main) mode

2.4 V

VDD < 2.7 V 0.0625

μs

LV (low voltage 1.6 V

main) mode

VDD

≤

5.5 V 0.25

5.5 V 0.125

5.5 V 28.5

5.5 V 0.04167

μs

LS (low-speed 1.8 V

main) mode

≤

V

DD

1

μs

Subsystem clock (fSUB)

operation

1.8 V

VDD

30.5

31.3

In the self

programmin main) mode

g mode

HS (high-speed 2.7 V

≤

V

DD

1

μs

2.4 V

VDD < 2.7 V 0.0625

LV (low voltage 1.8 V

main) mode

VDD

≤

5.5 V 0.25

LS (low-speed 1.8 V

main) mode

≤

VDD

≤

5.5 V 0.125

1

μs

External main system clock

frequency

f^EX

2.7 V ≤ VDD ≤ 5.5 V

1.0

32

20.0

16.0

8.0

MHz

kHz

ns

2.4 V ≤ VDD < 2.7 V

1.8 V ≤ VDD < 2.4 V

1.6 V ≤ VDD < 1.8 V

4.0

fEXS

35

External main system clock input t^EXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V

high-level width, low-level width

24

2.4 V ≤ VDD < 2.7 V

30

60

ns

μs

1.8 V ≤ VDD < 2.4 V

1.6 V ≤ VDD < 1.8 V

120

13.7

tEXHS,

t^EXLS

TI00 to TI07 input high-level

width, low-level width

tTIH,

t^TIL

1/f^MCK+10

ns

TO00 to TO07 output frequency

fTO

HS (high-speed

main) mode

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD < 2.7 V

1.8 V ≤ EV^DD≤ 5.5 V

16

8

MHz

4

LS (low-speed

main) mode

4

LV (low voltage

main) mode

1.6 V ≤ EV^DD≤ 5.5 V

2

MHz

PCLBUZ0, PCLBUZ1 output

frequency

f^PCL

HS (high-speed

main) mode

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD < 2.7 V

1.8 V ≤ EV^DD≤ 5.5 V

16

8

MHz

4

LS (low-speed

main) mode

4

LV (low-voltage

main) mode

1.8 V ≤ EV^DD≤ 5.5 V

1.6 V ≤ EVDD < 1.8 V

1.6 V ≤ V^DD≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD < 1.8 V

4

2

MHz

μs

Interrupt input high-level width,

low-level width

tINTH,

t^INTL

INTP0

1

INTP1 to INTP7

KR0 to KR3

μs

Key interrupt input low-level width tKR

250

1

ns

μs

RESET low-level width

tRSL

10

μs

Remark f^MCK: Timer array unit operation clock frequency

(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7))

Page 35 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Minimum Instruction Execution Time during Main System Clock Operation

T^CYvs VDD (HS (high-speed main) mode)

10

1.0

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

0.1

0.0625

0.04167

0.01

0

1.0

2.0

3.0

4.0

5.0

6.0

2.4 2.7

5.5

Supply voltage VDD [V]

T^CYvs VDD (LS (low-speed main) mode)

10

1.0

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

0.125

0.1

0.01

0

5.5

1.0

2.0

1.8

3.0

4.0

5.0

6.0

Supply voltage VDD [V]

Page 36 of 131

R01DS0157EJ0210 Rev.2.10

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

TCY vs VDD (LV (low-voltage main) mode)

10

1.0

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

0.25

0.1

0.01

5.5

0

1.0

2.0

1.6 1.8

3.0

4.0

5.0

6.0

Supply voltage VDD [V]

AC Timing Test Points

V

IH/VOH

V

IH/VOH

Test points

VIL/VOL

External System Clock Timing

1/f^EX/

1/f^EXS

t

EXL

/

t

EXH

/

EXLS

EXHS

EXCLK/EXCLKS

Page 37 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

TI/TO Timing

t

TIL

tTIH

TI00 to TI07

1/f^TO

TO00 to TO07

Interrupt Request Input Timing

t

INTL

tINTH

INTP0 to INTP7

Key Interrupt Input Timing

t

KR

KR0 to KR3

RESET Input Timing

t

RSL

RESET

Page 38 of 131

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Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.5 Peripheral Functions Characteristics

AC Timing Test Points

VIH/VOH

Test points

VIL/VOL

2.5.1 Serial array unit

(1) During communication at same potential (UART mode)

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed LS (low-speed LV (low-voltage

main) Mode main) Mode main) Mode

MIN. MAX. MIN. MAX. MIN. MAX.

Unit

Transfer rate ^{Note 1}

2.4 V ≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

4.0

1.3

0.6

Mbps

Note 2

f^MCK= fCLK

1.8 V ≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

1.3

0.6

Mbps

Note 2

f^MCK= fCLK

1.6 V ≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

0.6

Mbps

Note 2

fMCK = fCLK

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. The maximum operating frequencies of the CPU/peripheral hardware clock (f^CLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V ≤ V^DD≤ 5.5 V)

16 MHz (2.4 V ≤ V^DD≤ 5.5 V)

8 MHz (1.8 V ≤ V^DD≤ 5.5 V)

4 MHz (1.6 V ≤ V^DD≤ 5.5 V)

LS (low-speed main) mode:

LV (low-voltage main) mode:

Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

Page 39 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

UART mode connection diagram (during communication at same potential)

TxDq

RL78 microcontroller

RxDq

Rx

Tx

User's device

UART mode bit width (during communication at same potential) (reference)

1/Transfer rate

High-/Low-bit width

Baud rate error tolerance

TxDq

RxDq

Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 1)

2. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))

Page 40 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed LS (low-speed LV (low-voltage

main) Mode main) Mode main) Mode

MIN. MAX. MIN. MAX. MIN. MAX.

Unit

SCKp cycle time

tKCY1

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

167

500

1000

ns

Note 1

250

500

1000

Note 1

500

1000

Note 1

1000

Note 1

SCKp high-/low-level width t^KH1,

t^KL1

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

t^KCY1/2

ns

− 12

− 50

t^KCY1/2

− 18

− 50

t^KCY1/2

− 38

− 50

t^KCY1/2

tKCY1/2

− 50

t^KCY1/2

− 100

SIp setup time (to SCKp↑)

t^SIK1

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

44

75

110

220

19

ns

Note 2

SIp hold time (from SCKp↑) t^KSI1

19

Note 3

19

Delay time from SCKp↓ to

t^KSO1

C = 30 pF 2.4 V ≤ EV^DD≤ 5.5 V

Note 5

25

ns

SOp output ^{Note 4}

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

Notes 1. For CSI00, set a cycle of 2/f^MCKor longer. For CSI01, set a cycle of 4/fMCK or longer.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

5. C is the load capacitance of the SCKp and SOp output lines.

Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin

by using port input mode register g (PIMg) and port output mode register g (POMg).

(Remarks are listed on the next page.)

Page 41 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM numbers (g = 1)

2. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn).

m: Unit number, n: Channel number (mn = 00, 01))

(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(1/2)

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed LS (low-speed LV (low-voltage Unit

main) Mode

MIN. MAX. MIN.

MAX. MIN. MAX.

SCKp cycle time^Note

5

t^KCY2

4.0 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD ≤ 5.5 V

20 MHz < fMCK

8/fMCK

ns

fMCK ≤ 20 MHz

16 MHz < fMCK

fMCK ≤ 16 MHz

6/fMCK

8/fMCK

6/fMCK

ns

6/fMCK

6/f^MCK

and

6/f^MCK

500

1.8 V ≤ EVDD < 2.4 V

1.6 V ≤ EVDD < 1.8 V

4.0 V ≤ EV^DD≤ 5.5 V

6/fMCK

ns

SCKp high-/low-

level width

tKH2,

t^KCY2/2

t^KL2

− 7

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD < 2.7 V

1.8 V ≤ EVDD < 2.4 V

1.6 V ≤ EVDD < 1.8 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD < 2.7 V

1.8 V ≤ EVDD < 2.4 V

1.6 V ≤ EVDD < 1.8 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD < 2.4 V

1.6 V ≤ EVDD < 1.8 V

t^KCY2/2

tKCY2/2

ns

− 8

t^KCY2/2

− 18

t^KCY2/2

− 18

t^KCY2/2

− 66

SIp setup time

(to SCKp↑)^{Note 1}

t^SIK2

1/f^MCK

+ 20

1/f^MCK

+ 30

1/f^MCK

+ 30

1/f^MCK

+ 30

1/f^MCK

+ 30

1/f^MCK

+ 30

1/f^MCK

+ 30

1/f^MCK

+ 30

ns

1/f^MCK

+ 40

SIp hold time

(from SCKp↑)^{Note 2}

t^KSI2

1/f^MCK

+ 31

1/f^MCK

+ 31

1/f^MCK

+ 31

1/f^MCK

+ 31

1/f^MCK

+ 31

1/f^MCK

+

250

(Notes, Caution, and Remarks are listed on the next page.)

Page 42 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(2/2)

(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS LS (low- LV (low- Unit

(high- speed voltage

Para Symbol Conditions

meter

speed main)

main)

Mode

main)

Mode

Delay time from

SCKp↓ to SOp

output ^{Note 3}

t^KSO2

C = 30 pF ^{Note 4}4.0 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2/f^MCK

+ 44

2/f^MCK

+ 110

2/f^MCK

+ 110

ns

2/f^MCK

+ 44

2/f^MCK

+ 110

2/f^MCK

+ 110

2.4 V ≤ EVDD < 2.7 V

2/f^MCK

+ 75

2/f^MCK

+ 110

2/f^MCK

+ 110

1.8 V ≤ EVDD < 2.4 V

2/f^MCK

+ 110

2/f^MCK

+ 110

1.6 V ≤ EVDD < 1.8 V

2/f^MCK

+ 220

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps

Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin

by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),

n: Channel number (n = 0, 1), g: PIM number (g = 1)

2. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))

Page 43 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

CSI mode connection diagram (during communication at same potential)

SCKp

SIp

SCK

SO

RL78

microcontroller

User's device

SOp

SI

CSI mode serial transfer timing (during communication at same potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)

t

KCY1,2

t

KL1,2

t

KH1,2

SCKp

t

SIK1,2

t

KSI1, 2

SIp

Input data

t

KSO1,2

Output data

SOp

CSI mode serial transfer timing (during communication at same potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

t

KCY1, 2

t

KH1, 2

t

KL1, 2

SCKp

t

SIK1, 2

t

KSI1, 2

SIp

Input data

t

KSO1, 2

Output data

SOp

Remarks 1. p: CSI number (p = 00, 01)

2. m: Unit number, n: Channel number (mn = 00, 01)

Page 44 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)

(1/2)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage Unit

main) Mode

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer rate

Reception 4.0 V ≤ EV^DD≤ 5.5 V,

2.7 V ≤ V^b≤ 4.0 V

f^MCK/6

Note 1

f^MCK/6

Note 1

bps

Note 1

Theoretical value of the

4.0

1.3

0.6

Mbps

maximum transfer rate

Note 3

f^MCK= fCLK

2.7 V ≤ EVDD < 4.0 V,

2.3 V ≤ V^b≤ 2.7 V

f^MCK/6

Note 1

f^MCK/6

Note 1

bps

Note 1

Theoretical value of the

4.0

1.3

0.6

Mbps

maximum transfer rate

Note 3

f^MCK= fCLK

2.4 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V

f^MCK/6

Note 1

f^MCK/6

Note 1

bps

Note 1

Theoretical value of the

4.0

1.3

0.6

Mbps

maximum transfer rate

Note 3

f^MCK= fCLK

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V

Theoretical value of the

f^MCK/6

bps

Notes 1, 2

1.3

0.6

Mbps

maximum transfer rate

Note 3

f^MCK= fCLK

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. Use it with EV^DD≥ Vb.

3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V ≤ V^DD≤ 5.5 V)

16 MHz (2.4 V ≤ V^DD≤ 5.5 V)

8 MHz (1.8 V ≤ V^DD≤ 5.5 V)

4 MHz (1.6 V ≤ V^DD≤ 5.5 V)

LS (low-speed main) mode:

LV (low-voltage main) mode:

Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EV^DDtolerance (64-pin products)) mode for the TxDq pin by using port input mode

register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC characteristics

with TTL input buffer selected.

Remarks 1. V^b[V]: Communication line voltage

2. q: UART number (q = 0), g: PIM and POM number (g = 1)

3. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)

Page 45 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)

(2/2)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer rate

Transmissio 4.0 V ≤ EVDD ≤ 5.5 V,

Note 1

Note 1 bps

n

2.7 V ≤ V^b≤ 4.0 V

Theoretical value of the

maximum transfer rate

= 50 pF, R = 1.4 k

= 2.7 V

2.8^{Note 2}

2.8^{Note 2}Mbps

C

b

Ω,

Vb

2.7 V ≤ EVDD < 4.0 V,

2.3 V ≤ V^b≤ 2.7 V

Note 3

Note 3 bps

Theoretical value of the

maximum transfer rate

1.2^{Note 4}

1.2^{Note 4}Mbps

Cb

= 50 pF, R

b

= 2.7 kΩ

Vb

= 2.3 V

2.4 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V

Note 6

Note 6 bps

Theoretical value of the

maximum transfer rate

0.43^{Note 7}

0.43^{Note 7}Mbps

Cb

= 50 pF, R

b

= 5.5 kΩ

Vb

= 1.6 V

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V

Notes

5, 6

Notes

5, 6

bps

Theoretical value of the

maximum transfer rate

0.43^{Note 7}

0.43^{Note 7}Mbps

Cb

= 50 pF, R

b

= 5.5 kΩ,

Vb

= 1.6 V

Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum

transfer rate.

Expression for calculating the transfer rate when 4.0 V ≤ EV^DD≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V

1

Maximum transfer rate =

[bps]

2.2

V^b

{−C^b× Rb × ln (1 −

)} × 3

1

2.2

V^b

− {−Cb × Rb × ln (1 −

)}

Transfer rate × 2

Baud rate error (theoretical value) =

× 100 [%]

1

(

) × Number of transferred bits

Transfer rate

* This value is the theoretical value of the relative difference between the transmission and reception sides.

2. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.

Page 46 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum

transfer rate.

Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V

1

Maximum transfer rate =

[bps]

2.0

V^b

{−C^b× Rb × ln (1 −

)} × 3

1

2.0

V^b

− {−Cb × Rb × ln (1 −

)}

Transfer rate × 2

Baud rate error (theoretical value) =

× 100 [%]

1

(

) × Number of transferred bits

Transfer rate

* This value is the theoretical value of the relative difference between the transmission and reception sides.

4. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

5. Use it with EV^DD≥ Vb.

6. The smaller maximum transfer rate derived by using f^MCK/6 or the following expression is the valid maximum

transfer rate.

Expression for calculating the transfer rate when 1.8 V ≤ EV^DD< 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V

1

Maximum transfer rate =

[bps]

1.5

V^b

{−C^b× Rb × ln (1 −

)} × 3

1

1.5

V^b

− {−Cb × Rb × ln (1 −

)}

Transfer rate × 2

Baud rate error (theoretical value) =

× 100 [%]

1

(

) × Number of transferred bits

Transfer rate

* This value is the theoretical value of the relative difference between the transmission and reception sides.

7. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EV^DDtolerance (64-pin products)) mode for the TxDq pin by using port input mode

register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC characteristics

with TTL input buffer selected.

Page 47 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

UART mode connection diagram (during communication at different potential)

Vb

R

b

TxDq

RL78 microcontroller

Rx

Tx

User's device

RxDq

UART mode bit width (during communication at different potential) (reference)

1/Transfer rate

Low-bit width

High-bit width

Baud rate error tolerance

TxDq

1/Transfer rate

High-/Low-bit width

Baud rate error tolerance

RxDq

Remarks 1. R^b[Ω]:Communication line (TxDq) pull-up resistance,

C^b[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage

2. q: UART number (q = 0, 1), g: PIM and POM number (g = 1)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))

Page 48 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,

corresponding CSI00 only)

(T^A= −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high- LS (low-speed

speed main) main) Mode voltage main)

Mode Mode

MIN. MAX. MIN. MAX. MIN. MAX.

LV (low-

Unit

SCKp cycle time

tKCY1

tKCY1 ≥ 2/fCLK 4.0 V ≤ EV^DD≤ 5.5 V,

2.7 V ≤ V^b≤ 4.0 V,

200

1150

ns

Note 1

C^b= 20 pF, Rb = 1.4 kΩ

2.7 V ≤ EVDD < 4.0 V,

2.3 V ≤ V^b≤ 2.7 V,

300

Note 1

1150

Note 1

1150

Note 1

C^b= 20 pF, Rb = 2.7 kΩ

SCKp high-level width

SCKp low-level width

tKH1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, t^KCY1/2

t^KCY1/2

ns

− 50

C^b= 20 pF, Rb = 1.4 kΩ

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, t^KCY1/2

t^KCY1/2

− 120

C^b= 20 pF, Rb = 2.7 kΩ

tKL1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, t^KCY1/2

t^KCY1/2

− 7

− 50

C^b= 20 pF, Rb = 1.4 kΩ

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, t^KCY1/2

t^KCY1/2

− 10

− 50

C^b= 20 pF, Rb = 2.7 kΩ

SIp setup time

(to SCKp↑) ^{Note 2}

t^SIK1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

58

479

10

479

10

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 121

C^b= 20 pF, Rb = 2.7 kΩ

SIp hold time

(from SCKp↑) ^{Note 2}

t^KSI1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

10

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 20 pF, Rb = 2.7 kΩ

10

Delay time from SCKp↓ to t^KSO1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

60

SOp output ^{Note 2}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 20 pF, Rb = 2.7 kΩ

130

SIp setup time

(to SCKp↓) ^{Note 3}

t^SIK1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

23

33

10

110

10

110

10

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 20 pF, Rb = 2.7 kΩ

SIp hold time

(from SCKp↓) ^{Note 3}

t^KSI1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 20 pF, Rb = 2.7 kΩ

10

Delay time from SCKp↑ to t^KSO1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 20 pF, Rb = 1.4 kΩ

10

SOp output ^{Note 3}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 20 pF, Rb = 2.7 kΩ

(Notes, Caution and Remarks are listed on the next page.)

Page 49 of 131

R01DS0157EJ0210 Rev.2.10

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EV^DDtolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC

characteristics with TTL input buffer selected.

Remarks 1. R^b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load

capacitance, V^b[V]: Communication line voltage

2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM number (g = 1)

3. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)

Page 50 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high- LS (low-speed

speed main) main) Mode voltage main)

Mode Mode

MIN. MAX. MIN. MAX. MIN. MAX.

LV (low-

Unit

SCKp cycle time

tKCY1

tKCY1 ≥ 4/fCLK

4.0 V ≤ EV^DD≤ 5.5 V,

2.7 V ≤ V^b≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

300

1150

ns

2.7 V ≤ EVDD < 4.0 V,

2.3 V ≤ V^b≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

500

2.4 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1150

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^Note

,

C^b= 30 pF, Rb = 5.5 kΩ

SCKp high-level width tKH1

4.0 V ≤ EV^DD≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

t^KCY1/2

ns

− 75

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

t^KCY1/2

− 170

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V^Note

C^b= 30 pF, Rb = 5.5 kΩ

t^KCY1/2

tKCY1/2

− 458

,

t^KCY1/2

− 458

SCKp low-level width

tKL1

4.0 V ≤ EV^DD≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

t^KCY1/2

− 12

− 50

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

t^KCY1/2

tKCY1/2

− 18

− 50

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V^Note

C^b= 30 pF, Rb = 5.5 kΩ

t^KCY1/2

− 50

,

t^KCY1/2

− 50

Note

Use it with EVDD ≥ Vb.

Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EV^DDtolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC

characteristics with TTL input buffer selected.

Page 51 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

Unit

HS (high-

speed main) speed main) voltage main)

Mode Mode Mode

MIN. MAX. MIN. MAX. MIN. MAX.

LS (low-

LV (low-

SIp setup time

t^SIK1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

81

479

ns

(to SCKp↑) ^{Note 1}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

177

479

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

SIp hold time

t^KSI1

t^KSO1

t^SIK1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

19

ns

(from SCKp↑) ^{Note 1}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

Delay time from SCKp↓ to

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

100

195

483

100

195

483

100

195

483

ns

SOp output ^{Note 1}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

SIp setup time

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

44

110

ns

(to SCKp↓) ^{Note 2}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

110

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

Notes

1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. Use it with EV^DD≥ Vb.

Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC

characteristics with TTL input buffer selected.

Page 52 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

Unit

HS (high-

speed main) speed main) voltage main)

Mode Mode Mode

MIN. MAX. MIN. MAX. MIN. MAX.

LS (low-

LV (low-

SIp hold time

t^KSI1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

19

ns

(from SCKp↓) ^{Note 2}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

Delay time from SCKp↑ to

t^KSO1

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

25

ns

SOp output ^{Note 2}

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^{Note 3}

,

C^b= 30 pF, Rb = 5.5 kΩ

Notes

1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. Use it with EV^DD≥ Vb.

Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V^DDtolerance (32-pin to 52-

pin products)/EV^DDtolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC

characteristics with TTL input buffer selected.

Page 53 of 131

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

CSI mode connection diagram (during communication at different potential)

Vb

R

b

Rb

SCKp

SIp

SCK

SO

User's device

RL78

microcontroller

SOp

SI

Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load

capacitance, V^b[V]: Communication line voltage

2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM

number (g = 1)

3. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)

Page 54 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

CSI mode serial transfer timing (master mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)

t

KCY1

t

KL1

t

KH1

SCKp

t

SIK1

t

KSI1

SIp

Input data

t

KSO1

SOp

Output data

CSI mode serial transfer timing (master mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

t

KCY1

t

KL1

t

KH1

SCKp

t

SIK1

t

KSI1

SIp

Input data

t

KSO1

Output data

SOp

Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM number (g = 1)

Page 55 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter Symbol Conditions

(1/2)

Unit

HS (high-

speed main) main) mode voltage main)

mode mode

MIN. MAX. MIN. MAX. MIN. MAX.

LS (low-speed

LV (low-

SCKp cycle time ^{Note 1}tKCY2

4.0 V

2.7 V

≤

EVDD

≤

5.5 V,

20 MHz < f^MCK

≤

24 MHz 12/fMCK

ns

Vb ≤ 4.0 V

8 MHz < fMCK

4 MHz < fMCK

≤

20 MHz

8 MHz

10/fMCK

8/fMCK

6/fMCK

≤

16/fMCK

10/fMCK

fMCK

≤

4 MHz

10/fMCK

2.7 V

2.3 V

≤

EVDD < 4.0 V,

2.7 V

20 MHz < f^MCK

16 MHz < fMCK

≤

24 MHz 16/fMCK

20 MHz 14/fMCK

V ≤

b

8 MHz < fMCK

4 MHz < fMCK

≤

16 MHz

8 MHz

12/fMCK

8/fMCK

6/fMCK

≤

16/fMCK

10/fMCK

fMCK

≤

4 MHz

10/fMCK

2.4 V

1.6 V

≤

EVDD < 3.3 V,

2.0 V

20 MHz < f^MCK

16 MHz < fMCK

≤

24 MHz 36/fMCK

20 MHz 32/fMCK

V ≤

b

8 MHz < fMCK

4 MHz < fMCK

≤

16 MHz

26/fMCK

16/fMCK

10/fMCK

≤

8 MHz

16/fMCK

10/fMCK

16/fMCK

10/fMCK

f

MCK

≤

4 MHz

4 MHz < f^MCK

4 MHz

10/fMCK

1.8 V

1.6 V

≤

EVDD < 3.3 V,

2.0 V^{Note 2}

≤

V ≤

b

fMCK

≤

SCKp high-/low-level

width

t^KH2,

t^KL2

4.0 V ≤ EV^DD≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

tKCY2/2

− 12

− 50

tKCY2/2

ns

− 18

− 50

tKCY2/2

− 50

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^{Note 2}

tKCY2/2

− 50

SIp setup time

(to SCKp↑) ^{Note 3}

t^SIK2

4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

1/fMCK

20

+

1/fMCK

30

+

1/fMCK

30

+

1/fMCK

20

1/fMCK

30

1/fMCK

30

1/fMCK

30

1/fMCK

30

1/fMCK

30

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^{Note 2}

1/fMCK

30

1/fMCK

30

SIp hold time

(from SCKp↑) ^{Note 4}

t^KSI2

4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

1/fMCK

31

+

1/fMCK

31

1/fMCK

31

1/fMCK

31

1/fMCK

31

1/fMCK

31

1/fMCK

31

1/fMCK

31

1/fMCK

31

1.8 V ≤ EVDD < 3.3 V,

1.6 V ≤ V^b≤ 2.0 V ^{Note 2}

1/fMCK

31

1/fMCK

31

(Notes, Caution and Remarks are listed on the next page.)

Page 56 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)

(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(2/2)

Parameter

Symbol

Conditions

Unit

HS (high-

speed main) main) mode voltage main)

mode mode

MIN. MAX. MIN. MAX. MIN. MAX.

LS (low-speed

LV (low-

Delay time from SCKp↓ t^KSO2

4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

C^b= 30 pF, Rb = 1.4 kΩ

2/f^MCK

+ 120

2/fMCK

ns

to SOp output ^{Note 5}

+ 573

2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

C^b= 30 pF, Rb = 2.7 kΩ

2/f^MCK

+ 214

2/fMCK

+ 573

2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

C^b= 30 pF, Rb = 5.5 kΩ

2/f^MCK

+ 573

2/fMCK

+ 573

1.8 V ≤ EVDD < 3.3 V,

2/f^MCK

+ 573

2/fMCK

1.6 V ≤ V^b≤ 2.0 V ^{Note 2}

,

+ 573

C^b= 30 pF, Rb = 5.5 kΩ

Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps

2. Use it with EV^DD≥ Vb.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V^DDtolerance

(32-pin to 52-pin products)/EV^DDtolerance (64-pin products)) mode for the SOp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For V^IHand VIL, see the DC

characteristics with TTL input buffer selected.

CSI mode connection diagram (during communication at different potential)

<Slave>

V

b

R

b

SCKp

SIp

SCK

SO

User's device

RL78

microcontroller

SOp

SI

Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,

V^b[V]: Communication line voltage

2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM number (g = 1)

3. f^MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))

Page 57 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

CSI mode serial transfer timing (slave mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)

t

KCY2

t

KL2

t

KH2

SCKp

t

SIK2

t

KSI2

SIp

Input data

t

KSO2

Output data

SOp

CSI mode serial transfer timing (slave mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

t

KCY2

t

KL2

t

KH2

SCKp

t

SIK2

t

KSI2

SIp

Input data

t

KSO2

Output data

SOp

Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM number (g = 1)

Page 58 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.5.2 Serial interface IICA

(1) I²C standard mode

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high- LS (low-speed

speed main) main) Mode voltage main)

Mode Mode

MIN. MAX. MIN. MIN. MAX. MIN.

LV (low-

Unit

kHz

Standard

mode:

SCLA0 clock frequency

fSCL

2.7 V ≤ EV^DD≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

0

100

0

100

0

100

0

f^CLK≥ 1 MHz

0

Setup time of restart condition

tSU:STA

tHD:STA

tLOW

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

1.6 V ≤ EVDD ≤ 5.5 V

4.7

4.0

4.7

4.0

250

0

μs

ns

μs

Hold time ^{Note 1}

4.0

Hold time when SCLA0 = “L”

Hold time when SCLA0 = “H”

Data setup time (reception)

Data hold time (transmission)^{Note 2}

Setup time of stop condition

Bus-free time

4.7

tHIGH

4.0

tSU:DAT

tHD:DAT

tSU:STO

tBUF

250

0

3.45

0

3.45

0

4.0

4.7

(Notes and Remark are listed on the next page.)

Page 59 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.

2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK

(acknowledge) timing.

Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up

resistor) at that time in each mode are as follows.

Standard mode: C^b= 400 pF, Rb = 2.7 kΩ

Page 60 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(2) I²C fast mode

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high- LS (low-speed

speed main) main) Mode voltage main)

Mode Mode

MIN. MAX. MIN. MIN. MAX. MIN.

LV (low-

Unit

Fast mode:

SCLA0 clock frequency

Setup time of restart condition

Hold time ^{Note 1}

fSCL

2.7 V ≤ EV^DD≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

0

400

0

400

0

400

kHz

μs

ns

μs

f^CLK≥ 3.5

MHz

0

tSU:STA

tHD:STA

tLOW

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

2.7 V ≤ EVDD ≤ 5.5 V

2.4 V ≤ EVDD ≤ 5.5 V

1.8 V ≤ EVDD ≤ 5.5 V

0.6

1.3

0.6

100

0

0.6

1.3

0.6

100

0

0.6

Hold time when SCLA0 = “L”

Hold time when SCLA0 = “H”

Data setup time (reception)

Data hold time (transmission)^{Note 2}

Setup time of stop condition

Bus-free time

1.3

tHIGH

0.6

tSU:DAT

tHD:DAT

tSU:STO

tBUF

100

0

0.9

0

0.6

1.3

0.6

1.3

Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.

2. The maximum value (MAX.) of t^HD:DATis during normal transfer and a wait state is inserted in the ACK

(acknowledge) timing.

Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up

resistor) at that time in each mode are as follows.

Fast mode:

C^b= 320 pF, Rb = 1.1 kΩ

Page 61 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(3) I²C fast mode plus

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed LS (low-speed LV (low-voltage Unit

main) Mode main) Mode main) Mode

MIN. MAX. MIN. MAX.

MIN.

0

MAX.

1000

Fast mode plus:

SCLA0 clock frequency

fSCL

2.7 V ≤ EV^DD≤ 5.5 V

⎯

kHz

f^CLK≥ 10 MHz

Setup time of restart

condition

t^SU:STA

2.7 V ≤ EVDD ≤ 5.5 V

0.26

⎯

μs

Hold time^{Note 1}

tHD:STA

2.7 V ≤ EVDD ≤ 5.5 V

0.26

0.5

⎯

μs

Hold time when SCLA0 =

“L”

t^LOW

Hold time when SCLA0 =

“H”

t^HIGH

2.7 V ≤ EVDD ≤ 5.5 V

0.26

50

⎯

μs

Data setup time

(reception)

t^SU:DAT

t^HD:DAT

t^SU:STO

tBUF

Data hold time

(transmission)^{Note 2}

0

0.45

Setup time of stop

condition

0.26

0.5

Bus-free time

Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.

2. The maximum value (MAX.) of t^HD:DATis during normal transfer and a wait state is inserted in the ACK

(acknowledge) timing.

Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection

register (PIOR) is 1. At this time, the pin characteristics (I^OH1, IOL1, VOH1, VOL1) must satisfy the values in

the redirect destination.

Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up

resistor) at that time in each mode are as follows.

Fast mode plus: C^b= 120 pF, Rb = 1.1 kΩ

IICA serial transfer timing

t

LOW

SCLA0

SDAA0

t

HD:DAT

t

HIGH

SU:DAT

t

SU:STA

t

HD:STA

t

SU:STO

t

HD:STA

t

LOW

Stop

Start

Restart

condition

Stop

condition

condition condition

Page 62 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Classification of A/D converter characteristics

Reference Voltage

Reference voltage (+) = AVREFP Reference voltage (+) = VDD

Reference voltage (−) = AVREFM Reference voltage (−) = VSS

Reference voltage (+) = VBGR

Input channel

ANI0, ANI1

Reference voltage (−) = AVREFM

−

Refer to 2.6.1 (3).

Refer to 2.6.1 (4).

ANI16 to ANI23

Refer to 2.6.1 (2).

Refer to 2.6.1 (1).

Internal reference voltage

−

Temperature sensor output voltage

(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1

(ADREFM = 1), target pin : internal reference voltage, and temperature sensor output voltage

(T^A= −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) =

AV^REFP, Reference voltage (−) = AVREFM = 0 V)

Parameter

Resolution

Symbol

RES

Conditions

MIN.

8

TYP.

MAX.

10

Unit

bit

Overall error^{Note 1}

AINL

10-bit resolution

1.8 V ≤ V^DD≤ 5.5 V

1.2

3.5

7.0

39

LSB

μs

Note 3

1.6 V ≤ VDD ≤ 5.5 V ^{Note 4}

3.6 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD ≤ 5.5 V

AV^REFP= VDD

Conversion time

tCONV

10-bit resolution

2.375

3.5625

17

Target pin: Internal reference

voltage, and temperature

sensor output voltage (HS

(high-speed main) mode)

39

μs

39

μs

Zero-scale error^{Notes 1, 2}E_ZS

Full-scale error^{Notes 1, 2}E_FS

1.8 V ≤ AV^REFP≤ 5.5 V

1.6 V ≤ AVREFP ≤ 5.5 V ^{Note 4}

1.8 V ≤ AV^REFP≤ 5.5 V

1.6 V ≤ AVREFP ≤ 5.5 V ^{Note 4}

1.8 V ≤ V^DD≤ 5.5 V

0.25

0.50

0.25

0.50

2.5

%FSR

LSB

10-bit resolution

Note 3

AV^REFP= VDD

10-bit resolution

Note 3

AV^REFP= VDD

Integral linearity

error^{Note 1}

ILE

10-bit resolution

Note 3

1.6 V ≤ VDD ≤ 5.5 V ^{Note 4}

5.0

LSB

AVREFP = VDD

Differential linearity

error^{Note 1}

DLE

10-bit resolution

1.8 V ≤ V^DD≤ 5.5 V

1.6 V ≤ VDD ≤ 5.5 V ^{Note 4}

1.5

LSB

Note 3

AV^REFP= VDD

2.0

LSB

Note 5

Analog input voltage

VAIN

VBGR

Internal reference voltage

V^BGR

V

(2.4 V ≤ V^DD≤ 5.5 V, HS (high-speed main) mode)

Note 5

Temperature sensor output voltage

V^TMPS25

V

(2.4 V ≤ V^DD≤ 5.5 V, HS (high-speed main) mode)

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When AV^REFP< VDD, the MAX. values are as follows.

Overall error: Add 1.0 LSB to the MAX. value when AV^REFP= VDD.

Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AV^REFP= VDD.

Integral linearity error/Differential linearity error: Add 0.5 LSB to the MAX. value when AV^REFP= VDD.

4. Values when the conversion time is set to 57 μs (min.) and 95 μs (max.).

5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

Page 63 of 131

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1

(ADREFM = 1), target pin : ANI16 to ANI23

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) =

AVREFP, Reference voltage (−) = AVREFM = 0 V)

Parameter

Symbol

RES

Conditions

MIN.

8

TYP.

MAX.

10

Unit

bit

Resolution

Overall error^{Note 1}

Conversion time

AINL

10-bit resolution

1.8 V ≤ AV^REFP≤ 5.5 V

1.2

5.0

LSB

AV^REFP= EVDD = VDD

1.6 V ≤ AVREFP ≤ 5.5 V

8.5

Note 3

Note 4

tCONV

10-bit resolution

3.6 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V

1.8 V ≤ VDD ≤ 5.5 V

1.6 V ≤ VDD ≤ 5.5 V

1.8 V ≤ AV^REFP≤ 5.5 V

2.125

3.1875

17

39

μs

AV^REFP= EVDD = VDD

39

Note 3

39

μs

57

95

μs

Zero-scale error^{Notes 1, 2}

Full-scale error^{Notes 1, 2}

Integral linearity error^{Note 1}

E_ZS

0.35

0.60

%FSR

10-bit resolution

Note

AV^REFP= EVDD = VDD

1.6 V ≤ AVREFP ≤ 5.5 V

3

Note 4

10-bit resolution

E_FS

1.8 V ≤ AV^REFP≤ 5.5 V

0.35

0.60

%FSR

AV^REFP= EVDD = VDD

1.6 V ≤ AVREFP ≤ 5.5 V

3

Note 4

ILE

DLE

VAIN

10-bit resolution

1.8 V ≤ AV^REFP≤ 5.5 V

3.5

6.0

LSB

AV^REFP= EVDD = VDD

1.6 V ≤ AVREFP ≤ 5.5 V

Note 3

Note 4

Differential linearity error

10-bit resolution

1.8 V ≤ AV^REFP≤ 5.5 V

2.0

2.5

LSB

Note 1

AV^REFP= EVDD = VDD

1.6 V ≤ AVREFP ≤ 5.5 V

Note 3

Note 4

Analog input voltage

0

AV^REFP

and

V

EV^DD

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When AV^REFP< EVDD = VDD, the MAX. values are as follows.

Overall error: Add 4.0 LSB to the MAX. value when AV^REFP= VDD

.

Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AV^REFP= VDD

.

Integral linearity error/Differential linearity error: Add 2.0 LSB to the MAX. value when AV^REFP= VDD

.

4. When the conversion time is set to 57 μs (min.) and 95 μs (max.).

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0),

target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage

(T^A= −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−)

= VSS)

Parameter

Resolution

Symbol

RES

Conditions

MIN.

8

TYP.

MAX. Unit

10 bit

Overall error^{Note 1}

AINL

10-bit resolution

1.8 V ≤ VDD ≤ 5.5 V

1.2

7.0 LSB

10.5 LSB

1.6 V ≤ VDD ≤ 5.5 V

Note 3

Conversion time

tCONV

3.6 V ≤ VDD ≤ 5.5 V

2.125

39

95

39

μs

2.7 V ≤ VDD ≤ 5.5 V 3.1875

1.8 V ≤ VDD ≤ 5.5 V

1.6 V ≤ VDD ≤ 5.5 V

3.6 V ≤ VDD ≤ 5.5 V

17

57

10-bit resolution

2.375

Target pin: Internal

reference voltage, and

temperature sensor output

voltage (HS (high-speed

main) mode)

2.7 V ≤ VDD ≤ 5.5 V 3.5625

2.4 V ≤ VDD ≤ 5.5 V

17

Zero-scale error^{Notes 1, 2}

Full-scale error^{Notes 1, 2}

Integral linearity error^{Note 1}

EZS

EFS

ILE

1.8 V ≤ VDD ≤ 5.5 V

0.60 %FSR

0.85 %FSR

10-bit resolution

1.6 V ≤ VDD ≤ 5.5 V

Note 3

1.8 V ≤ VDD ≤ 5.5 V

0.60 %FSR

0.85 %FSR

1.6 V ≤ VDD ≤ 5.5 V

Note 3

1.8 V ≤ VDD ≤ 5.5 V

4.0 LSB

6.5 LSB

1.6 V ≤ VDD ≤ 5.5 V

Note 3

Differential linearity error ^{Note 1}DLE

1.8 V ≤ VDD ≤ 5.5 V

2.0 LSB

2.5 LSB

1.6 V ≤ VDD ≤ 5.5 V

Note 3

Analog input voltage

VAIN

ANI0, ANI1

0

VDD

V

ANI16 to ANI23

EVDD

Note 4

Internal reference voltage

V^BGR

(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)

Note 4

Temperature sensor output voltage

V^TMPS25

V

(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When the conversion time is set to 57 μs (min.) and 95 μs (max.).

4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

Page 65 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) =

AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23

(T^A= −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR ^{Note 3}, Reference

voltage (−) = AVREFM ^{Note 4}= 0 V, HS (high-speed main) mode)

Parameter

Symbol

RES

tCONV

EZS

Conditions

MIN.

TYP.

8

MAX.

Unit

bit

Resolution

Conversion time

8-bit resolution

2.4 V ≤ VDD ≤ 5.5 V

17

39

μs

Zero-scale error^{Notes 1, 2}

Integral linearity error^{Note 1}

Differential linearity error ^{Note 1}

Analog input voltage

2.4 V ≤ VDD ≤ 5.5 V

0.60

2.0

1.0

%FSR

LSB

V

ILE

DLE

VAIN

Note 3

0

VBGR

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

4. When reference voltage (−) = V^SS, the MAX. values are as follows.

Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (−) = AVREFM.

Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (−) = AV^REFM.

Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (−) = AVREFM.

2.6.2 Temperature sensor/internal reference voltage characteristics

(T^A= −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode)

Parameter

Symbol

Conditions

MIN.

TYP.

1.05

1.45

−3.6

MAX.

1.5

Unit

Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C

V

Internal reference voltage

Temperature coefficient

VBGR

Setting ADS register = 81H

1.38

FVTMPS

Temperature sensor that depends on the

temperature

mV/°C

Operation stabilization wait time

tAMP

5

μs

Page 66 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.6.3 POR circuit characteristics

(T^A= −40 to +85°C, VSS = 0 V)

Parameter

Detection voltage

Symbol

VPOR

Conditions

Power supply rise time

Power supply fall time

MIN.

1.47

1.46

300

TYP.

1.51

1.50

MAX.

1.55

1.54

Unit

V

VPDR

V

Minimum pulse width^Note

TPW

μs

Note Minimum time required for a POR reset when V^DDexceeds below VPDR. This is also the minimum time required for a

POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main

system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control

register (CSC).

TPW

Supply voltage (V^DD

)

V

POR

VPDR or 0.7 V

Page 67 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.6.4 LVD circuit characteristics

(T^A= −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

V^LVD0

Conditions

Power supply rise time

MIN.

3.98

3.90

3.68

3.60

3.07

3.00

2.96

2.90

2.86

2.80

2.76

2.70

2.66

2.60

2.56

2.50

2.45

2.40

2.05

2.00

1.94

1.90

1.84

1.80

1.74

1.70

1.64

1.60

300

TYP.

4.06

3.98

3.75

3.67

3.13

3.06

3.02

2.96

2.92

2.86

2.81

2.75

2.71

2.65

2.61

2.55

2.50

2.45

2.09

2.04

1.98

1.94

1.88

1.84

1.77

1.73

1.67

1.63

MAX.

4.14

4.06

3.82

3.74

3.19

3.12

3.08

3.02

2.97

2.91

2.87

2.81

2.76

2.70

2.66

2.60

2.55

2.50

2.13

2.08

2.02

1.98

1.91

1.87

1.81

1.77

1.70

1.66

Unit

V

Detection

voltage

Supply voltage level

V

μs

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

Power supply rise time

Power supply fall time

VLVD1

VLVD2

VLVD3

VLVD4

VLVD5

VLVD6

VLVD7

VLVD8

VLVD9

VLVD10

VLVD11

VLVD12

VLVD13

Minimum pulse width

Detection delay time

tLW

tLD

300

Page 68 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

LVD Detection Voltage of Interrupt & Reset Mode

(T^A= −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

1.60

1.74

1.70

1.84

1.80

2.86

2.80

1.80

1.94

1.90

2.05

2.00

3.07

3.00

2.40

2.56

2.50

2.66

2.60

3.68

3.60

2.70

2.86

2.80

2.96

2.90

3.98

3.90

TYP.

1.63

1.77

1.73

1.88

1.84

2.92

2.86

1.84

1.98

1.94

2.09

2.04

3.13

3.06

2.45

2.61

2.55

2.71

2.65

3.75

3.67

2.75

2.92

2.86

3.02

2.96

4.06

3.98

MAX.

1.66

1.81

1.77

1.91

1.87

2.97

2.91

1.87

2.02

1.98

2.13

2.08

3.19

3.12

2.50

2.66

2.60

2.76

2.70

3.82

3.74

2.81

2.97

2.91

3.08

3.02

4.14

4.06

Unit

V

Interrupt and reset V^LVDA0

VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage

LVIS1, LVIS0 = 1, 0 Rising release reset voltage

Falling interrupt voltage

mode

VLVDA1

VLVDA2

VLVDA3

LVIS1, LVIS0 = 0, 1 Rising release reset voltage

Falling interrupt voltage

LVIS1, LVIS0 = 0, 0 Rising release reset voltage

Falling interrupt voltage

VLVDB1

VLVDB2

VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage

LVIS1, LVIS0 = 1, 0 Rising release reset voltage

Falling interrupt voltage

VLVDB3

VLVDB4

LVIS1, LVIS0 = 0, 1 Rising release reset voltage

Falling interrupt voltage

LVIS1, LVIS0 = 0, 0 Rising release reset voltage

Falling interrupt voltage

VLVDC0

VLVDC1

VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage

LVIS1, LVIS0 = 1, 0 Rising release reset voltage

Falling interrupt voltage

VLVDC2

VLVDC3

LVIS1, LVIS0 = 0, 1 Rising release reset voltage

Falling interrupt voltage

LVIS1, LVIS0 = 0, 0 Rising release reset voltage

Falling interrupt voltage

VLVDD0

VLVDD1

VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage

LVIS1, LVIS0 = 1, 0 Rising release reset voltage

Falling interrupt voltage

VLVDD2

VLVDD3

LVIS1, LVIS0 = 0, 1 Rising release reset voltage

Falling interrupt voltage

LVIS1, LVIS0 = 0, 0 Rising release reset voltage

Falling interrupt voltage

2.6.5 Supply voltage rise time

(T^A= −40 to +85°C, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

54

Unit

Power supply voltage rising slope

SVDD

V/ms

Caution

Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the

operating voltage range shown in 30.4 AC Characteristics.

Page 69 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.7 LCD Characteristics

2.7.1 Resistance division method

(1) Static display mode

(T^A= −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

LCD drive voltage

Symbol

Conditions

MIN.

2.0

TYP.

MAX.

Unit

V

VL4

VDD

(2) 1/2 bias method, 1/4 bias method

(T^A= −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

LCD drive voltage

Symbol

Conditions

MIN.

2.7

MAX.

Unit

V

VL4

VDD

(3) 1/3 bias method

(T^A= −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

LCD drive voltage

Symbol

Conditions

MIN.

2.5

MAX.

Unit

V

VL4

VDD

Page 70 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.7.2 Internal voltage boosting method

(1) 1/3 bias method

(T^A= −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter Symbol Conditions

LCD output voltage variation range VL1

C1 to C4^{Note 1}

= 0.47 μF

MIN.

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

TYP.

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

2 V^L1

MAX.

Unit

V

VLCD = 04H

VLCD = 05H

VLCD = 06H

VLCD = 07H

VLCD = 08H

VLCD = 09H

VLCD = 0AH

VLCD = 0BH

VLCD = 0CH

VLCD = 0DH

VLCD = 0EH

VLCD = 0FH

VLCD = 10H

VLCD = 11H

VLCD = 12H

VLCD = 13H

1.08

1.13

1.18

1.23

1.28

1.33

1.38

1.43

1.48

1.53

1.58

1.63

1.68

1.73

1.78

1.83

Doubler output voltage

Tripler output voltage

VL2

VL4

C1 to C4^{Note 1}= 0.47 μF

2 VL1

− 0.1

C1 to C4^{Note 1}= 0.47 μF

3 VL1

3 V^L1

3 VL1

V

− 0.15

Reference voltage setup time ^{Note 2}

Voltage boost wait time^{Note 3}

tVWAIT1

tVWAIT2

5

ms

C1 to C4^{Note 1}= 0.47 μF

500

Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between V^L1and GND

C3: A capacitor connected between V^L2and GND

C4: A capacitor connected between V^L4and GND

C1 = C2 = C3 = C4 = 0.47 μF 30%

2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or

when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the

LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).

3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

Page 71 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

(2) 1/4 bias method

(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

C1 to C5^{Note 1}

= 0.47 μF

MIN.

0.90

TYP.

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

2 VL1

3 VL1

4 VL1

MAX.

Unit

V

Note 4

LCD output voltage variation range VL1

VLCD = 04H

VLCD = 05H

VLCD = 06H

VLCD = 07H

VLCD = 08H

VLCD = 09H

VLCD = 0AH

VLCD = 0BH

VLCD = 0CH

VLCD = 0DH

VLCD = 0EH

VLCD = 0FH

VLCD = 10H

VLCD = 11H

VLCD = 12H

VLCD = 13H

1.08

1.13

1.18

1.23

1.28

1.33

1.38

1.43

1.48

1.53

1.58

1.63

1.68

1.73

1.78

0.95

V

1.00

V

1.05

V

1.10

V

1.15

V

1.20

V

1.25

V

1.30

V

1.35

V

1.40

V

1.45

V

1.50

V

1.55

V

1.60

V

1.65

V

1.83

Doubler output voltage

VL2

VL3

VL4

C1 to C5^{Note 1}= 0.47 μF

2 VL1 − 0.08

3 VL1 − 0.12

4 VL1 − 0.16

5

2 VL1

V

Tripler output voltage

3 VL1

4 VL1

V

Note 4

Quadruply output voltage

Reference voltage setup time ^{Note 2}

Voltage boost wait time^{Note 3}

V

tVWAIT1

tVWAIT2

ms

C1 to C5^{Note 1}= 0.47 μF

500

Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between V^L1and GND

C3: A capacitor connected between V^L2and GND

C4: A capacitor connected between V^L3and GND

C5: A capacitor connected between V^L4and GND

C1 = C2 = C3 = C4 = C5 = 0.47 μF 30%

2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when

the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0

register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).

3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

4. V^L4must be 5.5 V or lower.

2.7.3 Capacitor split method

1/3 bias method

(T^A= −40 to +85°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

VL4

Conditions

C1 to C4 = 0.47 μ F^{Note 2}

MIN.

TYP.

VDD

MAX.

Unit

V

VL4 voltage

VL2 voltage

VL2

2/3 VL4

2/3 V^L4

2/3 VL4

+ 0.1

V

− 0.1

VL1 voltage

VL1

C1 to C4 = 0.47 μ F^{Note 2}

1/3 VL4

1/3 V^L4

1/3 VL4

+ 0.1

V

− 0.1

Capacitor split wait time^{Note 1}

tVWAIT

100

ms

Page 72 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).

2. This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between V^L1and GND

C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between V^L4and GND

C1 = C2 = C3 = C4 = 0.47 μF 30%

Page 73 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

<R>

2.8 RAM Data Retention Characteristics

(T^A= −40 to +85°C, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

VDDDR

1.46^Note

<R> Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage

reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.

Operation mode

STOP mode

<R>

RAM Data retention mode

VDD

VDDDR

STOP instruction execution

Standby release signal

(interrupt request)

2.9 Flash Memory Programming Characteristics

(T^A= −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

fCLK

Conditions

1.8 V ≤ VDD ≤ 5.5 V

MIN.

1

TYP.

MAX.

24

Unit

MHz

System clock frequency

Number of code flash rewrites

C^erwr

Retained for 20 years

1,000

Times

<R>

Note 1, 2, 3

T^A= 85°C

Number of data flash rewrites

Note 1, 2, 3

Retained for 1 year

1,000,000

TA = 25°C

Retained for 5 years

100,000

10,000

T^A= 85°C

Retained for 20 years

T^A= 85°C

Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.

The retaining years are until next rewrite after the rewrite.

2. When using flash memory programmer and Renesas Electronics self programming library

3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.

Remark When updating data multiple times, use the flash memory as one for updating data.

2.10 Dedicated Flash Memory Programmer Communication (UART)

(T^A= −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

bps

Transfer rate

During flash memory programming

115,200

1,000,000

Page 74 of 131

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2. ELECTRICAL SPECIFICATIONS (A, G: T^A= -40 to +85°C)

2.11 Timing Specifications for Switching Flash Memory Programming Modes

(T^A= −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

t^SUINIT

Conditions

MIN.

TYP.

MAX.

100

Unit

ms

Time to complete the

POR and LVD reset must be released before

the external reset is released.

communication for the initial setting

after the external reset is released

Time to release the external reset t^SU

after the TOOL0 pin is set to the

low level

POR and LVD reset must be released before

the external reset is released.

10

1

μ s

Time to hold the TOOL0 pin at the t^HD

low level after the external reset is

released

POR and LVD reset must be released before

the external reset is released.

ms

(excluding the processing time of

the firmware to control the flash

memory)

<1>

<4>

<2>

<3>

RESET

TOOL0

t

HD+

soft processing

time

1-byte data for mode setting

t

SU

tSUINIT

<1> The low level is input to the TOOL0 pin.

<2> The external reset is released (POR and LVD reset must be released before the external

reset is released.).

<3> The TOOL0 pin is set to the high level.

<4> Setting of the flash memory programming mode by UART reception and complete the baud

rate setting.

Remark t^SUINIT: Communication for the initial setting must be completed within 100 ms after a reset is released during this

period.

t

SU

:

Time to release the external reset after the TOOL0 pin is set to the low level

Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing

time of the firmware to control the flash memory)

t^HD:

Page 75 of 131

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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

3. ELECTRICAL SPECIFICATIONS (G: T = -40 to +105°C)

A

This chapter describes the electrical specifications for the products "G: Industrial applications (T^A= -40 to

+105°C)".

Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development

and evaluation. Do not use the on-chip debug function in products designated for mass

production, because the guaranteed number of rewritable times of the flash memory may be

exceeded when this function is used, and product reliability therefore cannot be guaranteed.

Renesas Electronics is not liable for problems occurring when the on-chip debug function is

used.

2. With products not provided with an EV^DDor EVSS pin, replace EVDD with VDD, or replace EVSS with

V^SS.

3. For derating with TA = +85 to +105°C, contact our Sales Division or the vender's sales division.

Derating means the specified reduction in an operating parameter to improve reliability.

Page 76 of 131

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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

There are following differences between the products "G: Industrial applications (TA = -40 to +105°C)" and the products “A:

Consumer applications, and G: Industrial applications (TA = -40 to +85°C)”.

Parameter

Application

A: Consumer applications,

G: Industrial applications

(with TA = -40 to +85°C)

G: Industrial applications

Operating ambient temperature

Operating mode

TA = -40 to +85°C

TA = -40 to +105°C

HS (high-speed main) mode:

2.7 V ≤ V^DD≤ 5.5 V@1 MHz to 32 MHz

2.4 V ≤ V^DD≤ 5.5 V@1 MHz to 16 MHz

LS (low-speed main) mode:

1.8 V ≤ V^DD≤ 5.5 V@1 MHz to 8 MHz

LV (low-voltage main) mode:

1.6 V ≤ V^DD≤ 5.5 V@1 MHz to 4 MHz

1.8 V ≤ VDD ≤ 5.5 V:

HS (high-speed main) mode only:

Operating voltage range

2.7 V ≤ V^DD≤ 5.5 V@1 MHz to 32 MHz

2.4 V ≤ V^DD≤ 5.5 V@1 MHz to 16 MHz

High-speed on-chip oscillator clock

accuracy

2.4 V ≤ V^DD≤ 5.5 V:

1.0%@ T^A= -20 to +85°C

1.5%@ T^A= -40 to -20°C

1.6 V ≤ V^DD< 1.8 V:

2.0%@ T^A= +85 to +105°C

1.0%@ T^A= -20 to +85°C

1.5%@ T^A= -40 to -20°C

5.0%@ T^A= -20 to +85°C

5.5%@ T^A= -40 to -20°C

UART

Serial array unit

UART

CSI00: f^CLK/2 (supporting 16 Mbps), fCLK/4

CSI00: f^CLK/4

CSI01

Simplified I²C communication

Normal mode

Simplified I²C communication

Normal mode

Fast mode

IICA

Fast mode

Fast mode plus

Voltage detector

Rise detection voltage: 1.67 V to 4.06 V

(14 levels)

Rise detection voltage: 2.61 V to 4.06 V

(8 levels)

Fall detection voltage: 1.63 V to 3.98 V

(14 levels)

Fall detection voltage: 2.55 V to 3.98 V

(8 levels)

Remark The electrical characteristics of the products G: Industrial applications (T^A= -40 to +105°C) are different from

those of the products “A: Consumer applications, and G: Industrial applications (only with T^A= -40 to +85°C)”.

For details, refer to 3.1 to 3.10.

Page 77 of 131

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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

3.1 Absolute Maximum Ratings

Absolute Maximum Ratings (T^A= 25°C)

(1/3)

Parameter

Supply voltage

Symbols

Conditions

Ratings

Unit

V

VDD

VDD = EVDD

−0.5 to +6.5

−0.5 to +0.3

EVDD

EVSS

VIREGC

V

REGC pin input voltage

Input voltage

REGC

−0.3 to +2.8

V

and −0.3 to VDD + 0.3 ^{Note 1}

VI1

VI2

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P70 to P74, P120, P125 to P127, P140

to P147

−0.3 to EV^DD+ 0.3

and −0.3 to V^DD+ 0.3^{Note 2}

V

P60, P61 (N-ch open-drain)

−0.3 to EVDD + 0.3

and −0.3 to V^DD+ 0.3^{Note 2}

−0.3 to V^DD+ 0.3^{Note 2}

VI3

P20, P21, P121 to P124, P137, EXCLK, EXCLKS,

RESET

V

Output voltage

VO1

P10 to P17, P30 to P32, P40 to P43, P50 to P54,

P60, P61, P70 to P74, P120, P125 to P127, P130,

P140 to P147

−0.3 to EV^DD+ 0.3

and −0.3 to V^DD+ 0.3 ^{Note 2}

VO2

VAI1

P20, P21

−0.3 to VDD + 0.3 ^{Note 2}

V

Analog input voltage

ANI16 to ANI23

−0.3 to EV^DD+ 0.3

and −0.3 to AVREF(+) + 0.3^{Notes 2, 3}

VAI2

ANI0, ANI1

−0.3 to V^DD+ 0.3

V

and −0.3 to AVREF(+) + 0.3^{Notes 2, 3}

Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute

maximum rating of the REGC pin. Do not use this pin with voltage applied to it.

2. Must be 6.5 V or lower.

3. Do not exceed AV^REF(+) + 0.3 V in case of A/D conversion target pin.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge

of suffering physical damage, and therefore the product must be used under conditions that ensure that

the absolute maximum ratings are not exceeded.

Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

2. AV^REF(+) : + side reference voltage of the A/D converter.

3.

VSS : Reference voltage

Page 78 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

Absolute Maximum Ratings (TA = 25°C)

(2/3)

Parameter

LCD voltage

Symbols

Conditions

Ratings

Unit

V

VL1

VL1 voltage^{Note 1}

−0.3 to +2.8

and −0.3 to V^L4+ 0.3

VL2

VL2 voltage^{Note 1}

VL3 voltage^{Note 1}

VL4 voltage^{Note 1}

−0.3 to VL4 + 0.3 ^{Note 2}

−0.3 to +6.5

−0.3 to VL4 + 0.3 ^{Note 2}

−0.3 to V^DD+ 0.3 ^{Note 2}

V

VL3

VL4

VLCAP

VLOUT

CAPL, CAPH voltage^{Note 1}

COM0 to COM7, External resistance division

SEG0 to

method

−0.3 to VDD + 0.3 ^{Note 2}

−0.3 to VL4 + 0.3 ^{Note 2}

SEG38,

Capacitor split method

Internal voltage boosting method

output voltage

Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3,

and V^L4pins; it does not mean that applying voltage to these pins is recommended. When using

the internal voltage boosting method or capacitance split method, connect these pins to V^SSvia a

capacitor (0.47 μ F 30%) and connect a capacitor (0.47 μ F 30%) between the CAPL and CAPH

pins.

2. Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge

of suffering physical damage, and therefore the product must be used under conditions that ensure that

the absolute maximum ratings are not exceeded.

Remark

VSS : Reference voltage

Page 79 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

Absolute Maximum Ratings (TA = 25°C)

(3/3)

Parameter

Symbols

Conditions

Ratings

Unit

mA

Output current, high

IOH1

Per pin

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P70 to P74, P120,

−40

P125 to P127, P130, P140 to P147

Total of all pins

P10 to P14, P40 to P43, P120,

P130, P140 to P147

−70

mA

−170 mA

P15 to P17, P30 to P32,

P50 to P54, P70 to P74,

P125 to P127

−100

IOH2

IOL1

Per pin

P20, P21

−0.5

−1

mA

Total of all pins

Per pin

Output current, low

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P60, P61, P70 to P74,

P120, P125 to P127, P130,

P140 to P147

40

Total of all pins

170 mA

P10 to P14, P40 to P43, P120,

P130, P140 to P147

70

mA

P15 to P17, P30 to P32, P50 to P54,

P60, P61, P70 to P74, P125 to P127

100

IOL2

T^A

Per pin

P20, P21

1

mA

°C

Total of all pins

2

Operating ambient

temperature

In normal operation mode

−40 to +105

In flash memory programming mode

Storage temperature

Tstg

−65 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge

of suffering physical damage, and therefore the product must be used under conditions that ensure that

the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.

Page 80 of 131

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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

3.2 Oscillator Characteristics

3.2.1 X1, XT1 oscillator characteristics

(T^A= −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Resonator

Conditions

2.7 V ≤ V^DD≤ 5.5 V

2.4 V ≤ VDD < 2.7 V

MIN.

1.0

32

TYP.

MAX.

20.0

16.0

35

Unit

MHz

kHz

X1 clock oscillation

frequency (f^X)^Note

Ceramic resonator/

crystal resonator

XT1 clock oscillation

frequency (f^XT)^Note

Crystal resonator

32.768

Note Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution

time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator

characteristics.

Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1

clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)

by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation

stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time

with the resonator to be used.

3.2.2 On-chip oscillator characteristics

(T^A= −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Oscillators

Parameters

f^IH

Conditions

MIN.

1

TYP.

MAX.

24

Unit

High-speed on-chip oscillator

clock frequency ^{Notes 1, 2}

MHz

High-speed on-chip oscillator

clock frequency accuracy

−20 to +85°C

−40 to −20°C

+85 to +105°C

2.4 V ≤ V^DD≤ 5.5 V

2.4 V ≤ VDD ≤ 5.5 V

−1

+1

%

−1.5

−2.0

+1.5

+2.0

%

Low-speed on-chip oscillator

clock frequency

f^IL

15

kHz

Low-speed on-chip oscillator

clock frequency accuracy

−15

+15

%

Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of

HOCODIV register.

2. This indicates the oscillator characteristics only. Refer to 3.4 AC Characteristics for instruction execution

time.

Page 81 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

3.3 DC Characteristics

3.3.1 Pin characteristics

(T^A= −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/5)

Items

Symbol

I^OH1

Conditions

MIN.

TYP.

MAX.

Unit

Output current,

high^{Note 1}

Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,

P70 to P74, P120, P125 to P127, P130, P140 to P147

-3.0 ^{Note 2}mA

Total of P10 to P14, P40 to P43, P120,

P130, P140 to P147

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD < 2.7 V

4.0 V ≤ EV^DD≤ 5.5 V

2.7 V ≤ EVDD < 4.0 V

2.4 V ≤ EVDD < 2.7 V

-30.0

−8.0

mA

(When duty = 70% ^{Note 3}

)

−4.0

Total of P15 to P17, P30 to P32,

-30.0

−15.0

−8.0

P50 to P54, P70 to P74, P125 to P127

(When duty = 70% ^{Note 3}

)

Total of all pins

-60.0

(When duty = 70%^{Note 3}

P20, P21

)

IOH2

Per pin

Total of all pins

−0.1

−0.2

mA

2.4 V ≤ VDD ≤ 5.5 V

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and

EVDD pins to an output pin.

2. Do not exceed the total current value.

3. Specification under conditions where the duty factor ≤ 70%.

The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the

following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (I^OH× 0.7)/(n × 0.01)

<Example> Where n = 80% and I^OH= −30.0 mA

Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.25 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 82 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(2/5)

Items

Symbol

I^OL1

Conditions

MIN.

TYP.

MAX.

Unit

Output current,

low^{Note 1}

Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,

P70 to P74, P120, P125 to P127, P130, P140 to P147

8.5 ^{Note 2}

mA

Per pin for P60, P61

15.0 ^{Note 2}

40.0

mA

Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EV^DD≤ 5.5 V

P130, P140 to P147

(When duty = 70% ^{Note 3}

2.7 V ≤ EVDD < 4.0 V

15.0

)

2.4 V ≤ EVDD < 2.7 V

9.0

Total of P15 to P17, P30 to P32, P50 4.0 V ≤ EV^DD≤ 5.5 V

to P54, P60, P61, P70 to P74,

40.0

2.7 V ≤ EVDD < 4.0 V

35.0

P125 to P127

(When duty = 70% ^{Note 3}

2,4 V ≤ EVDD < 2.7 V

20.0

)

Total of all pins

80.0

mA

(When duty = 70% ^{Note 3}

P20, P21 Per pin

Total of all pins

)

IOL2

0.4

0.8

mA

2.4 V ≤ VDD ≤ 5.5 V

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the V^DDand

EVDD pins to an output pin.

2. Do not exceed the total current value.

3. Specification under conditions where the duty factor ≤ 70%.

The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the

following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (I^OL× 0.7)/(n × 0.01)

<Example> Where n = 80% and I^OL= 40.0 mA

Total output current of pins = (40.0 × 0.7)/(80 × 0.01) ≅ 35.0 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 83 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(3/5)

Items

Symbol

V^IH1

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage,

high

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P70 to P74, P120,

P125 to P127, P140 to P147

Normal input buffer

0.8EV^DD

EVDD

V

VIH2

P10, P11, P15, P16

TTL input buffer

2.2

2.0

EVDD

V

4.0 V

TTL input buffer

3.3 V 4.0 V

TTL input buffer

2.4 V 3.3 V

≤ EVDD ≤ 5.5 V

≤

EVDD <

1.50

≤

EVDD <

VIH3

VIH4

VIH5

P20, P21

P60, P61

0.7VDD

0.7EVDD

0.8VDD

0

VDD

EVDD

V

P121 to P124, P137, EXCLK, EXCLKS, RESET

VDD

Input voltage, low VIL1

P10 to P17, P30 to P32, P40 to P43,

P50 to P54, P70 to P74, P120,

P125 to P127, P140 to P147

Normal input buffer

0.2EV^DD

VIL2

P10, P11, P15, P16

TTL input buffer

0

0.8

0.5

V

4.0 V

TTL input buffer

3.3 V 4.0 V

TTL input buffer

2.4 V 3.3 V

≤ EVDD ≤ 5.5 V

≤

EVDD <

0.32

≤

EVDD <

VIL3

VIL4

VIL5

P20, P21

P60, P61

0

0.3VDD

0.3EVDD

0.2VDD

V

P121 to P124, P137, EXCLK, EXCLKS, RESET

Caution The maximum value of V^IHof pins P10, P12, P15, and P17 is EVDD, even in the N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 84 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(4/5)

Items

Symbol

V^OH1

Conditions

MIN.

TYP.

MAX.

Unit

Output voltage,

high

P10 to P17, P30 to P32, P40 to P43, 4.0 V

≤

−

EVDD

≤

5.5 V,

EVDD −

0.7

V

P50 to P54, P70 to P74, P120,

I

OH1

=

3.0 mA

P125 to P127, P130, P140 to P147

2.7 V

≤

−

EVDD

≤

EVDD −

0.6

I

OH1

=

2.0 mA

2.4 V

≤

−

EVDD

≤

EVDD −

0.5

I

OH1

=

1.5 mA

VOH2

P20, P21

2.4 V ≤ V^DD≤ 5.5 V,

I^OH2= −100 μ A

V^DD− 0.5

Output voltage,

low

V^OL1

P10 to P17, P30 to P32, P40 to P43, 4.0 V

≤

EVDD

≤

5.5 V,

0.7

0.6

0.4

2.0

0.4

P50 to P54, P70 to P74, P120,

I^OL1= 8.5 mA

P125 to P127, P130, P140 to P147

2.7 V

≤

EVDD

I

OL1 = 3.0 mA

2.7 V

≤

I

OL1 = 1.5 mA

2.4 V

OL1 = 0.6 mA

≤

EVDD

I

VOL2

VOL3

P20, P21

P60, P61

2.4 V ≤ V^DD≤ 5.5 V,

I^OL2= 400 μ A

4.0 V

≤

EVDD

≤

5.5 V,

I

OL3 = 15.0 mA

4.0 V

≤

EVDD

I

OL3 = 5.0 mA

2.7 V

≤

EVDD

I

OL3 = 3.0 mA

2.4 V

≤

EVDD

I

OL3 = 2.0 mA

Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 85 of 131

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RL78/L12

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(5/5)

Items

Symbol

I^LIH1

Conditions

MIN.

TYP.

MAX.

1

Unit

Input leakage

current, high

P10 to P17, P30 to P32,

V^I= EVDD

μA

P40 to P43, P50 to P54, P60,

P61, P70 to P74, P120,

P125 to P127, P140 to P147

ILIH2

ILIH3

P20, P21, P137, RESET

VI = VDD

V^I= VDD

1

μA

P121 to P124

In input port or

external clock

input

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

In resonator

connection

10

μA

Input leakage

current, low

I^LIL1

P10 to P17, P30 to P32,

P40 to P43, P50 to P54, P60,

P61, P70 to P74, P120,

V^I= EVSS

−1

P125 to P127, P140 to P147

ILIL2

ILIL3

P20, P21, P137, RESET

VI = VSS

V^I= VSS

−1

μA

P121 to P124

In input port or

external clock

input

(X1, X2, XT1, XT2, EXCLK,

EXCLKS)

In resonator

connection

−10

μA

On-chip pll-up

resistance

R^U1

VI = EVSS

SEGxx port

2.4 V

≤

EVDD = VDD

≤

5.5 V

10

20

100

kΩ

RU2

Ports other than above

(Except for P60, P61, and

P130)

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

Page 86 of 131

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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

3.3.2 Supply current characteristics

(T^A= −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

(1/3)

Parameter Symbol

Conditions

f^IH= 24 MHz ^{Note 3}

MIN.

TYP.

1.5

3.3

2.5

2.8

3.0

2.8

3.0

1.8

3.5

3.6

MAX.

Unit

mA

μA

Supply

I^DD1

Operating HS (high-

Basic

operation

VDD = 5.0 V

current

Note 1

mode

speed main)

VDD = 3.0 V

mode ^{Note 5}

Normal

operation

VDD = 5.0 V

5.3

3.9

4.7

4.8

4.7

4.8

2.8

4.9

5.0

VDD = 3.0 V

fIH = 16 MHz ^{Note 3}

Normal

operation

VDD = 5.0 V

VDD = 3.0 V

HS (high-

f^MX= 20 MHz^{Note 2}

V^DD= 5.0 V

fMX = 20 MHz^{Note 2}

,

Normal

operation

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

Square wave input

Resonator connection

speed main)

mode ^{Note 5}

Normal

operation

V^DD= 3.0 V

fMX = 10 MHz^{Note 2}

V^DD= 5.0 V

fMX = 10 MHz^{Note 2}

Normal

operation

Normal

operation

V^DD= 3.0 V

Subsystem

clock

operation

f^SUB= 32.768 kHz

Normal

operation

Note 4

μA

TA = −40°C

fSUB = 32.768 kHz

Normal

operation

Square wave input

3.6

3.7

4.9

5.0

μA

Note 4

Resonator connection

T^A= +25°C

fSUB = 32.768 kHz

Note 4

Normal

operation

Square wave input

3.7

3.8

5.5

5.6

μA

Resonator connection

TA = +50°C

fSUB = 32.768 kHz

Note 4

Normal

operation

Square wave input

3.8

3.9

6.3

6.4

μA

Resonator connection

TA = +70°C

fSUB = 32.768 kHz

Note 4

Normal

operation

Square wave input

4.1

4.2

7.7

7.8

μA

Resonator connection

TA = +85°C

fSUB = 32.768 kHz

Note 4

Normal

operation

Square wave input

6.4

6.5

19.7

19.8

μA

Resonator connection

TA = +105°C

(Notes and Remarks are listed on the next page.)

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