R5F21266SDFP#U0_技术文档

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1^st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1^st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

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All information included in this document is current as of the date this document is issued. Such information, however, is

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R8C/26 Group, R8C/27 Group

SINGLE-CHIP 16-BIT CMOS MCU

REJ03B0168-0210

Rev.2.10

Sep 26, 2008

1. Overview

These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and

are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction

efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.

Furthermore, the R8C/27 Group has on-chip data flash (1 KB × 2 blocks).

The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash.

Their peripheral functions are the same.

1.1

Applications

Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.

Rev.2.10 Sep 26, 2008 Page 1 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

1.2

Performance Overview

Table 1.1 outlines the Functions and Specifications for R8C/26 Group and Table 1.2 outlines the Functions and

Specifications for R8C/27 Group.

Table 1.1

Functions and Specifications for R8C/26 Group

Item

Specification

CPU

Number of

fundamental

89 instructions

instructions

Minimum instruction

50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)

62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)

100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)

Single-chip

execution time

Operating mode

Address space

Memory capacity

Ports

LED drive ports

Timers

1 Mbyte

Refer to Table 1.3 Product Information for R8C/26 Group

I/O ports: 25 pins, Input port: 3 pins

I/O ports: 8 pins (N, D version)

Peripheral

Functions

Timer RA: 8 bits × 1 channel

Timer RB: 8 bits × 1 channel

(Each timer equipped with 8-bit prescaler)

Timer RC: 16 bits × 1 channel

(Input capture and output compare circuits)

Timer RE: With real-time clock and compare match function

(For J, K version, compare match function only.)

2 channels (UART0, UART1)

Serial interfaces

Clock synchronous serial I/O, UART

Clock synchronous

serial interface

1 channel

I C bus Interface

2

(1)

Clock synchronous serial I/O with chip select

Hardware LIN: 1 channel (timer RA, UART0)

10-bit A/D converter: 1 circuit, 12 channels

15 bits × 1 channel (with prescaler)

LIN module

A/D converter

Watchdog timer

Start-on-reset selectable

Interrupts

Internal: 15 sources, External: 4 sources,

Software: 4 sources, Priority levels: 7 levels

3 circuits

• XIN clock generation circuit (with on-chip feedback resistor)

• On-chip oscillator (high speed, low speed)

High-speed on-chip oscillator has a frequency adjustment function

• XCIN clock generation circuit (32 kHz) (N, D version)

• Real-time clock (timer RE) (N, D version)

XIN clock oscillation stop detection function

Clock generation

circuits

Oscillation-stopped

detector

Voltage detection

circuit

On-chip

Power-on reset circuit On-chip

Electrical

Characteristics

Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)

VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)

VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)

VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)

Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

(N, D version)

Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)

Typ. 0.7 µA (VCC = 3.0 V, stop mode)

VCC = 2.7 to 5.5 V

Flash Memory

Programming and

erasure voltage

Programming and

erasure endurance

100 times

Operating Ambient Temperature

-20 to 85°C (N version)

-40 to 85°C (D, J version)⁽²⁾, -40 to 125°C (K version)⁽²⁾

Package

NOTES:

32-pin molded-plastic LQFP

1. I²C bus is a trademark of Koninklijke Philips Electronics N. V.

2. Specify the D, K version if D, K version functions are to be used.

Rev.2.10 Sep 26, 2008 Page 2 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

Table 1.2

Functions and Specifications for R8C/27 Group

Item

Specification

CPU

Number of fundamental 89 instructions

instructions

Minimum instruction

execution time

50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)

62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)

100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)

Single-chip

Operating mode

Address space

Memory capacity

Ports

LED drive ports

Timers

1 Mbyte

Refer to Table 1.4 Product Information of R8C/27 Group

I/O ports: 25 pins, Input port: 3 pins

I/O ports: 8 pins (N, D version)

Peripheral

Functions

Timer RA: 8 bits × 1 channel

Timer RB: 8 bits × 1 channel

(Each timer equipped with 8-bit prescaler)

Timer RC: 16 bits × 1 channel

(Input capture and output compare circuits)

Timer RE: With real-time clock and compare match function

(For J, K version, compare match function only.)

2 channels (UART0, UART1)

Serial interfaces

Clock synchronous serial I/O, UART

Clock synchronous

serial interface

1 channel

2

(1)

I C bus Interface

Clock synchronous serial I/O with chip select

Hardware LIN: 1 channel (timer RA, UART0)

10-bit A/D converter: 1 circuit, 12 channels

15 bits × 1 channel (with prescaler)

LIN module

A/D converter

Watchdog timer

Start-on-reset selectable

Interrupts

Internal: 15 sources, External: 4 sources,

Software: 4 sources, Priority levels: 7 levels

3 circuits

• XIN clock generation circuit (with on-chip feedback resistor)

• On-chip oscillator (high speed, low speed)

High-speed on-chip oscillator has a frequency adjustment function

• XCIN clock generation circuit (32 kHz) (N, D version)

• Real-time clock (timer RE) (N, D version)

XIN clock oscillation stop detection function

Clock generation

circuits

Oscillation-stopped

detector

Voltage detection circuit On-chip

Power-on reset circuit

Supply voltage

On-chip

Electrical

Characteristics

VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)

VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)

VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)

VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)

Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)

Typ. 0.7 µA (VCC = 3.0 V, stop mode)

VCC = 2.7 to 5.5 V

Current consumption

(N, D version)

Flash Memory

Programming and

erasure voltage

Programming and

erasure endurance

10,000 times (data flash)

1,000 times (program ROM)

Operating Ambient Temperature

-20 to 85°C (N version)

-40 to 85°C (D, J version)⁽²⁾, -40 to 125°C (K version)⁽²⁾

Package

NOTES:

32-pin molded-plastic LQFP

1. I²C bus is a trademark of Koninklijke Philips Electronics N. V.

2. Specify the D, K version if D, K version functions are to be used.

Rev.2.10 Sep 26, 2008 Page 3 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

1.3

Block Diagram

Figure 1.1 shows a Block Diagram.

8

1

3

6

2

Port P0

Port P1

I/O ports

Port P3

Port P4

Port P5

Peripheral functions

System clock

generation circuit

A/D converter

(10 bits × 12 channels)

Timers

XIN-XOUT

High-speed on-chip oscillator

Low-Speed on-chip oscillator

XCIN-XCOUT⁽³⁾

Timer RA (8 bits)

Timer RB (8 bits)

Timer RC

(16 bits × 1 channel)

Timer RE (8 bits)

UART or

clock synchronous serial I/O

(8 bits × 2 channels)

I²C bus interface or clock synchronous

serial I/O with chip select

(8 bits × 1 channel)

LIN module

(1 channel)

Watchdog timer

(15 bits)

Memory

R8C CPU core

ROM⁽¹⁾

R0H

R1H

R0L

R1L

SB

USP

ISP

INTB

PC

FLG

R2

R3

RAM⁽²⁾

A0

A1

FB

Multiplier

NOTES:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

3. XCIN, XCOUT can be used only for N or D version.

Figure 1.1

Block Diagram

Rev.2.10 Sep 26, 2008 Page 4 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

1.4

Product Information

Table 1.3 lists the Product Information for R8C/26 Group and Table 1.4 lists the Product Information for R8C/27

Group.

Table 1.3

Product Information for R8C/26 Group

Current of Sep. 2008

ROM

Capacity

RAM

Capacity

512 bytes

1 Kbyte

Part No.

Package Type

Remarks

R5F21262SNFP

8 Kbytes

PLQP0032GB-A N version

PLQP0032GB-A

R5F21264SNFP

16 Kbytes

24 Kbytes

32 Kbytes

8 Kbytes

R5F21265SNFP

1.5 Kbytes PLQP0032GB-A

R5F21266SNFP

R5F21262SDFP

512 bytes

1 Kbyte

PLQP0032GB-A D version

PLQP0032GB-A

R5F21264SDFP

16 Kbytes

24 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

8 Kbytes

R5F21265SDFP

1.5 Kbytes PLQP0032GB-A

R5F21266SDFP

R5F21264JFP

1 Kbyte

PLQP0032GB-A J version

R5F21266JFP

1.5 Kbytes PLQP0032GB-A

R5F21264KFP

1 Kbyte

PLQP0032GB-A K version

R5F21266KFP

1.5 Kbytes PLQP0032GB-A

R5F21262SNXXXFP

R5F21264SNXXXFP

R5F21265SNXXXFP

R5F21266SNXXXFP

R5F21262SDXXXFP

R5F21264SDXXXFP

R5F21265SDXXXFP

R5F21266SDXXXFP

R5F21264JXXXFP

R5F21266JXXXFP

R5F21264KXXXFP

R5F21266KXXXFP

512 bytes

1 Kbyte

PLQP0032GB-A N version

PLQP0032GB-A

Factory

programming

16 Kbytes

24 Kbytes

32 Kbytes

8 Kbytes

(1)

product

1.5 Kbytes PLQP0032GB-A

512 bytes

1 Kbyte

PLQP0032GB-A D version

PLQP0032GB-A

16 Kbytes

24 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

1.5 Kbytes PLQP0032GB-A

1 Kbyte

PLQP0032GB-A J version

1.5 Kbytes PLQP0032GB-A

1 Kbyte

PLQP0032GB-A K version

1.5 Kbytes PLQP0032GB-A

NOTE:

1. The user ROM is programmed before shipment.

Rev.2.10 Sep 26, 2008 Page 5 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

Part No. R 5 F 21 26 6 S N XXX FP

Package type:

FP: PLQP0032GB-A

ROM number

Classification

N: Operating ambient temperature -20 to 85°C (N version)

D: Operating ambient temperature -40 to 85°C (D version)

J: Operating ambient temperature -40 to 85°C (J version)

K: Operating ambient temperature -40 to 125°C (K version)

S: Low-voltage version (other no symbols)

ROM capacity

2: 8 KB

4: 16 KB

5: 24 KB

6: 32 KB

R8C/26 Group

R8C/2x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.2

Part Number, Memory Size, and Package of R8C/26 Group

Rev.2.10 Sep 26, 2008 Page 6 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

Table 1.4

Product Information for R8C/27 Group

Current of Sep. 2008

ROM Capacity

Program

ROM

RAM

Capacity

Part No.

Package Type

Remarks

Data flash

R5F21272SNFP

R5F21274SNFP

R5F21275SNFP

R5F21276SNFP

R5F21272SDFP

R5F21274SDFP

R5F21275SDFP

R5F21276SDFP

R5F21274JFP

8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version

16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A

24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version

16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A

24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A J version

R5F21276JFP

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

R5F21274KFP

R5F21276KFP

R5F21272SNXXXFP

16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A K version

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version Factory

programming

R5F21274SNXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A

(1)

product

R5F21275SNXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

R5F21276SNXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

R5F21272SDXXXFP

8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version

PLQP0032GB-A

R5F21274SDXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte

R5F21275SDXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

R5F21276SDXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

R5F21274JXXXFP

R5F21276JXXXFP

R5F21274KXXXFP

R5F21276KXXXFP

NOTE:

16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A J version

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

16 Kbytes 1 Kbyte × 2 1 Kbyte

PLQP0032GB-A K version

32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A

1. The user ROM is programmed before shipment.

Rev.2.10 Sep 26, 2008 Page 7 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

Part No. R 5 F 21 27 6 S N XXX FP

Package type:

FP: PLQP0032GB-A

ROM number

Classification

N: Operating ambient temperature -20 to 85°C (N version)

D: Operating ambient temperature -40 to 85°C (D version)

J: Operating ambient temperature -40 to 85°C (J version)

K: Operating ambient temperature -40 to 125°C (K version)

S: Low-voltage version (other no symbols)

ROM capacity

2: 8 KB

4: 16 KB

5: 24 KB

6: 32 KB

R8C/27 Group

R8C/2x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.3

Part Number, Memory Size, and Package of R8C/27 Group

Rev.2.10 Sep 26, 2008 Page 8 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

1.5

Pin Assignments

Figure 1.4 shows Pin Assignments (Top View).

24 23 22 21 20 19 18 17

P1_5/RXD0/(TRAIO)/(INT1)⁽²⁾

P1_6/CLK0/(SSI)⁽²⁾

P5_3/TRCIOC

25

26

27

28

29

16

15

14

13

12

11

10

9

P0_7/AN0

P0_6/AN1

P0_5/AN2/CLK1

P0_4/AN3/TREO

P0_3/AN4

R8C/26 Group

R8C/27 Group

P5_4/TRCIOD

P3_1/TRBO

P3_6/(TXD1)/(RXD1)/(INT1)⁽²⁾

P1_7/TRAIO/INT1

P4_5/INT0/(RXD1)⁽²⁾

30

31

32

P0_2/AN5

PLQP0032GB-A

(32P6U-A)

P0_1/AN6

P0_0/AN7/(TXD1)⁽²⁾

(top view)

1

2

3

4

5

6

7

8

NOTES:

1. P4_7 is an input-only port.

2. Can be assigned to the pin in parentheses by a program.

3. XCIN, XCOUT can be used only for N or D version.

4. Confirm the pin 1 position on the package by referring to the package dimensions.

Figure 1.4

Pin Assignments (Top View)

Rev.2.10 Sep 26, 2008 Page 9 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

1.6

Pin Functions

Table 1.5 lists Pin Functions.

Table 1.5

Type

Power supply input VCC, VSS

Pin Functions

Symbol

I/O Type

I

Description

Apply 2.2 to 5.5 V (J, K version are 2.7 to 5.5 V) to the VCC

pin. Apply 0 V to the VSS pin.

Analog power

supply input

AVCC, AVSS

I

Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input

MODE

I

Input “L” on this pin resets the MCU.

Connect this pin to VCC via a resistor.

RESET

MODE

XIN

XIN clock input

These pins are provided for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between the

XIN and XOUT pins. To use an external clock, input it to the

XIN pin and leave the XOUT pin open.

XIN clock output

XOUT

XCIN

O

XCIN clock input

(N, D version)

I

These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins. To use an external clock, input it to the XCIN pin and

leave the XCOUT pin open.

XCIN clock output XCOUT

(N, D version)

O

INT interrupt input INT0, INT1, INT3

I

INT interrupt input pins

Key input interrupt input pins

Timer RA output pin

Key input interrupt

Timer RA

KI0 to KI3

TRAO

O

I/O

O

I

TRAIO

Timer RA I/O pin

Timer RB

Timer RC

TRBO

Timer RB output pin

TRCCLK

TRCTRG

External clock input pin

External trigger input pin

I

TRCIOA, TRCIOB,

TRCIOC, TRCIOD

I/O

Sharing output-compare output / input-capture input / PWM /

PWM2 output pins

Timer RE

TREO

O

I/O

I

Timer RE output pin

Clock I/O pin

Serial interface

CLK0, CLK1

RXD0, RXD1

TXD0, TXD1

SCL

Receive data input pin

Transmit data output pin

Clock I/O pin

O

I²C bus interface

I/O

I

SDA

Data I/O pin

Clock synchronous SSI

serial I/O with chip

select

SSCK

Data I/O pin

Chip-select signal I/O pin

Clock I/O pin

SCS

SSO

Data I/O pin

Reference voltage VREF

input

Reference voltage input pin to A/D converter

A/D converter

I/O port

AN0 to AN11

I

Analog input pins to A/D converter

P0_0 to P0_7,

P1_0 to P1_7,

P3_1, P3_3 to

P3_7,

I/O

CMOS I/O ports. Each port has an I/O select direction register,

allowing each pin in the port to be directed for input or output

individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

P4_5,

P5_3, P5_4

P1_0 to P1_7 also function as LED drive ports (N, D version).

Input port

P4_2, P4_6, P4_7

I

Input-only ports

I: Input

O: Output

I/O: Input and output

Rev.2.10 Sep 26, 2008 Page 10 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

1.Overview

Table 1.6

Pin Name Information by Pin Number

I/O Pin Functions for of Peripheral Modules

Clock

Number

I²C bus

Control Pin

Port

Serial

Interface

Synchronous

Serial I/O with

Chip Select

A/D

Converter

Interrupt

Timer

Interface

(TRCIOD)⁽¹⁾

TRAO

1

2

P3_5

P3_7

SSCK

SCL

RXD1/

(TXD1)^{(1, 3)}

SSO

3

RESET

XOUT/XCOUT⁽²⁾

VSS/AVSS

XIN/XCIN⁽²⁾

VCC/AVCC

MODE

4

5

6

7

8

9

P4_7

P4_6

(RXD1)^{(1, 3)}

P4_5

P1_7

INT0

INT1

10

11

TRAIO

(TXD1)/

(RXD1)^{(1, 3)}

(INT1)⁽¹⁾

P3_6

12

13

14

15

16

P3_1

P5_4

P5_3

P1_6

TRBO

TRCIOD

TRCIOC

(SSI)⁽¹⁾

CLK0

RXD0

TXD0

(TRAIO)⁽¹⁾

(INT1)⁽¹⁾

P1_5

P1_4

P1_3

17

18

(TRBO)

TRCIOB

AN11

AN10

KI3

KI2

19

P1_2

P4_2

P1_1

20

21

VRFF

TRCIOA/

TRCTRG

AN9

AN8

KI1

22

23

24

P1_0

P3_3

KI0

TRCCLK

SSI

INT3

(TRCIOC)⁽¹⁾

P3_4

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

SDA

SCS

25

26

27

28

29

30

31

32

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

CLK1

TREO

(TXD1)^{(1, 3)}

NOTES:

1. This can be assigned to the pin in parentheses by a program.

2. XCIN, XCOUT can be used only for N or D version.

3. For the combination of using pins TXD1 and RXD1, refer to Figure 15.7 Registers PINSR1 and

PMR of Hardware Manual (REJ09B0278).

Rev.2.10 Sep 26, 2008 Page 11 of 69

REJ03B0168-0210

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2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

register bank. There are two sets of register bank.

b31

b15

b8b7

b0

R0H (high-order of R0) R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)

R2

R3

Data registers⁽¹⁾

R3

A0

Address registers⁽¹⁾

A1

FB

Frame base register⁽¹⁾

b19

b15

b0

Interrupt table register

Program counter

INTBH

INTBL

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

b19

PC

b15

b0

User stack pointer

Interrupt stack pointer

Static base register

USP

ISP

SB

b15

b0

Flag register

FLG

b15

b8

b7

IPL

U I O B S Z D C

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

NOTE:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1

CPU Registers

Rev.2.10 Sep 26, 2008 Page 12 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

2. Central Processing Unit (CPU)

2.1

Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split

into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are

analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is

analogous to R2R0.

2.2

Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used

as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.

2.5

Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1

Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2

Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4

Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5

Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6

Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

Rev.2.10 Sep 26, 2008 Page 13 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

2. Central Processing Unit (CPU)

2.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

Rev.2.10 Sep 26, 2008 Page 14 of 69

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3.Memory

3. Memory

3.1

R8C/26 Group

Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses

00000h to FFFFFh.

The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal

ROM area is allocated addresses 0C000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each

interrupt routine.

The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal

RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for

calling subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control

registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use

and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXh

0FFDCh

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer/oscillation stop detection/voltage monitor

0YYYYh

(Reserved)

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

FFFFFh

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Internal ROM

Part Number

Internal RAM

Size

Address 0YYYYh

Size

Address 0XXXXh

005FFh

R5F21262SNFP, R5F21262SDFP,

R5F21262SNXXXFP, R5F21262SDXXXFP

R5F21264SNFP, R5F21264SDFP,

R5F21264JFP, R5F21264KFP,

8 Kbytes

0E000h

512 bytes

1 Kbyte

16 Kbytes

24 Kbytes

32 Kbytes

0C000h

0A000h

08000h

007FFh

009FFh

R5F21264SNXXXFP, R5F21264SDXXXFP,

R5F21264JXXXFP, R5F21264KXXXFP

R5F21265SNFP, R5F21265SDFP

1.5 Kbytes

R5F21265SNXXXFP, R5F21265SDXXXFP

R5F21266SNFP, R5F21266SDFP,

R5F21266JFP, R5F21266KFP,

R5F21266SNXXXFP, R5F21266SDXXXFP,

R5F21266JXXXFP, R5F21266KXXXFP

Figure 3.1

Memory Map of R8C/26 Group

Rev.2.10 Sep 26, 2008 Page 15 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

3.Memory

3.2

R8C/27 Group

Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses

00000h to FFFFFh.

The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a

16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each

interrupt routine.

The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.

The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte

internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also

for calling subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control

registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use

and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXXh

02400h

0FFDCh

Internal ROM

Undefined instruction

(data flash)⁽¹⁾

Overflow

02BFFh

0YYYYh

BRK instruction

Address match

Single step

Watchdog timer/oscillation stop detection/voltage monitor

(Reserved)

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

FFFFFh

NOTES:

1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.

2. The blank regions are reserved. Do not access locations in these regions.

Internal ROM

Part Number

Internal RAM

Size

Address 0YYYYh

Size

Address 0XXXXh

R5F21272SNFP, R5F21272SDFP,

R5F21272SNXXXFP, R5F21272SDXXXFP

R5F21274SNFP, R5F21274SDFP,

R5F21274JFP, R5F21274KFP,

8 Kbytes

0E000h

512 bytes

1 Kbyte

005FFh

16 Kbytes

24 Kbytes

32 Kbytes

0C000h

0A000h

08000h

007FFh

009FFh

R5F21274SNXXXFP, R5F21274SDXXXFP,

R5F21274JXXXFP, R5F21274KXXXFP

R5F21275SNFP, R5F21275SDFP,

R5F21275SNXXXFP, R5F21275SDXXXFP

R5F21276SNFP, R5F21276SDFP,

R5F21276JFP, R5F21276KFP,

1.5 Kbytes

R5F21276SNXXXFP, R5F21276SDXXXFP,

R5F21276JXXXFP, R5F21276KXXXFP

Figure 3.2

Memory Map of R8C/27 Group

Rev.2.10 Sep 26, 2008 Page 16 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special

function registers.

(1)

Table 4.1

SFR Information (1)

Address

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

Register

Symbol

After reset

Processor Mode Register 0

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

PM0

PM1

CM0

CM1

00h

01101000b

00100000b

Protect Register

PRCR

00h

Oscillation Stop Detection Register

Watchdog Timer Reset Register

Watchdog Timer Start Register

Watchdog Timer Control Register

Address Match Interrupt Register 0

OCD

00000100b

XXh

WDTR

WDTS

WDC

XXh

00X11111b

00h

RMAD0

00h

Address Match Interrupt Enable Register

Address Match Interrupt Register 1

AIER

RMAD1

Count Source Protection Mode Register

CSPR

00h

(2)

10000000b

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

High-Speed On-Chip Oscillator Control Register 0

High-Speed On-Chip Oscillator Control Register 1

High-Speed On-Chip Oscillator Control Register 2

FRA0

FRA1

FRA2

00h

When shipping

00h

Clock Prescaler Reset Flag

CPSRF

FRA4

00h

When shipping

(3)

High-Speed On-Chip Oscillator Control Register 4

(3)

FRA6

FRA7

When shipping

High-Speed On-Chip Oscillator Control Register 6

High-Speed On-Chip Oscillator Control Register 7

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. The CSPROINI bit in the OFS register is set to 0.

3. In J, K version these regions are reserved. Do not access locations in these regions.

Rev.2.10 Sep 26, 2008 Page 17 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

(1)

Table 4.2

SFR Information (2)

Address

0030h

0031h

0032h

Register

Symbol

After reset

(2)

VCA1

VCA2

00001000b

• N, D version 00h

00100000b

Voltage Detection Register 1

Voltage Detection Register 2

(3)

(4)

(8)

(7)

• J, K version 00h

01000000b

0033h

0034h

0035h

0036h

(5)

VW1C

• N, D version 00001000b

Voltage Monitor 1 Circuit Control Register

(7)

• J, K version 0000X000b

(8)

0100X001b

00h

(5)

(6)

0037h

0038h

VW2C

VW0C

Voltage Monitor 2 Circuit Control Register

Voltage Monitor 0 Circuit Control Register

(3)

0000X000b

(4)

0100X001b

0039h

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

Timer RC Interrupt Control Register

Timer RE Interrupt Control Register

TRCIC

TREIC

XXXXX000b

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

KUPIC

ADIC

SSUIC/IICIC

XXXXX000b

(9)

SSU/IIC bus Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

S0TIC

S0RIC

S1TIC

S1RIC

XXXXX000b

Timer RA Interrupt Control Register

TRAIC

XXXXX000b

Timer RB Interrupt Control Register

INT1 Interrupt Control Register

INT3 Interrupt Control Register

TRBIC

INT1IC

INT3IC

XXXXX000b

XX00X000b

INT0 Interrupt Control Register

INT0IC

XX00X000b

006Fh

0070h

007Fh

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.

(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register.

3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.

4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.

5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.

(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.

6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.

(J, K version) These regions are reserved. Do not access locations in these regions.

7. The LVD1ON bit in the OFS register is set to 1 and hardware reset.

8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.

9. Selected by the IICSEL bit in the PMR register.

Rev.2.10 Sep 26, 2008 Page 18 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

(1)

Table 4.3

SFR Information (3)

Address

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

Register

Symbol

After reset

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

U0MR

00h

XXh

U0BRG

U0TB

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

00001000b

00000010b

XXh

00h

XXh

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

U1MR

U1BRG

U1TB

UART1 Transmit Buffer Register

XXh

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

U1C0

U1C1

U1RB

00001000b

00000010b

XXh

(2)

SSCRH / ICCR1

SSCRL / ICCR2

SSMR / ICMR

SSER / ICIER

SSSR / ICSR

00h

SS Control Register H / IIC bus Control Register 1

(2)

01111101b

00011000b

00h

SS Control Register L / IIC bus Control Register 2

(2)

SS Mode Register / IIC bus Mode Register

(2)

SS Enable Register / IIC bus Interrupt Enable Register

(2)

00h / 0000X000b

00h

SS Status Register / IIC bus Status Register

(2)

SSMR2 / SAR

SSTDR / ICDRT

SSRDR / ICDRR

SS Mode Register 2 / Slave Address Register

(2)

FFh

SS Transmit Data Register / IIC bus Transmit Data Register

(2)

FFh

SS Receive Data Register / IIC bus Receive Data Register

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. Selected by the IICSEL bit in the PMR register.

Rev.2.10 Sep 26, 2008 Page 19 of 69

REJ03B0168-0210

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4. Special Function Registers (SFRs)

(1)

Table 4.4

SFR Information (4)

Address

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

Register

Symbol

After reset

A/D Register

AD

XXh

A/D Control Register 2

ADCON2

00h

A/D Control Register 0

A/D Control Register 1

ADCON0

ADCON1

00h

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

P0

P1

PD0

PD1

00h

Port P3 Register

P3

00h

Port P3 Direction Register

Port P4 Register

Port P5 Register

Port P4 Direction Register

Port P5 Direction Register

PD3

P4

P5

PD4

PD5

00h

Pin Select Register 1

Pin Select Register 2

Pin Select Register 3

Port Mode Register

PINSR1

PINSR2

PINSR3

PMR

INTEN

INTF

00h

External Input Enable Register

INT Input Filter Select Register

Key Input Enable Register

Pull-Up Control Register 0

Pull-Up Control Register 1

Port P1 Drive Capacity Control Register

KIEN

PUR0

PUR1

P1DRR

(2)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. In J, K version these regions are reserved. Do not access locations in these regions.

Rev.2.10 Sep 26, 2008 Page 20 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

(1)

Table 4.5

SFR Information (5)

Address

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

Register

Symbol

TRACR

TRAIOC

TRAMR

TRAPRE

TRA

After reset

Timer RA Control Register

Timer RA I/O Control Register

Timer RA Mode Register

Timer RA Prescaler Register

Timer RA Register

00h

FFh

LIN Control Register

LIN Status Register

Timer RB Control Register

Timer RB One-Shot Control Register

Timer RB I/O Control Register

Timer RB Mode Register

Timer RB Prescaler Register

Timer RB Secondary Register

Timer RB Primary Register

LINCR

LINST

00h

FFh

TRBCR

TRBOCR

TRBIOC

TRBMR

TRBPRE

TRBSC

TRBPR

Timer RE Second Data Register / Counter Data Register

Timer RE Minute Data Register / Compare Data Register

TRESEC

TREMIN

TREHR

00h

(2)

Timer RE Hour Data Register

(2)

TREWK

TRECR1

TRECR2

TRECSR

Timer RE Day of Week Data Register

Timer RE Control Register 1

Timer RE Control Register 2

Timer RE Count Source Select Register

00001000b

Timer RC Mode Register

TRCMR

TRCCR1

TRCIER

TRCSR

TRCIOR0

TRCIOR1

TRC

01001000b

00h

Timer RC Control Register 1

Timer RC Interrupt Enable Register

Timer RC Status Register

Timer RC I/O Control Register 0

Timer RC I/O Control Register 1

Timer RC Counter

01110000b

10001000b

00h

FFh

Timer RC General Register A

Timer RC General Register B

Timer RC General Register C

Timer RC General Register D

TRCGRA

TRCGRB

TRCGRC

TRCGRD

FFh

Timer RC Control Register 2

TRCCR2

TRCDF

TRCOER

00011111b

00h

01111111b

Timer RC Digital Filter Function Select Register

Timer RC Output Master Enable Register

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. In J, K version these regions are reserved. Do not access locations in these regions.

Rev.2.10 Sep 26, 2008 Page 21 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

(1)

Table 4.6

SFR Information (6)

Address

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

Register

Symbol

After reset

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Rev.2.10 Sep 26, 2008 Page 22 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

(1)

Table 4.7

SFR Information (7)

Address

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Register

Symbol

After reset

Flash Memory Control Register 4

Flash Memory Control Register 1

Flash Memory Control Register 0

FMR4

FMR1

FMR0

01000000b

1000000Xb

00000001b

FFFFh

Option Function Select Register

OFS

(Note 2)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.

Rev.2.10 Sep 26, 2008 Page 23 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

5.1

N, D Version

Table 5.1

Absolute Maximum Ratings

Symbol

Parameter

Supply voltage

Condition

Rated Value

Unit

V

VCC/AVCC

-0.3 to 6.5

-0.3 to VCC + 0.3

500

VI

Input voltage

V

VO

Pd

Output voltage

V

Power dissipation

Topr = 25°C

mW

°C

Topr

Operating ambient temperature

-20 to 85 (N version) /

-40 to 85 (D version)

Tstg

Storage temperature

-65 to 150

°C

Table 5.2

Recommended Operating Conditions

Standard

Symbol

Parameter

Conditions

Unit

Min.

Typ.

−

Max.

5.5

VCC/AVCC Supply voltage

2.2

V

VSS/AVSS

VIH

Supply voltage

−

0

−

Input “H” voltage

0.8 VCC

−

VCC

V

VIL

Input “L” voltage

0

−

0.2 VCC

-160

V

IOH(sum)

Peak sum output Sum of all pins IOH(peak)

“H” current

−

mA

IOH(sum)

IOH(peak)

Average sum

output “H” current

Peak output “H”

current

Sum of all pins IOH(avg)

−

-80

mA

Except P1_0 to P1_7

P1_0 to P1_7

−

-10

-40

-5

mA

IOH(avg)

Average output

“H” current

Except P1_0 to P1_7

P1_0 to P1_7

-20

160

IOL(sum)

IOL(peak)

Peak sum output Sum of all pins IOL(peak)

“L” currents

Average sum

output “L” currents

Peak output “L”

currents

Sum of all pins IOL(avg)

−

80

mA

Except P1_0 to P1_7

P1_0 to P1_7

−

0

−

10

40

5

mA

IOL(avg)

f(XIN)

Average output

“L” current

Except P1_0 to P1_7

P1_0 to P1_7

−

mA

−

20

10

5

mA

XIN clock input oscillation frequency

3.0 V ≤ VCC ≤ 5.5 V

2.7 V ≤ VCC < 3.0 V

2.2 V ≤ VCC < 2.7 V

2.2 V ≤ VCC ≤ 5.5 V

3.0 V ≤ VCC ≤ 5.5 V

2.7 V ≤ VCC < 3.0 V

2.2 V ≤ VCC < 2.7 V

−

MHz

kHz

MHz

kHz

−

f(XCIN)

XCIN clock input oscillation frequency

−

70

20

10

5

−

System clock

OCD2 = 0

XlN clock selected

−

OCD2 = 1

FRA01 = 0

125

−

Low-speed on-chip

oscillator clock selected

On-chip oscillator clock

selected

FRA01 = 1

−

20

10

5

MHz

High-speed on-chip

oscillator clock selected

3.0 V ≤ VCC ≤ 5.5 V

FRA01 = 1

High-speed on-chip

oscillator clock selected

2.7 V ≤ VCC ≤ 5.5 V

FRA01 = 1

High-speed on-chip

oscillator clock selected

2.2 V ≤ VCC ≤ 5.5 V

NOTES:

1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

Rev.2.10 Sep 26, 2008 Page 24 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.3

A/D Converter Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

−

Typ.

−

Max.

10

±3

±2

±5

±2

±5

±2

40

−

Resolution

Vref = AVCC

Bits

LSB

kΩ

Absolute

accuracy

10-bit mode

8-bit mode

10-bit mode

8-bit mode

10-bit mode

8-bit mode

φAD = 10 MHz, Vref = AVCC = 5.0 V

φAD = 10 MHz, Vref = AVCC = 3.3 V

φAD = 5 MHz, Vref = AVCC = 2.2 V

Vref = AVCC

−

Rladder

tconv

Resistor ladder

10

3.3

2.8

2.2

0

−

Conversion time 10-bit mode

8-bit mode

φAD = 10 MHz, Vref = AVCC = 5.0 V

−

µs

−

µs

Vref

VIA

−

Reference voltage

−

AVCC

10

5

V

Analog input voltage⁽²⁾

−

V

A/D operating

clock frequency

Without sample and hold Vref = AVCC = 2.7 to 5.5 V

0.25

1

−

MHz

With sample and hold

Vref = AVCC = 2.7 to 5.5 V

−

Without sample and hold Vref = AVCC = 2.2 to 5.5 V

With sample and hold Vref = AVCC = 2.2 to 5.5 V

0.25

1

−

5

NOTES:

1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

P0

P1

30pF

P3

P4

P5

Figure 5.1

Ports P0, P1, and P3 to P5 Timing Measurement Circuit

Rev.2.10 Sep 26, 2008 Page 25 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.4

Flash Memory (Program ROM) Electrical Characteristics

Standard

Unit

Symbol

Parameter

Conditions

R8C/26 Group

Min.

Typ.

−

Max.

−

Program/erase endurance⁽²⁾

100⁽³⁾

−

times

µs

1,000⁽³⁾

R8C/27 Group

−

Byte program time

Block erase time

−

50

0.4

−

400

9

−

s

td(SR-SUS)

Time delay from suspend request until

suspend

97 + CPU clock

× 6 cycles

µs

−

Interval from erase start/restart until

following suspend request

650

0

−

µs

ns

µs

Interval from program start/restart until

following suspend request

−

Time from suspend until program/erase

restart

−

3 + CPU clock

× 4 cycles

−

Program, erase voltage

Read voltage

2.7

2.2

0

−

5.5

60

−

V

Program, erase temperature

Data hold time⁽⁷⁾

°C

Ambient temperature = 55°C

20

year

NOTES:

1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024

1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

Rev.2.10 Sep 26, 2008 Page 26 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(4)

Table 5.5

Flash Memory (Data flash Block A, Block B) Electrical Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

10,000⁽³⁾

−

Typ.

−

Max.

−

Program/erase endurance⁽²⁾

−

times

Byte program time

50

400

µs

(program/erase endurance ≤ 1,000 times)

−

Byte program time

(program/erase endurance > 1,000 times)

−

65

0.2

0.3

−

9

−

µs

s

−

Block erase time

(program/erase endurance ≤ 1,000 times)

−

Block erase time

(program/erase endurance > 1,000 times)

−

s

td(SR-SUS)

Time delay from suspend request until

suspend

−

97 + CPU clock

× 6 cycles

µs

ns

µs

−

Interval from erase start/restart until

following suspend request

650

0

−

Interval from program start/restart until

following suspend request

−

Time from suspend until program/erase

restart

−

3 + CPU clock

× 4 cycles

−

Program, erase voltage

Read voltage

2.7

2.2

−

5.5

85

−

V

-20⁽⁸⁾

20

Program, erase temperature

°C

Data hold time⁽⁹⁾

Ambient temperature = 55°C

year

NOTES:

1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times

is the same as that in program ROM.

5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further

reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the

number of erase operations to a certain number.

6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

8. -40°C for D version.

9. The data hold time includes time that the power supply is off or the clock is not supplied.

Rev.2.10 Sep 26, 2008 Page 27 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Suspend request

(maskable interrupt request)

FMR46

Clock-dependent

time

Fixed time

Access restart

td(SR-SUS)

Figure 5.2

Time delay until Suspend

Table 5.6

Voltage Detection 0 Circuit Electrical Characteristics

Standard

Symbol

Parameter

Voltage detection level

Condition

Unit

Min.

Typ.

2.3

0.9

−

Max.

2.4

−

Vdet0

−

2.2

−

V

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts⁽²⁾

VCA25 = 1, VCC = 5.0 V

µA

µs

td(E-A)

−

300

Vccmin

MCU operating voltage minimum value

2.2

−

V

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).

2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

register to 0.

Table 5.7

Voltage Detection 1 Circuit Electrical Characteristics

Standard

Typ.

2.85

40

Symbol

Parameter

Voltage detection level⁽⁴⁾

Condition

Unit

Min.

2.70

−

Max.

3.00

−

Vdet1

V

Voltage monitor 1 interrupt request generation time⁽²⁾

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts⁽³⁾

−

µs

µA

µs

−

VCA26 = 1, VCC = 5.0 V

−

0.6

−

td(E-A)

−

100

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).

2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

register to 0.

4. This parameter shows the voltage detection level when the power supply drops.

The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply

drops by approximately 0.1 V.

Table 5.8

Voltage Detection 2 Circuit Electrical Characteristics

Standard

Typ.

3.6

Symbol

Parameter

Condition

Unit

Min.

3.3

−

Max.

3.9

−

Vdet2

V

Voltage detection level

Voltage monitor 2 interrupt request generation time⁽²⁾

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts⁽³⁾

−

40

µs

µA

µs

−

VCA27 = 1, VCC = 5.0 V

−

0.6

−

td(E-A)

−

100

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

register to 0.

Rev.2.10 Sep 26, 2008 Page 28 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(3)

Table 5.9

Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

−

Typ.

−

Max.

0.1

Power-on reset valid voltage⁽⁴⁾

Vpor1

Vpor2

V

Power-on reset or voltage monitor 0 reset valid

voltage

0

−

Vdet0

External power VCC rise gradient⁽²⁾

trth

20

−

mV/msec

NOTES:

1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.

3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the

VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.

4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for

3,000 s or more if -40°C ≤ Topr < -20°C.

(3)

Vdet0

(3)

Vdet0

2.2 V

trth

External

Power VCC

Vpor2

Vpor1

Sampling time^{(1, 2)}

tw(por1)

Internal

reset signal

(“L” valid)

1

× 32

fOCO-S

NOTES:

1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage

range (2.2 V or above) during the sampling time.

2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.

3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of Hardware Manual for details.

Figure 5.3

Reset Circuit Electrical Characteristics

Rev.2.10 Sep 26, 2008 Page 29 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.10

High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

39.2

Typ.

40

Max.

40.8

fOCO40M

High-speed on-chip oscillator frequency

temperature • supply voltage dependence

VCC = 4.75 to 5.25 V

0°C ≤ Topr ≤ 60°C⁽²⁾

VCC = 3.0 to 5.5 V

MHz

38.8

38.4

38

40

41.2

41.6

42

-20°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 3.0 to 5.5 V

-40°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 2.7 to 5.5 V

-20°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 2.7 to 5.5 V

37.6

35.2

34

42.4

44.8

46

-40°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 2.2 to 5.5 V

-20°C ≤ Topr ≤ 85°C⁽³⁾

VCC = 2.2 to 5.5 V

-40°C ≤ Topr ≤ 85°C⁽³⁾

VCC = 5.0 V ± 10%

-20°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 5.0 V ± 10%

-40°C ≤ Topr ≤ 85°C⁽²⁾

VCC = 5.0 V, Topr = 25°C

38.8

38.4

40.8

High-speed on-chip oscillator frequency when

correction value in FRA7 register is written to

FRA1 register⁽⁴⁾

−

36.864

−

MHz

%

VCC = 3.0 to 5.5 V

-20°C ≤ Topr ≤ 85°C

-3%

−

3%

08h⁽³⁾

F7h⁽³⁾

−

Value in FRA1 register after reset

−

Oscillation frequency adjustment unit of high-

speed on-chip oscillator

Adjust FRA1 register

(value after reset) to -1

−

+0.3

−

MHz

−

Oscillation stability time

−

10

100

µs

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°C

400

−

µA

NOTES:

1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. These standard values show when the FRA1 register value after reset is assumed.

3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.

4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

Table 5.11

Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Typ.

125

Symbol

fOCO-S

Parameter

Condition

Unit

Min.

30

−

Max.

250

100

−

Low-speed on-chip oscillator frequency

Oscillation stability time

kHz

µs

−

10

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°C

−

15

µA

NOTE:

1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

Table 5.12

Power Supply Circuit Timing Characteristics

Standard

Symbol

Parameter

Condition

Unit

Min.

1

Typ.

Max.

2000

td(P-R)

Time for internal power supply stabilization during

power-on⁽²⁾

−

µs

STOP exit time⁽³⁾

td(R-S)

−

150

µs

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.

Rev.2.10 Sep 26, 2008 Page 30 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(1)

Table 5.13

Timing Requirements of Clock Synchronous Serial I/O with Chip Select

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

−

Max.

−

(2)

tCYC

tSUCYC

tHI

SSCK clock cycle time

SSCK clock “H” width

SSCK clock “L” width

4

0.4

−

0.6

1

tSUCYC

tLO

0.4

−

(2)

tRISE

SSCK clock rising

time

Master

Slave

−

tCYC

−

1

µs

(2)

tFALL

SSCK clock falling

time

Master

Slave

−

1

tCYC

−

100

−

1

µs

tSU

SSO, SSI data input setup time

SSO, SSI data input hold time

−

ns

(2)

tH

1

−

tCYC

tLEAD

Slave

1tCYC + 50

−

ns

SCS setup time

SCS hold time

tLAG

1tCYC + 50

−

(2)

tOD

tSA

SSO, SSI data output delay time

SSI slave access time

−

1

tCYC

2.7 V ≤ VCC ≤ 5.5 V

2.2 V ≤ VCC < 2.7 V

2.7 V ≤ VCC ≤ 5.5 V

2.2 V ≤ VCC < 2.7 V

1.5tCYC + 100

1.5tCYC + 200

1.5tCYC + 100

1.5tCYC + 200

ns

tOR

SSI slave out open time

NOTES:

1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. 1tCYC = 1/f1(s)

Rev.2.10 Sep 26, 2008 Page 31 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

SCS (output)

VIH or VOH

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

4-Wire Bus Communication Mode, Master, CPHS = 0

VIH or VOH

SCS (output)

VIH or VOH

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

CPHS, CPOS: Bits in SSMR register

Figure 5.4

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)

Rev.2.10 Sep 26, 2008 Page 32 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

SCS (input)

VIH or VOH

tLEAD

tHI

tFALL

tRISE

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

4-Wire Bus Communication Mode, Slave, CPHS = 0

VIH or VOH

SCS (input)

VIH or VOH

tHI

tFALL

tRISE

tLEAD

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

CPHS, CPOS: Bits in SSMR register

Figure 5.5

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)

Rev.2.10 Sep 26, 2008 Page 33 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

tHI

VIH or VOH

SSCK

SSO (output)

SSI (input)

tLO

tSUCYC

tOD

tSU

tH

Figure 5.6

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous

Communication Mode)

Rev.2.10 Sep 26, 2008 Page 34 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

2

(1)

Table 5.14

Timing Requirements of I C bus Interface

Standard

Unit

Symbol

Parameter

SCL input cycle time

Condition

Min.

12t^CYC+ 600⁽²⁾

3t^CYC+ 300⁽²⁾

5t^CYC+ 500⁽²⁾

−

Typ.

−

Max.

−

t^SCL

ns

t^SCLH

t^SCLL

t^sf

SCL input “H” width

−

SCL input “L” width

−

SCL, SDA input fall time

−

300

(2)

t^SP

SCL, SDA input spike pulse rejection time

SDA input bus-free time

−

1tCYC

(2)

t^BUF

t^STAH

t^STAS

t^STOP

t^SDAS

t^SDAH

−

5t^CYC

(2)

Start condition input hold time

Retransmit start condition input setup time

Stop condition input setup time

Data input setup time

−

3t^CYC

(2)

−

3t^CYC

(2)

−

3t^CYC

1t^CYC+ 20⁽²⁾

0

−

Data input hold time

−

NOTES:

1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.

2. 1t^CYC= 1/f1(s)

VIH

SDA

VIL

tBUF

tSTAH

tSP

tSTOP

tSCLH

tSTAS

SCL

P⁽²⁾

S⁽¹⁾

tsf

Sr⁽³⁾

P⁽²⁾

tSCLL

tsr

tSDAS

tSCL

tSDAH

NOTES:

1. Start condition

2. Stop condition

3. Retransmit start condition

2

Figure 5.7

I/O Timing of I C bus Interface

Rev.2.10 Sep 26, 2008 Page 35 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.15

Electrical Characteristics (1) [VCC = 5 V]

Standard

Unit

Symbol

Parameter

Output “H” voltage Except P1_0 to P1_7, IOH = −5 mA

Condition

Min.

Typ.

−

Max.

VCC

2.0

V^OH

VCC - 2.0

V

XOUT

I^OH= -200 µA

VCC - 0.5

−

P1_0 to P1_7

Drive capacity HIGH I^OH= -20 mA

Drive capacity LOW I^OH= -5 mA

Drive capacity HIGH I^OH= -1 mA

Drive capacity LOW I^OH= -500 µA

VCC - 2.0

−

VCC - 2.0

−

XOUT

VCC - 2.0

−

VCC - 2.0

−

V^OL

Output “L” voltage Except P1_0 to P1_7, IOL = 5 mA

−

XOUT

I^OL= 200 µA

−

0.45

2.0

P1_0 to P1_7

Drive capacity HIGH I^OL= 20 mA

Drive capacity LOW I^OL= 5 mA

Drive capacity HIGH I^OL= 1 mA

Drive capacity LOW I^OL= 500 µA

−

2.0

XOUT

−

2.0

−

2.0

V^T+-VT-

Hysteresis

0.1

0.5

−

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, RXD0, RXD1,

CLK0, CLK1,

SSI, SCL, SDA, SSO

0.1

1.0

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 5 V, VCC = 5 V

VI = 0 V, VCC = 5 V

−

5.0

-5.0

167

−

µA

R^PULLUPPull-up resistance

30

−

50

1.0

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

RfXCIN

Feedback

resistance

XCIN

−

18

−

MΩ

VRAM

RAM hold voltage

During stop mode

1.8

−

V

NOTE:

1. V^CC= 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.

Rev.2.10 Sep 26, 2008 Page 36 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.16

Electrical Characteristics (2) [Vcc = 5 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

10

Max.

17

I^CC

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

(V^CC= 3.3 to 5.5 V)

Single-chip mode,

output pins are open,

other pins are V^SS

clock mode

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

9

6

15

−

mA

µA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

5

−

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

4

−

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

2.5

10

4

−

High-speed

on-chip

oscillator

mode

XIN clock off

15

−

High-speed on-chip oscillator on fOCO = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

5.5

2.5

130

10

−

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed

on-chip

oscillator

mode

XIN clock off

300

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

Low-speed

clock mode

XIN clock off

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

FMR47 = 1

XIN clock off

−

30

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

Program operation on RAM

Flash memory off, FMSTP = 1

Rev.2.10 Sep 26, 2008 Page 37 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.17

Electrical Characteristics (3) [Vcc = 5 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)

Standard

Symbol

Parameter

Condition

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

Unit

Min.

Typ.

25

Max.

75

I^CC

Power supply current Wait mode

(V^CC= 3.3 to 5.5 V)

Single-chip mode,

output pins are open,

other pins are V^SS

−

µA

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

23

4.0

2.2

60

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode

XIN clock off, T^opr= 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

0.8

1.2

3.0

µA

XIN clock off, T^opr= 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

Rev.2.10 Sep 26, 2008 Page 38 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]

Table 5.18

XIN Input, XCIN Input

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(XIN)

XIN input cycle time

XIN input “H” width

XIN input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

50

25

14

7

−

ns

µs

t^WH(XIN)

t^WL(XIN)

t^c(XCIN)

t^WH(XCIN)

t^WL(XCIN)

7

VCC = 5 V

tC(XIN)

tWH(XIN)

XIN input

tWL(XIN)

Figure 5.8

XIN Input and XCIN Input Timing Diagram when VCC = 5 V

Table 5.19

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

100

40

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

40

tC(TRAIO)

VCC = 5 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.9

TRAIO Input Timing Diagram when VCC = 5 V

Rev.2.10 Sep 26, 2008 Page 39 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.20

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

200

100

−

ns

t^W(CKH)

t^W(CKL)

t^d(C-Q)

t^h(C-Q)

t^su(D-C)

t^h(C-D)

−

50

−

0

RXDi input setup time

RXDi input hold time

50

90

−

i = 0 or 1

VCC = 5 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 or 1

Figure 5.10

Serial Interface Timing Diagram when VCC = 5 V

Table 5.21

External Interrupt INTi (i = 0, 1, 3) Input

Standard

Symbol

Parameter

Unit

Min.

Max.

250⁽¹⁾

250⁽²⁾

t^W(INH)

t^W(INL)

−

ns

INTi input “H” width

INTi input “L” width

−

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 5 V

tW(INL)

INTi input

tW(INH)

i = 0, 1, 3

Figure 5.11

External Interrupt INTi Input Timing Diagram when VCC = 5 V

Rev.2.10 Sep 26, 2008 Page 40 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.22

Electrical Characteristics (3) [VCC = 3 V]

Standard

Unit

Symbol

Parameter

Output “H” voltage Except P1_0 to P1_7, IOH = -1 mA

Condition

Min.

Typ.

Max.

VCC

V^OH

VCC - 0.5

−

V

XOUT

P1_0 to P1_7

Drive capacity

HIGH

I^OH= -5 mA

IOH = -1 mA

VCC - 0.5

−

VCC

0.5

−

Drive capacity

LOW

XOUT

Drive capacity

HIGH

I^OH= -0.1 mA VCC - 0.5

−

Drive capacity

LOW

I^OH= -50 µA

VCC - 0.5

−

VOL

Output “L” voltage

Except P1_0 to P1_7, IOL = 1 mA

XOUT

−

P1_0 to P1_7

Drive capacity

HIGH

I^OL= 5 mA

I^OL= 1 mA

I^OL= 0.1 mA

I^OL= 50 µA

−

Drive capacity

LOW

−

XOUT

Drive capacity

HIGH

−

Drive capacity

LOW

−

V^T+-VT-

Hysteresis

0.1

0.3

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, RXD0, RXD1,

CLK0, CLK1,

SSI, SCL, SDA, SSO

0.1

0.4

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 3 V, VCC = 3 V

VI = 0 V, VCC = 3 V

−

4.0

-4.0

500

−

µA

kΩ

MΩ

V

R^PULLUPPull-up resistance

66

−

160

3.0

18

−

RfXIN

Feedback resistance XIN

Feedback resistance XCIN

RAM hold voltage

RfXCIN

VRAM

−

During stop mode

1.8

−

NOTE:

1. V^CC= 2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.

Rev.2.10 Sep 26, 2008 Page 41 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.23

Electrical Characteristics (4) [Vcc = 3 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

6

Max.

I^CC

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

(V^CC= 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are V^SS

clock mode

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

2

5

−

9

mA

µA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

2

−

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed

on-chip

oscillator

mode

XIN clock off

130

300

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

Low-speed

clock mode

XIN clock off

−

130

30

300

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

FMR47 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

Program operation on RAM

Flash memory off, FMSTP = 1

Wait mode

XIN clock off

−

25

23

70

55

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

3.8

2.0

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

0.7

1.1

3.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, T^opr= 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

Rev.2.10 Sep 26, 2008 Page 42 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]

Table 5.24

XIN Input, XCIN Input

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(XIN)

XIN input cycle time

XIN input “H” width

XIN input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

100

40

14

7

−

ns

µs

t^WH(XIN)

t^WL(XIN)

t^c(XCIN)

t^WH(XCIN)

t^WL(XCIN)

7

tC(XIN)

VCC = 3 V

tWH(XIN)

XIN input

tWL(XIN)

Figure 5.12

XIN Input and XCIN Input Timing Diagram when VCC = 3 V

Table 5.25

TRAIO Input

Standard

Symbol

Parameter

Unit

Min.

300

120

Max.

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

VCC = 3 V

tC(TRAIO)

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.13

TRAIO Input Timing Diagram when VCC = 3 V

Rev.2.10 Sep 26, 2008 Page 43 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.26

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(CK)

CLKi input cycle time

CLKi input “H” width

CLKi Input “L” width

TXDi output delay time

TXDi hold time

300

150

−

ns

t^W(CKH)

t^W(CKL)

t^d(C-Q)

t^h(C-Q)

t^su(D-C)

t^h(C-D)

−

80

−

0

RXDi input setup time

RXDi input hold time

70

90

−

i = 0 or 1

tC(CK)

VCC = 3 V

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 or 1

Figure 5.14

Serial Interface Timing Diagram when VCC = 3 V

Table 5.27

External Interrupt INTi (i = 0, 1, 3) Input

Standard

Min. Max.

Symbol

Parameter

Unit

380⁽¹⁾

380⁽²⁾

t^W(INH)

t^W(INL)

−

ns

INTi input “H” width

INTi input “L” width

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 3 V

tW(INL)

INTi input

tW(INH)

i = 0, 1, 3

Figure 5.15

External Interrupt INTi Input Timing Diagram when VCC = 3 V

Rev.2.10 Sep 26, 2008 Page 44 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.28

Electrical Characteristics (5) [VCC = 2.2 V]

Standard

Unit

Symbol

Parameter

Output “H” voltage Except P1_0 to P1_7, IOH = -1 mA

Condition

Min.

Typ.

Max.

VCC

V^OH

VCC - 0.5

−

V

XOUT

P1_0 to P1_7

Drive capacity

HIGH

I^OH= -2 mA

IOH = -1 mA

VCC - 0.5

−

VCC

0.5

−

Drive capacity

LOW

XOUT

Drive capacity

HIGH

I^OH= -0.1 mA VCC - 0.5

−

Drive capacity

LOW

I^OH= -50 µA

VCC - 0.5

−

VOL

Output “L” voltage

Except P1_0 to P1_7, IOL = 1 mA

XOUT

−

P1_0 to P1_7

Drive capacity

HIGH

I^OL= 2 mA

I^OL= 1 mA

I^OL= 0.1 mA

I^OL= 50 µA

−

Drive capacity

LOW

−

XOUT

Drive capacity

HIGH

−

Drive capacity

LOW

−

V^T+-VT-

Hysteresis

0.05

0.3

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, RXD0, RXD1,

CLK0, CLK1,

SSI, SCL, SDA, SSO

0.05

0.15

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 2.2 V

VI = 0 V

−

4.0

-4.0

600

−

µA

kΩ

MΩ

V

R^PULLUPPull-up resistance

100

−

200

5

RfXIN

Feedback resistance XIN

Feedback resistance XCIN

RAM hold voltage

RfXCIN

VRAM

−

35

−

During stop mode

1.8

−

NOTE:

1. V^CC= 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.

Rev.2.10 Sep 26, 2008 Page 45 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.29

Electrical Characteristics (6) [Vcc = 2.2 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

3.5

Max.

I^CC

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

(V^CC= 2.2 to 2.7 V)

Single-chip mode,

output pins are open,

other pins are V^SS

clock mode

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

1.5

3.5

1.5

100

−

mA

µA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

−

High-speed on-chip oscillator on fOCO = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed

on-chip

oscillator

mode

XIN clock off

230

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

Low-speed

clock mode

XIN clock off

−

100

25

230

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

FMR47 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

Program operation on RAM

Flash memory off, FMSTP = 1

Wait mode

XIN clock off

−

22

20

60

55

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

3.0

1.8

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

0.7

1.1

3.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, T^opr= 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

Rev.2.10 Sep 26, 2008 Page 46 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]

Table 5.30

XIN Input, XCIN Input

Standard

Symbol

Parameter

Unit

Min.

Max.

t^c(XIN)

XIN input cycle time

XIN input “H” width

XIN input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

200

90

14

7

−

ns

µs

t^WH(XIN)

t^WL(XIN)

t^c(XCIN)

t^WH(XCIN)

t^WL(XCIN)

7

tC(XIN)

VCC = 2.2 V

tWH(XIN)

XIN input

tWL(XIN)

Figure 5.16

XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V

Table 5.31

TRAIO Input

Standard

Symbol

Parameter

Unit

Min.

500

200

Max.

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

tC(TRAIO)

VCC = 2.2 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.17

TRAIO Input Timing Diagram when VCC = 2.2 V

Rev.2.10 Sep 26, 2008 Page 47 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.32

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

800

400

−

ns

t^W(CKH)

t^W(CKL)

t^d(C-Q)

t^h(C-Q)

t^su(D-C)

t^h(C-D)

−

200

−

0

RXDi input setup time

RXDi input hold time

150

90

−

i = 0 or 1

VCC = 2.2 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 or 1

Figure 5.18

Serial Interface Timing Diagram when VCC = 2.2 V

Table 5.33

External Interrupt INTi (i = 0, 1, 3) Input

Standard

Min. Max.

Symbol

Parameter

Unit

1000⁽¹⁾

1000⁽²⁾

t^W(INH)

t^W(INL)

−

ns

INTi input “H” width

INTi input “L” width

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 2.2 V

tW(INL)

INTi input

tW(INH)

i = 0, 1, 3

Figure 5.19

External Interrupt INTi Input Timing Diagram when VCC = 2.2 V

Rev.2.10 Sep 26, 2008 Page 48 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

5.2

J, K Version

Table 5.34

Absolute Maximum Ratings

Symbol

Parameter

Supply voltage

Condition

Rated Value

Unit

V

V^CC/AVCC

-0.3 to 6.5

-0.3 to VCC + 0.3

300

V^I

Input voltage

V

V^O

P^d

Output voltage

V

Power dissipation

-40 °C ≤ Topr ≤ 85 °C

85 °C ≤ Topr ≤ 125 °C

mW

°C

125

T^opr

T^stg

Operating ambient temperature

Storage temperature

-40 to 85 (J version) /

-40 to 125 (K version)

-65 to 150

°C

Table 5.35

Recommended Operating Conditions

Standard

Symbol

Parameter

Conditions

Unit

Min.

Typ.

−

Max.

5.5

V^CC/AVCC Supply voltage

2.7

V

V^SS/AVSS

V^IH

Supply voltage

−

0

−

Input “H” voltage

0.8 VCC

−

VCC

0.2 VCC

-60

V

V^IL

Input “L” voltage

0

−

V

I^OH(sum)

Peak sum output Sum of all pins

−

mA

“H” current

I^OH(peak)

I^OH(avg)

I^OL(sum)

I^OL(peak)

I^OL(avg)

f^(XIN)

Peak output “H”

current

−

0

−

-10

-5

mA

MHz

Average output

“H” current

Peak sum output Sum of all pins

“L” currents

60

10

5

I^OL(peak)

Peak output “L”

currents

Average output

“L” current

XIN clock input oscillation frequency

3.0 V ≤ VCC ≤ 5.5 V (other than K

20

version)

3.0 V ≤ VCC ≤ 5.5 V (K version)

2.7 V ≤ VCC < 3.0 V

0

−

16

10

20

MHz

−

System clock

OCD2 = 0

3.0 V ≤ VCC ≤ 5.5 V (other than K

XlN clock selected version)

3.0 V ≤ VCC ≤ 5.5 V (K version)

0

−

16

10

−

MHz

kHz

2.7 V ≤ VCC < 3.0 V

OCD2 = 1

FRA01 = 0

125

On-chip oscillator Low-speed on-chip oscillator clock

clock selected

selected

FRA01 = 1

High-speed on-chip oscillator clock

selected (other than K version)

−

20

10

MHz

FRA01 = 1

High-speed on-chip oscillator clock

selected

NOTES:

1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

Rev.2.10 Sep 26, 2008 Page 49 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.36

A/D Converter Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

−

Typ.

−

Max.

10

−

Resolution

Vref = AVCC

Bits

LSB

kΩ

Absolute

accuracy

10-bit mode

8-bit mode

10-bit mode

8-bit mode

φAD = 10 MHz, Vref = AVCC = 5.0 V

φAD = 10 MHz, Vref = AVCC = 3.3 V

Vref = AVCC

−

±3

−

±2

−

±5

−

±2

R^ladder

Resistor ladder

10

3.3

2.8

2.7

0

−

40

tconv

Conversion time 10-bit mode

8-bit mode

φAD = 10 MHz, Vref = AVCC = 5.0 V

−

µs

−

µs

V^ref

V^IA

−

Reference voltage

Analog input voltage⁽²⁾

−

AVCC

10

V

−

V

A/D operating

clock frequency

Without sample and hold

With sample and hold

0.25

1

−

MHz

−

10

NOTES:

1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

P0

P1

30pF

P3

P4

P5

Figure 5.20

Ports P0, P1, and P3 to P5 Timing Measurement Circuit

Rev.2.10 Sep 26, 2008 Page 50 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.37

Flash Memory (Program ROM) Electrical Characteristics

Standard

Unit

Symbol

Parameter

Conditions

R8C/26 Group

Min.

100⁽³⁾

Typ.

−

Max.

−

Program/erase endurance⁽²⁾

−

times

µs

1,000⁽³⁾

R8C/27 Group

−

Byte program time

Block erase time

−

50

0.4

−

400

9

−

s

t^d(SR-SUS)

Time delay from suspend request until

suspend

97 + CPU clock

× 6 cycles

µs

−

Interval from erase start/restart until

following suspend request

650

0

−

µs

ns

µs

Interval from program start/restart until

following suspend request

−

Time from suspend until program/erase

restart

−

3 + CPU clock

× 4 cycles

−

Program, erase voltage

Read voltage

2.7

0

−

5.5

60

−

V

Program, erase temperature

Data hold time⁽⁷⁾

°C

Ambient temperature = 55°C

20

year

NOTES:

1. V^CC= 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024

1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

Rev.2.10 Sep 26, 2008 Page 51 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(4)

Table 5.38

Flash Memory (Data flash Block A, Block B) Electrical Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

10,000⁽³⁾

−

Typ.

−

Max.

−

Program/erase endurance⁽²⁾

−

times

Byte program time

50

400

µs

(program/erase endurance ≤ 1,000 times)

−

Byte program time

(program/erase endurance > 1,000 times)

−

65

0.2

0.3

−

9

−

µs

s

−

Block erase time

(program/erase endurance ≤ 1,000 times)

−

Block erase time

(program/erase endurance > 1,000 times)

−

s

t^d(SR-SUS)

Time delay from suspend request until

suspend

−

97 + CPU clock

× 6 cycles

µs

ns

µs

−

Interval from erase start/restart until

following suspend request

650

0

−

Interval from program start/restart until

following suspend request

−

Time from suspend until program/erase

restart

−

3 + CPU clock

× 4 cycles

−

Program, erase voltage

Read voltage

2.7

-40

20

−

5.5

85⁽⁸⁾

−

V

Program, erase temperature

°C

Data hold time⁽⁹⁾

Ambient temperature = 55°C

year

NOTES:

1. V^CC= 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times

is the same as that in program ROM.

5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further

reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the

number of erase operations to a certain number.

6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

8. 125°C for K version.

9. The data hold time includes time that the power supply is off or the clock is not supplied.

Rev.2.10 Sep 26, 2008 Page 52 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Suspend request

(maskable interrupt request)

FMR46

Clock-dependent

time

Fixed time

Access restart

td(SR-SUS)

Figure 5.21

Time delay until Suspend

Table 5.39

Voltage Detection 1 Circuit Electrical Characteristics

Standard

Symbol

Parameter

Voltage detection level^{(2, 4)}

Voltage monitor 1 reset generation time⁽⁵⁾

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts⁽³⁾

Condition

Unit

Min.

Typ.

2.85

40

Max.

3.0

200

−

V^det1

t^d(Vdet1-A)

−

2.70

V

−

µs

µA

µs

VCA26 = 1, VCC = 5.0 V

0.6

−

t^d(E-A)

100

Vccmin

MCU operating voltage minimum value

2.70

−

V

NOTES:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).

2. Hold V^det2> Vdet1.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

register to 0.

4. This parameter shows the voltage detection level when the power supply drops.

The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply

drops by approximately 0.1 V.

5. Time until the voltage monitor 1 reset is generated after the voltage passes V^det1when VCC falls. When using the digital filter,

its sampling time is added to t^d(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the

voltage passes V^det1when the power supply falls.

Table 5.40

Voltage Detection 2 Circuit Electrical Characteristics

Standard

Typ.

Symbol

V^det2

Parameter

Voltage detection level⁽²⁾

Condition

Unit

Min.

3.3

−

Max.

3.9

3.6

V

t^d(Vdet2-A)

Voltage monitor 2 reset/interrupt request generation

time^{(3, 5)}

40

200

µs

−

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts⁽⁴⁾

VCA27 = 1, VCC = 5.0 V

−

0.6

−

µA

µs

t^d(E-A)

−

100

NOTES:

1. The measurement condition is V^CC= 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).

2. Hold V^det2> Vdet1.

3. Time until the voltage monitor 2 reset/interrupt request is generated after the voltage passes V^det2.

4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

register to 0.

5. When using the digital filter, its sampling time is added to t^d(Vdet2-A). When using the voltage monitor 2 reset, maintain this time

until V^CC= 2.0 V after the voltage passes Vdet2 when the power supply falls.

Rev.2.10 Sep 26, 2008 Page 53 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(3)

Table 5.41

Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

−

Typ.

−

Max.

0.1

Power-on reset valid voltage⁽⁴⁾

V^por1

V^por2

V

Power-on reset or voltage monitor 1 reset valid

voltage

0

−

Vdet1

20⁽²⁾

t^rth

External power VCC rise gradient

VCC ≤ 3.6 V

V^CC> 3.6 V

−

mV/msec

2,000 mV/msec

NOTES:

1. The measurement condition is T^opr= -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V.

3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the

VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.

4. t^w(por1)indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain t^w(por1)for 30 s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for

3,000 s or more if -40°C ≤ Topr < -20°C.

(3)

Vdet1

trth

2.0 V

External

power VCC

td(Vdet1-A)

Vpor2

Vpor1

tw(por1)

Sampling time^{(1, 2)}

Internal reset

signal

(“L” valid)

1

× 32

fOCO-S

NOTES:

1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.

2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.

3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection

Circuit of Hardware Manual for details.

Figure 5.22

Reset Circuit Electrical Characteristics

Rev.2.10 Sep 26, 2008 Page 54 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.42

High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

39.2

Typ.

40

Max.

40.8

fOCO40M

High-speed on-chip oscillator frequency

temperature · supply voltage dependence

V^CC= 4.75 to 5.25 V

0°C ≤ Topr ≤ 60°C⁽²⁾

V^CC= 3.0 to 5.5 V

MHz

38.8

38.4

38

40

41.2

41.6

42

-20°C ≤ Topr ≤ 85°C⁽²⁾

V^CC= 3.0 to 5.5 V

-40°C ≤ Topr ≤ 85°C⁽²⁾

V^CC= 3.0 to 5.5 V

-40°C ≤ Topr ≤ 125°C⁽²⁾

V^CC= 2.7 to 5.5 V

37.6

42.4

-40°C ≤ Topr ≤ 125°C⁽²⁾

−

Value in FRA1 register after reset

08h

−

F7h

−

Oscillation frequency adjustment unit of high-

speed on-chip oscillator

Adjust FRA1 register

(value after reset) to -1

−

+0.3

−

MHz

−

Oscillation stability time

−

10

100

µs

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°C

400

−

µA

NOTES:

1. V^CC= 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. These standard values show when the FRA1 register value after reset is assumed.

Table 5.43

Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Typ.

125

Symbol

fOCO-S

Parameter

Condition

Unit

Min.

40

−

Max.

250

100

−

Low-speed on-chip oscillator frequency

Oscillation stability time

kHz

µs

−

10

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°C

−

15

µA

NOTE:

1. V^CC= 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

Table 5.44

Power Supply Circuit Timing Characteristics

Standard

Symbol

t^d(P-R)

Parameter

Condition

Unit

Min.

1

Typ.

Max.

2000

Time for internal power supply stabilization during

power-on⁽²⁾

−

µs

STOP exit time⁽³⁾

t^d(R-S)

−

150

µs

NOTES:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.

Rev.2.10 Sep 26, 2008 Page 55 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

(1)

Table 5.45

Timing Requirements of Clock Synchronous Serial I/O with Chip Select

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

−

Max.

−

(2)

tCYC

t^SUCYC

SSCK clock cycle time

SSCK clock “H” width

SSCK clock “L” width

4

tHI

0.4

−

0.6

1

tSUCYC

tLO

0.4

−

(2)

tRISE

SSCK clock rising

time

Master

Slave

−

t^CYC

−

1

µs

(2)

t^FALL

SSCK clock falling

time

Master

Slave

−

1

t^CYC

−

100

−

1

µs

t^SU

SSO, SSI data input setup time

SSO, SSI data input hold time

−

ns

(2)

t^H

1

−

tCYC

tLEAD

Slave

1t^CYC+ 50

−

ns

SCS setup time

SCS hold time

t^LAG

1t^CYC+ 50

−

(2)

t^OD

tSA

t^OR

SSO, SSI data output delay time

SSI slave access time

−

1

t^CYC

1.5tCYC + 100

ns

SSI slave out open time

NOTES:

1. V^CC= 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. 1tCYC = 1/f1(s)

Rev.2.10 Sep 26, 2008 Page 56 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

SCS (output)

VIH or VOH

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

4-Wire Bus Communication Mode, Master, CPHS = 0

VIH or VOH

SCS (output)

VIH or VOH

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

CPHS, CPOS: Bits in SSMR register

Figure 5.23

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)

Rev.2.10 Sep 26, 2008 Page 57 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

SCS (input)

VIH or VOH

tLEAD

tHI

tFALL

tRISE

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

4-Wire Bus Communication Mode, Slave, CPHS = 0

VIH or VOH

SCS (input)

VIH or VOH

tHI

tFALL

tRISE

tLEAD

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

CPHS, CPOS: Bits in SSMR register

Figure 5.24

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)

Rev.2.10 Sep 26, 2008 Page 58 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

tHI

VIH or VOH

SSCK

SSO (output)

SSI (input)

tLO

tSUCYC

tOD

tSU

tH

Figure 5.25

I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous

Communication Mode)

Rev.2.10 Sep 26, 2008 Page 59 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

2

(1)

Table 5.46

Timing Requirements of I C bus Interface

Standard

Unit

Symbol

Parameter

SCL input cycle time

Condition

Min.

12t^CYC+ 600⁽²⁾

3t^CYC+ 300⁽²⁾

5t^CYC+ 500⁽²⁾

−

Typ.

−

Max.

−

t^SCL

ns

t^SCLH

t^SCLL

t^sf

SCL input “H” width

−

SCL input “L” width

−

SCL, SDA input fall time

−

300

(2)

t^SP

SCL, SDA input spike pulse rejection time

SDA input bus-free time

−

1tCYC

(2)

t^BUF

t^STAH

t^STAS

t^STOP

t^SDAS

t^SDAH

−

5t^CYC

(2)

Start condition input hold time

Retransmit start condition input setup time

Stop condition input setup time

Data input setup time

−

3t^CYC

(2)

−

3t^CYC

(2)

−

3t^CYC

1t^CYC+ 20⁽²⁾

0

−

Data input hold time

−

NOTES:

1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.

2. 1t^CYC= 1/f1(s)

VIH

SDA

VIL

tBUF

tSTAH

tSP

tSTOP

tSCLH

tSTAS

SCL

P⁽²⁾

S⁽¹⁾

tsf

Sr⁽³⁾

P⁽²⁾

tSCLL

tsr

tSDAS

tSCL

tSDAH

NOTES:

1. Start condition

2. Stop condition

3. Retransmit start condition

2

Figure 5.26

I/O Timing of I C bus Interface

Rev.2.10 Sep 26, 2008 Page 60 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.47

Electrical Characteristics (1) [VCC = 5 V]

Standard

Unit

Symbol

Parameter

Condition

Min.

Typ.

−

Max.

VCC

2.0

V^OH

Output “H” voltage Except XOUT

IOH = -5 mA

VCC - 2.0

VCC - 0.3

VCC - 2.0

V

I^OH= -200 µA

−

XOUT

Output “L” voltage Except XOUT

XOUT

Drive capacity HIGH I^OH= -1 mA

−

Drive capacity LOW I^OH= -500 µA VCC - 2.0

−

V^OL

IOL = 5 mA

−

I^OL= 200 µA

−

0.45

2.0

Drive capacity HIGH I^OL= 1 mA

Drive capacity LOW I^OL= 500 µA

−

2.0

V^T+-VT-

Hysteresis

0.1

0.5

−

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, RXD0, RXD1,

CLK0, CLK1,

SSI, SCL, SDA, SSO

0.1

1.0

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 5 V, VCC = 5V

VI = 0 V, VCC = 5V

−

5.0

-5.0

167

−

µA

R^PULLUPPull-up resistance

30

−

50

1.0

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

VRAM

RAM hold voltage

During stop mode

2.0

−

V

NOTE:

1. V^CC= 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.

Rev.2.10 Sep 26, 2008 Page 61 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.48

Electrical Characteristics (2) [Vcc = 5 V]

(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

10

Max.

17

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

I^CC

−

(V^CC= 3.3 to 5.5 V)

Single-chip mode,

output pins are open,

other pins are V^SS

clock mode

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

9

6

15

−

mA

µA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

5

−

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

4

−

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

2.5

10

4

−

XIN clock off

High-speed

on-chip

oscillator

mode

15

−

High-speed on-chip oscillator on fOCO = 20 MHz (J version)

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO = 20 MHz (J version)

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

5.5

2.5

130

10

−

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

Low-speed

on-chip

oscillator

mode

300

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

XIN clock off

Wait mode

−

25

23

75

60

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Stop mode

−

0.8

1.2

4.0

3.0

−

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 125°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

Rev.2.10 Sep 26, 2008 Page 62 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]

Table 5.49

XIN Input

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(XIN)

XIN input cycle time

XIN input “H” width

XIN input “L” width

50

25

−

ns

t^WH(XIN)

t^WL(XIN)

VCC = 5 V

tC(XIN)

tWH(XIN)

XIN input

tWL(XIN)

Figure 5.27

XIN Input Timing Diagram when VCC = 5 V

Table 5.50

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

100

40

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

40

tC(TRAIO)

VCC = 5 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.28

TRAIO Input Timing Diagram when VCC = 5 V

Rev.2.10 Sep 26, 2008 Page 63 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.51

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

200

100

−

ns

t^W(CKH)

t^W(CKL)

t^d(C-Q)

t^h(C-Q)

t^su(D-C)

t^h(C-D)

−

50

−

0

RXDi input setup time

RXDi input hold time

50

90

−

i = 0 or 1

VCC = 5 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 or 1

Figure 5.29

Serial Interface Timing Diagram when VCC = 5 V

Table 5.52

External Interrupt INTi (i = 0, 1, 3) Input

Standard

Symbol

Parameter

Unit

Min.

Max.

250⁽¹⁾

250⁽²⁾

t^W(INH)

t^W(INL)

−

ns

INTi input “H” width

INTi input “L” width

−

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 5 V

tW(INL)

INTi input

tW(INH)

i = 0, 1, 3

Figure 5.30

External Interrupt INTi Input Timing Diagram when VCC = 5 V

Rev.2.10 Sep 26, 2008 Page 64 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.53

Electrical Characteristics (3) [VCC = 3 V]

Standard

Unit

Symbol

Parameter

Output “H” voltage Except XOUT

Condition

Min.

Typ.

−

Max.

VCC

V^OH

IOH = -1 mA

VCC - 0.5

V

XOUT

Drive capacity

HIGH

I^OH= -0.1 mA VCC - 0.5

−

Drive capacity

LOW

I^OH= -50 µA

VCC - 0.5

−

VCC

V

VOL

Output “L” voltage

Hysteresis

Except XOUT

XOUT

IOL = 1 mA

−

0.5

V

Drive capacity

HIGH

I^OL= 0.1 mA

Drive capacity

LOW

I^OL= 50 µA

−

0.5

V

V^T+-VT-

0.1

0.3

−

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, RXD0, RXD1,

CLK0,CLK1,

SSI, SCL, SDA, SSO

0.1

0.4

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 3 V, VCC = 3V

VI = 0 V, VCC = 3V

−

4.0

-4.0

500

−

µA

kΩ

MΩ

V

R^PULLUPPull-up resistance

66

−

160

3.0

−

RfXIN

VRAM

Feedback resistance XIN

RAM hold voltage

During stop mode

2.0

−

NOTE:

1. V^CC= 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.

Rev.2.10 Sep 26, 2008 Page 65 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.54

Electrical Characteristics (4) [Vcc = 3 V]

(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

6

Max.

I^CC

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

(V^CC= 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are V^SS

clock mode

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

2

5

−

9

mA

µA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

2

−

High-speed on-chip oscillator on fOCO = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed

on-chip

oscillator

mode

XIN clock off

130

25

300

70

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

Wait mode

XIN clock off

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

23

55

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode

XIN clock off, T^opr= 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

0.7

1.1

3.8

3.0

µA

XIN clock off, T^opr= 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

XIN clock off, T^opr= 125°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

Rev.2.10 Sep 26, 2008 Page 66 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]

Table 5.55

XIN Input

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(XIN)

XIN input cycle time

XIN input “H” width

XIN input “L” width

100

40

−

ns

t^WH(XIN)

t^WL(XIN)

40

tC(XIN)

VCC = 3 V

tWH(XIN)

XIN input

tWL(XIN)

Figure 5.31

XIN Input Timing Diagram when VCC = 3 V

Table 5.56

TRAIO Input

Standard

Symbol

Parameter

Unit

Min.

300

120

Max.

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

VCC = 3 V

tC(TRAIO)

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.32

TRAIO Input Timing Diagram when VCC = 3 V

Rev.2.10 Sep 26, 2008 Page 67 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

5. Electrical Characteristics

Table 5.57

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

Max.

t^c(CK)

CLKi input cycle time

CLKi input “H” width

CLKi Input “L” width

TXDi output delay time

TXDi hold time

300

150

−

ns

t^W(CKH)

t^W(CKL)

t^d(C-Q)

t^h(C-Q)

t^su(D-C)

t^h(C-D)

−

80

−

0

RXDi input setup time

RXDi input hold time

70

90

−

i = 0 or 1

tC(CK)

VCC = 3 V

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 or 1

Figure 5.33

Serial Interface Timing Diagram when VCC = 3 V

Table 5.58

External Interrupt INTi (i = 0, 1, 3) Input

Standard

Min. Max.

Symbol

Parameter

Unit

380⁽¹⁾

380⁽²⁾

t^W(INH)

t^W(INL)

−

ns

INTi input “H” width

INTi input “L” width

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 3 V

tW(INL)

INTi input

tW(INH)

i = 0, 1, 3

Figure 5.34

External Interrupt INTi Input Timing Diagram when VCC = 3 V

Rev.2.10 Sep 26, 2008 Page 68 of 69

REJ03B0168-0210

R8C/26 Group, R8C/27 Group

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Technology website.

JEITA Package Code

P-LQFP32-7x7-0.80

RENESAS Code

PLQP0032GB-A

Previous Code

32P6U-A

MASS[Typ.]

0.2g

H_D

*1

D

24

17

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

16

25

bp

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

6.9 7.0 7.1

1.4

Terminal cross section

32

9

A₂

H_D

H_E

A

8.8 9.0 9.2

1.7

1

8

Z_D

Index mark

A₁

b_p

b₁

c

0.1 0.2

0

0.32 0.37 0.42

0.35

F

c

0.09

0.20

0.145

0.125

c₁

L

L₁

0°

8°

e

0.8

Detail F

y

x

0.20

0.10

*3

b_p

x

e

y

Z_D

Z_E

L

0.7

0.3 0.5 0.7

1.0

L₁

Rev.2.10 Sep 26, 2008 Page 69 of 69

REJ03B0168-0210

REVISION HISTORY

R8C/26 Group, R8C/27 Group Datasheet

Description

Summary

Rev.

Date

Page

0.10

0.20

Nov 14, 2005

Feb 06, 2006

−

First edition issued

2, 3

Table 1.1 Functions and Specifications for R8C/26Group and Table 1.2

Functions and Specifications for R8C/27 Group;

Minimum instruction execution time and Supply voltage revised

9

Table 1.6 Pin Name Information by Pin Number;

“XOUT” → “XOUT/XCOUT” and “XIN” → “XIN/XCIN” revised

18

19

Table 4.4 SFR Information (4);

00FEh: “DRR” → “P1DRR” revised

Table 4.5 SFR Information (5);

-0119h: “Timer RE Minute Data Register / Compare Register” →

“Timer RE Minute Data Register / Compare Data Register”

-011Ah: “Timer RE Time Data Register” →

“Timer RE Hour Data Register”

-011Bh: “Timer RE Day Data Register” →

“Timer RE Day of Week Data Register” revised

22 to 45 5. Electrical Characteristics added

Nov 08, 2006 All pages “Preliminary” deleted

1.00

2

3

Table 1.1 revised

Table 1.2 revised

Figure 1.1 revised

Table 1.3 revised

Table 1.4 revised

Figure 1.4 revised

Table 1.6 revised

4

5

6

7

9

15

Table 4.1;

• 001Ch: “00h” → “00h, 10000000b” revised

• 000Fh: “000XXXXXb” → “00X11111b” revised

• 0029h: “High-Speed On-Chip Oscillator Control Register 4, FRA4,

When shipping” added

• 002Bh: “High-Speed On-Chip Oscillator Control Register 6, FRA6,

When shipping” added

• 0032h: “00h, 01000000b” → “00h, 00100000b” revised

• 0038h: “00001000b, 01001001b” → “0000X000b, 0100X001b” revised

• NOTE3 and 4 revised; NOTE6 added

18

Table 4.4;

• 00E0h, 00E1h, 00E5h, 00E8h, 00E9h: “XXh” → “00h” revised

• 00FDh: “XX00000000b” → “00h” revised

22

23

24

25

26

Table 5.2 revised

Figure 5.1 title revised

Table 5.4 revised

Table 5.5 revised

Figure 5.2 title revised and Table 5.7 NOTE4 added

A - 1

REVISION HISTORY

R8C/26 Group, R8C/27 Group Datasheet

Description

Summary

Rev.

1.00

Date

Page

Nov 08, 2006

27

28

34

35

36

39

40

44

47

Table 5.9, Figure 5.3 revised and Table 5.10 deleted

Table 5.10, Table 5.11 revised

Table 5.15 revised

Table 5.16 revised

Table 5.17 revised

Table 5.22 revised

Table 5.23 revised

Table 5.29 revised

Package Dimensions; “Diagrams showing the latest...website.” added

1.10

Nov 29, 2006 All pages “J, K version” added

1

1 “J and K versions are under development...notice.” added

1.1 revised

2

3

Table 1.1 revised

Table 1.2 revised

4

Figure 1.1 NOTE3 added

Table 1.3, Figure 1.2 revised

Table 1.4, Figure 1.3 revised

Figure 1.4 NOTE3 added

Table 1.5 revised

5

6

7

8

9

Table 1.6 NOTE2 added

Figure 3.1 revised

13

14

15

Figure 3.2 revised

Table 4.1; “0000h to 003Fh” → “0000h to 002Fh” revised

• NOTE3 added

16

Table 4.2; “0040h to 007Fh” → “0030h to 007Fh” revised

• 0032h, 0036h: “After reset” is revised

• 0038h: NOTE revised

• NOTES 2, 5, 6 revised and NOTE 7, 8 added

19

28

Table 4.5 NOTE2 added

Table 5.10 revised

48 to 66 5.2 J, K Version added

1.20

1.30

Jan 17, 2007

May 25, 2007

18

2

Table 4.4 NOTE2 added

Table 1.1 revised

3

Table 1.2 revised

5

Table 1.3 revised

6

Figure 1.2 revised

7

Table 1.4 revised

8

Figure 1.3 revised

9

Figure 1.4 NOTE4 added

Figure 3.1 part number revised

15

A - 2

REVISION HISTORY

R8C/26 Group, R8C/27 Group Datasheet

Description

Summary

Rev.

1.30

Date

Page

May 25, 2007

16

30

Figure 3.2 part number revised

Table 5.10 revised

53

Table 5.39 NOTE4 added

Table 5.42 revised

55

1.40a

2.00

Jun 14, 2007

Mar 01, 2008

5, 7

Table 1.3 and Table 1.4 revised

1, 49 1.1, 5.2 “J and K versions are ...” deleted

5, 7

11

Table 1.3, Table 1.4 revised

Table 1.6 NOTE3 added

15, 16 Figure 3.1, Figure 3.2; “Expanded area” deleted

17

18

Table 4.1 “002Ch” added

Table 4.2 “0036h”; J, K version “0100X000b” → “0100X001b”

24, 49 Table 5.2, Table 5.35; NOTE2 revised

30

Table 5.10 revised, NOTE4 added

2.10

Sep 26, 2008

−

“RENESAS TECHNICAL UP DATE” reflected: TN-16C-A172A/E

26, 51 Table 5.4, Table 5.37 NOTE2, NOTE4 revised

27, 52 Table 5.5, Table 5.38 NOTE2, NOTE5 revised

53

Table 5.39 Parameter: Voltage monitor 1 reset generation time added

NOTE5 added

Table 5.40 revised

54

Table 5.41 revised

Figure 5.22 revised

All trademarks and registered trademarks are the property of their respective owners.

A - 3

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Notes:

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes

warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property

rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,

but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass

destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws

and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this

document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,

please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be

disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a

result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability

of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular

application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications

or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898

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7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2377-3473

Renesas Technology Taiwan Co., Ltd.

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Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

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Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon .7.2


型号：	R5F21266SDFP#U0
厂家：	RENESAS TECHNOLOGY CORP
描述：	R8C Series, 26 Group, WDTO, RTC 32P6U-A; Vcc= 2.2 to 5.5 volts, Temp= -40 to 85 C; Package: PLQP0032GB-A 时钟外围集成电路
文件：	总75页 (文件大小：602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F21266SDFP#U0 [RENESAS]

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