R5F21321DDSP [RENESAS]

RENESAS MCU; 瑞萨MCU
R5F21321DDSP
型号: R5F21321DDSP
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

RENESAS MCU
瑞萨MCU

微控制器和处理器 外围集成电路 光电二极管 时钟
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中文:  中文翻译
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To our customers,  
Old Company Name in Catalogs and Other Documents  
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology  
Corporation, and Renesas Electronics Corporation took over all the business of both  
companies. Therefore, although the old company name remains in this document, it is a valid  
Renesas Electronics document. We appreciate your understanding.  
Renesas Electronics website: http://www.renesas.com  
April 1st, 2010  
Renesas Electronics Corporation  
Issued by: Renesas Electronics Corporation (http://www.renesas.com)  
Send any inquiries to http://www.renesas.com/inquiry.  
Notice  
1.  
2.  
All information included in this document is current as of the date this document is issued. Such information, however, is  
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please  
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to  
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3.  
4.  
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.  
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of  
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,  
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by  
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5.  
When exporting the products or technology described in this document, you should comply with the applicable export control  
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7.  
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics  
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“Standard”:  
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual  
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.  
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-  
crime systems; safety equipment; and medical equipment not specifically designed for life support.  
“Specific”:  
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or  
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9.  
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,  
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-  
owned subsidiaries.  
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.  
R8C/32D Group  
REJ03B0288-0100  
Rev.1.00  
Feb 26, 2010  
RENESAS MCU  
1. Overview  
1.1  
Features  
The R8C/32D Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions  
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high  
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.  
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are  
designed to maximize EMI/EMS performance.  
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of  
system components.  
1.1.1  
Applications  
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 1 of 42  
R8C/32D Group  
1.Overview  
1.1.2  
Specifications  
Tables 1.1 and 1.2 outline the Specifications for R8C/32D Group.  
Table 1.1  
Specifications for R8C/32D Group (1)  
Item  
CPU  
Function  
Central processing R8C CPU core  
Specification  
unit  
• Number of fundamental instructions: 89  
• Minimum instruction execution time:  
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)  
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)  
• Multiplier: 16 bits × 16 bits 32 bits  
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits  
• Operation mode: Single-chip mode (address space: 1 Mbyte)  
Refer to Table 1.3 Product List for R8C/32D Group.  
• Power-on reset  
Memory ROM, RAM  
Power Supply Voltage detection  
Voltage  
Detection  
I/O Ports  
circuit  
• Voltage detection 3 (detection level of voltage detection 0 and voltage  
detection 1 selectable)  
Programmable I/O • Input-only: 1 pin  
ports  
• CMOS I/O ports: 15, selectable pull-up resistor  
• High current drive ports: 15  
4 circuits: XIN clock oscillation circuit,  
Clock  
Clock generation  
circuits  
XCIN clock oscillation circuit (32 kHz)  
High-speed on-chip oscillator (with frequency adjustment function),  
Low-speed on-chip oscillator,  
• Oscillation stop detection: XIN clock oscillation stop detection function  
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16  
• Low power consumption modes:  
Standard operating mode (high-speed clock, low-speed clock, high-speed  
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode  
Real-time clock (timer RE)  
Interrupts  
• Number of interrupt vectors: 69  
• External Interrupt: 7 (INT × 3, Key input × 4)  
• Priority levels: 7 levels  
• 14 bits × 1 (with prescaler)  
Watchdog Timer  
• Reset start selectable  
• Low-speed on-chip oscillator for watchdog timer selectable  
Timer  
Timer RA  
Timer RB  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), pulse output mode (output level inverted every  
period), event counter mode, pulse width measurement mode, pulse period  
measurement mode  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), programmable waveform generation mode (PWM  
output), programmable one-shot generation mode, programmable wait one-  
shot generation mode  
16 bits × 1 (with 4 capture/compare registers)  
Timer mode (input capture function, output compare function), PWM mode  
(output 3 pins), PWM2 mode (PWM output pin)  
Timer RC  
Timer RE  
8 bits × 1  
Real-time clock mode (count seconds, minutes, hours, days of week)  
Serial  
Interface  
UART0  
UART2  
Clock synchronous serial I/O/UART  
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),  
multiprocessor communication function  
A/D Converter  
Comparator B  
10-bit resolution × 4 channels, includes sample and hold function, with sweep  
mode  
2 circuits  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 2 of 42  
 
R8C/32D Group  
1.Overview  
Table 1.2  
Specifications for R8C/32D Group (2)  
Item  
Flash Memory  
Function  
Specification  
• Programming and erasure voltage: VCC = 2.7 to 5.5 V  
• Programming and erasure endurance: 1,000 times (program ROM)  
• Program security: ROM code protect, ID code check  
• Debug functions: On-chip debug, on-board flash rewrite function  
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)  
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)  
Operating Frequency/Supply  
Voltage  
Current consumption  
Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)  
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)  
Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))  
Typ. 2.0 µA (VCC = 3.0 V, stop mode)  
Operating Ambient Temperature  
Package  
-20 to 85°C (N version)  
-40 to 85°C (D version) (1)  
20-pin LSSOP  
Package code: PLSP0020JB-A (previous code: 20P2F-A)  
Note:  
1. Specify the D version if D version functions are to be used.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 3 of 42  
 
R8C/32D Group  
1.Overview  
1.2  
Product List  
Table 1.3 lists Product List for R8C/32D Group, and Figure 1.1 shows a Part Number, Memory Size, and Package  
of R8C/32D Group.  
Table 1.3  
Product List for R8C/32D Group  
Current of Feb. 2010  
Part No.  
ROM Capacity  
4 Kbytes  
RAM Capacity  
1 Kbyte  
Package Type  
PLSP0020JB-A  
PLSP0020JB-A  
PLSP0020JB-A  
PLSP0020JB-A  
PLSP0020JB-A  
PLSP0020JB-A  
Remarks  
N version  
R5F21321DNSP  
R5F21322DNSP  
8 Kbytes  
1 Kbyte  
R5F21324DNSP  
16 Kbytes  
4 Kbytes  
1 Kbyte  
R5F21321DDSP (D)  
R5F21322DDSP (D)  
R5F21324DDSP (D)  
1 Kbyte  
D version  
8 Kbytes  
1 Kbyte  
16 Kbytes  
1 Kbyte  
(D): Under development  
Part No. R 5 F 21 32 4 D N SP  
Package type:  
SP: PLSP0020JB-A (0.65 mm pin-pitch)  
Classification  
N: Operating ambient temperature -20°C to 85°C  
D: Operating ambient temperature -40°C to 85°C  
ROM capacity  
1: 4 KB  
2: 8 KB  
4: 16 KB  
R8C/32D Group  
R8C/3x Series  
Memory type  
F: Flash memory  
Renesas MCU  
Renesas semiconductor  
Figure 1.1  
Part Number, Memory Size, and Package of R8C/32D Group  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 4 of 42  
 
 
R8C/32D Group  
1.Overview  
1.3  
Block Diagram  
Figure 1.2 shows a Block Diagram.  
8
3
1
4
Port P1  
I/O ports  
Peripheral functions  
Port P3  
Port P4  
UART or  
clock synchronous serial I/O  
Timers  
System clock generation  
circuit  
(8 bits × 2)  
Timer RA (8 bits × 1)  
Timer RB (8 bits × 1)  
Timer RC (16 bits × 1)  
Timer RE (8 bits × 1)  
XIN-XOUT  
High-speed on-chip oscillator  
Low-speed on-chip oscillator  
XCIN-XCOUT  
Watchdog timer  
(14 bits)  
Low-speed on-chip oscillator  
for watchdog timer  
A/D converter  
Voltage detection circuit  
Comparator B  
(10 bits × 4 channels)  
Memory  
R8C CPU core  
ROM (1)  
R0H  
R1H  
R0L  
R1L  
SB  
USP  
ISP  
INTB  
PC  
FLG  
R2  
R3  
RAM (2)  
A0  
A1  
FB  
Multiplier  
Notes:  
1. ROM size varies with MCU type.  
2. RAM size varies with MCU type.  
Figure 1.2  
Block Diagram  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 5 of 42  
 
R8C/32D Group  
1.Overview  
1.4  
Pin Assignment  
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
P1_0/AN8/KI0(/TRCIOD)  
P4_2/VREF  
MODE  
1
P1_1/AN9/KI1(/TRCIOA/TRCTRG)  
P1_2/AN10/Kl2(/TRCIOB)  
P1_3/AN11/Kl3/TRBO(/TRCIOC)  
P1_4(/TXD0/TRCCLK)  
2
3
RESET  
P4_7/XOUT(/XCOUT)  
4
5
VSS/AVSS  
P1_5(/INT1/RXD0/TRAIO)  
P1_6/IVREF1(/CLK0)  
6
P4_6/XIN(/XCIN)  
7
VCC/AVCC  
P1_7/IVCMP1/INT1(/TRAIO)  
P4_5/ADTRG/INT0(/RXD2/SCL2)  
8
P3_7/TRAO(/RXD2/SCL2/TXD2/SDA2)  
P3_5(/CLK2/TRCIOD)  
9
P3_4/IVREF3(/RXD2/SCL2/TXD2/SDA2/TRCIOC)  
P3_3/IVCMP3/INT3(/CTS2/RTS2/TRCCLK)  
10  
Notes:  
1. Can be assigned to the pin in parentheses by a program.  
2. Confirm the pin 1 position on the package by referring to the package dimensions.  
Figure 1.3  
Pin Assignment (Top View)  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 6 of 42  
 
R8C/32D Group  
1.Overview  
Table 1.4  
Pin Name Information by Pin Number  
I/O Pin Functions for Peripheral Modules  
Pin  
Number  
Control Pin  
Port  
A/D Converter,  
Comparator B  
VREF  
Interrupt  
Timer  
Serial Interface  
1
2
3
P4_2  
MODE  
RESET  
4
5
6
7
8
XOUT(/XCOUT)  
VSS/AVSS  
P4_7  
P4_6  
P3_7  
XIN(/XCIN)  
VCC/AVCC  
TRAO  
(RXD2/SCL2/  
TXD2/SDA2)  
9
P3_5  
P3_4  
(TRCIOD)  
(TRCIOC)  
(CLK2)  
10  
(RXD2/SCL2/  
TXD2/SDA2)  
IVREF3  
IVCMP3  
11  
12  
13  
P3_3  
P4_5  
P1_7  
(TRCCLK)  
INT3  
INT0  
INT1  
(CTS2/RTS2)  
(RXD2/SCL2)  
ADTRG  
IVCMP1  
(TRAIO)  
(TRAIO)  
14  
15  
P1_6  
P1_5  
(CLK0)  
(RXD0)  
IVREF1  
(INT1)  
16  
17  
P1_4  
P1_3  
(TRCCLK)  
(TXD0)  
TRBO(/TRCIOC)  
AN11  
AN10  
AN9  
KI3  
KI2  
KI1  
KI0  
18  
19  
20  
P1_2  
P1_1  
P1_0  
(TRCIOB)  
(TRCIOA/TRCTRG)  
(TRCIOD)  
AN8  
Note:  
1. Can be assigned to the pin in parentheses by a program.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 7 of 42  
R8C/32D Group  
1.Overview  
1.5  
Pin Functions  
Table 1.5 lists Pin Functions.  
Table 1.5  
Item  
Power supply input VCC, VSS  
Pin Functions  
Pin Name  
I/O Type  
Description  
Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.  
Analog power  
supply input  
AVCC, AVSS  
Power supply for the A/D converter.  
Connect a capacitor between AVCC and AVSS.  
Reset input  
MODE  
RESET  
MODE  
XIN  
I
I
I
Input “L” on this pin resets the MCU.  
Connect this pin to VCC via a resistor.  
XIN clock input  
These pins are provided for XIN clock generation circuit I/O.  
Connect a ceramic resonator or a crystal oscillator between  
the XIN and XOUT pins (1). To use an external clock, input it  
to the XOUT pin and leave the XIN pin open.  
XIN clock output  
XCIN clock input  
XOUT  
XCIN  
I/O  
I
These pins are provided for XCIN clock generation circuit I/O.  
Connect a crystal oscillator between the XCIN and XCOUT  
pins (1). To use an external clock, input it to the XCIN pin and  
leave the XCOUT pin open.  
XCIN clock output XCOUT  
O
INT interrupt input INT0, INT1, INT3  
I
I
INT interrupt input pins.  
INT0 is timer RB, and RC input pin.  
Key input interrupt  
Timer RA  
Key input interrupt input pins  
KI0 to KI3  
TRAIO  
I/O  
O
O
I
Timer RA I/O pin  
TRAO  
Timer RA output pin  
Timer RB output pin  
External clock input pin  
External trigger input pin  
Timer RC I/O pins  
Timer RB  
Timer RC  
TRBO  
TRCCLK  
TRCTRG  
I
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD  
I/O  
Serial interface  
CLK0, CLK2  
RXD0, RXD2  
TXD0, TXD2  
I/O  
Transfer clock I/O pins  
Serial data input pins  
I
O
I
Serial data output pins  
Transmission control input pin  
CTS2  
O
I/O  
I/O  
I
Reception control output pin  
RTS2  
SCL2  
SDA2  
I2C mode clock I/O pin  
I2C mode data I/O pin  
Reference voltage VREF  
input  
Reference voltage input pin to A/D converter  
A/D converter  
AN8 to AN11  
I
I
Analog input pins to A/D converter  
A/D external trigger input pin  
ADTRG  
Comparator B  
I/O port  
IVCMP1, IVCMP3  
IVREF1, IVREF3  
I
I
Comparator B analog voltage input pins  
Comparator B reference voltage input pins  
P1_0 to P1_7,  
P3_3 to P3_5, P3_7,  
P4_5 to P4_7  
I/O  
CMOS I/O ports. Each port has an I/O select direction  
register, allowing each pin in the port to be directed for input  
or output individually.  
Any port set to input can be set to use a pull-up resistor or not  
by a program.  
All ports can be used as LED drive ports.  
Input port  
P4_2  
I
Input-only port  
I: Input  
Note:  
O: Output  
I/O: Input and output  
1. Refer to the oscillator manufacturer for oscillation characteristics.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 8 of 42  
 
 
R8C/32D Group  
2. Central Processing Unit (CPU)  
2. Central Processing Unit (CPU)  
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a  
register bank. There are two sets of register bank.  
b31  
b15  
b8b7  
b0  
R0H (high-order of R0) R0L (low-order of R0)  
R1H (high-order of R1) R1L (low-order of R1)  
R2  
R2  
R3  
Data registers (1)  
R3  
A0  
Address registers (1)  
A1  
FB  
Frame base register (1)  
b19  
b15  
b0  
b0  
Interrupt table register  
Program counter  
INTBH  
INTBL  
The 4 high order bits of INTB are INTBH and  
the 16 low order bits of INTB are INTBL.  
b19  
PC  
b15  
b0  
User stack pointer  
Interrupt stack pointer  
Static base register  
USP  
ISP  
SB  
b15  
b0  
b0  
Flag register  
FLG  
b15  
b8  
b7  
IPL  
U I O B S Z D C  
Carry flag  
Debug flag  
Zero flag  
Sign flag  
Register bank select flag  
Overflow flag  
Interrupt enable flag  
Stack pointer select flag  
Reserved bit  
Processor interrupt priority level  
Reserved bit  
Note:  
1. These registers comprise a register bank. There are two register banks.  
Figure 2.1  
CPU Registers  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 9 of 42  
 
R8C/32D Group  
2. Central Processing Unit (CPU)  
2.1  
Data Registers (R0, R1, R2, and R3)  
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split  
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are  
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is  
analogous to R2R0.  
2.2  
Address Registers (A0 and A1)  
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also  
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-  
bit address register (A1A0).  
2.3  
Frame Base Register (FB)  
FB is a 16-bit register for FB relative addressing.  
2.4  
Interrupt Table Register (INTB)  
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.  
2.5  
Program Counter (PC)  
PC is 20 bits wide and indicates the address of the next instruction to be executed.  
2.6  
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)  
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between  
USP and ISP.  
2.7  
Static Base Register (SB)  
SB is a 16-bit register for SB relative addressing.  
2.8  
Flag Register (FLG)  
FLG is an 11-bit register indicating the CPU state.  
2.8.1  
Carry Flag (C)  
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.  
2.8.2  
Debug Flag (D)  
The D flag is for debugging only. Set it to 0.  
2.8.3  
Zero Flag (Z)  
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.  
2.8.4  
Sign Flag (S)  
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.  
2.8.5  
Register Bank Select Flag (B)  
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.  
2.8.6  
Overflow Flag (O)  
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 10 of 42  
R8C/32D Group  
2. Central Processing Unit (CPU)  
2.8.7  
Interrupt Enable Flag (I)  
The I flag enables maskable interrupts.  
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0  
when an interrupt request is acknowledged.  
2.8.8  
Stack Pointer Select Flag (U)  
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.  
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software  
interrupt numbers 0 to 31 is executed.  
2.8.9  
Processor Interrupt Priority Level (IPL)  
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.  
If a requested interrupt has higher priority than IPL, the interrupt is enabled.  
2.8.10 Reserved Bit  
If necessary, set to 0. When read, the content is undefined.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 11 of 42  
R8C/32D Group  
3.Memory  
3. Memory  
3.1  
R8C/32D Group  
Figure 3.1 is a Memory Map of R8C/32D Group. The R8C/32D Group has a 1-Mbyte address space from addresses  
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address  
0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.  
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt  
routine is stored here.  
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal  
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for data storage but also as  
a stack area when a subroutine is called or when an interrupt request is acknowledged.  
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. Peripheral function control registers  
are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users.  
00000h  
SFR  
(Refer to 4. Special  
Function Registers  
(SFRs))  
002FFh  
00400h  
Internal RAM  
0FFD8h  
0FFDCh  
0XXXXh  
Reserved area  
Undefined instruction  
Overflow  
BRK instruction  
Address match  
Single step  
Watchdog timer, oscillation stop detection, voltage monitor  
0YYYYh  
0FFFFh  
(Reserved)  
Internal ROM  
(program ROM)  
(Reserved)  
Reset  
0FFFFh  
FFFFFh  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
Internal ROM  
Part Number  
Internal RAM  
Address 0XXXXh  
Size  
Address 0YYYYh  
Size  
R5F21321DNSP, R5F21321DDSP  
R5F21322DNSP, R5F21322DDSP  
R5F21324DNSP, R5F21324DDSP  
4 Kbytes  
8 Kbytes  
16 Kbytes  
0F000h  
0E000h  
0C000h  
1 Kbyte  
1 Kbyte  
1 Kbyte  
007FFh  
007FFh  
007FFh  
Figure 3.1  
Memory Map of R8C/32D Group  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 12 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
4. Special Function Registers (SFRs)  
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.8 list the special  
function registers and Table 4.9 lists the ID Code Areas and Option Function Select Area.  
(1)  
Table 4.1  
SFR Information (1)  
Address  
0000h  
0001h  
0002h  
0003h  
0004h  
0005h  
0006h  
0007h  
0008h  
0009h  
000Ah  
000Bh  
000Ch  
000Dh  
000Eh  
000Fh  
0010h  
0011h  
0012h  
0013h  
0014h  
0015h  
0016h  
0017h  
0018h  
0019h  
001Ah  
001Bh  
001Ch  
Register  
Symbol  
After Reset  
Processor Mode Register 0  
Processor Mode Register 1  
PM0  
PM1  
CM0  
CM1  
00h  
00h  
System Clock Control Register 0  
System Clock Control Register 1  
Module Standby Control Register  
System Clock Control Register 3  
Protect Register  
00101000b  
00100000b  
00h  
MSTCR  
CM3  
00h  
00h  
PRCR  
RSTFR  
OCD  
(2)  
Reset Source Determination Register  
Oscillation Stop Detection Register  
Watchdog Timer Reset Register  
Watchdog Timer Start Register  
Watchdog Timer Control Register  
0XXXXXXXb  
00000100b  
XXh  
WDTR  
WDTS  
WDTC  
XXh  
00111111b  
High-Speed On-Chip Oscillator Control Register 7  
FRA7  
When shipping  
Count Source Protection Mode Register  
CSPR  
00h  
(3)  
10000000b  
001Dh  
001Eh  
001Fh  
0020h  
0021h  
0022h  
0023h  
0024h  
0025h  
0026h  
0027h  
0028h  
0029h  
002Ah  
002Bh  
002Ch  
002Dh  
002Eh  
002Fh  
0030h  
0031h  
0032h  
0033h  
0034h  
High-Speed On-Chip Oscillator Control Register 0  
High-Speed On-Chip Oscillator Control Register 1  
High-Speed On-Chip Oscillator Control Register 2  
On-Chip Reference Voltage Control Register  
FRA0  
FRA1  
00h  
When shipping  
FRA2  
OCVREFCR  
00h  
00h  
Clock Prescaler Reset Flag  
CPSRF  
FRA4  
FRA5  
FRA6  
00h  
High-Speed On-Chip Oscillator Control Register 4  
High-Speed On-Chip Oscillator Control Register 5  
High-Speed On-Chip Oscillator Control Register 6  
When Shipping  
When Shipping  
When Shipping  
High-Speed On-Chip Oscillator Control Register 3  
Voltage Monitor Circuit Control Register  
Voltage Monitor Circuit Edge Select Register  
FRA3  
CMPA  
VCAC  
When shipping  
00h  
00h  
Voltage Detect Register 1  
Voltage Detect Register 2  
VCA1  
VCA2  
00001000b  
(4)  
00h  
(5)  
00100000b  
0035h  
0036h  
0037h  
0038h  
Voltage Detection 1 Level Select Register  
Voltage Monitor 0 Circuit Control Register  
Voltage Monitor 1 Circuit Control Register  
VD1LS  
VW0C  
VW1C  
00000111b  
(4)  
1100X010b  
(5)  
1100X011b  
10001010b  
0039h  
X: Undefined  
Notes:  
1. The blank areas are reserved and cannot be accessed by users.  
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer  
reset does not affect this bit.  
3. The CSPROINI bit in the OFS register is set to 0.  
4. The LVDAS bit in the OFS register is set to 1.  
5. The LVDAS bit in the OFS register is set to 0.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 13 of 42  
 
 
 
 
 
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.2  
SFR Information (2)  
Address  
003Ah  
003Bh  
003Ch  
003Dh  
003Eh  
003Fh  
0040h  
0041h  
0042h  
0043h  
0044h  
0045h  
0046h  
0047h  
0048h  
0049h  
004Ah  
004Bh  
004Ch  
004Dh  
004Eh  
004Fh  
0050h  
0051h  
0052h  
0053h  
0054h  
0055h  
0056h  
0057h  
0058h  
0059h  
005Ah  
005Bh  
005Ch  
005Dh  
005Eh  
005Fh  
0060h  
0061h  
0062h  
0063h  
0064h  
0065h  
0066h  
0067h  
0068h  
0069h  
006Ah  
006Bh  
006Ch  
006Dh  
006Eh  
006Fh  
0070h  
0071h  
0072h  
0073h  
0074h  
0075h  
0076h  
0077h  
0078h  
0079h  
007Ah  
007Bh  
007Ch  
007Dh  
007Eh  
007Fh  
Register  
Symbol  
After Reset  
10000010b  
Voltage Monitor 2 Circuit Control Register  
VW2C  
Flash Memory Ready Interrupt Control Register  
FMRDYIC  
XXXXX000b  
XXXXX000b  
Timer RC Interrupt Control Register  
TRCIC  
Timer RE Interrupt Control Register  
TREIC  
S2TIC  
S2RIC  
KUPIC  
ADIC  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
UART2 Transmit Interrupt Control Register  
UART2 Receive Interrupt Control Register  
Key Input Interrupt Control Register  
A/D Conversion Interrupt Control Register  
UART0 Transmit Interrupt Control Register  
UART0 Receive Interrupt Control Register  
S0TIC  
S0RIC  
XXXXX000b  
XXXXX000b  
Timer RA Interrupt Control Register  
TRAIC  
XXXXX000b  
Timer RB Interrupt Control Register  
INT1 Interrupt Control Register  
INT3 Interrupt Control Register  
TRBIC  
INT1IC  
INT3IC  
XXXXX000b  
XX00X000b  
XX00X000b  
INT0 Interrupt Control Register  
INT0IC  
XX00X000b  
XXXXX000b  
UART2 Bus Collision Detection Interrupt Control Register  
U2BCNIC  
Voltage Monitor 1 Interrupt Control Register  
Voltage Monitor 2 Interrupt Control Register  
VCMP1IC  
VCMP2IC  
XXXXX000b  
XXXXX000b  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 14 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.3  
SFR Information (3)  
Address  
0080h  
0081h  
0082h  
0083h  
0084h  
0085h  
0086h  
0087h  
0088h  
0089h  
008Ah  
008Bh  
008Ch  
008Dh  
008Eh  
008Fh  
0090h  
0091h  
0092h  
0093h  
0094h  
0095h  
0096h  
0097h  
0098h  
0099h  
009Ah  
009Bh  
009Ch  
009Dh  
009Eh  
009Fh  
00A0h  
00A1h  
00A2h  
00A3h  
00A4h  
00A5h  
00A6h  
00A7h  
00A8h  
00A9h  
00AAh  
00ABh  
00ACh  
00ADh  
00AEh  
00AFh  
00B0h  
00B1h  
00B2h  
00B3h  
00B4h  
00B5h  
00B6h  
00B7h  
00B8h  
00B9h  
00BAh  
00BBh  
00BCh  
00BDh  
00BEh  
00BFh  
Register  
Symbol  
After Reset  
UART0 Transmit / Receive Mode Register  
UART0 Bit Rate Register  
U0MR  
00h  
XXh  
XXh  
XXh  
U0BRG  
U0TB  
UART0 Transmit Buffer Register  
UART0 Transmit / Receive Control Register 0  
UART0 Transmit / Receive Control Register 1  
UART0 Receive Buffer Register  
U0C0  
U0C1  
U0RB  
00001000b  
00000010b  
XXh  
XXh  
UART2 Transmit / Receive Mode Register  
UART2 Bit Rate Register  
U2MR  
U2BRG  
U2TB  
00h  
XXh  
UART2 Transmit Buffer Register  
XXh  
XXh  
UART2 Transmit / Receive Control Register 0  
UART2 Transmit / Receive Control Register 1  
UART2 Receive Buffer Register  
U2C0  
U2C1  
U2RB  
00001000b  
00000010b  
XXh  
XXh  
UART2 Digital Filter Function Select Register  
URXDF  
00h  
UART2 Special Mode Register 5  
UART2 Special Mode Register 4  
UART2 Special Mode Register 3  
UART2 Special Mode Register 2  
UART2 Special Mode Register  
U2SMR5  
U2SMR4  
U2SMR3  
U2SMR2  
U2SMR  
00h  
00h  
000X0X0Xb  
X0000000b  
X0000000b  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 15 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.4  
SFR Information (4)  
Address  
Register  
Symbol  
After Reset  
00C0h  
00C1h  
00C2h  
00C3h  
00C4h  
00C5h  
00C6h  
00C7h  
00C8h  
00C9h  
00CAh  
00CBh  
00CCh  
00CDh  
00CEh  
00CFh  
00D0h  
00D1h  
00D2h  
00D3h  
00D4h  
00D5h  
00D6h  
00D7h  
00D8h  
00D9h  
00DAh  
00DBh  
00DCh  
00DDh  
00DEh  
00DFh  
00E0h  
00E1h  
00E2h  
00E3h  
00E4h  
00E5h  
00E6h  
00E7h  
00E8h  
00E9h  
00EAh  
00EBh  
00ECh  
00EDh  
00EEh  
00EFh  
00F0h  
00F1h  
00F2h  
00F3h  
00F4h  
00F5h  
00F6h  
00F7h  
00F8h  
00F9h  
00FAh  
00FBh  
00FCh  
00FDh  
00FEh  
00FFh  
A/D Register 0  
A/D Register 1  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
XXh  
000000XXb  
XXh  
000000XXb  
XXh  
A/D Register 2  
A/D Register 3  
A/D Register 4  
A/D Register 5  
A/D Register 6  
A/D Register 7  
000000XXb  
XXh  
000000XXb  
XXh  
000000XXb  
XXh  
000000XXb  
XXh  
000000XXb  
XXh  
000000XXb  
A/D Mode Register  
ADMOD  
ADINSEL  
ADCON0  
ADCON1  
00h  
11000000b  
00h  
A/D Input Select Register  
A/D Control Register 0  
A/D Control Register 1  
00h  
Port P1 Register  
P1  
XXh  
00h  
XXh  
Port P1 Direction Register  
Port P3 Register  
PD1  
P3  
Port P3 Direction Register  
Port P4 Register  
PD3  
P4  
00h  
XXh  
Port P4 Direction Register  
PD4  
00h  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 16 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.5  
SFR Information (5)  
Address  
0100h  
0101h  
0102h  
0103h  
0104h  
0105h  
0106h  
0107h  
0108h  
0109h  
010Ah  
010Bh  
010Ch  
010Dh  
010Eh  
010Fh  
0110h  
0111h  
0112h  
0113h  
0114h  
0115h  
0116h  
0117h  
0118h  
0119h  
011Ah  
011Bh  
011Ch  
011Dh  
011Eh  
011Fh  
0120h  
0121h  
0122h  
0123h  
0124h  
0125h  
0126h  
0127h  
0128h  
0129h  
012Ah  
012Bh  
012Ch  
012Dh  
012Eh  
012Fh  
0130h  
0131h  
0132h  
0133h  
0134h  
0135h  
0136h  
0137h  
0138h  
0139h  
013Ah  
013Bh  
013Ch  
013Dh  
013Eh  
013Fh  
Register  
Symbol  
TRACR  
After Reset  
Timer RA Control Register  
Timer RA I/O Control Register  
Timer RA Mode Register  
Timer RA Prescaler Register  
Timer RA Register  
00h  
00h  
00h  
FFh  
FFh  
TRAIOC  
TRAMR  
TRAPRE  
TRA  
Timer RB Control Register  
TRBCR  
TRBOCR  
TRBIOC  
TRBMR  
TRBPRE  
TRBSC  
TRBPR  
00h  
00h  
00h  
00h  
FFh  
FFh  
FFh  
Timer RB One-Shot Control Register  
Timer RB I/O Control Register  
Timer RB Mode Register  
Timer RB Prescaler Register  
Timer RB Secondary Register  
Timer RB Primary Register  
Timer RE Second Data Register  
Timer RE Minute Data Register  
Timer RE Hour Data Register  
Timer RE Day of Week Data Register  
Timer RE Control Register 1  
TRESEC  
TREMIN  
TREHR  
00h  
00h  
00h  
00h  
00h  
00h  
TREWK  
TRECR1  
TRECR2  
TRECSR  
Timer RE Control Register 2  
Timer RE Count Source Select Register  
00001000b  
Timer RC Mode Register  
TRCMR  
TRCCR1  
TRCIER  
TRCSR  
TRCIOR0  
TRCIOR1  
TRC  
01001000b  
00h  
Timer RC Control Register 1  
Timer RC Interrupt Enable Register  
Timer RC Status Register  
01110000b  
01110000b  
10001000b  
10001000b  
00h  
Timer RC I/O Control Register 0  
Timer RC I/O Control Register 1  
Timer RC Counter  
00h  
Timer RC General Register A  
Timer RC General Register B  
Timer RC General Register C  
Timer RC General Register D  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
FFh  
FFh  
FFh  
FFh  
FFh  
FFh  
FFh  
FFh  
Timer RC Control Register 2  
TRCCR2  
TRCDF  
00011000b  
00h  
Timer RC Digital Filter Function Select Register  
Timer RC Output Master Enable Register  
Timer RC Trigger Control Register  
TRCOER  
TRCADCR  
01111111b  
00h  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 17 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.6  
SFR Information (6)  
Address  
0140h  
0141h  
0142h  
0143h  
0144h  
0145h  
0146h  
0147h  
0148h  
0149h  
014Ah  
014Bh  
014Ch  
014Dh  
014Eh  
014Fh  
0150h  
0151h  
0152h  
0153h  
0154h  
0155h  
0156h  
0157h  
0158h  
0159h  
015Ah  
015Bh  
015Ch  
015Dh  
015Eh  
015Fh  
0160h  
0161h  
0162h  
0163h  
0164h  
0165h  
0166h  
0167h  
0168h  
0169h  
016Ah  
016Bh  
016Ch  
016Dh  
016Eh  
016Fh  
0170h  
0171h  
0172h  
0173h  
0174h  
0175h  
0176h  
0177h  
0178h  
0179h  
017Ah  
017Bh  
017Ch  
017Dh  
017Eh  
017Fh  
Register  
Symbol  
After Reset  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 18 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.7  
SFR Information (7)  
Address  
0180h  
0181h  
0182h  
0183h  
0184h  
0185h  
0186h  
0187h  
0188h  
0189h  
018Ah  
018Bh  
018Ch  
018Dh  
018Eh  
018Fh  
0190h  
0191h  
0192h  
0193h  
0194h  
0195h  
0196h  
0197h  
0198h  
0199h  
019Ah  
019Bh  
019Ch  
019Dh  
019Eh  
019Fh  
01A0h  
01A1h  
01A2h  
01A3h  
01A4h  
01A5h  
01A6h  
01A7h  
01A8h  
01A9h  
01AAh  
01ABh  
01ACh  
01ADh  
01AEh  
01AFh  
01B0h  
01B1h  
01B2h  
01B3h  
01B4h  
01B5h  
01B6h  
01B7h  
01B8h  
01B9h  
01BAh  
01BBh  
01BCh  
01BDh  
01BEh  
01BFh  
Register  
Symbol  
TRASR  
After Reset  
Timer RA Pin Select Register  
Timer RC Pin Select Register  
Timer RC Pin Select Register 0  
Timer RC Pin Select Register 1  
00h  
00h  
00h  
00h  
TRBRCSR  
TRCPSR0  
TRCPSR1  
UART0 Pin Select Register  
U0SR  
00h  
UART2 Pin Select Register 0  
UART2 Pin Select Register 1  
U2SR0  
U2SR1  
00h  
00h  
INT Interrupt Input Pin Select Register  
I/O Function Pin Select Register  
INTSR  
PINSR  
00h  
00h  
Flash Memory Status Register  
FST  
10000X00b  
Flash Memory Control Register 0  
Flash Memory Control Register 1  
Flash Memory Control Register 2  
FMR0  
FMR1  
FMR2  
00h  
00h  
00h  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 19 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.8  
SFR Information (8)  
Address  
01C0h  
01C1h  
01C2h  
01C3h  
01C4h  
01C5h  
01C6h  
01C7h  
01C8h  
01C9h  
01CAh  
01CBh  
01CCh  
01CDh  
01CEh  
01CFh  
01D0h  
01D1h  
01D2h  
01D3h  
01D4h  
01D5h  
01D6h  
01D7h  
01D8h  
01D9h  
01DAh  
01DBh  
01DCh  
01DDh  
01DEh  
01DFh  
01E0h  
01E1h  
01E2h  
01E3h  
01E4h  
01E5h  
01E6h  
01E7h  
01E8h  
01E9h  
01EAh  
01EBh  
01ECh  
01EDh  
01EEh  
01EFh  
01F0h  
01F1h  
01F2h  
01F3h  
01F4h  
01F5h  
01F6h  
01F7h  
01F8h  
01F9h  
01FAh  
01FBh  
01FCh  
01FDh  
01FEh  
01FFh  
Register  
Symbol  
RMAD0  
After Reset  
Address Match Interrupt Register 0  
XXh  
XXh  
0000XXXXb  
00h  
XXh  
Address Match Interrupt Enable Register  
Address Match Interrupt Register 1  
AIER  
RMAD1  
XXh  
0000XXXXb  
Pull-Up Control Register 0  
Pull-Up Control Register 1  
PUR0  
PUR1  
00h  
00h  
Port P1 Drive Capacity Control Register  
P1DRR  
00h  
Drive Capacity Control Register 0  
Drive Capacity Control Register 1  
DRR0  
DRR1  
00h  
00h  
Input Threshold Control Register 0  
Input Threshold Control Register 1  
VLT0  
VLT1  
00h  
00h  
Comparator B Control Register 0  
External Input Enable Register 0  
INT Input Filter Select Register 0  
Key Input Enable Register 0  
INTCMP  
INTEN  
INTF  
00h  
00h  
00h  
00h  
KIEN  
X: Undefined  
Note:  
1. The blank areas are reserved and cannot be accessed by users.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 20 of 42  
 
R8C/32D Group  
4. Special Function Registers (SFRs)  
Table 4.9  
Address  
ID Code Areas and Option Function Select Area  
Area Name  
Symbol  
After Reset  
(Note 1)  
:
FFDBh  
Option Function Select Register 2  
OFS2  
:
FFDFh  
ID1  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 1)  
:
FFE3h  
ID2  
:
FFEBh  
ID3  
:
FFEFh  
ID4  
:
FFF3h  
ID5  
:
FFF7h  
ID6  
:
FFFBh  
:
FFFFh  
ID7  
Option Function Select Register  
OFS  
Notes:  
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.  
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select  
area is set to FFh.  
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.  
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.  
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.  
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.  
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.  
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 21 of 42  
 
 
R8C/32D Group  
5. Electrical Characteristics  
5. Electrical Characteristics  
Table 5.1  
Absolute Maximum Ratings  
Symbol  
Parameter  
Supply voltage  
Condition  
Rated Value  
0.3 to 6.5  
Unit  
V
VCC/AVCC  
VI  
Input voltage  
0.3 to VCC + 0.3  
0.3 to VCC + 0.3  
500  
V
VO  
Pd  
Output voltage  
V
Power dissipation  
40°C Topr 85°C  
mW  
°C  
Topr  
Operating ambient temperature  
20 to 85 (N version) /  
40 to 85 (D version)  
Tstg  
Storage temperature  
65 to 150  
°C  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 22 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.2  
Recommended Operating Conditions  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
1.8  
Typ.  
Max.  
VCC/AVCC Supply voltage  
0
5.5  
V
V
VSS/AVSS Supply voltage  
VIH  
Input “H” voltage Other than CMOS input  
0.8  
V
CC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
0.2 VCC  
0.2 VCC  
V
CMOS  
input  
Inputlevel Input level selection 4.0 V VCC 5.5 V 0.5 VCC  
switching : 0.35 VCC  
V
2.7 V VCC < 4.0 V 0.55 VCC  
V
function  
(I/O port)  
1.8 V VCC < 2.7 V 0.65 VCC  
V
Input level selection 4.0 V VCC 5.5 V 0.65 VCC  
V
: 0.5 VCC  
2.7 V VCC < 4.0 V 0.7  
1.8 V VCC < 2.7 V 0.8  
VCC  
CC  
V
V
V
Input level selection 4.0 V VCC 5.5 V 0.85 VCC  
: 0.7 VCC  
V
2.7 V VCC < 4.0 V 0.85 VCC  
V
1.8 V VCC < 2.7 V 0.85 VCC  
V
External clock input (XOUT)  
1.2  
0
0
0
0
0
0
0
0
0
0
0
32  
V
VIL  
Input “L” voltage Other than CMOS input  
V
CMOS  
input  
Inputlevel Input level selection 4.0 V VCC 5.5 V  
switching : 0.35 VCC  
function  
V
2.7 V VCC < 4.0 V  
1.8 V VCC < 2.7 V  
0.2  
0.2  
0.4  
0.3  
0.2  
VCC  
VCC  
VCC  
VCC  
VCC  
V
V
(I/O port)  
Input level selection 4.0 V VCC 5.5 V  
V
: 0.5 VCC  
2.7 V VCC < 4.0 V  
V
1.8 V VCC < 2.7 V  
V
Input level selection 4.0 V VCC 5.5 V  
: 0.7 VCC  
0.55 VCC  
0.45 VCC  
0.35 VCC  
0.4  
160  
80  
10  
40  
5  
V
2.7 V VCC < 4.0 V  
V
1.8 V VCC < 2.7 V  
V
External clock input (XOUT)  
IOH(sum) Peak sum output “H” current Sum of all pins IOH(peak)  
Average sum output “H” current Sum of all pins IOH(avg)  
V
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
MHz  
MHz  
kHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
IOH(sum)  
IOH(peak) Peak output “H” current  
Drive capacity Low  
Drive capacity High  
Drive capacity Low  
Drive capacity High  
IOH(avg)  
Average output “H” current  
20  
160  
80  
IOL(sum)  
IOL(sum)  
Peak sum output “L” current Sum of all pins IOL(peak)  
Average sum output “L” current Sum of all pins IOL(avg)  
IOL(peak) Peak output “L” current  
Drive capacity Low  
Drive capacity High  
Drive capacity Low  
Drive capacity High  
10  
40  
IOL(avg)  
f(XIN)  
Average output “L” current  
5
20  
XIN clock input oscillation frequency  
2.7 V VCC 5.5 V  
1.8 V VCC < 2.7 V  
1.8 V VCC 5.5 V  
2.7 V VCC 5.5 V  
2.7 V VCC 5.5 V  
1.8 V VCC < 2.7 V  
2.7 V VCC 5.5 V  
1.8 V VCC < 2.7 V  
2.7 V VCC 5.5 V  
1.8 V VCC < 2.7 V  
20  
5
f(XCIN)  
XCIN clock input oscillation frequency  
When used as the count source for timer RC  
32.768  
50  
(3)  
fOCO40M  
40  
fOCO-F fOCO-F frequency  
20  
5
System clock frequency  
CPU clock frequency  
20  
5
f(BCLK)  
20  
5
Notes:  
1. VCC = 1.8 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. The average output current indicates the average value of current measured during 100 ms.  
3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5V.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 23 of 42  
 
R8C/32D Group  
5. Electrical Characteristics  
P1  
P3  
P4  
30pF  
Figure 5.1  
Ports P1, P3, P4 Timing Measurement Circuit  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 24 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.3  
A/D Converter Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
10  
3
Resolution  
Vref = AVCC  
Vref = AVCC = 5.0 V  
Bit  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
MHz  
MHz  
MHz  
MHz  
kΩ  
Absolute accuracy  
10-bit mode  
8-bit mode  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
AN8 to AN11 input  
Vref = AVCC = 3.3 V  
Vref = AVCC = 3.0 V  
Vref = AVCC = 2.2 V  
Vref = AVCC = 5.0 V  
Vref = AVCC = 3.3 V  
Vref = AVCC = 3.0 V  
Vref = AVCC = 2.2 V  
5
5
5
2
2
2
2
4.0 V Vref = AVCC 5.5 V (2)  
3.2 V Vref = AVCC 5.5 V (2)  
2.7 V Vref = AVCC 5.5 V (2)  
2.2 V Vref = AVCC 5.5 V (2)  
φAD  
A/D conversion clock  
2
20  
16  
10  
5
2
2
2
Tolerance level impedance  
Conversion time  
3
tCONV  
10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz  
2.15  
2.15  
0.75  
µs  
8-bit mode  
Vref = AVCC = 5.0 V, φAD = 20 MHz  
φAD = 20 MHz  
µs  
tSAMP  
IVref  
Vref  
Sampling time  
µs  
Vref current  
VCC = 5 V, XIN = f1 = φAD = 20 MHz  
45  
µA  
Reference voltage  
Analog input voltage (3)  
2.2  
0
AVCC  
Vref  
1.49  
V
VIA  
V
OCVREF On-chip reference voltage  
2 MHz ≤ φAD 4 MHz  
1.19  
1.34  
V
Notes:  
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise  
specified.  
2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current-  
consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.  
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in  
8-bit mode.  
Table 5.4  
Comparator B Electrical Characteristics  
Standard  
Symbol  
Vref  
Parameter  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
VCC 1.4  
VCC + 0.3  
100  
IVREF1, IVREF3 input reference voltage  
IVCMP1, IVCMP3 input voltage  
Offset  
V
V
VI  
0.3  
5
mV  
µs  
µA  
Comparator output delay time (2)  
Comparator operating current  
td  
VI = Vref 100 mV  
VCC = 5.0 V  
0.1  
17.5  
ICMP  
Notes:  
1. VCC = 2.7 to 5.5 V, Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. When the digital filter is disabled.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 25 of 42  
 
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.5  
Flash Memory (Program ROM) Electrical Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Program/erase endurance (2)  
Byte program time  
1,000 (3)  
times  
µs  
80  
0.3  
500  
Block erase time  
s
td(SR-SUS)  
Time delay from suspend request until  
suspend  
5 + CPU clock  
× 3 cycles  
ms  
Interval from erase start/restart until  
following suspend request  
0
µs  
µs  
µs  
Time from suspend until erase restart  
30 + CPU clock  
× 1 cycle  
td(CMDRST-  
READY)  
Time from when command is forcibly  
stopped until reading is enabled  
30+CPUclock  
× 1 cycle  
Program, erase voltage  
Read voltage  
2.7  
1.8  
0
5.5  
5.5  
60  
V
V
Program, erase temperature  
Data hold time (7)  
°C  
Ambient temperature = 55°C  
20  
year  
Notes:  
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.  
2. Definition of programming/erasure endurance  
The programming and erasure endurance is defined on a per-block basis.  
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte  
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the  
programming/erasure endurance still stands at one.  
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).  
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).  
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential  
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,  
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups  
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit  
the number of erase operations to a certain number.  
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase  
command at least three times until the erase error does not occur.  
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.  
7. The data hold time includes time that the power supply is off or the clock is not supplied.  
Suspend request  
(FMR21 bit)  
FST7 bit  
FST6 bit  
Clock-dependent  
time  
Fixed time  
Access restart  
td(SR-SUS)  
FST6, FST7: Bit in FST register  
FMR21: Bit in FMR2 register  
Figure 5.2  
Time delay until Suspend  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 26 of 42  
 
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.6  
Voltage Detection 0 Circuit Electrical Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Condition  
Min.  
1.80  
2.15  
2.70  
3.55  
Typ.  
1.90  
2.35  
2.85  
3.80  
6
Max.  
2.05  
2.50  
3.05  
4.05  
150  
Voltage detection level Vdet0_0 (2)  
Voltage detection level Vdet0_1 (2)  
Voltage detection level Vdet0_2 (2)  
Voltage detection level Vdet0_3 (2)  
Voltage detection 0 circuit response time (4)  
Vdet0  
V
V
V
V
At the falling of VCC from 5 V  
to (Vdet0_0 0.1) V  
µs  
Voltage detection circuit self power consumption  
Waiting time until voltage detection circuit  
operation starts (3)  
VCA25 = 1, VCC = 5.0 V  
1.5  
µA  
µs  
td(E-A)  
100  
Notes:  
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85°C (N version) / 40 to 85°C (D version).  
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.  
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2  
register to 0.  
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.  
Table 5.7  
Voltage Detection 1 Circuit Electrical Characteristics  
Standard  
Typ.  
2.20  
2.35  
2.50  
2.65  
2.80  
2.95  
3.10  
3.25  
3.40  
3.55  
3.70  
3.85  
4.00  
4.15  
4.30  
4.45  
0.07  
Symbol  
Parameter  
Condition  
Unit  
Min.  
2.00  
2.15  
2.30  
2.45  
2.60  
2.75  
2.85  
3.00  
3.15  
3.30  
3.45  
3.60  
3.75  
3.90  
4.05  
4.20  
Max.  
2.40  
2.55  
2.70  
2.85  
3.00  
3.15  
3.40  
3.55  
3.70  
3.85  
4.00  
4.15  
4.30  
4.45  
4.60  
4.75  
Voltage detection level Vdet1_0 (2)  
Voltage detection level Vdet1_1 (2)  
Voltage detection level Vdet1_2 (2)  
Voltage detection level Vdet1_3 (2)  
Voltage detection level Vdet1_4 (2)  
Voltage detection level Vdet1_5 (2)  
Voltage detection level Vdet1_6 (2)  
Voltage detection level Vdet1_7 (2)  
Voltage detection level Vdet1_8 (2)  
Voltage detection level Vdet1_9 (2)  
Voltage detection level Vdet1_A (2)  
Voltage detection level Vdet1_B (2)  
Voltage detection level Vdet1_C (2)  
Voltage detection level Vdet1_D (2)  
Voltage detection level Vdet1_E (2)  
Voltage detection level Vdet1_F (2)  
Vdet1  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
At the falling of VCC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Hysteresis width at the rising of Vcc in voltage  
detection 1 circuit  
Vdet1_0 to Vdet1_5  
selected  
Vdet1_6 to Vdet1_F  
selected  
0.10  
60  
V
Voltage detection 1 circuit response time (3)  
At the falling of Vcc from 5 V  
150  
µs  
to (Vdet1_0  
0.1) V  
Voltage detection circuit self power consumption  
Waiting time until voltage detection circuit operation  
starts (4)  
VCA26 = 1, VCC = 5.0 V  
1.7  
µA  
µs  
td(E-A)  
100  
Notes:  
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85°C (N version) / 40 to 85°C (D version).  
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.  
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.  
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2  
register to 0.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 27 of 42  
 
 
 
 
 
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.8  
Voltage Detection 2 Circuit Electrical Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Condition  
Min.  
3.70  
Typ.  
4.00  
0.10  
Max.  
4.30  
Vdet2  
Voltage detection level Vdet2_0  
At the falling of VCC  
V
V
Hysteresis width at the rising of Vcc in voltage detection  
2 circuit  
Voltage detection 2 circuit response time (2)  
At the falling of Vcc from  
5 V to (Vdet2_0 0.1) V  
20  
150  
µs  
Voltage detection circuit self power consumption  
Waiting time until voltage detection circuit operation  
starts (3)  
VCA27 = 1, VCC = 5.0 V  
1.7  
µA  
µs  
td(E-A)  
100  
Notes:  
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85°C (N version) / 40 to 85°C (D version).  
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.  
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2  
register to 0.  
(2)  
Table 5.9  
Power-on Reset Circuit  
Standard  
Symbol  
Parameter  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
(1)  
trth  
External power VCC rise gradient  
50000 mV/msec  
Notes:  
1. The measurement condition is Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.  
(1)  
Vdet0  
(1)  
Vdet0  
trth  
trth  
External  
Power VCC  
0.5 V  
(2)  
Voltage detection 0  
circuit response time  
tw(por)  
Internal  
reset signal  
1
1
× 32  
× 32  
fOCO-S  
fOCO-S  
Notes:  
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection  
Circuit of Hardware Manual (REJ09B0528) for details.  
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable  
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain  
tw(por) for 1 ms or more.  
Figure 5.3  
Power-on Reset Circuit Electrical Characteristics  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 28 of 42  
 
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.10  
High-speed On-Chip Oscillator Circuit Electrical Characteristics  
Standard  
Typ.  
Symbol  
Parameter  
Condition  
Unit  
Min.  
38.4  
Max.  
41.6  
High-speed on-chip oscillator frequency after  
reset  
VCC = 1.8 V to 5.5 V  
40  
MHz  
20°C Topr 85°C  
VCC = 1.8 V to 5.5 V  
38.0  
35.389  
35.020  
30.72  
30.40  
40  
42.0  
MHz  
40°C Topr 85°C  
High-speed on-chip oscillator frequency when  
the FRA4 register correction value is written into 20°C Topr 85°C  
the FRA1 register and the FRA5 register  
VCC = 1.8 V to 5.5 V  
36.864 38.338 MHz  
36.864 38.707 MHz  
VCC = 1.8 V to 5.5 V  
correction value into the FRA3 register (3)  
40°C Topr 85°C  
High-speed on-chip oscillator frequency when  
VCC = 1.8 V to 5.5 V  
32  
32  
33.28  
33.60  
MHz  
MHz  
the FRA6 register correction value is written into 20°C Topr 85°C  
the FRA1 register and the FRA7 register  
correction value into the FRA3 register  
VCC = 1.8 V to 5.5 V  
40°C Topr 85°C  
Oscillation stability time  
VCC = 5.0 V, Topr = 25°C  
VCC = 5.0 V, Topr = 25°C  
0.5  
3
ms  
Self power consumption at oscillation  
400  
µA  
Notes:  
1. VCC = 1.8 to 5.5 V, Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator.  
3. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in  
UART mode.  
Table 5.11  
Low-speed On-Chip Oscillator Circuit Electrical Characteristics  
Standard  
Typ.  
125  
Symbol  
fOCO-S  
Parameter  
Condition  
Unit  
Min.  
60  
Max.  
250  
100  
Low-speed on-chip oscillator frequency  
Oscillation stability time  
kHz  
µs  
VCC = 5.0 V, Topr = 25°C  
VCC = 5.0 V, Topr = 25°C  
30  
Self power consumption at oscillation  
2
µA  
Note:  
1. VCC = 1.8 to 5.5 V, Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
Table 5.12  
Power Supply Circuit Timing Characteristics  
Standard  
Symbol  
Parameter  
Condition  
Unit  
Min.  
Typ.  
Max.  
2000  
td(P-R)  
Time for internal power supply stabilization during  
power-on (2)  
µs  
Notes:  
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.  
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 29 of 42  
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.13  
Electrical Characteristics (1) [4.2 V Vcc 5.5 V]  
Standard  
Unit  
Symbol  
Parameter  
Condition  
Min.  
Typ.  
Max.  
VCC  
VCC  
VCC  
2.0  
2.0  
0.5  
VOH  
Output “H” Other than XOUT  
voltage  
Drive capacity High VCC = 5 V IOH = 20 mA VCC 2.0  
V
V
V
V
V
V
V
Drive capacity Low VCC = 5 V IOH = 5 mA  
VCC = 5V IOH = 200 µA  
VCC 2.0  
XOUT  
1.0  
VOL  
Output “L” Other than XOUT  
voltage  
Drive capacity High VCC = 5 V IOL = 20 mA  
Drive capacity Low VCC = 5 V IOL = 5 mA  
XOUT  
VCC = 5V  
IOL = 200 µA  
VT+-VT-  
Hysteresis  
0.1  
1.2  
INT0, INT1, INT3,  
KI0, KI1, KI2, KI3,  
TRAIO, TRBO,  
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD,  
TRCTRG,  
TRCCLK, ADTRG,  
RXD0, RXD2,  
CLK0, CLK2  
0.1  
1.2  
V
RESET  
IIH  
IIL  
Input “H” current  
Input “L” current  
VI = 5 V, VCC = 5.0 V  
VI = 0 V, VCC = 5.0 V  
VI = 0 V, VCC = 5.0 V  
5.0  
5.0  
100  
µA  
µA  
RPULLUP Pull-up resistance  
25  
50  
0.3  
kΩ  
MΩ  
RfXIN  
Feedback XIN  
resistance  
RfXCIN  
Feedback XCIN  
resistance  
8
MΩ  
VRAM  
Note:  
RAM hold voltage  
During stop mode  
1.8  
V
1. 4.2 V VCC 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 30 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.14  
Electrical Characteristics (2) [3.3 V Vcc 5.5 V]  
(Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)  
Standard  
Symbol  
Parameter  
Condition  
Unit  
mA  
Min.  
Typ.  
6.5  
Max.  
15  
XIN = 20 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
ICC  
Power supply  
current  
High-speed  
clock mode  
(VCC = 3.3 to 5.5 V)  
Single-chip mode,  
output pins are  
open, other pins  
are VSS  
XIN = 16 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
5.3  
3.6  
3.0  
2.2  
1.5  
7.0  
3.0  
1
12.5  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN = 20 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN = 16 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
High-speed  
on-chip  
oscillator mode  
15  
High-speed on-chip oscillator on fOCO-F = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 4 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-16  
MSTTRC = 1  
XIN clock off  
Low-speed  
on-chip  
90  
85  
400  
400  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8, FMR27 = 1, VCA20 = 0  
oscillator mode  
Low-speed  
clock mode  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
FMR27 = 1, VCA20 = 0  
XIN clock off  
47  
15  
4
100  
90  
µA  
µA  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
Program operation on RAM  
Flash memory off, FMSTP = 1, VCA20 = 0  
XIN clock off  
Wait mode  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock operation  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
XIN clock off  
3.5  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz (peripheral clock off)  
While a WAIT instruction is executed  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
XIN clock off, Topr = 25°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
Stop mode  
2.0  
5.0  
5.0  
µA  
µA  
XIN clock off, Topr = 85°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 31 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Timing Requirements  
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C)  
Table 5.15  
External Clock Input (XOUT, XCIN)  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(XOUT)  
XOUT input cycle time  
XOUT input “H” width  
XOUT input “L” width  
XCIN input cycle time  
XCIN input “H” width  
XCIN input “L” width  
50  
24  
24  
14  
7
ns  
ns  
ns  
µs  
µs  
µs  
tWH(XOUT)  
tWL(XOUT)  
tc(XCIN)  
tWH(XCIN)  
tWL(XCIN)  
7
VCC = 5 V  
tC(XOUT), tC(XCIN)  
tWH(XOUT),  
tWH(XCIN)  
External Clock Input  
tWL(XOUT), tWL(XCIN)  
Figure 5.4  
External Clock Input Timing Diagram when VCC = 5 V  
Table 5.16  
TRAIO Input  
Standard  
Max.  
Symbol  
Parameter  
Unit  
Min.  
100  
40  
tc(TRAIO)  
TRAIO input cycle time  
TRAIO input “H” width  
TRAIO input “L” width  
ns  
ns  
ns  
tWH(TRAIO)  
tWL(TRAIO)  
40  
tC(TRAIO)  
VCC = 5 V  
tWH(TRAIO)  
TRAIO input  
tWL(TRAIO)  
Figure 5.5  
TRAIO Input Timing Diagram when VCC = 5 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 32 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.17  
Serial Interface  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(CK)  
CLKi input cycle time  
CLKi input “H” width  
CLKi input “L” width  
TXDi output delay time  
TXDi hold time  
200  
100  
100  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tW(CKH)  
tW(CKL)  
td(C-Q)  
th(C-Q)  
tsu(D-C)  
th(C-D)  
50  
0
RXDi input setup time  
RXDi input hold time  
50  
90  
i = 0, 2  
VCC = 5 V  
tC(CK)  
tW(CKH)  
CLKi  
tW(CKL)  
th(C-Q)  
TXDi  
RXDi  
td(C-Q)  
tsu(D-C)  
th(C-D)  
i = 0, 2  
Figure 5.6  
Serial Interface Timing Diagram when VCC = 5 V  
Table 5.18  
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
250 (1)  
250 (2)  
tW(INH)  
tW(INL)  
ns  
ns  
INTi input “H” width, KIi input “H” width  
INTi input “L” width, KIi input “L” width  
Notes:  
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
VCC = 5 V  
INTi input  
(i = 0, 1, 3)  
tW(INL)  
KIi input  
(i = 0 to 3)  
tW(INH)  
Figure 5.7  
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 33 of 42  
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.19  
Electrical Characteristics (3) [2.7 V Vcc < 4.2 V]  
Standard  
Unit  
Symbol  
Parameter  
Output “H” voltage Other than XOUT  
Condition  
Min.  
Typ.  
Max.  
VCC  
VCC  
VCC  
0.5  
0.5  
0.5  
VOH  
Drive capacity High IOH = 5 mA  
Drive capacity Low IOH = 1 mA  
IOH = 200 µA  
VCC 0.5  
V
V
V
V
V
V
V
VCC 0.5  
XOUT  
1.0  
VOL  
Output “L” voltage  
Hysteresis  
Other than XOUT  
Drive capacity High IOL = 5 mA  
Drive capacity Low IOL = 1 mA  
IOL = 200 µA  
XOUT  
VT+-VT-  
VCC = 3.0 V  
0.1  
0.4  
INT0, INT1, INT3,  
KI0, KI1, KI2, KI3,  
TRAIO, TRBO,  
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD,  
TRCTRG, TRCCLK,  
ADTRG,  
RXD0, RXD2,  
CLK0, CLK2  
VCC = 3.0 V  
0.1  
0.5  
V
RESET  
IIH  
IIL  
Input “H” current  
Input “L” current  
VI = 3 V, VCC = 3.0 V  
VI = 0 V, VCC = 3.0 V  
VI = 0 V, VCC = 3.0 V  
4.0  
4.0  
168  
µA  
µA  
kΩ  
MΩ  
MΩ  
V
RPULLUP Pull-up resistance  
42  
84  
0.3  
8
RfXIN  
Feedback resistance XIN  
Feedback resistance XCIN  
RAM hold voltage  
RfXCIN  
VRAM  
During stop mode  
1.8  
Note:  
1. 2.7 V VCC < 4.2 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 34 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.20  
Electrical Characteristics (4) [2.7 V Vcc < 3.3 V]  
(Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)  
Standard  
Symbol  
Parameter  
Condition  
Unit  
mA  
Min.  
Typ.  
3.5  
Max.  
10  
ICC  
Power supply current High-speed  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
(VCC = 2.7 to 3.3 V)  
Single-chip mode,  
output pins are open,  
other pins are VSS  
clock mode  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
1.5  
7.0  
3.0  
4.0  
1.5  
1
7.5  
15  
mA  
mA  
mA  
mA  
mA  
mA  
High-speed  
on-chip  
oscillator mode  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 4 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-16  
MSTTRC = 1  
Low-speed  
on-chip  
XIN clock off  
90  
80  
390  
400  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8, FMR27 = 1, VCA20 = 0  
oscillator mode  
Low-speed  
clock mode  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
FMR27 = 1, VCA20 = 0  
XIN clock off  
40  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
Program operation on RAM  
Flash memory off, FMSTP = 1, VCA20 = 0  
Wait mode  
XIN clock off  
15  
4
90  
80  
µA  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock operation  
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1  
XIN clock off  
3.5  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz (peripheral  
clock off)  
While a WAIT instruction is executed  
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1  
Stop mode  
XIN clock off, Topr = 25°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
2.0  
5.0  
5.0  
µA  
µA  
XIN clock off, Topr = 85°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 35 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Timing requirements  
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C)  
Table 5.21  
External Clock Input (XOUT, XCIN)  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(XOUT)  
XOUT input cycle time  
XOUT input “H” width  
XOUT input “L” width  
XCIN input cycle time  
XCIN input “H” width  
XCIN input “L” width  
50  
24  
24  
14  
7
ns  
ns  
ns  
µs  
µs  
µs  
tWH(XOUT)  
tWL(XOUT)  
tc(XCIN)  
tWH(XCIN)  
tWL(XCIN)  
7
tC(XOUT), tC(XCIN)  
VCC = 3 V  
tWH(XOUT),  
tWH(XCIN)  
External Clock Input  
tWL(XOUT), tWL(XCIN)  
Figure 5.8  
External Clock Input Timing Diagram when VCC = 3 V  
Table 5.22  
TRAIO Input  
Standard  
Symbol  
Parameter  
Unit  
Min.  
300  
120  
120  
Max.  
tc(TRAIO)  
TRAIO input cycle time  
TRAIO input “H” width  
TRAIO input “L” width  
ns  
ns  
ns  
tWH(TRAIO)  
tWL(TRAIO)  
VCC = 3 V  
tC(TRAIO)  
tWH(TRAIO)  
TRAIO input  
tWL(TRAIO)  
Figure 5.9  
TRAIO Input Timing Diagram when VCC = 3 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 36 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.23  
Serial Interface  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(CK)  
CLKi input cycle time  
CLKi input “H” width  
CLKi Input “L” width  
TXDi output delay time  
TXDi hold time  
300  
150  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tW(CKH)  
tW(CKL)  
td(C-Q)  
th(C-Q)  
tsu(D-C)  
th(C-D)  
80  
0
RXDi input setup time  
RXDi input hold time  
70  
90  
i = 0, 2  
tC(CK)  
VCC = 3 V  
tW(CKH)  
CLKi  
tW(CKL)  
th(C-Q)  
TXDi  
RXDi  
td(C-Q)  
tsu(D-C)  
th(C-D)  
i = 0, 2  
Figure 5.10  
Serial Interface Timing Diagram when VCC = 3 V  
Table 5.24  
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
380 (1)  
380 (2)  
tW(INH)  
tW(INL)  
ns  
ns  
INTi input “H” width, KIi input “H” width  
INTi input “L” width, KIi input “L” width  
Notes:  
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
VCC = 3 V  
INTi input  
(i = 0, 1, 3)  
tW(INL)  
KIi input  
(i = 0 to 3)  
tW(INH)  
Figure 5.11  
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 37 of 42  
 
 
R8C/32D Group  
5. Electrical Characteristics  
Table 5.25  
Electrical Characteristics (5) [1.8 V Vcc < 2.7 V]  
Standard  
Unit  
Symbol  
Parameter  
Output “H” voltage Other than XOUT  
Condition  
Min.  
Typ.  
Max.  
VCC  
VCC  
VCC  
0.5  
0.5  
0.5  
VOH  
Drive capacity High IOH = 2 mA  
Drive capacity Low IOH = 1 mA  
IOH = 200 µA  
VCC 0.5  
V
V
V
V
V
V
V
VCC 0.5  
XOUT  
1.0  
VOL  
Output “L” voltage  
Hysteresis  
Other than XOUT  
Drive capacity High IOL = 2 mA  
Drive capacity Low IOL = 1 mA  
IOL = 200 µA  
XOUT  
VT+-VT-  
0.05  
0.2  
INT0, INT1, INT3,  
KI0, KI1, KI2, KI3,  
TRAIO, TRBO,  
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD,  
TRCTRG,  
TRCCLK,  
ADTRG,  
RXD0, RXD2,  
CLK0, CLK2  
0.05  
0.20  
V
RESET  
IIH  
IIL  
Input “H” current  
Input “L” current  
VI = 2.2 V, VCC = 2.2 V  
VI = 0 V, VCC = 2.2 V  
VI = 0 V, VCC = 2.2 V  
4.0  
4.0  
300  
µA  
µA  
kΩ  
MΩ  
MΩ  
V
RPULLUP Pull-up resistance  
70  
140  
0.3  
8
RfXIN  
Feedback resistance XIN  
Feedback resistance XCIN  
RAM hold voltage  
RfXCIN  
VRAM  
During stop mode  
1.8  
Note:  
1. 1.8 V VCC < 2.7 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 38 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.26  
Electrical Characteristics (6) [1.8 V Vcc < 2.7 V]  
(Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)  
Standard  
Symbol  
Parameter  
Condition  
Unit  
mA  
Min.  
Typ.  
2.2  
Max.  
ICC  
Power supply current High-speed  
XIN = 5 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
(VCC = 1.8 to 2.7 V)  
Single-chip mode,  
output pins are open,  
other pins are VSS  
clock mode  
XIN = 5 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
0.8  
2.5  
1.7  
1
10  
mA  
mA  
mA  
mA  
High-speed  
on-chip  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 5 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
oscillator  
mode  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 5 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
High-speed on-chip oscillator on fOCO-F = 4 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-16  
MSTTRC = 1  
Low-speed on- XIN clock off  
chip oscillator  
mode  
90  
80  
300  
350  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8, FMR27 = 1, VCA20 = 0  
Low-speed  
clock mode  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
FMR27 = 1, VCA20 = 0  
XIN clock off  
40  
15  
4
90  
80  
µA  
µA  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz  
No division  
Program operation on RAM  
Flash memory off, FMSTP = 1, VCA20 = 0  
Wait mode  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock operation  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
XIN clock off  
3.5  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
XCIN clock oscillator on = 32 kHz (peripheral  
clock off)  
While a WAIT instruction is executed  
VCA27 = VCA26 = VCA25 = 0  
VCA20 = 1  
Stop mode  
XIN clock off, Topr = 25°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
2.0  
5.0  
5
µA  
µA  
XIN clock off, Topr = 85°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = VCA25 = 0  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 39 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Timing requirements  
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C)  
Table 5.27  
External Clock Input (XOUT, XCIN)  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(XOUT)  
XOUT input cycle time  
XOUT input “H” width  
XOUT input “L” width  
XCIN input cycle time  
XCIN input “H” width  
XCIN input “L” width  
200  
90  
90  
14  
7
ns  
ns  
ns  
µs  
µs  
µs  
tWH(XOUT)  
tWL(XOUT)  
tc(XCIN)  
tWH(XCIN)  
tWL(XCIN)  
7
tC(XOUT), tC(XCIN)  
VCC = 2.2 V  
tWH(XOUT),  
tWH(XCIN)  
External Clock Input  
tWL(XOUT), tWL(XCIN)  
Figure 5.12  
External Clock Input Timing Diagram when VCC = 2.2 V  
Table 5.28  
TRAIO Input  
Standard  
Max.  
Symbol  
Parameter  
Unit  
Min.  
500  
200  
200  
tc(TRAIO)  
TRAIO input cycle time  
TRAIO input “H” width  
TRAIO input “L” width  
ns  
ns  
ns  
tWH(TRAIO)  
tWL(TRAIO)  
tC(TRAIO)  
VCC = 2.2 V  
tWH(TRAIO)  
TRAIO input  
tWL(TRAIO)  
Figure 5.13  
TRAIO Input Timing Diagram when VCC = 2.2 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 40 of 42  
R8C/32D Group  
5. Electrical Characteristics  
Table 5.29  
Serial Interface  
Standard  
Unit  
Symbol  
Parameter  
Min.  
Max.  
tc(CK)  
CLKi input cycle time  
CLKi input “H” width  
CLKi input “L” width  
TXDi output delay time  
TXDi hold time  
800  
400  
400  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tW(CKH)  
tW(CKL)  
td(C-Q)  
th(C-Q)  
tsu(D-C)  
th(C-D)  
200  
0
RXDi input setup time  
RXDi input hold time  
150  
90  
i = 0, 2  
VCC = 2.2 V  
tC(CK)  
tW(CKH)  
CLKi  
tW(CKL)  
th(C-Q)  
TXDi  
RXDi  
td(C-Q)  
tsu(D-C)  
th(C-D)  
i = 0, 2  
Figure 5.14  
Serial Interface Timing Diagram when VCC = 2.2 V  
Table 5.30  
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
1000 (1)  
1000 (2)  
tW(INH)  
tW(INL)  
ns  
ns  
INTi input “H” width, KIi input “H” width  
INTi input “L” width, KIi input “L” width  
Notes:  
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
VCC = 2.2 V  
INTi input  
(i = 0, 1, 3)  
tW(INL)  
KIi input  
(i = 0 to 3)  
tW(INH)  
Figure 5.15  
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 2.2 V  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 41 of 42  
 
 
R8C/32D Group  
Package Dimensions  
Package Dimensions  
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of  
the Renesas Technology website.  
JEITA Package Code  
RENESAS Code  
PLSP0020JB-A  
Previous Code  
20P2F-A  
MASS[Typ.]  
0.1g  
P-LSSOP20-4.4x6.5-0.65  
11  
20  
NOTE)  
1. DIMENSIONS "*1" AND "*2"  
F
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION "*3" DOES NOT  
INCLUDE TRIM OFFSET.  
1
10  
Index mark  
c
A2  
A1  
Dimension in Millimeters  
Reference  
Symbol  
*2  
D
Min Nom Max  
D
E
6.4 6.5 6.6  
4.3 4.4 4.5  
1.15  
A2  
A
1.45  
0.1 0.2  
A1  
bp  
c
*3  
0
0.17 0.22 0.32  
bp  
e
Detail F  
y
0.2  
10°  
0.13 0.15  
0°  
HE  
e
6.2 6.4 6.6  
0.53 0.65 0.77  
0.10  
y
L
0.3 0.5 0.7  
REJ03B0288-0100 Rev.1.00 Feb 26, 2010  
Page 42 of 42  
REVISION HISTORY  
R8C/32D Group Datasheet  
Description  
Summary  
Rev.  
Date  
Page  
Feb. 26, 2008  
First Edition issued  
0.01  
1.00  
Feb. 26, 2010 All pages “Preliminary”, “Under development” deleted  
Table 1.3 revised  
22 to 41 “5. Electrical Characteristics” added  
4
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