R5F21346EJFP [RENESAS]
16-bit Microcontrollers with R8C CPU Core (Non Promotion), , /;型号: | R5F21346EJFP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 16-bit Microcontrollers with R8C CPU Core (Non Promotion), , / 微控制器 |
文件: | 总48页 (文件大小:536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
RENESAS MCU
REJ03B0246-0010
Rev.0.10
Apr 17, 2008
1. Overview
1.1
Features
The R8C/34E Group, R8C/34F Group, R8C/34G Group, and R8C/34H Group of single-chip MCUs incorporate the
R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of
address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a
multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/34E Group and R8C/34F Group have a single channel CAN module and are suitable for LAN systems in
vehicles and for FA.
The R8C/34G Group and the R8C/34H Group do not have CAN modules.
The R8C/34E Group and the R8C/34G Group have data flash (1 KB × 4 blocks) with the background operation
(BGO) function.
1.1.1
Applications
Automobiles and others
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 1 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/34E Group, tables 1.3 and 1.4 outline the Specifications
for R8C/34F Group, tables 1.5 and 1.6 outline the Specifications for R8C/34G Group, tables 1.7 and 1.8 outline
the Specifications for R8C/34H Group.
Table 1.1
Item
CPU
Specifications for R8C/34E Group (1)
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.9 Product List for R8C/34E Group.
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
• Power-on reset
Voltage
Detection
I/O Ports
circuit
• Voltage detection 3 (detection level of voltage detection 1 selectable)
Programmable I/O • Input-only: 1 pin
ports
Clock generation
circuits
• CMOS I/O ports: 43, selectable pull-up resistor
Clock
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
Interrupts
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
Watchdog Timer
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
DTC (Data Transfer Controller)
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timer RA
Timer RB
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RD
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE
8 bits × 1
Output compare mode
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 2 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.2
Specifications for R8C/34E Group (2)
Item
Serial
Function
Specification
UART0, 1
UART2
Clock synchronous serial I/O/UART × 2 channel
2
2
(1)
Interface
Clock synchronous serial I/O, UART, I C mode (I C-bus), IE mode (IE BUS ),
multiprocessor communication function
Synchronous Serial
Communication Unit (SSU)
LIN Module
CAN module
A/D Converter
1
Hardware LIN: 1 (timer RA, UART0)
One channel, 16 Mailboxes (conforms to the ISO 11898-1)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
Flash Memory
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Operating Frequency/Supply
Voltage
Current consumption
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature
Package
-40 to 85°C (J version)
(2)
-40 to 125°C (K version)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 3 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.3
Item
CPU
Specifications for R8C/34F Group (1)
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.10 Product List for R8C/34F Group.
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
• Power-on reset
Voltage
Detection
I/O Ports
circuit
• Voltage detection 3 (detection level of voltage detection 1 selectable)
Programmable I/O • Input-only: 1 pin
ports
Clock generation
circuits
• CMOS I/O ports: 43, selectable pull-up resistor
Clock
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
Interrupts
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
Watchdog Timer
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
DTC (Data Transfer Controller)
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timer RA
Timer RB
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RD
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE
8 bits × 1
Output compare mode
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 4 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.4
Specifications for R8C/34F Group (2)
Item
Serial
Function
Specification
UART0, 1
UART2
Clock synchronous serial I/O/UART × 2 channel
2
2
(1)
Interface
Clock synchronous serial I/O, UART, I C mode (I C-bus), IE mode (IE BUS ),
multiprocessor communication function
Synchronous Serial
Communication Unit (SSU)
LIN Module
CAN module
A/D Converter
1
Hardware LIN: 1 (timer RA, UART0)
One channel, 16 Mailboxes (conforms to the ISO 11898-1)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
Flash Memory
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Operating Frequency/Supply
Voltage
Current consumption
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature
Package
-40 to 85°C (J version)
(2)
-40 to 125°C (K version)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 5 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.5
Item
CPU
Specifications for R8C/34G Group (1)
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.11 Product List for R8C/34G Group.
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
• Power-on reset
Voltage
Detection
I/O Ports
circuit
• Voltage detection 3 (detection level of voltage detection 1 selectable)
Programmable I/O • Input-only: 1 pin
ports
Clock generation
circuits
• CMOS I/O ports: 43, selectable pull-up resistor
Clock
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
Interrupts
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
Watchdog Timer
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
DTC (Data Transfer Controller)
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timer RA
Timer RB
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RD
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE
8 bits × 1
Output compare mode
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 6 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.6
Specifications for R8C/34G Group (2)
Item
Serial
Function
Specification
UART0, 1
UART2
Clock synchronous serial I/O/UART × 2 channel
2
2
(1)
Interface
Clock synchronous serial I/O, UART, I C mode (I C-bus), IE mode (IE BUS ),
multiprocessor communication function
Synchronous Serial
Communication Unit (SSU)
LIN Module
1
Hardware LIN: 1 (timer RA, UART0)
A/D Converter
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
Flash Memory
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Operating Frequency/Supply
Voltage
Current consumption
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature
Package
-40 to 85°C (J version)
(2)
-40 to 125°C (K version)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 7 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.7
Item
CPU
Specifications for R8C/34H Group (1)
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.12 Product List for R8C/34H Group.
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
• Power-on reset
Voltage
Detection
I/O Ports
circuit
• Voltage detection 3 (detection level of voltage detection 1 selectable)
Programmable I/O • Input-only: 1 pin
ports
Clock generation
circuits
• CMOS I/O ports: 43, selectable pull-up resistor
Clock
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
Interrupts
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
Watchdog Timer
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
DTC (Data Transfer Controller)
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timer RA
Timer RB
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RD
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE
8 bits × 1
Output compare mode
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 8 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.8
Specifications for R8C/34H Group (2)
Item
Serial
Function
Specification
UART0, 1
UART2
Clock synchronous serial I/O/UART × 2 channel
2
2
(1)
Interface
Clock synchronous serial I/O, UART, I C mode (I C-bus), IE mode (IE BUS ),
multiprocessor communication function
Synchronous Serial
Communication Unit (SSU)
LIN Module
1
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
A/D Converter
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
Operating Ambient Temperature
Package
-40 to 85°C (J version)
(2)
-40 to 125°C (K version)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 9 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
1.2
Product List
Table 1.9 lists Product List for R8C/34E Group, Table 1.10 lists Product List for R8C/34F Group, Table 1.11 lists
Product List for R8C/34G Group, Table 1.12 lists Product List for R8C/34H Group.
Table 1.9
Product List for R8C/34E Group
Current of Apr. 2008
Package Type Remarks
ROM Capacity
RAM
Part No.
Capacity
Program ROM
Data flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F21346EJFP (D) 32 Kbytes
R5F21347EJFP (D) 48 Kbytes
R5F21348EJFP (D) 64 Kbytes
R5F2134AEJFP (P) 96 Kbytes
R5F2134CEJFP (P) 128 Kbytes
R5F21346EKFP (D) 32 Kbytes
R5F21347EKFP (D) 48 Kbytes
R5F21348EKFP (D) 64 Kbytes
R5F2134AEKFP (P) 96 Kbytes
R5F2134CEKFP (P) 128 Kbytes
2.5 Kbytes PLQP0048KB-A J version
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
2.5 Kbytes PLQP0048KB-A K version
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
(D): Under development
(P): Under planning
Part No. R 5 F 21 34 6 E J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34E Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/34E Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 10 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.10
Product List for R8C/34F Group
Current of Apr. 2008
ROM Capacity
Part No.
RAM Capacity
Package Type
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
R5F21346FJFP (D)
R5F21347FJFP (D)
R5F21348FJFP (D)
R5F2134AFJFP (P)
R5F2134CFJFP (P)
R5F21346FKFP (D)
R5F21347FKFP (D)
R5F21348FKFP (D)
R5F2134AFKFP (P)
R5F2134CFKFP (P)
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
K version
(D): Under development
(P): Under planning
Part No. R 5 F 21 34 6 F J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34F Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Part Number, Memory Size, and Package of R8C/34F Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 11 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.11
Product List for R8C/34G Group
Current of Apr. 2008
ROM Capacity
RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Part No.
Package Type
Remarks
Program ROM
Data flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F21346GJFP (D) 32 Kbytes
R5F21347GJFP (D) 48 Kbytes
R5F21348GJFP (D) 64 Kbytes
R5F2134AGJFP (P) 96 Kbytes
R5F2134CGJFP (P) 128 Kbytes
R5F21346GKFP (D) 32 Kbytes
R5F21347GKFP (D) 48 Kbytes
R5F21348GKFP (D) 64 Kbytes
R5F2134AGKFP (P) 96 Kbytes
R5F2134CGKFP (P) 128 Kbytes
PLQP0048KB-A J version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A K version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
(D): Under development
(P): Under planning
Part No. R 5 F 21 34 6 G J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34G Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Part Number, Memory Size, and Package of R8C/34G Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 12 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.12
Product List for R8C/34H Group
Current of Apr. 2008
ROM Capacity
Part No.
RAM Capacity
Package Type
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
R5F21346HJFP (D)
R5F21347HJFP (D)
R5F21348HJFP (D)
R5F2134AHJFP (P)
R5F2134CHJFP (P)
R5F21346HKFP (D)
R5F21347HKFP (D)
R5F21348HKFP (D)
R5F2134AHKFP (P)
R5F2134CHKFP (P)
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
K version
(D): Under development
(P): Under planning
Part No. R 5 F 21 34 6 H J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34H Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
Part Number, Memory Size, and Package of R8C/34H Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 13 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
1.3
Block Diagram
Figure 1.5 shows a Block Diagram.
8
8
5
1
8
6
8
Port P0
Port P1
I/O ports
Peripheral functions
Port P2
Port P3
Port P4
Port 6
System clock
A/D converter
Timers
generation circuit
(10 bits × 12 channels)
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC (16 bits)
Timer RD
XIN-XOUT
UART or
High-speed on-chip oscillator
Low-speed on-chip oscillator
clock synchronous serial I/O
(8 bits × 2 channels)
(16 bits × 2)
Timer RE (8 bits)
Timer RF (16 bits)
Timer RG (16 bits)
CAN module(3)
(1 channel)
clock synchronous serial I/O
with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
DTC
Watchdog timer
(15 bits)
Memory
R8C/Tiny Series CPU core
ROM (1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM (2)
A0
A1
FB
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. Only in the R8C/34E Group and the R8C/34F Group.
Figure 1.5
Block Diagram
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 14 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
1.4
Pin Assignment
Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 and 1.14 outlines the Pin Name Information by Pin
Number.
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
P1_3/KI3/TRBO/AN11
P1_4/TRCCLK/TXD0
P1_5/(INT1)(1)/(TRAIO)(1)/RXD0
P1_6/CLK0
P0_6/AN1
P0_5/AN2
P0_4/TREO/AN3
R8C/34E Group
R8C/34F Group
R8C/34G Group
R8C/34H Group
VREF/P4_2(3)
P6_0/(TREO)(1)
P1_7/INT1/(TRAIO)(1)
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P6_2/CRX0(2)
P6_1/CTX0(2)
PLQP0048KB-A (48P6Q-A)
(Top view)
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P3_7/(TRAO)(1)/(TXD2)/(SDA2)/(RXD2)/(SCL2)(1)/SSO
P2_6/TRDIOC1
1
2
3
4
5
6
7
8
9
10 11 12
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Only in the R8C/34E Group and the R8C/34F Group.
3. P4_2 is an input-only pin.
4. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.6
Pin Assignment (Top View)
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 15 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.13
Pin Name Information by Pin Number (1)
I/O Pin Functions for of Peripheral Modules
Clock
Synchronous
Serial I/O
with Chip
Select
Pin
A/D Converter
Control Pin
Port
CAN
Module
Number
Interrupt
INT3
Timer
Serial Interface
Voltage Detection
Circuit
(2)
(1)
1
2
P3_5
P3_3
SSCK
(CLK2)
(1)
CTS2/RTS2
(SSI) /SCS
(TXD2)/(SDA2)/
(RXD2)/(SCL2)
(1)
(1)
3
P3_4
SSI/(SCS)
4
MODE
5
P4_3
P4_4
6
7
RESET
XOUT
8
P4_7
P4_6
9
VSS/AVSS
XIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC/AVCC
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P4_5
P6_6
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/
TRDCLK
(TRAIO)
INT1
(1)
CLK0
RXD0
TXD0
(TRAIO)
(1)
(1)
INT1
TRCCLK
TRBO
KI3
AN11
INT0
INT2
ADTRG
(TXD2)/(SDA2)
(1)
TRCIOC
Note:
1. This can be assigned to the pin in parentheses by a program.
2. Only for R8C/34E group and R8C/34F group.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 16 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.14
Pin Name Information by Pin Number (2)
I/O Pin Functions for of Peripheral Modules
Clock
Synchronous
Serial I/O
with Chip
Select
Pin
Number
A/D Converter
Control Pin
Port
CAN
Module
Interrupt
Timer
Serial Interface
Voltage Detection
Circuit
(2)
(RXD2)/(SCL2)
(1)
(1)
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
P6_7
P1_2
P1_1
P1_0
P3_1
P3_0
P6_5
P6_4
P6_3
P0_7
P0_6
P0_5
P0_4
P4_2
P6_0
P6_2
P6_1
P0_3
P0_2
P0_1
P0_0
TRCIOD
TRCIOB
INT3
KI2
KI1
KI0
AN10
AN9
AN8
TRCIOA/
TRCTRG
(TRBO)
(1)
(TRAO)
(1)
(1)
INT4
(CLK2)
LVCMP2
AN0
AN1
AN2
TREO
AN3
VREF
(TREO)
(1)
(2)
CRX0
(2)
CTX0
AN4
AN5
AN6
AN7
(TXD2)/(SDA2)/
(RXD2)/(SCL2)
(1)
(TRAO)
(1)
48
P3_7
SSO
Note:
1. This can be assigned to the pin in parentheses by a program.
2. Only for R8C/34E group and R8C/34F group.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 17 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
1.5
Pin Functions
Tables 1.15 and 1.16 list Pin Functions.
Table 1.15
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input VCC, VSS
−
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
MODE
XIN clock input
RESET
MODE
XIN
I
I
I
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
(1)
the XIN and XOUT pins . To use an external clock, input it
XIN clock output
XOUT
O
to the XIN pin and leave the XOUT pin open.
INT interrupt input INT0 to INT4
I
I
INT interrupt input pins.
Key input interrupt input pins
Key input interrupt
KI0 to KI3
TRAIO
Timer RA
I/O
O
O
I
Timer RA I/O pin
TRAO
Timer RA output pin
Timer RB output pin
External clock input pin
External trigger input pin
Timer RC I/O pins
Timer RB
Timer RC
TRBO
TRCCLK
TRCTRG
I
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
TREO
CLK0, CLK1, CLK2
RXD0, RXD2
TXD0, TXD2
I
O
I/O
I
O
I
External clock input pin
Divided clock output pin
Transfer clock I/O pins
Serial data input pins
Serial data output pins
Transmission control input pin
Timer RE
Serial interface
CTS2
O
Reception control output pin
RTS2
SCL2
SDA2
SSI
2
I/O
I/O
I/O
I/O
I C mode clock I/O pin
2
I C mode data I/O pin
SSU
Data I/O pin
Chip-select signal I/O pin
SCS
SSCK
SSO
I/O
I/O
Clock I/O pin
Data I/O pin
I: Input
Note:
O: Output
I/O: Input and output
1. Refer to the oscillator manufacturer for oscillation characteristics.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 18 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.Overview
Table 1.16
Pin Functions (2)
Item
CAN module
Pin Name
CRX0(2)
CTX0(2)
I/O Type
Description
I
O
I
CAN data input pin
CAN data output pin
Reference voltage VREF
Reference voltage input pin to A/D converter
input
A/D converter
AN0 to AN11
I
I
Analog input pins to A/D converter
AD external trigger input pin
ADTRG
Voltage Detection
Circuit
LVCMP2
I
Detection target voltage pin for voltage detection 2
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_7,
P6_0 to P6_7
I/O
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Input port
P4_2
I
Input-only ports
I: Input
Note:
O: Output
I/O: Input and output
2. Only in the R8C/34E Group and the R8C/34F Group.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 19 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers (1)
R3
A0
A1
FB
Address registers (1)
Frame base register (1)
b19
b15
b0
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
PC
b15
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 20 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 21 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 22 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.Memory
3. Memory
3.1
R8C/34E Group
Figure 3.1 is a Memory Map of R8C/34E Group. The R8C/34E Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated
spaces within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
(2)
SFR
0FFDCh
0FFFFh
Undefined instruction
Overflow
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
03000h
BRK instruction
Internal ROM
(data flash) (1)
Address match
Single step
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The DataFlash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).
2. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Internal RAM
Address 0XXXXh
Part Number
Address ZZZZZh
Size
Address 0YYYYh
Size
R5F21346EJFP, R5F21346EKFP
R5F21347EJFP, R5F21347EKFP
R5F21348EJFP, R5F21348EKFP
R5F2134AEJFP, R5F2134AEKFP
R5F2134CEJFP, R5F2134CEKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
08000h
04000h
04000h
04000h
04000h
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
00DFFh
013FFh
01BFFh
023FFh
02BFFh
13FFFh
1BFFFh
23FFFh
Figure 3.1
Memory Map of R8C/34E Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 23 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.Memory
3.2
R8C/34F Group
Figure 3.2 is a Memory Map of R8C/34F Group. The R8C/34F Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated
spaces within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
(1)
SFR
0FFDCh
0FFFFh
Undefined instruction
Overflow
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
03000h
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
0FFFFh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Internal RAM
Address 0XXXXh
Address ZZZZZh
Size
Address 0YYYYh
Size
R5F21346FJFP, R5F21346FKFP
R5F21347FJFP, R5F21347FKFP
R5F21348FJFP, R5F21348FKFP
R5F2134AFJFP, R5F2134AFKFP
R5F2134CFJFP, R5F2134CFKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
08000h
04000h
04000h
04000h
04000h
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
00DFFh
013FFh
01BFFh
023FFh
02BFFh
13FFFh
1BFFFh
23FFFh
Figure 3.2
Memory Map of R8C/34F Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 24 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.Memory
3.3
R8C/34G Group
Figure 3.3 is a Memory Map of R8C/34G Group. The R8C/34G Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
(2)
SFR
0FFDCh
0FFFFh
Undefined instruction
Overflow
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
03000h
BRK instruction
Internal ROM
(data flash) (1)
Address match
Single step
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The DataFlash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).
2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Internal RAM
Address 0XXXXh
Part Number
Address ZZZZZh
Size
Address 0YYYYh
Size
R5F21346GJFP, R5F21346GKFP
R5F21347GJFP, R5F21347GKFP
R5F21348GJFP, R5F21348GKFP
R5F2134AGJFP, R5F2134AGKFP
R5F2134CGJFP, R5F2134CGKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
08000h
04000h
04000h
04000h
04000h
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
00DFFh
013FFh
01BFFh
023FFh
02BFFh
13FFFh
1BFFFh
23FFFh
Figure 3.3
Memory Map of R8C/34G Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 25 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.Memory
3.4
R8C/34H Group
Figure 3.4 is a Memory Map of R8C/34H Group. The R8C/34H Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
(1)
SFR
0FFDCh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
03000h
Single step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
0YYYYh
0FFFFh
Internal ROM
(Reserved)
Reset
(program ROM)
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Internal RAM
Address 0XXXXh
Address ZZZZZh
Size
Address 0YYYYh
Size
R5F21346HJFP, R5F21346HKFP
R5F21347HJFP, R5F21347HKFP
R5F21348HJFP, R5F21348HKFP
R5F2134AHJFP, R5F2134AHKFP
R5F2134CHJFP, R5F2134CHKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
08000h
04000h
04000h
04000h
04000h
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
00DFFh
013FFh
01BFFh
023FFh
02BFFh
13FFFh
1BFFFh
23FFFh
Figure 3.4
Memory Map of R8C/34H Group
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 26 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.17 list the special
function registers.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Register
Symbol
After reset
Processor Mode Register 0
PM0
PM1
CM0
CM1
00h
00h
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
00101000b
00100000b
00h
MSTCR
CM3
00h
00h
PRCR
RSTFR
OCD
(2)
0XXX00XXb
00000100b
XXh
WDTR
WDTS
WDTC
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
Count Source Protection Mode Register
FRA7
CSPR
When shipping
00h
(3)
10000000b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
00h
FRA1
When shipping
FRA2
OCVREFCR
00h
00h
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
FRA4
FRA5
FRA6
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
(4)
00h
(5)
00100000b
0035h
0036h
0037h
0038h
Voltage Detection 1 Level Select Register
Voltage Monitor 0 Circuit Control Register
Voltage Monitor 1 Circuit Control Register
VD1LS
VW0C
VW1C
00000111b
(4)
(5)
1100X010b
1100X011b
0039h
10001010b
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Software reset, watchdog timer reset, or oscillation
stop detection reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 27 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Symbol
After reset
10000010b
Voltage Monitor 2 Circuit Control Register
VW2C
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT4 Interrupt Control Register
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
ADIC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register
SSUIC
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
S0TIC
S0RIC
XXXXX000b
XXXXX000b
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
INT2IC
TRAIC
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
UART2 Bus Collision Detection Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
CAN0 Receive FIFO Interrupt Control Register
CAN0 Transmit FIFO Interrupt Control Register
CAN0 Error Interrupt Control Register
CAN0 Wake-up Interrupt Control Register
Voltage Monitor 1 Level Interrupt Control Register
Voltage Monitor 2 Level Interrupt Control Register
C0RIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
C0TIC
C0FRIC
C0FTIC
C0EIC
C0WIC
VCMP1IC
VCMP2IC
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 28 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
DTCTL
After reset
DTC Activation Control Register
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00000010b
XXh
XXh
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2MR
U2BRG
U2TB
00h
XXh
UART2 Transmit Buffer Register
XXh
XXh
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00001000b
00000010b
XXh
XXh
00h
UART2 Digital Filter Function Select Register
URXDF
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 29 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After reset
A/D Register 0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXh
000000XXb
XXh
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Mode Register
ADMOD
ADINSEL
ADCON0
ADCON1
00h
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
11000000b
00h
00h
Port P0 Register
Port P1 Register
P0
P1
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
PD0
PD1
P2
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P4 Direction Register
Port P6 Register
PD4
P6
00h
XXh
00h
Port P6 Direction Register
PD6
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 30 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.5
SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LIN0CR2
LIN0CR
LIN0ST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
After reset
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
LIN0 Control Register 2
LIN0 Control Register
LIN0 Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Timer RE Counter Data Register
Timer RE Compare Data Register
TRESEC
TREMIN
00h
00h
Timer RE Control Register 1
Timer RE Control Register 2
TRECR1
TRECR2
TRECSR
00h
00h
Timer RE Count Source Select Register
00001000b
Timer RC Mode Register
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
00h
Timer RC General Register A
Timer RC General Register B
Timer RC General Register C
Timer RC General Register D
TRCGRA
TRCGRB
TRCGRC
TRCGRD
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RC Control Register 2
TRCCR2
TRCDF
TRCOER
TRCADCR
00011000b
00h
01111111b
00h
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
Timer RD Trigger Control Register
Timer RD Start Register
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
00h
00h
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 31 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.6
SFR Information (6)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After reset
Timer RD Control Register 0
TRDCR0
00h
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
10001000b
10001000b
11100000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
00h
Timer RD General Register A0
Timer RD General Register B0
Timer RD General Register C0
Timer RD General Register D0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RD Control Register 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
00h
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
10001000b
10001000b
11000000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
00h
Timer RD General Register A1
Timer RD General Register B1
Timer RD General Register C1
Timer RD General Register D1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 32 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.7
SFR Information (7)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
TRASR
After reset
Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Timer RD Pin Select Register 0
Timer RD Pin Select Register 1
Timer Pin Select Register
00h
00h
00h
00h
00h
00h
00h
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
TIMSR
UART0 Pin Select Register
U0SR
00h
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU Pin Select Register
U2SR0
00h
00h
00h
U2SR1
SSUIICSR
INT Interrupt Input Pin Select Register
INTSR
00h
SS Bit Counter Register
SS Transmit Data Register
SSBR
SSTDR
11111000b
FFh
FFh
SS Receive Data Register
SSRDR
FFh
FFh
SS Control Register H
SS Control Register L
SS Mode Register
SS Enable Register
SS Status Register
SS Mode Register 2
SSCRH
SSCRL
SSMR
SSER
SSSR
SSMR2
00h
01111101b
00011000b
00h
00h
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 33 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.8
SFR Information (8)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Register
Symbol
RMAD0
After reset
Address Match Interrupt Register 0
XXh
XXh
0000XXXXb
00h
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
XXh
XXh
0000XXXXb
00h
Address Match Interrupt Enable Register 1
AIER1
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
00h
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
VLT0
VLT1
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 34 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.9
SFR Information (9)
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
Register
Symbol
After reset
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
DTCD0
DTC Control Data 1
DTC Control Data 2
DTC Control Data 3
DTC Control Data 4
DTC Control Data 5
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 35 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.10
SFR Information (10)
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
Register
Symbol
DTCD6
After reset
DTC Control Data 6
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 7
DTC Control Data 8
DTC Control Data 9
DTC Control Data 10
DTC Control Data 11
DTC Control Data 12
DTC Control Data 13
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 36 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.11
SFR Information (11)
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
Register
Symbol
DTCD14
After reset
DTC Control Data 14
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 15
DTC Control Data 16
DTC Control Data 17
DTC Control Data 18
DTC Control Data 19
DTC Control Data 20
DTC Control Data 21
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 37 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.12
SFR Information (12)
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
:
Register
Symbol
DTCD22
After reset
DTC Control Data 22
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 23
DTCD23
2E00h
2E01h
2E02h
2E03h
2E04h
2E05h
2E06h
2E07h
2E08h
2E09h
2E0Ah
2E0Bh
2E0Ch
2E0Dh
2E0Eh
2E0Fh
2E10h
2E11h
2E12h
2E13h
2E14h
2E15h
2E16h
2E17h
2E18h
2E19h
2E1Ah
2E1Bh
2E1Ch
2E1Dh
2E1Eh
2E1Fh
2E20h
2E21h
2E22h
2E23h
2E24h
2E25h
2E26h
2E27h
2E28h
2E29h
2E2Ah
2E2Bh
2E2Ch
2E2Dh
2E2Eh
2E2Fh
CAN0 Mailbox 0 : Message ID
C0MB0
XXXX XXXXh
CAN0 Mailbox 0 : Data length
CAN0 Mailbox 0 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox 0 : Time stamp
CAN0 Mailbox 1 : Message ID
XXXXh
C0MB1
XXXX XXXXh
CAN0 Mailbox 1 : Data length
CAN0 Mailbox 1 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox 1 : Time stamp
CAN0 Mailbox 2 : Message ID
XXXXh
C0MB2
XXXX XXXXh
CAN0 Mailbox 2 : Data length
CAN0 Mailbox 2 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox 2 : Time stamp
XXXXh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 38 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.13
SFR Information (13)
Address
2E30h
2E31h
2E32h
2E33h
2E34h
2E35h
2E36h
2E37h
2E38h
2E39h
2E3Ah
2E3Bh
2E3Ch
2E3Dh
2E3Eh
2E3Fh
2E40h
2E41h
2E42h
2E43h
2E44h
2E45h
2E46h
2E47h
2E48h
2E49h
2E4Ah
2E4Bh
2E4Ch
2E4Dh
2E4Eh
2E4Fh
2E50h
2E51h
2E52h
2E53h
2E54h
2E55h
2E56h
2E57h
2E58h
2E59h
2E5Ah
2E5Bh
2E5Ch
2E5Dh
2E5Eh
2E5Fh
2E60h
2E61h
2E62h
2E63h
2E64h
2E65h
2E66h
2E67h
2E68h
2E69h
2E6Ah
2E6Bh
2E6Ch
2E6Dh
2E6Eh
2E6Fh
Register
Symbol
C0MB3
After reset
XXXX XXXXh
CAN0 Mailbox 3 : Message ID
CAN0 Mailbox 3 : Data length
CAN0 Mailbox 3 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox3 : Time stamp
CAN0 Mailbox4 : Message ID
XXXXh
C0MB4
C0MB5
C0MB6
XXXX XXXXh
CAN0 Mailbox4 : Data length
CAN0 Mailbox4 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox4 : Time stamp
CAN0 Mailbox5 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox5 : Data length
CAN0 Mailbox5 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox5 : Time stamp
CAN0 Mailbox6 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox6 : Data length
CAN0 Mailbox6 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox6 : Time stamp
XXXXh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 39 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.14
SFR Information (14)
Address
2E70h
2E71h
2E72h
2E73h
2E74h
2E75h
2E76h
2E77h
2E78h
2E79h
2E7Ah
2E7Bh
2E7Ch
2E7Dh
2E7Eh
2E7Fh
2E80h
2E81h
2E82h
2E83h
2E84h
2E85h
2E86h
2E87h
2E88h
2E89h
2E8Ah
2E8Bh
2E8Ch
2E8Dh
2E8Eh
2E8Fh
2E90h
2E91h
2E92h
2E93h
2E94h
2E95h
2E96h
2E97h
2E98h
2E99h
2E9Ah
2E9Bh
2E9Ch
2E9Dh
2E9Eh
2E9Fh
2EA0h
2EA1h
2EA2h
2EA3h
2EA4h
2EA5h
2EA6h
2EA7h
2EA8h
2EA9h
2EAAh
2EABh
2EACh
2EADh
2EAEh
2EAFh
Register
Symbol
C0MB7
After reset
XXXX XXXXh
CAN0 Mailbox7 : Message ID
CAN0 Mailbox7 : Data length
CAN0 Mailbox7 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox7 : Time stamp
CAN0 Mailbox8 : Message ID
XXXXh
C0MB8
C0MB9
C0MB10
XXXX XXXXh
CAN0 Mailbox8 : Data length
CAN0 Mailbox8 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox8 : Time stamp
CAN0 Mailbox9 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox9 : Data length
CAN0 Mailbox9 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox9 : Time stamp
CAN0 Mailbox10 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox10 : Data length
CAN0 Mailbox10 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox10 : Time stamp
XXXXh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 40 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.15
SFR Information (15)
Address
2EB0h
2EB1h
2EB2h
2EB3h
2EB4h
2EB5h
2EB6h
2EB7h
2EB8h
2EB9h
2EBAh
2EBBh
2EBCh
2EBDh
2EBEh
2EBFh
2EC0h
2EC1h
2EC2h
2EC3h
2EC4h
2EC5h
2EC6h
2EC7h
2EC8h
2EC9h
2ECAh
2ECBh
2ECCh
2ECDh
2ECEh
2ECFh
2ED0h
2ED1h
2ED2h
2ED3h
2ED4h
2ED5h
2ED6h
2ED7h
2ED8h
2ED9h
2EDAh
2EDBh
2EDCh
2EDDh
2EDEh
2EDFh
2EE0h
2EE1h
2EE2h
2EE3h
2EE4h
2EE5h
2EE6h
2EE7h
2EE8h
2EE9h
2EEAh
2EEBh
2EECh
2EEDh
2EEEh
2EEFh
Register
Symbol
C0MB11
After reset
XXXX XXXXh
CAN0 Mailbox11 : Message ID
CAN0 Mailbox11 : Data length
CAN0 Mailbox11 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox11 : Time stamp
CAN0 Mailbox12 : Message ID
XXXXh
C0MB12
C0MB13
C0MB14
XXXX XXXXh
CAN0 Mailbox12 : Data length
CAN0 Mailbox12 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox12 : Time stamp
CAN0 Mailbox13 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox13 : Data length
CAN0 Mailbox13 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox13 : Time stamp
CAN0 Mailbox14 : Message ID
XXXXh
XXXX XXXXh
CAN0 Mailbox14 : Data length
CAN0 Mailbox14 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox14 : Time stamp
XXXXh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 41 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.16
SFR Information (16)
Address
2EF0h
2EF1h
2EF2h
2EF3h
2EF4h
2EF5h
2EF6h
2EF7h
2EF8h
2EF9h
2EFAh
2EFBh
2EFCh
2EFDh
2EFEh
2EFFh
2F00h
2F01h
2F02h
2F03h
2F04h
2F05h
2F06h
2F07h
2F08h
2F09h
2F0Ah
2F0Bh
2F0Ch
2F0Dh
2F0Eh
2F0Fh
2F10h
2F11h
2F12h
2F13h
2F14h
2F15h
2F16h
2F17h
2F18h
2F19h
2F1Ah
2F1Bh
2F1Ch
2F1Dh
2F1Eh
2F1Fh
2F20h
2F21h
2F22h
2F23h
2F24h
2F25h
2F26h
2F27h
2F28h
2F29h
2F2Ah
2F2Bh
2F2Ch
2F2Dh
2F2Eh
2F2Fh
2F30h
2F31h
2F32h
2F33h
2F34h
2F35h
2F36h
2F37h
2F38h
2F39h
2F3Ah
Register
Symbol
C0MB15
After reset
XXXX XXXXh
CAN0 Mailbox15 : Message ID
CAN0 Mailbox15 : Data length
CAN0 Mailbox15 : Data field
XXh
XXXX XXXX
XXXX XXXXh
CAN0 Mailbox15 : Time stamp
XXXXh
CAN0 Mask Register 0
CAN0 Mask Register 1
CAN0 Mask Register 2
CAN0 Mask Register 3
C0MKR0
C0MKR1
C0MKR2
C0MKR3
C0FIDCR0
C0FIDCR1
XXXX XXXXh
XXXX XXXXh
XXXX XXXXh
XXXX XXXXh
XXXX XXXXh
XXXX XXXXh
CAN0 FIFO Received ID Compare Register 0
CAN0 FIFO Received ID Compare Register 1
CAN0 Mask Invalid Register
C0MKIVLR
C0MIER
XXXXh
XXXXh
CAN0 Mailbox Interrupt Enable Register
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 42 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4. Special Function Registers (SFRs)
(1)
Table 4.17
SFR Information (17)
Address
2F3Bh
2F3Ch
2F3Dh
2F3Eh
2F3Fh
2F40h
2F41h
2F42h
2F43h
2F44h
2F45h
2F46h
2F47h
2F48h
2F49h
2F4Ah
2F4Bh
2F4Ch
2F4Dh
2F4Eh
2F4Fh
2F50h
2F51h
2F52h
2F53h
2F54h
2F55h
2F56h
2F57h
2F58h
:
Register
Symbol
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0CTLR
After reset
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
CAN0 Control Register
00h
00h
00h
00h
00h
0000 0101b
0000 0000b
0000 0101b
0000 0000b
00 0000h
CAN0 Status Register
C0STR
C0BCR
CAN0 Bit Configuration Register
CAN0 Receive FIFO Control Register
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
1000 0000b
XXh
1000 0000b
XXh
CAN0 Receive FIFO Pointer Control Register
CAN0 Transmit FIFO Control Register
CAN0 Transmit FIFO Pointer Control Register
CAN0 Error Interrupt Enable Register
CAN0 Error Interrupt Factor Judge Register
CAN0 Reception Error Count Register
CAN0 Transmission Error Count Register
CAN0 Error Code Store Register
00h
C0EIFR
00h
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
C0TSR
00h
00h
00h
CAN0 Channel Search Support Register
CAN0 Mailbox Search Status Register
CAN0 Mailbox Search Mode Register
CAN0 Time Stamp Register
XXh
1000 0000b
XXXX XX00b
0000h
CAN0 Acceptance Filter Support Register
CAN0 Test Control Register
C0AFSR
C0TCR
OFS2
XXXXh
00h
FFDBh
:
Option Function Select Register 2
Option Function Select Register
(Note 2)
(Note 2)
FFFFh
OFS
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register cannot be changed by a program. Use a flash programmer to write to it.
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 43 of 44
Preliminary specification
Under development
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
37
24
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
6.9 7.0 7.1
6.9 7.0 7.1
1.4
Terminal cross section
48
13
A2
HD
HE
A
8.8 9.0 9.2
8.8 9.0 9.2
1.7
1
12
Index mark
ZD
A1
bp
b1
c
0
0.1 0.2
0.17 0.22 0.27
0.20
F
0.145
0.125
0.09
0.20
L
c1
L1
0°
8°
e
0.5
y
*3
x
Detail F
0.08
0.10
bp
e
x
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
REJ03B0246-0010 Rev.0.10 Apr 17, 2008
Page 44 of 44
REVISION HISTORY
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Shortsheet
Description
Summary
Rev.
0.10
Date
Page
−
Apr 17, 2008
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
C - 1
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <65> 6213-0200, Fax: <65> 6278-8001
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Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2
相关型号:
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FLASH, 20MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
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FLASH, 20MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
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