R5F21347EJFP_技术文档

Preliminary DATASHEET

Specifications in this document are tentative and subject to change.

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

REJ03B0312-0010

Rev.0.10

RENESAS MCU

Apr 09, 2010

1. Overview

1.1

Features

The R8C/34W Group, R8C/34X Group, R8C/34Y Group, and R8C/34Z Group of single-chip MCUs incorporate

the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address

space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for

high-speed operation processing.

Power consumption is low, and the supported operating modes allow additional power control. These MCUs are

designed to maximize EMI/EMS performance.

Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of

system components.

The R8C/34W Group and R8C/34X Group have a single channel CAN module and are suitable for LAN systems in

vehicles and for FA.

The R8C/34Y Group and R8C/34Z Group do not have CAN modules.

The R8C/34W Group and R8C/34Y Group have data flash (1 KB × 4 blocks) with the background operation

(BGO) function.

1.1.1

Applications

Automobiles and others

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 1 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

1.1.2

Specifications

Tables 1.1 and 1.2 outline the Specifications for R8C/34W Group, tables 1.3 and 1.4 outline the Specifications

for R8C/34X Group, tables 1.5 and 1.6 outline the Specifications for R8C/34Y Group, and tables 1.7 and 1.8

outline the Specifications for R8C/34Z Group.

Table 1.1

Item

Specifications for R8C/34W Group (1)

Function

Specification

CPU

Central processing R8C CPU core

unit

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operating mode: Single-chip mode (address space: 1 Mbyte)

Refer to Table 1.9 Product List for R8C/34W Group.

Memory

ROM, RAM, Data

flash

Power Supply Voltage detection

• Power-on reset

Voltage

circuit

• Voltage detection 3 (detection level of voltage detection 1 selectable)

Detection

I/O Ports

Programmable I/O • Input-only: 1 pin

ports

• CMOS I/O ports: 43, selectable pull-up resistor

Clock

Clock generation

circuits

3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,

low-speed on-chip oscillator), wait mode, stop mode

• Interrupt vectors: 69

Interrupts

• External: 9 sources (INT × 5, key input × 4)

• Priority levels: 7 levels

Watchdog Timer

• 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

• 1 channel

DTC (Data Transfer Controller)

• Activation sources: 31

• Transfer modes: 2 (normal mode, repeat mode)

Timer

Timer RA

Timer RB

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programmable wait one-

shot generation mode

Timer RC

Timer RD

16 bits (with 4 capture/compare registers) × 1

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

16 bits (with 4 capture/compare registers) × 2

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

Timer RE

8 bits × 1

Output compare mode

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 2 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.2

Item

Serial

Specifications for R8C/34W Group (2)

Function

UART0

Specification

1 channel

Clock synchronous serial I/O, UART

Interface

UART2

1 channel

Clock synchronous serial I/O, UART, I²C mode (I²C-bus), IE mode (IEBus),

multiprocessor communication function

Synchronous Serial

Communication Unit (SSU)

LIN Module

1 channel

Hardware LIN: 1 (timer RA, UART0)

CAN Module

1 channel, 16 Mailboxes (conforms to the ISO 11898-1)

A/D Converter

10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

Flash Memory

• Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 10,000 times (data flash)

1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

• Background operation (BGO) function (data flash)

f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

Operating Frequency/Supply

Voltage

Current Consumption

Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -40 to 85°C (J version)

-40 to 125°C (K version) ⁽¹⁾

Package

Note:

48-pin LQFP

Package code: PLQP0048KB-A (previous code: 48P6Q-A)

1. Specify the K version if K version functions are to be used.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 3 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.3

Specifications for R8C/34X Group (1)

Item

CPU

Function

Specification

Central processing R8C CPU core

unit

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operating mode: Single-chip mode (address space: 1 Mbyte)

Refer to Table 1.10 Product List for R8C/34X Group.

Memory

ROM, RAM, Data

flash

Power Supply Voltage detection

• Power-on reset

Voltage

circuit

• Voltage detection 3 (detection level of voltage detection 1 selectable)

Detection

I/O Ports

Programmable I/O • Input-only: 1 pin

ports

Clock generation

circuits

• CMOS I/O ports: 43, selectable pull-up resistor

3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

Clock

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,

low-speed on-chip oscillator), wait mode, stop mode

• Interrupt vectors: 69

Interrupts

• External: 9 sources (INT × 5, key input × 4)

• Priority levels: 7 levels

Watchdog Timer

• 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

• 1 channel

DTC (Data Transfer Controller)

• Activation sources: 31

• Transfer modes: 2 (normal mode, repeat mode)

Timer

Timer RA

Timer RB

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programmable wait one-

shot generation mode

Timer RC

Timer RD

16 bits (with 4 capture/compare registers) × 1

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

16 bits (with 4 capture/compare registers) × 2

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

Timer RE

8 bits × 1

Output compare mode

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 4 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.4

Item

Serial

Specifications for R8C/34X Group (2)

Function

UART0

Specification

1 channel

Clock synchronous serial I/O, UART

Interface

UART2

1 channel

Clock synchronous serial I/O, UART, I²C mode (I²C-bus), IE mode (IEBus),

multiprocessor communication function

Synchronous Serial

Communication Unit (SSU)

LIN Module

1 channel

Hardware LIN: 1 (timer RA, UART0)

CAN Module

1 channel, 16 Mailboxes (conforms to the ISO 11898-1)

A/D Converter

10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

Flash Memory

• Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 100 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

Operating Frequency/Supply

Voltage

Current Consumption

Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -40 to 85°C (J version)

-40 to 125°C (K version) ⁽¹⁾

Package

Note:

48-pin LQFP

Package code: PLQP0048KB-A (previous code: 48P6Q-A)

1. Specify the K version if K version functions are to be used.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 5 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.5

Specifications for R8C/34Y Group (1)

Item

CPU

Function

Specification

Central processing R8C CPU core

unit

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operating mode: Single-chip mode (address space: 1 Mbyte)

Refer to Table 1.11 Product List for R8C/34Y Group.

Memory

ROM, RAM, Data

flash

Power Supply Voltage detection

• Power-on reset

Voltage

circuit

• Voltage detection 3 (detection level of voltage detection 1 selectable)

Detection

I/O Ports

Programmable I/O • Input-only: 1 pin

ports

Clock generation

circuits

• CMOS I/O ports: 43, selectable pull-up resistor

3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

Clock

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,

low-speed on-chip oscillator), wait mode, stop mode

• Interrupt vectors: 69

Interrupts

• External: 9 sources (INT × 5, key input × 4)

• Priority levels: 7 levels

Watchdog Timer

• 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

• 1 channel

DTC (Data Transfer Controller)

• Activation sources: 31

• Transfer modes: 2 (normal mode, repeat mode)

Timer

Timer RA

Timer RB

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programmable wait one-

shot generation mode

Timer RC

Timer RD

16 bits (with 4 capture/compare registers) × 1

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

16 bits (with 4 capture/compare registers) × 2

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

Timer RE

8 bits × 1

Output compare mode

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 6 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.6

Item

Serial

Specifications for R8C/34Y Group (2)

Function

UART0

Specification

1 channel

Clock synchronous serial I/O, UART

Interface

UART2

1 channel

Clock synchronous serial I/O, UART, I²C mode (I²C-bus), IE mode (IEBus),

multiprocessor communication function

Synchronous Serial

Communication Unit (SSU)

LIN Module

1 channel

Hardware LIN: 1 (timer RA, UART0)

A/D Converter

10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

Flash Memory

• Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 10,000 times (data flash)

1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

• Background operation (BGO) function (data flash)

f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

Operating Frequency/Supply

Voltage

Current Consumption

Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -40 to 85°C (J version)

-40 to 125°C (K version) ⁽¹⁾

Package

Note:

48-pin LQFP

Package code: PLQP0048KB-A (previous code: 48P6Q-A)

1. Specify the K version if K version functions are to be used.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 7 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.7

Specifications for R8C/34Z Group (1)

Item

CPU

Function

Specification

Central processing R8C CPU core

unit

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operating mode: Single-chip mode (address space: 1 Mbyte)

Refer to Table 1.12 Product List for R8C/34Z Group.

Memory

ROM, RAM, Data

flash

Power Supply Voltage detection

• Power-on reset

Voltage

circuit

• Voltage detection 3 (detection level of voltage detection 1 selectable)

Detection

I/O Ports

Programmable I/O • Input-only: 1 pin

ports

Clock generation

circuits

• CMOS I/O ports: 43, selectable pull-up resistor

3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),

Clock

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, high-speed on-chip oscillator,

low-speed on-chip oscillator), wait mode, stop mode

• Interrupt vectors: 69

Interrupts

• External: 9 sources (INT × 5, key input × 4)

• Priority levels: 7 levels

Watchdog Timer

• 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

• 1 channel

DTC (Data Transfer Controller)

• Activation sources: 31

• Transfer modes: 2 (normal mode, repeat mode)

Timer

Timer RA

Timer RB

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

8 bits (with 8-bit prescaler) × 1

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programmable wait one-

shot generation mode

Timer RC

Timer RD

16 bits (with 4 capture/compare registers) × 1

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

16 bits (with 4 capture/compare registers) × 2

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

Timer RE

8 bits × 1

Output compare mode

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 8 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.8

Item

Serial

Specifications for R8C/34Z Group (2)

Function

UART0

Specification

1 channel

Clock synchronous serial I/O, UART

Interface

UART2

1 channel

Clock synchronous serial I/O, UART, I²C mode (I²C-bus), IE mode (IEBus),

multiprocessor communication function

Synchronous Serial

Communication Unit (SSU)

LIN Module

1 channel

Hardware LIN: 1 (timer RA, UART0)

A/D Converter

10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

Flash Memory

• Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 100 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

Operating Frequency/Supply

Voltage

Current Consumption

Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Operating Ambient Temperature -40 to 85°C (J version)

-40 to 125°C (K version) ⁽¹⁾

Package

Note:

48-pin LQFP

Package code: PLQP0048KB-A (previous code: 48P6Q-A)

1. Specify the K version if K version functions are to be used.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 9 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

1.2

Product List

Table 1.9 lists Product List for R8C/34W Group, Table 1.10 lists Product List for R8C/34X Group, Table 1.11 lists

Product List for R8C/34Y Group, and Table 1.12 lists Product List for R8C/34Z Group.

Table 1.9

Product List for R8C/34W Group

Current of Apr. 2010

Package Type Remarks

ROM Capacity

RAM

Capacity

Part No.

Program ROM

Data flash

1 Kbyte × 4

R5F21346WJFP (D) 32 Kbytes

R5F21347WJFP (D) 48 Kbytes

R5F21348WJFP (D) 64 Kbytes

R5F2134AWJFP (D) 96 Kbytes

R5F2134CWJFP (D) 128 Kbytes

R5F21346WKFP (D) 32 Kbytes

R5F21347WKFP (D) 48 Kbytes

R5F21348WKFP (D) 64 Kbytes

R5F2134AWKFP (D) 96 Kbytes

R5F2134CWKFP (D) 128 Kbytes

2.5 Kbytes PLQP0048KB-A J version

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

2.5 Kbytes PLQP0048KB-A K version

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

(D): Under development

Part No. R 5 F 21 34 6 W J FP

Package type:

FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)

CAN, Data Flash

W: CAN module and Data Flash

X : CAN module but no Data Flash

Y : Data Flash but no CAN module

Z : None

Classification

J: Operating ambient temperature −40 °C to 85 °C

K: Operating ambient temperature −40 °C to 125 °C

ROM capacity

6: 32 KB

7: 48 KB

8: 64 KB

A: 96 KB

C: 128 KB

R8C/34W Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.1

Part Number, Memory Size, and Package of R8C/34W Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 10 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.10

Product List for R8C/34X Group

Current of Apr. 2010

Remarks

J version

ROM Capacity

Part No.

RAM Capacity

Package Type

Program ROM

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

R5F21346XJFP (D)

R5F21347XJFP (D)

R5F21348XJFP (D)

R5F2134AXJFP (D)

R5F2134CXJFP (D)

R5F21346XKFP (D)

R5F21347XKFP (D)

R5F21348XKFP (D)

R5F2134AXKFP (D)

R5F2134CXKFP (D)

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

K version

(D): Under development

Part No. R 5 F 21 34 6 X J FP

Package type:

FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)

CAN, Data Flash

W: CAN module and Data Flash

X : CAN module but no Data Flash

Y : Data Flash but no CAN module

Z : None

Classification

J: Operating ambient temperature −40 °C to 85 °C

K: Operating ambient temperature −40 °C to 125 °C

ROM capacity

6: 32 KB

7: 48 KB

8: 64 KB

A: 96 KB

C: 128 KB

R8C/34X Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.2

Part Number, Memory Size, and Package of R8C/34X Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 11 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.11

Product List for R8C/34Y Group

Current of Apr. 2010

Package Type Remarks

ROM Capacity

RAM

Capacity

Part No.

Program ROM

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

32 Kbytes

48 Kbytes

64 Kbytes

Data flash

1 Kbyte × 4

R5F21346YJFP (D)

R5F21347YJFP (D)

R5F21348YJFP (D)

R5F2134AYJFP (D)

R5F2134CYJFP (D)

R5F21346YKFP (D)

R5F21347YKFP (D)

R5F21348YKFP (D)

2.5 Kbytes PLQP0048KB-A J version

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

2.5 Kbytes PLQP0048KB-A K version

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

R5F2134AYKFP (D) 96 Kbytes

R5F2134CYKFP (D) 128 Kbytes

(D): Under development

Part No. R 5 F 21 34 6 Y J FP

Package type:

FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)

CAN, Data Flash

W: CAN module and Data Flash

X : CAN module but no Data Flash

Y : Data Flash but no CAN module

Z : None

Classification

J: Operating ambient temperature −40 °C to 85 °C

K: Operating ambient temperature −40 °C to 125 °C

ROM capacity

6: 32 KB

7: 48 KB

8: 64 KB

A: 96 KB

C: 128 KB

R8C/34Y Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.3

Part Number, Memory Size, and Package of R8C/34Y Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 12 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.12

Product List for R8C/34Z Group

Current of Apr. 2010

Remarks

J version

ROM Capacity

Part No.

RAM Capacity

Package Type

Program ROM

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

R5F21346ZJFP (D)

R5F21347ZJFP (D)

R5F21348ZJFP (D)

R5F2134AZJFP (D)

R5F2134CZJFP (D)

R5F21346ZKFP (D)

R5F21347ZKFP (D)

R5F21348ZKFP (D)

R5F2134AZKFP (D)

R5F2134CZKFP (D)

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

PLQP0048KB-A

K version

(D): Under development

Part No. R 5 F 21 34 6 Z J FP

Package type:

FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)

CAN, Data Flash

W: CAN module and Data Flash

X : CAN module but no Data Flash

Y : Data Flash but no CAN module

Z : None

Classification

J: Operating ambient temperature −40 °C to 85 °C

K: Operating ambient temperature −40 °C to 125 °C

ROM capacity

6: 32 KB

7: 48 KB

8: 64 KB

A: 96 KB

C: 128 KB

R8C/34Z Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.4

Part Number, Memory Size, and Package of R8C/34Z Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 13 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

1.3

Block Diagram

Figure 1.5 shows a Block Diagram.

8

5

1

8

6

8

Port P0

Port P1

I/O ports

Peripheral functions

Port P2

Port P3

Port P4

Port 6

System clock

generation circuit

A/D converter

(10 bits × 12 channels)

Timers

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

Timer RA (8 bits)

Timer RB (8 bits)

Timer RC (16 bits)

Timer RD

UART or

clock synchronous serial I/O

(8 bits × 2 channels)

(16 bits × 2)

Timer RE (8 bits)

CAN module ⁽³⁾

(1 channel)

SSU

(8 bits × 1 channel)

LIN module

(1 channel)

DTC

Watchdog timer

(14 bits)

Memory

R8C CPU core

ROM ⁽¹⁾

R0H

R1H

R0L

R1L

SB

USP

ISP

INTB

PC

FLG

R2

R3

RAM ⁽²⁾

A0

A1

FB

Multiplier

Notes:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

3. Only in the R8C/34W Group and R8C/34X Group.

Figure 1.5

Block Diagram

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 14 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

1.4

Pin Assignment

Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 and 1.14 outline the Pin Name Information by Pin

Number.

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

P0_6/AN1

P1_3/KI3/TRBO/AN11

P1_4/TRCCLK/TXD0

P1_5/(INT1)⁽¹⁾/(TRAIO)⁽¹⁾/RXD0

P1_6/CLK0

P1_7/INT1/(TRAIO)⁽¹⁾

P2_0/TRDIOA0/TRDCLK

P2_1/TRDIOB0

P0_5/AN2

P0_4/TREO/AN3

VREF/P4_2⁽³⁾

P6_0/(TREO)⁽¹⁾

P6_2/CRX0⁽²⁾

R8C/34W Group

R8C/34X Group

R8C/34Y Group

R8C/34Z Group

P6_1/CTX0⁽²⁾

PLQP0048KB-A (48P6Q-A)

(Top view)

P0_3/AN4

P2_2/TRDIOC0

P0_2/AN5

P2_3/TRDIOD0

P0_1/AN6

P2_4/TRDIOA1

P0_0/AN7

P2_5/TRDIOB1

P3_7/(TRAO)⁽¹⁾/(TXD2)/(SDA2)/(RXD2)/(SCL2)⁽¹⁾/SSO

P2_6/TRDIOC1

1

2

3

4

5

6

7

8

9

10 11 12

Notes:

1. Can be assigned to the pin in parentheses by a program.

2. Only in the R8C/34W Group and R8C/34X Group.

3. P4_2 is an input-only pin.

4. Confirm the pin 1 position on the package by referring to the Package Dimensions.

Figure 1.6

Pin Assignment (Top View)

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 15 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.13

Pin Name Information by Pin Number (1)

I/O Pin Functions for Peripheral Modules

Number

A/D Converter

Voltage Detection

Circuit

Control Pin

Port

CAN

Module ⁽²⁾

Interrupt

INT3

Timer

Serial Interface

(CLK2) ⁽¹⁾

SSU

1

2

P3_5

P3_3

SSCK

(SSI) ⁽¹⁾/SCS

CTS2/RTS2

(TXD2)/(SDA2)/

SSI/(SCS) ⁽¹⁾

(RXD2)/(SCL2)

(1)

3

P3_4

4

MODE

5

P4_3

P4_4

6

7

RESET

XOUT

8

P4_7

P4_6

9

VSS/AVSS

XIN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

VCC/AVCC

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

P2_0

P1_7

P1_6

P1_5

P1_4

P1_3

P4_5

P6_6

TRDIOD1

TRDIOC1

TRDIOB1

TRDIOA1

TRDIOD0

TRDIOC0

TRDIOB0

TRDIOA0/

TRDCLK

(TRAIO)

(1)

INT1

CLK0

RXD0

TXD0

(TRAIO)

(1)

INT1 ⁽¹⁾

TRCCLK

TRBO

KI3

AN11

INT0

INT2

ADTRG

(TXD2)/(SDA2)

(1)

TRCIOC

Notes:

1. This can be assigned to the pin in parentheses by a program.

2. Only for the R8C/34W Group and R8C/34X Group.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 16 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.14

Pin Name Information by Pin Number (2)

I/O Pin Functions for Peripheral Modules

Number

A/D Converter

Voltage Detection

Circuit

Control Pin

Port

CAN

Module ⁽²⁾

Interrupt

Timer

Serial Interface

SSU

(RXD2)/(SCL2)

(1)

INT3 ⁽¹⁾

KI2

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

P6_7

P1_2

P1_1

P1_0

P3_1

P3_0

P6_5

P6_4

P6_3

P0_7

P0_6

P0_5

P0_4

P4_2

P6_0

P6_2

P6_1

P0_3

P0_2

P0_1

P0_0

TRCIOD

TRCIOB

AN10

AN9

AN8

TRCIOA/

TRCTRG

KI1

KI0

(TRBO)

(1)

(TRAO)

(1)

(CLK2) ⁽¹⁾

INT4

AN0

AN1

AN2

TREO

AN3

VREF

(TREO)

(1)

CRX0 ⁽²⁾

CTX0 ⁽²⁾

AN4

AN5

AN6

AN7

(TXD2)/(SDA2)/

(RXD2)/(SCL2)

(1)

(TRAO)

(1)

48

P3_7

SSO

Notes:

1. This can be assigned to the pin in parentheses by a program.

2. Only for the R8C/34W Group and R8C/34X Group.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 17 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

1.5

Pin Functions

Tables 1.15 and 1.16 list Pin Functions.

Table 1.15

Pin Functions (1)

Item

Pin Name

I/O Type

Description

Power supply input VCC, VSS

−

Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Analog power

supply input

AVCC, AVSS

Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input

I

Input “L” on this pin resets the MCU.

Connect this pin to VCC via a resistor.

RESET

MODE

XIN

MODE

I

XIN clock input

These pins are provided for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between

the XIN and XOUT pins ⁽¹⁾. To use an external clock, input it

to the XOUT pin and leave the XIN pin open.

XIN clock output

XOUT

I/O

INT interrupt input INT0 to INT4

I

INT interrupt input pins.

Key input interrupt

Timer RA

Key input interrupt input pins

KI0 to KI3

TRAIO

I/O

O

I

Timer RA I/O pin

TRAO

Timer RA output pin

Timer RB output pin

External clock input pin

External trigger input pin

Timer RC I/O pins

Timer RB

Timer RC

TRBO

TRCCLK

TRCTRG

I

TRCIOA, TRCIOB,

TRCIOC, TRCIOD

I/O

Timer RD

TRDIOA0, TRDIOA1,

TRDIOB0, TRDIOB1,

TRDIOC0, TRDIOC1,

TRDIOD0, TRDIOD1

I/O

Timer RD I/O pins

TRDCLK

I

O

I/O

I

External clock input pin

Divided clock output pin

Transfer clock I/O pins

Serial data input pins

Timer RE

TREO

Serial interface

CLK0, CLK2

RXD0, RXD2

TXD0, TXD2

O

I

Serial data output pins

Transmission control input pin

CTS2

O

Reception control output pin

RTS2

SCL2

SDA2

SSI

I²C mode clock I/O pin

I²C mode data I/O pin

Data I/O pin

I/O

SSU

Chip-select signal I/O pin

SCS

SSCK

SSO

I/O

Clock I/O pin

Data I/O pin

I: Input

Note:

O: Output

I/O: Input and output

1. Refer to the oscillator manufacturer for oscillation characteristics.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 18 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

1. Overview

Table 1.16

Pin Functions (2)

Item

Pin Name

CRX0 ⁽¹⁾

I/O Type

Description

CAN module

I

O

I

CAN data input pin

CAN data output pin

CTX0 ⁽¹⁾

Reference voltage VREF

input

Reference voltage input pin to A/D converter

A/D converter

AN0 to AN11

I

Analog input pins to A/D converter

AD external trigger input pin

ADTRG

I/O port

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_1,

P3_3 to P3_5, P3_7,

P4_3 to P4_7,

P6_0 to P6_7

I/O

CMOS I/O ports. Each port has an I/O select direction

register, allowing each pin in the port to be directed for input

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

Input port

P4_2

I

I/O: Input and output

Input-only ports

I: Input

Note:

O: Output

1. Only in the R8C/34W Group and R8C/34X Group.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 19 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

register bank. There are two sets of register bank.

b31

b15

b8b7

b0

R0H (high-order of R0) R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)

R2

R3

Data registers ⁽¹⁾

R3

A0

Address registers ⁽¹⁾

A1

FB

Frame base register ⁽¹⁾

b19

b15

b0

Interrupt table register

Program counter

INTBH

INTBL

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

b19

PC

b15

b0

User stack pointer

Interrupt stack pointer

Static base register

USP

ISP

SB

b15

b0

Flag register

FLG

b15

b8

b7

IPL

U I O B S Z D C

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

Note:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1

CPU Registers

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 20 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

2. Central Processing Unit (CPU)

2.1

Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split

into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are

analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is

analogous to R2R0.

2.2

Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-

bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.

2.5

Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1

Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2

Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4

Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5

Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6

Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 21 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

2. Central Processing Unit (CPU)

2.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 22 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

3. Memory

3.1

R8C/34W Group

Figure 3.1 is a Memory Map of R8C/34W Group. The R8C/34W Group has a 1-Mbyte address space from

addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with

address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal

RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas

for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated

spaces within the SFRs are reserved and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXXh

02C00h

(2)

SFR

0FFDCh

Undefined instruction

Overflow

BRK instruction

Address match

(Refer to 4. Special Function

Registers (SFRs))

02FFFh

03000h

Internal ROM

(data flash) ⁽¹⁾

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

03FFFh

0YYYYh

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

ZZZZZh

0FFFFh

Internal ROM

(program ROM)

FFFFFh

Notes:

1. The Data Flash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).

2. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.

3. The blank areas are reserved and cannot be accessed by users.

Internal ROM

Internal RAM

Address 0XXXXh

Part Number

Address ZZZZZh

Size

Address 0YYYYh

Size

R5F21346WJFP, R5F21346WKFP

R5F21347WJFP, R5F21347WKFP

R5F21348WJFP, R5F21348WKFP

R5F2134AWJFP, R5F2134AWKFP

R5F2134CWJFP, R5F2134CWKFP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

08000h

04000h

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

00DFFh

013FFh

01BFFh

023FFh

02BFFh

13FFFh

1BFFFh

23FFFh

Figure 3.1

Memory Map of R8C/34W Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 23 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

3. Memory

3.2

R8C/34X Group

Figure 3.2 is a Memory Map of R8C/34X Group. The R8C/34X Group has a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal

RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas

for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated

spaces within the SFRs are reserved and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXXh

(1)

02C00h

02FFFh

SFR

0FFDCh

Undefined instruction

Overflow

BRK instruction

Address match

(Refer to 4. Special Function

Registers (SFRs))

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

0YYYYh

0FFFFh

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

Internal ROM

(program ROM)

ZZZZZh

FFFFFh

Notes:

1. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.

2. The blank areas are reserved and cannot be accessed by users.

Internal ROM

Internal RAM

Address 0XXXXh

Part Number

Address ZZZZZh

Size

Address 0YYYYh

Size

R5F21346XJFP, R5F21346XKFP

R5F21347XJFP, R5F21347XKFP

R5F21348XJFP, R5F21348XKFP

R5F2134AXJFP, R5F2134AXKFP

R5F2134CXJFP, R5F2134CXKFP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

08000h

04000h

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

00DFFh

013FFh

01BFFh

023FFh

02BFFh

13FFFh

1BFFFh

23FFFh

Figure 3.2

Memory Map of R8C/34X Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 24 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

3. Memory

3.3

R8C/34Y Group

Figure 3.3 is a Memory Map of R8C/34Y Group. The R8C/34Y Group has a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal

RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas

for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces

within the SFRs are reserved and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXXh

02C00h

(2)

SFR

0FFDCh

Undefined instruction

Overflow

BRK instruction

Address match

(Refer to 4. Special Function

Registers (SFRs))

02FFFh

03000h

Internal ROM

(data flash) ⁽¹⁾

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

03FFFh

0YYYYh

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

ZZZZZh

0FFFFh

Internal ROM

(program ROM)

FFFFFh

Notes:

1. The Data Flash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).

2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.

3. The blank areas are reserved and cannot be accessed by users.

Internal ROM

Internal RAM

Address 0XXXXh

Part Number

Address ZZZZZh

Size

Address 0YYYYh

Size

R5F21346YJFP, R5F21346YKFP

R5F21347YJFP, R5F21347YKFP

R5F21348YJFP, R5F21348YKFP

R5F2134AYJFP, R5F2134AYKFP

R5F2134CYJFP, R5F2134CYKFP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

08000h

04000h

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

00DFFh

013FFh

01BFFh

023FFh

02BFFh

13FFFh

1BFFFh

23FFFh

Figure 3.3

Memory Map of R8C/34Y Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 25 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

3. Memory

3.4

R8C/34Z Group

Figure 3.4 is a Memory Map of R8C/34Z Group. The R8C/34Z Group has a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal

RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas

for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces

within the SFRs are reserved and cannot be accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0XXXXh

(1)

02C00h

02FFFh

SFR

0FFDCh

Undefined instruction

Overflow

BRK instruction

Address match

(Refer to 4. Special Function

Registers (SFRs))

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

0YYYYh

0FFFFh

Internal ROM

(program ROM)

(Reserved)

Reset

0FFFFh

Internal ROM

(program ROM)

ZZZZZh

FFFFFh

Notes:

1. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.

2. The blank areas are reserved and cannot be accessed by users.

Internal ROM

Internal RAM

Address 0XXXXh

Part Number

Address ZZZZZh

Size

Address 0YYYYh

Size

R5F21346ZJFP, R5F21346ZKFP

R5F21347ZJFP, R5F21347ZKFP

R5F21348ZJFP, R5F21348ZKFP

R5F2134AZJFP, R5F2134AZKFP

R5F2134CZJFP, R5F2134CZKFP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

08000h

04000h

2.5 Kbytes

4 Kbytes

6 Kbytes

8 Kbytes

10 Kbytes

00DFFh

013FFh

01BFFh

023FFh

02BFFh

13FFFh

1BFFFh

23FFFh

Figure 3.4

Memory Map of R8C/34Z Group

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 26 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.17 list the special

function registers. Table 4.18 lists the ID Code Areas and Option Function Select Area.

(1)

Table 4.1

SFR Information (1)

Address

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

Register

Symbol

After reset

Processor Mode Register 0

Processor Mode Register 1

PM0

PM1

CM0

CM1

00h

System Clock Control Register 0

System Clock Control Register 1

Module Standby Control Register

System Clock Control Register 3

Protect Register

Reset Source Determination Register

Oscillation Stop Detection Register

Watchdog Timer Reset Register

Watchdog Timer Start Register

Watchdog Timer Control Register

00101000b

00100000b

00h

MSTCR

CM3

PRCR

RSTFR

OCD

WDTR

WDTS

WDTC

00h

0XXXXXXXb ⁽²⁾

00000100b

XXh

00111111b

High-Speed On-Chip Oscillator Control Register 7

FRA7

CSPR

When shipping

Count Source Protection Mode Register

00h

10000000b ⁽³⁾

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

High-Speed On-Chip Oscillator Control Register 0

High-Speed On-Chip Oscillator Control Register 1

High-Speed On-Chip Oscillator Control Register 2

On-Chip Reference Voltage Control Register

FRA0

FRA1

FRA2

OCVREFCR

00h

When shipping

00h

High-Speed On-Chip Oscillator Control Register 4

High-Speed On-Chip Oscillator Control Register 5

High-Speed On-Chip Oscillator Control Register 6

FRA4

FRA5

FRA6

When Shipping

High-Speed On-Chip Oscillator Control Register 3

Voltage Monitor Circuit Control Register

Voltage Monitor Circuit Edge Select Register

FRA3

CMPA

VCAC

When shipping

00h

Voltage Detect Register 1

Voltage Detect Register 2

VCA1

VCA2

00001000b

00h ⁽⁴⁾

00100000b ⁽⁵⁾

0035h

0036h

0037h

0038h

Voltage Detection 1 Level Select Register

Voltage Monitor 0 Circuit Control Register

Voltage Monitor 1 Circuit Control Register

VD1LS

VW0C

VW1C

00000111b

1100X010b ⁽⁴⁾

1100X011b ⁽⁵⁾

10001010b

0039h

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer

reset does not affect this bit.

3. The CSPROINI bit in the OFS register is set to 0.

4. The LVDAS bit in the OFS register is set to 1.

5. The LVDAS bit in the OFS register is set to 0.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 27 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.2

SFR Information (2)

Address

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

Register

Symbol

After reset

10000010b

Voltage Monitor 2 Circuit Control Register

VW2C

Flash Memory Ready Interrupt Control Register

FMRDYIC

XXXXX000b

INT4 Interrupt Control Register

INT4IC

TRCIC

TRD0IC

TRD1IC

TREIC

S2TIC

S2RIC

KUPIC

ADIC

XX00X000b

XXXXX000b

Timer RC Interrupt Control Register

Timer RD0 Interrupt Control Register

Timer RD1 Interrupt Control Register

Timer RE Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

SSU Interrupt Control Register

SSUIC

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

S0TIC

S0RIC

XXXXX000b

INT2 Interrupt Control Register

Timer RA Interrupt Control Register

INT2IC

TRAIC

XX00X000b

XXXXX000b

Timer RB Interrupt Control Register

INT1 Interrupt Control Register

INT3 Interrupt Control Register

TRBIC

INT1IC

INT3IC

XXXXX000b

XX00X000b

INT0 Interrupt Control Register

INT0IC

U2BCNIC

XX00X000b

XXXXX000b

UART2 Bus Collision Detection Interrupt Control Register

CAN0 Successful Reception Interrupt Control Register

CAN0 Successful Transmission Interrupt Control Register

CAN0 Receive FIFO Interrupt Control Register

CAN0 Transmit FIFO Interrupt Control Register

CAN0 Error Interrupt Control Register

CAN0 Wake-up Interrupt Control Register

Voltage Monitor 1 Level Interrupt Control Register

Voltage Monitor 2 Level Interrupt Control Register

C0RIC

XXXXX000b

C0TIC

C0FRIC

C0FTIC

C0EIC

C0WIC

VCMP1IC

VCMP2IC

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 28 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.3

SFR Information (3)

Address

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

Register

Symbol

DTCTL

After reset

00h

DTC Activation Control Register

DTC Activation Enable Register 0

DTC Activation Enable Register 1

DTC Activation Enable Register 2

DTC Activation Enable Register 3

DTC Activation Enable Register 4

DTC Activation Enable Register 5

DTC Activation Enable Register 6

DTCEN0

DTCEN1

DTCEN2

DTCEN3

DTCEN4

DTCEN5

DTCEN6

00h

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

U0MR

U0BRG

U0TB

00h

XXh

00001000b

00000010b

XXh

00h

XXh

00001000b

00000010b

XXh

00h

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

U2MR

U2BRG

U2TB

UART2 Transmit Buffer Register

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

U2C0

U2C1

U2RB

UART2 Digital Filter Function Select Register

URXDF

UART2 Special Mode Register 5

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

U2SMR5

U2SMR4

U2SMR3

U2SMR2

U2SMR

00h

000X0X0Xb

X0000000b

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 29 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.4

SFR Information (4)

Address

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

Register

Symbol

After reset

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

A/D Register 0

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A/D Register 1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

000000XXb

XXh

000000XXb

A/D Mode Register

ADMOD

ADINSEL

ADCON0

ADCON1

00h

11000000b

00h

A/D Input Select Register

A/D Control Register 0

A/D Control Register 1

00h

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

P0

P1

PD0

PD1

P2

XXh

00h

XXh

00h

XXh

Port P3 Register

P3

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

PD2

PD3

P4

Port P4 Direction Register

Port P6 Register

PD4

P6

00h

XXh

00h

Port P6 Direction Register

PD6

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 30 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.5

SFR Information (5)

Address

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

Register

Symbol

TRACR

TRAIOC

TRAMR

TRAPRE

TRA

LINCR2

LINCR

LINST

TRBCR

TRBOCR

TRBIOC

TRBMR

TRBPRE

TRBSC

TRBPR

After reset

Timer RA Control Register

Timer RA I/O Control Register

Timer RA Mode Register

Timer RA Prescaler Register

Timer RA Register

LIN Control Register 2

LIN Control Register

LIN Status Register

Timer RB Control Register

Timer RB One-Shot Control Register

Timer RB I/O Control Register

Timer RB Mode Register

Timer RB Prescaler Register

Timer RB Secondary Register

Timer RB Primary Register

00h

FFh

00h

FFh

Timer RE Counter Data Register

Timer RE Compare Data Register

TRESEC

TREMIN

00h

Timer RE Control Register 1

Timer RE Control Register 2

TRECR1

TRECR2

TRECSR

00h

Timer RE Count Source Select Register

00001000b

Timer RC Mode Register

TRCMR

TRCCR1

TRCIER

TRCSR

TRCIOR0

TRCIOR1

TRC

01001000b

00h

Timer RC Control Register 1

Timer RC Interrupt Enable Register

Timer RC Status Register

Timer RC I/O Control Register 0

Timer RC I/O Control Register 1

Timer RC Counter

01110000b

10001000b

00h

FFh

Timer RC General Register A

Timer RC General Register B

Timer RC General Register C

Timer RC General Register D

TRCGRA

TRCGRB

TRCGRC

TRCGRD

FFh

Timer RC Control Register 2

TRCCR2

TRCDF

TRCOER

TRCADCR

00011000b

00h

01111111b

00h

Timer RC Digital Filter Function Select Register

Timer RC Output Master Enable Register

Timer RC Trigger Control Register

Timer RD Trigger Control Register

Timer RD Start Register

Timer RD Mode Register

TRDADCR

TRDSTR

TRDMR

TRDPMR

TRDFCR

TRDOER1

TRDOER2

TRDOCR

TRDDF0

TRDDF1

00h

11111100b

00001110b

10001000b

10000000b

FFh

Timer RD PWM Mode Register

Timer RD Function Control Register

Timer RD Output Master Enable Register 1

Timer RD Output Master Enable Register 2

Timer RD Output Control Register

Timer RD Digital Filter Function Select Register 0

Timer RD Digital Filter Function Select Register 1

01111111b

00h

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 31 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.6

SFR Information (6)

Address

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

Register

Symbol

TRDCR0

TRDIORA0

TRDIORC0

TRDSR0

TRDIER0

TRDPOCR0

TRD0

After reset

00h

Timer RD Control Register 0

Timer RD I/O Control Register A0

Timer RD I/O Control Register C0

Timer RD Status Register 0

10001000b

11100000b

11111000b

00h

FFh

00h

10001000b

11000000b

11100000b

11111000b

00h

FFh

Timer RD Interrupt Enable Register 0

Timer RD PWM Mode Output Level Control Register 0

Timer RD Counter 0

Timer RD General Register A0

Timer RD General Register B0

Timer RD General Register C0

Timer RD General Register D0

TRDGRA0

TRDGRB0

TRDGRC0

TRDGRD0

Timer RD Control Register 1

TRDCR1

TRDIORA1

TRDIORC1

TRDSR1

TRDIER1

TRDPOCR1

TRD1

Timer RD I/O Control Register A1

Timer RD I/O Control Register C1

Timer RD Status Register 1

Timer RD Interrupt Enable Register 1

Timer RD PWM Mode Output Level Control Register 1

Timer RD Counter 1

Timer RD General Register A1

Timer RD General Register B1

Timer RD General Register C1

Timer RD General Register D1

TRDGRA1

TRDGRB1

TRDGRC1

TRDGRD1

FFh

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 32 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.7

SFR Information (7)

Address

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Register

Symbol

TRASR

After reset

Timer RA Pin Select Register

Timer RB/RC Pin Select Register

Timer RC Pin Select Register 0

Timer RC Pin Select Register 1

Timer RD Pin Select Register 0

Timer RD Pin Select Register 1

Timer Pin Select Register

00h

TRBRCSR

TRCPSR0

TRCPSR1

TRDPSR0

TRDPSR1

TIMSR

UART0 Pin Select Register

U0SR

00h

UART2 Pin Select Register 0

UART2 Pin Select Register 1

SSU Pin Select Register

U2SR0

U2SR1

SSUIICSR

00h

INT Interrupt Input Pin Select Register

I/O Function Pin Select Register

INTSR

PINSR

00h

SS Bit Counter Register

SS Transmit Data Register

SSBR

SSTDR

11111000b

FFh

00h

SS Receive Data Register

SSRDR

SS Control Register H

SS Control Register L

SS Mode Register

SS Enable Register

SS Status Register

SS Mode Register 2

SSCRH

SSCRL

SSMR

SSER

SSSR

SSMR2

01111101b

00010000b

00h

Flash Memory Status Register

FST

10000X00b

Flash Memory Control Register 0

Flash Memory Control Register 1

Flash Memory Control Register 2

FMR0

FMR1

FMR2

00h

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 33 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.8

SFR Information (8)

Address

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

Register

Symbol

RMAD0

After reset

Address Match Interrupt Register 0

XXh

0000XXXXb

00h

Address Match Interrupt Enable Register 0

Address Match Interrupt Register 1

AIER0

RMAD1

XXh

0000XXXXb

00h

Address Match Interrupt Enable Register 1

AIER1

Pull-Up Control Register 0

Pull-Up Control Register 1

PUR0

PUR1

00h

Input Threshold Control Register 0

Input Threshold Control Register 1

VLT0

VLT1

00h

External Input Enable Register 0

External Input Enable Register 1

INT Input Filter Select Register 0

INT Input Filter Select Register 1

Key Input Enable Register 0

INTEN

INTEN1

INTF

INTF1

KIEN

00h

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 34 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.9

SFR Information (9)

Address

2C00h

2C01h

2C02h

2C03h

2C04h

2C05h

2C06h

2C07h

2C08h

2C09h

2C0Ah

:

Register

Symbol

After reset

DTC Transfer Vector Area

XXh

DTC Transfer Vector Area

XXh

:

2C3Ah

2C3Bh

2C3Ch

2C3Dh

2C3Eh

2C3Fh

2C40h

2C41h

2C42h

2C43h

2C44h

2C45h

2C46h

2C47h

2C48h

2C49h

2C4Ah

2C4Bh

2C4Ch

2C4Dh

2C4Eh

2C4Fh

2C50h

2C51h

2C52h

2C53h

2C54h

2C55h

2C56h

2C57h

2C58h

2C59h

2C5Ah

2C5Bh

2C5Ch

2C5Dh

2C5Eh

2C5Fh

2C60h

2C61h

2C62h

2C63h

2C64h

2C65h

2C66h

2C67h

2C68h

2C69h

2C6Ah

2C6Bh

2C6Ch

2C6Dh

2C6Eh

2C6Fh

DTC Control Data 0

DTC Control Data 1

DTC Control Data 2

DTC Control Data 3

DTC Control Data 4

DTC Control Data 5

DTCD0

XXh

DTCD1

DTCD2

DTCD3

DTCD4

DTCD5

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 35 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.10

SFR Information (10)

Address

2C70h

2C71h

2C72h

2C73h

2C74h

2C75h

2C76h

2C77h

2C78h

2C79h

2C7Ah

2C7Bh

2C7Ch

2C7Dh

2C7Eh

2C7Fh

2C80h

2C81h

2C82h

2C83h

2C84h

2C85h

2C86h

2C87h

2C88h

2C89h

2C8Ah

2C8Bh

2C8Ch

2C8Dh

2C8Eh

2C8Fh

2C90h

2C91h

2C92h

2C93h

2C94h

2C95h

2C96h

2C97h

2C98h

2C99h

2C9Ah

2C9Bh

2C9Ch

2C9Dh

2C9Eh

2C9Fh

2CA0h

2CA1h

2CA2h

2CA3h

2CA4h

2CA5h

2CA6h

2CA7h

2CA8h

2CA9h

2CAAh

2CABh

2CACh

2CADh

2CAEh

2CAFh

Register

Symbol

DTCD6

After reset

XXh

DTC Control Data 6

DTC Control Data 7

DTC Control Data 8

DTC Control Data 9

DTC Control Data 10

DTC Control Data 11

DTC Control Data 12

DTC Control Data 13

DTCD7

DTCD8

DTCD9

DTCD10

DTCD11

DTCD12

DTCD13

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 36 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.11

SFR Information (11)

Address

2CB0h

2CB1h

2CB2h

2CB3h

2CB4h

2CB5h

2CB6h

2CB7h

2CB8h

2CB9h

2CBAh

2CBBh

2CBCh

2CBDh

2CBEh

2CBFh

2CC0h

2CC1h

2CC2h

2CC3h

2CC4h

2CC5h

2CC6h

2CC7h

2CC8h

2CC9h

2CCAh

2CCBh

2CCCh

2CCDh

2CCEh

2CCFh

2CD0h

2CD1h

2CD2h

2CD3h

2CD4h

2CD5h

2CD6h

2CD7h

2CD8h

2CD9h

2CDAh

2CDBh

2CDCh

2CDDh

2CDEh

2CDFh

2CE0h

2CE1h

2CE2h

2CE3h

2CE4h

2CE5h

2CE6h

2CE7h

2CE8h

2CE9h

2CEAh

2CEBh

2CECh

2CEDh

2CEEh

2CEFh

Register

Symbol

DTCD14

After reset

XXh

DTC Control Data 14

DTC Control Data 15

DTC Control Data 16

DTC Control Data 17

DTC Control Data 18

DTC Control Data 19

DTC Control Data 20

DTC Control Data 21

DTCD15

DTCD16

DTCD17

DTCD18

DTCD19

DTCD20

DTCD21

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 37 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.12

SFR Information (12)

Address

2CF0h

2CF1h

2CF2h

2CF3h

2CF4h

2CF5h

2CF6h

2CF7h

2CF8h

2CF9h

2CFAh

2CFBh

2CFCh

2CFDh

2CFEh

2CFFh

2D00h

2D01h

:

Register

Symbol

DTCD22

After reset

XXh

DTC Control Data 22

DTC Control Data 23

DTCD23

2E00h

2E01h

2E02h

2E03h

2E04h

2E05h

2E06h

2E07h

2E08h

2E09h

2E0Ah

2E0Bh

2E0Ch

2E0Dh

2E0Eh

2E0Fh

2E10h

2E11h

2E12h

2E13h

2E14h

2E15h

2E16h

2E17h

2E18h

2E19h

2E1Ah

2E1Bh

2E1Ch

2E1Dh

2E1Eh

2E1Fh

2E20h

2E21h

2E22h

2E23h

2E24h

2E25h

2E26h

2E27h

2E28h

2E29h

2E2Ah

2E2Bh

2E2Ch

2E2Dh

2E2Eh

2E2Fh

CAN0 Mailbox 0 : Message ID

C0MB0

XXXX XXXXh

CAN0 Mailbox 0 : Data length

CAN0 Mailbox 0 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox 0 : Time stamp

CAN0 Mailbox 1 : Message ID

XXXXh

C0MB1

XXXX XXXXh

CAN0 Mailbox 1 : Data length

CAN0 Mailbox 1 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox 1 : Time stamp

CAN0 Mailbox 2 : Message ID

XXXXh

C0MB2

XXXX XXXXh

CAN0 Mailbox 2 : Data length

CAN0 Mailbox 2 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox 2 : Time stamp

XXXXh

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 38 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.13

SFR Information (13)

Address

2E30h

2E31h

2E32h

2E33h

2E34h

2E35h

2E36h

2E37h

2E38h

2E39h

2E3Ah

2E3Bh

2E3Ch

2E3Dh

2E3Eh

2E3Fh

2E40h

2E41h

2E42h

2E43h

2E44h

2E45h

2E46h

2E47h

2E48h

2E49h

2E4Ah

2E4Bh

2E4Ch

2E4Dh

2E4Eh

2E4Fh

2E50h

2E51h

2E52h

2E53h

2E54h

2E55h

2E56h

2E57h

2E58h

2E59h

2E5Ah

2E5Bh

2E5Ch

2E5Dh

2E5Eh

2E5Fh

2E60h

2E61h

2E62h

2E63h

2E64h

2E65h

2E66h

2E67h

2E68h

2E69h

2E6Ah

2E6Bh

2E6Ch

2E6Dh

2E6Eh

2E6Fh

Register

Symbol

C0MB3

After reset

XXXX XXXXh

CAN0 Mailbox 3 : Message ID

CAN0 Mailbox 3 : Data length

CAN0 Mailbox 3 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox3 : Time stamp

CAN0 Mailbox4 : Message ID

XXXXh

C0MB4

C0MB5

C0MB6

XXXX XXXXh

CAN0 Mailbox4 : Data length

CAN0 Mailbox4 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox4 : Time stamp

CAN0 Mailbox5 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox5 : Data length

CAN0 Mailbox5 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox5 : Time stamp

CAN0 Mailbox6 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox6 : Data length

CAN0 Mailbox6 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox6 : Time stamp

XXXXh

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 39 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.14

SFR Information (14)

Address

2E70h

2E71h

2E72h

2E73h

2E74h

2E75h

2E76h

2E77h

2E78h

2E79h

2E7Ah

2E7Bh

2E7Ch

2E7Dh

2E7Eh

2E7Fh

2E80h

2E81h

2E82h

2E83h

2E84h

2E85h

2E86h

2E87h

2E88h

2E89h

2E8Ah

2E8Bh

2E8Ch

2E8Dh

2E8Eh

2E8Fh

2E90h

2E91h

2E92h

2E93h

2E94h

2E95h

2E96h

2E97h

2E98h

2E99h

2E9Ah

2E9Bh

2E9Ch

2E9Dh

2E9Eh

2E9Fh

2EA0h

2EA1h

2EA2h

2EA3h

2EA4h

2EA5h

2EA6h

2EA7h

2EA8h

2EA9h

2EAAh

2EABh

2EACh

2EADh

2EAEh

2EAFh

Register

Symbol

C0MB7

After reset

XXXX XXXXh

CAN0 Mailbox7 : Message ID

CAN0 Mailbox7 : Data length

CAN0 Mailbox7 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox7 : Time stamp

CAN0 Mailbox8 : Message ID

XXXXh

C0MB8

C0MB9

C0MB10

XXXX XXXXh

CAN0 Mailbox8 : Data length

CAN0 Mailbox8 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox8 : Time stamp

CAN0 Mailbox9 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox9 : Data length

CAN0 Mailbox9 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox9 : Time stamp

CAN0 Mailbox10 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox10 : Data length

CAN0 Mailbox10 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox10 : Time stamp

XXXXh

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 40 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.15

SFR Information (15)

Address

2EB0h

2EB1h

2EB2h

2EB3h

2EB4h

2EB5h

2EB6h

2EB7h

2EB8h

2EB9h

2EBAh

2EBBh

2EBCh

2EBDh

2EBEh

2EBFh

2EC0h

2EC1h

2EC2h

2EC3h

2EC4h

2EC5h

2EC6h

2EC7h

2EC8h

2EC9h

2ECAh

2ECBh

2ECCh

2ECDh

2ECEh

2ECFh

2ED0h

2ED1h

2ED2h

2ED3h

2ED4h

2ED5h

2ED6h

2ED7h

2ED8h

2ED9h

2EDAh

2EDBh

2EDCh

2EDDh

2EDEh

2EDFh

2EE0h

2EE1h

2EE2h

2EE3h

2EE4h

2EE5h

2EE6h

2EE7h

2EE8h

2EE9h

2EEAh

2EEBh

2EECh

2EEDh

2EEEh

2EEFh

Register

Symbol

C0MB11

After reset

XXXX XXXXh

CAN0 Mailbox11 : Message ID

CAN0 Mailbox11 : Data length

CAN0 Mailbox11 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox11 : Time stamp

CAN0 Mailbox12 : Message ID

XXXXh

C0MB12

C0MB13

C0MB14

XXXX XXXXh

CAN0 Mailbox12 : Data length

CAN0 Mailbox12 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox12 : Time stamp

CAN0 Mailbox13 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox13 : Data length

CAN0 Mailbox13 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox13 : Time stamp

CAN0 Mailbox14 : Message ID

XXXXh

XXXX XXXXh

CAN0 Mailbox14 : Data length

CAN0 Mailbox14 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox14 : Time stamp

XXXXh

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 41 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.16

SFR Information (16)

Address

2EF0h

2EF1h

2EF2h

2EF3h

2EF4h

2EF5h

2EF6h

2EF7h

2EF8h

2EF9h

2EFAh

2EFBh

2EFCh

2EFDh

2EFEh

2EFFh

2F00h

2F01h

2F02h

2F03h

2F04h

2F05h

2F06h

2F07h

2F08h

2F09h

2F0Ah

2F0Bh

2F0Ch

2F0Dh

2F0Eh

2F0Fh

2F10h

2F11h

2F12h

2F13h

2F14h

2F15h

2F16h

2F17h

2F18h

2F19h

2F1Ah

2F1Bh

2F1Ch

2F1Dh

2F1Eh

2F1Fh

2F20h

2F21h

2F22h

2F23h

2F24h

2F25h

2F26h

2F27h

2F28h

2F29h

2F2Ah

2F2Bh

2F2Ch

2F2Dh

2F2Eh

2F2Fh

2F30h

2F31h

2F32h

2F33h

2F34h

2F35h

2F36h

2F37h

2F38h

2F39h

2F3Ah

Register

Symbol

C0MB15

After reset

XXXX XXXXh

CAN0 Mailbox15 : Message ID

CAN0 Mailbox15 : Data length

CAN0 Mailbox15 : Data field

XXh

XXXX XXXX

XXXX XXXXh

CAN0 Mailbox15 : Time stamp

XXXXh

CAN0 Mask Register 0

CAN0 Mask Register 1

CAN0 Mask Register 2

CAN0 Mask Register 3

C0MKR0

C0MKR1

C0MKR2

C0MKR3

C0FIDCR0

C0FIDCR1

XXXX XXXXh

CAN0 FIFO Received ID Compare Register 0

CAN0 FIFO Received ID Compare Register 1

CAN0 Mask Invalid Register

C0MKIVLR

C0MIER

XXXXh

CAN0 Mailbox Interrupt Enable Register

CAN0 Message Control Register 0

CAN0 Message Control Register 1

CAN0 Message Control Register 2

CAN0 Message Control Register 3

CAN0 Message Control Register 4

CAN0 Message Control Register 5

CAN0 Message Control Register 6

CAN0 Message Control Register 7

CAN0 Message Control Register 8

CAN0 Message Control Register 9

CAN0 Message Control Register 10

C0MCTL0

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

00h

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 42 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

4. Special Function Registers (SFRs)

(1)

Table 4.17

SFR Information (17)

Address

2F3Bh

2F3Ch

2F3Dh

2F3Eh

2F3Fh

2F40h

2F41h

2F42h

2F43h

2F44h

2F45h

2F46h

2F47h

2F48h

2F49h

2F4Ah

2F4Bh

2F4Ch

2F4Dh

2F4Eh

2F4Fh

2F50h

2F51h

2F52h

2F53h

2F54h

2F55h

2F56h

2F57h

2F58h

:

Register

Symbol

C0MCTL11

After reset

CAN0 Message Control Register 11

CAN0 Message Control Register 12

CAN0 Message Control Register 13

CAN0 Message Control Register 14

CAN0 Message Control Register 15

CAN0 Control Register

00h

C0MCTL12

C0MCTL13

C0MCTL14

C0MCTL15

C0CTLR

00h

0000 0101b

0000 0000b

0000 0101b

CAN0 Status Register

C0STR

C0BCR

0000 0000b

00 0000h

CAN0 Bit Configuration Register

CAN0 Receive FIFO Control Register

C0RFCR

C0RFPCR

C0TFCR

C0TFPCR

C0EIER

1000 0000b

XXh

1000 0000b

XXh

CAN0 Receive FIFO Pointer Control Register

CAN0 Transmit FIFO Control Register

CAN0 Transmit FIFO Pointer Control Register

CAN0 Error Interrupt Enable Register

CAN0 Error Interrupt Factor Judge Register

CAN0 Reception Error Count Register

CAN0 Transmission Error Count Register

CAN0 Error Code Store Register

CAN0 Channel Search Support Register

CAN0 Mailbox Search Status Register

CAN0 Mailbox Search Mode Register

CAN0 Time Stamp Register

00h

XXh

C0EIFR

C0RECR

C0TECR

C0ECSR

C0CSSR

C0MSSR

C0MSMR

C0TSR

1000 0000b

00h

0000h

CAN0 Acceptance Filter Support Register

CAN0 Test Control Register

C0AFSR

C0TCR

XXXXh

00h

2FFFh

X : Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Table 4.18

ID Code Areas and Option Function Select Area

Address

Area Name

Symbol

After Reset

(Note 1)

:

FFDBh

Option Function Select Register 2

OFS2

:

FFDFh

ID1

(Note 2)

:

FFE3h

ID2

(Note 2)

:

FFEBh

ID3

(Note 2)

:

FFEFh

ID4

(Note 2)

:

FFF3h

ID5

(Note 2)

:

FFF7h

ID6

(Note 2)

:

FFFBh

:

ID7

(Note 2)

FFFFh

Option Function Select Register

OFS

(Note 1)

Notes:

1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select

area is set to FFh.

When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.

When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.

2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.

When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.

When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 43 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.1

Absolute Maximum Ratings

Symbol

Parameter

Condition

Rated Value

Unit

V

VCC/AVCC Supply voltage

−0.3 to 6.5

−0.3 to VCC + 0.3

−4 to 4

Input voltage ⁽¹⁾

Input current ⁽¹⁾

Output voltage

Power dissipation

VI

V

(2, 3, 4)

IIN

VO

Pd

mA

V

−0.3 to VCC + 0.3

300

−40 °C ≤ Topr < 85 °C

85 °C ≤ Topr < 125 °C

mW

°C

125

Topr

Operating ambient temperature

Storage temperature

−40 to 85 (J version) /

−40 to 125 (K version)

Tstg

−65 to 150

°C

Notes:

1. Meet the specified range for the input voltage or the input current.

2. Applicable ports: P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6

3. The total input current must be 12 mA or less.

4. Even if no voltage is supplied to Vcc, the input current may cause the MCU to be powered on and operate. When a voltage is

supplied to Vcc, the input current may cause the supply voltage to rise. Since operations in any cases other than above are

not guaranteed, use the power supply circuit in the system to ensure the supply voltage for the MCU is stable within the

specified range.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 44 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.2

Recommended Operating Conditions (1)

Standard

Symbol

Parameter

Conditions

Unit

Min.

2.7

Typ.

−

0

−

Max.

5.5

VCC/AVCC Supply voltage

V

VSS/AVSS Supply voltage

−

VIH

Input “H” voltage Other than CMOS input

0.8 VCC

0.5 VCC

0.55 VCC

0.65 VCC

VCC

V

CMOS

input

Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V

switching

function

VCC

V

: 0.35 VCC

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

: 0.5 VCC

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

: 0.7 VCC

2.7 V ≤ VCC < 4.0 V

VCC

V

VCC

V

(I/O port)

2.7 V ≤ VCC < 4.0 V

0.7

VCC

V

0.85 VCC

VCC

V

2.7 V ≤ VCC < 4.0 V

0.85 VCC

VCC

V

External clock input (XOUT)

1.2

0

VCC

V

VIL

Input “L” voltage Other than CMOS input

0.2 VCC

V

CMOS

input

Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V

switching

function

0

V

: 0.35 VCC

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

: 0.5 VCC

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

2.7 V ≤ VCC < 4.0 V

0

0.2

0.4

0.3

VCC

V

0

V

(I/O port)

2.7 V ≤ VCC < 4.0 V

0

V

0

0.55 VCC

0.45 VCC

0.4

V

: 0.7 VCC

2.7 V ≤ VCC < 4.0 V

0

V

External clock input (XOUT)

0

V

IOH(sum) Peak sum output “H”

IOH(sum) Average sum output “H”

IOH(peak) Peak output “H” current

Sum of all pins IOH(peak)

Sum of all pins IOH(avg)

−

−80

−40

−10

−5

mA

MHz

−

IOH(avg)

IOL(sum)

Average output “H” current

Peak sum output “L”

−

Sum of all pins IOL(peak)

Sum of all pins IOL(avg)

−

80

Average sum output “L”

−

40

IOL(peak) Peak output “L” current

−

10

IOL(avg)

f(XIN)

Average output “L” current

XIN clock input oscillation frequency

−

5

2.7 V ≤ VCC ≤ 5.5 V

−

20

fOCO40M When used as the count source for timer RC or timer RD

fOCO-F fOCO-F frequency

32

−

40

20

−

System clock frequency

CPU clock frequency

−

20

f(BCLK)

−

20

Notes:

1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 45 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.3

Recommended Operating Conditions (2)

Standard

Typ. Max.

Symbol

Parameter

Conditions

Unit

mA

Min.

IIC(H)

IIC(L)

High input injection P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, V_I> V_CC

current P4_3 to P4_5, P6

Low input injection P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, V_I> V_SS

−

2

−2

8

−

mA

current

P4_3 to P4_5, P6

Σ|IIC|

Total injection current

Note:

1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified.

P0

P1

P2

P3_0, P3_1, P3_3 to P3_5, P3_7

30 pF

P4_2 to P4_7

P6

Figure 5.1

Ports P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_2 to P4_7, and P6 Timing

Measurement Circuit

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 46 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.4

A/D Converter Characteristics

Standard

Symbol

Parameter

Conditions

Unit

Min.

−

Typ.

−

Max.

10

−

Resolution

Vref = AVCC

Bit

Absolute accuracy

10-bit mode

8-bit mode

Vref = AVCC = 5.0 V

Vref = AVCC = 3.0 V

Vref = AVCC = 5.0 V

Vref = AVCC = 3.0 V

AN0 to AN7 input,

AN8 to AN11 input

−

±3

LSB

AN0 to AN7 input,

AN8 to AN11 input

−

±5

±2

LSB

AN0 to AN7 input,

AN8 to AN11 input

AN0 to AN7 input,

AN8 to AN11 input

(2)

φAD

A/D conversion clock

2

−

20

10

−

MHz

kΩ

µA

µs

V

4.0 ≤ Vref = AVCC = ≤ 5.5

2.7 ≤ Vref = AVCC = ≤ 5.5

(2)

−

Tolerance level impedance

Vref current

−

3

Ivref

tCONV

VCC = 5.0 V, XIN = f1 = φAD = 20 MHz

10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz

−

45

−

Conversion time

2.2

0.75

2.7

0

−

8-bit mode

Vref = AVCC = 5.0 V, φAD = 20 MHz

φAD = 20 MHz

−

tSAMP

Vref

Sampling time

−

Reference voltage

−

AVCC

Vref

1.54

(3)

VIA

−

V

Analog input voltage

OCVREF On-chip reference voltage

2 MHz ≤ φAD ≤ 4 MHz

1.14

1.34

V

Notes:

1. VCC/AVCC = Vref = 2.7 to 5.5 V, VSS = 0 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise

specified.

2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-consumption

current mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.

3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 47 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.5

Flash Memory (Program ROM) Electrical Characteristics

Standard

Typ.

Symbol

Parameter

Conditions

Unit

Min.

Max.

(2)

(3)

−

R8C/34X, R8C/34Z Group

R8C/34W, R8C/34Y Group

−

times

µs

Program/erase endurance

100

(3)

1,000

−

Byte program time

−

60

300

(program/erase endurance ≤ 1,000 times)

Byte program time

−

60

500

400

650

4

µs

s

(program/erase endurance > 1,000 times)

Word program time

100

(program/erase endurance ≤ 1,000 times)

Word program time

(program/erase endurance > 1,000 times)

Block erase time

−

0.3

td(SR-SUS) Time delay from suspend request until

suspend

−

5+CPU clock × ms

3 cycles

−

Interval from erase start/restart until

following suspend request

0

−

µs

−

Time from suspend until erase restart

30+CPU clock ×

1 cycle

td(CMDRST- Time from when command is forcibly

READY)

30+CPU clock ×

1 cycle

terminated until reading is enabled

−

Program, erase voltage

Read voltage

2.7

−40

−

5.5

V

Program, erase temperature

85 (J version)

°C

125 (K version)

(7)

(8)

−

20

−

year

Data hold time

Ambient temperature = 55°C

Notes:

1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version) (under consideration), unless otherwise

specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100, 1,000), each block can be erased n times. For example, if 1,024 1-

byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

8. This data hold time includes 3,000 hours in Ta = 125°C and 7,000 hours in Ta = 85°C.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 48 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.6

Flash Memory (Data flash Block A to Block D) Electrical Characteristics

Standard

Typ.

Symbol

Parameter

Conditions

Unit

Min.

10,000

−

Max.

(2)

(3)

−

times

Program/erase endurance

Byte program time

160

950

µs

(program/erase endurance ≤ 1,000 times)

−

Byte program time

(program/erase endurance > 1,000 times)

−

0

−

300

0.2

0.3

−

950

1

µs

s

Block erase time

(program/erase endurance ≤ 1,000 times)

Block erase time

(program/erase endurance > 1,000 times)

1

s

td(SR-SUS) Time delay from suspend request until

suspend

3+CPU clock × ms

3 cycles

−

Interval from erase start/restart until

following suspend request

−

µs

−

Time from suspend until erase restart

−

30+CPU clock ×

1 cycle

td(CMDRST- Time from when command is forcibly

READY)

−

30+CPU clock ×

1 cycle

terminated until reading is enabled

−

Program, erase voltage

Read voltage

2.7

−40

−

5.5

V

Program, erase temperature

85 (J version)

°C

125 (K version)

(7)

(8)

−

20

−

year

Data hold time

Ambient temperature = 55 °C

Notes:

1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100, 1,000, 10,000), each block can be erased n times. For example, if

1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further

reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the

number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

8. This data hold time includes 3,000 hours in Ta = 125°C and 7,000 hours in Ta = 85°C.

Suspend request

(FMR21 bit)

FST7 bit

FST6 bit

Clock-dependent

Fixed time

time

Access restart

td(SR-SUS)

FST6, FST7: Bit in FST register

FMR21: Bit in FMR2 register

Figure 5.2

Time delay until Suspend

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 49 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.7

Voltage Detection 0 Circuit Electrical Characteristics

Standard

Symbol

Parameter

Condition

Unit

Min.

2.70

−

Typ.

2.85

6

Max.

3.00

150

Vdet0

Voltage detection level

Voltage detection 0 circuit response time

At the falling of VCC

V

(3)

−

At the falling of Vcc from

µs

5 V to (Vdet0 − 0.1) V

−

Voltage detection circuit self power consumption

VCA25 = 1, VCC = 5.0 V

−

1.5

−

µA

µs

td(E-A)

Wait time until voltage detection circuit operation starts

−

100

(2)

Notes:

1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

register to 0.

3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.

Table 5.8

Voltage Detection 1 Circuit Electrical Characteristics

Standard

Typ.

3.25

3.40

3.55

3.70

3.85

4.00

4.15

4.30

0.1

Symbol

Parameter

Condition

Unit

Min.

3.05

3.20

3.35

3.50

3.65

3.80

3.95

4.10

−

Max.

3.45

3.60

3.75

3.90

4.05

4.20

4.35

4.50

−

(2)

Vdet1

At the falling of VCC

V

Voltage detection level Vdet1_7

Voltage detection level Vdet1_8

Voltage detection level Vdet1_9

Voltage detection level Vdet1_A

Voltage detection level Vdet1_B

Voltage detection level Vdet1_C

Voltage detection level Vdet1_D

Voltage detection level Vdet1_E

(2)

−

Hysteresis width at the rising of Vcc in voltage detection

1 circuit

(3)

At the falling of Vcc from

−

60

150

µs

Voltage detection 1 circuit response time

5 V to (Vdet1_7 − 0.1) V

−

Voltage detection circuit self power consumption

VCA26 = 1, VCC = 5.0 V

−

1.7

−

µA

µs

td(E-A)

−

100

Wait time until voltage detection circuit operation starts

(4)

Notes:

1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

register to 0.

Table 5.9

Voltage Detection 2 Circuit Electrical Characteristics

Standard

Typ.

Symbol

Parameter

Voltage detection level Vdet2

Condition

Unit

Min.

3.80

−

Max.

4.20

−

Vdet2

At the falling of VCC

4.00

V

−

Hysteresis width at the rising of Vcc in voltage detection

2 circuit

0.1

(2)

−

At the falling of Vcc from

−

20

150

µs

Voltage detection 2 circuit response time

5 V to (Vdet2 − 0.1) V

−

Voltage detection circuit self power consumption

VCA26 = 1, VCC = 5.0 V

−

1.7

−

µA

µs

td(E-A)

−

100

Wait time until voltage detection circuit operation starts

(3)

Notes:

1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

register to 0.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 50 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

(2)

Table 5.10

Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics

Standard

Symbol

Parameter

Condition

Unit

Min.

0

Typ.

Max.

(1)

trth

External power VCC rise gradient

−

50000 mV/msec

Notes:

1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

(1)

Vdet0

(1)

Vdet0

trth

External

Power VCC

0.5 V

(2)

Voltage detection 0

circuit response time

tw(por)

Internal

reset signal

1

× 32

fOCO-S

Notes:

1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of User’s Manual: Hardware (REJ09B0605) for details.

2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a

power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por)

for 1 ms or more.

Figure 5.3

Power-on Reset Circuit Electrical Characteristics

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 51 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.11

High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Symbol

Parameter

Condition

Unit

Min.

Typ.

40

Max.

−

High-speed on-chip oscillator frequency after

reset

VCC = 2.7 V to 5.5 V,

−40°C ≤ Topr ≤ 85°C (J version) /

−

MHz

−40°C ≤ Topr ≤ 125°C (K version)

High-speed on-chip oscillator frequency when

the FRA4 register correction value is written

into the FRA1 register and the FRA5 register

−

36.864

−

5

MHz

%

(3)

correction value into the FRA3 register

High-speed on-chip oscillator frequency when

the FRA6 register correction value is written

into the FRA1 register and the FRA7 register

correction value into the FRA3 register

32

High-speed on-chip oscillator frequency

−5

−

(2)

temperature • supply voltage dependence

−

Oscillation stabilization time

−

200

400

−

µs

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°C

µA

Notes:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator.

3. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

Table 5.12

Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Typ.

Symbol

fOCO-S

Parameter

Condition

Unit

Min.

112.5

Max.

137.5

Low-speed on-chip oscillator frequency

125

kHz

fOCO-WDT Low-speed on-chip oscillator frequency for watchdog

timer

125

−

Oscillation stabilization time

VCC = 5.0 V, Topr = 25°C

−

30

3

100

µs

Self power consumption at oscillation

−

µA

Note:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

Table 5.13

Power Supply Circuit Timing Characteristics

Standard

Typ. Max.

2000

Symbol

Parameter

Condition

Unit

Min.

td(P-R)

Time for internal power supply stabilization during

−

µs

(2)

power-on

Notes:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. Wait time until the internal power supply generation circuit stabilizes during power-on.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 52 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

(1)

Table 5.14

Timing Requirements of SSU

Standard

Symbol

Parameter

Conditions

Unit

Min.

Typ.

−

Max.

(2)

tSUCYC

tHI

SSCK clock cycle time

SSCK clock “H” width

SSCK clock “L” width

4

−

0.6

1

tCYC

0.4

−

tSUCYC

tLO

0.4

−

(2)

tRISE

SSCK clock rising

time

Master

Slave

−

tCYC

−

1

µs

(2)

tFALL

SSCK clock falling

time

Master

Slave

−

1

tCYC

−

100

−

1

µs

tSU

SSO, SSI data input setup time

SSO, SSI data input hold time

−

ns

(2)

tH

1

−

tCYC

tLEAD

Slave

1tCYC + 50

−

ns

SCS setup time

SCS hold time

tLAG

1tCYC + 50

−

(2)

tOD

tSA

tOR

SSO, SSI data output delay time

SSI slave access time

−

1

tCYC

2.7 V ≤ VCC ≤ 5.5 V

1.5tCYC + 100

ns

SSI slave out open time

Notes:

1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version).

2. 1tCYC = 1/f1(s)

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 53 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

SCS (output)

VIL or VOL

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

4-Wire Bus Communication Mode, Master, CPHS = 0

VIH or VOH

SCS (output)

VIL or VOL

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

CPHS, CPOS: Bits in SSMR register

Figure 5.4

I/O Timing of SSU (Master)

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 54 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

SCS (input)

VIL or VOL

tLEAD

tHI

tFALL

tRISE

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

4-Wire Bus Communication Mode, Slave, CPHS = 0

VIH or VOH

SCS (input)

VIL or VOL

tHI

tFALL

tRISE

tLEAD

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

CPHS, CPOS: Bits in SSMR register

Figure 5.5

I/O Timing of SSU (Slave)

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 55 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

tHI

VIH or VOH

SSCK

VIL or VOL

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

Figure 5.6

I/O Timing of SSU (Clock Synchronous Communication Mode)

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 56 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.15

Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]

Standard

Symbol

Parameter

Condition

IOH = −5 mA

Unit

Min.

Typ.

−

Max.

VCC

2.0

VOH

Output “H” voltage Other than XOUT

VCC − 2.0

V

IOH = −200 µA

IOL = 5 mA

VCC − 0.3

−

XOUT

1.0

−

VOL

Output “L” voltage Other than XOUT

−

IOL = 200 µA

IOH = −200 µA

−

0.45

0.5

XOUT

−

VT+-VT-

Hysteresis

0.1

1.2

−

INT0 to INT4, KI0 to KI3,

TRAIO, TRBO,

TRCIOA to TRCIOD,

TRDIOA0 to TRDIOD0,

TRDIOA1 to TRDIOD1,

TRCCLK, TRDCLK,

TRCTRG, ADTRG,

RXD0, RXD2, CLK0,

CLK2, SSI, SCL2,

SDA2, SSO

0.1

1.2

−

V

RESET

IIH

IIL

Input “H” current

Input “L” current

VI = 5 V

VI = 0 V

−

1.0

−1.0

100

−

µA

RPULLUP Pull-up resistance

25

−

50

0.3

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

VRAM

Note:

RAM hold voltage

During stop mode

2.0

−

V

1. 4.2 V ≤ VCC ≤ 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 57 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.16

Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]

(Topr = −40 to 85°C (J version), unless otherwise specified.)

Standard

Typ.

7.0

Symbol

Parameter

Power supply

Condition

Unit

mA

Min.

−

Max.

15

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

ICC

High-speed

clock mode

(1)

current

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are

open, other pins

are VSS

−

5.6

3.6

3.0

2.2

1.5

7.0

3.0

90

12.5

−

mA

µA

−

XIN clock off

High-speed

on-chip

oscillator mode

15

−

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

(1)

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

Low-speed

on-chip

oscillator mode

Wait mode

180

110

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

XIN clock off

15

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

5

100

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Stop mode

−

2.0

5.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

15.0

−

Note:

1. The typical value (Typ.) indicates the current value when the CPU and the memory operate.

The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the

flash memory is programmed/erased.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 58 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.17

Electrical Characteristics (3) [3.3 V ≤ VCC ≤ 5.5 V]

(Topr = −40 to 125°C (K version), unless otherwise specified.)

Standard

Typ.

7.0

Symbol

Parameter

Power supply

Condition

Unit

mA

Min.

−

Max.

15

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

ICC

High-speed

clock mode

(1)

current

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are

open, other pins

are VSS

−

5.6

3.6

3.0

2.2

1.5

7.0

3.0

90

12.5

−

mA

µA

−

XIN clock off

High-speed

on-chip

oscillator mode

15

−

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

(1)

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

Low-speed

on-chip

oscillator mode

Wait mode

400

330

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

XIN clock off

15

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

−

5

320

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Stop mode

−

2.0

5.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 125°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

60.0

−

Note:

1. The typical value (Typ.) indicates the current value when the CPU and the memory operate.

The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the

flash memory is programmed/erased.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 59 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr =

−

40°

C to 85

°

C (J ver)/

−

40

°C to 125

°C (K ver))

Table 5.18

External clock input (XOUT)

Standard

Symbol

Parameter

Unit

Min.

Max.

tc(XOUT)

XOUT input cycle time

XOUT input “H” width

XOUT input “L” width

50

24

−

ns

tWH(XOUT)

tWL(XOUT)

VCC = 5 V

tC(XOUT)

tWH(XOUT)

External Clock Input

tWL(XOUT)

Figure 5.7

External Clock Input Timing Diagram when VCC = 5 V

Table 5.19

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

100

40

tc(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

tWH(TRAIO)

tWL(TRAIO)

40

tC(TRAIO)

VCC = 5 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.8

TRAIO Input Timing Diagram when VCC = 5 V

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 60 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.20

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

200

100

−

Max.

tc(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

−

ns

tW(CKH)

tW(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

−

90

−

0

RXDi input setup time

RXDi input hold time

50

−

90

−

i = 0, 2

VCC = 5 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0, 2

Figure 5.9

Serial Interface Timing Diagram when VCC = 5 V

Table 5.21

External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Standard

Symbol

Parameter

Unit

Min.

Max.

(1)

tW(INH)

tW(INL)

−

ns

250

INTi input “H” width, KIi input “H” width

INTi input “L” width, KIi input “L” width

(2)

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 5 V

INTi input

(i = 0 to 4)

tW(INL)

KIi input

(i = 0 to 3)

tW(INH)

Figure 5.10

Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 61 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.22

Electrical Characteristics (3) [2.7 V ≤ VCC ≤ 4.2 V]

Standard

Symbol

Parameter

Other than XOUT

Condition

IOH = −1 mA

Unit

Min.

Typ.

−

Max.

VCC

0.5

−

VOH

Output “H” voltage

VCC − 0.5

V

XOUT

IOH = −200 µA

IOL = 1 mA

1.0

−

VOL

Output “L” voltage

Hysteresis

Other than XOUT

XOUT

−

IOL = 200 µA

−

VT+-VT-

0.1

0.4

INT0 to INT4, KI0 to KI3,

TRAIO, TRBO,

TRCIOA to TRCIOD,

TRDIOA0 to TRDIOD0,

TRDIOA1 to TRDIOD1,

TRCCLK, TRDCLK,

TRCTRG, ADTRG,

RXD0, RXD2, CLK0,

CLK2, SSI, SCL2,

SDA2, SSO

0.1

0.5

−

V

RESET

IIH

IIL

Input “H” current

Input “L” current

VI = 3 V

VI = 0 V

−

1.0

−1.0

168

−

µA

kΩ

MΩ

V

RPULLUP Pull-up resistance

42

−

84

0.3

−

RfXIN

VRAM

Feedback resistance XIN

RAM hold voltage

During stop mode

2.0

−

Note:

1. 2.7 V ≤ VCC ≤ 4.2 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 62 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.23

Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V]

(Topr = −40 to 85°C (J version), unless otherwise specified.)

Standard

Typ. Max.

Symbol

Parameter

Condition

Unit

mA

Min.

ICC

Power supply current High-speed XIN = 20 MHz (square wave)

−

7.0

5.6

3.6

3.0

2.2

1.5

7.0

3.0

85

14.5

12.0

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

clock mode

(1)

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

mA

µA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

High-speed XIN clock off

on-chip

oscillator

14.5

−

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

(1)

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed XIN clock off

180

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

on-chip

oscillator

mode

Wait mode XIN clock off

High-speed on-chip oscillator off

−

15

110

100

µA

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

5

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode XIN clock off, Topr = 25°C

−

2.0

5.0

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

13.0

−

Note:

1. The typical value (Typ.) indicates the current value when the CPU and the memory operate.

The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the

flash memory is programmed/erased.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 63 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Table 5.24

Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V]

(Topr = −40 to 125°C (K version), unless otherwise specified.)

Standard

Typ. Max.

Symbol

Parameter

Condition

Unit

mA

Min.

ICC

Power supply current High-speed XIN = 20 MHz (square wave)

−

7.0

5.6

3.6

3.0

2.2

1.5

7.0

3.0

85

14.5

12.0

−

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

clock mode

(1)

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

mA

µA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

High-speed XIN clock off

on-chip

oscillator

14.5

−

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

(1)

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

Low-speed XIN clock off

390

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

on-chip

oscillator

mode

Wait mode XIN clock off

High-speed on-chip oscillator off

−

15

320

310

µA

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

5

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode XIN clock off, Topr = 25°C

−

2.0

5.0

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 125°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

55.0

−

Note:

1. The typical value (Typ.) indicates the current value when the CPU and the memory operate.

The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the

flash memory is programmed/erased.

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 64 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr =

−

40°

C to 85

°

C (J ver)/

−

40

°C to 125

°C (K ver))

Table 5.25

External clock input (XOUT)

Standard

Symbol

Parameter

Unit

Min.

Max.

tc(XOUT)

XOUT input cycle time

XOUT input “H” width

XOUT input “L” width

50

24

−

ns

tWH(XOUT)

tWL(XOUT)

tC(XOUT)

VCC = 3 V

tWH(XOUT)

External Clock Input

tWL(XOUT)

Figure 5.11

External Clock Input Timing Diagram when VCC = 3 V

Table 5.26

TRAIO Input

Standard

Symbol

Parameter

Unit

Min.

300

120

Max.

tc(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

tWH(TRAIO)

tWL(TRAIO)

VCC = 3 V

tC(TRAIO)

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.12

TRAIO Input Timing Diagram when VCC = 3 V

Table 5.27

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

300

150

−

Max.

tc(CK)

CLKi input cycle time

CLKi input “H” width

CLKi Input “L” width

TXDi output delay time

TXDi hold time

−

ns

tW(CKH)

tW(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

−

140

−

0

RXDi input setup time

RXDi input hold time

70

−

90

−

i = 0, 2

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 65 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

5. Electrical Characteristics

tC(CK)

VCC = 3 V

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

td(C-Q)

tsu(D-C)

th(C-D)

RXDi

i = 0, 2

Figure 5.13

Serial Interface Timing Diagram when VCC = 3 V

Table 5.28

External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Standard

Symbol

Parameter

Unit

Min.

Max.

(1)

tW(INH)

tW(INL)

−

ns

380

INTi input “H” width, KIi input “H” width

INTi input “L” width, KIi input “L” width

(2)

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 3 V

INTi input

(i = 0 to 4)

tW(INL)

KIi input

(i = 0 to 3)

tW(INH)

Figure 5.14

Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 66 of 67

Preliminary document

Specifications in this document are tentative and subject to change.

Under development

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Electronics website.

JEITA Package Code

P-LQFP48-7x7-0.50

RENESAS Code

PLQP0048KB-A

Previous Code

48P6Q-A

MASS[Typ.]

0.2g

H_D

*1

D

36

25

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

37

24

bp

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

6.9 7.0 7.1

1.4

Terminal cross section

48

13

A₂

H_D

H_E

A

8.8 9.0 9.2

1.7

1

12

Index mark

Z_D

A₁

b_p

b₁

c

0

0.1 0.2

0.17 0.22 0.27

0.20

F

c

0.145

0.125

0.09

0.20

S

L

c₁

L₁

0°

8°

e

0.5

y

S

*3

x

Detail F

0.08

0.10

b_p

e

x

y

Z_D

Z_E

L

0.75

0.5

0.35

0.65

L₁

1.0

REJ03B0312-0010 Rev.0.10

Apr 09, 2010

Page 67 of 67

R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group

Datasheet

REVISION HISTORY

Description

Summary

Rev.

0.10

Date

Page

—

Apr 09, 2010

First Edition issued

All trademarks and registered trademarks are the property of their respective owners.

C - 1

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or

technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific":

Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

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redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

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http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

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Tel: +1-408-588-6000, Fax: +1-408-588-6130

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Tel: +1-905-898-5441, Fax: +1-905-898-3220

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Tel: +44-1628-585-100, Fax: +44-1628-585-900

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Tel: +49-211-65030, Fax: +49-211-6503-1327

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Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

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Tel: +82-2-558-3737, Fax: +82-2-558-5141

Colophon 1.0


型号：	R5F21347EJFP
厂家：	RENESAS TECHNOLOGY CORP
描述：	FLASH, 20MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件：	总70页 (文件大小：596K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F21347EJFP [RENESAS]

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