R5F21368SDFP [RENESAS]
RENESAS MCU; 瑞萨MCU
| 型号： | R5F21368SDFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | RENESAS MCU |
| 文件： | 总61页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
R8C/36T-A Group
RENESAS MCU
R01DS0055EJ0100
Rev.1.00
Dec 09, 2011
1. Overview
1.1
Features
The R8C/36T-A Group of single-chip microcontrollers (MCUs) incorporates the R8C CPU core, which provides
sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of
executing instructions at high speed. In addition, it features a multiplier for high-speed arithmetic processing.
Power consumption is low, and additional power control is possible by selecting the operating mode. The R8C/36T-
A Group is also designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface on the same chip,
reduces the number of system components.
The R8C/36T-A Group integrates a touch sensor control unit, which enables detection of the floating capacitance of
the electrostatic capacitive touch electrode.
This group also has on-chip data flash (1 KB × 4 blocks) with background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 1 of 58
R8C/36T-A Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline Specifications.
Table 1.1
Specifications (1)
Item
CPU
Function
Description
Central
R8C CPU core
processing unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (CPU clock = 20 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 5.5 V)
• Multiplier: 16 bits × 16 bits 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM,
data flash
Refer to Table 1.3 Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Clock
Programmable
I/O ports
• Input only: 1
• CMOS I/O: 59, selectable pull-up resistor
• High current drive ports: 59
Clock generation • 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit,
circuits high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, low-speed
clock, high-speed on-chip oscillator, low-speed on-chip
oscillator), wait mode, stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(30 sources × 10 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 27
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timers RJ_0
Timer RB2_0
16 bits × 1: 1 circuit integrated on-chip
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
16 bits × 1: 1 circuit integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
Timer RE2
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
8 bits × 1
Compare match timer mode, real-time clock mode
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Dec 09, 2011
Page 2 of 58
R8C/36T-A Group
1. Overview
Table 1.2
Specifications (2)
Item
Function
Description
Serial interface UART0_0 and
UART0_1
2 channels
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode, I2C
mode (I2C-bus), multiprocessor communication mode
1 channel (also used for the I2C bus)
Clock
(SSU)
Synchronous
serial
interface
SSU_0
(I2C bus)
I2C_0
1 channel (also used for the SSU)
LIN
HW-LIN_0
Hardware LIN
module
1 channel (timer RJ_0, UART0_0, or UART0_1 used)
A/D converter
Comparator B
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
2 circuits
Touch Sensor control unit (TSCU) System CH × 4, electrostatic capacitive touch detection × 28
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
CRC calculator
Flash memory
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
Operating frequency/
Power supply voltage
CPU clock = 20 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 5.5 V)
Current consumption
Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 4.0 A (VCC = 3.0 V, wait mode f(XCIN) = 32 kHz)
Typ. 2.2 A (VCC = 3.0 V, stop mode)
Operating ambient temperature
Package
-20C to 85C (N version)
-40C to 85C (D version) (1)
64-pin LQFP
Package code: PLQP0064KB-A (previous code: 64P6Q-A)
Package code: PLQP0064GA-A (previous code: 64P6U-A)
Note:
1. Specify the D version if it is to be used.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 3 of 58
R8C/36T-A Group
1. Overview
1.2
Product List
Table 1.3 lists product information. Figure 1.1 shows the Product Part Number Structure.
Table 1.3 Product List
Part No.
Current of Dec 2011
Internal ROM Capacity
Internal RAM
Capacity
Package Type
Remarks
Program ROM
Data Flash
1 Kbyte × 4
R5F21368SNFP
R5F2136ASNFP
R5F2136CSNFP
R5F21368SNFA
R5F2136ASNFA
R5F2136CSNFA
R5F21368SDFP
R5F2136ASDFP
R5F2136CSDFP
R5F21368SDFA
R5F2136ASDFA
R5F2136CSDFA
64 Kbytes
96 Kbytes
128 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0064KB-A N version
PLQP0064GA-A
PLQP0064KB-A D version
PLQP0064GA-A
Part No. R 5 F 21 36 C S N FP
Package type:
FP: PLQP0064KB-A
(0.5 mm pin pitch, 10 10 mm square body)
FA: PLQP0064GA-A
(0.8 mm pin pitch, 14 14 mm square body)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
8: 64 KB
A: 96 KB
C: 128 KB
R8C/36T-A Group
R8C/3xT-A Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Product Part Number Structure
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 4 of 58
R8C/36T-A Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows the Block Diagram.
8
8
8
5
1
8
7
8
Port P0
Port P1
Port P2
I/O ports
Port P3
Port P5
Port P6
Port P4
System clock generation circuit
Peripheral functions
XIN-XOUT
A/D converter
(10 bits 12 channels)
XCIN-XCOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Low-speed on-chip oscillator
(for watchdog timer)
Timers
Timer RJ (16 bits 1)
Timer RB2 (16 bits 1)
Timer RC (16 bits 1)
Timer RE2 (8 bits 1)
UART0
(8 bits 2 channels)
Voltage detection circuit
UART2
(8 bits 1 channel)
DTC
Comparator B
Synchronous serial
Event link controller
TSCU
(28 channels)
communication unit (SSU/I2C)
(8 bits 1 channel)
LIN module
(1 channel)
Watchdog timer
(14 bits)
Memory
R8C CPU core
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
ROM (1)
R2
R3
CRC calculator
RAM (2)
A0
A1
FB
Multiplier
Port P8
7
Notes:
1. ROM size varies with the product.
2. RAM size varies with the product.
Figure 1.2
Block Diagram
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 5 of 58
R8C/36T-A Group
1. Overview
1.4
Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Tables 1.4 to 1.6 list the Pin Name Information by Pin Number.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0_7/AN0(/TRCIOC_0)
P0_6/AN1(/TRCIOD_0)
P8_4/CHxB
P8_5/CHxC
P0_5/AN2(/TRCIOB_0)
P8_6/CH08
P0_4/AN3/TMRE2O(/TRCIOB_0)
P0_3/AN4(/CLK_1/TRCIOB_0)
P3_1/CH10
P3_6/CH11
P0_2/AN5(/RXD_1/TRCIOA_0/TRCTRG_0)
P0_1/AN6(/TXD_1/TRCIOA_0/TRCTRG_0)
P0_0/AN7(/TRCIOA_0/TRCTRG_0
P6_4(/RXD_1/CH35)
P2_0(/INT1/TRCIOB_0/CH16)
P2_1(/TRCIOC_0/CH17)
P2_2(/TRCIOD_0/CH18)
P2_3/CH19
R8C/36T-A Group
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
(Top view)
P6_3(/TXD_1/CH34)
P2_4/CH20
P6_2(/CLK_1/CH33)
P2_5/CH21
P6_1(/CH32)
P2_6/CH22
P6_0(/TMRE2O/CH31)
P2_7/CH23
P5_7(/CH28)
P3_3/IVCMP3/INT3/SCS_0(/CTS2/RTS2/TRCCLK_0)
P3_4/IVREF3/SSI_0(/RXD2/SCL2/TXD2/SDA2/TRCIOC_0)
P3_5/SCL_0/SSCK_0(/CLK2/TRCIOD_0)
63
64
P5_6(/CH27)
P3_2(/INT1/INT2/TRJIO_0/CH25)
Figure 1.3
Pin Assignment (Top View)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 6 of 58
R8C/36T-A Group
1. Overview
Table 1.4
Pin Name Information by Pin Number (INT, URAT0, and UART2)
INT
UART0
UART2
RTS2
Port
Pin No.
INT0
INT1
INT2
INT3
INT4
TXD_0
TXD_1
TXD_1
RXD_0 RXD_1
CLK_0
CLK_1
TXD2
RXD2
CTS2
SDA2
SCL2
CLK2
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_6
P5_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P8_0
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
27
26
25
24
23
22
21
20
1
RXD_1
CLK_1
TXD_0
INT1
RXD_0
CLK_0
INT1
INT1
29
64
19
18
17
28
16
2
INT1
INT2
INT3
CTS2
RTS2
TXD2
TXD2
RXD2
RXD2
SDA2
SDA2
SCL2
SCL2
CLK2
4
5
40
9
INT0
RXD2
SCL2
7
15
14
13
12
11
63
62
61
60
59
58
57
39
38
37
36
35
34
33
32
31
30
CLK_1
CLK_1
TXD_1
RXD_1
INT4
CLK2
INT2
TXD2
SDA2
INT3
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Dec 09, 2011
Page 7 of 58
R8C/36T-A Group
1. Overview
2
Table 1.5
Pin Name Information by Pin Number (SSU/I C, Timer RJ, and Timer RB2)
SSU/I2C
Timer RJ
Timer RB2
TRBO_0
Port
Pin No.
SCL_0
SDA_0
SSI_0
SCS_0
SSCK_0
SSO_0
TRJO_0
TRJIO_0
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_6
P5_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P8_0
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
27
26
25
24
23
22
21
20
1
TRBO_0
TRJIO_0
TRJO_0
29
64
19
18
17
28
16
2
TRJIO_0
SCS_0
SSI_0
SCL_0
SSCK_0
SDA_0
SSO_0
4
5
40
9
7
15
14
13
12
11
63
62
61
60
59
58
57
39
38
37
36
35
34
33
32
31
30
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 8 of 58
R8C/36T-A Group
1. Overview
Table 1.6
Pin Name Information by Pin Number (Timer RC, Timer RE2, and Others)
Timer RC
Timer RE2
Port
Pin No.
Others
TRCCLK_0
TRCIOA_0
TRCIOA_0
TRCIOA_0
TRCIOA_0
TRCIOB_0
TRCIOC_0
TRCIOD_0
TRCTRG_0
TRCTRG_0
TRCTRG_0
TRCTRG_0
TMRE2O
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_6
P5_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P8_0
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
27
26
25
24
23
22
21
20
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AN8
AN9
AN10
AN11
TRCIOB_0
TRCIOB_0
TRCIOB_0
TMRE2O
TRCIOD_0
TRCIOD_0
TRCIOC_0
TRCIOC_0
KI0
KI1
KI2
KI3
TRCIOA_0
TRCTRG_0
TRCIOB_0
TRCCLK_0
IVREF1
IVCMP1
CH00
CH01
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH10
CH25
TRCIOB_0
TRCIOC_0
TRCIOD_0
29
64
19
18
17
28
16
2
TRCCLK_0
IVCMP3
IVREF3
TRCIOC_0
TRCIOD_0
CH11
CH02
VREF
XCIN
4
5
XCOUT
ADTRG
XIN
40
9
7
XOUT
15
14
13
12
11
63
62
61
60
59
58
57
39
38
37
36
35
34
33
32
31
30
TRCCLK_0
TRCIOA_0
TRCTRG_0
TRCIOB_0
TRCIOC_0
TRCIOD_0
CH27
CH28
CH31
CH32
CH33
CH34
CH35
CH03
CH04
CH05
CH06
CH07
CHxA0
CHxA1
CHxB
CHxC
CH08
TMRE2O
TRCIOB_0
TRCIOC_0
TRCIOD_0
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R8C/36T-A Group
1. Overview
1.5
Pin Functions
Tables 1.7 and 1.8 list Pin Functions.
Table 1.7
Item
Pin Functions (1)
Pin Name
VCC, VSS
I/O
—
Description
Power supply input
Apply 1.8 V through 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power supply
input
AVCC, AVSS
—
I
Power supply input for the A/D converter.
Connect a capacitor between pins AVCC and AVSS.
Reset input
Applying a low level to this pin resets the MCU.
RESET
MODE
XIN
MODE
I
I
Connect this pin to the VCC pin via a resistor.
XIN clock input
XIN clock output
I/O for the XIN clock generation circuit.
Connect a ceramic resonator or a crystal oscillator
between pins XIN and XOUT. (1)
XOUT
I/O
To use an external clock, input it to the XIN pin and
leave the XOUT pin open.
XCIN clock input
XCIN clock output
XCIN
I
I/O for the XCIN clock generation circuit.
Connect a crystal oscillator between pins XCIN and
XCOUT. (1)
XCOUT
I/O
To use an external clock, input it to the XCOUT pin and
leave the XCIN pin open.
I
I
INT interrupt input
Key input interrupt
INT0 to INT4
INT interrupt input.
Key input interrupt input.
KI0 to KI3
TRJIO_0
Timer RJ_0
I/O
O
O
I
Input/output for timer RJ.
Output for timer RJ.
TRJO_0
Timer RB2_0
Timer RC_0
TRBO_0
Output for timer RB2.
External clock input.
External trigger input.
Input/output for timer RC.
TRCCLK_0
TRCTRG_0
I
TRCIOA_0, TRCIOB_0,
TRCIOC_0, TRCIOD_0
I/O
Timer RE2
TMRE2O
O
I/O
I
Divided clock output.
Transfer clock input/output.
Serial data input.
Serial interface
(UART0)
CLK_0, CLK_1
RXD_0, RXD_1
TXD_0, TXD_1
O
I
Serial data output.
Serial interface
(UART2)
Input for transmission control.
CTS2
O
Output for reception control.
RTS2
SCL2
SDA2
RXD2
TXD2
CLK2
SSI_0
I2C mode clock input/output.
I2C mode data input/output.
Serial data input.
I/O
I/O
I
O
Serial data output.
I/O
I/O
I/O
Transfer clock input/output.
Data input/output.
Synchronous serial
communication unit
(SSU_0)
Chip-select input/output.
SCS_0
I/O
Clock input/output.
SSCK_0
SSO_0
SCL_0
SDA_0
VREF
I/O
I/O
I/O
I
Data input/output.
I2C bus (I2C_0)
Clock input/output.
Data input/output.
Reference voltage
input
Reference voltage input for the A/D converter.
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/36T-A Group
1. Overview
Table 1.8
Pin Functions (2)
Pin Name
Item
I/O
Description
A/D converter
AN0 to AN11
I
I
Analog input for the A/D converter.
External trigger input for the A/D converter.
ADTRG
Comparator B
IVCMP1, IVCMP3
IVREF1, IVREF3
I
I
Analog voltage input for comparator B.
Reference voltage input for comparator B.
Touch sensor control
unit
CHxA0, CHxA1, CHxB,
CHxC
I/O
Control pins for electrostatic capacitive touch detection.
CH00 to CH08, CH10,
CH11, CH16 to CH25,
CH27, CH28,
I
Electrostatic capacitive touch detection pins.
CH31 to CH35
I/O ports
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_7,
P5_0 to P5_4, P5_6,
P5_7,
I/O
8-bit CMOS input/output ports.
Each port has an I/O select direction register, enabling
switching input and output for each pin.
For input ports, the presence or absence of a pull-up
resistor can be selected by a program.
All ports can be used as LED drive (high drive) ports.
P6_0 to P6_7,
P8_0 to P8_6
Input port
P4_2
I
Input-only port.
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R8C/36T-A Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the 13 CPU Registers. The registers R0, R1, R2, R3, A0, A1, and FB form a single register bank. The
CPU has two register banks.
b31
b15
b8 b7
b0
R0H (R0 high-order byte) R0L (R0 low-order byte)
R2
R3
R1H (R1 high-order byte) R1L (R1 low-order byte)
Data registers (1)
R2
R3
A0
A1
FB
Address registers (1)
Frame base register (1)
b19
b15
b0
Interrupt table register
Program counter
INTBH
INTBL
The higher 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
b15
b8 b7
IPL
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bits
Processor interrupt priority level
Reserved bit
Note:
1. These registers form a single register bank.
The CPU has two register banks.
Figure 2.1
CPU Registers
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R8C/36T-A Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3.
R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers.
The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0).
Similarly, R3 and R1 can be used as a 32-bit data register.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
PC is a 20-bit register that indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch
between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. It must only be set to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0.
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2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I
flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware
interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is
executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has
higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
The write value must be 0. The read value is undefined.
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R8C/36T-A Group
3. Address Space
3. Address Space
3.1
Memory Map
Figure 3.1 shows the Memory Map. The R8C/36T-A Group has a 1-Mbyte address space from addresses 00000h to
FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower addresses, beginning with
address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses, beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (2)
0FFDCh
06FFFh
07000h
Undefined instruction
Overflow
Internal ROM
(data flash) (1)
BRK instruction
Address match
07FFFh
0YYYYh
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the ELC, DTC, and TSCU SFR areas.
3. The blank areas are reserved. No access is allowed.
Internal ROM
Internal RAM
Part Number
Address 0YYYYh Address ZZZZZh
Address 0XXXXh
Capacity
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
6 Kbytes
8 Kbytes
10 Kbytes
R5F21368SNFP/FA, R5F21368SDFP/FA
R5F21368SNFP/FA, R5F21368SDFP/FA
R5F21368SNFP/FA, R5F21368SDFP/FA
08000h
08000h
08000h
17FFFh
1FFFFh
27FFFh
01BFFh
023FFh
02BFFh
Figure 3.1
Memory Map
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3. Address Space
3.2
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 3.1 to 3.16 list the SFR
Information. Table 3.17 lists the ID code Area, Option Function Select Area.
(1)
Table 3.1
SFR Information (1)
Address
Symbol
Register Name
After Reset
Remarks
00000h
00001h
00002h
00003h
00004h PM0
00005h PM1
00006h
Processor Mode Register 0
Processor Mode Register 1
00h
10000000b
00007h PRCR
00008h CM0
00009h CM1
0000Ah OCD
0000Bh CM3
0000Ch CM4
0000Dh
Protect Register
00h
System Clock Control Register 0
System Clock Control Register 1
Oscillation Stop Detection Register
System Clock Control Register 3
System Clock Control Register 4
00101000b
00100000b
00h
00h
00000001b
0000Eh
0000Fh
00010h CPSRF
00011h
00012h FRA0
00013h
00014h FRA2
00015h
Clock Prescaler Reset Flag
00h
00h
00h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 2
00016h
00017h
00018h
00019h
0001Ah
0001Bh
0001Ch
0001Dh
0001Eh
0001Fh
00020h RISR
Reset Interrupt Select Register
10000000b or
00000000b
FFh
(Note 2)
00021h WDTR
00022h WDTS
00023h WDTC
00024h CSPR
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Count Source Protection Mode Register
FFh
01111111b
10000000b or
00000000b
(Note 2)
00025h
00026h
00027h
00028h RSTFR
00029h
0002Ah
0002Bh
0002Ch SVDC
0002Dh
Reset Source Determination Register
STBY VDC Power Control Register
00XXXXXXb
00h
0002Eh
0002Fh
00030h CMPA
00031h VCAC
00032h OCVREFCR
00033h
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
On-Chip Reference Voltage Control Register
00h
00h
00h
00034h VCA2
Voltage Detection Register 2
00000000b or
00100000b
(Note 3)
(Note 3)
00035h
00036h VD1LS
00037h
Voltage Detection 1 Level Select Register
Voltage Monitor 0 Circuit Control Register
Voltage Monitor 1 Circuit Control Register
00000111b
00038h VW0C
1100XX10b or
1100XX11b
10001010b
00039h VW1C
X: Undefined
Notes:
1. The blank areas are reserved. No access is allowed.
2. Depends on the CSPROINI bit in the OFS register.
3. Depends on the LVDASI bit in the OFS register.
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3. Address Space
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Table 3.2
SFR Information (2)
Address
0003Ah VW2C
0003Bh
Symbol
Register Name
Voltage Monitor 2 Circuit Control Register
After Reset
10001010b
Remarks
0003Ch
0003Dh
0003Eh
0003Fh
00040h
00041h FMRDYIC
00042h
Interrupt Control Register
00h
00043h
00044h
00045h
00046h INT4IC
00047h TRCIC_0
00048h
Interrupt Control Register
Interrupt Control Register
00h
00h
00049h
0004Ah TRE2IC
0004Bh U2TIC
0004Ch U2RIC
0004Dh KUPIC
0004Eh ADIC
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
00h
00h
00h
0004Fh SSUIC_0/IICIC_0 Interrupt Control Register
00050h
00051h U0TIC_0
00052h U0RIC_0
00053h U0TIC_1
00054h U0RIC_1
00055h INT2IC
00056h TRJIC_0
00057h
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
00h
00h
00h
00058h TRB2IC_0
00059h INT1IC
0005Ah INT3IC
0005Bh
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
0005Ch
0005Dh INT0IC
0005Eh U2BCNIC
0005Fh
Interrupt Control Register
Interrupt Control Register
00h
00h
00060h
00061h
00062h
00063h
00064h
00065h
00066h
00067h
00068h
00069h
0006Ah
0006Bh
0006Ch
0006Dh
0006Eh
0006Fh
00070h
00071h
00072h VCMP1IC
00073h VCMP2IC
00074h
Interrupt Control Register
Interrupt Control Register
00h
00h
00075h TSCUIC
00076h
Interrupt Control Register
00h
00077h
00078h
00079h
Note:
1. The blank areas are reserved. No access is allowed.
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3. Address Space
(1)
Table 3.3
SFR Information (3)
Address
Symbol
Register Name
After Reset
Remarks
0007Ah
0007Bh
0007Ch
0007Dh
0007Eh
0007Fh
00080h U0MR_0
00081h U0BRG_0
00082h U0TB_0
00083h
UART0_0 Transmit/Receive Mode Register
UART0_0 Bit Rate Register
UART0_0 Transmit Buffer Register
00h
XXh
XXh
XXh
00084h U0C0_0
00085h U0C1_0
00086h U0RB_0
00087h
UART0_0 Transmit/Receive Control Register 0
UART0_0 Transmit/Receive Control Register 1
UART0_0 Receive Buffer Register
00001000b
00000010b
XXXXh
00088h U0IR_0
00089h
UART0_0 Interrupt Flag and Enable Register
00h
0008Ah
0008Bh
0008Ch LINCR2_0
0008Dh
LIN_0 Special Function Register
00h
0008Eh LINCT_0
0008Fh LINST_0
00090h U0MR_1
00091h U0BRG_1
00092h U0TB_1
00093h
LIN_0 Control Register
LIN_0 Status Register
UART0_1 Transmit/Receive Mode Register
UART0_1 Bit Rate Register
UART0_1 Transmit Buffer Register
00h
00h
00h
XXh
XXh
XXh
00094h U0C0_1
00095h U0C1_1
00096h U0RB_1
00097h
UART0_1 Transmit/Receive Control Register 0
UART0_1 Transmit/Receive Control Register 1
UART0_1 Receive Buffer Register
00001000b
00000010b
XXXXh
00098h U0IR_1
00099h
UART0_1 Interrupt Flag and Enable Register
00h
0009Ah
0009Bh
0009Ch
0009Dh
0009Eh
0009Fh
000A0h
000A1h
000A2h
000A3h
000A4h
000A5h
000A8h
000A9h
000AAh
000ABh
000ACh
000ADh
000AEh
000AFh
000B0h
000B1h
000B4h
000B5h
000B8h
000B9h
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
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3. Address Space
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Table 3.4
SFR Information (4)
Address
Symbol
Register Name
After Reset
Remarks
000BAh
000BBh
000BCh
000BDh
000BEh
000BFh
000C0h U2MR
000C1h U2BRG
000C2h U2TB
000C3h
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
00h
00h
00h
00h
000C4h U2C0
000C5h U2C1
000C6h U2RB
000C7h
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
00001000b
00000010b
0000h
000C8h U2RXDF
000C9h
UART2 Digital Filter Function Select Register
00h
000CAh
000CBh
000CCh
000CDh
000CEh
000CFh
000D0h U2SMR5
000D1h
UART2 Special Mode Register 5
00h
000D2h
000D3h
000D4h U2SMR4
000D5h U2SMR3
000D6h U2SMR2
000D7h U2SMR
000D8h
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
00h
00h
00h
00h
000D9h
000DAh
000DBh
000DCh
000DDh
000DEh
000DFh
2
000E0h IICCR_0
000E1h SSBR_0
000E2h SITDR_0
000E3h
00001110b
11111000b
FFh
I C_0 Control Register
SS_0 Bit Counter Register
SI_0 Transmit Data Register
FFh
000E4h SIRDR_0
000E5h
SI_0 Receive Data Register
FFh
FFh
000E6h SICR1_0
000E7h SICR2_0
000E8h SIMR1_0
000E9h SIER_0
000EAh SISR_0
000EBh SIMR2_0
000ECh
SI_0 Control Register 1
SI_0 Control Register 2
SI_0 Mode Register 1
SI_0 Interrupt Enable Register
SI_0 Status Register
00h
01111101b
00010000b
00h
00h
00h
SI_0 Mode Register 2
000EDh
000EEh
000EFh
000F0h
000F1h
000F2h
000F3h
000F4h
000F5h
000F6h
000F7h
000F8h
000F9h
Note:
1. The blank areas are reserved. No access is allowed.
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3. Address Space
(1)
Table 3.5
SFR Information (5)
Address
Symbol
Register Name
After Reset
Remarks
000FAh
000FBh
000FCh
000FDh
000FEh
000FFh
00100h
00101h
00102h
00103h
00104h
00105h
00106h
00107h
00108h
00109h
0010Ah
0010Bh
0010Ch
0010Dh
0010Eh
0010Fh
00110h TRJ_0
00111h
Timer RJ_0 Counter Register
FFFFh
00112h TRJCR_0
00113h TRJIOC_0
00114h TRJMR_0
00115h TRJISR_0
00116h
Timer RJ_0 Control Register
Timer RJ_0 I/O Control Register
Timer RJ_0 Mode Register
00h
00h
00h
00h
Timer RJ_0 Event Pin Select Register
00117h
00118h
00119h
0011Ah
0011Bh
0011Ch
0011Dh
0011Eh
0011Fh
00120h
00121h
00122h
00123h
00124h
00125h
00126h
00127h
00128h
00129h
0012Ah
0012Bh
0012Ch
0012Dh
0012Eh
0012Fh
00130h TRBCR_0
00131h TRBOCR_0
00132h TRBIOC_0
00133h TRBMR_0
00134h TRBPRE_0
00135h TRBPR_0
00136h TRBSC_0
00137h TRBIR_0
00138h TRCCNT_0
00139h
Timer RB2_0 Control Register
Timer RB2_0 One-Shot Control Register
Timer RB2_0 I/O Control Register
Timer RB2_0 Mode Register
Timer RB2_0 Prescaler Register
Timer RB2_0 Primary Register
Timer RB2_0 Secondary Register
Timer RB2_0 Interrupt Request Register
Timer RC_0 Counter
00h
00h
00h
00h
FFh
FFh
FFh
00h
0000h
Note:
1. The blank areas are reserved. No access is allowed.
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(1)
Table 3.6
SFR Information (6)
Address
Symbol
Register Name
After Reset
Remarks
0013Ah TRCGRA_0
0013Bh
0013Ch TRCGRB_0
0013Dh
0013Eh TRCGRC_0
0013Fh
00140h TRCGRD_0
00141h
Timer RC_0 General Register A
Timer RC_0 General Register B
Timer RC_0 General Register C
Timer RC_0 General Register D
FFFFh
FFFFh
FFFFh
FFFFh
00142h TRCMR_0
00143h TRCCR1_0
00144h TRCIER_0
00145h TRCSR_0
00146h TRCIOR0_0
00147h TRCIOR1_0
00148h TRCCR2_0
00149h TRCDF_0
0014Ah TRCOER_0
0014Bh TRCADCR_0
0014Ch TRCOPR_0
0014Dh TRCELCCR_0
0014Eh
Timer RC_0 Mode Register
Timer RC_0 Control Register 1
Timer RC_0 Interrupt Enable Register
Timer RC_0 Status Register
Timer RC_0 I/O Control Register 0
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00011000b
00h
01111111b
11110000b
00h
Timer RC_0 I/O Control Register 1
Timer RC_0 Control Register 2
Timer RC_0 Digital Filter Function Select Register
Timer RC_0 Output Enable Register
Timer RC_0 A/D Conversion Trigger Control Register
Timer RC_0 Output Waveform Manipulation Register
Timer RC_0 ELC Cooperation Control Register
00h
0014Fh
00150h
00151h
00152h
00153h
00154h
00155h
00156h
00157h
00158h
00159h
0015Ah
0015Bh
0015Ch
0015Dh
0015Eh
0015Fh
00160h
00161h
00162h
00163h
00164h
00165h
00166h
00167h
00168h
00169h
0016Ah
0016Bh
0016Ch
0016Dh
0016Eh
0016Fh
00170h TRESEC
Timer RE2 Counter Data Register
Timer RE2 Second Data Register
Timer RE2 Compare Data Register
Timer RE2 Minute Data Register
Timer RE2 Hour Data Register
Timer RE2 Day-of-the-Week Data Register
Timer RE2 Day Data Register
Timer RE2 Month Data Register
Timer RE2 Year Data Register
00h
00h
00171h TREMIN
00172h TREHR
00173h TREWK
00174h TREDY
00175h TREMON
00176h TREYR
00177h TRECR
00178h TRECSR
00179h TREADJ
00h
00h
00000001b
00000001b
00h
00000100b
00001000b
00h
Timer RE2 Control Register
Timer RE2 Count Source Select Register
Timer RE2 Clock Error Correction Register
Note:
1. The blank areas are reserved. No access is allowed.
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Table 3.7
SFR Information (7)
Address
Symbol
Register Name
After Reset
Remarks
0017Ah TREIFR
0017Bh TREIER
0017Ch TREAMN
0017Dh TREAHR
0017Eh TREAWK
0017Fh TREPRC
00180h
Timer RE2 Interrupt Flag Register
Timer RE2 Interrupt Enable Register
Timer RE2 Alarm Minute Register
Timer RE2 Alarm Hour Register
Timer RE2 Alarm Day-of-the-Week Register
Timer RE2 Protect Register
00h
00h
00h
00h
00h
00h
to
001FFh
00200h AD0
00201h
00202h AD1
00203h
00204h AD2
00205h
00206h AD3
00207h
00208h AD4
00209h
0020Ah AD5
0020Bh
0020Ch AD6
0020Dh
0020Eh AD7
0020Fh
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00210h
00211h
00212h
00213h
00214h ADMOD
00215h ADINSEL
00216h ADCON0
00217h ADCON1
00218h
A/D Mode Register
00h
11000000b
00h
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
00h
00219h
0021Ah
0021Bh
0021Ch
0021Dh
0021Eh
0021Fh
00220h
00221h
00222h
00223h
00224h
00225h
00226h
00227h
00228h INTCMP
00229h
Comparator B Control Register 0
00h
0022Ah
0022Bh
0022Ch
0022Dh
0022Eh
0022Fh
00230h INTEN
00231h INTEN1
00232h INTF
00233h INTF1
00234h INTPOL
00235h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
INT Input Polarity Switch Register
00h
00h
00h
00h
00h
00236h KIEN
00237h
Key Input Interrupt Enable Register
00h
00238h MSTCR0
00239h MSTCR1
Module Standby Control Register 0
Module Standby Control Register 1
00h
00h
Note:
1. The blank areas are reserved. No access is allowed.
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3. Address Space
(1)
Table 3.8
SFR Information (8)
Address
Symbol
Register Name
After Reset
Remarks
0023Ah MSTCR2
0023Bh MSTCR3
0023Ch MSTCR4
0023Dh
Module Standby Control Register 2
Module Standby Control Register 3
Module Standby Control Register 4
00h
00h
00h
0023Eh
0023Fh
00240h
00241h
00242h
00243h
00244h
00245h
00246h
00247h
00248h
00249h
0024Ah
0024Bh
0024Ch
0024Dh
0024Eh
0024Fh
00250h
00251h
00252h FST
00253h
Flash Memory Status Register
10000X00b
00254h FMR0
00255h FMR1
00256h FMR2
00257h
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
00h
00h
00h
00258h
00259h
0025Ah
0025Bh
0025Ch
0025Dh
0025Eh
0025Fh
00260h AIADR0L
00261h
Address Match Interrupt Address 0L Register
XXXXh
00262h AIADR0H
00263h AIEN0
00264h AIADR1L
00265h
Address Match Interrupt Address 0H Register
Address Match Interrupt Enable 0 Register
Address Match Interrupt Address 1L Register
0000XXXXb
00h
XXXXh
00266h AIADR1H
00267h AIEN1
00268h
Address Match Interrupt Address 1H Register
Address Match Interrupt Enable 1 Register
0000XXXXb
00h
00269h
0026Ah
0026Bh
0026Ch
0026Dh
0026Eh
0026Fh
00270h
00271h
00272h
00273h
00274h
00275h
00276h
00277h
00278h
00279h
0027Ah
0027Bh
0027Ch
0027Dh
0027Eh
0027Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 23 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.9
SFR Information (9)
Address
Symbol
Register Name
After Reset
Remarks
00280h DTCTL
00281h
DTC Activation Control Register
00h
00282h
00283h
00284h
00285h
00286h
00287h
00288h DTCEN0
00289h DTCEN1
0028Ah DTCEN2
0028Bh DTCEN3
0028Ch
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
00h
00h
00h
00h
0028Dh DTCEN5
0028Eh DTCEN6
0028Fh
DTC Activation Enable Register 5
DTC Activation Enable Register 6
00h
00h
00290h CRCSAR
00291h
00292h CRCMR
00293h
00294h CRCD
00295h
00296h CRCIN
00297h
SFR Snoop Address Register
CRC Control Register
CRC Data Register
0000h
00h
0000h
00h
CRC Input Register
00298h
00299h
0029Ah
0029Bh
0029Ch
0029Dh
0029Eh
0029Fh
002A0h TRJ_0SR
002A1h
Timer RJ_0 Pin Select Register
08h
002A2h
002A3h
002A4h
002A5h TRCCLKSR
002A6h TRC_0SR0
002A7h TRC_0SR1
002A8h
Timer RCCLK Pin Select Register
Timer RC_0 Pin Select Register 0
Timer RC_0 Pin Select Register 1
00h
00h
00h
002A9h
002AAh
002ABh
002ACh
002ADh TIMSR
002AEh U_0SR
002AFh U_1SR
002B0h
Timer Pin Select Register
UART0_0 Pin Select Register
UART0_1 Pin Select Register
00h
00h
00h
002B1h
002B2h U2SR0
002B3h U2SR1
002B4h
UART2 Pin Select Register 0
UART2 Pin Select Register 1
00h
00h
002B5h
002B6h INTSR0
002B7h
002B8h
002B9h PINSR
002BAh
INT Interrupt Input Pin Select Register 0
I/O Function Pin Select Register
00h
00h
002BBh
002BCh
002BDh
002BEh PMCSEL
002BFh
Pin Assignment Select Register
00h
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 24 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.10
SFR Information (10)
Address
Symbol
Register Name
After Reset
Remarks
002C0h PUR0
002C1h PUR1
002C2h PUR2
002C3h
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
00h
00h
00h
002C4h
002C5h
002C6h
002C7h
002C8h P1DRR
002C9h P2DRR
002CAh
Port P1 Drive Capacity Control Register
Port P2 Drive Capacity Control Register
00h
00h
002CBh
002CCh DRR0
002CDh DRR1
002CEh DRR2
002CFh
Drive Capacity Control Register 0
Drive Capacity Control Register 1
Drive Capacity Control Register 2
00h
00h
00h
002D0h VLT0
002D1h VLT1
002D2h VLT2
002D3h
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
00h
00h
00h
002D4h
002D5h
002D6h
002D7h
002D8h
002D9h
002DAh
002DBh
002DCh
002DDh
002DEh
002DFh
002E0h PORT0
002E1h PORT1
002E2h PD0
002E3h PD1
002E4h PORT2
002E5h PORT3
002E6h PD2
002E7h PD3
002E8h PORT4
002E9h PORT5
002EAh PD4
002EBh PD5
002ECh PORT6
002EDh
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
002EEh PD6
002EFh
002F0h PORT8
002F1h
002F2h PD8
002F3h
Port P6 Direction Register
Port P8 Register
00h
XXh
00h
Port P8 Direction Register
002F4h
002F5h
002F6h
002F7h
002F8h
002F9h
002FAh
002FBh
002FCh
002FDh
002FEh
002FFh
00300h
to
003FFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 25 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.11
SFR Information (11)
Address
Symbol
Register Name
After Reset
Remarks
00400h On-chip RAM
to
On-chip RAM
053FFh
05400h
to
069FFh
06A00h ELSELR0
06A01h ELSELR1
06A02h ELSELR2
06A03h ELSELR3
06A04h ELSELR4
06A05h
Event Output Destination Select Register 0
Event Output Destination Select Register 1
Event Output Destination Select Register 2
Event Output Destination Select Register 3
Event Output Destination Select Register 4
00h
00h
00h
00h
00h
06A06h
06A07h
06A08h ELSELR8
06A09h ELSELR9
06A0Ah
Event Output Destination Select Register 8
Event Output Destination Select Register 9
00h
00h
06A0Bh ELSELR11
06A0Ch ELSELR12
06A0Dh ELSELR13
06A0Eh ELSELR14
06A0Fh ELSELR15
06A10h ELSELR16
06A11h
Event Output Destination Select Register 11
Event Output Destination Select Register 12
Event Output Destination Select Register 13
Event Output Destination Select Register 14
Event Output Destination Select Register 15
Event Output Destination Select Register 16
00h
00h
00h
00h
00h
00h
06A12h
06A13h
06A14h
06A15h
06A16h
06A17h
06A18h
06A19h
06A1Ah
06A1Bh
06A1Ch
06A1Dh
06A1Eh
06A1Fh
06A20h
06A21h
06A22h
06A23h
06A24h
06A25h
06A26h
06A27h
06A28h
06A29h
06A2Ah
06A2Bh
06A2Ch
06A2Dh
06A2Eh
06A2Fh
06A30h
06A31h
to
06AFFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 26 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.12
SFR Information (12)
Address
Symbol
Register Name
After Reset
Remarks
06B00h TSCUCR0
06B01h
06B02h TSCUCR1
06B03h
06B04h TSCUMR
06B05h
06B06h TSCUTCR0A
06B07h
06B08h TSCUTCR0B
06B09h
06B0Ah TSCUTCR1
06B0Bh
06B0Ch TSCUTCR2
06B0Dh
06B0Eh TSCUTCR3
06B0Fh
TSCU Control Register 0
TSCU Control Register 1
TSCU Mode Register
0000h
0000000000010000b
0000000010000000b
0000000001111111b
0000000001111111b
0000000000000001b
0000h
TSCU Timing Control Register 0A
TSCU Timing Control Register 0B
TSCU Timing Control Register 1
TSCU Timing Control Register 2
TSCU Timing Control Register 3
TSCU Channel Control Register
TSCU Flag Register
0000h
06B10h TSCUCHC
06B11h
06B12h TSCUFR
06B13h
0011111100000000b
0000h
06B14h TSCUSTC
06B15h
06B16h TSCUSCS
06B17h
06B18h TSCUSCC
06B19h
06B1Ah TSCUDBR
06B1Bh
TSCU Status Counter Register
TSCU Secondary Counter Set Register
TSCU Secondary Counter
0000h
0000000000100000b
0000000000100000b
0000h
TSCU Data Buffer Register
06B1Ch TSCUPRC
06B1Dh
TSCU Primary Counter
0000h
06B1Eh TSCURVR0
06B1Fh
06B20h TSCURVR1
06B21h
06B22h TSCURVR2
06B23h
06B24h TSCURVR3
06B25h
06B26h TSIE0
06B27h
06B28h TSIE1
06B29h
06B2Ah TSIE2
06B2Bh
06B2Ch TSCHSEL0
06B2Dh
TSCU Random Value Store Register 0
TSCU Random Value Store Register 1
TSCU Random Value Store Register 2
TSCU Random Value Store Register 3
TSCU Input Enable Register 0
TSCU Input Enable Register 1
TSCU Input Enable Register 2
TSCUCHXA Select Register 0
TSCUCHXA Select Register 1
TSCUCHXA Select Register 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
06B2Eh TSCHSEL1
06B2Fh
06B30h TSCHSEL2
06B31h
0000h
0000h
06B32h
to
06BFFh
06C00h
06C01h
06C02h
06C03h
Area for storing DTC transfer vector 0
Area for storing DTC transfer vector 1
Area for storing DTC transfer vector 2
Area for storing DTC transfer vector 3
Area for storing DTC transfer vector 4
XXh
XXh
XXh
XXh
XXh
06C04h
06C05h
06C06h
06C07h
06C08h
06C09h
Area for storing DTC transfer vector 8
Area for storing DTC transfer vector 9
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 27 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.13
SFR Information (13)
Address
06C0Ah
06C0Bh
06C0Ch
06C0Dh
06C0Eh
06C0Fh
06C10h
06C11h
Symbol
Register Name
After Reset
Remarks
Area for storing DTC transfer vector 10
Area for storing DTC transfer vector 11
Area for storing DTC transfer vector 12
Area for storing DTC transfer vector 13
Area for storing DTC transfer vector 14
Area for storing DTC transfer vector 15
Area for storing DTC transfer vector 16
Area for storing DTC transfer vector 17
Area for storing DTC transfer vector 18
Area for storing DTC transfer vector 19
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
06C12h
06C13h
06C14h
06C15h
06C16h
06C17h
06C18h
06C19h
Area for storing DTC transfer vector 22
Area for storing DTC transfer vector 23
Area for storing DTC transfer vector 24
Area for storing DTC transfer vector 25
XXh
XXh
XXh
XXh
06C1Ah
06C1Bh
06C1Ch
06C1Dh
06C1Eh
06C1Fh
06C20h
06C21h
06C22h
06C23h
06C24h
06C25h
06C26h
06C27h
06C28h
06C29h
06C2Ah
06C2Bh
06C2Ch
06C2Dh
06C2Eh
06C2Fh
06C30h
06C31h
Area for storing DTC transfer vector 42
XXh
XXh
Area for storing DTC transfer vector 49
06C32h
06C33h
06C34h
06C35h
06C36h
Area for storing DTC transfer vector 51
Area for storing DTC transfer vector 52
Area for storing DTC transfer vector 53
Area for storing DTC transfer vector 54
XXh
XXh
XXh
XXh
06C37h
06C38h
06C39h
06C3Ah
06C3Bh
06C3Ch
06C3Dh
06C3Eh
06C3Fh
06C40h DTCCR0
06C41h DTBLS0
06C42h DTCCT0
06C43h DTRLD0
06C44h DTSAR0
06C45h
DTC Control Register 0
DTC Block Size Register 0
DTC Transfer Count Register 0
DTC Transfer Count Reload Register 0
DTC Source Address Register 0
XXh
XXh
XXh
XXh
XXXXh
06C46h DTDAR0
06C47h
DTC Destination Address Register 0
XXXXh
06C48h DTCCR1
06C49h DTBLS1
X: Undefined
Note:
DTC Control Register 1
DTC Block Size Register 1
XXh
XXh
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 28 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.14
SFR Information (14)
Address
Symbol
Register Name
After Reset
Remarks
06C4Ah DTCCT1
06C4Bh DTRLD1
06C4Ch DTSAR1
06C4Dh
DTC Transfer Count Register 1
DTC Transfer Count Reload Register 1
DTC Source Address Register 1
XXh
XXh
XXXXh
06C4Eh DTDAR1
06C4Fh
DTC Destination Address Register 1
XXXXh
06C50h DTCCR2
06C51h DTBLS2
06C52h DTCCT2
06C53h DTRLD2
06C54h DTSAR2
06C55h
DTC Control Register 2
DTC Block Size Register 2
DTC Transfer Count Register 2
DTC Transfer Count Reload Register 2
DTC Source Address Register 2
XXh
XXh
XXh
XXh
XXXXh
06C56h DTDAR2
06C57h
DTC Destination Address Register 2
XXXXh
06C58h DTCCR3
06C59h DTBLS3
06C5Ah DTCCT3
06C5Bh DTRLD3
06C5Ch DTSAR3
06C5Dh
DTC Control Register 3
DTC Block Size Register 3
DTC Transfer Count Register 3
DTC Transfer Count Reload Register 3
DTC Source Address Register 3
XXh
XXh
XXh
XXh
XXXXh
06C5Eh DTDAR3
06C5Fh
DTC Destination Address Register 3
XXXXh
06C60h DTCCR4
06C61h DTBLS4
06C62h DTCCT4
06C63h DTRLD4
06C64h DTSAR4
06C65h
DTC Control Register 4
DTC Block Size Register 4
DTC Transfer Count Register 4
DTC Transfer Count Reload Register 4
DTC Source Address Register 4
XXh
XXh
XXh
XXh
XXXXh
06C66h DTDAR4
06C67h
DTC Destination Address Register 4
XXXXh
06C68h DTCCR5
06C69h DTBLS5
06C6Ah DTCCT5
06C6Bh DTRLD5
06C6Ch DTSAR5
06C6Dh
DTC Control Register 5
DTC Block Size Register 5
DTC Transfer Count Register 5
DTC Transfer Count Reload Register 5
DTC Source Address Register 5
XXh
XXh
XXh
XXh
XXXXh
06C6Eh DTDAR5
06C6Fh
DTC Destination Address Register 5
XXXXh
06C70h DTCCR6
06C71h DTBLS6
06C72h DTCCT6
06C73h DTRLD6
06C74h DTSAR6
06C75h
DTC Control Register 6
DTC Block Size Register 6
DTC Transfer Count Register 6
DTC Transfer Count Reload Register 6
DTC Source Address Register 6
XXh
XXh
XXh
XXh
XXXXh
06C76h DTDAR6
06C77h
DTC Destination Address Register 6
XXXXh
06C78h DTCCR7
06C79h DTBLS7
06C7Ah DTCCT7
06C7Bh DTRLD7
06C7Ch DTSAR7
06C7Dh
DTC Control Register 7
DTC Block Size Register 7
DTC Transfer Count Register 7
DTC Transfer Count Reload Register 7
DTC Source Address Register 7
XXh
XXh
XXh
XXh
XXXXh
06C7Eh DTDAR7
06C7Fh
DTC Destination Address Register 7
XXXXh
06C80h DTCCR8
06C81h DTBLS8
06C82h DTCCT8
06C83h DTRLD8
06C84h DTSAR8
06C85h
DTC Control Register 8
DTC Block Size Register 8
DTC Transfer Count Register 8
DTC Transfer Count Reload Register 8
DTC Source Address Register 8
XXh
XXh
XXh
XXh
XXXXh
06C86h DTDAR8
06C87h
DTC Destination Address Register 8
XXXXh
06C88h DTCCR9
06C89h DTBLS9
06C8Ah DTCCT9
06C8Bh DTRLD9
06C8Ch DTSAR9
06C8Dh
DTC Control Register 9
DTC Block Size Register 9
DTC Transfer Count Register 9
DTC Transfer Count Reload Register 9
DTC Source Address Register 9
XXh
XXh
XXh
XXh
XXXXh
06C8Eh DTDAR9
06C8Fh
DTC Destination Address Register 9
XXXXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 29 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.15
SFR Information (15)
Address
Symbol
Register Name
After Reset
Remarks
06C90h DTCCR10
06C91h DTBLS10
06C92h DTCCT10
06C93h DTRLD10
06C94h DTSAR10
06C95h
DTC Control Register 10
DTC Block Size Register 10
DTC Transfer Count Register 10
DTC Transfer Count Reload Register 10
DTC Source Address Register 10
XXh
XXh
XXh
XXh
XXXXh
06C96h DTDAR10
06C97h
DTC Destination Address Register 10
XXXXh
06C98h DTCCR11
06C99h DTBLS11
06C9Ah DTCCT11
06C9Bh DTRLD11
06C9Ch DTSAR11
06C9Dh
DTC Control Register 11
DTC Block Size Register 11
DTC Transfer Count Register 11
DTC Transfer Count Reload Register 11
DTC Source Address Register 11
XXh
XXh
XXh
XXh
XXXXh
06C9Eh DTDAR11
06C9Fh
DTC Destination Address Register 11
XXXXh
06CA0h DTCCR12
06CA1h DTBLS12
06CA2h DTCCT12
06CA3h DTRLD12
06CA4h DTSAR12
06CA5h
DTC Control Register 12
DTC Block Size Register 12
DTC Transfer Count Register 12
DTC Transfer Count Reload Register 12
DTC Source Address Register 12
XXh
XXh
XXh
XXh
XXXXh
06CA6h DTDAR12
06CA7h
DTC Destination Address Register 12
XXXXh
06CA8h DTCCR13
06CA9h DTBLS13
06CAAh DTCCT13
06CABh DTRLD13
06CACh DTSAR13
06CADh
DTC Control Register 13
DTC Block Size Register 13
DTC Transfer Count Register 13
DTC Transfer Count Reload Register 13
DTC Source Address Register 13
XXh
XXh
XXh
XXh
XXXXh
06CAEh DTDAR13
06CAFh
DTC Destination Address Register 13
XXXXh
06CB0h DTCCR14
06CB1h DTBLS14
06CB2h DTCCT14
06CB3h DTRLD14
06CB4h DTSAR14
06CB5h
DTC Control Register 14
DTC Block Size Register 14
DTC Transfer Count Register 14
DTC Transfer Count Reload Register 14
DTC Source Address Register 14
XXh
XXh
XXh
XXh
XXXXh
06CB6h DTDAR14
06CB7h
DTC Destination Address Register 14
XXXXh
06CB8h DTCCR15
06CB9h DTBLS15
06CBAh DTCCT15
06CBBh DTRLD15
06CBCh DTSAR15
06CBDh
DTC Control Register 15
DTC Block Size Register 15
DTC Transfer Count Register 15
DTC Transfer Count Reload Register 15
DTC Source Address Register 15
XXh
XXh
XXh
XXh
XXXXh
06CBEh DTDAR15
06CBFh
DTC Destination Address Register 15
XXXXh
06CC0h DTCCR16
06CC1h DTBLS16
06CC2h DTCCT16
06CC3h DTRLD16
06CC4h DTSAR16
06CC5h
DTC Control Register 16
DTC Block Size Register 16
DTC Transfer Count Register 16
DTC Transfer Count Reload Register 16
DTC Source Address Register 16
XXh
XXh
XXh
XXh
XXXXh
06CC6h DTDAR16
06CC7h
DTC Destination Address Register 16
XXXXh
06CC8h DTCCR17
06CC9h DTBLS17
06CCAh DTCCT17
06CCBh DTRLD17
06CCCh DTSAR17
06CCDh
DTC Control Register 17
DTC Block Size Register 17
DTC Transfer Count Register 17
DTC Transfer Count Reload Register 17
DTC Source Address Register 17
XXh
XXh
XXh
XXh
XXXXh
06CCEh DTDAR17
06CCFh
DTC Destination Address Register 17
XXXXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 30 of 58
R8C/36T-A Group
3. Address Space
(1)
Table 3.16
SFR Information (16)
Address
Symbol
Register Name
After Reset
Remarks
06CD0h DTCCR18
06CD1h DTBLS18
06CD2h DTCCT18
06CD3h DTRLD18
06CD4h DTSAR18
06CD5h
DTC Control Register 18
DTC Block Size Register 18
DTC Transfer Count Register 18
DTC Transfer Count Reload Register 18
DTC Source Address Register 18
XXh
XXh
XXh
XXh
XXXXh
06CD6h DTDAR18
06CD7h
DTC Destination Address Register 18
XXXXh
06CD8h DTCCR19
06CD9h DTBLS19
06CDAh DTCCT19
06CDBh DTRLD19
06CDCh DTSAR19
06CDDh
DTC Control Register 19
DTC Block Size Register 19
DTC Transfer Count Register 19
DTC Transfer Count Reload Register 19
DTC Source Address Register 19
XXh
XXh
XXh
XXh
XXXXh
06CDEh DTDAR19
06CDFh
DTC Destination Address Register 19
XXXXh
06CE0h DTCCR20
06CE1h DTBLS20
06CE2h DTCCT20
06CE3h DTRLD20
06CE4h DTSAR20
06CE5h
DTC Control Register 20
DTC Block Size Register 20
DTC Transfer Count Register 20
DTC Transfer Count Reload Register 20
DTC Source Address Register 20
XXh
XXh
XXh
XXh
XXXXh
06CE6h DTDAR20
06CE7h
DTC Destination Address Register 20
XXXXh
06CE8h DTCCR21
06CE9h DTBLS21
06CEAh DTCCT21
06CEBh DTRLD21
06CECh DTSAR21
06CEDh
DTC Control Register 21
DTC Block Size Register 21
DTC Transfer Count Register 21
DTC Transfer Count Reload Register 21
DTC Source Address Register 21
XXh
XXh
XXh
XXh
XXXXh
06CEEh DTDAR21
06CEFh
DTC Destination Address Register 21
XXXXh
06CF0h DTCCR22
06CF1h DTBLS22
06CF2h DTCCT22
06CF3h DTRLD22
06CF4h DTSAR22
06CF5h
DTC Control Register 22
DTC Block Size Register 22
DTC Transfer Count Register 22
DTC Transfer Count Reload Register 22
DTC Source Address Register 22
XXh
XXh
XXh
XXh
XXXXh
06CF6h DTDAR22
06CF7h
DTC Destination Address Register 22
XXXXh
06CF8h DTCCR23
06CF9h DTBLS23
06CFAh DTCCT23
06CFBh DTRLD23
06CFCh DTSAR23
06CFDh
DTC Control Register 23
DTC Block Size Register 23
DTC Transfer Count Register 23
DTC Transfer Count Reload Register 23
DTC Source Address Register 23
XXh
XXh
XXh
XXh
XXXXh
06CFEh DTDAR23
06CFFh
DTC Destination Address Register 23
XXXXh
06D00h
to
06FFFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
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R8C/36T-A Group
3. Address Space
Table 3.17
ID code Area, Option Function Select Area
Address
Symbol
Area Name
After Reset
(Note 1)
Address size
:
0FFDBh OFS2
Option Function Select Register 2
:
0FFDFh ID1
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 1)
:
0FFE3h ID2
:
0FFEBh ID3
:
0FFEFh ID4
:
0FFF3h ID5
:
0FFF7h ID6
:
0FFFBh ID7
:
0FFFFh OFS
Option Function Select Register
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not perform any additional writes to the option function select area. Erasing the block including the option function select area sets the option
function select area to FFh.
2. The ID code area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not perform any
additional writes to the ID code area. Erasing the block including the ID code area sets the ID code area to FFh.
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R8C/36T-A Group
4. Electrical Characteristics
4. Electrical Characteristics
4.1
Absolute Maximum Ratings
Table 4.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated Value
Unit
V
Vcc/AVcc
Supply voltage
0.3 to 6.5
ICEVcc
VI
Input voltage
0.3 to Vcc + 0.3
0.3 to Vcc + 0.3
500
V
V
VO
Output voltage
Pd
Power dissipation
Operating ambient temperature
40°C Topr 85°C
mW
°C
Topr
20 to 85 (N version)/
40 to 85 (D version)
Tstg
Storage temperature
65 to 150
°C
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R8C/36T-A Group
4. Electrical Characteristics
4.2
Recommended Operating Conditions
Table 4.2
Recommended Operating Conditions (1)
(Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Standard
Symbol
Parameter
Conditions
Unit
Min.
1.8
―
0.8VCC
Typ.
―
0
Max.
5.5
―
VCC/AVCC Supply voltage
VSS/AVSS Supply voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
VIH
Input high
voltage
Other than CMOS input
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VCC
CMOS
input
Input level Input level
switching
function
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
0.5VCC
VCC
selection
0.35VCC
:
0.55VCC
VCC
0.65VCC
VCC
(I/O port)
Input level
0.65VCC
VCC
selection
:
0.7VCC
VCC
0.5VCC
0.8VCC
VCC
Input level
0.85VCC
VCC
selection
:
0.85VCC
VCC
0.7VCC
0.85VCC
1.2
0
VCC
External clock input (XOUT)
Other than CMOS input
VCC
VIL
Input low
voltage
0.2VCC
0.2VCC
0.2VCC
0.2VCC
0.4VCC
0.3VCC
0.2VCC
0.55VCC
0.45VCC
0.35VCC
0.4
CMOS
input
Input level Input level
switching
function
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
4.0 V VCC 5.5 V
2.7 V VCC 4.0 V
1.8 V VCC 2.7 V
0
0
0
0
0
0
0
0
selection
:
0.35VCC
(I/O port)
Input level
selection
:
0.5VCC
Input level
selection
:
0.7VCC
0
0
―
External clock input (XOUT)
IOH(sum)
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
Peak sum output high
current
Sum of all pins IOH(peak)
80
Average sum output high Sum of all pins IOH(avg)
current
―
―
40
mA
Peak output high current
When drive capacity is low
When drive capacity is high
When drive capacity is low
When drive capacity is high
Sum of all pins IOL(peak)
―
―
―
―
―
―
―
―
―
―
10
40
5
20
80
mA
mA
mA
mA
mA
Average output high
current
Peak sum output low
current
Average sum output low
current
Sum of all pins IOL(avg)
―
―
40
mA
Peak output low current
When drive capacity is low
When drive capacity is high
When drive capacity is low
When drive capacity is high
―
―
―
―
―
―
―
32
―
―
―
―
―
―
―
―
―
―
―
―
32.768
―
―
―
10
40
5
20
20
5
50
40
20
5
20
5
mA
mA
mA
Average output low
current
mA
XIN clock input oscillation frequency
2.7 V VCC 5.5 V
1.8 V VCC 2.7 V
1.8 V VCC 5.5 V
2.7 V VCC 5.5 V
2.7 V VCC 5.5 V
1.8 V VCC 2.7 V
2.7 V VCC 5.5 V
1.8 V VCC 2.7 V
2.7 V VCC 5.5 V
1.8 V VCC 2.7 V
MHz
MHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
f(XCIN)
XCIN clock input oscillation frequency
Count source for timer RC
fHOCO
fHOCO-F fHOCO-F frequency
—
System clock frequency
CPU clock frequency
―
―
―
―
f(BCLK)
20
5
Note:
1. The average output current indicates the average value of current measured during 100 ms.
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Page 34 of 58
R8C/36T-A Group
4. Electrical Characteristics
P0, P1, P2, P3
P4_2 to P4_7
P5_0 to P5_4
P5_6, P5_7
30 pF
P6, P8_0 to P8_6
Figure 4.1
Timing Measurement Circuit for Ports P0, P1, P2, P3, P4_2 to P4_7, P5_0 to P5_4,
P5_6, P5_7, P6, and P8_0 to P8_6
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R8C/36T-A Group
4. Electrical Characteristics
4.3
Peripheral Function Characteristics
Table 4.3
A/D Converter Characteristics
(Vcc/AVcc = Vref = 2.2 V to 5.5 V, Vss = 0 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version), unless otherwise specified)
Standard
Symbol
Parameter
Conditions
Unit
Min.
―
―
―
―
―
―
―
―
―
2
Typ.
―
―
―
―
―
―
―
―
―
―
―
―
―
3
Max.
10
±3
―
Resolution
Vref = AVcc
Bit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MHz
MHz
MHz
MHz
kΩ
―
Absolute
accuracy
10-bit mode
Vref = AVcc = 5.0 V AN0 to AN11 input
Vref = AVcc = 3.3 V AN0 to AN11 input
Vref = AVcc = 3.0 V AN0 to AN11 input
Vref = AVcc = 2.2 V AN0 to AN11 input
Vref = AVcc = 5.0 V AN0 to AN11 input
Vref = AVcc = 3.3 V AN0 to AN11 input
Vref = AVcc = 3.0 V AN0 to AN11 input
Vref = AVcc = 2.2 V AN0 to AN11 input
4.0 V Vref = AVcc 5.5 V (1)
±5
±5
±5
8-bit mode
±2
±2
±2
±2
AD
A/D conversion clock
20
16
10
5
3.2 V Vref = AVcc 5.5 V (1)
2.7 V Vref = AVcc 5.5 V (1)
2.2 V Vref = AVcc 5.5 V (1)
2
2
2
―
Tolerance level impedance
Vref current
―
―
2.2
2.2
0.8
2.2
0
―
Ivref
tCONV
Vcc = 5 V, XIN = f1 = fAD = 20 MHz
Vref = AVcc = 5.0 V, AD = 20 MHz
Vref = AVcc = 5.0 V, AD = 20 MHz
AD = 20 MHz
45
―
―
―
―
―
1.34
―
μA
Conversion time
10-bit mode
8-bit mode
―
μs
―
μs
tSAMP
Vref
Sampling time
―
μs
Reference voltage
Analog input voltage (2)
AVcc
Vref
1.49
V
VIA
V
OCVREF On-chip reference voltage
2MHz AD 4MHz
1.19
V
Notes:
1. If the CPU and the flash memory stop, the A/D conversion result will be undefined.
2. When the analog input voltage exceeds the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh
in 8-bit mode.
Table 4.4
Comparator B Characteristics
(Vcc/AVcc = 2.2 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Standard
Symbol
Parameter
Conditions
Unit
V
Min.
0
Typ.
Max.
Vref
IVREF1, IVREF3 input reference
voltage
―
Vcc 1.4
VI
IVCMP1, IVCMP3 input voltage
Offset
Comparator output delay time (1)
Comparator operating current
0.3
―
5
Vcc
+
0.3
V
―
―
―
―
100
―
mV
μs
td
VI = Vref ±100 mV
Vcc = 5.0 V
0.1
17.5
ICMP
―
μA
Note:
1. When the digital filter is not selected.
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Page 36 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.5
Flash Memory (Program ROM) Characteristics
(Vcc = 2.7 V to 5.5 V, Topr =20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Standard
Symbol
Parameter
Conditions
Unit
Min.
1,000 (2)
―
Typ.
―
Max.
―
Program/erase endurance (1)
―
―
times
Byte program time
―
―
μs
(Program and erase endurance 100
times)
―
―
―
―
―
Byte program time
(Program and erase endurance 1,000
times)
―
―
―
―
―
―
200
400
650
4
μs
μs
μs
μs
Word program time
(Program and erase endurance 100
times)
Topr = 25°C,
VCC = 5.0 V
100
100
100
Word program time
(Program and erase endurance 100
times)
Word program time
(Program and erase endurance 1,000
times)
Block erase time
―
―
0.3
s
td(SR-SUS) Time delay from suspend request until
suspend
―
5 + CPU clock
× 3 cycles
ms
―
Interval from erase start/restart until
following suspend request
0
―
―
―
―
μs
μs
μs
―
Time from suspend until erase restart
―
―
30 + CPU clock
× 1 cycle
td(CMDRST Time from when command is forcibly
-READY)
30 + CPU clock
× 1 cycle
terminated until reading is enabled
―
―
―
Program, erase voltage
Read voltage
2.7
1.8
―
―
―
5.5
5.5
85
V
V
Program, erase temperature
20 (N ver.)
40 (D ver.)
°C
Data hold time (6)
―
Ambient temperature
= 55°C (7)
20
―
―
year
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-
byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C.
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Page 37 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.6
Flash Memory (Data flash Block A to Block D) Characteristics
(Vcc = 2.7 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Standard
Symbol
Parameter
Conditions
Unit
Min.
10,000 (2)
―
Typ.
―
Max.
―
Program/erase endurance (1)
―
―
times
Byte program time
160
950
μs
(Program and erase endurance 1,000
times)
―
―
―
Byte program time
(Program and erase endurance > 1,000
times)
―
―
―
300
0.2
0.3
950
1
μs
s
Block erase time
(Program and erase endurance 1,000
times)
Block erase time
1
s
(Program and erase endurance > 1,000
times)
td(SR-SUS) Time delay from suspend request until
suspend
―
0
―
―
―
―
3 + CPU clock
× 3 cycles
ms
μs
μs
μs
―
Interval from erase start/restart until
following suspend request
―
―
Time from suspend until erase restart
―
―
30 + CPU clock
× 1 cycle
td(CMDRST Time from when command is forcibly
30 + CPU clock
× 1 cycle
-READY)
terminated until reading is enabled
―
―
―
Program, erase voltage
Read voltage
2.7
1.8
―
―
―
5.5
5.5
85
V
V
Program, erase temperature
20 (N ver.)
40 (D ver.)
°C
Data hold time (6)
―
Ambient temperature
= 55°C (7)
20
―
―
year
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100, 1,000 or 10,000), each block can be erased n times. For example, if
1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C.
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R8C/36T-A Group
4. Electrical Characteristics
Suspend request
(FMR21 bit)
FST6 bit
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
FST6: Bit in FST register
FMR21: Bit in FMR2 register
Figure 4.2
Table 4.7
Time Delay from Suspend Request until Suspend
Voltage Detection 0 Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
1.80
2.15
2.70
3.55
―
Typ.
1.90
2.35
2.85
3.80
6
Max.
2.05
2.55
3.05
4.05
150
Voltage detection level Vdet0_0 (1)
Voltage detection level Vdet0_1 (1)
Voltage detection level Vdet0_2 (1)
Voltage detection level Vdet0_3 (1)
Voltage detection 0 circuit response time (2)
Vdet0
When Vcc falls
V
V
When Vcc falls
When Vcc falls
When Vcc falls
V
V
―
At the falling of Vcc from 5 V
μs
to (Vdet0 0.1) V
―
Voltage detection circuit self power
consumption
VCA25 = 1, Vcc = 5.0 V
―
―
1.5
―
μA
μs
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
―
100
Notes:
1. The voltage detection level must be selected with bits VDSEL0 and VDSEL1 in the OFS register.
2. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
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R8C/36T-A Group
4. Electrical Characteristics
Table 4.8
Voltage Detection 1 Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
2.00
2.15
2.30
2.45
2.60
2.75
2.80
2.95
3.10
3.25
3.40
3.55
3.70
3.85
4.00
4.15
―
Typ.
2.20
2.35
2.50
2.65
2.80
2.95
3.10
3.25
3.40
3.55
3.70
3.85
4.00
4.15
4.30
4.45
0.07
Max.
2.40
2.55
2.70
2.85
3.00
3.15
3.40
3.55
3.70
3.85
4.00
4.15
4.30
4.45
4.60
4.75
―
Voltage detection level Vdet1_0 (1)
Voltage detection level Vdet1_1 (1)
Voltage detection level Vdet1_2 (1)
Voltage detection level Vdet1_3 (1)
Voltage detection level Vdet1_4 (1)
Voltage detection level Vdet1_5 (1)
Voltage detection level Vdet1_6 (1)
Voltage detection level Vdet1_7 (1)
Voltage detection level Vdet1_8 (1)
Voltage detection level Vdet1_9 (1)
Voltage detection level Vdet1_A (1)
Voltage detection level Vdet1_B (1)
Voltage detection level Vdet1_C (1)
Voltage detection level Vdet1_D (1)
Voltage detection level Vdet1_E (1)
Voltage detection level Vdet1_F (1)
Vdet1
When Vcc falls
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
When Vcc falls
―
Hysteresis width at the rising of Vcc in
voltage detection 1 circuit
Vdet1_0 to Vdet1_5
selected
Vdet1_6 to Vdet1_F
selected
―
―
―
―
0.10
60
―
150
―
V
Voltage detection 1 circuit response time (2)
―
At the falling of Vcc from 5 V
to (Vdet1 0.1) V
VCA26 = 1, Vcc = 5.0 V
μs
μA
μs
―
Voltage detection circuit self power
consumption
1.7
―
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
100
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 4.9
Voltage Detection 2 Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
When Vcc falls
Unit
Min.
3.70
―
Typ.
4.00
0.1
Max.
4.30
―
Vdet2
Voltage detection level Vdet2_0
V
―
Hysteresis width at the rising of Vcc in
voltage detection 2 circuit
μs
Voltage detection 2 circuit response time (1)
―
At the falling of Vcc from 5 V
to (Vdet2_0 0.1) V
VCA27 = 1, Vcc = 5.0 V
―
―
―
20
1.7
―
150
―
μs
μA
μs
―
Voltage detection circuit self power
consumption
td(E-A)
Waiting time until voltage detection circuit
operation starts (2)
100
Notes:
1. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
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R8C/36T-A Group
4. Electrical Characteristics
(1)
Table 4.10
Power-On Reset Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
0
Typ.
Max.
50,000 mV/msec
trth
External power VCC rise gradient
―
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
(1)
(1)
Vdet0
Vdet0
trth
trth
External
Power VCC
0.5 V
(2)
Voltage detection 0
circuit response time
tw(por)
Internal
reset signal
1
1
32
32
fOCO-S
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to the Voltage Detection
Circuit chapter of User’s Manual: Hardware for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 4.3
Power-on Reset Circuit Characteristics
Table 4.11
High-Speed On-Chip Oscillator Circuit Characteristics
Standard
Typ.
Symbol
Parameter
Conditions
Unit
Min.
Max.
―
High-speed on-chip oscillator frequency Vcc = 1.8 V to 5.5 V,
―
40
―
MHz
after reset
20°C Topr 85°C
(N version)
40°C Topr 85°C
(D version)
High-speed on-chip oscillator frequency
when 01b or 10b is written to bits
FRA25 and FRA24 in the FRA2 register
—
36.864
—
MHz
(1)
High-speed on-chip oscillator frequency
when 10b is written to bits FRA25 and
FRA24 in the FRA2 register
—
32
—
MHz
%
High-speed on-chip oscillator frequency
dependence on temperature and power
supply voltage (2)
1.5
―
1.5
―
Oscillation stability time
Vcc = 5.0 V, Topr = 25°C
Vcc = 5.0 V, Topr = 25°C
―
―
250
500
―
―
μs
―
Self power consumption at oscillation
μA
Notes:
1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 41 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.12
Low-Speed On-Chip Oscillator Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
60
Typ.
125
30
Max.
250
100
―
fLOCO
―
Low-speed on-chip oscillator frequency
Oscillation stability time
kHz
μs
Vcc = 5.0 V, Topr = 25°C
Vcc = 5.0 V, Topr = 25°C
―
―
Self power consumption at oscillation
―
3
μA
Table 4.13
Power Supply Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
td(P-R)
Time for internal power supply
stabilization during power-on (1)
―
―
2,000
μs
Note:
1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 42 of 58
R8C/36T-A Group
4. Electrical Characteristics
4.4
DC Characteristics
Table 4.14
DC Characteristics (1) [4.2 V Vcc 5.5 V]
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
VOH
Parameter
Conditions
IOH = 20 mA
Unit
V
Min.
Typ. Max.
Output high Other than XOUT
voltage
Drive capacity is
high
Vcc 2.0
―
Vcc
Drive capacity is low IOH = 5 mA
IOH = 200 A
Vcc 2.0
Vcc 0.3
1.0
—
—
—
―
Vcc
Vcc
Vcc
2.0
V
V
V
V
XOUT
IOH = 200 A
VOL
Output low Other than XOUT
voltage
Drive capacity is
high
IOL= 20 mA
―
Drive capacity is low IOL = 5 mA
IOL = 200 A
—
—
—
—
2.0
0.45
0.5
―
V
V
V
V
XOUT
IOL = 200 A
—
—
VT+-VT-
Hysteresis
0.1
1.2
INT0 to INT4, KI0 to KI3,
TRJIO_0, TRCCLK_0,
TRCTRG_0, TRCIOA_0,
TRCIOB_0, TRCIOC_0,
TRCIOD_0,
CLK_0, CLK_1,
RXD_0, RXD_1, CTS2,
SCL2, SDA2, CLK2, RXD2,
SCL_0, SDA_0, SSI_0,
SCS_0, SSCK_0, SSO_0
Vcc = 5.0 V
0.1
1.2
―
V
RESET
IIH
IIL
Input high current
Input low current
VI = 5.0 V
VI = 0 V
VI = 0 V
―
―
25
―
―
―
1.0
1.0
100
―
μA
μA
RPULLUP Pull-up resistance
50
0.3
kΩ
RfXIN
Feedback
resistance
XIN
MΩ
RfXCIN
VRAM
Feedback
resistance
XCIN
―
8
―
―
MΩ
RAM hold voltage
During stop mode
1.8
―
V
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 43 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.15
DC Characteristics (2) [3.3 V Vcc 5.5 V]
(Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise
specified)
Standard (4)
Conditions
Oscillation
On-Chip Oscillator
Low-Power-
CPU Clock Consumption
Setting
Symbol Parameter
Unit
mA
Other
Min. Typ. Max.
High-
Low-
XIN (2)
XCIN
Speed
Speed
ICC
Power
High-
speed
clock
mode
20 MHz
16 MHz
10 MHz
20 MHz
16 MHz
10 MHz
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
125 kHz No division
125 kHz No division
125 kHz No division
125 kHz Divide-by-8
125 kHz Divide-by-8
125 kHz Divide-by-8
125 kHz No division
125 kHz Divide-by-8
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
6.5
15
supply
current (1)
5.3 12.5 mA
Off
3.6
3.0
2.2
1.5
7.0
3.0
1
―
―
―
―
15
―
―
mA
mA
mA
mA
mA
mA
mA
Off
Off
Off
20 MHz (3)
20 MHz (3)
4 MHz (3)
High-
speed on-
chip
oscillator
mode
Off
Off
125 kHz Divide-by-16 MSTIIC = 1
MSTTRC = 1
Low-
speed on-
chip
Off
Off
Off
125 kHz Divide-by-8 FMR27 = 1
SVC0 = 0
―
90 400 μA
oscillator
mode
Low-
Off
Off
Off
32 kHz
32 kHz
Off
Off
Off
Off
Off
Off
―
―
―
FMR27 = 1
SVC0 = 0
―
―
―
85 400 μA
47 μA
15 100 μA
speed
clock
mode
FMSTP = 1
SVC0 = 0
Program operation on RAM
Flash memory off
―
Wait
mode
125 kHz
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock operation
Off
Off
Off
Off
Off
32 kHz
Off
Off
Off
Off
Off
125 kHz
Off
―
―
―
―
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
―
―
―
―
4
90
μA
μA
μA
μA
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
3.5
―
Stop
mode
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 25°C
Peripheral clock off
2.2 6.0
Off
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 85°C
Peripheral clock off
30
―
Notes:
1. Vcc = 3.3 V to 5.5 V, single-chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. fHOCO-F
4. The typical value (Typ.) indicates the current value when the CPU and the memory operate.
The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and
the flash memory is programmed/erased.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 44 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.16
DC Characteristics (3) [2.7 V Vcc 4.2 V]
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
IOH = 5 mA
Unit
V
Min.
Typ. Max.
VOH
Output high Other than XOUT
voltage
Drive capacity is
high
Vcc 0.5
―
Vcc
Drive capacity is low IOH = 1 mA
IOH = 200 A
Vcc 0.5
1.0
—
—
―
Vcc
Vcc
0.5
V
V
V
XOUT
VOL
Output low Other than XOUT
voltage
Drive capacity is
high
IOL = 5 mA
―
Drive capacity is low IOL = 1 mA
—
—
—
—
0.5
0.5
―
V
V
V
XOUT
IOL = 200 A
VT+-VT-
Hysteresis
0.1
0.4
INT0 to INT4, KI0 to KI3,
TRJIO_0, TRCCLK_0,
TRCTRG_0, TRCIOA_0,
TRCIOB_0, TRCIOC_0,
TRCIOD_0,
CLK_0, CLK_1,
RXD_0, RXD_1, CTS2,
SCL2, SDA2, CLK2, RXD2,
SCL_0, SDA_0, SSI_0,
SCS_0, SSCK_0, SSO_0
Vcc = 3.0 V
0.1
0.5
―
V
RESET
IIH
IIL
Input high current
Input low current
VI = 3.0 V
VI = 0 V
VI = 0 V
―
―
42
―
―
―
1.0
1.0
168
―
μA
μA
RPULLUP Pull-up resistance
84
0.3
kΩ
RfXIN
Feedback
resistance
XIN
MΩ
RfXCIN
VRAM
Feedback
resistance
XCIN
―
8
―
―
MΩ
RAM hold voltage
During stop mode
1.8
―
V
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 45 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.17
DC Characteristics (4) [2.7 V Vcc 3.3 V]
(Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise
specified))
Standard (4)
Conditions
Oscillation
On-Chip Oscillator
Low-Power-
CPU Clock Consumption
Setting
Symbol Parameter
Unit
mA
Other
Min. Typ. Max.
High-
Low-
XIN (2)
XCIN
Speed
Speed
ICC
Power
High-
speed
clock
mode
10 MHz
10 MHz
Off
Off
Off
Off
125 kHz No division
125 kHz Divide-by-8
―
―
―
―
3.5
10
supply
current (1)
1.5 7.5 mA
20 MHz (3)
20 MHz (3)
10 MHz (3)
10 MHz (3)
4 MHz (3)
High-
speed on-
chip
oscillator
mode
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
125 kHz No division
125 kHz Divide-by-8
125 kHz No division
125 kHz Divide-by-8
―
―
―
―
―
―
―
―
―
7.0
3.0
4.0
1.5
1
15
―
―
―
―
mA
mA
mA
mA
mA
125 kHz Divide-by-16 MSTIIC = 1
MSTTRC = 1
Low-
speed on-
chip
Off
Off
Off
125 kHz Divide-by-8 FMR27 = 1
SVC0 = 0
―
90 390 μA
oscillator
mode
Low-
Off
Off
Off
32 kHz
32 kHz
Off
Off
Off
Off
Off
Off
No division FMR27 = 1
SVC0 = 0
―
―
―
80 400 μA
speed
clock
mode
No division FMSTP = 1
SVC0 = 0
Program operation on RAM
Flash memory off
40
15
―
μA
μA
Wait
mode
125 kHz
―
―
―
―
―
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock operation
90
Off
Off
Off
Off
Off
32 kHz
Off
Off
Off
Off
Off
125 kHz
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
―
―
―
―
4
80
μA
μA
μA
μA
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
3.5
―
Stop
mode
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 25°C
Peripheral clock off
2.2 6.0
Off
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 85°C
Peripheral clock off
30
―
Notes:
1. Vcc = 2.7 V to 3.3 V, single-chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. fHOCO-F
4. The typical value (Typ.) indicates the current value when the CPU and the memory operate.
The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and
the flash memory is programmed/erased.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 46 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.18
DC Characteristics (5) [1.8 V Vcc 2.7 V]
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
IOH = 2 mA
Unit
V
Min.
Typ. Max.
VOH
Output high Other than XOUT
voltage
Drive capacity is
high
Vcc 0.5
―
Vcc
Drive capacity is low IOH = 1 mA
IOH = 200 A
Vcc 0.5
1.0
—
—
―
Vcc
Vcc
0.5
V
V
V
XOUT
VOL
Output low Other than XOUT
voltage
Drive capacity is
high
IOL = 2 mA
―
Drive capacity is low IOL = 1 mA
—
—
—
—
0.5
0.5
―
V
V
V
XOUT
IOL = 200 A
VT+-VT-
Hysteresis
0.05
0.2
INT0 to INT4, KI0 to KI3,
TRJIO_0, TRCCLK_0,
TRCTRG_0, TRCIOA_0,
TRCIOB_0, TRCIOC_0,
TRCIOD_0,
CLK_0, CLK_1,
RXD_0, RXD_1,CTS2,
SCL2, SDA2, CLK2, RXD2,
SCL_0, SDA_0,SSI_0,
SCS_0, SSCK_0,SSO_0
VCC = 2.2 V
0.05
0.2
―
V
RESET
IIH
IIL
Input high current
Input low current
VI = 2.2 V
VI = 0 V
VI = 0 V
―
―
―
―
1.0
1.0
400
―
μA
μA
RPULLUP Pull-up resistance
100
―
200
0.3
kΩ
RfXIN
Feedback
resistance
XIN
MΩ
RfXCIN
VRAM
Feedback
resistance
XCIN
―
8
―
―
MΩ
RAM hold voltage
During stop mode
1.8
―
V
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 47 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.19
DC Characteristics (6) [1.8 V Vcc 2.7 V]
(Topr = 20°C to 85°C (N version)/40°C to 85°C (D version), unless otherwise
specified)
Standard (4)
Conditions
Oscillation
On-Chip Oscillator
Low-Power-
CPU Clock Consumption
Setting
Symbol Parameter
Unit
Other
Min. Typ. Max.
High-
Low-
XIN (2)
XCIN
Speed
Speed
ICC
Power
supply
current (1)
High-
speed
clock
mode
5 MHz
5 MHz
Off
Off
Off
Off
125 kHz No division
125 kHz Divide-by-8
―
―
―
―
2.2
0.8
―
―
mA
mA
5 MHz (3)
5 MHz (3)
4 MHz (3)
High-
speed on-
chip
oscillator
mode
Off
Off
Off
Off
Off
Off
125 kHz No division
125 kHz Divide-by-8
―
―
―
―
―
2.5
1.7
1
10
―
―
mA
mA
mA
125 kHz Divide-by-16 MSTIIC = 1
MSTTRC = 1
Low-
speed on-
chip
Off
Off
Off
125 kHz Divide-by-8 FMR27 = 1
SVC0 = 0
―
90 300 μA
oscillator
mode
Low-
Off
Off
Off
Off
Off
Off
32 kHz
Off
Off
Off
Off
Off
Off
Off
Off
125 kHz
125 kHz
Off
No division FMR27 = 1
SVC0 = 0
―
―
―
―
―
―
80 350 μA
speed
clock
mode
Wait
mode
―
―
―
―
―
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock operation
15
4
90
80
―
6
μA
μA
μA
μA
μA
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
32 kHz
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
SVC0 = 1
While a WAIT instruction is executed
Peripheral clock off
3.5
2.2
30
Stop
mode
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 25°C
Peripheral clock off
Off
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Topr = 85°C
Peripheral clock off
―
Notes:
1. Vcc = 1.8 V to 2.7 V, single-chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. fHOCO-F
4. The typical value (Typ.) indicates the current value when the CPU and the memory operate.
The maximum value (Max.) indicates the current value when the CPU, the memory, and the peripheral functions operate and
the flash memory is programmed/erased.
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 48 of 58
R8C/36T-A Group
4. Electrical Characteristics
4.5
AC Characteristics
Table 4.20
Timing Requirements of Clock Synchronous Serial I/O with Chip Select
(during Master Operation)
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
Typ.
―
―
―
―
―
―
―
―
―
―
―
―
―
Max.
―
(1)
tSUCYC
tHI
SSCK clock cycle time
SSCK clock high width
SSCK clock low width
SSCK clock rising time
4.00
tCYC
0.40
0.60
0.60
0.50
1.00
0.50
1.00
―
tSUCYC
tSUCYC
tLO
0.40
(1)
tRISE
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
4.5 V Vcc 5.5 V
2.7 V Vcc 4.5 V
1.8 V Vcc 2.7 V
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
―
tCYC
(1)
―
tCYC
(1)
tFALL
tSU
SSCK clock falling time
―
tCYC
(1)
―
tCYC
SSI, SSO data input setup time
60
ns
ns
ns
70
―
100
2.00
―
(1)
tH
SSI, SSO data input hold time
SCS-SCK output delay time
―
tCYC
(1)
2.00
―
tCYC
tLEAD
tLAG
tOD
0.5 tSUCYC - 1 tCYC
―
ns
ns
ns
0.5 tSUCYC - 1 tCYC
―
―
SCK -SCS output valid time
SSO data output delay time
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
―
―
―
―
30.00
1.00
(1)
tCYC
Note:
1. 1tCYC = 1/f1 (s)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 49 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.21
Timing Requirements of Clock Synchronous Serial I/O with Chip Select
(during Slave Operation)
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Standard
Symbol
Parameter
Conditions
Unit
Min.
4.00
Typ.
―
―
―
―
―
―
―
―
Max.
―
(1)
tSUCYC
SSCK clock cycle time
SSCK clock high width
tCYC
tHI
0.40
0.60
0.60
1.00
1.00
―
tSUCYC
tSUCYC
μs
tLO
SSCK clock low width
SSCK clock rising time
SSCK clock falling time
SSO data input setup time
SSO data input hold time
0.40
tRISE
tFALL
tSU
―
―
μs
10.00
2.00
ns
(1)
tH
―
tCYC
tLEAD
1tCYC + 50
―
ns
ns
SCS setup time
tLAG
tOD
1tCYC + 50
―
―
SCS hold time
SSI, SSO data output delay time
4.5 V Vcc 5.5 V
2.7 V Vcc 4.5 V
1.8 V Vcc 2.7 V
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
2.7 V Vcc 5.5 V
1.8 V Vcc 2.7 V
―
―
―
―
―
―
―
―
―
―
―
―
―
―
60
ns
ns
ns
ns
ns
ns
ns
70
100.00
tSA
tOR
SSI slave access time
SSI slave out open time
1.5tCYC + 100
1.5tCYC + 200
1.5tCYC + 100
1.5tCYC + 200
Note:
1. 1tCYC = 1/f1 (s)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 50 of 58
R8C/36T-A Group
4. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tLEAD
tLAG
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
CPHS, CPOS: Bits in SIMR1 register
Figure 4.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
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R8C/36T-A Group
4. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIL or VOL
SCS (input)
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
SSI (output)
tSU
tH
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SIMR1 register
Figure 4.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 52 of 58
R8C/36T-A Group
4. Electrical Characteristics
tHI
VIH or VOH
VIL or VOL
SSCK
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 4.6
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 53 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.22
External Clock Input (XOUT, XCIN)
Standard
Symbol
Parameter
Vcc = 2.2 V, Topr = 25°C
Vcc = 3 V, Topr = 25°C
Vcc = 5 V, Topr = 25°C
Unit
Min.
200
90
90
14
7
Max.
―
Min.
50
24
24
14
7
Max.
―
Min.
50
24
24
14
7
Max.
―
tc(XOUT)
XOUT input cycle time
ns
ns
ns
μs
μs
μs
tWH(XOUT) XOUT input high width
tWL(XOUT) XOUT input low width
―
―
―
―
―
―
tc(XCIN)
XCIN input cycle time
XCIN input high width
XCIN input low width
―
―
―
tWH(XCIN)
tWL(XCIN)
―
―
―
7
―
7
―
7
―
tC(XOUT), tC(XCIN)
tWH(XOUT),
tWH(XCIN)
External
Clock Input
tWL(XOUT), tWL(XCIN)
Figure 4.7
External Clock Input Timing Diagram
Timing Requirements of TRJIO
Table 4.23
Standard
Vcc = 3 V, Topr = 25°C
Symbol
Parameter
Vcc = 2.2 V, Topr = 25°C
Vcc = 5 V, Topr = 25°C
Unit
Min.
500
200
200
Max.
―
Min.
300
120
120
Max.
―
Min.
100
40
Max.
―
tc(TRJIO)
TRJIO input cycle time
ns
ns
ns
tWH(TRJIO) TRJIO input high width
tWL(TRJIO) TRJIO input low width
―
―
―
―
―
40
―
tC(TRJIO)
tWH(TRJIO)
TRJIO input
tWL(TRJIO)
Figure 4.8
Input Timing of TRJIO
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 54 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.24
Timing Requirements of Serial Interface
(Internal clock selected as transfer clock (master communication))
Standard
Symbol
Parameter
Vcc = 2.2 V, Topr = 25°C
Vcc = 3 V, Topr = 25°C
Vcc = 5 V, Topr = 25°C
Unit
Min.
―
Max.
200
―
Min.
―
Max.
30
Min.
―
Max.
10
td(C-Q)
tsu(D-C)
th(C-D)
TXDi output delay time
ns
ns
ns
(1)
150
90
120
90
―
90
90
―
RXDi input setup time
RXDi input hold time
―
―
―
i = 0 or 1
Note:
1. External pin load condition CL = 30 pF
Table 4.25
Timing Requirements of Serial Interface
(External clock selected as transfer clock (slave communication))
Standard
Symbol
Parameter
Vcc = 2.2 V, Topr = 25°C
Vcc = 3 V, Topr = 25°C
Vcc = 5 V, Topr = 25°C
Unit
Min.
800
400
400
―
Max.
―
Min.
300
150
150
―
Max.
―
Min.
200
100
100
―
Max.
―
tc(CK)
CLKi input cycle time
CLKi input high width
CLKi input low width
TXDi output delay time
RXDi input setup time
RXDi input hold time
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
tsu(D-C)
th(C-D)
―
―
―
―
―
―
200
―
120
―
90
―
150
90
30
10
―
90
―
90
―
i = 0 or 1
tC(CK)
tW(CKH)
CLKi
TXDi
tW(CKL)
th(C-Q)
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 4.9
Input and Output Timing of Serial Interface (i = 0 or 1)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 55 of 58
R8C/36T-A Group
4. Electrical Characteristics
Table 4.26
Timing Requirements of External Interrupt INTi (i = 0 to 4) and Key Input Interrupt KIj
(j = 0 to 3)
Standard
Symbol
Parameter
Vcc = 2.2 V, Topr = 25°C
Vcc = 3 V, Topr = 25°C
Vcc = 5 V, Topr = 25°C
Unit
Min.
Max.
Min.
Max.
Min.
Max.
(1)
(1)
(1)
tW(INH)
INTi input high width,
KIj input high width
―
―
―
ns
ns
1000
380
250
(2)
(2)
(2)
tW(INL)
INTi input low width,
KIj input low width
―
―
―
1000
380
250
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input high pulse width of either (1/digital filter
sampling frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input low pulse width of either (1/digital filter
sampling frequency × 3) or the minimum value of standard, whichever is greater.
tW(INL)
INTi input
tW(INH)
KIj input
Figure 4.10
Input Timing of External Interrupt INTi and Key Input Interrupt KIj (i = 0 to 4; j = 0 to 3)
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 56 of 58
R8C/36T-A Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
MASS[Typ.]
0.3g
64P6Q-A / FP-64K / FP-64KV
HD
D
*1
48
33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1
10.0 10.1
1.4
9.9
9.9
64
17
Terminal cross section
A2
HD
HE
A
11.8 12.0 12.2
11.8 12.0 12.2
1.7
1
16
Index mark
ZD
A1
bp
b1
c
0.05
0.15
0.1
0.15 0.20 0.25
0.18
F
S
0.09
0.20
0.145
0.125
c1
0°
8°
y
S
e
0.5
*3
L
bp
e
x
0.08
0.08
x
L1
y
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 57 of 58
R8C/36T-A Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
MASS[Typ.]
0.7g
64P6U-A/ ⎯
HD
*1
D
33
48
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
A2
HD
HE
A
64
17
A1
bp
b1
c
0.1 0.2
0.32 0.37 0.42
0.35
0
1
16
ZD
Index mark
F
0.145
0.125
0.09
0.20
S
c1
L
L1
0°
8°
e
x
y
0.8
y
S
Detail F
0.20
0.10
*3
e
bp
x
ZD
ZE
L
1.0
1.0
0.3 0.5 0.7
1.0
L1
R01DS0055EJ0100 Rev.1.00
Dec 09, 2011
Page 58 of 58
REVISION HISTORY
R8C/36T-A Group Datasheet
Description
Summary
Rev.
Date
Page
—
0.01
1.00
Feb 23, 2011
Dec 09, 2011
First Edition issued
All pages “Preliminary”, “Under development” deleted,
“sensor control unit” “touch sensor control unit”
2, 3
6
Tables 1.1 and 1.2 revised
Figure 1.3 “P3_10/CH10” “P3_1/CH10”
Table 1.8 “Touch sensor control unit” added
2.1 revised
11
13
16, 17,
19 to 22,
24 to 28
Tables 3.1, 3.2, 3.4 to 3.7, 3.9 to 3.13
32
Table 3.17 revised, Note 2 added
“4. Electrical Characteristics” added
33 to 56
All trademarks and registered trademarks are the property of their respective owners.
C - 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
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depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
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no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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