R5F21546EJFP [RENESAS]
RENESAS MCU;
| 型号： | R5F21546EJFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | RENESAS MCU |
| 文件： | 总55页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
RENESAS MCU
R01DS0043EJ0010
Rev.0.10
Mar 15, 2011
1. Overview
1.1
Features
The R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group single-chip microcontrollers (MCUs)
incorporate the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1
Mbyte of address space, the CPU core is capable of executing instructions at high speed. In addition, it features a
multiplier for high-speed arithmetic processing.
Power consumption is low, and additional power control is possible by selecting the operating mode. The R8C/54E
Group, R8C/54F Group, R8C/54G Group, R8C/54H Group are also designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface on the same chip,
reduces the number of system components.
The R8C/54E Group and R8C/54F Group incorporate one channel of CAN module, ideal for the LAN systems of
automotive and factory automation applications.
The R8C/54G Group and R8C/54H Group do not incorporate the CAN module.
The R8C/54E Group and R8C/54G Group also have on-chip data flash (1 KB × 4 blocks) with background
operation (BGO) function.
1.1.1
Applications
Automotive, etc.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 1 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the R8C/54E Group Specifications. Tables 1.3 and 1.4 outline the R8C/54F Group
Specifications. Tables 1.5 and 1.6 outline the R8C/54G Group Specifications. Tables 1.7 and 1.8 outline the
R8C/54H Group Specifications.
Table 1.1
Item
R8C/54E Group Specifications (1)
Function
Description
CPU
Central
R8C CPU core
processing unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM,
data flash
See Table 1.9 R8C/54E Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Clock
Programmable
I/O ports
• Input only: 1
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 2 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.2
R8C/54E Group Specifications (2)
Item
Function
Description
Timer
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
Timers RD_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (three-
phase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
UART0_1
2 channels
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
2 channels (also used for the I2C bus)
Clock
(SSU)
Synchronous
serial interface SSU_1
SSU_0 and
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
(I2C bus)
2 channels (also used for the SSU)
I2C_0 and I2C_1
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
HW-LIN_1
Hardware LIN
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
CAN module
A/D converter
Comparator B
CRC calculator
Flash memory
CAN_0
1 channel: 16 mailboxes (ISO11898-1 standard compliant)
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
2 circuits
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
Debug functions
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
Operating frequency/
Power supply voltage
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
Current consumption
T.B.D.
Operating ambient temperature
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
Package
Note:
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 3 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.3
R8C/54F Group Specifications (1)
Item
CPU
Function
Description
Central
R8C CPU core
processing unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM
See Table 1.10 R8C/54F Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Clock
Programmable
I/O ports
• Input only: 1
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 4 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.4
R8C/54F Group Specifications (2)
Item
Function
Description
Timer
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
Timers RD_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (three-
phase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
UART0_1
2 channels
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
2 channels (also used for the I2C bus)
Clock
(SSU)
Synchronous
serial interface SSU_1
SSU_0 and
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
(I2C bus)
2 channels (also used for the SSU)
I2C_0 and I2C_1
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
HW-LIN_1
Hardware LIN
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
CAN module
A/D converter
Comparator B
CRC calculator
Flash memory
CAN_0
1 channel: 16 mailboxes (ISO11898-1 standard compliant)
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
2 circuits
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance: 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Debug functions
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
Operating frequency/
Power supply voltage
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
Current consumption
T.B.D.
Operating ambient temperature
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
Package
Note:
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 5 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.5
R8C/54G Group Specifications (1)
Item
CPU
Function
Description
Central
R8C CPU core
processing unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM,
data flash
See Table 1.11 R8C/54G Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Clock
Programmable
I/O ports
• Input only: 1
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 6 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.6
R8C/54G Group Specifications (2)
Item
Function
Description
Timer
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
Timers RD_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (three-
phase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
UART0_1
2 channels
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
2 channels (also used for the I2C bus)
Clock
(SSU)
Synchronous
serial interface SSU_1
SSU_0 and
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
(I2C bus)
2 channels (also used for the SSU)
I2C_0 and I2C_1
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
HW-LIN_1
Hardware LIN
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
A/D converter
Comparator B
CRC calculator
Flash memory
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
2 circuits
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
Debug functions
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
Operating frequency/
Power supply voltage
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
Current consumption
T.B.D.
Operating ambient temperature
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
Package
Note:
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 7 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.7
R8C/54H Group Specifications (1)
Item
CPU
Function
Description
Central
R8C CPU core
processing unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM
See Table 1.12 R8C/54H Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Clock
Programmable
I/O ports
• Input only: 1
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 8 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.8
R8C/54H Group Specifications (2)
Item
Function
Description
Timer
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
Timers RD_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (three-
phase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
UART0_1
2 channels
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
2 channels (also used for the I2C bus)
Clock
(SSU)
Synchronous
serial interface SSU_1
SSU_0 and
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
(I2C bus)
2 channels (also used for the SSU)
I2C_0 and I2C_1
(2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
HW-LIN_1
Hardware LIN
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
A/D converter
Comparator B
CRC calculator
Flash memory
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
2 circuits
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance: 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Debug functions
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
Operating frequency/
Power supply voltage
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
Current consumption
T.B.D.
Operating ambient temperature
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
Package
Note:
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 9 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
1.2
Product List
Table 1.9 shows the R8C/54E Group Product List. Figure 1.1 shows the R8C/54E Group Product Part Number
Structure. Table 1.10 shows the R8C/54F Group Product List. Figure 1.2 shows the R8C/54F Group Product Part
Number Structure. Table 1.11 shows the R8C/54G Group Product List. Figure 1.3 shows the R8C/54G Group
Product Part Number Structure. Table 1.12 shows the R8C/54H Group Product List. Figure 1.4 shows the R8C/54H
Group Product Part Number Structure.
Table 1.9
R8C/54E Group Product List
Internal ROM Capacity
Current of Mar 2011
Internal RAM
Capacity
Part No.
Package Type
PLQP0048KB-A
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
R5F21546EJFP
R5F21547EJFP
R5F21548EJFP
R5F2154AEJFP
R5F2154CEJFP
R5F21546EKFP
R5F21547EKFP
R5F21548EKFP
R5F2154AEKFP
R5F2154CEKFP
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
K version
Part No. R 5 F 21 54 C E J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7 7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54E Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
R8C/54E Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 10 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.10
R8C/54F Group Product List
Internal ROM Capacity
Current of Mar 2011
Part No.
Internal RAM Capacity Package Type
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
R5F21546FJFP
R5F21547FJFP
R5F21548FJFP
R5F2154AFJFP
R5F2154CFJFP
R5F21546FKFP
R5F21547FKFP
R5F21548FKFP
R5F2154AFKFP
R5F2154CFKFP
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
K version
Part No. R 5 F 21 54 C F J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7 7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54F Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
R8C/54F Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 11 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.11
R8C/54G Group Product List
Internal ROM Capacity
Current of Mar 2011
Internal RAM
Capacity
Part No.
Package Type
PLQP0048KB-A
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
R5F21546GJFP
R5F21547GJFP
R5F21548GJFP
R5F2154AGJFP
R5F2154CGJFP
R5F21546GKFP
R5F21547GKFP
R5F21548GKFP
R5F2154AGKFP
R5F2154CGKFP
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
K version
Part No. R 5 F 21 54 C G J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7 7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54G Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
R8C/54G Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 12 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.12
R8C/54H Group Product List
Internal ROM Capacity
Current of Mar 2011
Part No.
Internal RAM Capacity Package Type
Remarks
J version
Program ROM
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
R5F21546HJFP
R5F21547HJFP
R5F21548HJFP
R5F2154AHJFP
R5F2154CHJFP
R5F21546HKFP
R5F21547HKFP
R5F21548HKFP
R5F2154AHKFP
R5F2154CHKFP
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0048KB-A
K version
Part No. R 5 F 21 54 C H J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7 7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54H Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
R8C/54H Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 13 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
1.3
Block Diagram
Figure 1.5 shows the Block Diagram.
8
8
8
5
1
6
8
Port P0
Port P1
Port P2
I/O ports
Port P3
Port P6
Port P4
PMC (Peripheral Mapping Controller)
System clock generation circuit
Peripheral functions
XIN-XOUT
A/D converter
(10 bits 12 channels)
High-speed on-chip oscillator
Low-speed on-chip oscillator
Low-speed on-chip oscillator
(for watchdog timer)
Timers
Timer RJ (16 bits 2)
Timer RB2 (16 bits 1)
Timer RC (16 bits 1)
Timer RD (16 bits 2)
Timer RE2 (8 bits 1)
PLL frequency synthesizer
UART0
(8 bits 2 channels)
Voltage detection circuit
UART2
(8 bits 1 channel)
Comparator B
DTC
CAN module (1)
(1 channel)
Event link controller
Synchronous serial
communication unit (SSU/I2C)
LIN module
(2 channels)
(8 bits 2 channels)
Watchdog timer
(14 bits)
Memory
R8C CPU core
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
ROM (2)
R2
R3
CRC calculator
RAM (3)
A0
A1
FB
Multiplier
PMC (Peripheral Mapping Controller)
Port P9
4
Notes:
1. Available only in the R8C/54E Group and the R8C/54F Group.
2. ROM size varies with the product.
3. RAM size varies with the product.
Figure 1.5
Block Diagram
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 14 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
1.4
Pin Assignment
Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 to 1.17 list the Pin Name Information by Pin Number.
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P0_6/AN1/TRCIOD_0
P0_5/AN2/CLK2/TRCIOB_0
P1_3/KI3/AN11/TRBO_0/TRCIOC_0/TRDIOD1_0
P1_4/TXD_0/TRCCLK_0
R8C/54E Group
R8C/54F Group
R8C/54G Group
R8C/54H Group
P0_4/AN3/TMRE2O/TRCIOB_0
P1_5/RXD_0/TRJIO_0/INT1
P4_2/VREF
P1_6/CLK_0/SSI_0
P6_0/TMRE2O
P1_7/INT1/TRJIO_0
P6_2/CRX_0 (1)/CLK_1
P2_0/TRDIOA0_0/TRDCLK_0/TXD2/INT1/RXD2/TRCIOB_0
P2_1/TRDIOB0_0/TRDIOC0_0/TRCIOC_0
P2_2/TRDIOC0_0/TRDIOB0_0/TRCIOD_0
P2_3/TRDIOD0_0
P6_1/CTX_0 (1)
P0_3/AN4/CLK_1/TRCIOB_0
P0_2/AN5/RXD_1/TRCIOA_0/TRCTRG_0/TRJIO_1/INT2
P0_1/AN6/TXD_1/TRCIOA_0/TRCTRG_0/TRJO_1
P0_0/AN7/TXD2/TRCIOA_0/TRCTRG_0
P3_7/SSO_0/TXD2/RXD2/TRJO_0/SDA_0/INT3/TRCCLK_0/TRDIOC0_0
PLQP0048KB-A (48P6Q-A)
(Top view)
P2_4/TRDIOA1_0/IVCMP3
P2_5/TRDIOB1_0/IVREF3
P2_6/TRDIOC1_0
Note:
1. Available only in the R8C/54E Group and the R8C/54F Group.
Figure 1.6
Pin Assignment (Top View)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 15 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.13
Pin Name Information by Pin Number (INT, URAT0, and UART2)
INT
UART0
UART2
CTS2
Port
Pin No.
INT0
INT1
INT2
INT3
INT4
TXD_0
TXD_1
TXD_1
RXD_0 RXD_1
CLK_0
CLK_1
TXD2
TXD2
RXD2
RTS2
CLK2
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_3
P3_4
P3_5
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P9_4
P9_5
P9_6
P9_7
Note:
47
46
45
INT2
RXD_1
44
CLK_1
39
38
CLK2
37
36
30
29
28
24
23
TXD_0
22
INT1
RXD_0
21
CLK_0
20
INT1
INT1
19 (1)
18 (1)
17 (1)
16 (1)
15
TXD2
RXD2
14
13
12
32
31
CTS2
CTS2
RTS2
RTS2
2
INT3
INT3
3
TXD2
TXD2
RXD2
RXD2
1
CLK2
48
40
5
6
25
INT0
RXD2
10
8
41
43
42
CLK_1
CLK_1
35
TXD_1
34
INT2
INT2
RXD_1
33
INT4
CLK2
26
TXD2
27
INT3
RXD2
19 (1)
18 (1)
17 (1)
16 (1)
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 16 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.14
Pin Name Information by Pin Number (CAN and SSU)
CAN (1)
SSU/I2C
Port
Pin No.
CTX_0 CRX_0
SCL_0
SCL_1
SDA_0
SDA_1
SSI_0
SSI_1 SCS_0
SCS_1
SSCK_0
SSCK_1
SSO_0
SSO_1
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_3
P3_4
P3_5
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P9_4
P9_5
P9_6
P9_7
Notes:
47
46
45
44
39
38
37
36
30
29
28
24
23
22
21
SSI_0
20
19 (2)
18 (2)
17 (2)
16 (2)
15
14
13
12
32
31
2
SSI_0
SSI_0
SCS_0
SCS_0
3
SDA_0
SDA_0
1
SCL_0
SSCK_0
48
SSO_0
40
5
6
25
10
8
41
43
CTX_0
42
CRX_0
35
34
33
26
27
19 (2)
18 (2)
17 (2)
16 (2)
SSI_1
SDA_1
SCS_1
SCL_1
SSCK_1
SSO_1
1. Available only in the R8C/54E Group and the R8C/54F Group.
2. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 17 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.15
Pin Name Information by Pin Number (Timer RJ, Timer RB2, and Timer RC)
Timer RJ
Timer RB2
Timer RC
Port
Pin No.
TRJO_0
TRJO_1
TRJIO_0
TRJIO_1
TRBO_0
TRCCLK_0
TRCIOA_0
TRCIOA_0
TRCIOA_0
TRCIOA_0
TRCIOB_0
TRCIOC_0
TRCIOD_0
TRCTRG_0
TRCTRG_0
TRCTRG_0
TRCTRG_0
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_3
P3_4
P3_5
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P9_4
P9_5
P9_6
P9_7
Note:
47
46
TRJO_1
45
TRJIO_1
44
TRCIOB_0
TRCIOB_0
TRCIOB_0
39
38
37
TRCIOD_0
TRCIOD_0
36
TRCIOC_0
TRCIOC_0
30
29
TRCIOA_0
TRCTRG_0
28
TRCIOB_0
24
TRBO_0
23
TRCCLK_0
22
TRJIO_0
TRJIO_0
21
20
19 (1)
18 (1)
17 (1)
16 (1)
15
TRCIOB_0
TRCIOC_0
TRCIOD_0
14
13
12
32
TRJO_0
TRJO_0
31
TRBO_0
2
TRCCLK_0
TRCCLK_0
3
TRCIOC_0
1
TRCIOD_0
48
40
5
6
25
10
8
41
43
42
35
TRJO_1
34
TRJIO_1
33
TRCIOB_0
26
TRCIOC_0
27
TRCIOD_0
19 (1)
18 (1)
17 (1)
16 (1)
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 18 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.16
Pin Name Information by Pin Number (Timer RD and Timer RE2)
Timer RD
Timer RE2
TMRE2O
Port
Pin No.
TRDCLK_0
TRDIOA0_0
TRDIOB0_0
TRDIOC0_0
TRDIOD0_0
TRDIOA1_0
TRDIOB1_0
TRDIOC1_0
TRDIOD1_0
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_3
P3_4
P3_5
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P9_4
P9_5
P9_6
P9_7
Note:
47
46
45
44
39
TMRE2O
38
37
36
30
TRDIOA1_0
29
TRDIOB1_0
28
TRDIOC1_0
24
TRDIOD1_0
23
22
21
20
19 (1)
18 (1)
17 (1)
16 (1)
15
TRDCLK_0
TRDIOA0_0
TRDIOB0_0
TRDIOB0_0
TRDIOC0_0
TRDIOC0_0
TRDIOD0_0
TRDIOA1_0
14
TRDIOB1_0
13
TRDIOC1_0
TRDIOC1_0
12
TRDIOD1_0
TRDIOD1_0
32
31
2
TRDIOD0_0
3
TRDIOB0_0
1
TRDCLK_0
TRDIOA0_0
48
TRDIOC0_0
40
5
6
25
10
8
41
TMRE2O
43
42
35
34
33
26
27
19 (1)
18 (1)
17 (1)
16 (1)
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 19 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.17
Pin Name Information by Pin Number (Others)
Port
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_3
P3_4
P3_5
P3_7
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P9_4
P9_5
P9_6
P9_7
Note:
Pin No.
Others
47
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
46
45
44
39
38
37
36
30
KI0
KI1
KI2
KI3
AN8
AN9
IVREF1
IVCMP1
29
28
AN10
AN11
24
23
22
21
20
19 (1)
18 (1)
17 (1)
16 (1)
15
IVCMP3
IVREF3
14
13
12
32
31
2
3
1
48
40
VREF
5
6
25
10
XIN
8
XOUT
41
43
42
35
34
33
26
27
19 (1)
18 (1)
17 (1)
16 (1)
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 20 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
1.5
Pin Functions
Tables 1.18 and 1.19 list Pin Functions.
Table 1.18
Item
Pin Functions (1)
Pin Name
VCC, VSS
I/O
—
Description
Power supply input
Apply 2. 7 V through 5.5 V to the VCC pin when the
CPU clock = 32 MHz and apply 1.8 V through 2.7 V to
this pin when the CPU clock = 5 MHz.
Apply 0 V to the VSS pin.
Analog power supply
input
AVCC, AVSS
—
I
Power supply input for the A/D converter.
Connect a capacitor between pins AVCC and AVSS.
Reset input
Applying a low level to this pin resets the MCU.
Connect this pin to the VCC pin via a resistor.
RESET
MODE
XIN
MODE
I
I
XIN clock input
XIN clock output
I/O for the XIN clock generation circuit.
Connect a ceramic resonator or a crystal oscillator
between pins XIN and XOUT. (1)
XOUT
I/O
To use an external clock, input it to the XIN pin and
leave the XOUT pin open.
I
I
INT interrupt input
Key input interrupt
INT0 to INT4
KI0 to KI3
INT interrupt input.
Key input interrupt input.
Timers RJ_0 and RJ_1 TRJIO_0, TRJIO_1
TRJO_0, TRJO_1
I/O
O
O
I
Input/output for timer RJ.
Output for timer RJ.
Timers RB2_0
Timers RC_0
TRBO_0
Output for timer RB2.
External clock input.
External trigger input.
Input/output for timer RC.
TRCCLK_0
TRCTRG_0
I
TRCIOA_0, TRCIOB_0,
TRCIOC_0, TRCIOD_0
I/O
Timers RD_0
TRDIOA0_0,
TRDIOA1_0,
TRDIOB0_0,
TRDIOB1_0,
TRDIOC0_0,
TRDIOC1_0,
TRDIOD0_0,
TRDIOD1_0
I/O
Input/output for timer RD.
TRDCLK_0
I
O
I/O
I
External clock input.
Divided clock output.
Transfer clock input/output.
Serial data input.
Timer RE2
TMRE2O
Serial interface
(UART0)
CLK_0, CLK_1
RXD_0, RXD_1
TXD_0, TXD_1
O
I
Serial data output.
Serial interface
(UART2)
Input for transmission control.
CTS2
O
Output for reception control.
RTS2
RXD2
TXD2
CLK2
I
Serial data input.
O
Serial data output.
I/O
Transfer clock input/output.
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 21 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1. Overview
Table 1.19
Item
Pin Functions (2)
Pin Name
SSI_0, SSI_1
I/O
I/O
I/O
Description
Synchronous serial
communication unit
(SSU_0, SSU_1)
Data input/output.
Chip-select input/output.
SCS_0, SCS_1
SSCK_0, SSCK_1
SSO_0, SSO_1
SCL_0, SCL_1
SDA_0, SDA_1
CRX_0
I/O
I/O
I/O
I/O
I
Clock input/output.
Data input/output.
I2C bus
(I2C_0 and I2C_1)
CAN module (CAN_0) (1)
Clock input/output.
Data input/output.
Data input for CAN.
CTX_0
O
I
Data output for CAN.
Reference voltage input VREF
Reference voltage input for the A/D converter.
Analog input for the A/D converter.
Analog voltage input for comparator B.
Reference voltage input for comparator B.
8-bit CMOS input/output ports.
Each port has an I/O select direction register, enabling
switching input and output for each pin.
For input ports, the presence or absence of a pull-up
resistor can be selected by a program.
A/D converter
Comparator B
AN0 to AN11
I
IVCMP1, IVCMP3
IVREF1, IVREF3
I
I
I/O ports
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 and P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_7,
P6_0 to P6_7,
P9_4 to P9_7
I/O
All ports can be used as LED drive (high drive) ports.
Input port
Note:
P4_2
I
Input-only port.
1. Available only in the R8C/54E Group and the R8C/54F Group.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 22 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the 13 CPU Registers. The registers R0, R1, R2, R3, A0, A1, and FB form a single register bank. The
CPU has two register banks.
b31
b15
b8 b7
b0
R0H (R0 high-order byte) R0L (R0 low-order byte)
R2
R3
R1H (R1 high-order byte) R1L (R1 low-order byte)
Data registers (1)
R2
R3
A0
A1
FB
Address registers (1)
Frame base register (1)
b19
b15
b0
Interrupt table register
Program counter
INTBH
INTBL
The higher 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
O
b15
b8 b7
IPL
U
I
B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bits
Processor interrupt priority level
Reserved bit
Note:
1. These registers form a single register bank.
The CPU has two register banks.
Figure 2.1
CPU Registers
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 23 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3.
R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers.
The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). In the
same way as with R0 and R2, R3 and R1 can be used as a 32-bit data register (R3R1).
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
PC is a 20-bit register that indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch
between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. It must only be set to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 24 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I
flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware
interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is
executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has
higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
The write value must be 0. The read value is undefined.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 25 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
3. Address Space
3.1
R8C/54E Group Memory Map
Figure 3.1 shows the R8C/54E Group Memory Map. The R8C/54E Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (2)
0FFDCh
06FFFh
07000h
Undefined instruction
Overflow
Internal ROM
(data flash) (1)
BRK instruction
Address match
07FFFh
0YYYYh
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the CAN, DTC, and other SFR areas.
3. The blank areas are reserved. No access is allowed.
Internal ROM
Internal RAM
Part Number
Address 0YYYYh Address ZZZZZh
Address 0XXXXh
Capacity
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
R5F21546EJFP, R5F21546EKFP
R5F21547EJFP, R5F21547EKFP
R5F21548EJFP, R5F21548EKFP
R5F2154AEJFP, R5F2154AEKFP
R5F2154CEJFP, R5F2154CEKFP
08000h
08000h
08000h
08000h
08000h
0FFFFh
13FFFh
17FFFh
1FFFFh
27FFFh
00DFFh
013FFh
01BFFh
023FFh
02BFFh
Figure 3.1
R8C/54E Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 26 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
3.2
R8C/54F Group Memory Map
Figure 3.2 shows the R8C/54F Group Memory Map. The R8C/54F Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (1)
0FFDCh
06FFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
0FFFFh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Addresses 06800h to 06FFFh are used for the CAN, DTC, and other SFR areas.
2. The blank areas are reserved. No access is allowed.
Internal ROM
Part Number
Internal RAM
Address 0YYYYh Address ZZZZZh
Address 0XXXXh
Capacity
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
R5F21546FJFP, R5F21546FKFP
R5F21547FJFP, R5F21547FKFP
R5F21548FJFP, R5F21548FKFP
R5F2154AFJFP, R5F2154AFKFP
R5F2154CFJFP, R5F2154CFKFP
08000h
08000h
08000h
08000h
08000h
0FFFFh
13FFFh
17FFFh
1FFFFh
27FFFh
00DFFh
013FFh
01BFFh
023FFh
02BFFh
Figure 3.2
R8C/54F Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 27 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
3.3
R8C/54G Group Memory Map
Figure 3.3 shows the R8C/54G Group Memory Map. The R8C/54G Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (2)
0FFDCh
06FFFh
07000h
Undefined instruction
Overflow
Internal ROM
(data flash) (1)
BRK instruction
Address match
07FFFh
0YYYYh
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the DTC and other SFR areas.
3. The blank areas are reserved. No access is allowed.
Internal ROM
Internal RAM
Part Number
Address 0YYYYh Address ZZZZZh
Address 0XXXXh
Capacity
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
R5F21546GJFP, R5F21546GKFP
R5F21547GJFP, R5F21547GKFP
R5F21548GJFP, R5F21548GKFP
R5F2154AGJFP, R5F2154AGKFP
R5F2154CGJFP, R5F2154CGKFP
08000h
08000h
08000h
08000h
08000h
0FFFFh
13FFFh
17FFFh
1FFFFh
27FFFh
00DFFh
013FFh
01BFFh
023FFh
02BFFh
Figure 3.3
R8C/54G Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 28 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
3.4
R8C/54H Group Memory Map
Figure 3.4 shows the R8C/54H Group Memory Map. The R8C/54H Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (1)
0FFDCh
06FFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
0FFFFh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Addresses 06800h to 06FFFh are used for the DTC and other SFR areas.
2. The blank areas are reserved. No access is allowed.
Internal ROM
Part Number
Internal RAM
Address 0YYYYh Address ZZZZZh
Address 0XXXXh
Capacity
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
R5F21546HJFP, R5F21546HKFP
R5F21547HJFP, R5F21547HKFP
R5F21548HJFP, R5F21548HKFP
R5F2154AHJFP, R5F2154AHKFP
R5F2154CHJFP, R5F2154CHKFP
08000h
08000h
08000h
08000h
08000h
0FFFFh
13FFFh
17FFFh
1FFFFh
27FFFh
00DFFh
013FFh
01BFFh
023FFh
02BFFh
Figure 3.4
R8C/54H Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 29 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
3.5
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 3.1 to 3.23 list the SFR
Information. Table 3.23 lists the ID code Area, Option Function Select Area.
(1)
Table 3.1
SFR Information (1)
Address
Symbol
Register Name
After Reset
Remarks
00000h
00001h
00002h
00003h
00004h PM0
00005h PM1
00006h
Processor Mode Register 0
Processor Mode Register 1
00h
10000000b
00007h PRCR
00008h CM0
00009h CM1
0000Ah OCD
0000Bh CM3
0000Ch CM4
0000Dh
Protect Register
00h
System Clock Control Register 0
System Clock Control Register 1
Oscillation Stop Detection Register
System Clock Control Register 3
System Clock Control Register 4
00101000b
00100000b
00h
00h
00000001b
0000Eh
0000Fh PCLKR1
00010h
Peripheral Clock Select Register 1
00h
00011h
00012h FRA0
00013h
00014h FRA2
00015h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 2
00h
00h
00016h
00017h
00018h
00019h
0001Ah
0001Bh
0001Ch PLC0
0001Dh PLCF
0001Eh
PLL Control Register 0
PLL Function Clock Control Register 1
00010010b
00h
0001Fh
00020h RISR
Reset Interrupt Select Register
10000000b or
00000000b
FFh
(Note 2)
00021h WDTR
00022h WDTS
00023h WDTC
00024h CSPR
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Count Source Protection Mode Register
FFh
01111111b
10000000b or
00000000b
(Note 2)
00025h
00026h
00027h
00028h RSTFR
00029h
0002Ah
0002Bh
0002Ch SVDC
0002Dh
Reset Source Determination Register
STBY VDC Power Control Register
00XXXXXXb
00h
0002Eh
0002Fh
00030h CMPA
00031h VCAC
00032h OCVREFCR
00033h
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
On-Chip Reference Voltage Control Register
00h
00h
00h
00034h VCA2
Voltage Detection Register 2
00000000b or
00100000b
(Note 3)
00035h
00036h VD1LS
00037h
Voltage Detection 1 Level Select Register
00000111b
00038h VW0C
00039h VW1C
X: Undefined
Notes:
Voltage Monitor 0 Circuit Control Register
Voltage Monitor 1 Circuit Control Register
11001010b or 11001011b (Note 3)
10001010b
1. The blank areas are reserved. No access is allowed.
2. Depends on the CSPROINI bit in the OFS register.
3. Depends on the LVDASI bit in the OFS register.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 30 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.2
SFR Information (2)
Address
0003Ah VW2C
0003Bh
Symbol
Register Name
Voltage Monitor 2 Circuit Control Register
After Reset
10001010b
Remarks
0003Ch
0003Dh
0003Eh
0003Fh
00040h
00041h FMRDYIC
00042h TRJIC_1
00043h
Interrupt Control Register
Interrupt Control Register
00h
00h
00044h
00045h
00046h INT4IC
00047h TRCIC_0
00048h TRD0IC_0
00049h TRD1IC_0
0004Ah TRE2IC
0004Bh U2TIC
0004Ch U2RIC
0004Dh KUPIC
0004Eh ADIC
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0004Fh SSUIC_0/IICIC_0 Interrupt Control Register
00050h
00051h U0TIC_0
00052h U0RIC_0
00053h U0TIC_1
00054h U0RIC_1
00055h INT2IC
00056h TRJIC_0
00057h
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
00h
00h
00h
00058h TRB2IC_0
00059h INT1IC
0005Ah INT3IC
0005Bh
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
0005Ch
0005Dh INT0IC
0005Eh U2BCNIC
0005Fh
Interrupt Control Register
Interrupt Control Register
00h
00h
00060h
00061h
00062h
00063h
00064h
00065h
00066h
00067h
00068h
00069h
0006Ah
0006Bh
0006Ch CANRXIC_0
0006Dh CANTXIC_0
0006Eh CANERIC_0
0006Fh
Interrupt Control Register
Interrupt Control Register
Interrupt Control Register
00h
00h
00h
00070h
00071h
00072h VCMP1IC
00073h VCMP2IC
00074h
Interrupt Control Register
Interrupt Control Register
00h
00h
00075h
00076h
00077h
00078h
00079h SSUIC_1/IICIC_1 Interrupt Control Register
Note:
1. The blank areas are reserved. No access is allowed.
00h
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 31 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.3
SFR Information (3)
Address
0007Ah
0007Bh
0007Ch
0007Dh
0007Eh
0007Fh
Symbol
Register Name
After Reset
Remarks
00080h U0MR_0
00081h U0BRG_0
00082h U0TB_0
00083h
UART0_0 Transmit/Receive Mode Register
UART0_0 Bit Rate Register
UART0_0 Transmit Buffer Register
00h
XXh
XXh
XXh
00084h U0C0_0
00085h U0C1_0
00086h U0RB_0
00087h
UART0_0 Transmit/Receive Control Register 0
UART0_0 Transmit/Receive Control Register 1
UART0_0 Receive Buffer Register
00001000b
00000010b
XXXXh
00088h U0IR_0
00089h
UART0_0 Interrupt Flag and Enable Register
00h
0008Ah
0008Bh
0008Ch LINCR2_0
0008Dh
LIN_0 Special Function Register
00h
0008Eh LINCT_0
0008Fh LINST_0
00090h U0MR_1
00091h U0BRG_1
00092h U0TB_1
00093h
LIN_0 Control Register
LIN_0 Status Register
UART0_1 Transmit/Receive Mode Register
UART0_1 Bit Rate Register
UART0_1 Transmit Buffer Register
00h
00h
00h
XXh
XXh
XXh
00094h U0C0_1
00095h U0C1_1
00096h U0RB_1
00097h
UART0_1 Transmit/Receive Control Register 0
UART0_1 Transmit/Receive Control Register 1
UART0_1 Receive Buffer Register
00001000b
00000010b
XXXXh
00098h U0IR_1
00099h
UART0_1 Interrupt Flag and Enable Register
00h
0009Ah
0009Bh
0009Ch LINCR2_1
0009Dh
LIN_1 Special Function Register
00h
0009Eh LINCT_1
0009Fh LINST_1
000A0h
LIN_1 Control Register
LIN_1 Status Register
00h
00h
000A1h
000A2h
000A3h
000A4h
000A5h
000A6h
000A7h
000A8h
000A9h
000AAh
000ABh
000ACh
000ADh
000AEh
000AFh
000B0h
000B1h
000B2h
000B3h
000B4h
000B5h
000B6h
000B7h
000B8h
000B9h
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 32 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.4
SFR Information (4)
Address
000BAh
000BBh
000BCh
000BDh
000BEh
000BFh
Symbol
Register Name
After Reset
Remarks
000C0h U2MR
000C1h U2BRG
000C2h U2TB
000C3h
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
00h
00h
00h
00h
000C4h U2C0
000C5h U2C1
000C6h U2RB
000C7h
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
00001000b
00000010b
0000h
000C8h U2RXDF
000C9h
UART2 Digital Filter Function Select Register
00h
000CAh
000CBh
000CCh
000CDh
000CEh
000CFh
000D0h U2SMR5
000D1h
UART2 Special Mode Register 5
00h
000D2h
000D3h
000D4h
000D5h U2SMR3
000D6h
000D7h U2SMR
000D8h
UART2 Special Mode Register 3
UART2 Special Mode Register
00h
00h
000D9h
000DAh
000DBh
000DCh
000DDh
000DEh
000DFh
I2C_0 Control Register
SS_0 Bit Counter Register
SI_0 Transmit Data Register
000E0h IICCR_0
000E1h SSBR_0
000E2h SITDR_0
000E3h
00001110b
11111000b
FFh
FFh
000E4h SIRDR_0
000E5h
SI_0 Receive Data Register
FFh
FFh
000E6h SICR1_0
000E7h SICR2_0
000E8h SIMR1_0
000E9h SIER_0
000EAh SISR_0
000EBh SIMR2_0
000ECh
SI_0 Control Register 1
SI_0 Control Register 2
SI_0 Mode Register 1
SI_0 Interrrupt Enable Register
SI_0 Status Register
00h
01111101b
00010000b
00h
00h
00h
SI_0 Mode Register 2
000EDh
000EEh
000EFh
I2C_1 Control Register
SS_1 Bit Counter Register
SI_1 Transmit Data Register
000F0h IICCR_1
000F1h SSBR_1
000F2h SITDR_1
000F3h
00001110b
11111000b
FFh
FFh
000F4h SIRDR_1
000F5h
SI_1 Receive Data Register
FFh
FFh
000F6h SICR1_1
000F7h SICR2_1
000F8h SIMR1_1
000F9h SIER_1
X: Undefined
Note:
SI_1 Control Register 1
SI_1 Control Register 2
SI_1 Mode Register 1
00h
01111101b
00010000b
00h
SI_1 Interrrupt Enable Register
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 33 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.5
SFR Information (5)
Address
Symbol
Register Name
After Reset
Remarks
000FAh SISR_1
000FBh SIMR2_1
000FCh
SI_1 Status Register
SI_1 Mode Register 2
00h
00h
000FDh
000FEh
000FFh
00100h
00101h
00102h
00103h
00104h
00105h
00106h
00107h
00108h
00109h
0010Ah
0010Bh
0010Ch
0010Dh
0010Eh
0010Fh
00110h TRJ_0
00111h
Timer RJ_0 Counter Register
FFFFh
00112h TRJCR_0
00113h TRJIOC_0
00114h TRJMR_0
00115h TRJISR_0
00116h
Timer RJ_0 Control Register
Timer RJ_0 I/O Control Register
Timer RJ_0 Mode Register
00h
00h
00h
00h
Timer RJ_0 Event Pin Select Register
00117h
00118h TRJ_1
00119h
Timer RJ_1 Counter Register
FFFFh
0011Ah TRJCR_1
0011Bh TRJIOC_1
0011Ch TRJMR_1
0011Dh TRJISR_1
0011Eh
Timer RJ_1 Control Register
Timer RJ_1 I/O Control Register
Timer RJ_1 Mode Register
00h
00h
00h
00h
Timer RJ_1 Event Pin Select Register
0011Fh
00120h
00121h
00122h
00123h
00124h
00125h
00126h
00127h
00128h
00129h
0012Ah
0012Bh
0012Ch
0012Dh
0012Eh
0012Fh
00130h TRBCR_0
00131h TRBOCR_0
00132h TRBIOC_0
00133h TRBMR_0
00134h TRBPRE_0
Timer RB2_0 Control Register
Timer RB2_0 One-Shot Control Register
Timer RB2_0 I/O Control Register
Timer RB2_0 Mode Register
Timer RB2_0 Prescaler Register
00h
00h
00h
00h
FFh
Timer RB2_0 Primary/Secondary Register (Lower 8 Bits)
Timer RB2_0 Primary Register
Timer RB2_0 Primary Register (Higher 8 Bits)
Timer RB2_0 Secondary Register
00135h TRBPR_0
00136h TRBSC_0
FFh
FFh
Timer RB2_0 Secondary Register (Higher 8 Bits)
Timer RB2_0 Interrupt Request and Status Register
Timer RC_0 Counter
00137h TRBIR_0
00138h TRCCNT_0
00139h
00h
0000h
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 34 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.6
SFR Information (6)
Address
0013Ah TRCGRA_0
0013Bh
0013Ch TRCGRB_0
0013Dh
0013Eh TRCGRC_0
0013Fh
Symbol
Register Name
Timer RC_0 General Register A
After Reset
Remarks
FFFFh
FFFFh
FFFFh
FFFFh
Timer RC_0 General Register B
Timer RC_0 General Register C
Timer RC_0 General Register D
00140h TRCGRD_0
00141h
00142h TRCMR_0
00143h TRCCR1_0
00144h TRCIER_0
00145h TRCSR_0
00146h TRCIOR0_0
00147h TRCIOR1_0
00148h TRCCR2_0
00149h TRCDF_0
0014Ah TRCOER_0
0014Bh TRCADCR_0
0014Ch TRCOPR_0
0014Dh TRCELCCR_0
0014Eh
Timer RC_0 Mode Register
Timer RC_0 Control Register 1
Timer RC_0 Interrupt Enable Register
Timer RC_0 Status Register
Timer RC_0 I/O Control Register 0
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00011000b
00h
01111111b
11110000b
00h
Timer RC_0 I/O Control Register 1
Timer RC_0 Control Register 2
Timer RC_0 Digital Filter Function Select Register
Timer RC_0 Output Enable Register
Timer RC_0 A/D Conversion Trigger Control Register
Timer RC_0 Output Waveform Manipulation Register
Timer RC_0 ELC Cooperation Control Register
00h
0014Fh
00150h
00151h
00152h
00153h
00154h
00155h
00156h
00157h
00158h
00159h
0015Ah
0015Bh
0015Ch
0015Dh
0015Eh
0015Fh
00160h
00161h
00162h
00163h
00164h
00165h
00166h
00167h
00168h
00169h
0016Ah
0016Bh
0016Ch
0016Dh
0016Eh
0016Fh
00170h TRESEC
00171h TREMIN
00172h
Timer RE2 Counter Data Register
Timer RE2 Compare Data Register
00h
00h
00173h
00174h
00175h
00176h
00177h TRECR
00178h TRECSR
00179h
Timer RE2 Control Register
Timer RE2 Count Source Select Register
00000100b
00001000b
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 35 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.7
SFR Information (7)
Address
Symbol
Register Name
Timer RE2 Interrupt Flag Register
Timer RE2 Interrupt Enable Register
After Reset
Remarks
0017Ah TREIFR
0017Bh TREIER
0017Ch
00h
00h
0017Dh
0017Eh
0017Fh TREPRC
00180h TRDELC_0
00181h
Timer RE2 Protect Register
Timer RD_0 ELC Register
00h
00h
00182h TRDADCR_0
00183h TRDSTR_0
00184h TRDMR_0
00185h TRDPMR_0
00186h TRDFCR_0
00187h TRDOER1_0
00188h TRDOER2_0
00189h TRDOCR_0
0018Ah TRDDF0_0
0018Bh TRDDF1_0
0018Ch
Timer RD_0 Trigger Control Register
Timer RD_0 Start Register
Timer RD_0 Mode Register
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
Timer RD_0 PWM Mode Register
Timer RD_0 Function Control Register
Timer RD_0 Output Master Enable Register 1
Timer RD_0 Output Master Enable Register 2
Timer RD_0 Output Control Register
Timer RD_0 Digital Filter Function Select Register 0
Timer RD_0 Digital Filter Function Select Register 1
00h
0018Dh
0018Eh
0018Fh
00190h TRDCR0_0
00191h TRDIORA0_0
00192h TRDIORC0_0
00193h TRDSR0_0
00194h TRDIER0_0
00195h TRDPOCR0_0
00196h TRD0_0
00197h
Timer RD_0 Control Register 0
00h
Timer RD_0 I/O Control Register A0
Timer RD_0 I/O Control Register C0
Timer RD_0 Status Register 0
Timer RD_0 Interrupt Enable Register 0
Timer RD_0 PWM Mode Output Level Control Register 0
Timer RD_0 Counter 0
10001000b
10001000b
11100000b
11100000b
11111000b
0000h
00198h TRDGRA0_0
00199h
0019Ah TRDGRB0_0
0019Bh
0019Ch TRDGRC0_0
0019Dh
0019Eh TRDGRD0_0
0019Fh
Timer RD_0 General Register A0
Timer RD_0 General Register B0
Timer RD_0 General Register C0
Timer RD_0 General Register D0
FFFFh
FFFFh
FFFFh
FFFFh
001A0h TRDCR1_0
001A1h TRDIORA1_0
001A2h TRDIORC1_0
001A3h TRDSR1_0
001A4h TRDIER1_0
001A5h TRDPOCR1_0
001A6h TRD1_0
001A7h
Timer RD_0 Control Register 1
00h
Timer RD_0 I/O Control Register A1
Timer RD_0 I/O Control Register C1
Timer RD_0 Status Register 1
Timer RD_0 Interrupt Enable Register 1
Timer RD_0 PWM Mode Output Level Control Register 1
Timer RD_0 Counter 1
10001000b
10001000b
11000000b
11100000b
11111000b
0000h
001A8h TRDGRA1_0
001A9h
001AAh TRDGRB1_0
001ABh
001ACh TRDGRC1_0
001ADh
001AEh TRDGRD1_0
001AFh
Timer RD_0 General Register A1
Timer RD_0 General Register B1
Timer RD_0 General Register C1
Timer RD_0 General Register D1
FFFFh
FFFFh
FFFFh
FFFFh
001B0h
to
001FFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 36 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.8
SFR Information (8)
Address
00200h AD0
00201h
00202h AD1
00203h
00204h AD2
00205h
00206h AD3
00207h
00208h AD4
00209h
0020Ah AD5
0020Bh
0020Ch AD6
0020Dh
0020Eh AD7
0020Fh
Symbol
Register Name
After Reset
Remarks
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00210h
00211h
00212h
00213h
00214h ADMOD
00215h ADINSEL
00216h ADCON0
00217h ADCON1
00218h
A/D Mode Register
00h
11000000b
00h
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
00h
00219h
0021Ah
0021Bh
0021Ch
0021Dh
0021Eh
0021Fh
00220h
00221h
00222h
00223h
00224h
00225h
00226h
00227h
00228h INTCMP
00229h
Comparator B Control Register 0
00h
0022Ah
0022Bh
0022Ch
0022Dh
0022Eh
0022Fh
00230h INTEN
00231h INTEN1
00232h INTF
00233h INTF1
00234h INTPOL
00235h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
INT Input Polarity Switch Register
00h
00h
00h
00h
00h
00236h KIEN
00237h
Key Input Interrupt Enable Register
00h
00238h MSTCR0
00239h MSTCR1
0023Ah MSTCR2
0023Bh MSTCR3
0023Ch
Module Standby Control Register 0
Module Standby Control Register 1
Module Standby Control Register 2
Module Standby Control Register 3
00h
00h
00h
00h
0023Dh
0023Eh
0023Fh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 37 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.9
SFR Information (9)
Address
00240h
00241h
00242h
00243h
00244h
00245h
00246h
00247h
00248h
00249h
0024Ah
0024Bh
0024Ch
0024Dh
0024Eh
0024Fh
00250h
00251h
00252h FST
00253h
Symbol
Register Name
After Reset
Remarks
Flash Memory Status Register
10000X00b
00254h FMR0
00255h FMR1
00256h FMR2
00257h
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
00h
00h
00h
00258h
00259h
0025Ah
0025Bh
0025Ch
0025Dh
0025Eh
0025Fh
00260h AIADR0L
00261h
Address Match Interrupt Address 0L Register
XXXXh
00262h AIADR0H
00263h AIEN0
00264h AIADR1L
00265h
Address Match Interrupt Address 0H Register
Address Match Interrupt Enable 0 Register
Address Match Interrupt Address 1L Register
0000XXXXb
00h
XXXXh
00266h AIADR1H
00267h AIEN1
00268h
Address Match Interrupt Address 1H Register
Address Match Interrupt Enable 1 Register
0000XXXXb
00h
00269h
0026Ah
0026Bh
0026Ch
0026Dh
0026Eh
0026Fh
00270h
00271h
00272h
00273h
00274h
00275h
00276h
00277h
00278h
00279h
0027Ah
0027Bh
0027Ch
0027Dh
0027Eh
0027Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 38 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.10
SFR Information (10)
Address
00280h DTCTL
00281h
Symbol
Register Name
DTC Activation Control Register
After Reset
Remarks
00h
00282h
00283h
00284h
00285h
00286h
00287h
00288h DTCEN0
00289h DTCEN1
0028Ah DTCEN2
0028Bh DTCEN3
0028Ch DTCEN4
0028Dh DTCEN5
0028Eh DTCEN6
0028Fh
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
00h
00h
00h
00h
00h
00h
00h
00290h CRCSAR
00291h
00292h CRCMR
00293h
00294h CRCD
00295h
00296h CRCIN
00297h
SFR Snoop Address Register
CRC Control Register
CRC Data Register
0000h
00h
0000h
00h
CRC Input Register
00298h
00299h
0029Ah
0029Bh
0029Ch
0029Dh
0029Eh
0029Fh
002A0h TRJ_0SR
002A1h TRJ_1SR
002A2h
Timer RJ_0 Pin Select Register
Timer RJ_1 Pin Select Register
00h
00h
002A3h
002A4h TRBSR
002A5h TRCCLKSR
002A6h TRC_0SR0
002A7h TRC_0SR1
002A8h
Timer RB2 Pin Select Register
Timer RCCLK Pin Select Register
Timer RC_0 Pin Select Register 0
Timer RC_0 Pin Select Register 1
00h
00h
00h
00h
002A9h TRD_0SR0
002AAh TRD_0SR1
002ABh
Timer RD_0 Pin Select Register 0
Timer RD_0 Pin Select Register 1
00h
00h
002ACh
002ADh TIMSR
002AEh U_0SR
002AFh U_1SR
002B0h
Timer Pin Select Register
UART0_0 Pin Select Register
UART0_1 Pin Select Register
00h
00h
00h
002B1h
002B2h U2SR0
002B3h U2SR1
002B4h SSUIIC_0SR
002B5h
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC_0 Pin Select Register
00h
00h
00h
002B6h INTSR0
002B7h
002B8h
002B9h PINSR
002BAh
INT Interrupt Input Pin Select Register 0
I/O Function Pin Select Register
00h
00h
002BBh
002BCh
002BDh
002BEh PMCSEL
002BFh
Pin Assignment Select Register
00h
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 39 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.11
SFR Information (11)
Address
Symbol
Register Name
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
After Reset
Remarks
002C0h PUR0
002C1h PUR1
002C2h PUR2
002C3h
00h
00h
00h
002C4h
002C5h
002C6h
002C7h
002C8h P1DRR
002C9h P2DRR
002CAh
Port P1 Drive Capacity Control Register
Port P2 Drive Capacity Control Register
00h
00h
002CBh
002CCh DRR0
002CDh DRR1
002CEh DRR2
002CFh
Drive Capacity Control Register 0
Drive Capacity Control Register 1
Drive Capacity Control Register 2
00h
00h
00h
002D0h VLT0
002D1h VLT1
002D2h VLT2
002D3h
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
00h
00h
00h
002D4h
002D5h
002D6h
002D7h
002D8h
002D9h
002DAh
002DBh
002DCh
002DDh
002DEh
002DFh
002E0h PORT0
002E1h PORT1
002E2h PD0
002E3h PD1
002E4h PORT2
002E5h PORT3
002E6h PD2
002E7h PD3
002E8h PORT4
002E9h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
002EAh PD4
002EBh
002ECh PORT6
002EDh
002EEh PD6
002EFh
Port P4 Direction Register
Port P6 Register
00h
XXh
00h
Port P6 Direction Register
002F0h
002F1h PORT9
002F2h
002F3h PD9
002F4h
Port P9 Register
XXh
00h
Port P9 Direction Register
002F5h
002F6h
002F7h
002F8h
002F9h
002FAh
002FBh
002FCh
002FDh
002FEh
002FFh
00300h On-chip RAM for On-chip RAM for firmware
to
firmware
003FFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 40 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.12
SFR Information (12)
Address
Symbol
Register Name
After Reset
Remarks
00400h On-chip RAM
to
On-chip RAM
02BFFh
02C00h
to
069FFh
06A00h ELSELR0
06A01h ELSELR1
06A02h ELSELR2
06A03h ELSELR3
06A04h ELSELR4
06A05h
Event Output Destination Select Register 0
Event Output Destination Select Register 1
Event Output Destination Select Register 2
Event Output Destination Select Register 3
Event Output Destination Select Register 4
00h
00h
00h
00h
00h
06A06h
06A07h
06A08h ELSELR8
06A09h ELSELR9
06A0Ah ELSELR10
06A0Bh ELSELR11
06A0Ch ELSELR12
06A0Dh ELSELR13
06A0Eh ELSELR14
06A0Fh ELSELR15
06A10h ELSELR16
06A11h ELSELR17
06A12h ELSELR18
06A13h ELSELR19
06A14h ELSELR20
06A15h ELSELR21
06A16h ELSELR22
06A17h ELSELR23
06A18h ELSELR24
06A19h
Event Output Destination Select Register 8
Event Output Destination Select Register 9
Event Output Destination Select Register 10
Event Output Destination Select Register 11
Event Output Destination Select Register 12
Event Output Destination Select Register 13
Event Output Destination Select Register 14
Event Output Destination Select Register 15
Event Output Destination Select Register 16
Event Output Destination Select Register 17
Event Output Destination Select Register 18
Event Output Destination Select Register 19
Event Output Destination Select Register 20
Event Output Destination Select Register 21
Event Output Destination Select Register 22
Event Output Destination Select Register 23
Event Output Destination Select Register 24
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
06A1Ah
06A1Bh
06A1Ch
06A1Dh
06A1Eh
06A1Fh
06A20h
06A21h
06A22h
06A23h
06A24h
06A25h
06A26h
06A27h
06A28h
06A29h
06A2Ah
06A2Bh
06A2Ch
06A2Dh
06A2Eh
06A2Fh
06A30h
06A31h
to
06BFFh
06C00h
06C01h
06C02h
06C03h
Area for storing DTC transfer vector 0
Area for storing DTC transfer vector 1
Area for storing DTC transfer vector 2
Area for storing DTC transfer vector 3
Area for storing DTC transfer vector 4
XXh
XXh
XXh
XXh
XXh
06C04h
06C05h
06C06h
06C07h
06C08h
06C09h
Area for storing DTC transfer vector 8
Area for storing DTC transfer vector 9
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 41 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.13
SFR Information (13)
Address
06C0Ah
06C0Bh
06C0Ch
06C0Dh
06C0Eh
06C0Fh
06C10h
06C11h
06C12h
06C13h
06C14h
06C15h
06C16h
06C17h
06C18h
06C19h
06C1Ah
06C1Bh
06C1Ch
06C1Dh
06C1Eh
06C1Fh
06C20h
06C21h
06C22h
06C23h
06C24h
06C25h
06C26h
06C27h
06C28h
06C29h
06C2Ah
06C2Bh
06C2Ch
06C2Dh
06C2Eh
06C2Fh
06C30h
06C31h
06C32h
06C33h
06C34h
06C35h
06C36h
06C37h
06C38h
06C39h
06C3Ah
06C3Bh
06C3Ch
06C3Dh
06C3Eh
06C3Fh
Symbol
Register Name
After Reset
Remarks
Area for storing DTC transfer vector 10
Area for storing DTC transfer vector 11
Area for storing DTC transfer vector 12
Area for storing DTC transfer vector 13
Area for storing DTC transfer vector 14
Area for storing DTC transfer vector 15
Area for storing DTC transfer vector 16
Area for storing DTC transfer vector 17
Area for storing DTC transfer vector 18
Area for storing DTC transfer vector 19
Area for storing DTC transfer vector 20
Area for storing DTC transfer vector 21
Area for storing DTC transfer vector 22
Area for storing DTC transfer vector 23
Area for storing DTC transfer vector 24
Area for storing DTC transfer vector 25
Area for storing DTC transfer vector 26
Area for storing DTC transfer vector 27
Area for storing DTC transfer vector 28
Area for storing DTC transfer vector 29
Area for storing DTC transfer vector 30
Area for storing DTC transfer vector 31
Area for storing DTC transfer vector 32
Area for storing DTC transfer vector 33
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Area for storing DTC transfer vector 38
Area for storing DTC transfer vector 39
XXh
XXh
Area for storing DTC transfer vector 42
XXh
Area for storing DTC transfer vector 49
Area for storing DTC transfer vector 50
Area for storing DTC transfer vector 51
Area for storing DTC transfer vector 52
XXh
XXh
XXh
XXh
06C40h DTCCR0
06C41h DTBLS0
06C42h DTCCT0
06C43h DTRLD0
06C44h DTSAR0
06C45h
DTC Control Register 0
DTC Block Size Register 0
DTC Transfer Count Register 0
DTC Transfer Count Reload Register 0
DTC Source Address Register 0
XXh
XXh
XXh
XXh
XXXXh
06C46h DTDAR0
06C47h
DTC Destination Address Register 0
XXXXh
06C48h DTCCR1
06C49h DTBLS1
X: Undefined
DTC Control Register 1
DTC Block Size Register 1
XXh
XXh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 42 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.14
SFR Information (14)
Address
Symbol
Register Name
DTC Transfer Count Register 1
DTC Transfer Count Reload Register 1
DTC Source Address Register 1
After Reset
Remarks
06C4Ah DTCCT1
06C4Bh DTRLD1
06C4Ch DTSAR1
06C4Dh
XXh
XXh
XXXXh
06C4Eh DTDAR1
06C4Fh
DTC Destination Address Register 1
XXXXh
06C50h DTCCR2
06C51h DTBLS2
06C52h DTCCT2
06C53h DTRLD2
06C54h DTSAR2
06C55h
DTC Control Register 2
DTC Block Size Register 2
DTC Transfer Count Register 2
DTC Transfer Count Reload Register 2
DTC Source Address Register 2
XXh
XXh
XXh
XXh
XXXXh
06C56h DTDAR2
06C57h
DTC Destination Address Register 2
XXXXh
06C58h DTCCR3
06C59h DTBLS3
06C5Ah DTCCT3
06C5Bh DTRLD3
06C5Ch DTSAR3
06C5Dh
DTC Control Register 3
DTC Block Size Register 3
DTC Transfer Count Register 3
DTC Transfer Count Reload Register 3
DTC Source Address Register 3
XXh
XXh
XXh
XXh
XXXXh
06C5Eh DTDAR3
06C5Fh
DTC Destination Address Register 3
XXXXh
06C60h DTCCR4
06C61h DTBLS4
06C62h DTCCT4
06C63h DTRLD4
06C64h DTSAR4
06C65h
DTC Control Register 4
DTC Block Size Register 4
DTC Transfer Count Register 4
DTC Transfer Count Reload Register 4
DTC Source Address Register 4
XXh
XXh
XXh
XXh
XXXXh
06C66h DTDAR4
06C67h
DTC Destination Address Register 4
XXXXh
06C68h DTCCR5
06C69h DTBLS5
06C6Ah DTCCT5
06C6Bh DTRLD5
06C6Ch DTSAR5
06C6Dh
DTC Control Register 5
DTC Block Size Register 5
DTC Transfer Count Register 5
DTC Transfer Count Reload Register 5
DTC Source Address Register 5
XXh
XXh
XXh
XXh
XXXXh
06C6Eh DTDAR5
06C6Fh
DTC Destination Address Register 5
XXXXh
06C70h DTCCR6
06C71h DTBLS6
06C72h DTCCT6
06C73h DTRLD6
06C74h DTSAR6
06C75h
DTC Control Register 6
DTC Block Size Register 6
DTC Transfer Count Register 6
DTC Transfer Count Reload Register 6
DTC Source Address Register 6
XXh
XXh
XXh
XXh
XXXXh
06C76h DTDAR6
06C77h
DTC Destination Address Register 6
XXXXh
06C78h DTCCR7
06C79h DTBLS7
06C7Ah DTCCT7
06C7Bh DTRLD7
06C7Ch DTSAR7
06C7Dh
DTC Control Register 7
DTC Block Size Register 7
DTC Transfer Count Register 7
DTC Transfer Count Reload Register 7
DTC Source Address Register 7
XXh
XXh
XXh
XXh
XXXXh
06C7Eh DTDAR7
06C7Fh
DTC Destination Address Register 7
XXXXh
06C80h DTCCR8
06C81h DTBLS8
06C82h DTCCT8
06C83h DTRLD8
06C84h DTSAR8
06C85h
DTC Control Register 8
DTC Block Size Register 8
DTC Transfer Count Register 8
DTC Transfer Count Reload Register 8
DTC Source Address Register 8
XXh
XXh
XXh
XXh
XXXXh
06C86h DTDAR8
06C87h
DTC Destination Address Register 8
XXXXh
06C88h DTCCR9
06C89h DTBLS9
06C8Ah DTCCT9
06C8Bh DTRLD9
06C8Ch DTSAR9
06C8Dh
DTC Control Register 9
DTC Block Size Register 9
DTC Transfer Count Register 9
DTC Transfer Count Reload Register 9
DTC Source Address Register 9
XXh
XXh
XXh
XXh
XXXXh
06C8Eh DTDAR9
06C8Fh
DTC Destination Address Register 9
XXXXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 43 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.15
SFR Information (15)
Address
Symbol
Register Name
After Reset
Remarks
06C90h DTCCR10
06C91h DTBLS10
06C92h DTCCT10
06C93h DTRLD10
06C94h DTSAR10
06C95h
DTC Control Register 10
DTC Block Size Register 10
DTC Transfer Count Register 10
DTC Transfer Count Reload Register 10
DTC Source Address Register 10
XXh
XXh
XXh
XXh
XXXXh
06C96h DTDAR10
06C97h
DTC Destination Address Register 10
XXXXh
06C98h DTCCR11
06C99h DTBLS11
06C9Ah DTCCT11
06C9Bh DTRLD11
06C9Ch DTSAR11
06C9Dh
DTC Control Register 11
DTC Block Size Register 11
DTC Transfer Count Register 11
DTC Transfer Count Reload Register 11
DTC Source Address Register 11
XXh
XXh
XXh
XXh
XXXXh
06C9Eh DTDAR11
06C9Fh
DTC Destination Address Register 11
XXXXh
06CA0h DTCCR12
06CA1h DTBLS12
06CA2h DTCCT12
06CA3h DTRLD12
06CA4h DTSAR12
06CA5h
DTC Control Register 12
DTC Block Size Register 12
DTC Transfer Count Register 12
DTC Transfer Count Reload Register 12
DTC Source Address Register 12
XXh
XXh
XXh
XXh
XXXXh
06CA6h DTDAR12
06CA7h
DTC Destination Address Register 12
XXXXh
06CA8h DTCCR13
06CA9h DTBLS13
06CAAh DTCCT13
06CABh DTRLD13
06CACh DTSAR13
06CADh
DTC Control Register 13
DTC Block Size Register 13
DTC Transfer Count Register 13
DTC Transfer Count Reload Register 13
DTC Source Address Register 13
XXh
XXh
XXh
XXh
XXXXh
06CAEh DTDAR13
06CAFh
DTC Destination Address Register 13
XXXXh
06CB0h DTCCR14
06CB1h DTBLS14
06CB2h DTCCT14
06CB3h DTRLD14
06CB4h DTSAR14
06CB5h
DTC Control Register 14
DTC Block Size Register 14
DTC Transfer Count Register 14
DTC Transfer Count Reload Register 14
DTC Source Address Register 14
XXh
XXh
XXh
XXh
XXXXh
06CB6h DTDAR14
06CB7h
DTC Destination Address Register 14
XXXXh
06CB8h DTCCR15
06CB9h DTBLS15
06CBAh DTCCT15
06CBBh DTRLD15
06CBCh DTSAR15
06CBDh
DTC Control Register 15
DTC Block Size Register 15
DTC Transfer Count Register 15
DTC Transfer Count Reload Register 15
DTC Source Address Register 15
XXh
XXh
XXh
XXh
XXXXh
06CBEh DTDAR15
06CBFh
DTC Destination Address Register 15
XXXXh
06CC0h DTCCR16
06CC1h DTBLS16
06CC2h DTCCT16
06CC3h DTRLD16
06CC4h DTSAR16
06CC5h
DTC Control Register 16
DTC Block Size Register 16
DTC Transfer Count Register 16
DTC Transfer Count Reload Register 16
DTC Source Address Register 16
XXh
XXh
XXh
XXh
XXXXh
06CC6h DTDAR16
06CC7h
DTC Destination Address Register 16
XXXXh
06CC8h DTCCR17
06CC9h DTBLS17
06CCAh DTCCT17
06CCBh DTRLD17
06CCCh DTSAR17
06CCDh
DTC Control Register 17
DTC Block Size Register 17
DTC Transfer Count Register 17
DTC Transfer Count Reload Register 17
DTC Source Address Register 17
XXh
XXh
XXh
XXh
XXXXh
06CCEh DTDAR17
06CCFh
DTC Destination Address Register 17
XXXXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 44 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.16
SFR Information (16)
Address
Symbol
Register Name
After Reset
Remarks
06CD0h DTCCR18
06CD1h DTBLS18
06CD2h DTCCT18
06CD3h DTRLD18
06CD4h DTSAR18
06CD5h
DTC Control Register 18
DTC Block Size Register 18
DTC Transfer Count Register 18
DTC Transfer Count Reload Register 18
DTC Source Address Register 18
XXh
XXh
XXh
XXh
XXXXh
06CD6h DTDAR18
06CD7h
DTC Destination Address Register 18
XXXXh
06CD8h DTCCR19
06CD9h DTBLS19
06CDAh DTCCT19
06CDBh DTRLD19
06CDCh DTSAR19
06CDDh
DTC Control Register 19
DTC Block Size Register 19
DTC Transfer Count Register 19
DTC Transfer Count Reload Register 19
DTC Source Address Register 19
XXh
XXh
XXh
XXh
XXXXh
06CDEh DTDAR19
06CDFh
DTC Destination Address Register 19
XXXXh
06CE0h DTCCR20
06CE1h DTBLS20
06CE2h DTCCT20
06CE3h DTRLD20
06CE4h DTSAR20
06CE5h
DTC Control Register 20
DTC Block Size Register 20
DTC Transfer Count Register 20
DTC Transfer Count Reload Register 20
DTC Source Address Register 20
XXh
XXh
XXh
XXh
XXXXh
06CE6h DTDAR20
06CE7h
DTC Destination Address Register 20
XXXXh
06CE8h DTCCR21
06CE9h DTBLS21
06CEAh DTCCT21
06CEBh DTRLD21
06CECh DTSAR21
06CEDh
DTC Control Register 21
DTC Block Size Register 21
DTC Transfer Count Register 21
DTC Transfer Count Reload Register 21
DTC Source Address Register 21
XXh
XXh
XXh
XXh
XXXXh
06CEEh DTDAR21
06CEFh
DTC Destination Address Register 21
XXXXh
06CF0h DTCCR22
06CF1h DTBLS22
06CF2h DTCCT22
06CF3h DTRLD22
06CF4h DTSAR22
06CF5h
DTC Control Register 22
DTC Block Size Register 22
DTC Transfer Count Register 22
DTC Transfer Count Reload Register 22
DTC Source Address Register 22
XXh
XXh
XXh
XXh
XXXXh
06CF6h DTDAR22
06CF7h
DTC Destination Address Register 22
XXXXh
06CF8h DTCCR23
06CF9h DTBLS23
06CFAh DTCCT23
06CFBh DTRLD23
06CFCh DTSAR23
06CFDh
DTC Control Register 23
DTC Block Size Register 23
DTC Transfer Count Register 23
DTC Transfer Count Reload Register 23
DTC Source Address Register 23
XXh
XXh
XXh
XXh
XXXXh
06CFEh DTDAR23
06CFFh
DTC Destination Address Register 23
XXXXh
06D00h
to
06DFFh
06E00h CMB0_0
06E01h
06E02h
06E03h
06E04h
06E05h
06E06h
06E07h
06E08h
06E09h
06E0Ah
06E0Bh
06E0Ch
06E0Dh
06E0Eh
06E0Fh
CAN_0 Mailbox 0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 45 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.17
SFR Information (17)
Address
Symbol
Register Name
After Reset
Remarks
06E10h CMB1_0
06E11h
06E12h
06E13h
06E14h
06E15h
06E16h
06E17h
06E18h
CAN_0 Mailbox 1
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
06E19h
06E1Ah
06E1Bh
06E1Ch
06E1Dh
06E1Eh
06E1Fh
06E20h CMB2_0
06E21h
06E22h
06E23h
06E24h
06E25h
06E26h
06E27h
06E28h
06E29h
06E2Ah
06E2Bh
06E2Ch
06E2Dh
06E2Eh
06E2Fh
06E30h CMB3_0
06E31h
06E32h
06E33h
06E34h
06E35h
06E36h
06E37h
06E38h
06E39h
06E3Ah
06E3Bh
06E3Ch
06E3Dh
06E3Eh
06E3Fh
06E40h CMB4_0
06E41h
06E42h
06E43h
06E44h
06E45h
CAN_0 Mailbox 2
CAN_0 Mailbox 3
CAN_0 Mailbox 4
06E46h
06E47h
06E48h
06E49h
06E4Ah
06E4Bh
06E4Ch
06E4Dh
06E4Eh
06E4Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 46 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.18
SFR Information (18)
Address
Symbol
Register Name
After Reset
Remarks
06E50h CMB5_0
06E51h
06E52h
06E53h
06E54h
06E55h
06E56h
06E57h
06E58h
CAN_0 Mailbox 5
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
06E59h
06E5Ah
06E5Bh
06E5Ch
06E5Dh
06E5Eh
06E5Fh
06E60h CMB6_0
06E61h
06E62h
06E63h
06E64h
06E65h
06E66h
06E67h
06E68h
06E69h
06E6Ah
06E6Bh
06E6Ch
06E6Dh
06E6Eh
06E6Fh
06E70h CMB7_0
06E71h
06E72h
06E73h
06E74h
06E75h
06E76h
06E77h
06E78h
06E79h
06E7Ah
06E7Bh
06E7Ch
06E7Dh
06E7Eh
06E7Fh
06E80h CMB8_0
06E81h
06E82h
06E83h
06E84h
06E85h
CAN_0 Mailbox 6
CAN_0 Mailbox 7
CAN_0 Mailbox 8
06E86h
06E87h
06E88h
06E89h
06E8Ah
06E8Bh
06E8Ch
06E8Dh
06E8Eh
06E8Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 47 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.19
SFR Information (19)
Address
Symbol
Register Name
After Reset
Remarks
06E90h CMB9_0
06E91h
06E92h
06E93h
06E94h
06E95h
06E96h
06E97h
06E98h
CAN_0 Mailbox 9
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
06E99h
06E9Ah
06E9Bh
06E9Ch
06E9Dh
06E9Eh
06E9Fh
06EA0h CMB10_0
06EA1h
06EA2h
06EA3h
06EA4h
06EA5h
06EA6h
CAN_0 Mailbox 10
CAN_0 Mailbox 11
CAN_0 Mailbox 12
06EA7h
06EA8h
06EA9h
06EAAh
06EABh
06EACh
06EADh
06EAEh
06EAFh
06EB0h CMB11_0
06EB1h
06EB2h
06EB3h
06EB4h
06EB5h
06EB6h
06EB7h
06EB8h
06EB9h
06EBAh
06EBBh
06EBCh
06EBDh
06EBEh
06EBFh
06EC0h CMB12_0
06EC1h
06EC2h
06EC3h
06EC4h
06EC5h
06EC6h
06EC7h
06EC8h
06EC9h
06ECAh
06ECBh
06ECCh
06ECDh
06ECEh
06ECFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 48 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.20
SFR Information (20)
Address
Symbol
Register Name
After Reset
Remarks
06ED0h CMB13_0
06ED1h
06ED2h
06ED3h
06ED4h
06ED5h
06ED6h
06ED7h
06ED8h
06ED9h
06EDAh
06EDBh
06EDCh
06EDDh
06EDEh
06EDFh
06EE0h CMB14_0
06EE1h
06EE2h
06EE3h
06EE4h
06EE5h
06EE6h
06EE7h
06EE8h
06EE9h
06EEAh
06EEBh
06EECh
06EEDh
06EEEh
06EEFh
06EF0h CMB15_0
06EF1h
06EF2h
06EF3h
06EF4h
06EF5h
06EF6h
06EF7h
06EF8h
06EF9h
06EFAh
06EFBh
06EFCh
06EFDh
06EFEh
06EFFh
06F00h
CAN_0 Mailbox 13
CAN_0 Mailbox 14
CAN_0 Mailbox 15
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
06F01h
06F02h
06F03h
06F04h
06F05h
06F06h
06F07h
06F08h
06F09h
06F0Ah
06F0Bh
06F0Ch
06F0Dh
06F0Eh
06F0Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 49 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.21
SFR Information (21)
Address
Symbol
Register Name
After Reset
Remarks
06F10h CMKR0_0
06F11h
06F12h
06F13h
06F14h CMKR1_0
06F15h
06F16h
06F17h
06F18h CMKR2_0
06F19h
06F1Ah
06F1Bh
06F1Ch CMKR3_0
06F1Dh
06F1Eh
06F1Fh
06F20h CFIDCR0_0
06F21h
06F22h
06F23h
06F24h CFIDCR1_0
06F25h
CAN_0 Mask Register 0
CAN_0 Mask Register 1
CAN_0 Mask Register 2
CAN_0 Mask Register 3
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN_0 FIFO Received ID Compare Register 0
CAN_0 FIFO Received ID Compare Register 1
06F26h
06F27h
06F28h
06F29h
06F2Ah CMKIVLR_0
06F2Bh
CAN_0 Mask Invalid Register
XXh
XXh
06F2Ch
06F2Dh
06F2Eh CMIER_0
06F2Fh
CAN_0 Mailbox Interrupt Enable Register
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
06F30h CMCTL0_0
06F31h CMCTL1_0
06F32h CMCTL2_0
06F33h CMCTL3_0
06F34h CMCTL4_0
06F35h CMCTL5_0
06F36h CMCTL6_0
06F37h CMCTL7_0
06F38h CMCTL8_0
06F39h CMCTL9_0
06F3Ah CMCTL10_0
06F3Bh CMCTL11_0
06F3Ch CMCTL12_0
06F3Dh CMCTL13_0
06F3Eh CMCTL14_0
06F3Fh CMCTL15_0
06F40h CCTLR_0
06F41h
CAN_0 Message Control Register 0
CAN_0 Message Control Register 1
CAN_0 Message Control Register 2
CAN_0 Message Control Register 3
CAN_0 Message Control Register 4
CAN_0 Message Control Register 5
CAN_0 Message Control Register 6
CAN_0 Message Control Register 7
CAN_0 Message Control Register 8
CAN_0 Message Control Register 9
CAN_0 Message Control Register 10
CAN_0 Message Control Register 11
CAN_0 Message Control Register 12
CAN_0 Message Control Register 13
CAN_0 Message Control Register 14
CAN_0 Message Control Register 15
CAN_0 Control Register
00000101b
00h
06F42h CSTR_0
06F43h
CAN_0 Status Register
00000101b
00h
06F44h CBCR_0
06F45h
CAN_0 Bit Configuration Register
00h
00h
06F46h
00h
06F47h CCLKR_0
06F48h CRFCR_0
06F49h CRFPCR_0
06F4Ah CTFCR_0
06F4Bh CTFPCR_0
06F4Ch CEIER_0
06F4Dh CEIFR_0
06F4Eh CRECR_0
06F4Fh CTECR_0
X: Undefined
CAN_0 Clock Select Register
00h
10000000b
XXh
10000000b
XXh
00h
00h
00h
00h
CAN_0 Receive FIFO Control Register
CAN_0 Receive FIFO Pointer Control Register
CAN_0 Transmit FIFO Control Register
CAN_0 Transmit FIFO Pointer Control Register
CAN_0 Error Interrupt Enable Register
CAN_0 Error Interrupt Factor Judge Register
CAN_0 Receive Error Count Register
CAN_0 Transmit Error Count Register
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 50 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3. Address Space
(1)
Table 3.22
SFR Information (22)
Address
Symbol
Register Name
CAN_0 Error Code Store Register
CAN_0 Channel Search Support Register
CAN_0 Mailbox Search Status Register
CAN_0 Mailbox Search Mode Register
CAN_0 Time Stamp Register
After Reset
Remarks
06F50h CECSR_0
06F51h CCSSR_0
06F52h CMSSR_0
06F53h CMSMR_0
06F54h CTSR_0
06F55h
00h
XXh
10000000b
00h
0000h
06F56h CAFSR_0
06F57h
06F58h CTCR_0
06F59h
CAN_0 Acceptance Filter Support Register
CAN_0 Test Control Register
XXh
XXh
00h
06F5Ah
06F5Bh
06F5Ch
06F5Dh
06F5Eh
06F5Fh
06F60h
06F61h
06F62h
06F63h
06F64h
06F65h
06F66h
06F67h
06F68h
06F69h
06F6Ah
06F6Bh
06F6Ch
06F6Dh
06F6Eh
06F6Fh
06F70h
06F71h
06F72h
06F73h
06F74h
06F75h
06F76h
06F77h
06F78h
06F79h
06F7Ah
06F7Bh
06F7Ch
06F7Dh
06F7Eh CANISR_0
06F7Fh CANIE_0
06F80h
CAN_0 Interrupt Status Register
CAN_0 Interrupt Control Register
00h
00h
to
06FFFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
Table 3.23
ID code Area, Option Function Select Area
Address
:
0FFDBh OFS2
Symbol
Area Name
Option Function Select Register 2
Option Function Select Register
After Reset
Address size
:
0FFFFh OFS
Note:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not perform any additional writes to the option function select area. Erasure of the block including the option function select area will cause
the option function select area to be set to FFh.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 51 of 52
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
37
24
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
6.9 7.0 7.1
6.9 7.0 7.1
1.4
Terminal cross section
48
13
A2
HD
HE
A
8.8 9.0 9.2
8.8 9.0 9.2
1.7
1
12
Index mark
ZD
A1
bp
b1
c
0
0.1 0.2
0.17 0.22 0.27
0.20
F
0.145
0.125
0.09
0.20
S
L
c1
L1
0°
8°
e
0.5
y
S
*3
x
Detail F
0.08
0.10
bp
e
x
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 52 of 52
REVISION HISTORY
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group Datasheet
Description
Summary
Rev.
Date
Page
—
0.01
0.10
Dec 17, 2010
Mar 15, 2011
First Edition issued
1 to 22
27 to 29
40
1. Overview R8C/54F Group, R8C/54G Group, and R8C/54H Group added
3.2, 3.3, and 3.4 added
Table 3.11 Port register symbol revised
All trademarks and registered trademarks are the property of their respective owners.
C - 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
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The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
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personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
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8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
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please evaluate the safety of the final products or system manufactured by you.
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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