R5F2L368CDFP#U0 [RENESAS]
IC,MICROCONTROLLER,16-BIT,R8C CPU,CMOS,QFP,64PIN,PLASTIC;型号: | R5F2L368CDFP#U0 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | IC,MICROCONTROLLER,16-BIT,R8C CPU,CMOS,QFP,64PIN,PLASTIC |
文件: | 总75页 (文件大小:846K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
RENESAS MCU
R01DS0095EJ0101
Rev.1.01
Apr 15, 2011
1. Overview
1.1
Features
The R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, and R8C/L3AC Group of single-chip MCUs
incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and
supports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, the CPU core
integrates a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the
number of system components.
These groups have data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Household appliances, office equipment, audio equipment, consumer products, etc.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 1 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.1.2
Differences between Groups
Table 1.1 lists the Differences between Groups, Table 1.2 lists the Programmable I/O Ports Provided for Each
Group, and Table 1.3 lists the LCD Display Function Pins Provided for Each Group. Figures 1.9 to 1.13 show
the Pin Assignment for Each Group, and Tables 1.7 to 1.10 list Product Information.
The explanations in the chapters which follow apply to the R8C/L3AC Group only. Note the differences shown
below.
Table 1.1
Differences between Groups
Item
Function
R8C/L35C Group
R8C/L36C Group
52 pins
R8C/L38C Group
68 pins
R8C/L3AC Group
88 pins
I/O Ports
Programmable I/O ports
High current drive ports
41 pins
5 pins
8 pins
8 pins
16 pins
Interrupts
INT interrupt pins
5 pins
4 pins
None
None
None
None
None
None
10 pins
8 pins
4 pins
1 pin
8 pins
8 pins
1 pin
8 pins
8 pins
1 pin
Key input interrupt pins
Timer RA output pin
Timer RB output pin
Timer RD I/O pin
Timer RA
Timer RB
Timer RD
Timer RE
Timer RG
1 pin
1 pin
1 pin
None
1 pin
8 pins
1 pin
8 pins
1 pin
Timer RE output pin
Timer RG I/O pin
None
None
10 pins
None
None
16 pins
2 pins
2 pins
20 pins
Timer RG output pin
A/D Converter Analog input pin
LCD Drive
LCD power supply
3 pins
4 pins
4 pins
4 pins
Control Circuit
(VL1, VL2, VL4)
(VL1 to VL4)
(VL1 to VL4)
(VL1 to VL4)
Common output pins
Segment output pins
Max. 4 pins
Max. 24 pins
52-pin LQFP
Max. 8 pins
Max. 32 pins
64-pin LQFP
Max. 8 pins
Max. 48 pins
80-pin LQFP
Max. 8 pins
Max. 56 pins
Packages
Note:
100-pin LQFP/
100-pin QFP
1. I/O ports are shared with I/O functions, such as interrupts or timers.
Refer to Tables 1.11 to 1.13, Pin Name Information by Pin Number, for details.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 2 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.2
Programmable I/O Ports Provided for Each Group
R8C/L35C Group
Total: 41 I/O pins
R8C/L36C Group
Total: 52 I/O pins
R8C/L38C Group
Total: 68 I/O pins
R8C/L3AC Group
Total: 88 I/O pins
Programmable
I/O Port
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P0
−
3
−
−
3
−
−
3
−
−
3
−
−
−
−
−
−
−
−
−
−
3
3
3
−
−
3
3
3
−
−
3
3
3
−
−
3
3
3
−
−
−
−
−
−
−
−
−
−
3
3
3
−
−
3
3
3
−
−
3
3
3
−
−
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P1
P2
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
P3
3
−
3
−
3
−
3
−
P4
P5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
3
3
3
3
−
P6
3
−
3
−
3
−
3
−
−
−
−
−
3
−
3
−
3
−
3
−
3
−
3
−
3
−
3
−
P7
−
−
−
−
P10
P11
P12
P13
−
−
−
3
−
3
3
3
3
3
3
3
3
3
3
3
3
3
−
3
−
3
−
3
−
3
3
3
3
3
3
3
3
3
3
3
3
3
−
3
−
3
−
3
−
3
3
3
3
3
3
3
3
3
3
3
3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
3
3
Notes:
1. The symbol “3” indicates a programmable I/O port.
2. The symbol “−” indicates the settings should be made as follows:
- Set 1 to the corresponding bits in the PDi (i = 1 to 3, 5 to 7, and 10 to 13) register.
- Set 0 to the corresponding bits in the Pi (i = 1 to 3, 5 to 7, and 10 to 13) register.
- Set 0 to the corresponding bits in the P10DRR or P11DRR register.
Table 1.3
LCD Display Function Pins Provided for Each Group
L35C Group
Common output: Max. 4
Segment output: Max. 24
L36C Group
Common output: Max. 8
Segment output: Max. 32
L38C Group
Common output: Max. 8
Segment output: Max. 48
L3AC Group
Common output: Max. 8
Segment output: Max. 56
Shared
I/O Port
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
P0
P1
P2
P3
P4
P5
P6
P7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
11 10 15 14 13 12 11 10
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
9
8
9
8
SEG SEG SEG SEG
SEG SEG SEG SEG
23 22 21 20
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
23 22 21 20 19 18 17 16 23 22 21 20 19 18 17 16
−
−
−
−
−
−
−
−
23
22
21
20
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
27 26 25 24 31 30 29 28 27 26 25 24 31 30 29 28 27 26 25 24 31 30 29 28 27 26 25 24
−
−
−
−
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
39
38
37
36
35
SEG SEG SEG SEG
43 42 41 40
34
33
32
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
51 50 49 48 47 46 45 44 51 50 49 48 47 46 45 44
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
COM COM COM COM
0
COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG
−
−
−
−
1
2
3
0
1
2
3
55
54
53
52
0
1
2
3
55
54
53
52
0
1
2
3
55
54
53
52
−
−
−
−
CL2 CL1
−
−
−
−
CL2 CL1
−
−
−
−
−
−
CL2 CL1
−
−
−
−
−
−
CL2 CL1
−
−
P12
−
VL1
VL1
VL1
VL1
−
VL2
−
VL2
VL3
VL4
VL2
VL3
VL4
VL2
VL3
VL4
−
−
VL4
Notes:
1. The symbol “−” indicates there is no LCD display function. Set the corresponding bits in registers LSE1 to LSE3, LSE5 to
LSE7 to 0 for these pins.
2. SEG52 to SEG55 can be used as COM7 to COM4.
The R8C/L35C Group does not have pins SEG52 to SEG55, so 1/8 duty cannot be selected.
3. The R8C/L35C Group does not have the VL3 pin, so 1/4 bias cannot be selected. When the internal voltage multiplier is
used, 1/2 bias cannot also be selected.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 3 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.1.3
Specifications
Tables 1.4 to 1.6 list the Specifications.
Table 1.4
Specifications (1)
Item
CPU
Function
Central processing unit
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Refer to Tables 1.7 to 1.10 Product Lists.
Memory
ROM/RAM
Data flash
Power
Voltage detection circuit
• Power-on reset
Supply
Voltage
Detection
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
I/O Ports Programmable R8C/L35C Group • CMOS I/O ports: 41, selectable pull-up resistor
I/O ports
• High current drive ports: 5
R8C/L36C Group • CMOS I/O ports: 52, selectable pull-up resistor
• High current drive ports: 8
R8C/L38C Group • CMOS I/O ports: 68, selectable pull-up resistor
• High current drive ports: 8
R8C/L3AC Group • CMOS I/O ports: 88, selectable pull-up resistor
• High current drive ports: 16
Clock
Clock generation circuits
4 circuits: XIN clock oscillation circuit
XCIN clock oscillation circuit (32 kHz)
High-speed on-chip oscillator (with frequency adjustment function)
Low-speed on-chip oscillator
• Oscillation stop detection:
XIN clock oscillation stop detection function
• Frequency divider circuit:
Division ratio selectable from 1, 2, 4, 8, and 16
• Low-power-consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-
speed on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode, power-off mode
Real-time clock (timer RE)
Interrupts
R8C/L35C Group • Number of interrupt vectors: 69
• External Interrupt: 9 (INT × 5, key input × 4)
• Priority levels: 7 levels
R8C/L36C Group • Number of interrupt vectors: 69
• External Interrupt: 12 (INT × 8, key input × 4)
• Priority levels: 7 levels
R8C/L38C Group • Number of interrupt vectors: 69
• External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels
R8C/L3AC Group • Number of interrupt vectors: 69
• External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels
Watchdog Timer
• 14 bits × 1 (with prescaler)
• Selectable reset start function
• Selectable low-speed on-chip oscillator for watchdog timer
• 1 channel
DTC (Data Transfer Controller)
• Activation sources: 38
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 4 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.5
Specifications (2)
Item
Timer
Function
Timer RA
Specification
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode,
pulse period measurement mode
Timer RB
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RD
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output:
6 pins, sawtooth wave modulation), complementary PWM mode (three-phase
waveform output: 6 pins, triangular wave modulation), PWM3 mode (PWM
output with fixed period: 2 pins)
Timer RE
Timer RG
8 bits × 1
Real-time clock mode (counting of seconds, minutes, hours, days of week),
output compare mode
16 bits × 1
Phase-counting mode,
timer mode (output compare function, input capture function),
PWM mode (output: 1 pin)
Serial
Interface
UART0, UART1
UART2
Clock synchronous serial I/O/UART × 2 channels
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),
multiprocessor communication function
1 (shared with I2C-bus)
Synchronous Serial
Communication Unit (SSU)
I2C bus
1 (shared with SSU)
LIN Module
Hardware LIN: 1 channel (timer RA, UART0 used)
A/D
Converter
R8C/L35C Group 10-bit resolution × 10 channels, including sample and hold function, with sweep
mode
R8C/L36C Group 10-bit resolution × 10 channels, including sample and hold function, with sweep
mode
R8C/L38C Group 10-bit resolution × 16 channels, including sample and hold function, with sweep
mode
R8C/L3AC Group 10-bit resolution × 20 channels, including sample and hold function, with sweep
mode
D/A Converter
Comparator B
LCD Drive
Control
8-bit resolution × 2 circuits
2 circuits
R8C/L35C Group Common output: Max. 4 pins
Bias: 1/2, 1/3
Duty: static, 1/2, 1/3, 1/4
Segment output: Max. 24 pins
R8C/L36C Group Common output: Max. 8 pins
Circuit
Segment output: Max. 32 pins (1)
R8C/L38C Group Common output: Max. 8 pins
Bias: 1/2, 1/3, 1/4
Segment output: Max. 48 pins (1)
Duty: static, 1/2, 1/3, 1/4, 1/8
R8C/L3AC Group Common output: Max. 8 pins
Segment output: Max. 56 pins (1)
Voltage multiplier and dedicated regulator integrated
Note:
1. This applies when four pins are selected for common output.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 5 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.6
Specifications (3)
Item
Specification
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
Flash Memory
• Program security: ROM code protect, ID code check
• On-chip debug function
• On-board flash rewrite function
• Background operation (BGO) function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Operating Frequency/
Supply Voltage
Current Consumption
Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2 µA (VCC = 3.0 V, stop mode)
Typ. 0.02 µA (VCC = 3.0 V, power-off mode)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
Operating Ambient Temperature
Note:
1. Specify the D version if D version functions are to be used.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 6 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.2
Product Lists
Tables 1.7 to 1.10 list Product List for Each Group. Figures 1.1 to 1.4 show the Correspondence of Part No., with
Memory Size and Package for Each Group.
Table 1.7
Product List for R8C/L35C Group
Current of Apr 2011
Internal ROM Capacity
Internal RAM
Capacity
Part No.
Package Type
Remarks
N Version
Program ROM
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F2L357CNFP
R5F2L358CNFP
R5F2L35ACNFP
R5F2L35CCNFP
R5F2L357CDFP
R5F2L358CDFP
R5F2L35ACDFP
R5F2L35CCDFP
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
D Version
Part No. R 5 F 2L 35 C C N FP
Package type:
FP: LQFP (0.65 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L35C Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Correspondence of Part No., with Memory Size and Package of R8C/L35C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 7 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.8
Product List for R8C/L36C Group
Current of Apr 2011
Internal ROM Capacity
Internal RAM
Capacity
Part No.
Package Type
Remarks
N Version
Program ROM
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F2L367CNFP
R5F2L367CNFA
R5F2L368CNFP
R5F2L368CNFA
R5F2L36ACNFP
R5F2L36ACNFA
R5F2L36CCNFP
R5F2L36CCNFA
R5F2L367CDFP
R5F2L367CDFA
R5F2L368CDFP
R5F2L368CDFA
R5F2L36ACDFP
R5F2L36ACDFA
R5F2L36CCDFP
R5F2L36CCDFA
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
D Version
Part No. R 5 F 2L 36 C C N FP
Package type:
FP: LQFP (0.50 mm pin pitch)
FA: LQFP (0.80 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L36C Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Correspondence of Part No., with Memory Size and Package of R8C/L36C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 8 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.9
Product List for R8C/L38C Group
Current of Apr 2011
Internal ROM Capacity
Internal RAM
Capacity
Part No.
Package Type
Remarks
N Version
Program ROM
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F2L387CNFP
R5F2L387CNFA
R5F2L388CNFP
R5F2L388CNFA
R5F2L38ACNFP
R5F2L38ACNFA
R5F2L38CCNFP
R5F2L38CCNFA
R5F2L387CDFP
R5F2L387CDFA
R5F2L388CDFP
R5F2L388CDFA
R5F2L38ACDFP
R5F2L38ACDFA
R5F2L38CCDFP
R5F2L38CCDFA
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
D Version
Part No. R 5 F 2L 38 C C N FP
Package type:
FP: LQFP (0.50 mm pin pitch)
FA: LQFP (0.65 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L38C Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Correspondence of Part No., with Memory Size and Package of R8C/L38C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 9 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.10
Product List for R8C/L3AC Group
Current of Apr 2011
Internal ROM Capacity
Internal RAM
Capacity
Part No.
Package Type
Remarks
N Version
Program ROM
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Data Flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F2L3A7CNFP
R5F2L3A7CNFA
R5F2L3A8CNFP
R5F2L3A8CNFA
R5F2L3AACNFP
R5F2L3AACNFA
R5F2L3ACCNFP
R5F2L3ACCNFA
R5F2L3A7CDFP
R5F2L3A7CDFA
R5F2L3A8CDFP
R5F2L3A8CDFA
R5F2L3AACDFP
R5F2L3AACDFA
R5F2L3ACCDFP
R5F2L3ACCDFA
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
D Version
Part No. R 5 F 2L 3A C C N FP
Package type:
FP: LQFP (0.50 mm pin pitch)
FA: QFP (0.65 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L3AC Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
Correspondence of Part No., with Memory Size and Package of R8C/L3AC Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 10 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.3
Block Diagrams
Figure 1.5 shows a Block Diagram of R8C/L35C Group. Figure 1.6 shows a Block Diagram of R8C/L36C Group.
Figure 1.7 shows a Block Diagram of R8C/L38C Group. Figure 1.8 shows a Block Diagram of R8C/L3AC Group.
8
4
4
8
Port P0
Port P2
I/O ports
Port P3
Port P4
Peripheral functions
System clock generation
UART or
circuit
Timers
clock synchronous serial I/O
(8 bits × 3)
XIN-XOUT
4
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
DTC
LIN module
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
5
LCD drive control circuit
A/D converter
(10 bits × 10 channels)
Common output: Max. 4 pins
Segment output: Max. 24 pins
Comparator B
4
4
D/A converter
Memory
R8C CPU core
(8 bits × 2 channels)
R0H
R1H
R2
R0L
R1L
SB
ROM (1)
USP
ISP
Voltage detection circuit
R3
RAM (2)
INTB
PC
A0
A1
FLG
FB
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.5
Block Diagram of R8C/L35C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 11 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
8
4
8
8
Port P0
Port P2
I/O ports
Port P3
Port P4
Peripheral functions
System clock generation
UART or
circuit
Timers
clock synchronous serial I/O
(8 bits × 3)
XIN-XOUT
8
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
DTC
LIN module
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
8
LCD drive control circuit
A/D converter
(10 bits × 10 channels)
Common output: Max. 8 pins
Segment output: Max. 32 pins
Comparator B
4
4
D/A converter
Memory
R8C CPU core
(8 bits × 2 channels)
R0H
R1H
R2
R0L
R1L
SB
ROM (1)
USP
ISP
Voltage detection circuit
R3
RAM (2)
INTB
PC
A0
A1
FLG
FB
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.6
Block Diagram of R8C/L36C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 12 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
8
4
8
8
8
8
Port P6
Port P0
Port P1
Port P2
I/O ports
Port P3
Port P4
Peripheral functions
System clock generation
UART or
circuit
Timers
clock synchronous serial I/O
(8 bits × 3)
XIN-XOUT
8
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
DTC
LIN module
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
8
LCD drive control circuit
A/D converter
(10 bits × 16 channels)
Common output: Max. 8 pins
Segment output: Max. 48 pins
Comparator B
4
4
D/A converter
Memory
R8C CPU core
(8 bits × 2 channels)
R0H
R1H
R2
R0L
R1L
SB
ROM (1)
USP
ISP
Voltage detection circuit
R3
RAM (2)
INTB
PC
A0
A1
FLG
FB
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.7
Block Diagram of R8C/L38C Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 13 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
8
8
8
8
4
8
8
Port P0
Port P1
Port P2
I/O ports
Port P3
Port P4
Port P5
Port P6
Peripheral functions
System clock generation
circuit
UART or
Timers
clock synchronous serial I/O
(8 bits × 3)
XIN-XOUT
8
8
8
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
DTC
LIN module
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
LCD drive control circuit
A/D converter
(10 bits × 20 channels)
Common output: Max. 8 pins
Segment output: Max. 56 pins
Comparator B
4
8
D/A converter
Memory
R8C CPU core
(8 bits × 2 channels)
R0H
R1H
R2
R0L
R1L
SB
ROM (1)
USP
ISP
Voltage detection circuit
R3
RAM (2)
INTB
PC
A0
A1
FLG
FB
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.8
Block Diagram of R8C/L3AC Group
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 14 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.4
Pin Assignments
Figures 1.9 to 1.13 show Pin Assignments (Top View). Tables 1.11 to 1.13 list the Pin Name Information by Pin
Number.
39 38 37 36 35 34 33 32 31 30 29 28 27
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
R8C/L35C Group
VL2
CL2/P12_3
CL1/P12_2
PLQP0052JA-A (52P6A-A)
(top view)
VL4
P13_3/AN3/CLK0
P13_2/AN2/RXD0
1
2
3
4
5
6
7
8
9 10 11 12 13
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.9
Pin Assignment (Top View) of PLQP0052JA-A Package
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 15 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
P4_2/SEG34/CLK1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
R8C/L36C Group
VL2
VL3
CL2/P12_3
CL1/P12_2
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
(top view)
VL4
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1
P13_3/AN3/CLK0
P13_2/AN2/RXD0
P13_1/AN1/DA1/TXD0
P13_0/AN0/DA0
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.10
Pin Assignment (Top View) of PLQP0064KB-A and PLQP0064GA-A Packages
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 16 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P2_0/SEG16/KI0
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1
62
63
64
65
66
67
68
69
R8C/L38C Group
P0_4/SEG4/AN8
70
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
71
72
PLQP0080KB-A (80P6Q-A)
PLQP0080JA-A (FP-80WV)
(top view)
73
74
VL1
VL2
VL3
75
76
77
24
23
22
21
CL2/P12_3
CL1/P12_2
VL4
78
79
80
P13_3/AN3/CLK0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.11
Pin Assignment (Top View) of PLQP0080KB-A and PLQP0080JA-A Packages
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 17 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P1_6/SEG14
P1_5/SEG13
P1_4/SEG12
P5_0/SEG40
P5_1/SEG41
P5_2/SEG42
P5_3/SEG43
77
78
79
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
80
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P10_0/(TRDIOA0/TRDCLK/KI0)
P10_1/(TRDIOB0/KI1)
P10_2/(TRDIOC0/KI2)
P10_3/(TRDIOD0/KI3)
P10_4/(TRDIOA1/KI4)
81
82
83
84
85
R8C/L3AC Group
86
87
88
89
90
91
VL1
VL2
PLQP0100KB-A (100P6Q-A)
92
93
(top view)
VL3
94
CL2/P12_3
CL1/P12_2
95
31
30
96
VL4
29
28
27
26
97
P13_7/AN19/TRGCLKB
P13_6/AN18/TRGIOB
P13_5/AN17/TRGCLKA
P13_4/AN16/TRGIOA
98
99
1
00
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.12
Pin Assignment (Top View) of PLQP0100KB-A Package
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 18 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72 71 70 69 68
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
P5_2/SEG42
P5_3/SEG43
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
R8C/L3AC Group
PRQP0100JD-B (100P6F-A)
(top view)
VL2
VL3
CL2/P12_3
CL1/P12_2
VL4
P13_7/AN19/TRGCLKB
P13_6/AN18/TRGIOB
P10_0/(TRDIOA0/TRDCLK/KI0)
P10_1/(TRDIOB0/KI1)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.13
Pin Assignment (Top View) of PRQP0100JD-B Package
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 19 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.11
Pin Name Information by Pin Number (1)
Pin Number
I/O Pin Functions for Peripheral Modules
Control
Pin
A/D Converter, LCD drive
2
Port
L3AC
(Note 2)
L38C L36C L35C
Serial
Interface
I C
Interrupt
Timer
SSU
D/A Converter,
Comparator B
AN3
control
circuit
bus
1 [3]
2 [4]
3 [5]
4 [6]
80
1
61
62
63
64
51
52
1
P13_3
P13_2
P13_1
P13_0
CLK0
RXD0
TXD0
AN2
2
AN1/DA1
AN0/DA0
3
2
5 [7]
4
1
3
WKUP0
VREF
MODE
6 [8]
7 [9]
5
6
2
3
4
5
8 [10]
9 [11]
7
8
4
5
6
7
XCIN
XCOUT
10 [12]
11 [13]
9
6
7
8
9
RESET
XOUT
VSS/
AVSS
XIN
10
P12_1
P12_0
12 [14]
13 [15]
14 [16]
11
12
13
8
9
10
11
12
VCC/
AVCC
10
15 [17]
16 [18]
17 [19]
18 [20]
19 [21]
14
15
16
17
18
11
12
13
14
15
P11_7
P11_6
P11_5
P11_4
P11_3
TREO
TRBO
TRAO
TRAIO
(ADTRG)
(INT7)
(INT6)
(INT5)
(INT4)
(INT3)
13
14
(RXD0)
IVCMP3
IVREF3
(CTS2/RTS2) SCS
(RXD2/SCL2/
TXD2/SDA2)
(RXD2/SCL2/
TXD2/SDA2)
20 [22]
21 [23]
19
16
15
P11_2
P11_1
SSO SDA
(INT2)
(INT1)
20
21
17
18
16
17
SSI
IVCMP1
IVREF1
22 [24]
23 [25]
24 [26]
25 [27]
26 [28]
27 [29]
28 [30]
29 [31]
P11_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
(CLK2)
SSCK SCL
(INT0)
(KI7)
(KI6)
(KI5)
(KI4)
(KI3)
(KI2)
(KI1)
(TRDIOD1)
(TRDIOC1)
(TRDIOB1)
(TRDIOA1)
(TRDIOD0)
(TRDIOC0)
(TRDIOB0)
(TRDIOA0/
TRDCLK)
30 [32]
P10_0
(KI0)
31 [33]
32 [34]
33 [35]
34 [36]
22
23
24
25
19
20
21
22
18
19
20
21
P7_7
P7_6
P7_5
P7_4
COM0
COM1
COM2
COM3
SEG55/
COM4
SEG54/
COM5
SEG53/
COM6
SEG52/
COM7
35 [37]
36 [38]
37 [39]
26
27
28
23
24
25
26
P7_3
P7_2
P7_1
38 [40]
39 [41]
29
30
P7_0
P6_7
TRDIOD1
SEG51
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.12
Pin Name Information by Pin Number (2)
Pin Number
I/O Pin Functions for Peripheral Modules
Control
Pin
A/D Converter, LCD drive
2
Port
L3AC
(Note 2)
L38C L36C L35C
Serial
Interface
I C
Interrupt
Timer
SSU
D/A Converter,
Comparator B
control
circuit
bus
40 [42]
41 [43]
42 [44]
43 [45]
44 [46]
45 [47]
31
32
33
34
35
36
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/
TRDCLK
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
46 [48]
37
P6_0
SEG44
47 [49]
48 [50]
49 [51]
50 [52]
P5_3
P5_2
P5_1
P5_0
SEG43
SEG42
SEG41
SEG40
TRCIOD/
TRCIOB
TRCIOC/
TRCIOB
TRCIOB
51 [53]
38
27
22
P4_7
SEG39
52 [54]
53 [55]
54 [56]
39
40
41
28
29
30
23
24
25
P4_6
P4_5
P4_4
SEG38
SEG37
SEG36
TRCIOA/
TRCTRG
TRCCLK/
TRCTRG
55 [57]
42
31
26
P4_3
SEG35
56 [58]
57 [59]
58 [60]
43
44
45
32
33
34
27
28
29
P4_2
P4_1
P4_0
CLK1
RXD1
TXD1
SEG34
SEG33
SEG32
59 [61]
60 [62]
61 [63]
62 [64]
63 [65]
64 [66]
65 [67]
66 [68]
67 [69]
68 [70]
69 [71]
70 [72]
71 [73]
72 [74]
73 [75]
74 [76]
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
35
36
37
38
39
40
41
42
43
44
45
46
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P3_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
TRCTRG
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
ADTRG
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
KI7
30
31
32
33
34
35
36
37
KI6
KI5
KI4
KI3
KI2
KI1
KI0
75 [77]
76 [78]
77 [79]
78 [80]
79 [81]
80 [82]
81 [83]
82 [84]
83 [85]
84 [86]
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
62
63
64
65
66
67
AN15
AN14
AN13
AN12
SEG8
(3)
47
48
38
39
SEG7
AN11
(3)
SEG6
AN10
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
3. Pins AN10 and AN11 are not available in the R8C/L35C, and R8C/L36C Groups.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.13
Pin Name Information by Pin Number (3)
Pin Number
I/O Pin Functions for Peripheral Modules
Control
Pin
LCD drive
control
circuit
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VL1
A/D Converter,
D/A Converter,
Comparator B
2
Port
L3AC
(Note 2)
L38C L36C L35C
Serial
Interface
I C
Interrupt
Timer
SSU
bus
85 [87]
86 [88]
87 [89]
88 [90]
89 [91]
90 [92]
91 [93]
92 [94]
93 [95]
94 [96]
95 [97]
96 [98]
97 [99]
98 [100]
99 [1]
68
69
70
71
72
73
74
75
76
77
78
79
49
50
51
52
53
54
55
56
57
58
59
60
40
41
42
43
44
45
46
47
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN9
AN8
AN7
AN6
AN5
AN4
VL2
VL3
48
49
50
P12_3
P12_2
CL2
CL1
VL4
P13_7
P13_6
P13_5
P13_4
TRGCLKB
TRGIOB
AN19
AN18
AN17
AN16
TRGCLKA
TRGIOA
100 [2]
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
1.5
Pin Functions
Tables 1.14 and 1.15 list Pin Functions for R8C/L3AC Group.
Table 1.14
Pin Functions for R8C/L3AC Group (1)
Item
Pin Name
I/O Type
Description
Power supply input VCC, VSS
−
Apply 1.8 V to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
MODE
RESET
MODE
I
I
Driving this pin low resets the MCU.
Connect this pin to VCC via a resistor.
Power-off mode exit
input
WKUP0
I
This pin is provided for input to exit the mode used in power-off
mode. Connect to VSS when not using power-off mode.
XIN clock input
XIN clock output
XCIN clock input
XCIN clock output
XIN
I
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic oscillator or a crystal oscillator between pins
(1)
XIN and XOUT.
To use an external clock, input it to the XIN
XOUT
XCIN
O
I
pin and leave the XOUT pin open.
These pins are provided for XCIN clock generation circuit I/O.
(1)
Connect a crystal oscillator between pins XCIN and XCOUT.
To use an external clock, input it to the XCIN pin and leave the
XCOUT pin open.
XCOUT
O
INT interrupt input
Key input interrupt
INT0 to INT7
I
I
INT interrupt input pins.
Key input interrupt input pins
KI0 to KI7
TRAIO
Timer RA
I/O
O
O
I
Timer RA I/O pin
TRAO
Timer RA output pin
Timer RB output pin
External clock input pin
External trigger input pin
Timer RC I/O pins
Timer RB
Timer RC
TRBO
TRCCLK
TRCTRG
I
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
O
I
External clock input pin
Divided clock output pin
Timer RG input pins
Timer RE
Timer RG
TREO
TRGCLKA, TRGCLKB
TRGIOA, TRGIOB
CLK0, CLK1, CLK2
RXD0, RXD1, RXD2
TXD0, TXD1, TXD2
I/O
I/O
I
Timer RG I/O pins
Serial interface
Transfer clock I/O pins
Serial data input pins
Serial data output pins
Transmission control input pin
O
I
CTS2
O
Reception control output pin
RTS2
SCL2
SDA2
2
I/O
I/O
I C mode clock I/O pin
2
I C mode data I/O pin
I: Input
Note:
O: Output
I/O: Input and output
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
1. Overview
Table 1.15
Pin Functions for R8C/L3AC Group (2)
Item
Pin Name
I/O Type
I/O
Description
I2C bus
SCL
SDA
SSI
Clock I/O pin
I/O
Data I/O pin
SSU
I/O
Data I/O pin
I/O
Chip-select signal I/O pin
SCS
SSCK
SSO
I/O
I/O
I
Clock I/O pin
Data I/O pin
Reference voltage VREF
input
Reference voltage input pin for the A/D converter and the D/A
converter
A/D converter
AN0 to AN11
ADTRG
I
I
A/D converter analog input pins
A/D external trigger input pin
D/A converter
Comparator B
DA0, DA1
O
I
D/A converter output pins
IVCMP1, IVCMP3
IVREF1, IVREF3
Comparator B analog voltage input pins
Comparator B reference voltage input pins
I
I/O ports
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0, P5_3,
P6_0 to P6_7
P7_0 to P7_7,
P10_0 to P10_7,
P11_0 to P11_7,
P12_0 to P12_3,
P13_0 to P13_7
I/O
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Ports P10_0 to P10_7 and P11_0 to P11_7 can be used as
LED drive ports.
Segment output
Common output
SEG0 to SEG55
COM0 to COM7
CL1, CL2
O
O
O
LCD segment output pins
LCD common output pins
Voltage multiplier
capacity connect
pins
Connect pins for the LCD control voltage multiplier
LCD power supply VL1
VL2 to VL4
I/O
I
Apply the voltage: 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VL4.
VL1 can be used as the reference potential input or output pin
when setting the voltage multiplier.
I: Input
Note:
O: Output
I/O: Input and output
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register banks.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers (1)
R3
A0
Address registers (1)
A1
FB
Frame base register (1)
b19
b15
b0
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4 high-order bits of INTB are INTBH and
the 16 low-order bits of INTB are INTBL.
b19
PC
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers configure a register bank.
There are two sets of register banks.
Figure 2.1
CPU Registers
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
3. Memory
3. Memory
Figure 3.1 is a Memory Map of each group. Each group has a 1-Mbyte address space from addresses 00000h to
FFFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal
RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a
stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0FFD8h
0FFDCh
0XXXXh
02C00h
Reserved area
SFR
Undefined instruction
Overflow
BRK instruction
(Refer to 4. Special Function
Registers (SFRs))
02FFFh
03000h
Internal ROM
(data flash) (1)
Address match
Single step
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
Internal ROM
(program ROM)
(Reserved)
Reset
0FFFFh
0FFFFh
Internal ROM
(program ROM)
Notes:
ZZZZZh
FFFFFh
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte),
block C (1 Kbyte), and block D (1 Kbyte).
2. Blank spaces are reserved. No access is allowed.
Internal ROM
Address
0YYYYh
Internal RAM
Part Number
Address
0XXXXh
Address
ZZZZZh
Capacity
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Capacity
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
R5F2L357C***, R5F2L367C***, R5F2L387C***, R5F2L3A7C***
R5F2L358C***, R5F2L368C***, R5F2L388C***, R5F2L3A8C***
R5F2L35AC***, R5F2L36AC***, R5F2L38AC***, R5F2L3AAC***
R5F2L35CC***, R5F2L36CC***, R5F2L38CC***, R5F2L3ACC***
04000h
04000h
04000h
04000h
−
01BFFh
023FFh
02BFFh
02BFFh
13FFFh
1BFFFh
23FFFh
Figure 3.1
Memory Map
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.16 list SFR
Informations and Table 4.17 lists the ID Code Areas and Option Function Select Area. The description offered in this
chapter is based on the R8C/L3AC Group.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
CM0
CM1
00h
00h
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
00100000b
00100000b
00h
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
XXh
(2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
Power-Off Mode Control Register 0
CSPR
00h
(3)
10000000b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
POMCR0
X0000000b
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
00h
When shipping
00h
00h
OCVREFCR
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
FRA4
FRA5
FRA6
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
(4)
00h
(5)
00100000b
0035h
0036h
0037h
0038h
Voltage Detection 1 Level Select Register
Voltage Monitor 0 Circuit Control Register
VD1LS
VW0C
00000111b
(4)
1100X010b
(5)
1100X011b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
10001010b
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. Hardware reset, software
reset, or watchdog timer reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 29 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Symbol
After Reset
10000010b
Voltage Monitor 2 Circuit Control Register
VW2C
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT7 Interrupt Control Register
INT6 Interrupt Control Register
INT5 Interrupt Control Register
INT4 Interrupt Control Register
INT7IC
INT6IC
INT5IC
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register / IIC bus Interrupt Control Register
S2RIC
KUPIC
ADIC
SSUIC/IICIC
(2)
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RA Interrupt Control Register
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
UART2 Bus Collision Detection Interrupt Control Register
Timer RG Interrupt Control Register
TRGIC
XXXXX000b
Voltage monitor 1 Interrupt Control Register
Voltage monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 30 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
DTCTL
After Reset
DTC Activation Control Register
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2MR
U2BRG
U2TB
UART2 Transmit Buffer Register
XXh
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00001000b
00000010b
XXh
XXh
00h
UART2 Digital Filter Function Select Register
URXDF
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 31 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After Reset
A/D Register 0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
D/A 0 Register
ADMOD
ADINSEL
ADCON0
ADCON1
DA0
00h
11000000b
00h
00h
00h
00h
D/A 1 Register
DA1
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
PD4
PD5
P6
P7
PD6
PD7
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
P10
P11
PD10
PD11
P12
P13
PD12
PD13
XXh
XXh
00h
00h
XXh
XXh
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 32 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.5
SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
After Reset
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Timer RE Counter Data Register
Timer RE Minute Data Register / Timer RE Compare Data Register
Timer RE Hour Data Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
XXh
XXh
XXh
XXh
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
XXXXX0XXb
XXh
00001000b
Timer RE Count Source Select Register
Timer RC Mode Register
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
01001000b
00h
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RC General Register A
Timer RC General Register B
Timer RC General Register C
Timer RC General Register D
TRCGRA
TRCGRB
TRCGRC
TRCGRD
FFh
Timer RC Control Register 2
TRCCR2
TRCDF
TRCOER
TRCADCR
00011000b
00h
01111111b
00h
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
Timer RD Control Expansion Register
Timer RD Trigger Control Register
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
TRDECR
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
00h
11111100b
00001110b
10001000b
10000000b
FFh
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
01111111b
00h
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 33 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.6
SFR Information (6)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
After Reset
Timer RD Control Register 0
00h
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
10001000b
10001000b
11100000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RD General Register A0
Timer RD General Register B0
Timer RD General Register C0
Timer RD General Register D0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
FFh
00h
Timer RD Control Register 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
10001000b
10001000b
11000000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
Timer RD General Register A1
Timer RD General Register B1
Timer RD General Register C1
Timer RD General Register D1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00001000b
00000010b
XXh
XXh
Timer RG Mode Register
TRGMR
TRGCNTC
TRGCR
TRGIER
TRGSR
TRGIOR
TRG
01000000b
00h
10000000b
11110000b
11100000b
00h
Timer RG Count Control Register
Timer RG Control Register
Timer RG Interrupt Enable Register
Timer RG Status Register
Timer RG I/O Control Register
Timer RG Counter
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
Timer RG General Register A
Timer RG General Register B
Timer RG General Register C
Timer RG General Register D
TRGGRA
TRGGRB
TRGGRC
TRGGRD
FFh
FFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 34 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.7
SFR Information (7)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
TRASR
After Reset
Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Timer RD Pin Select Register 0
Timer RD Pin Select Register 1
00h
00h
00h
00h
00h
00h
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
Timer RG Pin Select Register
UART0 Pin Select Register
UART1 Pin Select Register
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
Key Input Pin Select Register
TRGPSR
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
KISR
INTSR
PINSR
00h
00h
00h
00h
00h
00h
00h
00h
00h
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
SS Bit Counter Register
SSBR
SSTDR/ICDRT
SSTDRH
SSRDR/ICDRR
SSRDRH
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
SSSR/ICSR
SSMR2/SAR
11111000b
(2)
FFh
FFh
FFh
FFh
SS Transmit Data Register L / IIC bus Transmit Data Register
(2)
SS Transmit Data Register H
(2)
SS Receive Data Register L / IIC bus Receive Data Register
(2)
SS Receive Data Register H
(2)
00h
SS Control Register H / IIC bus Control Register 1
SS Control Register L / IIC bus Control Register 2
(2)
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
(2)
SS Mode Register / IIC bus Mode Register
(2)
SS Enable Register / IIC bus Interrupt Enable Register
(2)
SS Status Register / IIC bus Status Register
(2)
SS Mode Register 2 / Slave Address Register
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 35 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.8
SFR Information (8)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Register
Symbol
RMAD0
After Reset
Address Match Interrupt Register 0
XXh
XXh
0000XXXXb
00h
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
XXh
XXh
0000XXXXb
00h
Address Match Interrupt Enable Register 1
AIER1
Port P0 Pull-Up Control Register
Port P1 Pull-Up Control Register
Port P2 Pull-Up Control Register
Port P3 Pull-Up Control Register
Port P4 Pull-Up Control Register
Port P5 Pull-Up Control Register
Port P6 Pull-Up Control Register
Port P7 Pull-Up Control Register
P0PUR
P1PUR
P2PUR
P3PUR
P4PUR
P5PUR
P6PUR
P7PUR
00h
00h
00h
00h
00h
00h
00h
00h
Port 10 Pull-Up Control Register
Port 11 Pull-Up Control Register
Port 12 Pull-Up Control Register
Port 13 Pull-Up Control Register
P10PUR
P11PUR
P12PUR
P13PUR
00h
00h
00h
00h
Port P10 Drive Capacity Control Register
Port P11 Drive Capacity Control Register
P10DRR
P11DRR
00h
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
Comparator B Control Register 0
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
00h
Key Input Enable Register 1
KIEN1
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 36 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.9
SFR Information (9)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Register
Symbol
After Reset
LCD Control Register
LCR0
LCR1
LCR2
LCR3
00h
00h
LCD Bias Control Register
LCD Display Control Register
LCD Clock Control Register
X0000000b
00h
LCD Port Select Register 0
LCD Port Select Register 1
LCD Port Select Register 2
LCD Port Select Register 3
LCD Port Select Register 4
LCD Port Select Register 5
LCD Port Select Register 6
LCD Port Select Register 7
LSE0
LSE1
LSE2
LSE3
LSE4
LSE5
LSE6
LSE7
00h
00h
00h
00h
00h
00h
00h
00h
LCD Display Data Register
LRA0L
LRA1L
LRA2L
LRA3L
LRA4L
LRA5L
LRA6L
LRA7L
LRA8L
LRA9L
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
LRA10L
LRA11L
LRA12L
LRA13L
LRA14L
LRA15L
LRA16L
LRA17L
LRA18L
LRA19L
LRA20L
LRA21L
LRA22L
LRA23L
LRA24L
LRA25L
LRA26L
LRA27L
LRA28L
LRA29L
LRA30L
LRA31L
LRA32L
LRA33L
LRA34L
LRA35L
LRA36L
LRA37L
LRA38L
LRA39L
LRA40L
LRA41L
LRA42L
LRA43L
LRA44L
LRA45L
LRA46L
LRA47L
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 37 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.10
SFR Information (10)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
Register
Symbol
LRA48L
After Reset
LCD Display Data Register
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
LRA49L
LRA50L
LRA51L
LRA52L
LRA53L
LRA54L
LRA55L
LCD Display Control Data Register
LRA0H
LRA1H
LRA2H
LRA3H
LRA4H
LRA5H
LRA6H
LRA7H
LRA8H
LRA9H
LRA10H
LRA11H
LRA12H
LRA13H
LRA14H
LRA15H
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 38 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.11
SFR Information (11)
Address
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
Register
Symbol
LRA16H
After Reset
LCD Display Control Data Register
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
LRA17H
LRA18H
LRA19H
LRA20H
LRA21H
LRA22H
LRA23H
LRA24H
LRA25H
LRA26H
LRA27H
LRA28H
LRA29H
LRA30H
LRA31H
LRA32H
LRA33H
LRA34H
LRA35H
LRA36H
LRA37H
LRA38H
LRA39H
LRA40H
LRA41H
LRA42H
LRA43H
LRA44H
LRA45H
LRA46H
LRA47H
LRA48H
LRA49H
LRA50H
LRA51H
LRA52H
LRA53H
LRA54H
LRA55H
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 39 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.12
SFR Information (12)
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
Register
Symbol
After Reset
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 40 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.13
SFR Information (13)
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
Register
Symbol
After Reset
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
DTCD0
DTC Control Data 1
DTC Control Data 2
DTC Control Data 3
DTC Control Data 4
DTC Control Data 5
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 41 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.14
SFR Information (14)
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
Register
Symbol
DTCD6
After Reset
DTC Control Data 6
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 7
DTC Control Data 8
DTC Control Data 9
DTC Control Data 10
DTC Control Data 11
DTC Control Data 12
DTC Control Data 13
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 42 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.15
SFR Information (15)
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
Register
Symbol
DTCD14
After Reset
DTC Control Data 14
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 15
DTC Control Data 16
DTC Control Data 17
DTC Control Data 18
DTC Control Data 19
DTC Control Data 20
DTC Control Data 21
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 43 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4. Special Function Registers (SFRs)
(1)
Table 4.16
SFR Information (16)
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
:
Register
Symbol
DTCD22
After Reset
DTC Control Data 22
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 23
DTCD23
2FFFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
Table 4.17
ID Code Areas and Option Function Select Area
Address
Area Name
Symbol
After Reset
:
FFDBh
Option Function Select Register 2
OFS2
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 1)
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Option Function Select Register
OFS
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 44 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
5. Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 5.1
Absolute Maximum Ratings
Symbol
VCC/AVCC Supply voltage
Parameter
Condition
Rated Value
−0.3 to 6.5
−0.3 to 1.65
Unit
V
VI
Input voltage
XIN
XIN
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
V
−0.3 to VCC + 0.3
V
VL1
VL2
−0.3 to VL2
VL1 to VL4
V
V
V
V
V
V
V
R8C/L35C
R8C/L36C, R8C/L38C, R8C/L3AC
VL1 to VL3
VL3
VL2 to VL4
VL4
VL3 to 6.5
Other pins
−0.3 to VCC + 0.3
−0.3 to 1.65
VO
Output voltage XOUT
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
XOUT
−0.3 to VCC + 0.3
V
−0.3 to VL2 (2)
VL1 to VL4
VL1 to VL3
VL2 to VL4
−0.3 to 6.5
−0.3 to 6.5
−0.3 to VL4
−0.3 to VL4
−0.3 to VCC + 0.3
500
VL1
VL2
V
V
R8C/L35C
R8C/L36C, R8C/L38C, R8C/L3AC
V
VL3
VL4
V
V
CL1, CL2
V
COM0 to COM7
SEG0 to SEG55
Other pins
V
V
V
Pd
Power dissipation
−40°C ≤ Topr ≤ 85°C
mW
°C
Topr
Operating ambient temperature
−20 to 85 (N version) /
−40 to 85 (D version)
Tstg
Storage temperature
−65 to 150
°C
Notes:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit in the User’s Manual:
Hardware.
2. The VL1 voltage should be VCC or below.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 45 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
5.2
Recommended Operating Conditions
Table 5.2
Recommended Operating Conditions
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
Conditions
Unit
Min.
1.8
—
0.8 VCC
0.8 VCC
0.9 VCC
0.5 VCC
0.55 VCC
0.65 VCC
0.65 VCC
Typ.
—
0
Max.
5.5
—
VCC/AVCC Supply voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
VSS/AVSS Supply voltage
VIH
Input “H” voltage Other than CMOS input
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCC
VCC
VCC
CMOS Inputlevel Input level selection 4.0 V ≤ VCC ≤ 5.5 V
VCC
input
switching : 0.35 VCC
function
(I/O port)
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
VCC
VCC
VCC
: 0.5 VCC
0.7
0.8
V
CC
VCC
VCC
VCC
0.85 VCC
VCC
: 0.7 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
0.85 VCC
VCC
0.85 VCC
VCC
VIL
Input “L” voltage Other than CMOS input
0
0
0
0
0
0
0
0
0
0
0
0
—
0.2 VCC
0.2 VCC
0.05 VCC
0.2 VCC
CMOS Inputlevel Input level selection
input
switching : 0.35 VCC
function
(I/O port)
0.2
0.2
0.4
0.3
0.2
VCC
VCC
VCC
VCC
VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
0.55 VCC
0.45 VCC
0.35 VCC
−160
IOH(sum) Peak sum output Sum of all pins IOH(peak)
“H” current
IOH(sum) Average sum
output “H” current
IOH(peak) Peak output “H”
current
Sum of all pins IOH(avg)
—
—
−80
mA
Port P10, P11 (2)
Other pins
Port P10, P11 (2)
—
—
—
—
—
—
—
—
—
—
−40
−10
−20
−5
mA
mA
mA
mA
mA
IOH(avg)
Average output
“H” current (1)
Other pins
IOL(sum)
IOL(sum)
Peak sum output Sum of all pins IOL(peak)
“L” current
Average sum
160
Sum of all pins IOL(avg)
—
—
80
mA
output “L” current
Port P10, P11 (2)
Other pins
Port P10, P11 (2)
IOL(peak) Peak output “L”
current
—
—
—
—
—
—
—
32
—
—
40
10
20
5
20
5
mA
mA
IOL(avg)
Average output
“L” current (1)
—
mA
Other pins
—
—
—
32.768
—
mA
f(XIN)
XIN clock input oscillation frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 5.5 V
MHz
MHz
kHz
MHz
f(XCIN)
XCIN clock input oscillation frequency
50
40
fOCO40M When used as the count source for timer RC, timer RD, or 2.7 V ≤ VCC ≤ 5.5 V
timer RG (3)
fOCO-F fOCO-F frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
—
—
—
—
—
—
—
—
—
—
—
—
20
5
20
5
20
5
MHz
MHz
MHz
MHz
MHz
MHz
—
System clock frequency
CPU clock frequency
f(BCLK)
Notes:
1. The average output current indicates the average value of current measured during 100 ms.
2. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
3. fOCO40M can be used as the count source for timer RC, timer RD, or timer RG in the range of VCC = 2.7 V to 5.5V.
R01DS0095EJ0101 Rev.1.01
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Page 46 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
P0
P1
P2
P3
30 pF
P4
P5_0 to P5_3
P6
P7
P10
P11
P12_0 to P12_3
P13
Figure 5.1
Ports P0 to P4, P5_0 to P5_3, P6, P7, P10, P11, P12_0 to P12_3, and P13 Timing
Measurement Circuit
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 47 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
5.3
Peripheral Function Characteristics
Table 5.3
A/D Converter Characteristics
(VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr
=
−
20 to 85
°
C (N version) /
−
40 to 85°C (D version), unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Conditions
Min.
—
—
—
—
—
—
—
—
—
2
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Max.
10
±3
—
—
Resolution
Vref = AVCC
Bit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MHz
MHz
MHz
MHz
kΩ
Absolute accuracy (2)
10-bit mode
8-bit mode
Vref = AVCC = 5.0 V
Vref = AVCC = 3.3 V
Vref = AVCC = 3.0 V
Vref = AVCC = 2.2 V
Vref = AVCC = 5.0 V
Vref = AVCC = 3.3 V
Vref = AVCC = 3.0 V
Vref = AVCC = 2.2 V
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
AN0 to AN19 input
±5
±5
±5
±2
±2
±2
±2
4.0 ≤ Vref = AVCC ≤ 5.5 V (1)
3.2 ≤ Vref = AVCC ≤ 5.5 V (1)
2.7 ≤ Vref = AVCC ≤ 5.5 V (1)
2.2 ≤ Vref = AVCC ≤ 5.5 V (1)
φAD
A/D conversion clock
20
2
16
2
10
2
5
—
Tolerance level impedance
Conversion time
—
2.2
2.2
0.8
—
2.2
0
—
tCONV
10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz
—
—
—
45
—
—
1.34
—
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
φAD = 20 MHz
—
µs
tSAMP
IVref
Vref
Sampling time
—
µs
Vref current
Vcc = 5 V, XIN = f1 = φAD = 20 MHz
—
µA
Reference voltage
Analog input voltage (3)
AVCC
Vref
1.49
V
VIA
V
OCVREF On-chip reference voltage
2 MHz ≤ φAD ≤ 4 MHz
1.19
V
Notes:
1. The A/D conversion result will be undefined in wait mode, stop mode, power-off mode, when the flash memory stops, and in
low-current-consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D
conversion.
2. This applies when the peripheral functions are stopped.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
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Apr 15, 2011
Page 48 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.4
D/A Converter Characteristics
(VCC/AVCC = Vref = 2.7 to 5.5 V and Topr
=
−20 to 85
°C (N version) /
−
40 to 85
°
C
(D version), unless otherwise specified.)
Standard
Symbol
Parameter
Conditions
Unit
Min.
Typ.
—
—
—
6
Max.
8
—
Resolution
—
—
—
—
—
Bit
LSB
µs
—
Absolute accuracy
Setup time
2.5
3
tsu
RO
IVref
Output resistor
—
kΩ
Reference power input current
(Note 1)
—
1.5
mA
Note:
1. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included.
Table 5.5
Comparator B Characteristics
(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Vref
Parameter
Condition
Unit
Min.
0
Typ.
—
Max.
VCC − 1.4
VCC + 0.3
100
IVREF1, IVREF3 input reference voltage
IVCMP1, IVCMP3 input voltage
Offset
Comparator output delay time (1)
Comparator operating current
V
V
VI
−0.3
—
—
—
5
mV
µs
µA
td
VI = Vref ± 100 mV
VCC = 5.0 V
—
0.1
17.5
—
ICMP
—
—
Note:
1. When the digital filter is disabled.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 49 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.6
Flash Memory (Program ROM) Characteristics
(VCC = 2.7 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.)
Standard
Symbol
Parameter
Conditions
Unit
Min.
1,000 (2)
—
Typ.
—
Max.
—
Program/erase endurance (1)
Byte program time
—
times
µs
—
80
500
—
—
Block erase time
—
0.3
—
s
td(SR-SUS)
Time delay from suspend request until
suspend
—
5 + CPU clock
× 3 cycles
ms
—
—
Interval from erase start/restart until
following suspend request
0
—
—
—
—
ms
µs
µs
Time from suspend until erase restart
—
—
30+CPU clock
× 1 cycle
td(CMDRST-
READY)
Time from when command is forcibly
terminated until reading is enabled
30+CPU clock
× 1 cycle
—
—
—
—
Program, erase voltage
Read voltage
2.7
1.8
0
—
—
—
—
5.5
5.5
60
V
V
Program, erase temperature
Data hold time (6)
°C
Ambient temperature = 55°C
20
—
year
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
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Apr 15, 2011
Page 50 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.7
Flash Memory (Data flash Block A to Block D) Characteristics
(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
Conditions
Unit
Min.
10,000
—
Typ.
—
Max.
—
Program/erase endurance (1)
(2)
—
—
times
Byte program time
160
1500
µs
(program/erase endurance ≤ 1,000 times)
—
Byte program time
(program/erase endurance > 1,000 times)
—
—
—
—
0
300
0.2
0.3
—
1500
µs
s
—
Block erase time
(program/erase endurance ≤ 1,000 times)
1
1
—
Block erase time
(program/erase endurance > 1,000 times)
s
td(SR-SUS)
Time delay from suspend request until
suspend
5 + CPU clock
× 3 cycles
ms
ms
µs
µs
—
—
Interval from erase start/restart until
following suspend request
—
—
Time from suspend until erase restart
—
—
—
30+CPU clock
× 1 cycle
td(CMDRST-
READY)
Time from when command is forcibly
terminated until reading is enabled
—
30+CPU clock
× 1 cycle
—
—
—
—
Program, erase voltage
Read voltage
2.7
1.8
−20 (6)
—
—
—
—
5.5
5.5
85
—
V
V
Program, erase temperature
°C
Data hold time (7)
Ambient temperature = 55 °C
20
year
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. −40°C for D version.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Clock-dependent
Fixed time
time
Access restart
td(SR-SUS)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
R01DS0095EJ0101 Rev.1.01
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R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.8
Voltage Detection 0 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Vdet0
Parameter
Condition
Unit
Min.
1.80
2.15
2.70
3.55
—
Typ.
1.90
2.35
2.85
3.80
6
Max.
2.05
2.50
3.05
4.05
150
Voltage detection level Vdet0_0 (1)
Voltage detection level Vdet0_1 (1)
Voltage detection level Vdet0_2 (1)
Voltage detection level Vdet0_3 (1)
Voltage detection 0 circuit response time (3)
V
V
V
V
—
At the falling of Vcc from 5 V
µs
to (Vdet0_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit
operation starts (2)
VCA25 = 1, VCC = 5.0 V
—
—
1.5
—
—
µA
µs
td(E-A)
100
Notes:
1. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.9
Voltage Detection 1 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Vdet1
Parameter
Condition
Unit
Min.
2.00
2.15
2.30
2.45
2.60
2.75
2.85
3.00
3.15
3.30
3.45
3.60
3.75
3.90
4.05
4.20
—
Typ.
2.20
2.35
2.50
2.65
2.80
2.95
3.10
3.25
3.40
3.55
3.70
3.85
4.00
4.15
4.30
4.45
0.07
Max.
2.40
2.55
2.70
2.85
3.00
3.15
3.40
3.55
3.70
3.85
4.00
4.15
4.30
4.45
4.60
4.75
—
Voltage detection level Vdet1_0 (1)
Voltage detection level Vdet1_1 (1)
Voltage detection level Vdet1_2 (1)
Voltage detection level Vdet1_3 (1)
Voltage detection level Vdet1_4 (1)
Voltage detection level Vdet1_5 (1)
Voltage detection level Vdet1_6 (1)
Voltage detection level Vdet1_7 (1)
Voltage detection level Vdet1_8 (1)
Voltage detection level Vdet1_9 (1)
Voltage detection level Vdet1_A (1)
Voltage detection level Vdet1_B (1)
Voltage detection level Vdet1_C (1)
Voltage detection level Vdet1_D (1)
Voltage detection level Vdet1_E (1)
Voltage detection level Vdet1_F (1)
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
—
—
Hysteresis width at the rising of Vcc in voltage
detection 1 circuit
Vdet1_0 to Vdet1_5
selected
Vdet1_6 to Vdet1_F
selected
—
—
0.10
60
—
V
Voltage detection 1 circuit response time (2)
At the falling of Vcc from
150
µs
5 V to (Vdet1_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (3)
VCA26 = 1, VCC = 5.0 V
—
—
1.7
—
—
µA
µs
td(E-A)
100
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
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Apr 15, 2011
Page 52 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.10
Voltage Detection 2 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
Condition
Unit
Min.
3.70
—
Typ.
4.00
0.10
Max.
4.30
—
Vdet2
—
At the falling of VCC
V
V
Voltage detection level Vdet2_0
Hysteresis width at the rising of Vcc in voltage detection
2 circuit
Voltage detection 2 circuit response time (1)
—
At the falling of Vcc from
—
20
150
µs
5 V to (Vdet2_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (2)
VCA27 = 1, VCC = 5.0 V
—
—
1.7
—
—
µA
µs
td(E-A)
100
Notes:
1. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
2. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
(1)
Table 5.11
Power-on Reset Circuit Characteristics
20 to 85 C (N version) /
(Topr
=
−
°
−
40 to 85
°
C (D version), unless otherwise specified.)
Standard
Symbol
Parameter
External power VCC rise gradient
Condition
Unit
Min.
0
Typ.
—
Max.
50000 mV/msec
trth
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
(1)
Vdet0
(1)
Vdet0
trth
trth
External
Power VCC
0.5 V
(2)
Voltage detection 0
circuit response time
tw(por)
Internal
reset signal
1
1
× 32
× 32
fOCO-S
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit in the User’s Manual: Hardware for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Characteristics
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 53 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.12
High-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Typ.
Unit
Symbol
—
Parameter
Condition
Min.
38.4
Max.
41.6
High-speed on-chip oscillator frequency after
reset
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
40
MHz
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
38.0
35.389
35.020
30.72
30.40
40
42.0
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into −20°C ≤ Topr ≤ 85°C
the FRA1 register and the FRA5 register
correction value into the FRA3 register (1)
VCC = 1.8 V to 5.5 V
36.864 38.338 MHz
36.864 38.707 MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
High-speed on-chip oscillator frequency when
the FRA6 register correction value is written into −20°C ≤ Topr ≤ 85°C
the FRA1 register and the FRA7 register
correction value into the FRA3 register
VCC = 1.8 V to 5.5 V
32
32
33.28
33.60
MHz
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
—
—
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
VCC = 5.0 V, Topr = 25°C
—
—
0.5
3
ms
Self power consumption at oscillation
400
—
µA
Note:
1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.13
Low-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Standard
Symbol
fOCO-S
Parameter
Condition
Unit
Min.
112.5
—
Typ.
125
30
Max.
137.5
100
Low-speed on-chip oscillator frequency
Oscillation stability time
kHz
µs
—
—
VCC = 5.0 V, Topr = 25°C
VCC = 5.0 V, Topr = 25°C
Self power consumption at oscillation
—
3
—
µA
fOCO-WDT Low-speed on-chip oscillator frequency for the
watchdog timer
60
125
250
kHz
—
—
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
VCC = 5.0 V, Topr = 25°C
—
—
30
2
100
—
µs
Self power consumption at oscillation
µA
Table 5.14
Power Supply Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 25°C, unless otherwise specified.)
Standard
Symbol
Parameter
Condition
Unit
Min.
—
Typ.
—
Max.
2000
td(P-R)
Time for internal power supply stabilization during
power-on (1)
µs
Note:
1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 54 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.15
LCD Drive Control Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Standard
Symbol
Parameter
Condition
Unit
Min.
2.2
VL2
VL1
VL1
1
Typ.
—
Max.
5.5
VLCD
VL3
LCD power supply voltage
VL3 voltage
VLCD = VL4
V
V
V
V
V
V
—
VL4
VL2
VL2 voltage
R8C/L35C
—
VL4
R8C/L36C, R8C/L38C, R8C/L3AC
—
VL3
VL2 (3)
VL1
—
VL1 voltage
—
VL1 internally-generated voltage accuracy
Setting Setting Setting
voltage voltage voltage
(1)
−0.2
+0.2
180
—
f(FR)
ILCD
Frame frequency
50
—
Hz
LCD drive control circuit current
—
(Note 2)
µA
Notes:
1. The voltage is selected with bits LVLS0 to LVLS3 in the LCR1 register.
2. Refer to Table 5.18 DC Characteristics (2), Table 5.20 DC Characteristics (4), and Table 5.22 DC Characteristics (6).
3. The VL1 voltage should be VCC or below.
Table 5.16
Power-Off Mode Characteristics
(VCC = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Standard
Symbol
Parameter
Condition
Unit
V
Min.
2.2
Typ.
—
Max.
5.5
—
Power-off mode operating supply voltage
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 55 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
5.4
DC Characteristics
Table 5.17
DC Characteristics (1) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Symbol
VOH
Parameter
Port P10, P11 (1)
Condition
IOH = −20 mA
Unit
Min.
VCC − 2.0
VCC − 2.0
1.0
Typ.
—
Max.
VCC
VCC
—
Output “H” voltage
Output “L” voltage
Hysteresis
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
V
V
V
V
V
V
V
Other pins
XOUT
IOH = −5 mA
IOH = −200 µA
IOL = 20 mA
IOL = 5 mA
—
—
Port P10, P11 (1)
Other pins
XOUT
VOL
—
—
2.0
2.0
0.5
—
—
—
IOL = 200 µA
—
—
VT+-VT-
0.05
0.5
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA,
TRGCLKB, TRGIOA,
TRGIOB, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
0.1
—
—
25
—
1.0
—
—
5.0
−5.0
100
—
V
RESET, WKUP0
IIH
IIL
Input “H” current
Input “L” current
VI = 5.0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
µA
µA
kΩ
MΩ
—
RPULLUP Pull-up resistance
50
0.3
RfXIN
Feedback
resistance
XIN
RfXCIN
Feedback
resistance
XCIN
—
14
—
—
—
MΩ
VRAM
RAM hold voltage
During stop mode
1.8
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 56 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.18
DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Standard
Oscillation
Circuit
XIN
XCIN
(2)
On-Chip
Oscillator
High-Speed Low-
(fOCO-F) Speed
Low-Power-
Consumption
Setting
Symbol Parameter
Unit
CPU
Clock
Typ.
(3)
Other
Min.
Max.
ICC
Power
supply
current
High-
speed
clock
mode
20
MHz
16
MHz
10
MHz
20
MHz
16
MHz
10
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
125
No
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.0 15 mA
5.6 12.5 mA
kHz division
125 No
kHz division
125 No
kHz division
125 Divide-
kHz
125 Divide-
kHz by-8
125 Divide-
(1)
3.6
3.0
2.2
1.5
—
—
—
—
mA
mA
mA
mA
by-8
MHz
kHz
by-8
No
High-
Off Off
Off Off
Off Off
20 MHz 125
7.0 15 mA
speed
on-chip
oscillator
mode
kHz division
20 MHz 125 Divide-
3.0
1
—
—
mA
mA
kHz
by-8
4 MHz
125 Divide- MSTIIC = 1
kHz by-16 MSTTRD = 1
MSTTRC = 1
MSTTRG = 1
Low-
Off Off
Off
125 Divide- FMR27 = 1
—
90 400 µA
speed
on-chip
oscillator
mode
Low-
speed
clock
mode
kHz
by-8 VCA20 = 0
Off
Off
32
kHz
32
Off
Off
Off
Off
Off
No FMR27 = 1
division VCA20 = 0
No FMSTP = 1 Flash memory off
division VCA20 = 0 Program operation on RAM
—
—
—
100 400 µA
55
—
µA
kHz
Wait
mode
Off Off
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
15 100 µA
VCA26 = 0
VCA25 = 0
VCA20 = 1
Peripheral clock operation
Off Off
Off
Off
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
—
4
90 µA
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
Peripheral clock off
Off
Off
32
kHz
Off
Off
—
—
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
While a WAIT
LCD drive control
circuit
—
—
—
7
—
—
—
µA
µA
µA
(4)
instruction is executed
Peripheral clock off
Timer RE operation in
real-time clock mode
When external division
resistors are used
LCD drive control
12
3.5
(5)
circuit
When the internal
voltage multiplier is used
VCA27 = 0 While a WAIT instruction is executed
32
Off
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
kHz
Peripheral clock off
Timer RE operation in real-time clock mode
Stop
mode
Off Off
Off Off
Off
Off
Off
Off
—
—
VCA27 = 0 Topr = 25°C
—
—
2.0 5.0 µA
VCA26 = 0
VCA25 = 0
CM10 = 1
Peripheral clock off
VCA27 = 0 Topr = 85°C
VCA26 = 0 Peripheral clock off
VCA25 = 0
15
—
µA
CM10 = 1
Power-
off mode
Off Off
Off Off
Off
Off
Off
Off
—
—
—
—
Topr = 25°C
Topr = 85°C
—
—
0.02 0.2 µA
0.4 µA
—
Notes:
1. Vcc = 4.0 V to 5.5 V, single chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. Vcc = 5.0 V
4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 57 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.19
DC Characteristics (3) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Symbol
Parameter
Output “H” voltage
Condition
Unit
Min.
VCC − 0.5
VCC − 0.5
1.0
Typ.
—
Max.
VCC
VCC
—
Port P10, P11 (1)
VOH
IOH = −5 mA
IOH = −1 mA
V
V
V
V
V
V
V
Other pins
XOUT
—
IOH = −200 µA
IOL = 5 mA
—
Port P10, P11 (1)
Other pins
XOUT
VOL
Output “L” voltage
Hysteresis
—
—
0.5
0.5
0.5
—
IOL = 1 mA
—
—
IOL = 200 µA
—
—
VT+-VT-
0.05
0.4
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3, KI4,
KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA, TRGCLKB,
TRGIOA, TRGIOB,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
0.1
—
0.8
—
—
5.0
−5.0
170
—
V
RESET, WKUP0
IIH
IIL
Input “H” current
Input “L” current
VI = 3.0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
µA
µA
kΩ
MΩ
—
—
RPULLUP Pull-up resistance
30
—
100
0.3
RfXIN
Feedback
resistance
XIN
RfXCIN
Feedback
resistance
XCIN
—
14
—
—
—
MΩ
VRAM
RAM hold voltage
During stop mode
1.8
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 58 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.20
DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Standard
Oscillation
Circuit
On-Chip
Oscillator
Low-Power-
Consumption
Setting
Symbol Parameter
Unit
CPU
Clock
Typ.
(3)
Other
Min.
Max.
High-Speed Low-
(fOCO-F) Speed
XIN
XCIN
(2)
ICC
Power
supply
current
High-
speed
clock
mode
20
MHz
10
MHz
20
MHz
Off
Off
Off
Off
Off
Off
Off
Off
125 No
kHz division
125 No
kHz division
125 Divide-
kHz by-8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.0 14.5 mA
3.6 10 mA
(1)
3.0
1.5
—
—
mA
mA
10
MHz
125 Divide-
kHz by-8
High-
Off Off 20 MHz 125 No
kHz division
Off Off 20 MHz 125 Divide-
kHz by-8
7.0 14.5 mA
speed
on-chip
oscillator
mode
3.0
4.0
1.7
1
—
—
—
—
mA
mA
mA
mA
Off Off 10 MHz 125 No
kHz division
Off Off 10 MHz 125 Divide-
kHz by-8
Off Off
4 MHz
125 Divide- MSTIIC = 1
MSTTRD = 1
MSTTRC = 1
MSTTRG = 1
kHz by-16
Low-
Off Off
Off
125 Divide- FMR27 = 1
—
85 390 µA
speed
on-chip
oscillator
mode
kHz by-8
VCA20 = 0
Low-
Off
Off
32
kHz
Off
Off
Off No
FMR27 = 1
—
—
90 400 µA
speed
clock
mode
division VCA20 = 0
Off No FMSTP = 1 Flash memory off
division VCA20 = 0 Program operation on RAM
32
kHz
50
—
µA
Wait
mode
Off Off
Off Off
Off
Off
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
—
—
15 90 µA
VCA26 = 0
VCA25 = 0
VCA20 = 1
Peripheral clock operation
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
5
80 µA
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
Peripheral clock off
Off
32
kHz
Off
Off
—
VCA27 = 0 While a WAIT
VCA26 = 0 instruction is
VCA25 = 0 executed
LCD drive control
circuit
When external division
resistors are used
—
—
5
—
—
µA
µA
(4)
VCA20 = 1 Peripheral clock off
CM02 = 1
CM01 = 0
Timer RE operation
in real-time clock
mode
LCD drive control
11
(5)
circuit
When the internal
voltage multiplier is
used
Off
32
kHz
Off
Off
—
VCA27 = 0 While a WAIT instruction is executed
—
3.5
—
µA
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
Peripheral clock off
Timer RE operation in real-time clock mode
Stop
mode
Off Off
Off Off
Off
Off
Off
Off
—
—
VCA27 = 0 Topr = 25°C
—
—
2
5.0 µA
VCA26 = 0
VCA25 = 0
CM10 = 1
Peripheral clock off
VCA27 = 0 Topr = 85°C
13.0
—
µA
VCA26 = 0
VCA25 = 0
CM10 = 1
Peripheral clock off
Power-
off mode
Off Off
Off Off
Off
Off
Off
Off
—
—
—
—
Topr = 25°C
Topr = 85°C
—
—
0.02 0.2 µA
0.3 µA
—
Notes:
1. Vcc = 2.7 V to 4.0 V, single chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. Vcc = 3.0 V
4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 59 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.21
DC Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Symbol
Parameter
Output “H” voltage
Condition
Unit
Min.
VCC − 0.5
VCC − 0.5
1.0
Typ.
—
Max.
VCC
VCC
—
Port P10, P11 (1)
VOH
IOH = −2 mA
IOH = −1 mA
V
V
V
V
V
V
V
Other pins
XOUT
—
IOH = −200 µA
IOL = 2 mA
—
Port P10, P11 (1)
Other pins
XOUT
VOL
Output “L” voltage
Hysteresis
—
—
0.5
0.5
0.5
—
IOL = 1 mA
—
—
IOL = 200 µA
—
—
VT+-VT-
0.05
0.4
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3, KI4,
KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA, TRGCLKB,
TRGIOA, TRGIOB,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
0.1
—
0.8
—
—
4.0
−4.0
420
—
V
RESET, WKUP0
IIH
IIL
Input “H” current
Input “L” current
VI = 1.8 V, VCC = 1.8 V
VI = 0 V, VCC = 1.8 V
VI = 0 V, VCC = 1.8 V
µA
µA
kΩ
MΩ
—
—
RPULLUP Pull-up resistance
60
—
160
0.3
RfXIN
Feedback
resistance
XIN
RfXCIN
Feedback
resistance
XCIN
—
14
—
—
—
MΩ
VRAM
RAM hold voltage
During stop mode
1.8
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 60 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.22
DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Standard
Oscillation
Circuit
On-Chip
Oscillator
Low-Power-
Consumption
Setting
Symbol Parameter
Unit
CPU
Clock
Typ.
(3)
Other
Min.
Max.
High-Speed Low-
(fOCO-F) Speed
XIN
XCIN
(2)
ICC
Power
supply
current
High-
speed
clock
mode
5
MHz
5
MHz
Off Off
Off Off
Off Off
Off
Off
125 No
kHz division
125 Divide-
kHz by-8
125 No
—
—
—
—
—
—
—
—
—
2.2
0.8
—
—
mA
mA
(1)
Off
Off
High-
5 MHz
5 MHz
4 MHz
2.5 10 mA
speed
on-chip
oscillator
mode
kHz division
125 Divide-
kHz by-8
125 Divide- MSTIIC = 1
kHz by-16 MSTTRD = 1
MSTTRC = 1
1.7
1
—
—
mA
mA
MSTTRG = 1
Low-
Off Off
Off
125 Divide- FMR27 = 1
—
90 300 µA
speed
on-chip
oscillator
mode
kHz by-8
VCA20 = 0
Low-
Off
Off
32
kHz
32
kHz
Off
Off
Off
Off No
FMR27 = 1
—
—
—
90 400 µA
speed
clock
mode
division VCA20 = 0
Off No FMSTP = 1 Flash memory off
division VCA20 = 0 Program operation on RAM
45
—
µA
Wait
mode
Off Off
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
VCA26 = 0 Peripheral clock operation
VCA25 = 0
15 90 µA
VCA20 = 1
Off Off
Off
Off
125
kHz
—
VCA27 = 0 While a WAIT instruction is executed
VCA26 = 0 Peripheral clock off
VCA25 = 0
VCA20 = 1
CM02 = 1
—
4
80 µA
CM01 = 1
Off
32
Off
—
VCA27 = 0 While a WAIT
VCA26 = 0 instruction is
VCA25 = 0 executed
LCD drive control
circuit
When external division
resistors are used
—
—
4
—
—
µA
µA
(4)
kHz
VCA20 = 1 Peripheral clock off
CM02 = 1
CM01 = 0
Timer RE operation
in real-time clock
mode
LCD drive control
circuit
When the internal
voltage multiplier is
used
11
(5)
Off
32
Off
Off
—
VCA27 = 0 While a WAIT instruction is executed
—
3.5
—
µA
kHz
VCA26 = 0 Peripheral clock off
VCA25 = 0 Timer RE operation in real-time clock mode
VCA20 = 1
CM02 = 1
CM01 = 1
Stop
mode
Off Off
Off Off
Off
Off
Off
Off
—
—
VCA27 = 0 Topr = 25°C
VCA26 = 0 Peripheral clock off
VCA25 = 0
—
—
2.0 5.0 µA
CM10 = 1
VCA27 = 0 Topr = 85°C
VCA26 = 0 Peripheral clock off
VCA25 = 0
13
—
µA
CM10 = 1
Power-
off mode
Off Off
Off Off
Off
Off
Off
Off
—
—
—
—
Topr = 25°C
Topr = 85°C
—
—
0.02 0.2 µA
0.3 µA
—
Notes:
1. Vcc = 1.8 V to 2.7 V, single chip mode, output pins are open, and other pins are Vss.
2. XIN is set to square wave input.
3. Vcc = 2.2 V
4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open.The standard value does not include the current that flows through external division resistors.
5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 61 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
5.5
AC Characteristics
Table 5.23
Timing Requirements of Synchronous Serial Communication Unit (SSU)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Standard
Symbol
tSUCYC
Parameter
Conditions
Unit
Min.
4
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
0.6
0.6
1
(1)
SSCK clock cycle time
SSCK clock “H” width
SSCK clock “L” width
tCYC
tHI
0.4
0.4
—
tSUCYC
tSUCYC
tLO
(1)
tRISE
SSCK clock rising
time
Master
Slave
tCYC
—
1
µs
(1)
tFALL
SSCK clock falling
time
Master
Slave
—
1
tCYC
—
1
µs
tSU
SSO, SSI data input setup time
SSO, SSI data input hold time
100
1
—
—
ns
(1)
tH
tCYC
tLEAD
Slave
1tCYC + 50
1tCYC + 50
—
—
—
—
ns
ns
SCS setup time
tLAG
tOD
tSA
Slave
SCS hold time
(1)
SSO, SSI data output delay time
SSI slave access time
—
—
—
—
—
—
—
—
—
—
1
tCYC
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.5tCYC + 100
1.5tCYC + 200
1.5tCYC + 100
1.5tCYC + 200
ns
ns
ns
ns
tOR
SSI slave out open time
Note:
1. 1tCYC = 1/f1(s)
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 62 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
4-Wire Bus Communication Mode, Master, CPHS = 1
5. Electrical Characteristics
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 63 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
SSI (output)
tSU
tH
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 64 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
Figure 5.6
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 65 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
2
(1)
Table 5.24
Timing Requirements of I C bus Interface
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr
unless otherwise specified.)
=
−
20 to 85
°C (N version) /
−40 to 85
°C (D version),
Standard
Typ.
Symbol
Parameter
SCL input cycle time
Condition
Unit
Min.
12tCYC + 600
3tCYC + 300
5tCYC + 500
—
Max.
(1)
tSCL
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(1)
tSCLH
tSCLL
tsf
SCL input “H” width
SCL input “L” width
—
SCL, SDA input fall time
300
(1)
tSP
SCL, SDA input spike pulse rejection time
SDA input bus-free time
—
1tCYC
—
(1)
tBUF
tSTAH
tSTAS
tSTOP
tSDAS
tSDAH
5tCYC
(1)
Start condition input hold time
Retransmit start condition input setup time
Stop condition input setup time
Data input setup time
—
3tCYC
(1)
—
3tCYC
(1)
—
3tCYC
(1)
—
1tCYC + 40
10
Data input hold time
—
Note:
SDA
SCL
1. 1tCYC = 1/f1(s)
VIH
VIL
tBUF
tSTAH
tSP
tSTOP
tSCLH
tSTAS
P(2)
S(1)
tsf
Sr(3)
P(2)
tSCLL
tsr
tSDAS
tSCL
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
2
Figure 5.7
I/O Timing of I C bus Interface
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 66 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.25
External Clock Input (XIN, XCIN)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr
unless otherwise specified.)
= −20 to 85°C (N version) / −40 to 85°C (D version),
Standard
Symbol
Parameter
V
CC = 2.2V, Topr = 25
°
C
V
CC = 3V, Topr = 25
°C
V
CC = 5V, Topr = 25
°C
Unit
Min.
200
90
90
14
7
Max.
—
Min.
50
24
24
14
7
Max.
—
Min.
50
24
24
14
7
Max.
—
tc(XIN)
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
ns
ns
ns
µs
µs
µs
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
—
—
—
—
—
—
—
—
—
—
—
—
7
—
7
—
7
—
tC(XIN), tC(XCIN)
tWH(XIN),
tWH(XCIN)
External
Clock Input
tWL(XIN), tWL(XCIN)
Figure 5.8
Table 5.26
External Clock Input Timing Diagram
Timing Requirements of TRAIO
(VCC = 1.8 to 5.5 V, VSS = 0 V and Topr
unless otherwise specified.)
= −20 to 85°C (N version) / −40 to 85°C (D version),
Standard
Symbol
Parameter
V
CC = 2.2V, Topr = 25
°
C
V
CC = 3V, Topr = 25
°C
V
CC = 5V, Topr = 25
°C
Unit
Min.
500
200
200
Max.
—
Min.
300
120
120
Max.
—
Min.
100
40
Max.
—
tc(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
ns
ns
ns
tWH(TRAIO)
tWL(TRAIO)
—
—
—
—
—
40
—
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
Input Timing of TRAIO
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 67 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
5. Electrical Characteristics
Table 5.27
Timing Requirements of Serial Interface
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr
unless otherwise specified.)
= −20 to 85°C (N version) / −40 to 85°C (D version),
Standard
VCC = 2.2V, Topr = 25°C VCC = 3V, Topr = 25°C VCC = 5V, Topr = 25°C
Symbol
Parameter
Unit
Min.
800
400
400
—
Max.
—
Min.
300
150
150
—
Max.
—
Min.
200
100
100
—
Max.
—
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
—
—
—
—
—
—
200
—
80
—
50
—
0
0
0
RXDi input setup time
RXDi input hold time
150
90
—
70
—
50
—
—
90
—
90
—
i = 0 to 2
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 to 2
Figure 5.10
Table 5.28
Input and Output Timing of Serial Interface
Timing Requirements of External Interrupt INTi (i = 0 to 7) and Key Input Interrupt KIi
(i = 0 to 7)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr
unless otherwise specified.)
= −20 to 85°C (N version) / −40 to 85°C (D version),
Standard
Symbol
Parameter
V
CC = 2.2V, Topr = 25
°C
V
CC = 3V, Topr = 25
°
C
V
CC = 5V, Topr = 25
°
C
Unit
Min.
Max.
—
Min.
Max.
Min.
Max.
(1)
(1)
(1)
tW(INH)
ns
ns
—
—
—
—
1000
1000
380
250
INTi input “H” width, KIi input “H” width
INTi input “L” width, KIi input “L” width
(2)
(2)
(2)
tW(INL)
—
380
250
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
INTi input
(i = 0 to 7)
tW(INL)
KIi input
(i = 0 to 7)
tW(INH)
Figure 5.11
Input Timing of External Interrupt INTi and Key Input Interrupt KIi
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 68 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics web site.
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
HD
D
*1
39
27
NOTE)
1. DIMENSIONS "*1" AND "*2"
40
26
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
52
Terminal cross section
D
E
9.9 10.0 10.1
9.9 10.0 10.1
1.4
14
A2
HD
HE
A
1
13
11.8 12.0 12.2
11.8 12.0 12.2
1.7
ZD
Index mark
F
c
A1
bp
b1
c
0.05 0.1 0.15
0.27 0.32 0.37
0.30
S
0.145
0.125
0.09
0.20
L
c1
y
S
*3
e
bp
L1
0°
8°
x
e
x
0.65
Detail F
0.13
0.10
y
ZD
ZE
L
1.1
1.1
0.35 0.5 0.65
1.0
L1
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 69 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
Package Dimensions
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
MASS[Typ.]
0.3g
64P6Q-A / FP-64K / FP-64KV
HD
D
*1
48
33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1
10.0 10.1
1.4
9.9
9.9
64
17
Terminal cross section
A2
HD
HE
A
11.8 12.0 12.2
11.8 12.0 12.2
1.7
1
16
Index mark
ZD
A1
bp
b1
c
0.05
0.15
0.1
0.15 0.20 0.25
0.18
F
S
0.09
0.20
c
0.145
0.125
c1
0°
8°
y
S
e
0.5
*3
L
bp
e
x
0.08
0.08
x
L1
y
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
MASS[Typ.]
0.7g
64P6U-A/
HD
*1
D
33
48
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
64
17
A1
bp
b1
c
0.1 0.2
0
1
16
ZD
0.32 0.37 0.42
0.35
Index mark
c
F
0.145
0.125
0.09
0.20
S
c1
L
L1
0°
8°
e
x
0.8
y
S
Detail F
0.20
0.10
*3
e
bp
y
x
ZD
ZE
L
1.0
1.0
0.3 0.5 0.7
1.0
L1
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 70 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
Package Dimensions
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
61
40
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
11.9 12.0 12.1
11.9 12.0 12.1
1.4
80
A2
HD
HE
A
21
13.8 14.0 14.2
13.8 14.0 14.2
1.7
1
20
ZD
Index mark
A1
bp
b1
c
0.1 0.2
0
F
0.15 0.20 0.25
0.18
S
0.09 0.145 0.20
0.125
c1
0°
10°
y
S
*3
bp
e
x
e
L
0.5
x
0.08
0.08
L1
y
ZD
ZE
L
Detail F
1.25
1.25
0.3 0.5 0.7
1.0
L1
JEITA Package Code
P-LQFP80-14x14-0.65
RENESAS Code
PLQP0080JA-A
Previous Code
MASS[Typ.]
0.6g
FP-80W / FP-80WV
HD
*1
D
41
60
61
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Nom Max
Min
D
E
A2
HD
HE
A
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
Terminal cross section
80
21
1
20
A1
bp
b1
0.05
0.15
0.1
ZD
Index mark
0.27 0.32 0.37
0.30
F
c
c1
0.09
0.20
0.145
0.125
S
θ
e
0°
8°
L
0.65
x
y
0.13
0.10
L1
y
S
*3
Detail F
e
bp
×
M
ZD
ZE
L
0.825
0.825
0.5
0.35
0.65
L1
1.0
R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 71 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0100KB-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP100-14x14-0.50
100P6Q-A / FP-100U / FP-100UV
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
76
50
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
Terminal cross section
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
100
26
A1
bp
b1
c
0.1
0.05
0.15
1
25
Index mark
0.15 0.20 0.25
0.18
ZD
F
0.145
0.125
0.09
0.20
S
c1
c
0°
8°
e
0.5
y
S
*3
x
L
0.08
0.08
bp
e
x
y
L1
ZD
ZE
L
1.0
1.0
0.5
1.0
Detail F
0.35
0.65
L1
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JD-B
Previous Code
100P6F-A
MASS[Typ.]
1.8g
HD
*1
D
80
51
81
50
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
Reference
Symbol
Min Nom Max
100
D
E
19.8 20.0 20.2
13.8 14.0 14.2
2.8
31
A2
HD
HE
A
1
30
c
22.5 22.8 23.1
16.5 16.8 17.1
3.05
ZD
Index mark
F
A1
bp
c
0.1 0.2
0.3 0.4
0
0.25
S
0.2
10°
0.13 0.15
0°
0.65
L
*3
e
bp
y
S
x
Detail F
e
x
0.13
0.10
y
ZD
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R01DS0095EJ0101 Rev.1.01
Apr 15, 2011
Page 72 of 72
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group
Datasheet
REVISION HISTORY
Description
Summary
Rev.
Date
Page
0.10 Oct 30, 2009
0.20 Apr 15, 2011
—
6
First Edition issued
Table 1.6 Function deleted, Current consumption revised
1.2 “of R8C/Lx Series” → “for Each Group”
7
7 to 10 Tables 1.7 to 1.10 revised
24
Table 1.15 “Voltage detection circuit” deleted
4. Special Function Registers (SFRs) “The description offered in this
chapter is based on the R8C/L3AC Group.” added
29
45 to 68 5. Electrical Characteristics added
1.00 Jun 25, 2010
—
1
“Preliminary” and “Under development” deleted
1.1 revised
7 to 10 Tables 1.7 to 1.10 revised
45
55
Tables 5.1 Note 2 added
Table 5.15 Note 3 added
69 to 72 Package Dimensions revised
1.01 Apr 15, 2011
2
3
6
Table 1.1 revised
Table 1.2 Note 2, Table 1.3 Note 1 revised
Table 1.6 “Flash Memory” revised
11 to 14 Figure 1.5 to Figure 1.8 revised
20 to 22 Table 1.11 to Table 1.13 “Voltage Detection Circuit” deleted
23, 24
28
Table 1.14 and Table 1.15 title “for R8C/L3AC Group” added
3. “The internal ROM ... with address 0FFFFh.” deleted
38 to 40 Table 4.10 to Table 4.12
“0248h to 026Fh”, “02A8h to 02BFh”, “02C0h to 02CFh” revised
Table 5.3 “tCONV”, “tSAMP” revised
48
57, 59, 61 Table 5.18, Table 5.20, Table 5.22
“High-Speed” → “High-Speed (fOCO-F)”
All trademarks and registered trademarks are the property of their respective owners.
C - 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
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range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
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no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Colophon 1.0
相关型号:
R5F2L368CNFA
These groups have data flash (1 KB × 4 blocks) with the background operation (BGO)
RENESAS
R5F2L368CNFP
These groups have data flash (1 KB × 4 blocks) with the background operation (BGO)
RENESAS
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