R5F35713KFE [RENESAS]
RENESAS MCU; 瑞萨MCU型号: | R5F35713KFE |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | RENESAS MCU |
文件: | 总159页 (文件大小:990K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
M16C/5M Group, M16C/57 Group
RENESAS MCU
REJ03B0267-0101
Rev.1.01
Jul 23, 2010
1. Overview
1.1
Features
The M16C/5M and M16C/57 Group’s microcomputers (MCUs) are single-chip control units that utilize
high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5M
Group and M16C/57 Group are available in 64-pin, 80-pin, and 100-pin plastic molded LQFP packages.
The MCUs employ sophisticated instructions for a high level of efficiency and they are capable of
executing instructions at high speed.
The MCUs have the CAN module (M16C/5M Group) and LIN module, which makes them suitable for
automotive control and factory automation LAN systems. In addition, the CPU core boasts a multiplier and
DMAC for high-speed operation processing which makes it adequate for controlling office equipment,
home appliances, and industrial equipment.
The M16C/5M and M16C/57 Group’s MCUs are a high-end microcontroller series in the M16C/5L and
M16C/56 Group, featuring a single architecture as well as compatible pin assignments and peripheral
2
2
functions. They have an on-chip E PROM emulation data flash (E dataFlash) which is a data flash with
2
serial E PROM.
1.1.1
Applications
Automotive, car audio, factory automation LAN system, etc.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 1 of 156
M16C/5M Group, M16C/57 Group
1. Overview
1.2
Specifications
Table 1.1 to Table 1.6 list specifications of the M16C/5M Group, M16C/57 Group.
Table 1.1
Item
Specifications (100-pin Package) (1/2)
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 ꢀ 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 ꢀ 32 bits))
CPU
Central processing unit
• Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
ROM, RAM, data flash,
E2dataFlash
Memory
See Table 1.7 to Table 1.10.
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-
chip oscillator, 40 MHz on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
Clock
Clock generator
• Real-time clock
Programmable I/O
ports
• 70 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
I/O Ports
Interrupts
• Interrupt vectors: 70
• External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
Watchdog Timer
DMA
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 50
• Transfer modes: 2 (single transfer, repeat transfer)
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Timer A
Timer B
Programmable output mode × 3
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timers
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
Task monitoring timer
Real-time clock
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
Serial
Interface
UART0 to UART4
Multi-master I2C-bus Interface
A/D Converter
1 channel
10-bit resolution × 26 channels
8-bit resolution × 1 channel
D/A Converter
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 2 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.2
Specifications (100-pin Package) (2/2)
Function
Item
Specification
•1 circuit
•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
•MSB/LSB selectable
CRC Calculator
1 channel
•Clock synchronous serial communication mode
•4-wire bus communication mode
•Programmable character length: 8 to 16 bits
Serial Bus Interface
LIN Module
1 channel
(1)
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group)
•Programming and erasure supply voltage: 3.0 to 5.5 V
•Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
Flash Memory
•Program security: ROM code protect, ID code check
E2dataFlash
(1)
Programming and erasure endurance: 100,000
Debug Functions
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Operating Frequency/Power Supply
Voltage
Current Consumption
Described in 31. “Electrical Characteristics”
-40°C to 85°C
Operating Temperature
(1)
-40°C to 125°C
100-pin plastic mold LQFP: PLQP0100KB-A (Previous package code:
100P6Q-A)
Package
Note:
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
2
List (K-Version) for Operating Temperature, CAN Module, and E dataFlash.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 3 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.3
Specifications (80-pin Package) (1/2)
Item
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 ꢀ 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 ꢀ 32 bits))
CPU
Central processing unit
• Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
ROM, RAM, data flash,
E2dataFlash
Memory
See Table 1.7 to Table 1.10.
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-
chip oscillator, 40 MHz on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
Clock
Clock generator
• Real-time clock
Programmable I/O
ports
• 70 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
I/O Ports
Interrupts
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
Watchdog Timer
DMA
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Timer A
Timer B
Programmable output mode × 3
16-bit timer × 3
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timers
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
Task monitoring timer
Real-time clock
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
Serial
Interface
UART0 to UART4
Multi-master I2C-bus Interface
A/D Converter
1 channel
10-bit resolution × 27 channels
8-bit resolution × 1 channel
D/A Converter
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 4 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.4
Specifications (80-pin Package) (2/2)
Function
Item
Specification
•1 circuit
•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
•MSB/LSB selectable
CRC Calculator
1 channel
•Clock synchronous serial communication mode
•4-wire bus communication mode
•Programmable character length: 8 to 16 bits
Serial Bus Interface
LIN Module
1 channel
(1)
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group)
•Programming and erasure supply voltage: 3.0 to 5.5 V
•Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
Flash Memory
•Program security: ROM code protect, ID code check
E2dataFlash
(1)
Programming and erasure endurance: 100,000
Debug Functions
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Operating Frequency/Power Supply
Voltage
Current Consumption
Described in 31. “Electrical Characteristics”
-40°C to 85°C
Operating Temperature
(1)
-40°C to 125°C
Package
Note:
80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A)
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
2
List (K-Version) for Operating Temperature, CAN Module, and E dataFlash.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 5 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.5
Specifications (64-pin Package) (1/2)
Item
Function
Specification
M16C/60 Series CPU Core (Multiplier: 16 × 16 ꢀ 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 ꢀ 32 bits))
CPU
Central processing unit
• Basic instructions: 91
• Minimum instruction execution time:
• Operating mode: Single-chip mode
ROM, RAM, data flash,
E2dataFlash
Memory
See Table 1.7 to Table 1.10.
Voltage
Detection
Voltage detector
• 2 voltage detect points
• 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz on-
chip oscillator, 40 MHz on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
Clock
Clock generator
• Real-time clock
Programmable I/O
ports
• 54 CMOS inputs/outputs, a pull-up resistor selectable
• N-channel open drain ports: 1
I/O Ports
Interrupts
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• Dedicated 125 kHz on-chip oscillator for the watchdog timer contained
Watchdog Timer
DMA
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 41
• Transfer modes: 2 (single transfer, repeat transfer)
DMAC
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Timer A
Timer B
Programmable output mode × 3
16-bit timer × 3
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timers
Timer function for three- Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
Timer S (Input capture/
output compare)
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
Task monitoring timer
Real-time clock
16-bit timer × 1 channel
Count: seconds, minutes, hours, weeks
3 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)
Serial
Interface
UART0 to UART3
Multi-master I2C-bus Interface
A/D Converter
1 channel
10-bit resolution × 16 channels
8-bit resolution × 1 channel
D/A Converter
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 6 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.6
Specifications (64-pin Package) (2/2)
Function
Item
Specification
•1 circuit
•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
•MSB/LSB selectable
CRC Calculator
1 channel
•Clock synchronous serial communication mode
•4-wire bus communication mode
•Programmable character length: 8 to 16 bits
Serial Bus Interface
LIN Module
1 channel
(1)
CAN Module
32-slot message buffer × 2 channels or 1 channel (M16C/5M Group)
•Programming and erasure supply voltage: 3.0 to 5.5 V
•Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
Flash Memory
•Program security: ROM code protect, ID code check
E2dataFlash
(1)
Programming and erasure endurance: 100,000
Debug Functions
On-board flash rewrite function, address match × 4
32 MHz / 3.0 to 5.5 V
Operating Frequency/Power Supply
Voltage
Current Consumption
Described in 31. “Electrical Characteristics”
-40°C to 85°C
Operating Temperature
(1)
-40°C to 125°C
Package
Note:
64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A)
1. Refer to Table 1.7 “M16C/5M Group Product List (J-Version)” to Table 1.10 “M16C/57 Group Product
2
List (K-Version) for Operating Temperature, CAN Module, and E dataFlash.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 7 of 156
M16C/5M Group, M16C/57 Group
1. Overview
1.3
Product List
Table 1.7 to Table 1.8 list product informations. Figure 1.1 shows part numbers, memory sizes, and
packages. Figure 1.2 shows marking drawing (top view).
Table 1.7
M16C/5M Group Product List (J-Version)
As of May. 2010
ROM Capacity
RAM
Capacity
CAN
Part Number
Package Name Remarks
Program
ROM 1
Program
ROM 2
E2dataFlash
4 Kbytes
Data flash
R5F35M23JFE (P)
R5F35M33JFF (P)
R5F35M73JFE (P)
R5F35M83JFF (P)
R5F35M16JFB (P)
R5F35M26JFE (P)
R5F35M36JFF (P)
R5F35M66JFB (P)
R5F35M76JFE (P)
R5F35M86JFF (P)
R5F35M1EJFB (P)
R5F35M2EJFE (P)
R5F35M3EJFF (P)
R5F35M6EJFB (P)
R5F35M7EJFE (P)
R5F35M8EJFF (P)
R5F35MB3JFE (P)
R5F35MC3JFF (P)
R5F35ME3JFE (P)
R5F35MF3JFF (P)
R5F35MA6JFB (P)
R5F35MB6JFE (P)
R5F35MC6JFF (P)
R5F35MD6JFB (P)
R5F35ME6JFE (P)
R5F35MF6JFF (P)
R5F35MAEJFB (D)
R5F35MBEJFE (D)
R5F35MCEJFF (D)
R5F35MDEJFB (P)
R5F35MEEJFE (P)
R5F35MFEJFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
4 Kbytes
× 2 blocks
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
8 Kbytes
—–
4 Kbytes
4 Kbytes
× 2 blocks
12 Kbytes
1 channel
—–
4 Kbytes
—–
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
20 Kbytes
8 Kbytes
12 Kbytes
Operating
Temperature
-40°C to 85°C
PLQP0064KB-A
PLQP0080KB-A
4 Kbytes
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
× 2 blocks
—–
4 Kbytes
—–
4 Kbytes
× 2 blocks
2 channels
4 Kbytes
—–
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
20 Kbytes
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 8 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.8
Part Number
M6C/5M Group Product List (K-Version)
ROM Capacity
As of May. 2010
RAM
Capacity
CAN
Package Name Remarks
Program
ROM 1
Program
ROM 2
E2dataFlash
Data flash
R5F35M23KFE (P)
R5F35M33KFF (P)
R5F35M73KFE (P)
R5F35M83KFF (P)
R5F35M16KFB (P)
R5F35M26KFE (P)
R5F35M36KFF (P)
R5F35M66KFB (P)
R5F35M76KFE (P)
R5F35M86KFF (P)
R5F35M1EKFB (P)
R5F35M2EKFE (P)
R5F35M3EKFF (P)
R5F35M6EKFB (P)
R5F35M7EKFE (P)
R5F35M8EKFF (P)
R5F35MB3KFE (P)
R5F35MC3KFF (P)
R5F35ME3KFE (P)
R5F35MF3KFF (P)
R5F35MA6KFB (P)
R5F35MB6KFE (P)
R5F35MC6KFF (P)
R5F35MD6KFB (P)
R5F35ME6KFE (P)
R5F35MF6KFF (P)
R5F35MAEKFB (P)
R5F35MBEKFE (P)
R5F35MCEKFF (P)
R5F35MDEKFB (P)
R5F35MEEKFE (P)
R5F35MFEKFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
4 Kbytes
× 2 blocks
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
8 Kbytes
—–
4 Kbytes
4 Kbytes
× 2 blocks
12 Kbytes
1 channel
—–
4 Kbytes
—–
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
20 Kbytes
8 Kbytes
12 Kbytes
Operating Tem-
perature
-40°C to 125°C
4 Kbytes
4 Kbytes
× 2 blocks
—–
4 Kbytes
—–
4 Kbytes
× 2 blocks
2 channels
4 Kbytes
—–
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
20 Kbytes
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 9 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.9
M16C/57 Group Product List (J-Version)
ROM Capacity
As of May. 2010
RAM
Capacity
CAN
Part Number
Package Name Remarks
Program
ROM 1
Program
ROM 2
E2dataFlash
Data flash
R5F35723JFE (P)
R5F35733JFF (P)
R5F35773JFE (P)
R5F35783JFF (P)
R5F35716JFB (P)
R5F35726JFE (P)
R5F35736JFF (P)
R5F35766JFB (P)
R5F35776JFE (P)
R5F35786JFF (P)
R5F3571EJFB (P)
R5F3572EJFE (P)
R5F3573EJFF (P)
R5F3576EJFB (P)
R5F3577EJFE (P)
R5F3578EJFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
4 Kbytes
× 2 blocks
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
8 Kbytes
—–
4 Kbytes
4 Kbytes
× 2 blocks
12 Kbytes
Operating
Temperature
-40°C to 85°C
N/A
—–
4 Kbytes
—–
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
20 Kbytes
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
Table 1.10
M16C/57 Group Product List (K-Version)
As of May. 2010
ROM Capacity
RAM
Capacity
CAN
Part Number
Package Name Remarks
Program
ROM 1
Program
ROM 2
E2dataFlash
4 Kbytes
Data flash
R5F35723KFE (P)
R5F35733KFF (P)
R5F35773KFE (P)
R5F35783KFF (P)
R5F35716KFB (P)
R5F35726KFE (P)
R5F35736KFF (P)
R5F35766KFB (P)
R5F35776KFE (P)
R5F35786KFF (P)
R5F3571EKFB (P)
R5F3572EKFE (P)
R5F3573EKFF (P)
R5F3576EKFB (P)
R5F3577EKFE (P)
R5F3578EKFF (P)
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
× 2 blocks
96 Kbytes 16 Kbytes
128 Kbytes 16 Kbytes
8 Kbytes
—–
4 Kbytes
4 Kbytes
× 2 blocks
12 Kbytes
Operating
Temperature
-40°C to 125°C
PLQP0100KB-A
N/A
PLQP0080KB-A
—–
4 Kbytes
—–
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
× 2 blocks
256 Kbytes 16 Kbytes
20 Kbytes
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP00100KB-A: 100P6Q-A
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 10 of 156
M16C/5M Group, M16C/57 Group
1. Overview
MCU Part No. R 5 F 3 5M 2 E J FE
Package type
FB: PLQP0100KB-A (100P6Q-A)
FE: PLQP0080KB-A (80P6Q-A)
FF: PLQP0064KB-A (64P6Q-A)
Property code
J: Operating temperature -40°C to 85°C
K: Operating temperature -40°C to 125°C
Memory capacity
Program ROM 1/RAM
3: 96 Kbytes/8 Kbytes
6: 128 Kbytes/12 Kbytes
E: 256 Kbytes/20 Kbytes
Pin / CAN module / E2 data flash capacity
1: 100 pins / 1 channel / 4 Kbytes
2: 80 pins / 1 channel / 4 Kbytes
3: 64 pins / 1 channel / 4 Kbytes
6: 100 pins / 1 channel / —
7: 80 pins / 1 channel / —
57 Group has no CAN Module
8: 64 pins / 1 channel / —
A: 100 pins / 2 channels / 4 Kbytes
B: 80 pins / 2 channels / 4 Kbytes
C: 64 pins / 2 channels / 4 Kbytes
D: 100 pins / 2 channels / —
E: 80 pins / 2 channels / —
F: 64 pins / 2 channels / —
Group Name
5M: M16C/5M Group,
57: M16C/57 Group
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package
16C
amber
(See Figure 1.1 “Part Number, Memory Size, and Package”.)
5 F32 J FE
X X X
even diit date code
Figure 1.2
Marking Diagram of Flash Memory Version (Top View)
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Jul 23, 2010
Page 11 of 156
M16C/5M Group, M16C/57 Group
1. Overview
1.4
Block Diagrams
Figure 1.3 to Figure 1.5 show a block diagram of M16C/5M Group and M16C/57 Group.
8
8
8
8
8
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Peripherals
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
UART/clock synchronous serial
interface (5 channels)
Clock generator
XIN-XOUT
XCIN-XCOUT
DMAC (4 channels)
Three-phase motor control circuit
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
Multi-master I2C-bus (1 channel)
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
LIN module (1 channel)
CRC calculator
(CCITT, CRC-16)
CAN module
(32-slot message buffer,
2 or 1 channel)
Task monitoring timer (1 channel)
Real-time clock
Voltage detector
Power-on reset
(1)
(M16C/5M Group only)
E2dataFlash (1)
On-chip debugger
A/D converter
(10-bit x 26 channel)
Memory
ROM (1)
D/A converter (8-bit x 1 circuit)
M16C/60 Series CPU core
Serial bus interface
(1 channel)
R0H
R1H
R0L
R1L
SB
USP
ISP
RAM (1)
R2
R3
Watchdog timer (15 bits,
with the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
R3
INTB
PC
A0
A1
FB
Multiplier
FLG
FB
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not
depend on the MCU type.
Figure 1.3
100-Pin Block Diagram
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 12 of 156
M16C/5M Group, M16C/57 Group
1. Overview
8
8
8
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Peripherals
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
UART/clock synchronous serial
interface (5 channels)
Clock generator
XIN-XOUT
DMAC (4 channels)
Multi-master I2C-bus (1 channel)
LIN module (1 channel)
XCIN-XCOUT
Three-phase motor control circuit
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
CAN module
(32-slot message buffer,
2 or 1 channel)
CRC calculator
(CCITT, CRC-16)
Task monitoring timer (1 channel)
Real-time clock
(1)
(M16C/5M Group only)
Voltage detector
Power-on reset
E2dataFlash (1)
On-chip debugger
A/D converter
(10-bit x 27 channel)
D/A converter (8-bit x 1 circuit)
M16C/60 Series CPU core
Memory
ROM (1)
Serial bus interface
(1 channel)
R0H
R1H
R0L
R1L
SB
USP
ISP
R2
R3
RAM (1)
Watchdog timer (15 bits,
with the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
R3
INTB
PC
A0
A1
FB
Multiplier
FLG
FB
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not
depend on the MCU type.
Figure 1.4
80-Pin Block Diagram
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Jul 23, 2010
Page 13 of 156
M16C/5M Group, M16C/57 Group
1. Overview
4
3
8
4
I/O ports
Port P0
Port P1
Port P2
Port P3
Peripherals
UART/clock synchronous serial
interface (4 channels)
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
Clock generator
XIN-XOUT
XCIN-XCOUT
DMAC(4 channels)
Multi-master I2C-bus (1 channel)
LIN module (1 channel)
40 MHz on-chip oscillator
125 kHz on-chip oscillator
PLL frequency synthesizer
Three-phase motor control circuit
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
CAN module
(32-slot message buffer,
2 or 1 channel)
CRC calculator
(CCITT, CRC-16)
(1)
(M16C/5M Group only)
Task monitoring timer (1 channel)
Real-time clock
Voltage detector
Power-on reset
E2dataFlash (1)
On-chip debugger
A/D converter
(10-bit x 16 channels)
Memory
ROM (1)
D/A converter (8-bit x 1 circuit)
M16C/60 Series CPU core
R0H
R1H
R0L
R1L
SB
Serial bus interface
(1 channel)
USP
ISP
R2
R3
RAM (1)
Watchdog timer (15 bits,
the dedicated 125 kHz on-chip
oscillator for the watchdog timer)
R3
INTB
PC
A0
A1
FB
Multiplier
FLG
FB
Note:
1. The ROM size, RAM size, number of channels for the CAN module, and whether the E2dataFlash is provided or not
depend on the MCU type.
Figure 1.5
64-Pin Block Diagram
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 14 of 156
M16C/5M Group, M16C/57 Group
1. Overview
1.5
Pin Assignments
Figure 1.6 shows the pin assignments for the 100-pin package, Figure 1.7 shows the pin assignments for
the 80-pin package, and Figure 1.8 shows the pin assignments for the 64-pin package.
P1_2 / AN2_2
P1_1 / AN2_1
P1_0 / AN2_0
P0_7 / AN0_7
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P4_2
P4_3
P4_4
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
M16C/5M Group
M16C/57 Group
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P5_7
PLQP0100KB-A
(100P6Q-A)
(Top view)
P6_0 / RTCOUT / CTS0 / RTS0
P6_1 / CLK0
P6_2 / RXD0
P6_3 / TXD0
P6_4 / CTS1 / RTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / CTS1 / RTS1 / TA0OUT
P7_1 / RXD2 / SCL2 / CLK1 / TA0IN / TB5IN
P7_2 / CLK2 / TA1OUT / V / RXD1
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
VREF
AVCC
P9_7 / RXD4 / AN2_7
P9_6 / TXD4 / CTX0 (1) / AN2_6
P9_5 / CLK4 / CRX0 (1) / AN2_5
26
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.6
Pin Assignments for 100-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 100b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 15 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Analog Pin
Table 1.11
Pin Names, 100-Pin Package(1/2)
Multi-
master
I2C-bus Pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
TB4IN
Timer S Pin
No.
Pin
1
2
3
4
5
6
7
8
9
P9_4
P9_3
P9_2
P9_1
TB3IN
TB2IN
TB1IN
TB0IN
DA0
AN3_2
AN3_1
AN3_0
CLKOUT P9_0
NC
CNVSS
XCIN
P8_7
P8_6
XCOUT
10 RESET
11 XOUT
12 VSS
13 XIN
14 VCC
15
16
17
18
19
20
21
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
NMI
SD
ZP
INT2
INT1
INT0
TA4IN/U
TA4OUT/U
TA3IN
TSUDB
TSUDA
(1)
CRX1
(1)
P7_6
TA3OUT
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CTX1
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
TA2IN/W
TA2OUT/W
LIN0IN
LIN0OUT
TA1IN/V
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
TA1OUT/V
TA0IN/TB5IN
TA0OUT
RXD1
CLK1
CTS1/RTS1
TXD0
RXD0
CLK0
RTCOUT
CTS0/RTS0
Note:
1. There are pins CTX1 and CRX1 only in the M16C/5M Group.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 16 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Analog Pin
Table 1.12
Pin Names, 100-Pin Package(2/2)
Multi-
master I2C-
bus Pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
Timer S Pin
No.
Pin
51
52
53
54
55
56
57
58
59
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
CTS3/RTS3/SCS0
TXD3/SSO0
RXD3/SSI0
60 VCC
61
P3_0
CLK3/SSCK0
VSS
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
INT7
INT6
SCLMM
SDAMM
INT5
INT4
INT3
IDU
IDW
IDV
ADTRG
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
P10_7 KI3
P10_6 KI2
P10_5 KI1
P10_4 KI0
P10_3
AN_6
AN_5
AN_4
AN_3
P10_2
AN_2
P10_1
AN_1
94 AVSS
95
P10_0
AN_0
96 VREF
97 AVCC
98
P9_7
P9_6
RXD4
AN2_7
AN2_6
(1)
99
TXD4/CTX0
(1)
P9_5
AN2_5
100
CLK4/CRX0
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.
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Jul 23, 2010
Page 17 of 156
M16C/5M Group, M16C/57 Group
1. Overview
61
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P6_3 / TXD0
P3_0 / CLK3 / SSCK0
P3_1 / RXD3 / SSI0
P3_2 / TXD3 / SSO0
P3_3 / CTS3 / RTS3 / SCS0
P3_4
P3_5
P3_6
P3_7
P6_4 / CTS1 / RTS1
P6_5 / CLK1
62
63
64
65
66
M16C/5M Group
M16C/57 Group
67
68
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
69
70
71
PLQP0080KB-A
(80P6Q-A)
72
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
P6_6 / RXD1
P6_7 / TXD1
73
74
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W / LIN0OUT
P7_5 / TA2IN / W / LIN0IN
75
(Top view)
76
77
VREF
AVCC
P9_7 / AN2_7 / RXD4
P9_6 / AN2_6 / TXD4
78
79
P7_6 / TA3OUT / CTX1 (1)
80
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.7
Pin Assignment for 80-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 011b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 18 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Analog Pin
Table 1.13
Pin Names, 80-Pin Package (1/2)
Multi-
master
I2C-bus
pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
Timer S Pin
No.
pin
1
2
3
P9_5
P9_3
CLK4
AN2_5
AN2_4
(1)
(1)
CTX0
CRX0
P9_2
P9_1
TB2IN
AN3_2
TB1IN
AN3_1/
DA0
4
5
6
7
8
9
CLKOUT P9_0
CNVSS
TB0IN
AN3_0
XCIN
P8_7
XCOUT P8_6
RESET
10 XOUT
11 VSS
12 XIN
13 VCC
14
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
NMI
SD
ZP
15
INT2
INT1
INT0
16
17
TSUDB
TSUDA
18
TA4IN/U
TA4OUT/U
TA3IN
19
(1)
(1)
20
CRX1
CTX1
P7_6
TA3OUT
21
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P3_0
P6_3
LIN0IN
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN
LIN0OUT
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
TA0OUT
RXD1
CLK1
CTS1/RTS1
CTS3/RTS3/SCS0
TXD3/SSO0
RXD3/SSI0
CLK3/SSCK0
TXD0
Note:
1. Pins CTX0, CRX0, CTX1 and CRX1 are only available in the M16C/5M Group.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 19 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.14
Pin Names, 80-Pin Package (2/2)
Multi-
master
I2C-bus
pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
Timer S Pin
Analog Pin
No.
pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
P6_2
P6_1
P6_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
RXD0
CLK0
RTCOUT
CTS0/RTS0
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
SCLMM
SDAMM
IDU
IDW
IDV
INT5
INT4
INT3
ADTRG
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
KI3
KI2
KI1
KI0
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
75 AVSS
76
P10_0
AN_0
77 VREF
78 AVCC
79
P9_7
P9_6
RXD4
TXD4
AN2_7
AN2_6
80
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Jul 23, 2010
Page 20 of 156
M16C/5M Group, M16C/57 Group
1. Overview
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P3_0 / CLK3 / SSCK0
P3_1 / RXD3 / SSI0
P3_2 / TXD3 / SSO0
P3_3 / CTS3 / RTS3 / SCS0
P6_4 / RTS1 / CTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W / LIN0OUT
P7_5 / TA2IN / W / LIN0IN
P7_6 / TA3OUT / CTX1 (1)
P7_7 / TA3IN / CRX1 (1)
50
51
52
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
M16C/5M Group
M16C/57 Group
53
54
55
56
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
57
PLQP0064KB-A
(64P6Q-A)
58
59
60
61
VREF
AVCC
(Top view)
62
P9_3 / AN2_4 /CTX0 (1)
63
P9_2 / AN3_2 / TB2IN / CRX0 (1)
64
Note:
1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.8
Pin Assignments for 64-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 21 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.15
Pin Names, 64-Pin Package (1/2)
Multi-
master
I2C-bus
Pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
Timer S Pin
Analog Pin
No.
pin
P9_1
TB1IN
AN3_1/
DA0
1
2
3
4
5
6
7
8
9
CLKOUT P9_0
CNVSS
TB0IN
AN3_0
XCIN
P8_7
XCOUT P8_6
RESET
XOUT
VSS
XIN
10 VCC
11
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
SD
NMI
ZP
12
INT2
INT1
INT0
13
14
TSUDB
TSUDA
15
TA4IN/U
TA4OUT/U
TA3IN
16
(1)
17
CRX1
(1)
TA3OUT
18
CTX1
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P3_3
P3_2
LIN0IN
19
20
21
22
23
24
25
26
27
28
29
30
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN
LIN0OUT
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
TA0OUT
RXD1
CLK1
CTS1/RTS1
CTS3/RTS3 / SCS0
TXD3 / SSO0
Note:
1. Pins CTX1 and CRX1 are only available in the M16C/5M Group.
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1. Overview
Table 1.16
Pin Names, 64-Pin Package (2/2)
Multi-
master
I2C-bus
pin
Pin Control
Interrupt
Pin
UART/CAN/LIN/Serial
Bus Interface Pin
Port
Timer Pin
Timer S Pin
Analog Pin
No.
pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
P3_1
P3_0
P6_3
P6_2
P6_1
P6_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
RXD3 / SSI0
CLK3 / SSCK0
TXD0
RXD0
CLK0
RTCOUT
CTS0/RTS0
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
SCLMM
SDAMM
IDU
IDW
IDV
INT5
INT4
INT3
ADTRG
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
KI3
KI2
KI1
KI0
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
59 AVSS
60
P10_0
AN_0
61 VREF
62 AVCC
63
(1)
P9_3
P9_2
AN2_4
AN3_2
CTX0
(1)
TB2IN
64
CRX0
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.
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1. Overview
1.6
Pin Functions
Table 1.17
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Signal Name
Pin Name
VCC, VSS
I/O
I
Description
Power supply
Apply 3.0 V to 5.5 V to the VCC pin and 0 V to the VSS pin.
Power supply for the A/D converter and D/A converter. Pins
AVCC and AVSS should be connected to VCC and VSS,
respectively.
Analog power
supply
AVCC,
AVSS
I
Reset input
CNVSS
RESET
CNVSS
XIN
I
I
Driving this pin low resets the MCU.
Connect to VSS via a resistor.
Main clock input
Input/output for the main clock oscillator. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. (1)
To apply an external clock, connect it to XIN and leave XOUT
open. When XIN is not used, connect XIN to VCC pin and leave
XOUT open.
I
Main clock output
XOUT
O
Sub clock input
Sub clock output
XCIN
I
Input/output for the sub clock oscillator. Connect a crystal
(1)
oscillator between XCIN and XCOUT.
XCOUT
O
This pin outputs the clock having the same frequency as f1, f8,
f32, or fC.
Clock output
CLKOUT
O
INT interrupt input INT0 to INT5
NMI input NMI
I
I
I
Input for INT interrupt
Input for NMI
Key input interrupt KI0 to KI3
Input for the key input interrupt
TA0OUT to
I/O Timers A0 to A4 input/output
TA4OUT
Timer A
TA0IN to TA4IN
I
I
Timers A0 to A4 input
ZP
Input for Z-phase
Timer B
TB0IN to TB2IN
U,U,V,V,W,W
IDU, IDW, IDV, SD
RTCOUT
I
Timers B0 to B2 input
O
I
Output for three-phase motor control timer
Input for three-phase motor control timer
Output for real-time clock
Three-phase motor
control timer
Real-time clock
O
I
CTS0 to CTS3
RTS0 to RTS3
CLK0 to CLK3
RXD0 to RXD3
TXD0 to TXD3
SDA2
Input to control data transmission
Output to control data reception
O
Serial interface
UART0 to UART3
I/O Transfer clock input/output
I
Serial data input
Serial data output
O
I/O Serial data input/output
UART2
I2C mode
SCL2
I/O Transfer clock input/output
SDAMM
Serial data input/output
I/O
Multi-master I2C
bus
SCLMM
Transfer clock input/output
Note:
1. Please contact the oscillator manufacturer for oscillation characteristic.
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M16C/5M Group, M16C/57 Group
1. Overview
Table 1.18
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Signal Name
Pin Name
I/O
I
Description
Reference voltage
input
VREF
Reference voltage input for the A/D converter and D/A converter.
AN_0 to AN_7
AN0_0 to AN0_3
AN3_0 to AN3_2
I
Analog input
A/D converter
Timer S
ADTRG
I
I
Input for an external trigger
INPC1_0 to INPC1_7
OUTC1_0 to OUTC1_7
TSUDA, TSUDB
CRX0, CRX1
CTX0, CTX1
DA0
Input for time measurement function
Output for waveform generating function
Two-phase pulse input
O
I
I
Receive data input for CAN communication
Transmit data output for CAN communication
Output for the D/A converter
(1)
CAN Module
O
O
O
I
D/A converter
LIN module
LIN0OUT
Transmit data output for LIN communication
Receive data input for LIN communication
Serial data output
LIN0IN
SSO0
O
I
SSI0
Serial data input
Serial bus interface
SSCK0
I/O Input/output for transmit/receive clock
SCS0
I
Input to control the serial interface
P0_0 to P0_3
P1_5 to P1_7
P2_0 to P2_7
P3_0 to P3_3
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_3
P10_0 to P10_7
CMOS I/O ports. A direction register determines whether each
pin is used as an input port or an output port. For input ports,
pull-up resistor is selectable for every unit of 4 bits.
However, P8_5 output is N-channel open drain output and does
not have a pull-up resistor.
I/O port
Note:
I/O
Port P8_5 shares the pin with NMI, so that the NMI input level
can be read from the P8 register P8_5 bit.
1. There is the CAN module only in the M16C/5M Group.
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1. Overview
Table 1.19
Signal Name
INT interrupt input INT6 and INT7
Pin Functions (100-Pin Package Only)
Pin Name
I/O
Description
I
Input for INT interrupt
Timer B
TB3IN to TB5IN
Timers B3 to B5 input
I
P4_0 to P4_7
P5_0 to P5_7
P9_4
CMOS I/O ports. A direction register determines whether each
pin is used as an input port or an output port. For input ports,
pull-up resistor is selectable for every unit of 4 bits.
I/O port
I/O
Table 1.20
Pin Functions (80-Pin and 64-Pin Package Only)
Signal Name
Pin Name
AN2_4
I/O
I
Description
A/D converter
Analog input
Table 1.21
Pin Functions (100-Pin and 80-Pin Package Only)
Signal Name
Pin Name
I/O
I/O
I
Description
CLK4
RXD4
TXD4
Transfer clock input/output
Serial data input
Serial Interface
UART4
Serial data output
O
AN0_4 to AN0_7
AN2_0 to AN2_3
AN2_5 to AN2_7
A/D converter
I/O port
Analog input
I
P0_4 to P0_7
P1_0 to P1_4
P3_4 to P3_7
P9_5 to P9_7
CMOS I/O ports. A direction register determines whether each
pin is used as an input port or an output port. For input ports,
Pull-up resistor is selectable for every unit of 4 bits.
I/O
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2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
b15
R0H (upper bits of R0)
b8b7
b0
R2
R3
R0L (lower bits of R0)
R1L (lower bits of R1)
R1H (upper bits of R1)
Data registers (1)
R2
R3
A0
A1
FB
Address registers (1)
Frame base registers (1)
b19
b15
b0
INTBH
INTBL
Interrupt table register
INTBH is the 4 upper bits of the INTB register and INTBL
is the 16 lower bits.
b19
b0
PC
Program counter
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
FLG
O
Flag register
b15
b8 b7
U
IPL
I
B
S
Z
D
C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1
CPU Registers
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2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
2.2
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register that is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes
0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O Flag)
The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
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2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10 Reserved Areas
Only set these bits to 0. The read value is undefined.
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M16C/5M Group, M16C/57 Group
3. Memory
3. Memory
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved,
so do not access any blank spaces.
The internal RAM is allocated from address 00400h to superior direction. For example, a 8-Kbyte internal
RAM is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for
stack area when subroutines are called or when interrupt request are acknowledged.
2
The internal ROM is flash memory. Four internal ROM areas are available: E dataFlash, data flash,
program ROM 1, and program ROM 2.
The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage
but also for program storage.
Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses
FFFFFh to inferior direction. For example, the 64-Kbyte program ROM 1 space has addresses F0000h to
FFFFFh.
2
The E dataFlash is not shown in the memory map because the E2FA register value is used as an address.
2
2
The E dataFlash cannot be used for program storage. Whether the E dataFlash is provided or not depends
on the product.
The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS
instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for
details.
The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned
addresses FFFDBh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
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3. Memory
00000h
00400h
SFRs
Relocatable vector table
Internal RAM
256 bytes beginning with the start
address set in the INTB register
XXXXXh
Reserved (1)
0D000h
0D800h
0E000h
SFRs
Reserved (1)
13000h
On-chip debugger
monitor area
Internal ROM
(Data flash)
13FF0h
13FFFh
10000h
14000h
Internal ROM
(Program ROM 2)
Internal RAM
User boot code area
Capacity
8 Kbytes
12 Kbytes
20 Kbytes
XXXXXh
023FFh
033FFh
053FFh
Reserved (1)
FFE00h
Special page vector
table
Internal ROM
Capacity
96 Kbytes
128 Kbytes
256 Kbytes
YYYYYh
E8000h
E0000h
C0000h
FFFD8h
FFFDBh
Reserved (2)
YYYYYh
FFFFFh
Fixed vector table
ID code write address
OFS1 address
Internal ROM
(Program ROM 1)
OSF2 address
FFFFFh
The above assumes the following:
-The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash)
-The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)
Notes:
1. Do not access these reserved areas.
2. Do not change the data from FFh.
Figure 3.1
Memory Map
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4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
4.1
SFRs
An SFR is a control register for a peripheral function.
Table 4.1
SFR Information (1) (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
Register
Symbol
Reset Value
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
CM0
CM1
00h
0000 1000b
0100 1000b
0010 0000b
System Clock Control Register 0
System Clock Control Register 1
000Ah Protect Register
000Bh
000Ch Oscillation Stop Detection Register
PRCR
CM2
00h
0X00 0010b (3)
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
Program 2 Area Control Register
Peripheral Clock Select Register
PRG2C
PCLKR
XXXX XX00b
0000 0011b
Clock Prescaler Reset Flag
CPSRF
0XXX XXXXb
XX0X 001Xb
(hardware reset) (4)
0018h
0019h
Reset Source Determine Register
Voltage Detector 2 Flag Register
RSTFR
VCR1
(2)
0000 1000b
000X 0000b (2, 5)
001X 0000b(2, 6)
001Ah Voltage Detector Operation Enable Register
VCR2
001Bh
PLC0
PM2
001Ch PLL Control Register 0
001Dh
001Eh Processor Mode Register 2
001Fh
0X01 X010b
XX00 0X01b
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the
following registers: the VCR1 register and the VCR2 register.
3.
4.
5.
6.
Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
The state of bits in the RSTFR register depends on the reset type.
This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset.
This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0
during hardware reset.
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4. Special Function Registers (SFRs)
Table 4.2
SFR Information (2) (1)
Address
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
Register
Symbol
Reset Value
40 MHz On-Chip Oscillator Control Register 0
40 MHz On-Chip Oscillator Control Register 2
Voltage Monitor Function Select Register
Voltage Detector 2 Level Select Register
FRA0
FRA2
XXXX XX00b
0XX0 X000b
00h
VWCE
VD2LS
(2)
0000 0100b
(3, 4)
1100 1X10b
002Ah Voltage Monitor 0 Control Register
VW0C
VW2C
1100 1X11b (3, 5)
002Bh
002Ch Voltage Monitor 2 Control Register
1000 0X10b(3, 6)
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
X: Undefined
Notes:
1.
2.
3.
The blank areas are reserved. No access is allowed.
Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset.
Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the
following registers or bit: the VW0C register, and bits VW2C2 and VW2C3 in the VW2C register.
This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset
This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0
during hardware reset.
4.
5.
6.
This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset
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4. Special Function Registers (SFRs)
Table 4.3
SFR Information (3) (1)
Address
0040h
Register
Symbol
E2FIC
Reset Value
E2dataFlash Interrupt Control Register
0041h
XXXX X000b
XX00 X000b
INT7IC
SS0IC
INT7 Interrupt Control Register
Serial Bus Interface 0 Interrupt Control Register
0042h
0043h
INT6IC
LIN0IC
INT6 Interrupt Control Register
LIN0 Interrupt Control Register
XX00 X000b
0044h
0045h
0046h
0047h
INT3 Interrupt Control Register
INT3IC
TB5IC
TB4IC
TB3IC
XX00 X000b
XXXX X000b
XXXX X000b
XXXX X000b
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register
Timer B3 Interrupt Control Register
0048h
0049h
INT5 Interrupt Control Register
INT5IC
XX00 X000b
XX00 X000b
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
Task Monitoring Timer Interrupt Control Register
INT4IC
BCNIC
TMOSIC
004Ah
XXXX X000b
004Bh DMA0 Interrupt Control Register
DM0IC
DM1IC
KUPIC
ADIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
004Ch DMA1 Interrupt Control Register
004Dh Key Input Interrupt Control Register
004Eh A/D Conversion Interrupt Control Register
004Fh UART2 Transmit Interrupt Control Register
S2TIC
S2RIC
0050h
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
LIN0 Low Detection Interrupt Control Register
S0TIC
L0WIC
0051h
XXXX X000b
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
005Ah Timer B0 Interrupt Control Register
005Bh Timer B1 Interrupt Control Register
005Ch Timer B2 Interrupt Control Register
005Dh INT0 Interrupt Control Register
005Eh INT1 Interrupt Control Register
005Fh INT2 Interrupt Control Register
INT0IC
INT1IC
INT2IC
XX00 X000b
XX00 X000b
XX00 X000b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.4
SFR Information (4) (1)
Address
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
Register
Symbol
Reset Value
DMA2 Interrupt Control Register
DMA3 Interrupt Control Register
DM2IC
DM3IC
C1RIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
CAN 1 Receive Completion Interrupt Control Register
CAN 1 Transmit Completion Interrupt Control Register
CAN 1 Receive FIFO Interrupt Control Register
CAN 1 Transmit FIFO Interrupt Control Register
UART4 Transmit Interrupt Control Register
Real-Time Clock Compare Interrupt Control Register
UART4 Receive Interrupt Control Register
CAN0 Wakeup Interrupt Control Register
UART3 Transmit Interrupt Control Register
CAN0 Error Interrupt Control Register
C1TIC
C1FRIC
C1FTIC
S4TIC
RTCCIC
S4RIC
C0WIC
S3TIC
C0EIC
006Fh
XXXX X000b
0070h
0071h
XXXX X000b
XXXX X000b
0072h
0073h
0074h
XXXX X000b
XXXX X000b
XXXX X000b
UART3 Receive Interrupt Control Register
CAN 1 Wakeup Interrupt Control Register
Real-Time Clock Cycle Interrupt Control Register
CAN 1 Error Interrupt Control Register
S3RIC
C1WIC
RTCTIC
C1EIC
0075h
0076h
0077h
0078h
0079h
007Ah
CAN0 Receive Completion Interrupt Control Register
CAN0 Transmit Completion Interrupt Control Register
CAN0 Receive FIFO Interrupt Control Register
CAN0 Transmit FIFO Interrupt Control Register
IC/OC Interrupt 0 Control Register
IC/OC Channel 0 Interrupt Control Register
IC/OC Interrupt 1 Control Register
I2C-bus Interface Interrupt Control Register
IC/OC Channel 1 Interrupt Control Register
SCL/SDA Interrupt Control Register
C0RIC
C0TIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
C0FRIC
C0FTIC
ICOC0IC
ICOCH0IC
ICOC1IC
IICIC
ICOCH1IC
SCLDAIC
ICOCH2IC
ICOCH3IC
BTIC
007Bh
007Ch
XXXX X000b
XXXX X000b
007Dh
007Eh
007Fh
IC/OC Channel 2 Interrupt Control Register
IC/OC Channel 3 Interrupt Control Register
IC/OC Base Timer Interrupt Control Register
XXXX X000b
XXXX X000b
XXXX X000b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 35 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.5
SFR Information (5) (1)
Register
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
Symbol
E2FA
Reset Value
00h
00h
XXh
XXh
E2dataFlash Address Register
E2FI
00h
XXh
E2dataFlash Command Register
E2dataFlash Data Register
XXh
XXh
E2FD
E2dataFlash Mode Register
E2dataFlash Control Register
E2dataFlash Status Register 1
E2FM
E2FC
00h
XXXX XXX0b
XXXX XXX0b
E2FS1
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h to
015Fh
E2dataFlash Status Register 0
E2FS0
0X00 XXXXb
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 36 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.6
Address
0160h
SFR Information (6) (1)
Register
Symbol
Reset Value
0161h LIN Wakeup Baud Rate Select Register
0162h LIN Baud Rate Prescaler 0 Register
0163h LIN Baud Rate Prescaler 1 Register
0164h LIN Self-test Control Register
0165h LIN Port Clock Control Register
0166h
LWBR
LBRP0
LBRP1
LSTC
LPC
00h
00h
00h
00h
00h
0167h
0168h LIN0 Mode Register
L0MD
L0BRK
L0SPC
L0WUP
L0IE
00h
00h
00h
00h
00h
00h
00h
0169h LIN0 Break Field Setting Register
016Ah LIN0 Space Width Setting Register
016Bh LIN0 Wakeup Setting Register
016Ch LIN0 Interrupt Enable Register
016Dh LIN0 Error Detection Enable Register
016Eh LIN0 Control Register
L0EDE
L0C
016Fh
0170h LIN0 Transmit Control Register
0171h LIN0 Mode Status Register
0172h LIN0 Status Register
L0TC
L0MST
L0ST
00h
00h
00h
00h
00h
XXh
XXh
0173h LIN0 Error Status Register
0174h LIN0 Response Field Setting Register
0175h LIN0 ID Buffer Register
0176h LIN0 Check Sum Buffer Register
0177h
L0EST
L0RFC
L0IDB
L0CB
0178h LIN0 Data 1 Buffer Register
0179h LIN0 Data 2 Buffer Register
017Ah LIN0 Data 3 Buffer Register
017Bh LIN0 Data 4 Buffer Register
017Ch LIN0 Data 5 Buffer Register
017Dh LIN0 Data 6 Buffer Register
017Eh LIN0 Data 7 Buffer Register
017Fh LIN0 Data 8 Buffer Register
L0DB1
L0DB2
L0DB3
L0DB4
L0DB5
L0DB6
L0DB7
L0DB8
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 37 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.7
SFR Information (7) (1)
Register
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
Symbol
SAR0
Reset Value
XXh
DMA0 Source Pointer
XXh
0Xh
XXh
XXh
0Xh
DMA0 Destination Pointer
DMA0 Transfer Counter
DAR0
TCR0
XXh
XXh
018Ch DMA0 Control Register
DM0CON
0000 0X00b
018Dh
018Eh
018Fh
0190h
XXh
XXh
0Xh
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
DMA1 Source Pointer
SAR1
XXh
XXh
0Xh
DMA1 Destination Pointer
DMA1 Transfer Counter
DAR1
TCR1
XXh
XXh
019Ch DMA1 Control Register
DM1CON
0000 0X00b
019Dh
019Eh
019Fh
01A0h
XXh
XXh
0Xh
01A1h DMA2 Source Pointer
01A2h
SAR2
01A3h
01A4h
XXh
XXh
0Xh
01A5h DMA2 Destination Pointer
01A6h
01A7h
DAR2
TCR2
01A8h
XXh
XXh
DMA2 Transfer Counter
01A9h
01AAh
01ABh
01ACh DMA2 Control Register
DM2CON
0000 0X00b
01ADh
01AEh
01AFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 38 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.8
SFR Information (8) (1)
Register
Address
Symbol
SAR3
Reset Value
XXh
01B0h
01B1h DMA3 Source Pointer
XXh
01B2h
0Xh
01B3h
01B4h
XXh
XXh
0Xh
01B5h DMA3 Destination Pointer
01B6h
01B7h
DAR3
TCR3
01B8h
XXh
XXh
DMA3 Transfer Counter
01B9h
01BAh
01BBh
01BCh DMA3 Control Register
DM3CON
0000 0X00b
01BDh
01BEh
01BFh
01C0h
XXh
XXh
XXh
XXh
XXh
XXh
Timer B0-1 Register
01C1h
TB01
TB11
01C2h
Timer B1-1 Register
01C3h
01C4h
Timer B2-1 Register
01C5h
TB21
Pulse Period/Pulse Width Measurement Mode Function Select
Register 1
01C6h
01C7h
PPWFS1
XXXX X000b
01C8h Timer B Count Source Select Register 0
01C9h Timer B Count Source Select Register 1
TBCS0
TBCS1
00h
X0h
01CAh
01CBh Timer AB Division Control Register 0
TCKDIVC0
0000 X000b
01CCh
01CDh
01CEh
01CFh
01D0h Timer A Count Source Select Register 0
01D1h Timer A Count Source Select Register 1
01D2h Timer A Count Source Select Register 2
TACS0
TACS1
TACS2
00h
00h
X0h
01D3h
01D4h 16-bit Pulse Width Modulation Mode Function Select Register
01D5h Timer A Waveform Output Function Select Register
PWMFS
TAPOFS
0XX0 X00Xb
XXX0 0000b
01D6h
01D7h
01D8h Timer A Output Waveform Change Enable Register
01D9h
01DAh Three-Phase Protect Control Register
TAOW
TPRC
XXX0 X00Xb
00h
01DBh
01DCh
01DDh
01DEh
01DFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 39 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.9
SFR Information (9) (1)
Register
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
Symbol
TB31
Reset Value
XXh
Timer B3-1 Register
Timer B4-1 Register
Timer B5-1 Register
XXh
XXh
XXh
XXh
XXh
TB41
TB51
Pulse Period/Pulse Width Measurement Mode Function Select Reg-
ister 2
01E6h
01E7h
PPWFS2
XXXX X000b
01E8h Timer B Count Source Select Register 2
01E9h Timer B Count Source Select Register 3
TBCS2
TBCS3
00h
X0h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
XXh
XXh
Task Monitor Timer Register
01F1h
TMOS
01F2h Task Monitor Timer Count Start Flag
01F3h Task Monitor Timer Count Source Select Register
01F4h Task Monitor Timer Protect Register
TMOSSR
TMOSCS
TMOSPR
XXXX XXX0b
XXXX 0000b
00h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
Interrupt Source Select Register 4
Interrupt Source Select Register 3
Interrupt Source Select Register 2
Interrupt Source Select Register
IFSR4A
IFSR3A
IFSR2A
IFSR
00h
00h
00h
00h
020Eh Address Match Interrupt Enable Register
020Fh Address Match Interrupt Enable Register 2
AIER
AIER2
XXXX XX00b
XXXX XX00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 40 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.10
SFR Information (10) (1)
Address
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
Register
Symbol
Reset Value
00h
Address Match Interrupt Register 0
RMAD0
RMAD1
RMAD2
RMAD3
00h
X0h
00h
00h
X0h
Address Match Interrupt Register 1
Address Match Interrupt Register 2
00h
00h
X0h
00h
00h
X0h
021Dh Address Match Interrupt Register 3
021Eh
021Fh
0000 0001b
(Other than user boot mode)
0010 0001b
0220h
Flash Memory Control Register 0
FMR0
(User boot mode)
00X0 XX0Xb
XXXX 0000b
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Flash Memory Control Register 1
Flash Memory Control Register 2
Flash Memory Control Register 3
FMR1
FMR2
FMR3
XXXX 0000b
Flash Memory Control Register 6
FMR6
XX0X XX00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 41 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.11
SFR Information (11) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
Register
Symbol
Reset Value
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
00h
XXh
XXh
UART0 Transmit Buffer Register
U0TB
XXh
024Ch UART0 Transmit/Receive Control Register 0
024Dh UART0 Transmit/Receive Control Register 1
U0C0
U0C1
0000 1000b
0000 0010b
XXh
024Eh
UART0 Receive Buffer Register
024Fh
U0RB
XXh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
UART Clock Select Register
UCLKSEL0
X0h
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
00h
XXh
XXh
UART1 Transmit Buffer Register
U1TB
XXh
025Ch UART1 Transmit/Receive Control Register 0
025Dh UART1 Transmit/Receive Control Register 1
U1C0
U1C1
0000 1000b
0000 0010b
XXh
025Eh
UART1 Receive Buffer Register
025Fh
U1RB
XXh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
U2BRG
XXh
XXh
XXh
UART2 Transmit Buffer Register
U2TB
026Ch UART2 Transmit/Receive Control Register 0
026Dh UART2 Transmit/Receive Control Register 1
U2C0
U2C1
0000 1000b
0000 0010b
XXh
026Eh
UART2 Receive Buffer Register
026Fh
U2RB
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 42 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.12
SFR Information (12) (1)
Address
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
Register
Symbol
Reset Value
UART4 Transmit/Receive Mode Register
UART4 Bit Rate Register
U4MR
U4BRG
00h
XXh
XXh
UART4 Transmit Buffer Register
U4TB
XXh
029Ch UART4 Transmit/Receive Control Register 0
029Dh UART4 Transmit/Receive Control Register 1
U4C0
U4C1
0000 1000b
0000 0010b
XXh
029Eh
UART4 Receive Buffer Register
029Fh
U4RB
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 43 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.13
SFR Information (13) (1)
Register
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
Symbol
Reset Value
02A8h UART3 Transmit/Receive Mode Register
02A9h UART3 Bit Rate Register
U3MR
U3BRG
00h
XXh
02AAh
XXh
XXh
UART3 Transmit Buffer Register
02ABh
U3TB
02ACh UART3 Transmit/Receive Control Register 0
02ADh UART3 Transmit/Receive Control Register 1
U3C0
U3C1
0000 1000b
0000 0010b
XXh
02AEh
UART3 Receive Buffer Register
02AFh
U3RB
S00
XXh
XXh
02B0h I2C0 Data Shift Register
02B1h
02B2h I2C0 Address Register 0
02B3h I2C0 Control Register 0
02B4h I2C0 Clock Control Register
02B5h I2C0 Start/Stop Condition Control Register
02B6h I2C0 Control Register 1
02B7h I2C0 Control Register 2
02B8h I2C0 Status Register 0
02B9h I2C0 Status Register 1
02BAh I2C0 Address Register 1
02BBh I2C0 Address Register 2
02BCh
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
XXXX X000b
0000 000Xb
0000 000Xb
02BDh
02BEh
02BFh
02C0h Time Measurement Register 0
G1TM0
G1PO0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Waveform Generation Register 0
02C1h
02C2h Time Measurement Register 1
Waveform Generation Register 1
02C3h
02C4h Time Measurement Register 2
Waveform Generation Register 2
02C5h
02C6h Time Measurement Register 3
Waveform Generation Register 3
02C7h
02C8h Time Measurement Register 4
Waveform Generation Register 4
02C9h
02CAh Time Measurement Register 5
Waveform Generation Register 5
02CBh
02CCh Time Measurement Register 6
Waveform Generation Register 6
02CDh
02CEh Time Measurement Register 7
Waveform Generation Register 7
02CFh
G1TM1
G1PO1
G1TM2
G1PO2
G1TM3
G1PO3
G1TM4
G1PO4
G1TM5
G1PO5
G1TM6
G1PO6
G1TM7
G1PO7
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 44 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.14
SFR Information (14) (1)
Register
Address
Symbol
Reset Value
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
00h
02D0h Waveform Generation Control Register 0
02D1h Waveform Generation Control Register 1
02D2h Waveform Generation Control Register 2
02D3h Waveform Generation Control Register 3
02D4h Waveform Generation Control Register 4
02D5h Waveform Generation Control Register 5
02D6h Waveform Generation Control Register 6
02D7h Waveform Generation Control Register 7
02D8h Time Measurement Control Register 0
02D9h Time Measurement Control Register 1
02DAh Time Measurement Control Register 2
02DBh Time Measurement Control Register 3
02DCh Time Measurement Control Register 4
02DDh Time Measurement Control Register 5
02DEh Time Measurement Control Register 6
02DFh Time Measurement Control Register 7
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
00h
00h
00h
00h
00h
00h
00h
02E0h
XXh
XXh
Base Timer Register
02E1h
G1BT
02E2h Base Timer Control Register 0
02E3h Base Timer Control Register 1
02E4h Time Measurement Prescaler Register 6
02E5h Time Measurement Prescaler Register 7
02E6h Function Enable Register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
00h
00h
00h
00h
00h
02E7h Function Select Register
G1FS
00h
02E8h
XXh
XXh
00h
Base Timer Reset Register
02E9h
G1BTRR
G1DV
02EAh Count Source Divide Register
02EBh
02ECh Waveform Output Master Enable Register
G1OER
00h
02EDh
02EEh Timer S I/O Control Register 0
02EFh Timer S I/O Control Register 1
02F0h Interrupt Request Register
02F1h Interrupt Enable Register 0
G1IOR0
G1IOR1
G1IR
G1IE0
G1IE1
00h
00h
XXh
00h
00h
02F2h Interrupt Enable Register 1
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh NMI Digital Debounce Register
02FFh P1_7 Digital Debounce Register
NDDR
P17DDR
FFh
FFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 45 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.15
SFR Information (15) (1)
Register
Timer B3/B4/B5 Count Start Flag
Address
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
Symbol
TBSR
Reset Value
000X XXXXb
XXh
XXh
XXh
XXh
XXh
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
TA11
TA21
TA41
XXh
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
INVC0
INVC1
IDB0
IDB1
DTT
00h
00h
XX11 1111b
XX11 1111b
XXh
030Ah Three-Phase Output Buffer Register 0
030Bh Three-Phase Output Buffer Register 1
030Ch Dead Time Timer
030Dh Timer B2 Interrupt Generation Frequency Set Counter
030Eh Position-Data-Retain Function Control Register
030Fh
ICTB2
PDRF
XXh
XXXX 0000b
0310h
XXh
XXh
XXh
XXh
XXh
XXh
Timer B3 Register
0311h
TB3
TB4
TB5
0312h
Timer B4 Register
0313h
0314h
Timer B5 Register
0315h
0316h
0317h
0318h
0319h
031Ah
Port Function Control Register
PFCR
0011 1111b
031Bh Timer B3 Mode Register
031Ch Timer B4 Mode Register
031Dh Timer B5 Mode Register
031Eh
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
Count Start Flag
TABSR
00h
One-Shot Start Flag
Trigger Select Register
Increment/Decrement Flag
ONSF
TRGSR
UDF
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
TA0
TA1
TA2
TA3
TA4
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 46 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.16
SFR Information (16) (1)
Register
Address
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
Symbol
TB0
Reset Value
XXh
Timer B0 Register
Timer B1 Register
Timer B2 Register
XXh
XXh
XXh
XXh
XXh
TB1
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
033Ah Timer A4 Mode Register
033Bh Timer B0 Mode Register
033Ch Timer B1 Mode Register
033Dh Timer B2 Mode Register
033Eh Timer B2 Special Mode Register
033Fh
00h
00XX 0000b
00XX 0000b
00XX 0000b
X000 0000b
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
Real-Time Clock Second Data Register
Real-Time Clock Minute Data Register
Real-Time Clock Hour Data Register
Real-Time Clock Day Data Register
Real-Time Clock Control Register 1
Real-Time Clock Control Register 2
Real-Time Clock Count Source Select Register
RTCSEC
RTCMIN
RTCHR
RTCWK
RTCCR1
RTCCR2
RTCCSR
00h
X000 0000b
XX00 0000b
XXXX X000b
0000 X00Xb
X000 0000b
XXX0 0000b
Real-Time Clock Second Compare Data Register
Real-Time Clock Minute Compare Data Register
RTCCSEC
RTCCMIN
RTCCHR
X000 0000b
X000 0000b
X000 0000b
034Ah Real-Time Clock Hour Compare Data Register
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
SS0 Bit Counter Register
SS0BR
1111 1000b
FFh
SS0 Transmit Data Register
SS0TDR
FFh
FFh
FFh
00h
SS0 Receive Data Register
SS0RDR
SS0 Control Register H
SS0 Control Register L
SS0CRH
SS0CRL
SS0MR
SS0ER
SS0SR
SS0MR2
0111 1101b
0001 0000b
00h
035Ah SS0 Mode Register
035Bh SS0 Enable Register
035Ch SS0 Status Register
035Dh SS0 Mode Register 2
035Eh
00h
00h
035Fh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 47 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.17
SFR Information (17) (1)
Register
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
Address
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
Symbol
PUR0
PUR1
PUR2
Reset Value
00h
00h
00h
Port Control Register
PCR
0XX0 0XX0b
036Ch Input Threshold Select Register 0
036Dh Input Threshold Select Register 1
036Eh Input Threshold Select Register 2
036Fh
VLT0
VLT1
VLT2
00h
00h
XX00 0000b
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
Pin Assignment Control Register
PACR
0XXX X000b
037Ch Count Source Protection Mode Register
037Dh Watchdog Timer Refresh Register
037Eh Watchdog Timer Start Register
037Fh Watchdog Timer Control Register
CSPR
WDTR
WDTS
WDC
00h (2)
XXh
XXh
00XX XXXXb
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
X: Undefined
Notes:
1.
2.
The blank areas are reserved. No access is allowed.
When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 48 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.18
SFR Information (18) (1)
Register
DMA2 Source Select Register
Address
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
Symbol
DM2SL
Reset Value
00h
DMA3 Source Select Register
DM3SL
00h
DMA0 Source Select Register
DM0SL
DM1SL
00h
00h
039Ah DMA1 Source Select Register
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h Open-Circuit Detection Assist Function Register
AINRST
XX00 XXXXb
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
XXXX XXXXb
00XX XXXXb
0XXX XXX0b
SFR Snoop Address Register
03B5h
CRCSAR
CRCMR
03B6h CRC Mode Register
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
XXh
XXh
XXh
CRC Data Register
03BDh
CRCD
CRCIN
03BEh CRC Input Register
03BFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 49 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.19
SFR Information (19) (1)
Register
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
Symbol
AD0
Reset Value
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
03D4h A/D Control Register 2
ADCON2
0000 X00Xb
03D5h
03D6h A/D Control Register 0
03D7h A/D Control Register 1
03D8h D/A0 Register
ADCON0
ADCON1
DA0
0000 0XXXb
0000 X000b
00h
03D9h
03DAh
03DBh
03DCh D/A Control Register
DACON
00h
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P5 Register
P5
03EAh Port P4 Direction Register
03EBh Port P5 Direction Register
03ECh Port P6 Register
03EDh Port P7 Register
03EEh Port P6 Direction Register
03EFh Port P7 Direction Register
PD4
PD5
P6
P7
PD6
PD7
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 50 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.20
SFR Information (20) (1)
Register
Address
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
Symbol
P8
P9
PD8
PD9
P10
Reset Value
XXh
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
XXh
00h
00h
XXh
Port P10 Direction Register
PD10
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 51 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.21
SFR Information (21) (1)
Address
D1F0h
D1F1h
D1F2h
D1F3h
D1F4h
D1F5h
D1F6h
D1F7h
D1F8h
D1F9h
D1FAh
D1FBh
D1FCh
D1FDh
D1FEh
D1FFh
D200h
D201h
D202h
D203h
D204h
D205h
D206h
D207h
D208h
D209h
D20Ah
D20Bh
D20Ch
D20Dh
D20Eh
D20Fh
D210h
D211h
D212h
D213h
D214h
D215h
D216h
D217h
D218h
D219h
D21Ah
D21Bh
D21Ch
D21Dh
D21Eh
D21Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 0: Message Identifier
CAN1 Mailbox 0: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB0
CAN1 Mailbox 0: Data Field
CAN1 Mailbox 0: Time Stamp
CAN1 Message Identifier
CAN1 Mailbox 1: Data Length
CAN1 Mailbox 1: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB1
CAN1 Mailbox 1: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 52 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.22
SFR Information (22) (1)
Address
D220h
D221h
D222h
D223h
D224h
D225h
D226h
D227h
D228h
D229h
D22Ah
D22Bh
D22Ch
D22Dh
D22Eh
D22Fh
D230h
D231h
D232h
D233h
D234h
D235h
D236h
D237h
D238h
D239h
D23Ah
D23Bh
D23Ch
D23Dh
D23Eh
D23Fh
D240h
D241h
D242h
D243h
D244h
D245h
D246h
D247h
D248h
D249h
D24Ah
D24Bh
D24Ch
D24Dh
D24Eh
D24Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 2: Message Identifier
CAN1 Mailbox 2: Data Length
CAN1 Mailbox 2: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB2
CAN1 Mailbox 2: Time Stamp
CAN1 Mailbox 3: Message Identifier
CAN1 Mailbox 3: Data Length
CAN1 Mailbox 3: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB3
CAN1 Mailbox 3: Time Stamp
CAN1 Mailbox 4: Message Identifier
CAN1 Mailbox 4: Data Length
CAN1 Mailbox 4: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB4
CAN1 Mailbox 4: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 53 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.23
SFR Information (23) (1)
Address
D250h
D251h
D252h
D253h
D254h
D255h
D256h
D257h
D258h
D259h
D25Ah
D25Bh
D25Ch
D25Dh
D25Eh
D25Fh
D260h
D261h
D262h
D263h
D264h
D265h
D266h
D267h
D268h
D269h
D26Ah
D26Bh
D26Ch
D26Dh
D26Eh
D26Fh
D270h
D271h
D272h
D273h
D274h
D275h
D276h
D277h
D278h
D279h
D27Ah
D27Bh
D27Ch
D27Dh
D27Eh
D27Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 5: Message Identifier
CAN1 Mailbox 5: Data Length
CAN1 Mailbox 5: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB5
CAN1 Mailbox 5: Time Stamp
CAN1 Mailbox 6: Message Identifier
CAN1 Mailbox 6: Data Length
CAN1 Mailbox 6: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB6
CAN1 Mailbox 6: Time Stamp
CAN1 Mailbox 7: Message Identifier
CAN1 Mailbox 7: Data Length
CAN1 Mailbox 7: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB7
CAN1 Mailbox 7: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 54 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.24
SFR Information (24) (1)
Address
D280h
D281h
D282h
D283h
D284h
D285h
D286h
D287h
D288h
D289h
D28Ah
D28Bh
D28Ch
D28Dh
D28Eh
D28Fh
D290h
D291h
D292h
D293h
D294h
D295h
D296h
D297h
D298h
D299h
D29Ah
D29Bh
D29Ch
D29Dh
D29Eh
D29Fh
D2A0h
D2A1h
D2A2h
D2A3h
D2A4h
D2A5h
D2A6h
D2A7h
D2A8h
D2A9h
D2AAh
D2ABh
D2ACh
D2ADh
D2AEh
D2AFh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 8: Message Identifier
CAN1 Mailbox 8: Data Length
CAN1 Mailbox 8: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB8
CAN1 Mailbox 8: Time Stamp
CAN1 Mailbox 9: Message Identifier
CAN1 Mailbox 9: Data Length
CAN1 Mailbox 9: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB9
CAN1 Mailbox 9: Time Stamp
CAN1 Mailbox 10: Message Identifier
CAN1 Mailbox 10: Data Length
CAN1 Mailbox 10: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB10
CAN1 Mailbox 10: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 55 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.25
SFR Information (25) (1)
Address
D2B0h
D2B1h
D2B2h
D2B3h
D2B4h
D2B5h
D2B6h
D2B7h
D2B8h
D2B9h
D2BAh
D2BBh
D2BCh
D2BDh
D2BEh
D2BFh
D2C0h
D2C1h
D2C2h
D2C3h
D2C4h
D2C5h
D2C6h
D2C7h
D2C8h
D2C9h
D2CAh
D2CBh
D2CCh
D2CDh
D2CEh
D2CFh
D2D0h
D2D1h
D2D2h
D2D3h
D2D4h
D2D5h
D2D6h
D2D7h
D2D8h
D2D9h
D2DAh
D2DBh
D2DCh
D2DDh
D2DEh
D2DFh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 11: Message Identifier
CAN1 Mailbox 11: Data Length
CAN1 Mailbox 11: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB11
CAN1 Mailbox 11: Time Stamp
CAN1 Mailbox 12: Message Identifier
CAN1 Mailbox 12: Data Length
CAN1 Mailbox 12: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB12
CAN1 Mailbox 12: Time Stamp
CAN1 Mailbox 13: Message Identifier
CAN1 Mailbox 13: Data Length
CAN1 Mailbox 13: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB13
CAN1 Mailbox 13: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 56 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.26
SFR Information (26) (1)
Address
D2E0h
D2E1h
D2E2h
D2E3h
D2E4h
D2E5h
D2E6h
D2E7h
D2E8h
D2E9h
D2EAh
D2EBh
D2ECh
D2EDh
D2EEh
D2EFh
D2F0h
D2F1h
D2F2h
D2F3h
D2F4h
D2F5h
D2F6h
D2F7h
D2F8h
D2F9h
D2FAh
D2FBh
D2FCh
D2FDh
D2FEh
D2FFh
D300h
D301h
D302h
D303h
D304h
D305h
D306h
D307h
D308h
D309h
D30Ah
D30Bh
D30Ch
D30Dh
D30Eh
D30Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 14: Message Identifier
CAN1 Mailbox 14: Data Length
CAN1 Mailbox 14: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB14
CAN1 Mailbox 14: Time Stamp
CAN1 Mailbox 15: Message Identifier
CAN1 Mailbox 15: Data Length
CAN1 Mailbox 15: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB15
CAN1 Mailbox 15: Time Stamp
CAN1 Mailbox16: Message Identifier
CAN1 Mailbox 16: Data Length
CAN1 Mailbox 16: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB16
CAN1 Mailbox 16: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 57 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.27
SFR Information (27) (1)
Address
D310h
D311h
D312h
D313h
D314h
D315h
D316h
D317h
D318h
D319h
D31Ah
D31Bh
D31Ch
D31Dh
D31Eh
D31Fh
D320h
D321h
D322h
D323h
D324h
D325h
D326h
D327h
D328h
D329h
D32Ah
D32Bh
D32Ch
D32Dh
D32Eh
D32Fh
D330h
D331h
D332h
D333h
D334h
D335h
D336h
D337h
D338h
D339h
D33Ah
D33Bh
D33Ch
D33Dh
D33Eh
D33Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 17: Message Identifier
CAN1 Mailbox 17: Data Length
CAN1 Mailbox 17: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB17
CAN1 Mailbox 17: Time Stamp
CAN1 Mailbox 18: Message Identifier
CAN1 Mailbox 18: Data Length
CAN1 Mailbox 18: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB18
CAN1 Mailbox 18: Time Stamp
CAN1 Mailbox 19: Message Identifier
CAN1 Mailbox 19: Data Length
CAN1 Mailbox 19: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB19
CAN1 Mailbox 19: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 58 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.28
SFR Information (28) (1)
Address
D340h
D341h
D342h
D343h
D344h
D345h
D346h
D347h
D348h
D349h
D34Ah
D34Bh
D34Ch
D34Dh
D34Eh
D34Fh
D350h
D351h
D352h
D353h
D354h
D355h
D356h
D357h
D358h
D359h
D35Ah
D35Bh
D35Ch
D35Dh
D35Eh
D35Fh
D360h
D361h
D362h
D363h
D364h
D365h
D366h
D367h
D368h
D369h
D36Ah
D36Bh
D36Ch
D36Dh
D36Eh
D36Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 20: Message Identifier
CAN1 Mailbox 20: Data Length
CAN1 Mailbox 20: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB20
CAN1 Mailbox 20: Time Stamp
CAN1 Mailbox 21: Message Identifier
CAN1 Mailbox 21: Data Length
CAN1 Mailbox 21: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB21
CAN1 Mailbox 21: Time Stamp
CAN1 Mailbox 22: Message Identifier
CAN1 Mailbox 22: Data Length
CAN1 Mailbox 22: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB22
CAN1 Mailbox 22: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 59 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.29
SFR Information (29) (1)
Address
D370h
D371h
D372h
D373h
D374h
D375h
D376h
D377h
D378h
D379h
D37Ah
D37Bh
D37Ch
D37Dh
D37Eh
D37Fh
D380h
D381h
D382h
D383h
D384h
D385h
D386h
D387h
D388h
D389h
D38Ah
D38Bh
D38Ch
D38Dh
D38Eh
D38Fh
D390h
D391h
D392h
D393h
D394h
D395h
D396h
D397h
D398h
D399h
D39Ah
D39Bh
D39Ch
D39Dh
D39Eh
D39Fh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 23: Message Identifier
CAN1 Mailbox 23: Data Length
CAN1 Mailbox 23: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB23
CAN1 Mailbox 23: Time Stamp
CAN1 Mailbox 24: Message Identifier
CAN1 Mailbox 24: Data Length
CAN1 Mailbox 24: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB24
CAN1 Mailbox 24: Time Stamp
CAN1 Mailbox 25: Message Identifier
CAN1 Mailbox 25: Data Length
CAN1 Mailbox 25: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB25
CAN1 Mailbox 25: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 60 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.30
SFR Information (30) (1)
Address
D3A0h
D3A1h
D3A2h
D3A3h
D3A4h
D3A5h
D3A6h
D3A7h
D3A8h
D3A9h
D3AAh
D3ABh
D3ACh
D3ADh
D3AEh
D3AFh
D3B0h
D3B1h
D3B2h
D3B3h
D3B4h
D3B5h
D3B6h
D3B7h
D3B8h
D3B9h
D3BAh
D3BBh
D3BCh
D3BDh
D3BEh
D3BFh
D3C0h
D3C1h
D3C2h
D3C3h
D3C4h
D3C5h
D3C6h
D3C7h
D3C8h
D3C9h
D3CAh
D3CBh
D3CCh
D3CDh
D3CEh
D3CFh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 26: Message Identifier
CAN1 Mailbox 26: Data Length
CAN1 Mailbox 26: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB26
CAN1 Mailbox 26: Time Stamp
CAN1 Mailbox 27: Message Identifier
CAN1 Mailbox 27: Data Length
CAN1 Mailbox 27: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB27
CAN1 Mailbox 27: Time Stamp
CAN1 Mailbox 28: Message Identifier
CAN1 Mailbox 28: Data Length
CAN1 Mailbox 28: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB28
CAN1 Mailbox 28: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 61 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.31
SFR Information (31) (1)
Address
D3D0h
D3D1h
D3D2h
D3D3h
D3D4h
D3D5h
D3D6h
D3D7h
D3D8h
D3D9h
D3DAh
D3DBh
D3DCh
D3DDh
D3DEh
D3DFh
D3E0h
D3E1h
D3E2h
D3E3h
D3E4h
D3E5h
D3E6h
D3E7h
D3E8h
D3E9h
D3EAh
D3EBh
D3ECh
D3EDh
D3EEh
D3EFh
D3F0h
D3F1h
D3F2h
D3F3h
D3F4h
D3F5h
D3F6h
D3F7h
D3F8h
D3F9h
D3FAh
D3FBh
D3FCh
D3FDh
D3FEh
D3FFh
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
CAN1 Mailbox 29: Message Identifier
CAN1 Mailbox 29: Data Length
CAN1 Mailbox 29: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB29
CAN1 Mailbox 29: Time Stamp
CAN1 Mailbox 30: Message Identifier
CAN1 Mailbox 30: Data Length
CAN1 Mailbox 30: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB30
CAN1 Mailbox 30: Time Stamp
CAN1 Mailbox 31: Message Identifier
CAN1 Mailbox 31: Data Length
CAN1 Mailbox 31: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1MB31
CAN1 Mailbox 31: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 62 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.32
SFR Information (32) (1)
Register
Address
D400h
D401h
D402h
D403h
D404h
D405h
D406h
D407h
D408h
D409h
D40Ah
D40Bh
D40Ch
D40Dh
D40Eh
D40Fh
D410h
D411h
D412h
D413h
D414h
D415h
D416h
D417h
D418h
D419h
D41Ah
D41Bh
D41Ch
D41Dh
D41Eh
D41Fh
D420h
D421h
D422h
D423h
D424h
D425h
D426h
D427h
D428h
D429h
D42Ah
D42Bh
D42Ch
D42Dh
D42Eh
D42Fh
D430h to
D49Fh
Symbol
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Mask Register 0
CAN1 Mask Register 1
CAN1 Mask Register 2
CAN1 Mask Register 3
CAN1 Mask Register 4
CAN1 Mask Register 5
CAN1 Mask Register 6
CAN1 Mask Register 7
C1MKR0
C1MKR1
C1MKR2
C1MKR3
C1MKR4
C1MKR5
C1MKR6
C1MKR7
C1FIDCR0
C1FIDCR1
C1MKIVLR
C1MIER
CAN1FIFO Receive ID Compare Register 0
CAN1FIFO Receive ID Compare Register 1
CAN1 Mask Invalid Register
CAN1 Mailbox Interrupt Enable Register
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 63 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.33
SFR Information (33) (1)
Address
D4A0h
D4A1h
D4A2h
D4A3h
D4A4h
D4A5h
D4A6h
D4A7h
D4A8h
D4A9h
D4AAh
D4ABh
D4ACh
D4ADh
D4AEh
D4AFh
D4B0h
D4B1h
D4B2h
D4B3h
D4B4h
D4B5h
D4B6h
D4B7h
D4B8h
D4B9h
D4BAh
D4BBh
D4BCh
D4BDh
D4BEh
D4BFh
Register
CAN1 Message Control Register 0
CAN1 Message Control Register 1
CAN1 Message Control Register 2
CAN1 Message Control Register 3
CAN1 Message Control Register 4
CAN1 Message Control Register 5
CAN1 Message Control Register 6
CAN1 Message Control Register 7
CAN1 Message Control Register 8
CAN1 Message Control Register 9
CAN1 Message Control Register 10
CAN1 Message Control Register 11
CAN1 Message Control Register 12
CAN1 Message Control Register 13
CAN1 Message Control Register 14
CAN1 Message Control Register 15
CAN1 Message Control Register 16
CAN1 Message Control Register 17
CAN1 Message Control Register 18
CAN1 Message Control Register 19
CAN1 Message Control Register 20
CAN1 Message Control Register 21
CAN1 Message Control Register 22
CAN1 Message Control Register 23
CAN1 Message Control Register 24
CAN1 Message Control Register 25
CAN1 Message Control Register 26
CAN1 Message Control Register 27
CAN1 Message Control Register 28
CAN1 Message Control Register 29
CAN1 Message Control Register 30
CAN1 Message Control Register 31
Symbol
Reset Value
00h
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
C1MCTL16
C1MCTL17
C1MCTL18
C1MCTL19
C1MCTL20
C1MCTL21
C1MCTL22
C1MCTL23
C1MCTL24
C1MCTL25
C1MCTL26
C1MCTL27
C1MCTL28
C1MCTL29
C1MCTL30
C1MCTL31
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 64 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.34
SFR Information (34) (1)
Register
Address
D4C0h
D4C1h
D4C2h
D4C3h
D4C4h
D4C5h
D4C6h
D4C7h
D4C8h
D4C9h
D4CAh
D4CBh
D4CCh
D4CDh
D4CEh
D4CFh
D4D0h
D4D1h
D4D2h
D4D3h
D4D4h
D4D5h
D4D6h
D4D7h
D4D8h
D4D9h
D4DAh
D4DBh
D4DCh
D4DDh
D4DEh
D4DFh
Symbol
Reset Value
0000 0101b
00h
CAN1 Control Register
CAN1 Status Register
C1CTLR
0000 0101b
00h
C1STR
C1BCR
00h
CAN1 Bit Configuration Register
00h
00h
CAN1 Clock Select Register
C1CLKR
C1RFCR
C1RFPCR
C1TFCR
C1TFPCR
C1EIER
00h
CAN1 Receive FIFO Control Register
CAN1 Receive FIFO Pointer Control Register
CAN1 Transmit FIFO Control Register
CAN1 Transmit FIFO Pointer Control Register
CAN1 Error Interrupt Enable Register
CAN1 Error Interrupt Source Judge Register
CAN1 Receive Error Count Register
CAN1 Transmit Error Count Register
CAN1 Error Code Store Register
10000000b
XXh
1000 0000b
XXh
00h
C1EIFR
00h
C1RECR
C1TECR
C1ECSR
C1CSSR
C1MSSR
C1MSMR
00h
00h
00h
CAN1 Channel Search Support Register
CAN1 Mailbox Search Status Register
CAN1 Mailbox Search Mode Register
XXh
1000 0000b
XXXX XX00b
00h
CAN1 Time Stamp Register
C1TSR
00h
XXh
CAN1 Acceptance Filter Support Register
CAN1 Test Control Register
C1AFSR
C1TCR
XXh
00h
D4E0h to
D4FFh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 65 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.35
Address
D500h
D501h
D502h
D503h
D504h
D505h
D506h
D507h
D508h
D509h
D50Ah
D50Bh
D50Ch
D50Dh
D50Eh
D50Fh
D510h
D511h
D512h
D513h
D514h
D515h
D516h
D517h
D518h
D519h
D51Ah
D51Bh
D51Ch
D51Dh
D51Eh
D51Fh
D520h
D521h
D522h
D523h
D524h
D525h
D526h
D527h
D528h
D529h
D52Ah
D52Bh
D52Ch
D52Dh
D52Eh
D52Fh
SFR Information (35) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 0: Message Identifier
XXh
XXh
CAN0 Mailbox 0: Data Length
CAN0 Mailbox 0: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB0
CAN0 Mailbox 0: Time Stamp
CAN0 Mailbox 1: Message Identifier
CAN0 Mailbox 1: Data Length
CAN0 Mailbox 1: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB1
CAN0 Mailbox 1: Time Stamp
CAN0 Mailbox 2: Message Identifier
CAN0 Mailbox 2: Data Length
CAN0 Mailbox 2: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB2
CAN0 Mailbox 2: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 66 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.36
Address
D530h
D531h
D532h
D533h
D534h
D535h
D536h
D537h
D538h
D539h
D53Ah
D53Bh
D53Ch
D53Dh
D53Eh
D53Fh
D540h
D541h
D542h
D543h
D544h
D545h
D546h
D547h
D548h
D549h
D54Ah
D54Bh
D54Ch
D54Dh
D54Eh
D54Fh
D550h
D551h
D552h
D553h
D554h
D555h
D556h
D557h
D558h
D559h
D55Ah
D55Bh
D55Ch
D55Dh
D55Eh
D55Fh
SFR Information (36) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 3: Message Identifier
XXh
XXh
CAN0 Mailbox 3: Data Length
CAN0 Mailbox 3: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB3
CAN0 Mailbox 3: Time Stamp
CAN0 Mailbox 4: Message Identifier
CAN0 Mailbox 4: Data Length
CAN0 Mailbox 4: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB4
CAN0 Mailbox 4: Time Stamp
CAN0 Mailbox 5: Message Identifier
CAN0 Mailbox 5: Data Length
CAN0 Mailbox 5: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB5
CAN0 Mailbox 5: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 67 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.37
Address
D560h
D561h
D562h
D563h
D564h
D565h
D566h
D567h
D568h
D569h
D56Ah
D56Bh
D56Ch
D56Dh
D56Eh
D56Fh
D570h
D571h
D572h
D573h
D574h
D575h
D576h
D577h
D578h
D579h
D57Ah
D57Bh
D57Ch
D57Dh
D57Eh
D57Fh
D580h
D581h
D582h
D583h
D584h
D585h
D586h
D587h
D588h
D589h
D58Ah
D58Bh
D58Ch
D58Dh
D58Eh
D58Fh
SFR Information (37) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 6: Message Identifier
XXh
XXh
CAN0 Mailbox 6: Data Length
CAN0 Mailbox 6: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB6
CAN0 Mailbox 6: Time Stamp
CAN0 Mailbox 7: Message Identifier
CAN0 Mailbox 7: Data Length
CAN0 Mailbox 7: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB7
CAN0 Mailbox 7: Time Stamp
CAN0 Mailbox 8: Message Identifier
CAN0 Mailbox 8: Data Length
CAN0 Mailbox 8: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB8
CAN0 Mailbox 8: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 68 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.38
Address
D590h
D591h
D592h
D593h
D594h
D595h
D596h
D597h
D598h
D599h
D59Ah
D59Bh
D59Ch
D59Dh
D59Eh
D59Fh
D5A0h
D5A1h
D5A2h
D5A3h
D5A4h
D5A5h
D5A6h
D5A7h
D5A8h
D5A9h
D5AAh
D5ABh
D5ACh
D5ADh
D5AEh
D5AFh
D5B0h
D5B1h
D5B2h
D5B3h
D5B4h
D5B5h
D5B6h
D5B7h
D5B8h
D5B9h
D5BAh
D5BBh
D5BCh
D5BDh
D5BEh
D5BFh
SFR Information (38) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 9: Message Identifier
XXh
XXh
CAN0 Mailbox 9: Data Length
CAN0 Mailbox 9: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB9
CAN0 Mailbox 9: Time Stamp
CAN0 Mailbox 10: Message Identifier
CAN0 Mailbox 10: Data Length
CAN0 Mailbox 10: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB10
CAN0 Mailbox 10: Time Stamp
CAN0 Mailbox 11: Message Identifier
CAN0 Mailbox 11: Data Length
CAN0 Mailbox 11: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB11
CAN0 Mailbox 11: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 69 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.39
Address
D5C0h
D5C1h
D5C2h
D5C3h
D5C4h
D5C5h
D5C6h
D5C7h
D5C8h
D5C9h
D5CAh
D5CBh
D5CCh
D5CDh
D5CEh
D5CFh
D5D0h
D5D1h
D5D2h
D5D3h
D5D4h
D5D5h
D5D6h
D5D7h
D5D8h
D5D9h
D5DAh
D5DBh
D5DCh
D5DDh
D5DEh
D5DFh
D5E0h
D5E1h
D5E2h
D5E3h
D5E4h
D5E5h
D5E6h
D5E7h
D5E8h
D5E9h
D5EAh
D5EBh
D5ECh
D5EDh
D5EEh
D5EFh
SFR Information (39) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 12: Message Identifier
XXh
XXh
CAN0 Mailbox 12: Data Length
CAN0 Mailbox 12: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB12
CAN0 Mailbox 12: Time Stamp
CAN0 Mailbox 13: Message Identifier
CAN0 Mailbox 13: Data Length
CAN0 Mailbox 13: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB13
CAN0 Mailbox 13: Time Stamp
CAN0 Mailbox 14: Message Identifier
CAN0 Mailbox 14: Data Length
CAN0 Mailbox 14: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB14
CAN0 Mailbox 14: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 70 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.40
Address
D5F0h
D5F1h
D5F2h
D5F3h
D5F4h
D5F5h
D5F6h
D5F7h
D5F8h
D5F9h
D5FAh
D5FBh
D5FCh
D5FDh
D5FEh
D5FFh
D600h
D601h
D602h
D603h
D604h
D605h
D606h
D607h
D608h
D609h
D60Ah
D60Bh
D60Ch
D60Dh
D60Eh
D60Fh
D610h
D611h
D612h
D613h
D614h
D615h
D616h
D617h
D618h
D619h
D61Ah
D61Bh
D61Ch
D61Dh
D61Eh
D61Fh
SFR Information (40) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 15: Message Identifier
XXh
XXh
CAN0 Mailbox 15: Data Length
CAN0 Mailbox 15: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB15
CAN0 Mailbox 15: Time Stamp
CAN0 Mailbox 16: Message Identifier
CAN0 Mailbox 16: Data Length
CAN0 Mailbox 16: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB16
CAN0 Mailbox 16: Time Stamp
CAN0 Mailbox 17: Message Identifier
CAN0 Mailbox 17: Data Length
CAN0 Mailbox 17: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB17
CAN0 Mailbox 17: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 71 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.41
Address
D620h
D621h
D622h
D623h
D624h
D625h
D626h
D627h
D628h
D629h
D62Ah
D62Bh
D62Ch
D62Dh
D62Eh
D62Fh
D630h
D631h
D632h
D633h
D634h
D635h
D636h
D637h
D638h
D639h
D63Ah
D63Bh
D63Ch
D63Dh
D63Eh
D63Fh
D640h
D641h
D642h
D643h
D644h
D645h
D646h
D647h
D648h
D649h
D64Ah
D64Bh
D64Ch
D64Dh
D64Eh
D64Fh
SFR Information (41) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 18: Message Identifier
XXh
XXh
CAN0 Mailbox 18: Data Length
CAN0 Mailbox 18: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB18
CAN0 Mailbox 18: Time Stamp
CAN0 Mailbox 19: Message Identifier
CAN0 Mailbox 19: Data Length
CAN0 Mailbox 19: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB19
CAN0 Mailbox 19: Time Stamp
CAN0 Mailbox 20: Message Identifier
CAN0 Mailbox 20: Data Length
CAN0 Mailbox 20: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB20
CAN0 Mailbox 20: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 72 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.42
Address
D650h
D651h
D652h
D653h
D654h
D655h
D656h
D657h
D658h
D659h
D65Ah
D65Bh
D65Ch
D65Dh
D65Eh
D65Fh
D660h
D661h
D662h
D663h
D664h
D665h
D666h
D667h
D668h
D669h
D66Ah
D66Bh
D66Ch
D66Dh
D66Eh
D66Fh
D670h
D671h
D672h
D673h
D674h
D675h
D676h
D677h
D678h
D679h
D67Ah
D67Bh
D67Ch
D67Dh
D67Eh
D67Fh
SFR Information (42) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 21: Message Identifier
XXh
XXh
CAN0 Mailbox 21: Data Length
CAN0 Mailbox 21: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB21
CAN0 Mailbox 21: Time Stamp
CAN0 Mailbox 22: Message Identifier
CAN0 Mailbox 22: Data Length
CAN0 Mailbox 22: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB22
CAN0 Mailbox 22: Time Stamp
CAN0 Mailbox 23: Message Identifier
CAN0 Mailbox 23: Data Length
CAN0 Mailbox 23: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB23
CAN0 Mailbox 23: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 73 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.43
Address
D680h
D681h
D682h
D683h
D684h
D685h
D686h
D687h
D688h
D689h
D68Ah
D68Bh
D68Ch
D68Dh
D68Eh
D68Fh
D690h
D691h
D692h
D693h
D694h
D695h
D696h
D697h
D698h
D699h
D69Ah
D69Bh
D69Ch
D69Dh
D69Eh
D69Fh
D6A0h
D6A1h
D6A2h
D6A3h
D6A4h
D6A5h
D6A6h
D6A7h
D6A8h
D6A9h
D6AAh
D6ABh
D6ACh
D6ADh
D6AEh
D6AFh
SFR Information (43) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 24: Message Identifier
XXh
XXh
CAN0 Mailbox 24: Data Length
CAN0 Mailbox 24: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB24
CAN0 Mailbox 24: Time Stamp
CAN0 Mailbox 25: Message Identifier
CAN0 Mailbox 25: Data Length
CAN0 Mailbox 25: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB25
CAN0 Mailbox 25: Time Stamp
CAN0 Mailbox 26: Message Identifier
CAN0 Mailbox 26: Data Length
CAN0 Mailbox 26: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB26
CAN0 Mailbox 26: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 74 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.44
Address
D6B0h
D6B1h
D6B2h
D6B3h
D6B4h
D6B5h
D6B6h
D6B7h
D6B8h
D6B9h
D6BAh
D6BBh
D6BCh
D6BDh
D6BEh
D6BFh
D6C0h
D6C1h
D6C2h
D6C3h
D6C4h
D6C5h
D6C6h
D6C7h
D6C8h
D6C9h
D6CAh
D6CBh
D6CCh
D6CDh
D6CEh
D6CFh
D6D0h
D6D1h
D6D2h
D6D3h
D6D4h
D6D5h
D6D6h
D6D7h
D6D8h
D6D9h
D6DAh
D6DBh
D6DCh
D6DDh
D6DEh
D6DFh
SFR Information (44) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 27: Message Identifier
XXh
XXh
CAN0 Mailbox 27: Data Length
CAN0 Mailbox 27: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB27
CAN0 Mailbox 27: Time Stamp
CAN0 Mailbox 28: Message Identifier
CAN0 Mailbox 28: Data Length
CAN0 Mailbox 28: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB28
CAN0 Mailbox 28: Time Stamp
CAN0 Mailbox 29: Message Identifier
CAN0 Mailbox 29: Data Length
CAN0 Mailbox 29: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB29
CAN0 Mailbox 29: Time Stamp
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 75 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.45
Address
D6E0h
D6E1h
D6E2h
D6E3h
D6E4h
D6E5h
D6E6h
D6E7h
D6E8h
D6E9h
D6EAh
D6EBh
D6ECh
D6EDh
D6EEh
D6EFh
D6F0h
D6F1h
D6F2h
D6F3h
D6F4h
D6F5h
D6F6h
D6F7h
D6F8h
D6F9h
D6FAh
D6FBh
D6FCh
D6FDh
D6FEh
D6FFh
D700h
D701h
D702h
D703h
D704h
D705h
D706h
D707h
D708h
D709h
D70Ah
D70Bh
D70Ch
D70Dh
D70Eh
D70Fh
SFR Information (45) (1)
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 30: Message Identifier
XXh
XXh
CAN0 Mailbox 30: Data Length
CAN0 Mailbox 30: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB30
CAN0 Mailbox 30: Time Stamp
CAN0 Mailbox 31: Message Identifier
CAN0 Mailbox 31: Data Length
CAN0 Mailbox 31: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB31
CAN0 Mailbox 31: Time Stamp
CAN0 Mask Register 0
C0MKR0
C0MKR1
C0MKR2
C0MKR3
CAN0 Mask Register 1
CAN0 Mask Register 2
CAN0 Mask Register 3
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 76 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.46
Address
D710h
D711h
D712h
D713h
D714h
D715h
D716h
D717h
D718h
D719h
D71Ah
D71Bh
D71Ch
D71Dh
D71Eh
D71Fh
D720h
D721h
D722h
D723h
D724h
D725h
D726h
D727h
D728h
D729h
D72Ah
D72Bh
D72Ch
D72Dh
D72Eh
D72Fh
SFR Information (46) (1)
Register
Symbol
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Mask Register 4
CAN0 Mask Register 5
CAN0 Mask Register 6
CAN0 Mask Register 7
C0MKR4
C0MKR5
C0MKR6
C0MKR7
C0FIDCR0
C0FIDCR1
C0MKIVLR
C0MIER
CAN0 FIFO Receive ID Compare Register 0
CAN0 FIFO Receive ID Compare Register 1
CAN0 Mask Invalid Register
CAN0 Mailbox Interrupt Enable Register
D730h to
D79Fh
D7A0h
D7A1h
D7A2h
D7A3h
D7A4h
D7A5h
D7A6h
D7A7h
D7A8h
D7A9h
D7AAh
D7ABh
D7ACh
D7ADh
D7AEh
D7AFh
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 77 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.47
Address
D7B0h
D7B1h
D7B2h
D7B3h
D7B4h
D7B5h
D7B6h
D7B7h
D7B8h
D7B9h
D7BAh
D7BBh
D7BCh
D7BDh
D7BEh
D7BFh
D7C0h
D7C1h
D7C2h
D7C3h
D7C4h
D7C5h
D7C6h
D7C7h
D7C8h
D7C9h
D7CAh
D7CBh
D7CCh
D7CDh
D7CEh
D7CFh
D7D0h
D7D1h
D7D2h
D7D3h
D7D4h
D7D5h
D7D6h
D7D7h
D7D8h
D7D9h
D7DAh
D7DBh
D7DCh
D7DDh
D7DEh
D7DFh
SFR Information (47) (1)
Register
CAN0 Message Control Register 16
CAN0 Message Control Register 17
CAN0 Message Control Register 18
CAN0 Message Control Register 19
CAN0 Message Control Register 20
CAN0 Message Control Register 21
CAN0 Message Control Register 22
CAN0 Message Control Register 23
CAN0 Message Control Register 24
CAN0 Message Control Register 25
CAN0 Message Control Register 26
CAN0 Message Control Register 27
CAN0 Message Control Register 28
CAN0 Message Control Register 29
CAN0 Message Control Register 30
CAN0 Message Control Register 31
Symbol
Reset Value
00h
C0MCTL16
C0MCTL17
C0MCTL18
C0MCTL19
C0MCTL20
C0MCTL21
C0MCTL22
C0MCTL23
C0MCTL24
C0MCTL25
C0MCTL26
C0MCTL27
C0MCTL28
C0MCTL29
C0MCTL30
C0MCTL31
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0000 0101b
00h
CAN0 Control Register
CAN0 Status Register
C0CTLR
C0STR
0000 0101b
00h
00h
CAN0 Bit Configuration Register
C0BCR
00h
00h
CAN0 Clock Select Register
C0CLKR
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
00h
CAN0 Receive FIFO Control Register
CAN0 Receive FIFO Pointer Control Register
CAN0 Transmit FIFO Control Register
CAN0 Transmit FIFO pointer Control Register
CAN0 Error Interrupt Enable Register
CAN0 Error Interrupt Source Judge Register
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
CAN0 Error Code Store Register
1000 0000b
XXh
1000 0000b
XXh
00h
C0EIFR
00h
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
00h
00h
00h
CAN0 Channel Search Support Register
CAN0 Mailbox Search Status Register
CAN0 Mailbox Search Mode Register
XXh
1000 0000b
0000 0000b
00h
CAN0 Time Stamp Register
C0TSR
00h
XXh
CAN0 Acceptance Filter Support Register
CAN0 Test Control Register
C0AFSR
C0TCR
XXh
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 78 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
4.2
4.2.1
Notes on SFRs
Register Settings
Table 4.48 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. Do not use read-modify-write instructions. When
establishing the next value by altering the existing value, write the existing value to the RAM as well as
to the register. Transfer the next value to the register after making changes in the RAM.
Read-modify-write instructions can be used when writing to the no register bits.
Table 4.48
Registers with Write-Only Bits
Address
Register
Symbol
U0BRG
U0TB
0249h
024Bh to 024Ah
0259h
UART0 Bit Rate Register
UART0 Transmit Buffer Register
UART1 Bit Rate Register
U1BRG
U1TB
025Bh to 025Ah
0269h
UART1 Transmit Buffer Register
UART2 Bit Rate Register
U2BRG
U2TB
026Bh to 026Ah
0299h
UART2 Transmit Buffer Register
UART4 Bit Rate Register
U4BRG
U4TB
029Bh to 029Ah
02A9h
UART4 Transmit Buffer Register
UART3 Bit Rate Register
U3BRG
U3TB
02ABh to 02AAh
02B6h
UART3 Transmit Buffer Register
I2C0 Control Register 1
S3D0
02B8h
I2C0 Status Register 0
S10
0303h to 0302h
0305h to 0304h
0307h to 0306h
030Ah
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
IDB0
030Bh
IDB1
030Ch
DTT
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
Timer A0 Register
ICTB2
TA0
0327h to 0326h
0329h to 0328h
032Bh to 032Ah
032Dh to 032Ch
032Fh to 032Eh
037Dh
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Watchdog Timer Refresh Register
Watchdog Timer Start Register
CAN1 Receive FIFO Pointer Control Register
CAN1 Transmit FIFO Pointer Control Register
CAN0 Receive FIFO Pointer Control Register
CAN0 Transmit FIFO pointer Control Register
WDTR
WDTS
C1RFPCR
C1TFPCR
C0RFPCR
C0TFPCR
037Eh
D4C9h
D4CBh
D7C9h
D7CBh
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 79 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.49
Read-Modify-Write Instructions
Function
Mnemonic
Transfer
MOVDir
Bit processing
Shifting
BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS
ROLC, RORC, ROT, SHA, and SHL
ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,
SBB, and SUB
Arithmetic operation
Decimal operation
Logical operation
Jump
DADC, DADD, DSBB, and DSUB
AND, NOT, OR, and XOR
ADJNZ, SBJNZ
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 80 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
5. Electrical Characteristics
J-Version
5.1
5.1.1
Electrical Characteristics (J-Version, Common to 3 V and 5 V)
Absolute Maximum Rating
Table 5.1
Absolute Maximum Ratings
Characteristic
Symbol
Condition
Value
Unit
V
V
Supply voltage
V
= AV
= AV
-0.3 to 6.5
-0.3 to 6.5
CC
CC
CC
CC
AV
Analog supply voltage
V
V
CC
CC
−0.3 to V + 0.1 (1)
V
Analog reference voltage
V
REF
CC
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
Input voltage
V
-0.3 to V + 0.3
V
I
CC
to P8_7, P9_0 toP9_7,
P10_0 to P10_7
XIN, RESET, CNVSS,
VREF
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
Output
P5_0 to P5_7, P6_0 to
voltage
V
-0.3 to V + 0.3
V
O
CC
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XOUT
Power
consumption
P
-40°C ≤ T ≤ 85°C
300
mW
d
opr
While CPU operation
Operating
-40 to 85
0 to 60
While flash memory
temperature
Programming area
Data area
T
°C
°C
opr
program and erase
range
-40 to 85
operation
T
Storage temperature range
-65 to 150
stg
Note:
1. Maximum value is 6.5 V.
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Jul 23, 2010
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5. Electrical Characteristics
J-Version
5.1.2
Recommended Operating Conditions
Table 5.2
Operating Conditions (1)
VCC = 3.0 V to 5.5 V, Topr = -40°C to 85°C unless otherwise specified.
Value
Unit
Symbol
Characteristic
Min.
3.0
Typ.
Max.
5.5
VCC
Supply voltage
V
V
V
V
AVCC
VSS
VCC
0
Analog supply voltage
Ground voltage
AVSS
Analog ground voltage
0
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
0.7 VCC
0.85VCC
VCC
V
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
Input level 0.70 VCC
VCC
V
High level
input voltage
VIH
P10_0 to P10_7
0.8 VCC
0.7 VCC
2.1
VCC
VCC
XIN, RESET, CNVSS
When I2C-bus input level selected
When SMBUS input level selected
V
V
V
SDAMM, SCLMM
VCC
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
0.3 VCC
0
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
Input level 0.70 VCC
0.45VCC
0
V
Low level input
voltage
VIL
0.2 VCC
0.3 VCC
0.8
XIN, RESET, CNVSS
0
0
0
V
V
V
When I2C-bus input level selected
When SMBUS input level selected
SDAMM, SCLMM
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
High peak
output current
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(peak)
IOL(avg)
-80.0
-10.0
-5.0
mA
mA
mA
mA
mA
mA
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
High level
peak output
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
High level
averageoutput
current (1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
Low peak
output current
80.0
10.0
5.0
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
Low level peak
output current
Low level
averageoutput
current (1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
Main clock input oscillation frequency (2)
Sub clock oscillation oscillator frequency
PLL clock oscillation frequency (2)
f(XIN)
0
20
50
32
32
1
MHz
kHz
MHz
MHz
ms
f(XCIN)
f(PLL)
32.768
10
0
f(BCLK)
tsu(PLL)
Notes:
CPU operation frequency
Wait time to stabilize PLL frequency synthesizer
1.
2.
The mean output current is the mean value within 100ms.
Refer to Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency” for the relationship between main
clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 82 of 156
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5. Electrical Characteristics
J-Version
Main clock input oscillation frequency
PLL clock oscillation frequency
32.0
20.0 MHz
32.0 MHz
20.0
10.0
0.0
10.0
0.0
3.0
5.5
3.0
5.5
Vcc [V] (main clock: no division)
Vcc [V] (PLL clock oscillation)
Figure 5.1
Table 5.3
Main clock input oscillation frequency, PLL clock oscillation frequency
(1)
Recommended Operating Conditions (2/2)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 85°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.
Standard
Typ.
Symbol
Parameter
Unit
Min.
Max.
0.5
VCC = 5.0 V
VCC = 3.0 V
VCC = 5.0 V
VCC = 3.0 V
Vp-p
Vp-p
V/ms
V/ms
Vr(VCC)
Allowable ripple voltage
0.3
0.3
dVr(VCC)/dt
Note:
Ripple voltage falling gradient
0.3
1. The device is operationally guaranteed under these operating conditions.
VCC
Vr(
V
)
CC
Figure 5.2
Ripple Waveform
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 83 of 156
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5. Electrical Characteristics
J-Version
5.1.3
A/D Conversion Characteristics
(1)
Table 5.4
A/D Conversion Characteristics
V
= AV = V
= 3.0 to 5.5 V, V = AV = 0 V at T = -40°C to 85°C unless otherwise specified.
SS SS opr
CC
Symbol
—–
CC
REF
Standard
Typ.
Parameter
Measuring Condition
Unit
Min.
Max.
10
VREF = VCC
Resolution
Bits
LSB
LSB
LSB
LSB
VREF = VCC = 5.0 V (2)
±3
INL
Integral Non-Linearity Error
Absolute Accuracy
V
V
V
REF = VCC = 3.3 V (2)
REF = VCC = 5.0 V (2)
REF = VCC = 3.3 V (2)
±5
±3
—–
±5
25
16
10
4.0 V ≤ VCC ≤ 5.5 V
3.2 V ≤ VCC ≤ 4.0 V
3.0 V ≤ VCC ≤ 3.2 V
2
2
2
MHz
MHz
MHz
kΩ
φAD
A/D operating clock frequency
—–
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
3
DNL
(2)
(2)
(2)
±1
±3
±3
LSB
LSB
LSB
—–
—–
Gain Error
VREF = VCC = 5V,
10-bit Conversion Time
tCONV
1.60
μs
φAD = 25 MHz
tSAMP
VREF
VIA
Sampling time
0.6
3.0
0
μs
V
VCC
Reference Voltage
Analog Input Voltage (3)
VREF
V
Notes:
1. Use when AV = V
CC
CC
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input
ports and connect them to V . See Figure 5.3 “A/D Accuracy Measure Circuit”.
SS
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
AN: One of the analog input pin
P0 to P10: I/O pins other than AN
Figure 5.3
A/D Accuracy Measure Circuit
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Jul 23, 2010
Page 84 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.4
D/A Conversion Characteristics
Table 5.5
D/A Conversion Characteristics
V
= AV = V
= 3.0 to 5.5 V, V = AV = 0 V at T = -40°C to 85°C unless otherwise specified.
CC
CC
REF SS SS opr
Standard
Typ.
Symbol
Parameter
Measuring Condition
Unit
Min.
Max.
8
-
-
Resolution
Bits
LSB
μs
Absolute Accuracy
Setup Time
2.5
3
tSU
RO
Output Resistance
5
6
8.2
1.5
kΩ
See Notes 1 and 2
IVREF
Reference Power Supply Input Current
mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 85 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.5
Flash Memory Electrical Characteristics
Table 5.6
CPU Clock When Operating Flash Memory (f(BCLK))
VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
CPU rewrite mode
Conditions
Min.
Typ.
Max.
16 (1)
5 (3)
35
-
MHz
MHz
kHz
f(SLOW_R)
-
Slow read mode
Low current consumption read mode
Data flash read
fC
20 (2)
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub
clock as the CPU clock source, a wait is not necessary.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 86 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.7
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Program/erase cycles (1, 3, 4)
Two words program time
Lock bit program time
Block erase time
1,000 (2)
-
-
VCC = 3.3 V, Topr = 25°C
times
μs
V
CC = 3.3 V, Topr = 25°C
CC = 3.3 V, Topr = 25°C
150
70
4000
3000
3.0
V
μs
-
VCC = 3.3 V, Topr = 25°C
0.2
s
3
Time delay from suspend request
until suspend
5 + ---------------
td(SR-SUS)
-
ms
f(BCLK)
Interval from erase start/restart
until following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
-
-
ms
20
1
Time from suspend until erase
restart
30 + ---------------
μs
f(BCLK)
-
Program, erase voltage
Read voltage
3.0
3.0
0
5.5
5.5
60
V
V
-
Topr = -40°C to 85°C
-
Program, erase temperature
°C
μs
tPS
-
Flash Memory Circuit Stabilization Wait Time
Ambient temperature = 55°C
50
Data hold time (6)
20
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word
data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be
written to the same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 87 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.8
Flash Memory (Data Flash) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 85°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Program/erase cycles (1, 3, 4)
Two words program time
Lock bit program time
Block erase time
10,000 (2)
-
-
-
-
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
times
μs
300
140
0.2
4000
3000
3.0
μs
VCC = 3.3 V, Topr = 25°C
s
3
Time delay from suspend request
until suspend
5 + ---------------
td(SR-SUS)
-
ms
f(BCLK)
Interval from erase start/restart until
following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
-
-
ms
20
1
Time from suspend until erase
restart
30 + ---------------
μs
f(BCLK)
-
Program, erase voltage
Read voltage
3.0
3.0
−40
5.5
5.5
85
V
V
-
-
Program, erase temperature
°C
μs
tPS
Flash memory circuit stabilization wait time
Ambient temperature = 55°C
50
Data hold time (6)
-
20
year
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request,
the erase sequence cannot be completed.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 88 of 156
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5. Electrical Characteristics
J-Version
2
5.1.6
E PROM Emulation Data Flash
2
Table 5.9
E PROM Emulation Data Flash Electrical Characteristics
VCC = 3.0 to 5.5 V, VSS = 0 V, and T = -40°C to 85°C unless otherwise specified.
opr
Value
Symbol
Characteristic
Unit
Min.
Typ.
100
15
Max.
Program/erase cycles (1)
—
—
—
—
100000
times
µs
Word program time (2-byte program)
Read time (2-byte read)
2000
1
µs
Block erase time (32-byte block)
200
ms
Flash memory circuit stabilization wait time
(sleep mode to normal mode)
tPS
—
50
µs
Data hold time (2)
Ambient temperature = 55°C (3, 4)
20
years
Notes:
1. Definition of program/erase cycles definition
This value represents the number of erasure per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it
is considered the programming/erasure is performed just once. However a write in the same
address more than once for one erasure is disabled. (overwrite disabled).
2. The data hold time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data hold time includes (7000) hours in Ambient temperature = 85°C.
4. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 89 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
5.1.7
Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.10
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.
Standard
Symbol
Vdet0
Parameter
Condition
When VCC is falling.
VCC = 3.0 to 5.0 V
Unit
V
Min.
2.70
Typ. Max.
Voltage detection level Vdet0
2.85
3.00
Waiting time until voltage detector operation
starts (1)
td(E-A)
100
μs
Note:
1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
Table 5.11
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 85°C, unless otherwise specified.
Standard
Symbol
Parameter
Condition
Unit
Min.
3.51
Typ. Max.
3.21
Vdet2_0
V
V
V
V
V
V
V
V
Voltage detection level Vdet2_0
Vdet2_1 Voltage detection level Vdet2_1
Vdet2_2 Voltage detection level Vdet2_2
Vdet2_3 Voltage detection level Vdet2_3
3.36
3.51
3.66
When VCC is falling
Vdet2_4
3.81
3.96
4.10
4.25
4.11
Voltage detection level Vdet2_4
Vdet2_5 Voltage detection level Vdet2_5
Vdet2_6 Voltage detection level Vdet2_6
Vdet2_7 Voltage detection level Vdet2_7
Hysteresis width at the rising of VCC in voltage
-
0.15
V
detector 2
Waiting time until voltage detector operation starts (1)
td(E-A)
Note:
VCC = 3.0 to 5.0 V
100
μs
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
REJ03B0267-0101 Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Table 5.12
Power-On Reset Circuit
The measurement condition is Topr = -40°C to 85°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Condition
Min.
2.0
Typ.
Max.
trth
External power VCC rise gradient
External power VCC fall gradient
50000 mV/ms
50000 mV/ms
tfth
Voltage at which power-on reset enabled (1)
Hold time at which power-on reset enabled
Vpor
tw(por)
0.1
V
1.0
ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0.
Vdet0
Vdet0
trth
trth
V
CC
External Power
tfth
Vpor
tw(por)
Internal
reset signal
1
1
× 128
× 128
fOCO-S
fOCO-S
Figure 5.4
Power-On Reset Circuit Electrical Characteristics
Power Supply Circuit Timing Characteristics
Table 5.13
Standard
Symbol
Parameter
Measuring Condition
Unit
ms
Min. Typ. Max.
Time for Internal Power Supply Stabilization
During Powering-On
td(P-R)
5
VCC = 3.0 V to 5.5V
td(R-S)
td(W-S)
STOP Release Time
300
300
μs
μs
Low Power Mode Wait Mode Release Time
Note:
1. When V
= 5 V.
CC
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 91 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version
Recommended
operating
voltage
td(P-R)
VCC
Time to stabilize internal supply
voltage during powering-on
td(P-R)
CPU clock
(a) Interrupt to exit from stop mode
(b) Interrupt to exit from wait mode
td(R-S)
STOP release time
td(W-S)
Low power consumption
mode wait mode exit time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
td(E-A)
VC25, VC27
Voltage detection circuit
operation start time
Voltage detection circuit
Stop
Operate
td(E-A)
Figure 5.5
5.1.8
Power Supply Circuit Timing Diagram
Oscillation Circuit Electrical Characteristics
Table 5.14
On-chip Oscillator Oscillation Circuit Electrical Characteristics
VCC = 3.0 to 5.5 V, Topr = −40°C to 85°C, unless otherwise specified
Value
Typ.
125
Unit
Symbol
Characteristic
Min.
100
32
Max.
150
48
fOCO-S
fOCO40M
125 kHz on-chip oscillator oscillation frequency
40 MHz on-chip oscillator oscillation frequency
kHz
40
MHz
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 92 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
5.2
5.2.1
Electrical Characteristics (J-Version, V = 5 V)
CC
Electrical Characteristics
J-Version, VCC = 5 V
Table 5.15
Electrical Characteristics (1)
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Standard
Typ.
Symbol
OH
Parameter
Measuring Condition
Unit
V
Min.
Max.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
V
V
I
I
=−5 mA
V
2.0
V
HIGH Output Voltage
HIGH Output Voltage
OH
CC−
CC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7,P9_0 to P9_7, P10_0 to P10_7
= −200 μA
V
−0.3
V
V
OH
OH
OH
CC−
CC
I
I
= −1 mA
V
V
−2.0
−2.0
V
HIGH POWER
OH
OH
CC−
CC
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
V
V
= −0.5 mA
V
LOW POWER
HIGH POWER
LOW POWER
CC−
CC
V
With no load applied
With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
V
V
I
I
= 5 mA
LOW Output Voltage
LOW Output Voltage
2.0
V
V
OL
OL
OL
OL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
= 200 μA
0.45
I
I
= 1 mA
HIGH POWER
2.0
2.0
OL
OL
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
= 0.5 mA
LOW POWER
HIGH POWER
LOW POWER
V
OL
With no load applied
With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,
NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,
CLK0 to CLK4, TA0OUT to TA4OUT,
V +-V
0.4V
CC
Hysteresis
0.2
V
T
T-
KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,
SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0,
LIN0IN, CRX0, CRX1
V
V
-V
Hysteresis
Hysteresis
RESET
0.2
0.2
2.5
0.8
V
V
T+ T-
-V
XIN
T+ T-
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
I
V = 5 V
I
HIGH Input Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
5.0
μA
IH
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
LOW Input Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
I
V = 0 V
I
−5.0
μA
kΩ
IL
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
Pull-Up
Resistance
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
R
V = 0 V
I
30
50
170
PULLUP
R
R
V
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
1.5
15
MΩ
MΩ
V
fXIN
fXCIN
At stop mode
2.0
RAM
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 93 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Table 5.16
Electrical Characteristics (2)
T
= −40°C to 85°C unless otherwise specified.
opr
Standard
Unit
Symbol
Parameter
Measuring Condition
f(BCLK) = 32 MHz,
Min. Typ. Max.
25
21
17
45
39
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
No division
21
6
39
mA
mA
40 MHz on-chip oscillator
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
Power Supply
Current
(VCC = 4.2V to 5.5
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
125 kHz on-chip oscillator
mode
190
580
μA
V)
In single-chip
mode, the output
pins are open and
other pins are
VSS
ICC
f(BCLK) = 32 kHz
On Flash memory (2)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Low power mode
200
25
μA
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Wait mode
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 85°C
55
μA
Topr = 25°C
3
15
μA
μA
Stop mode
T
opr = 85°C
(BCLK) = 10 MHz, PM17 = 1 (one wait)
CC = 5.0 V
(BCLK) = 10 MHz, PM17 = 1 (one wait)
CC = 5.0 V
30
During flash memory
program
f
20.0
30.0
mA
mA
V
During flash memory
erase
f
V
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
Note:
1. This indicates the memory in which the program to be executed exists.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 94 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
5.2.2
Timing Requirements (Peripheral Functions and Others)
(V = 5 V, V = 0 V, at T = -40°C to 85°C unless otherwise specified)
opr
CC
SS
5.2.2.1
Reset Input (RESET Input)
Table 5.17
Reset Input (RESET Input)
Parameter
Standard
Unit
Symbol
tw(RSTL)
Min.
Max.
RESET input low pulse width
10
μs
RESET input
tw(RTSL)
Figure 5.6
Reset Input (RESET Input)
5.2.2.2
External Clock Input
(1)
Table 5.18
External Clock Input (XIN Input)
Standard
Max.
Symbol
Parameter
Unit
Min.
50
tc
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
20
20
9
9
tf
External clock fall time
Note:
1. The condition is V = 5.0V.
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.7
External Clock Input (XIN Input)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 95 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.3
Timer A Input
Table 5.19
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN input cycle time
100
40
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
40
Table 5.20
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.21
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.22
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.8
Timer A Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 96 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
Table 5.23
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
Symbol
tc(TA)
Parameter
Unit
Min.
800
200
200
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.9
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 97 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.4
Timer B Input
Table 5.24
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
100
40
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high pulse width (counted on one edge)
TBiIN input low pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input high pulse width (counted on both edges)
TBiIN Input low pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.25
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
Table 5.26
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.10 Timer B Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 98 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.5
Table 5.27
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Standard
Symbol
tw(TSH)
Parameter
Unit
Min.
2
Max.
TSUDA, TSUDB input high pulse width
TSUDA, TSUDB input low pulse width
TSUDB input setup time
μs
μs
μs
μs
t
2
w(TSL)
t
1
su(TSUDA-TSUDB)
t
TSUDA input setup time
1
su(TSUDB-TSUDA)
Two-phase pulse input in two-phase pulse signal processing mode
t
w(TSH)
t
w(TSL)
TSUDA input
t
t
su(TSUDA-TSUDB)
su(TSUDA-TSUDB)
t
t
w(TSH)
su(TSUDB-TSUDA)
t
w(TSL)
TSUDB input
Note:
t
su(TSUDB-TSUDA)
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.11 Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 99 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
opr
CC
SS
5.2.2.6
Serial Interface
Table 5.28
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input high pulse width
CLKi input low pulse width
TXDi output delay time
TXDi hold time
200
100
100
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
RXDi input setup time
RXDi input hold time
70
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.12 Serial Interface
5.2.2.7
External Interrupt INTi Input
Table 5.29
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi input high pulse width
INTi input low pulse width
tw(INL)
INTi input
tw(INH)
Figure 5.13 External Interrupt INTi Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 100 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
opr
CC
SS
2
5.2.2.8
Multi-master I C-bus
2
Table 5.30
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.14 Multi-master I C-bus
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 101 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T
= −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.9
Serial bus interface
Table 5.31
Serial Bus Interface
Value
Typ.
Measurement
condition
Symbol
Characteristic
Unit
Min.
250
0.4
Max.
tc(SSCK)
tw(SSCKH)
tw(SSCKL)
SSCK clock cycle time
ns
tc(SSCK)
tc(SSCK)
SSCK clock high pulse width
SSCK clock low pulse width
0.6
0.6
1
0.4
(1)
tCYC
Master
Slave
tr(SSCK)
SSCK clock rising time
SSCK clock falling time
1
μs
(1)
tCYC
Master
Slave
1
tf(SSCK)
1
μs
tsu(SSIO-SSCK)
th(SSCK-SSIO)
tsu(SCS-SSCK)
th(SSCK-SCS)
td(SSCK-SSIO)
ten(SCS-SSI)
SSO, SSI data input setup time
SSO, SSI data input hold time
100
1
ns
(1)
tCYC
1 tCYC + 50 (1)
1 tCYC + 50 (1)
SCS setup time
SCS hold time
Slave
Slave
ns
ns
(1)
tCYC
SS0, SSI data output delay time
SSI output enable time
1
1.5 tCYC + 100 (1)
1.5 tCYC + 100 (1)
3.0 V ≤ VCC ≤ 5.5 V
3.0 V ≤ VCC ≤ 5.5 V
ns
ns
tdis(SCS-SSI)
SSI output disable time
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 102 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t h(SSCK-SSIO)
t su(SSIO-SSCK)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.15 I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 103 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t h(SSCK-SCS)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
t d(SSCK-SSIO)
t dis(SCS-SSI)
t en(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
t su(SCS-SSCK)
t r(SSCK)
t h(SSCK-SCS)
t w(SSCKH)
t f(SSCK)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t
t
s
u
(
S
S
I
O
-
S
S
C
K
)
h
(
S
S
C
K
-
S
S
I
O
)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.16 I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 104 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 5 V
tw(SSCKH)
VIH or VOH
SSCK
VIL or VOL
tc(SSCK)
tw(SSCKL)
SSO (output)
SSI (input)
td(SSCK-SSIO)
tsu(SSIO-SSCK)
th(SSCK-SSIO)
Figure 5.17 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
30 pF
Figure 5.18 Switching Characteristic Measurement Circuit
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 105 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
5.3
5.3.1
Electrical Characteristics (J-Version, V = 3 V)
CC
Electrical Characteristics
J-Version, VCC = 3 V
Table 5.32
Electrical Characteristics (1)
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 85°C, f(BCLK)= 32 MHz unless otherwise specified.
Standard
Symbol
Parameter
Measuring Condition
Unit
V
Min.
Typ.
Max.
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
HIGH
Output
Voltage
VOH
IOH = −1 mA
VCC−0.5
I
OH = −0.1 mA
VCC−0.5
VCC−0.5
VCC
VCC
HIGH POWER
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
V
V
IOH = −50 μA
LOW POWER
VOH
VOL
VOL
HIGH POWER With no load applied
LOW POWER With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
LOW
Output
Voltage
IOL = 1mA
0.5
V
IOL = 0.1mA
HIGH POWER
0.5
0.5
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
IOL = 50μA
LOW POWER
HIGH POWER With no load applied
LOW POWER With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB5IN, INT0
to INT7, NMI, ADTRG, CTS0 to CTS3,
SCL2, SDA2, CLK0 to CLK4, TA0OUT
Hysteresis to TA4OUT, KI0 to KI3, RXD0 to RXD4,
ZP, IDU, IDW, IDV, SD, INPC1_0 to
INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,
CRX0, CRX1
VT+-VT-
0.4VCC
V
VT+-VT-
T+-VT-
Hysteresis RESET
1.8
0.8
V
V
V
Hysteresis
XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
HIGH Input P5_0 to P5_7, P6_0 to P6_7, P7_0 to
IIH
VI = 3V
4.0
μA
Current
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
LOW Input P5_0 to P5_7, P6_0 to P6_7, P7_0 to
IIL
VI = 0V
VI = 0V
−4.0
μA
kΩ
Current
P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
Pull-Up
Resistance
RPULLUP
50
100
500
RfXIN
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
3.0
25
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 106 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Table 5.33
Electrical Characteristics (2)
Topr = −40°C to 85°C unless otherwise specified.
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
f(BCLK) = 32 MHz,
23
20
16
43
38
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
No division
20
6
38
mA
mA
40 MHz on-chip oscillator
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
Power Supply
Current
(VCC = 3.0 V to 3.6
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
125 kHz on-chip oscillator
mode
190
580
μA
V)
ICC
In single-chip
mode, the output
pins are open and
other pins are
VSS
f(BCLK) = 32 kHz
On Flash memory (1)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Low power mode
200
25
μA
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Wait mode
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
55
μA
Topr = 85°C
Topr = 25°C
2
12
μA
μA
Stop mode
Topr = 85°C
30
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
During flash memory
program
20.0
30.0
mA
mA
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
During flash memory
erase
VCC = 3.0 V
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
Note:
1. This indicates the memory in which the program to be executed exists.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 107 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
5.3.2
Timing Requirements (Peripheral Functions and Others)
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
opr
CC
SS
5.3.2.1
Reset Input (RESET Input)
Table 5.34
Reset Input (RESET Input)
Parameter
Standard
Unit
Symbol
tw(RSTL)
Min.
Max.
RESET input low pulse width
10
μs
RESET input
tw(RTSL)
Figure 5.19 Reset Input (RESET Input)
5.3.2.2
External Clock Input
(1)
Table 5.35
External Clock Input (XIN input)
Standard
Max.
Symbol
Parameter
Unit
Min.
50
tc
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
20
20
9
9
tf
External clock fall time
Note:
1. The condition is V = 3.0V.
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.20 External Clock Input (XIN Input)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 108 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
opr
CC
SS
5.3.2.3
Timer A Input
Table 5.36
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN input cycle time
150
60
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
60
Table 5.37
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
600
300
300
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.38
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
300
150
150
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.39
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.21 Timer A Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 109 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
opr
CC
SS
Table 5.40
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
Symbol
tc(TA)
Parameter
Unit
Min.
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
μs
ns
ns
t
500
500
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.22 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 110 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.4
Timer B Input
Table 5.41
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
150
60
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high pulse width (counted on one edge)
TBiIN input low pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input high pulse width (counted on both edges)
TBiIN Input low pulse width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.42
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
Table 5.43
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.23 Timer B Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 111 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.5
Table 5.44
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Standard
Symbol
tw(TSH)
Parameter
Unit
Min.
2
Max.
TSUDA, TSUDB input high pulse width
TSUDA, TSUDB input low pulse width
TSUDB input setup time
μs
μs
μs
μs
t
2
w(TSL)
t
1
su(TSUDA-TSUDB)
t
TSUDA input setup time
1
su(TSUDB-TSUDA)
Two-phase pulse input in two-phase pulse signal processing mode
t
w(TSH)
t
w(TSL)
TSUDA input
t
t
su(TSUDA-TSUDB)
su(TSUDA-TSUDB)
t
t
w(TSH)
su(TSUDB-TSUDA)
t
w(TSL)
TSUDB input
Note:
t
su(TSUDB-TSUDA)
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.24 Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 112 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.6
Serial Interface
Table 5.45
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input high pulse width
CLKi input low pulse width
TXDi output delay time
TXDi hold time
300
150
150
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
160
0
RXDi input setup time
RXDi input hold time
100
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.25 Serial Interface
5.3.2.7
External Interrupt INTi Input
Table 5.46
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
tw(INL)
INTi input
tw(INH)
Figure 5.26 External Interrupt INTi Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 113 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 85°C unless otherwise specified)
CC
SS
opr
2
5.3.2.8
Multi-master I C-bus
2
Table 5.47
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.27 Multi-master I C-bus
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 114 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T
= −40°C to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.9
Serial bus interface
Table 5.48
Serial Bus Interface
Value
Typ.
Measurement
condition
Symbol
Characteristic
Unit
Min.
250
0.4
Max.
tc(SSCK)
tw(SSCKH)
tw(SSCKL)
SSCK clock cycle time
ns
tc(SSCK)
tc(SSCK)
SSCK clock high pulse width
SSCK clock low pulse width
0.6
0.6
1
0.4
(1)
tCYC
Master
Slave
tr(SSCK)
SSCK clock rising time
SSCK clock falling time
1
μs
(1)
tCYC
Master
Slave
1
tf(SSCK)
1
μs
tsu(SSIO-SSCK)
th(SSCK-SSIO)
tsu(SCS-SSCK)
th(SSCK-SCS)
td(SSCK-SSIO)
ten(SCS-SSI)
SSO, SSI data input setup time
SSO, SSI data input hold time
100
1
ns
(1)
tCYC
1 tCYC + 50 (1)
1 tCYC + 50 (1)
SCS setup time
SCS hold time
Slave
Slave
ns
ns
(1)
tCYC
SS0, SSI data output delay time
SSI output enable time
1
1.5 tCYC + 100 (1)
1.5 tCYC + 100 (1)
3.0 V ≤ VCC ≤ 5.5 V
3.0 V ≤ VCC ≤ 5.5 V
ns
ns
tdis(SCS-SSI)
SSI output disable time
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 115 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t h(SSCK-SSIO)
t su(SSIO-SSCK)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.28 I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 116 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t h(SSCK-SCS)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
t d(SSCK-SSIO)
t dis(SCS-SSI)
t en(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
t su(SCS-SSCK)
t r(SSCK)
t h(SSCK-SCS)
t w(SSCKH)
t f(SSCK)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t
t
s
u
(
S
S
I
O
-
S
S
C
K
)
h
(
S
S
C
K
-
S
S
I
O
)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.29 I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 117 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
J-Version, VCC = 3 V
tw(SSCKH)
VIH or VOH
SSCK
VIL or VOL
tc(SSCK)
tw(SSCKL)
SSO (output)
SSI (input)
td(SSCK-SSIO)
tsu(SSIO-SSCK)
th(SSCK-SSIO)
Figure 5.30 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
30 pF
Figure 5.31 Switching Characteristic Measurement Circuit
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 118 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4
5.4.1
Electrical Characteristics (K-Version, Common to 3 V and 5 V)
Absolute Maximum Rating
Table 5.49
Absolute Maximum Ratings
Symbol
Characteristic
Condition
Value
Unit
V
V
Supply voltage
V
= AV
= AV
-0.3 to 6.5
-0.3 to 6.5
CC
CC
CC
CC
AV
V
Analog supply voltage
Analog reference voltage
V
V
CC
CC
−0.3 to V + 0.1 (1)
V
REF
I
CC
V
Input voltage P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
-0.3 to V + 0.3
V
CC
XIN, RESET, CNVSS,
VREF
V
Output
voltage
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to
P6_7, P7_0 to P7_7, P8_0
to P8_7, P9_0 to P9_7,
P10_0 to P10_7
O
-0.3 to V + 0.3
V
CC
XOUT
P
Power consumption
-40°C ≤ T ≤ 85°C
300
250
mW
mW
d
opr
85°C < T ≤ 125°C
opr
T
Operating
temperature
range
While CPU operation
opr
-40 to 125
°C
°C
While flash memory
program and erase
operation
Programming area
Data area
0 to 60
-40 to 125
-65 to 150
T
Storage temperature range
stg
Note:
1. Maximum value is 6.5 V.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 119 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4.2
Recommended Operating Conditions
Table 5.50
Operating Conditions (1)
VCC = 3.0 V to 5.5 V, Topr = -40 °C to 125 °C unless otherwise specified.
Value
Unit
Symbol
Characteristic
Min.
3.0
Typ.
Max.
5.5
VCC
Supply voltage
V
V
V
V
AVCC
VSS
Analog supply voltage
Ground voltage
VCC
0
AVSS
Analog ground voltage
0
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
0.7 VCC
0.85VCC
VCC
V
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
Input level 0.70 VCC
VCC
V
High level input
voltage
VIH
P10_0 to P10_7
0.8 VCC
0.7 VCC
2.1
VCC
VCC
XIN, RESET, CNVSS
When I2C-bus input level selected
When SMBUS input level selected
V
V
V
SDAMM, SCLMM
VCC
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC
P2_0 to P2_7, P3_0 to P3_7,
0.3 VCC
0
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
Input level 0.70 VCC
0.45VCC
0
V
Low level input
voltage
VIL
0.2 VCC
0.3 VCC
0.8
XIN, RESET, CNVSS
0
0
0
V
V
V
When I2C-bus input level selected
When SMBUS input level selected
SDAMM, SCLMM
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
High peak
output current
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(peak)
IOL(avg)
-80.0
-10.0
-5.0
mA
mA
mA
mA
mA
mA
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
High level peak
output current
High level
average output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
Low peak
output current
80.0
10.0
5.0
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
Low level peak
output current
Low level
average output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to
P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
Main clock input oscillation frequency (2)
Sub clock oscillation oscillator frequency
PLL clock oscillation frequency (2)
f(XIN)
0
20
50
32
32
1
MHz
kHz
MHz
MHz
ms
f(XCIN)
f(PLL)
32.768
10
0
f(BCLK)
tsu(PLL)
Notes:
CPU operation frequency
Wait time to stabilize PLL frequency synthesizer
1.
2.
The mean output current is the mean value within 100ms.
Refer to “Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency”” for the relationship between main
clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
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5. Electrical Characteristics
K-Version
Main clock input oscillation frequency
PLL clock oscillation frequency
32.0
20.0 MHz
32.0 MHz
20.0
10.0
0.0
10.0
0.0
3.0
5.5
3.0
5.5
Vcc [V] (main clock: no division)
Vcc [V] (PLL clock oscillation)
Figure 5.32 Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency
(1)
Table 5.51
Recommended Operating Conditions (2/2)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40°C to 125°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt.
Standard
Typ.
Symbol
Parameter
Unit
Min.
Max.
0.5
VCC = 5.0 V
VCC = 3.0 V
VCC = 5.0 V
VCC = 3.0 V
Vp-p
Vp-p
V/ms
V/ms
Vr(VCC)
Allowable ripple voltage
0.3
0.3
dVr(VCC)/dt
Note:
Ripple voltage falling gradient
0.3
1. The device is operationally guaranteed under these operating conditions.
VCC
Vr(
VCC
)
Figure 5.33 Ripple Waveform
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Jul 23, 2010
Page 121 of 156
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5. Electrical Characteristics
K-Version
5.4.3
A/D Conversion Characteristics
(1)
Table 5.52
A/D Conversion Characteristics
V
= AV = V
= 3.0 to 5.5 V, V = AV = 0 V at T = -40°C to 125°C unless otherwise specified.
SS SS opr
CC
Symbol
—–
CC
REF
Standard
Typ.
Parameter
Measuring Condition
Unit
Min.
Max.
10
Resolution
VREF = VCC
Bits
(2)
(2)
(2)
(2)
±3
±5
±3
±5
LSB
VREF = VCC = 5.0 V
INL
Integral Non-Linearity Error
Absolute Accuracy
LSB
LSB
LSB
V
REF = VCC = 3.3 V
REF = VCC = 5.0 V
V
—–
VREF = VCC = 3.3 V
4.0 V ≤ VCC ≤ 5.5 V
3.2 V ≤ VCC ≤ 4.0 V
3.0 V ≤ VCC ≤ 3.2 V
2
2
2
25
16
10
MHz
MHz
MHz
kΩ
φAD
A/D operating clock frequency
—–
Tolerance Level Impedance
3
(2)
(2)
(2)
DNL
Differential Non-Linearity Error
±1
±3
±3
LSB
Offset Error (4)
Gain Error (4)
—–
—–
LSB
LSB
V
REF = VCC = 5V,
tCONV
10-bit Conversion Time
1.60
μs
φAD = 25 MHz
tsamp
VREF
VIA
Sampling time
0.6
3.0
0
μs
V
Reference Voltage
VCC
(3)
VREF
V
Analog Input Voltage
Notes:
1. Use when AV = V
CC
CC
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input
ports and connect them to V . See Figure 5.34 “A/D Accuracy Measure Circuit”.
SS
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
AN: One of the analog input pin
P0 to P10: I/O pins other than AN
Figure 5.34 A/D Accuracy Measure Circuit
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Page 122 of 156
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5. Electrical Characteristics
K-Version
5.4.4
D/A Conversion Characteristics
Table 5.53
D/A Conversion Characteristics
V
= AV = V
= 3.0 to 5.5 V, V = AV = 0 V at T = -40°C to 125°C unless otherwise specified.
CC
CC
REF SS SS opr
Standard
Typ.
Symbol
Parameter
Measuring Condition
Unit
Min.
Max.
8
-
-
Resolution
Bits
LSB
μs
Absolute Accuracy
Setup Time
2.5
3
tSU
RO
Output Resistance
5
6
8.2
1.5
kΩ
See Notes 1 and 2
IVREF
Reference Power Supply Input Current
mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
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5. Electrical Characteristics
K-Version
5.4.5
Flash Memory Electrical Characteristics
Table 5.54
CPU Clock When Operating Flash Memory (f(BCLK))
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
CPU rewrite mode
Conditions
Min.
Typ.
Max.
16 (1)
5 (3)
35
-
MHz
MHz
kHz
f(SLOW_R)
Slow read mode
-
-
Low current consumption read mode
Data flash read
fC
20 (2)
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). No wait states are required if the 125 kHz on-chip oscillator
clock or sub clock is used as the clock source of the CPU clock.
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5. Electrical Characteristics
K-Version
Table 5.55
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = 0°C to 60°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Program/erase cycles (1, 3, 4)
Two words program time
Lock bit program time
Block erase time
1,000 (2)
-
-
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
times
μs
150
70
4000
3000
3.0
V
CC = 3.3 V, Topr = 25°C
CC = 3.3 V, Topr = 25°C
μs
-
V
0.2
s
3
Time delay from suspend request
until suspend
5 + ---------------
td(SR-SUS)
-
ms
f(BCLK)
Interval from erase start/restart
until following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
-
-
ms
20
1
Time from suspend until erase
restart
30 + ---------------
μs
f(BCLK)
-
Program, erase voltage
Read voltage
3.0
3.0
0
5.5
5.5
60
V
V
-
Topr = -40°C to 125°C
-
Program, erase temperature
°C
μs
tPS
-
Flash Memory Circuit Stabilization Wait Time
Ambient temperature = 55°C
50
Data hold time (6)
20
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word
data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be
written to the same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
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Page 125 of 156
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5. Electrical Characteristics
K-Version
Table 5.56
Flash Memory (Data Flash) Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Program/erase cycles (1, 3, 4)
Two words program time
Lock bit program time
Block erase time
10,000 (2)
-
-
-
-
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
times
μs
300
140
0.2
4000
3000
3.0
μs
s
3
td(SR-SUS)
Time delay from suspend request
until suspend
5 + ---------------
ms
f(BCLK)
-
-
Interval from erase start/restart until
following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
ms
20
1
-
Time from suspend until erase
restart
30 + ---------------
μs
f(BCLK)
-
Program, erase voltage
Read voltage
3.0
3.0
−40
5.5
5.5
125
50
V
V
-
-
Program, erase temperature
°C
μs
tPS
Flash Memory Circuit Stabilization Wait Time
Ambient temperature = 55 °C
Data hold time (6)
-
20
year
Notes:
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request,
the erase sequence cannot be completed.
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Jul 23, 2010
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5. Electrical Characteristics
K-Version
5.4.6
E2PROM Emulation Data Flash
2
Table 5.57
E PROM Emulation Data Flash Electrical Characteristics
VCC = 3.0 to 5.5 V at Topr = -40°C to 125°C, unless otherwise specified.
Value
Unit
Symbol
Characteristic
Program/erase cycles (1)
Min.
Typ.
Max.
—
—
—
—
100000
times
µs
Word program time (2-byte program)
Read time (2-byte read)
100
2000
1
µs
Block erase time (32-byte block)
15
35
200
ms
Flash memory circuit stabilization wait time
(sleep mode to normal mode)
tPS
50
µs
Data hold time (2)
Ambient temperature = 55°C (3, 4)
—
20
years
Notes:
1. Definition of program/erase cycles definition
This value represents the number of erasure per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it
is considered the programming/erasure is performed just once. However a write in the same
address more than once for one erasure is disabled. (overwrite disabled).
2. The data hold time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data hold time includes (3000) hours in Ambient temperature = 125°C.
4. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
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Page 127 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
5.4.7
Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.58
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.
Standard
Symbol
Vdet0
Parameter
Condition
When VCC is falling.
VCC = 3.0 to 5.0 V
Unit
V
Min.
2.70
Typ. Max.
Voltage detection level Vdet0
2.85
3.00
Waiting time until voltage detector operation
starts (1)
td(E-A)
100
μs
Note:
1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
Table 5.59
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40°C to 125°C, unless otherwise specified.
Standard
Symbol
Parameter
Condition
Unit
Min.
3.51
Typ. Max.
3.21
Vdet2_0
V
V
V
V
V
V
V
V
Voltage detection level Vdet2_0
Vdet2_1 Voltage detection level Vdet2_1
Vdet2_2 Voltage detection level Vdet2_2
Vdet2_3 Voltage detection level Vdet2_3
3.36
3.51
3.66
When VCC is falling
Vdet2_4
3.81
3.96
4.10
4.25
4.11
Voltage detection level Vdet2_4
Vdet2_5 Voltage detection level Vdet2_5
Vdet2_6 Voltage detection level Vdet2_6
Vdet2_7 Voltage detection level Vdet2_7
Hysteresis width at the rising of VCC in voltage
-
0.15
V
detector 2
(1)
td(E-A)
Note:
V
= 3.0 to 5.0 V
100
μs
Waiting time until voltage detector operation starts
CC
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
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Jul 23, 2010
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
Table 5.60
Power-On Reset Circuit
The measurement condition is Topr = -40°C to 125°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Condition
Min.
2.0
Typ.
Max.
trth
External power VCC rise gradient
External power VCC fall gradient
50000 mV/ms
50000 mV/ms
tfth
Voltage at which power-on reset enabled (1)
Hold time at which power-on reset enabled
Vpor
tw(por)
0.1
V
1.0
ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0.
Vdet0
Vdet0
trth
trth
V
CC
External Power
tfth
Vpor
tw(por)
Internal
reset signal
1
1
× 128
× 128
fOCO-S
fOCO-S
Figure 5.35 Power-On Reset Circuit Electrical Characteristics
Table 5.61
Power Supply Circuit Timing Characteristics
Standard
Symbol
td(P-R)
Parameter
Measuring Condition
Unit
ms
Min. Typ. Max.
Time for Internal Power Supply Stabilization VCC = 3.0 V to 5.5V
During Powering-On
5
td(R-S)
td(W-S)
STOP Release Time
300
300
μs
μs
Low Power Mode Wait Mode Release Time
Note:
1. When V
= 5 V.
CC
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 129 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version
Recommended
operating
voltage
td(P-R)
VCC
Time to stabilize internal supply
voltage during powering-on
td(P-R)
CPU clock
(a) Interrupt to exit from stop mode
(b) Interrupt to exit from wait mode
td(R-S)
STOP release time
td(W-S)
Low power consumption
mode wait mode exit time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
td(E-A)
VC25, VC27
Voltage detection circuit
operation start time
Voltage detection circuit
Stop
Operate
td(E-A)
Figure 5.36 Power Supply Circuit Timing Diagram
5.4.8
Oscillation Circuit Electrical Characteristics
Table 5.62
On-chip Oscillator Oscillation Circuit Electrical Characteristics
VCC = 3.0 to 5.5 V, Topr = −40°C to 125°C, unless otherwise specified
Value
Typ.
125
Unit
Symbol
Characteristic
Min.
100
32
Max.
150
48
fOCO-S
fOCO40M
125 kHz on-chip oscillator oscillation frequency
40 kHz on-chip oscillator oscillation frequency
kHz
40
MHz
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 130 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
5.5
5.5.1
Electrical Characteristics (K-Version, V = 5 V)
CC
Electrical Characteristics
K-Version, VCC = 5 V
Table 5.63
Electrical Characteristics (1)
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK) = 32 MHz unless otherwise specified.
Standard
Symbol
Parameter
Measuring Condition
Unit
V
Min.
Typ.
Max.
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
VOH
IOH=−5 mA
V
CC−2.0
HIGH Output Voltage
HIGH Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
VOH
IOH = −200 μA
VCC−−0.3
VCC
V
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
HIGH POWER
LOW POWER
IOH = −1 mA
VCC−−2.0
VCC−−2.0
VCC
VCC
V
V
IOH = −0.5 mA
VOH
HIGH POWER
LOW POWER
With no load applied
With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
VOL
IOL = 5 mA
LOW Output Voltage
LOW Output Voltage
2.0
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
VOL
IOL = 200 μA
0.45
HIGH POWER
IOL = 1 mA
2.0
2.0
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
LOW POWER
IOL = 0.5 mA
VOL
HIGH POWER
LOW POWER
With no load applied
With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7,
NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,
CLK0 to CLK4, TA0OUT to TA4OUT,
VT+-VT-
0.4VCC
Hysteresis
0.2
V
KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,
SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0,
LIN0IN, CRX0, CRX1
VT+-VT-
VT+-VT-
RESET
Hysteresis
Hysteresis
0.2
0.2
2.5
0.8
V
V
XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
IIH
VI = 5 V
HIGH Input Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
5.0
μA
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
IIL
VI = 0 V
VI = 0 V
LOW Input Current
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 toP9_7, P10_0 to P10_7
XIN, RESET, CNVSS
−5.0
μA
kΩ
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
Pull-Up
Resistance
RPULLUP
30
50
170
RfXIN
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
1.5
15
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 131 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Table 5.64
Electrical Characteristics (2)
T
= −40°C to 125°C unless otherwise specified.
opr
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
f(BCLK) = 32 MHz,
25
21
17
45
39
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
High speed mode
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
No division
21
6
39
mA
mA
40 MHz on-chip oscillator
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Divide-by-8
125 kHz on-chip oscillator
mode
190
580
μA
FMR22 = FMR23 = 1 (Low-current consumption
read mode)
f
(BCLK) = 32 kHz
Power Supply Current
(VCC = 4.2 V to 5.5 V)
In single-chip mode, the
output pins are open and
other pins are VSS
On Flash memory (2)
FMR22 = FMR23 = 1 (Low-current consumption
read mode)
Main clock stops
Low power mode
200
25
μA
μA
ICC
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 105°C
Wait mode
85
μA
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 125°C
125
T
opr = 25°C
3
15
μA
μA
Topr = 105°C
Topr = 125°C
60
Stop mode
100
μA
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
During flash memory
program
20.0
mA
f
(BCLK) = 10 MHz, PM17 = 1 (one wait)
During flash memory
erase
30.0
mA
VCC = 5.0 V
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
Note:
1. This indicates the memory in which the program to be executed exists.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 132 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
5.5.2
Timing Requirements (Peripheral Functions and Others)
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.5.2.1
Reset Input (RESET Input)
Table 5.65
Reset Input (RESET Input)
Parameter
Standard
Unit
Symbol
tw(RSTL)
Min.
Max.
RESET input low pulse width
10
μs
RESET input
tw(RTSL)
Figure 5.37 Reset Input (RESET Input)
5.5.2.2
External Clock Input
(1)
Table 5.66
External Clock Input (XIN input)
Standard
Max.
Symbol
Parameter
Unit
Min.
50
tc
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
20
20
9
9
tf
External clock fall time
Note:
1. The condition is V = 5.0V.
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.38 External Clock Input (XIN Input)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 133 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.5.2.3
Timer A Input
Table 5.67
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN input cycle time
100
40
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
40
Table 5.68
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.69
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.70
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.39 Timer A Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 134 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
Table 5.71
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
Symbol
tc(TA)
Parameter
Unit
Min.
800
200
200
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.40 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 135 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.5.2.4
Timer B Input
Table 5.72
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
100
40
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high pulse width (counted on one edge)
TBiIN input low pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input high pulse width (counted on both edges)
TBiIN Input low pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.73
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
Table 5.74
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.41 Timer B Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 136 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.5.2.5
Table 5.75
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Standard
Symbol
tw(TSH)
Parameter
Unit
Min.
2
Max.
TSUDA, TSUDB input high pulse width
TSUDA, TSUDB input low pulse width
TSUDB input setup time
μs
μs
μs
μs
t
2
w(TSL)
t
1
su(TSUDA-TSUDB)
t
TSUDA input setup time
1
su(TSUDB-TSUDA)
Two-phase pulse input in two-phase pulse signal processing mode
t
w(TSH)
t
w(TSL)
TSUDA input
t
t
su(TSUDA-TSUDB)
su(TSUDA-TSUDB)
t
t
w(TSH)
su(TSUDB-TSUDA)
t
w(TSL)
TSUDB input
Note:
t
su(TSUDB-TSUDA)
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.42 Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 137 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.5.2.6
Serial Interface
Table 5.76
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input high pulse width
CLKi input low pulse width
TXDi output delay time
TXDi hold time
200
100
100
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
RXDi input setup time
RXDi input hold time
70
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.43 Serial Interface
5.5.2.7
External Interrupt INTi Input
Table 5.77
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi input high pulse width
INTi input low pulse width
tw(INL)
INTi input
tw(INH)
Figure 5.44 External Interrupt INTi Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 138 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
CC
SS
opr
2
5.5.2.8
Multi-master I C-bus
2
Table 5.78
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.45 Multi-master I C-bus
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 139 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T
= −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.5.2.9
Serial bus interface
Table 5.79
Serial Bus Interface
Value
Typ.
Measurement
condition
Symbol
Characteristic
Unit
Min.
250
0.4
Max.
tc(SSCK)
tw(SSCKH)
tw(SSCKL)
SSCK clock cycle time
ns
tc(SSCK)
tc(SSCK)
SSCK clock high pulse width
SSCK clock low pulse width
0.6
0.6
1
0.4
(1)
tCYC
Master
Slave
tr(SSCK)
SSCK clock rising time
SSCK clock falling time
1
μs
(1)
tCYC
Master
Slave
1
tf(SSCK)
1
μs
tsu(SSIO-SSCK)
th(SSCK-SSIO)
tsu(SCS-SSCK)
th(SSCK-SCS)
td(SSCK-SSIO)
ten(SCS-SSI)
SSO, SSI data input setup time
SSO, SSI data input hold time
100
1
ns
(1)
tCYC
1 tCYC + 50 (1)
1 tCYC + 50 (1)
SCS setup time
SCS hold time
Slave
Slave
ns
ns
(1)
tCYC
SS0, SSI data output delay time
SSI output enable time
1
1.5 tCYC + 100 (1)
1.5 tCYC + 100 (1)
3.0 V ≤ VCC ≤ 5.5 V
3.0 V ≤ VCC ≤ 5.5 V
ns
ns
tdis(SCS-SSI)
SSI output disable time
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 140 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t h(SSCK-SSIO)
t su(SSIO-SSCK)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.46 I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 141 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t h(SSCK-SCS)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
t d(SSCK-SSIO)
t dis(SCS-SSI)
t en(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
t su(SCS-SSCK)
t r(SSCK)
t h(SSCK-SCS)
t w(SSCKH)
t f(SSCK)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t
t
s
u
(
S
S
I
O
-
S
S
C
K
)
h
(
S
S
C
K
-
S
S
I
O
)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.47 I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 142 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 5 V
tw(SSCKH)
VIH or VOH
SSCK
VIL or VOL
tc(SSCK)
tw(SSCKL)
SSO (output)
SSI (input)
td(SSCK-SSIO)
tsu(SSIO-SSCK)
th(SSCK-SSIO)
Figure 5.48 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
30 pF
Figure 5.49 Switching Characteristic Measurement Circuit
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 143 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
5.6
5.6.1
Electrical Characteristics (K-Version, V = 3 V)
CC
Electrical Characteristics
K-Version, VCC = 3 V
Table 5.80
Electrical Characteristics (1)
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = −40°C to 125°C, f(BCLK)=32 MHz unless otherwise specified.
Standard
Symbol
Parameter
Measuring Condition
Unit
V
Min.
Typ.
Max.
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to
P7_7, P8_0 to P8_4, P8_6 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
HIGH
Output
Voltage
VOH
I
OH = −1 mA
VCC−0.5
IOH = −0.1 mA
IOH = −50 μA
VCC−0.5
VCC−0.5
VCC
VCC
HIGH POWER
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
V
V
LOW POWER
VOH
VOL
VOL
HIGH POWER With no load applied
LOW POWER With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
LOW
Output
Voltage
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
IOL = 1mA
0.5
V
IOL = 0.1mA
OL = 50μA
HIGH POWER
0.5
0.5
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
I
LOW POWER
HIGH POWER With no load applied
LOW POWER With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB5IN, INT0
to INT7, NMI, ADTRG, CTS0 to CTS3,
SCL2, SDA2, CLK0 to CLK4, TA0OUT
Hysteresis to TA4OUT, KI0 to KI3, RXD0 to RXD4,
ZP, IDU, IDW, IDV, SD, INPC1_0 to
INPC1_7, SSI0, SSCK0, SCS0, LIN0IN,
CRX0, CRX1
VT+-VT-
0.4VCC
V
VT+-VT-
T+-VT-
Hysteresis RESET
1.8
0.8
V
V
V
Hysteresis
XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
HIGH Input to P5_7, P6_0 to P6_7, P7_0 to P7_7,
IIH
VI = 3V
4.0
μA
Current
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
LOW Input to P5_7, P6_0 to P6_7, P7_0 to P7_7,
IIL
VI = 0V
VI = 0V
−4.0
μA
kΩ
Current
P8_0 to P8_7, P9_0 to P9_7, P10_0 to
P10_7
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0
to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6 to P8_7, P9_0 to
P9_7, P10_0 to P10_7
Pull-Up
Resistance
RPULLUP
50
100
500
RfXIN
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
3.0
25
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 144 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Table 5.81
Electrical Characteristics (2)
Topr = −40°C to 125°C unless otherwise specified.
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
f(BCLK) = 32 MHz,
23
20
16
43
38
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125 kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125 kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125 kHz on-chip oscillator operates
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
No division
20
6
38
mA
mA
40 MHz on-chip oscillator
mode
Main clock stops
40 MHz on-chip oscillator operates
125 kHz on-chip oscillator operates
Divide-by-8
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator 125 kHz on-chip oscillator operates
190
580
μA
mode
Divide-by-8
FMR22 = FMR23 = 1 (Low-current consumption read
mode)
f
(BCLK) = 32 kHz
Power Supply Current
(VCC = 3.0 V to 3.6 V)
In single-chip mode, the
output pins are open and
other pins are VSS
On ROM
Low power mode
200
25
μA
μA
FMR22 = FMR23 = 1 (Low-current consumption read
mode)
ICC
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
Topr = 105°C
Wait mode
85
μA
μA
Main clock stops
40 MHz on-chip oscillator stops
125 kHz on-chip oscillator operates
Peripheral clock operates
125
Topr = 125°C
T
opr = 25°C
2
12
μA
μA
μA
Topr = 105°C
Topr = 125°C
Stop mode
60
100
f
(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
During flash memory
program
20.0
30.0
mA
mA
f
During flash memory
erase
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 145 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
5.6.2
Timing Requirements (Peripheral Functions and Others)
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.6.2.1
Reset Input (RESET Input)
Table 5.82
Reset Input (RESET Input)
Parameter
Standard
Unit
Symbol
tw(RSTL)
Min.
Max.
RESET input low pulse width
10
μs
RESET input
tw(RTSL)
Figure 5.50 Reset Input (RESET Input)
5.6.2.2
External Clock Input
(1)
Table 5.83
External Clock Input (XIN input)
Standard
Max.
Symbol
Parameter
Unit
Min.
50
tc
External clock input cycle time
External clock input high pulse width
External clock input low pulse width
External clock rise time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
20
20
9
9
tf
External clock fall time
Note:
1. The condition is V = 3.0V.
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.51 External Clock Input (XIN Input)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 146 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.6.2.3
Timer A Input
Table 5.84
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN input cycle time
150
60
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
60
Table 5.85
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
600
300
300
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.86
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
300
150
150
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
Table 5.87
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
tw(TAH)
tw(TAL)
TAiIN input high pulse width
TAiIN input low pulse width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.52 Timer A Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 147 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
Table 5.88
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
Symbol
tc(TA)
Parameter
Unit
Min.
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
μs
ns
ns
t
500
500
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.53 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 148 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.6.2.4
Timer B Input
Table 5.89
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
150
60
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high pulse width (counted on one edge)
TBiIN input low pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input high pulse width (counted on both edges)
TBiIN Input low pulse width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.90
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
Table 5.91
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input high pulse width
TBiIN input low pulse width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.54 Timer B Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 149 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.6.2.5
Table 5.92
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Standard
Symbol
tw(TSH)
Parameter
Unit
Min.
2
Max.
TSUDA, TSUDB input high pulse width
TSUDA, TSUDB input low pulse width
TSUDB input setup time
μs
μs
μs
μs
t
2
w(TSL)
t
1
su(TSUDA-TSUDB)
t
TSUDA input setup time
1
su(TSUDB-TSUDA)
Two-phase pulse input in two-phase pulse signal processing mode
t
w(TSH)
t
w(TSL)
TSUDA input
t
t
su(TSUDA-TSUDB)
su(TSUDA-TSUDB)
t
t
w(TSH)
su(TSUDB-TSUDA)
t
w(TSL)
TSUDB input
Note:
t
su(TSUDB-TSUDA)
1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA)
are also interchanged.
Figure 5.55 Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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Jul 23, 2010
Page 150 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
5.6.2.6
Serial Interface
Table 5.93
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input high pulse width
CLKi input low pulse width
TXDi output delay time
TXDi hold time
300
150
150
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
160
0
RXDi input setup time
RXDi input hold time
100
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.56 Serial Interface
5.6.2.7
External Interrupt INTi Input
Table 5.94
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
tw(INL)
INTi input
tw(INH)
Figure 5.57 External Interrupt INTi Input
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 151 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40°C to 125°C unless otherwise specified)
opr
CC
SS
2
5.6.2.8
Multi-master I C-bus
2
Table 5.95
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.58 Multi-master I C-bus
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 152 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T
= −40°C to 125°C unless otherwise specified)
CC
SS
opr
5.6.2.9
Serial bus interface
Table 5.96
Serial Bus Interface
Value
Typ.
Measurement
condition
Symbol
Characteristic
Unit
Min.
250
0.4
Max.
tc(SSCK)
tw(SSCKH)
tw(SSCKL)
SSCK clock cycle time
ns
tc(SSCK)
tc(SSCK)
SSCK clock high pulse width
SSCK clock low pulse width
0.6
0.6
1
0.4
(1)
tCYC
Master
Slave
tr(SSCK)
SSCK clock rising time
SSCK clock falling time
1
μs
(1)
tCYC
Master
Slave
1
tf(SSCK)
1
μs
tsu(SSIO-SSCK)
th(SSCK-SSIO)
tsu(SCS-SSCK)
th(SSCK-SCS)
td(SSCK-SSIO)
ten(SCS-SSI)
SSO, SSI data input setup time
SSO, SSI data input hold time
100
1
ns
(1)
tCYC
1 tCYC + 50 (1)
1 tCYC + 50 (1)
SCS setup time
SCS hold time
Slave
Slave
ns
ns
(1)
tCYC
SS0, SSI data output delay time
SSI output enable time
1
1.5 tCYC + 100 (1)
1.5 tCYC + 100 (1)
3.0 V ≤ VCC ≤ 5.5 V
3.0 V ≤ VCC ≤ 5.5 V
ns
ns
tdis(SCS-SSI)
SSI output disable time
Note:
1.
1 tCYC is 1/f1 (s).
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 153 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t h(SSCK-SSIO)
t su(SSIO-SSCK)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
t w(SSCKH)
t f(SSCK)
t r(SSCK)
SSCK (output)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (output)
(CPOS =0)
t c(SSCK)
t w(SSCKL)
SSO (output)
SSI (input)
t d(SSCK-SSIO)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.59 I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 154 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
t r(SSCK)
t h(SSCK-SCS)
t f(SSCK)
t su(SCS-SSCK) t w(SSCKH)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
t d(SSCK-SSIO)
t dis(SCS-SSI)
t en(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
t su(SCS-SSCK)
t r(SSCK)
t h(SSCK-SCS)
t w(SSCKH)
t f(SSCK)
SSCK (input)
(CPOS = 1)
t w(SSCKL)
t w(SSCKH)
SSCK (input)
(CPOS = 0)
t c(SSCK)
t w(SSCKL)
SSO (input)
SSI (output)
t
t
s
u
(
S
S
I
O
-
S
S
C
K
)
h
(
S
S
C
K
-
S
S
I
O
)
t en(SCS-SSI)
t d(SSCK-SSIO)
t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.60 I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 155 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
tw(SSCKH)
VIH or VOH
SSCK
VIL or VOL
tc(SSCK)
tw(SSCKL)
SSO (output)
SSI (input)
td(SSCK-SSIO)
tsu(SSIO-SSCK)
th(SSCK-SSIO)
Figure 5.61 I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be
measured
30 pF
Figure 5.62 Switching Characteristic Measurement Circuit
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 156 of 156
REVISION HISTORY
M16C/5M Group Datasheet
Description
Summary
Rev.
1.01
Date
Page
—
Jul 23, 2010
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
A- 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
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depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2010 Renesas Electronics Corporation. All rights reserved.
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