R5F364AKNFA#U0_技术文档

Datasheet

M16C/64A Group

RENESAS MCU

R01DS0032EJ0200

Rev.2.00

Feb 07, 2011

1. Overview

1.1

Features

The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash

memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address

space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the

CPU core boasts a multiplier for high-speed operation processing.

This MCU consumes low power, and supports operating modes that allow additional power control. The

MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed

to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including

the multifunction timer and serial interface, the number of system components has been reduced.

1.1.1

Applications

This MCU can be used in audio components, cameras, televisions, household appliances, office

equipment, communication devices, mobile devices, industrial equipment, and other applications.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 1 of 88

M16C/64A Group

1. Overview

1.2

Specifications

The M16C/64A Group includes 100-pin package. Table 1.1 and Table 1.2 list specifications.

Table 1.1

Item

Specifications for the 100-Pin Package (1/2)

Function

Description

M16C/60 Series core

(multiplier: 16 bit × 16 bit ꢀ 32 bit,

multiply and accumulate instruction: 16 bit × 16 bit + 32 bit ꢀ 32 bit)

•Number of basic instructions: 91

CPU

Central processing unit

•Minimum instruction execution time:

40.0 ns (f(BCLK) = 25 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)

•Operating modes: Single-chip, memory expansion, and microprocessor

Memory

ROM, RAM, data flash

Voltage detector

See Table 1.3 “Product List”.

•Power-on reset

Voltage

Detection

•3 voltage detection points (detection level of voltage detection 0 and 1

selectable)

•4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),

PLL frequency synthesizer

•Oscillation stop detection: Main clock oscillation stop/restart detection

function

Clock

Clock generator

•Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16

•Power saving features: Wait mode, stop mode

•Real-time clock

•Address space: 1 MB

•External bus interface: 0 to 3 waits inserted, 4 chip select outputs,

memory area expansion function (expandable to 4 MB), 3 V and 5 V

interfaces

•Bus format: Separate bus or multiplexed bus selectable, data bus width

selectable (8 or 16 bits), number of address buses selectable (12, 16, or

20)

External Bus

Expansion

Bus memory expansion

Programmable I/O ports

•CMOS I/O ports: 85 (selectable pull-up resistors)

•N-channel open drain ports: 3

I/O Ports

Interrupts

•Interrupt vectors: 70

•External interrupt inputs: 13 (NMI, INT × 8, key input × 4)

•Interrupt priority levels: 7

15-bit timer × 1 (with prescaler)

Automatic reset start function selectable

Watchdog Timer

•4 channels, cycle steal mode

DMA

DMAC

•Trigger sources: 43

•Transfer modes: 2 (single transfer, repeat transfer)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 2 of 88

M16C/64A Group

1. Overview

Table 1.2

Specifications for the 100-Pin Package (2/2)

Item

Function

Description

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse width

modulation (PWM) mode

Event counter two-phase pulse signal processing (two-phase encoder

input) × 3

Timer A

Programmable output mode × 3

16-bit timer × 6

Timer B

Timer mode, event counter mode, pulse period measurement mode,

pulse width measurement mode

• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)

• On-chip dead time timer

Timers

Three-phase motor control

timer functions

Real-time clock

PWM function

Count: seconds, minutes, hours, days of the week

8 bits × 2

• 2 circuits

• 4 wave pattern matchings (differentiate wave pattern for headers, data

0, data 1, and special data)

Remote control signal receiver

• 6-byte receive buffer (1 circuit only)

• Operating frequency of 32 kHz

Clock synchronous/asynchronous × 6 channels

I²C-bus, IEBus, special mode 2

SIM (UART2)

UART0 to UART2, UART5 to

UART7

Serial

Interface

SI/O3, SI/O4

Clock synchronization only × 2 channels

1 channel

Multi-master I²C-bus Interface

CEC transmit/receive, arbitration lost detection, ACK automatic output,

operation frequency of 32 kHz

CEC Functions ⁽²⁾

10-bit resolution × 26 channels, including sample and hold function

Conversion time: 1.72 µs

A/D Converter

D/A Converter

CRC Calculator

8-bit resolution × 2 circuits

CRC-CCITT (X¹⁶+ X¹²+ X⁵+ 1),

CRC-16 (X¹⁶+ X¹⁵+ X²+ 1) compliant

• Program and erase power supply voltage: 2.7 to 5.5 V

• Program and erase cycles: 1,000 times (program ROM 1, program

ROM 2), 10,000 times (data flash)

Flash Memory

• Program security: ROM code protect, ID code check

Debug Functions

On-chip debug, on-board flash rewrite, address match interrupt × 4

25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1

Described in Electrical Characteristics

Operation Frequency/Supply Voltage

Current Consumption

-20°C to 85°C, -40°C to 85°C ⁽¹⁾

Operating Temperature

100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)

100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)

Package

Notes:

1. See Table 1.3 “Product List” for the operating temperature.

2. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized

by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are

registered trademarks of HDMI Licensing, LLC.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 3 of 88

M16C/64A Group

1. Overview

1.3

Product List

Table 1.3 lists product information. Figure 1.1 shows the Part No., with Memory Size and Package, and

Figure 1.2 shows the Marking Diagram (Top View).

Table 1.3

Product List

As of December 2010

Package Code Remarks

PRQP0100JD-B Operating

ROM Capacity

RAM

Capacity

Part No.

Program

ROM 2

Data flash

ROM 1

128 KB

R5F364A6NFA

R5F364A6NFB

R5F364A6DFA

R5F364A6DFB

R5F364AENFA

R5F364AENFB

R5F364AEDFA

R5F364AEDFB

R5F364AKNFA

R5F364AKNFB

R5F364AKDFA

R5F364AKDFB

R5F364AMNFA

R5F364AMNFB

R5F364AMDFA

R5F364AMDFB

16 KB

4 KB

12 KB

20 KB

31 KB

× 2 blocks

temperature

-20°C to 85°C

PLQP0100KB-A

PRQP0100JD-B Operating

temperature

-40°C to 85°C

PLQP0100KB-A

256 KB

384 KB

512 KB

4 KB

× 2 blocks

PRQP0100JD-B Operating

temperature

-20°C to 85°C

PLQP0100KB-A

PRQP0100JD-B Operating

temperature

-40°C to 85°C

PLQP0100KB-A

4 KB

× 2 blocks

PRQP0100JD-B Operating

temperature

-20°C to 85°C

PLQP0100KB-A

PRQP0100JD-B Operating

temperature

-40°C to 85°C

PLQP0100KB-A

4 KB

× 2 blocks

PRQP0100JD-B Operating

temperature

-20°C to 85°C

PLQP0100KB-A

PRQP0100JD-B Operating

temperature

-40°C to 85°C

PLQP0100KB-A

(D): Under development

(P): Planning

Previous package codes are as follows:

PRQP0100JD-B: 100P6F-A

PLQP0100KB-A: 100P6Q-A

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 4 of 88

M16C/64A Group

Part No.

1. Overview

R 5 F 3 6 4 A 6 D FA

Package type

FA: Package PRQP0100JD-B (100P6F-A)

FB: Package PLQP0100KB-A (100P6Q-A)

Property code

N: Operating temperature: -20°C to 85°C

D: Operating temperature: -40°C to 85°C

Memory capacity

Program ROM 1/RAM

6: 128 KB/12 KB

E: 256 KB/20 KB

K: 384 KB/31KB

M: 512 KB/31 KB

M16C/64A Group (100 pins)

16-bit MCU

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.1

Part No., with Memory Size and Package

M1 6 C

R 5 F 3 6 4 A 6 D F A

Type No.

(See Figure 1.1 “Part No., with Memory Size and Package”)

ꢀꢀ

X X X X X X X

Running No. 0 to 9, A to Z (except for I, O, Q)

Week code (from 01 to 54)

Last digit of year

Figure 1.2

Marking Diagram (Top View)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

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M16C/64A Group

1. Overview

1.4

Block Diagram

Figure 1.3 shows block diagram.

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

VCC2 ports

Internal peripheral functions

System clock generator

UART or

clock synchronous serial I/O

(6 channels)

XIN-XOUT

XCIN-XCOUT

Timer (16 bit)

Outputs (timer A): 5

Inputs (timer B): 6

PLL frequency synthesizer

On-chip oscillator (125 kHz)

Clock synchronous serial I/O

(8 bit x 2 channels)

Three-phase motor control

circuit

Multi-master I²C-bus interface

(1 channel)

DMAC (4 channels)

Real-time clock

CRC calculator

(CRC-CCITT or CRC-16)

CEC function

PWM function (8 bit x 2)

Voltage detector

Power-on reset

Remote control signal

receiver (2 circuits)

Watchdog timer

(15 bit)

On-chip debugger

A/D converter

(10-bit resolution x 26

channels)

Memory

ROM ⁽¹⁾

M16C/60 Series CPU core

SB

USP

ISP

R0H

R1H

R0L

R1L

D/A converter

(8-bit resolution x 2

circuits)

R2

R3

RAM ⁽²⁾

INTB

PC

FLG

A0

A1

FB

Multiplier

VCC1 ports

Port P10

8

Port P9

8

Port P8

8

Port P7

8

Port P6

8

Notes:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Figure 1.3

Block Diagram for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 6 of 88

M16C/64A Group

1. Overview

1.5

Pin Assignments

Figure 1.4 and Figure 1.5 show pin assignments. Table 1.4 and Table 1.5 list pin names.

See Note 3

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P4_4/CTS7/RTS7/CS0

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P4_5/CLK7/CS1

P4_6/PWM0/RXD7/SCL7/CS2

P4_7/PWM1/TXD7/SDA7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/RTCOUT/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

VCC2 ports

M16C/64A Group

PRQP0100JD-B

(100P6F-A)

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

(Top view)

VREF

AVCC

P9_7/ADTRG/SIN4

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

VCC1 ports

Notes:

1. N-channel open drain output.

2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.

3. Pin names in brackets [ ] represent a single functional signal.

They should not be considered as two separate functional signals.

Figure 1.4

Pin Assignment for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 7 of 88

M16C/64A Group

1. Overview

See Note 3

P1_2/RXD6/SCL6/D10

P1_1/CLK6/D9

P1_0/CTS6/RTS6/D8

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P4_2/A18

P4_3/A19

P4_4/CTS7/RTS7/CS0

P4_5/CLK7/CS1

P4_6/PWM0/RXD7/SCL7/CS2

P4_7/PWM1/TXD7/SDA7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

VCC2 ports

M16C/64A Group

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

PLQP0100KB-A

(100P6Q-A)

(Top view)

P5_7/RDY/CLKOUT

P6_0/RTCOUT/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P7_0/TXD2/SDA2/SDAMM/TA0OUT ⁽¹⁾

P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN ⁽¹⁾

P7_2/CLK2/TA1OUT/V

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

P9_5/ANEX0/CLK4

VCC1 ports

Notes:

1. N-channel open drain output.

2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.

3. Pin names in brackets [ ] represent a single functional signal.

They should not be considered as two separate functional signals.

Figure 1.5

Pin Assignment for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 8 of 88

M16C/64A Group

1. Overview

Table 1.4

Pin Names for the 100-Pin Package (1/2)

I/O Pin for Peripheral Function

Pin No.

Bus Control

Control Pin Port

A/D converter,

D/A converter

ANEX1

FA FB

Interrupt

Timer

Serial interface

1

2

3

99

100

1

P9_6

P9_5

P9_4

P9_3

P9_2

SOUT4

CLK4

ANEX0

DA1

DA0

TB4IN/PWM1

TB3IN/PWM0

TB2IN/PMC0

TB1IN/PMC1

TB0IN

4

2

5

3

SOUT3

SIN3

CLK3

6

4

P9_1

P9_0

7

5

8

6

BYTE

9

7

CNVSS

10

11

8

9

XCIN

XCOUT

P8_7

P8_6

12 10

13 11

14 12

15 13

16 14

17 15

RESET

XOUT

VSS

XIN

VCC1

P8_5

P8_4

P8_3

P8_2

CEC

NMI

INT2

INT1

INT0

SD

ZP

18 16

19 17

20 18

21 19

22 20

23 21

24 22

25 23

26 24

27 25

28 26

29 27

30 28

31 29

32 30

33 31

P8_1

P8_0

P7_7

P7_6

P7_5

P7_4

P7_3

P7_2

P7_1

P7_0

P6_7

P6_6

P6_5

TA4IN/U

TA4OUT/U

TA3IN

CTS5/RTS5

RXD5/SCL5

CLK5

TA3OUT

TXD5/SDA5

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA0IN/TB5IN

TA0OUT

CTS2/RTS2

CLK2

RXD2/SCL2/SCLMM

TXD2/SDA2/SDAMM

TXD1/SDA1

RXD1/SCL1

CLK1

CTS1/RTS1/CTS0

/CLKS1

34 32

P6_4

35 33

36 34

37 35

38 36

P6_3

P6_2

P6_1

P6_0

TXD0/SDA0

RXD0/SCL0

CLK0

RTCOUT

CTS0/RTS0

39 37 CLKOUT P5_7

RDY

40 38

41 39

42 40

43 41

44 42

45 43

46 44

47 45

48 46

49 47

50 48

P5_6

P5_5

P5_4

P5_3

P5_2

P5_1

P5_0

P4_7

P4_6

P4_5

P4_4

ALE

HOLD

HLDA

BCLK

RD

WRH/BHE

WRL/WR

CS3

PWM1

PWM0

TXD7/SDA7

RXD7/SCL7

CLK7

CS2

CS1

CS0

CTS7/RTS7

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

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M16C/64A Group

1. Overview

Table 1.5

Pin Names for the 100-Pin Package (2/2)

I/O Pin for Peripheral Function

Pin No.

Control

Port

A/D converter,

D/A converter

Bus Control Pin

FA FB

Interrupt

Timer

Serial interface

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

P4_3

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

VCC2

VSS

P3_0

A8, [A8/D7]

P2_7

P2_6

P2_5

AN2_7

AN2_6

AN2_5

A7, [A7/D7], [A7/D6]

A6, [A6/D6], [A6/D5]

A5, [A5/D5], [A5/D4]

INT7

INT6

68

69

70

71

72

73

66

67

68

69

70

71

P2_4

P2_3

P2_2

P2_1

P2_0

P1_7

AN2_4

AN2_3

AN2_2

AN2_1

AN2_0

A4, [A4/D4], [A4/D3]

A3, [A3/D3], [A3/D2]

A2, [A2/D2], [A2/D1]

A1, [A1/D1], [A1/D0]

A0, [A0/D0], A0

D15

IDU

IDW

IDV

INT5

INT4

INT3

74

72

P1_6

D14

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

P1_5

P1_4

P1_3

P1_2

P1_1

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

P10_7

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

TXD6/SDA6

RXD6/SCL6

CLK6

CTS6/RTS6

AN0_7

AN0_6

AN0_5

AN0_4

AN0_3

AN0_2

AN0_1

AN0_0

AN7

D2

D1

D0

KI3

KI2

KI1

KI0

90

91

92

93

94

88

89

90

91

92

P10_6

P10_5

P10_4

P10_3

P10_2

P10_1

AN6

AN5

AN4

AN3

AN2

AN1

95

96

97

98

99

93

94

95

96

97

AVSS

P10_0

P9_7

AN0

VREF

AVCC

100 98

SIN4

ADTRG

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M16C/64A Group

1. Overview

1.6

Pin Functions

Table 1.6

Pin Functions for the 100-Pin Package (1/3)

Signal Name

Pin Name

I/O

Power Supply

Description

Power supply

input

VCC1,

VCC2, VSS

Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2)

and 0 V to the VSS pin.

I

-

This is the power supply for the A/D and D/A converters.

Connect the AVCC pin to VCC1, and connect the AVSS pin

to VSS.

Analog power

supply input

AVCC, AVSS

I

VCC1

Reset input

RESET

Driving this pin low resets the MCU.

Input pin to switch processor modes. After a reset, to start

operating in single-chip mode, connect the CNVSS pin to

VSS via a resistor. To start operating in microprocessor

mode, connect the pin to VCC1.

CNVSS

I

VCC1

Input pin to select the data bus of the external area. The data

bus is 16 bits when it is low, and 8 bits when it is high. This

pin must be fixed either high or low. Connect the BYTE pin to

VSS in single-chip mode.

External data bus

width select input

BYTE

I

VCC1

VCC2

Inputs or outputs data (D0 to D7) while accessing an

external area with a separate bus.

D0 to D7

I/O

Inputs or outputs data (D8 to D15) while accessing an

external area with a 16-bit separate bus.

D8 to D15

A0 to A19

I/O

O

VCC2

Outputs address bits A0 to A19.

Inputs or outputs data (D0 to D7) and outputs address bits

(A0 to A7) by timesharing, while accessing an external area

with an 8-bit multiplexed bus.

A0/D0 to

A7/D7

I/O

VCC2

Inputs or outputs data (D0 to D7) and outputs address bits

(A1 to A8) by timesharing, while accessing an external area

with a 16-bit multiplexed bus.

A1/D0 to

A8/D7

I/O

O

VCC2

Outputs chip-select signals CS0 to CS3 to specify an

external area.

CS0 to CS3

Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and

WRH can be switched with BHE and WR.

• WRL, WRH, and RD selected

Bus control pins

If the external data bus is 16 bits, data is written to an even

address in an external area when WRL is driven low. Data

is written to an odd address when WRH is driven low. Data

is read when RD is driven low.

WRL/WR

WRH/BHE

RD

O

VCC2

• WR, BHE, and RD selected

Data is written to an external area when WR is driven low.

Data in an external area is read when RD is driven low. An

odd address is accessed when BHE is driven low. Select

WR, BHE, and RD when using an 8-bit external data bus.

ALE

HOLD

HLDA

RDY

O

I

VCC2

Outputs an ALE signal to latch the address.

HOLD input is unavailable. Connect the HOLD pin to VCC2

via a resistor (pull-up).

O

I

In a hold state, HLDA outputs a low-level signal.

The MCU bus is placed in a wait state while the RDY pin is

driven low.

Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration

allows VCC2 to interface at a different voltage than VCC1.

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M16C/64A Group

1. Overview

Table 1.7

Pin Functions for the 100-Pin Package (2/3)

Power

Supply

Signal Name

Main clock input

Main clock output

Sub clock input

Sub clock output

Pin Name

XIN

I/O

I

Description

VCC1

I/O for the main clock oscillator. Connect a ceramic resonator

or crystal between pins XIN and XOUT. ⁽¹⁾Input an external

clock to XIN pin and leave XOUT pin open.

XOUT

XCIN

O

I

VCC1

I/O for a sub clock oscillator. Connect a crystal between XCIN

pin and XCOUT pin. ⁽¹⁾Input an external clock to XCIN pin and

leave XCOUT pin open.

XCOUT

O

BCLK output

Clock output

BCLK

CLKOUT

INT0 to INT2

INT3 to INT7

NMI

O

I

VCC2 Outputs the BCLK signal.

VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32.

VCC1

INT interrupt input

NMI interrupt input

Input for the INT interrupt.

I

VCC2

I

VCC1 Input for the NMI interrupt.

Key input interrupt

input

KI0 to KI3

I

VCC1 Input for the key input interrupt.

TA0OUT to

TA4OUT

I/O for timers A0 to A4 (TA0OUT is N-channel open drain

output).

I/O VCC1

Timer A

Timer B

TA0IN to TA4IN

ZP

I

VCC1 Input for timers A0 to A4.

VCC1 Input for Z-phase.

TB0IN to TB5IN

U, U, V, V, W, W

SD

I

VCC1 Input for timers B0 to B5.

VCC1 Output for the three-phase motor control timer.

VCC1 Forced cutoff input.

O

I

Three-phase motor

control timer

IDU, IDV, IDW

RTCOUT

I

VCC2 Input for the position data.

VCC1 Output for the real-time clock.

Real-time clock output

PWM output

O

VCC1,

PWM0, PWM1

PMC0, PMC1

O

I

PWM output.

VCC2

Remote control signal

receiver input

VCC1 Input for the remote control signal receiver.

CTS0 to CTS2,

I

VCC1

CTS5

Input pins to control data transmission.

CTS6, CTS7

I

VCC2

RTS0 to RTS2,

O

VCC1

RTS5

Output pins to control data reception.

RTS6, RTS7

VCC2

CLK0 to CLK2,

CLK5

I/O VCC1

I/O VCC2

Serial interface

UART0 to UART2,

UART5 to UART7

Transmit/receive clock I/O.

Serial data input.

CLK6, CLK7

RXD0 to RXD2,

RXD5

I

VCC1

VCC2

VCC1

VCC2

RXD6, RXD7

TXD0 to TXD2,

TXD5

O

Serial data output. ⁽²⁾

TXD6, TXD7

CLKS1

O

VCC1 Output for the transmit/receive clock multiple-pin output function.

Notes:

1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.

2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be

selected as CMOS output pins or N-channel open drain output pins.

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M16C/64A Group

1. Overview

Table 1.8

Pin Functions for the 100-Pin Package (3/3)

Power

Signal Name

Pin Name

I/O

Description

Supply

VCC1

VCC2

VCC1

SDA0 to SDA2,

SDA5

I/O

UART0 to

UART2,

UART5 to

UART7

Serial data I/O.

SDA6, SDA7

SCL0 to SCL2,

SCL5

I²C mode

Transmit/receive clock I/O.

SCL6, SCL7

CLK3, CLK4

SIN3, SIN4

I/O

I

VCC2

VCC1

Transmit/receive clock I/O.

Serial data input.

Serial

interface

SI/O3, SI/O4

SOUT3, SOUT4

O

Serial data output.

Multi-master

I²C-bus

interface

SDAMM

I/O

VCC1

Serial data I/O (N-channel open drain output).

SCLMM

CEC

I/O

VCC1

Transmit/receive clock I/O (N-channel open drain output).

CEC I/O (N-channel open drain output).

CEC I/O

Reference

voltage input

VREF

I

VCC1

VCC2

Reference voltage input for the A/D and D/A converters.

AN0 to AN7

Analog input.

AN0_0 to AN0_7

AN2_0 to AN2_7

A/D

converter

ADTRG

I

VCC1

External trigger input.

Extended analog input.

ANEX0, ANEX1

D/A

converter

DA0, DA1

O

VCC1

Output for the D/A converter.

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

8-bit CMOS I/O ports. A direction register determines whether

each pin is used as an input port or an output port. A pull-up

resistor may be enabled or disabled for input ports in 4-bit

units.

I/O

VCC2

I/O ports

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_7

P9_0 to P9_7

P10_0 to P10_7

8-bit I/O ports having equivalent functions to P0. However,

P7_0, P7_1, and P8_5 are N-channel open drain output ports.

No pull-up resistor is provided. P8_5 is an input port for

verifying the NMI pin level and shares a pin with NMI.

I/O

VCC1

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M16C/64A Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a

register bank, and there are two register banks.

b31

b15

R0H (upper bits of R0)

b8b7

b0

R2

R3

R0L (lower bits of R0)

R1L (lower bits of R1)

R1H (upper bits of R1)

Data registers ⁽¹⁾

R2

R3

A0

A1

FB

Address registers ⁽¹⁾

Frame base registers ⁽¹⁾

b19

b15

b0

INTBH

INTBL

Interrupt table register

INTBH is the 4 upper bits of the INTB register and INTBL

is the 16 lower bits.

b19

b0

PC

Program counter

b15

b0

User stack pointer

Interrupt stack pointer

Static base register

USP

ISP

SB

b15

b0

FLG

O

Flag register

b15

b8 b7

U

IPL

I

B

S

Z

D

C

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Note:

1. These registers compose a register bank. There are two register banks.

Figure 2.1

CPU Registers

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M16C/64A Group

2. Central Processing Unit (CPU)

2.1

Data Registers (R0, R1, R2, and R3)

R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can

be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers.

R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers

R2R0 and R3R1, respectively.

2.2

Address Registers (A0 and A1)

A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and

logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register that is used for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.

2.5

Program Counter (PC)

The PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register used for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register that indicates the CPU state.

2.8.1

Carry Flag (C Flag)

The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.

2.8.2

Debug Flag (D Flag)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z Flag)

The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.

2.8.4

Sign Flag (S Flag)

The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes

0.

2.8.5

Register Bank Select Flag (B Flag)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.

2.8.6

Overflow Flag (O Flag)

The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.

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M16C/64A Group

2. Central Processing Unit (CPU)

2.8.7

Interrupt Enable Flag (I Flag)

The I flag enables maskable interrupts.

Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0

when an interrupt request is accepted.

2.8.8

Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0. USP is selected when the U flag is 1.

The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software

interrupt number 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.

If a requested interrupt has higher priority than IPL, the interrupt request is enabled.

2.8.10 Reserved Areas

Only set these bits to 0. The read value is undefined.

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M16C/64A Group

3. Address Space

3.1

Address Space

The M16C/64A Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to

4 MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external

areas from bank 0 to bank 7. Figure 3.1 shows the Address Space. Areas that can be accessed vary

depending on processor mode and the status of each control bit.

Memory expansion mode

00000h

SFR

00400h

The internal RAM is allocated

from address 00400h higher.

Internal RAM

Reserved area

04000h

External area

0D000h

SFR

0D800h

External area

In 4 MB mode

0E000h

10000h

Internal ROM

(data flash)

When data flash is enabled

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

When program ROM 2

is enabled

Internal ROM

(program ROM 2)

1 MB

address space

14000h

27000h

28000h

External area

Reserved area

40000h

External area

Bank 0

512 KB × 8

BFFFFh

D0000h

FFFFFh

Reserved area

Internal ROM

(program ROM 1)

Program ROM 1 is allocated from

address FFFFFh lower.

Notes:

1. Do not access reserved areas.

2. The figure above applies under the following condition:

- The PM13 bit in the PM1 register is 0

(addresses 04000h to 0CFFFh and 80000h to CFFFFh are used as external areas)

Figure 3.1

Address Space

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M16C/64A Group

3. Address Space

3.2

Memory Map

Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to

0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.

Do not access these areas.

Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from

00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when

subroutines are called or when an interrupt request is accepted.

The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,

and program ROM 2.

The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but

can also store programs.

Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh and lower,

with the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh.

The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS

instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.

The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.

The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table

for interrupts.

Figure 3.2 shows the Memory Map.

00000h

SFR

00400h

Internal RAM

XXXXXh

Address XXXXXh

033FFh

Size

Reserved area ⁽¹⁾

12 KB

053FFh

0D000h

0D800h

20 KB

31 KB

SFR

07FFFh

External area

0E000h

10000h

Internal ROM

(data flash)

13000h

On-chip debugger

monitor area

13FF0h

13FFFh

Internal ROM

(program ROM 2)

User boot code area

14000h

External area

27000h

28000h

Reserved area ⁽¹⁾

Relocatable vector table

External area

256 bytes beginning with the

start address set in the INTB

register

Program ROM 1

Size

Address YYYYYh

E0000h

80000h

128 KB

256 KB

384 KB

512 KB

Reserved area ⁽¹⁾

C0000h

FFE00h

FFFD8h

Special page vector table

Reserved area ⁽³⁾

A0000h

80000h

YYYYYh

FFFFFh

FFFDCh

Internal ROM

(program ROM 1)

Fixed vector table

Address for ID code stored

OFS1 address

FFFFFh

Notes:

1. Do not access reserved areas.

2. The figure above applies under the following conditions:

- Memory expansion mode

- The PM10 bit in the PM1 register is 1

(addresses 0E000h to 0FFFFh are used as data flash)

- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)

- The PM13 bit in the PM1 register is 1

(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)

3. Do not change the data from FFh.

Figure 3.2

Memory Map

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M16C/64A Group

3. Address Space

3.3

Accessible Area in Each Mode

Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure

3.3 shows the Accessible Area in Each Mode.

In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.

In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.

Address space is expandable to 4 MB with the memory area expansion function.

In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is

expandable to 4 MB with the memory area expansion function. Allocate ROM to the fixed vector table

from FFFDCh to FFFFFh.

Single-Chip Mode

SFR

Memory Expansion Mode

Microprocessor Mode

SFR

00000h

00400h

00000h

00400h

00000h

SFR

00400h

Internal RAM

Reserved area

SFR

Reserved area

SFR

Reserved area

SFR

0D000h

0D800h

0D000h

0D800h

0E000h

0D800h

0E000h

Reserved area

External area

Internal ROM

(data flash)

Internal ROM

(data flash)

External area

10000h

14000h

10000h

Internal ROM

(program ROM 2)

Internal ROM

(program ROM 2)

14000h

27000h

28000h

External area

27000h

28000h

Reserved area

External area

Reserved area

80000h

Reserved area

External area

Internal ROM

(program ROM 1)

Internal ROM

(program ROM 1)

FFFFFh

Notes:

FFFFFh

1. Do not access reserved areas.

2. The figure above applies under the following conditions:

Single-chip mode and memory expansion mode

- The PM10 bit in the PM1 register is 1

(addresses 0E000h to 0FFFFh are used as data flash)

- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)

- The PM13 bit in the PM1 register is 1

(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)

Microprocessor mode

- The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area)

- The PRG2C0 bit is 1 (program ROM 2 disabled)

Figure 3.3

Accessible Area in Each Mode

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M16C/64A Group

4. Special Function Registers (SFRs)

4.1

SFRs

An SFR is a control register for a peripheral function.

Table 4.1

SFR Information (1) ⁽¹⁾

Address

0000h

0001h

0002h

0003h

Register

Symbol

Reset Value

0000 0000b

(CNVSS pin is low)

0000 0011b

0004h

Processor Mode Register 0

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register

PM0

(CNVSS pin is high)⁽²⁾

0005h

0006h

0007h

0008h

0009h

PM1

CM0

CM1

CSR

0000 1000b

0100 1000b

0010 0000b

01h

000Ah Protect Register

000Bh Data Bank Register

PRCR

DBR

00h

0X00 0010b ⁽³⁾

000Ch Oscillation Stop Detection Register

CM2

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

Program 2 Area Control Register

Peripheral Clock Select Register

PRG2C

PCLKR

XXXX XX00b

0000 0011b

Clock Prescaler Reset Flag

CPSRF

0XXX XXXXb

XX00 001Xb

0018h

Reset Source Determine Register

Voltage Detector 2 Flag Register

RSTFR

(hardware reset) ⁽⁴⁾

(5)

0019h

VCR1

VCR2

CSE

0000 1000b

(5)

001Ah Voltage Detector Operation Enable Register

001Bh Chip Select Expansion Control Register

001Ch PLL Control Register 0

001Dh

00h

PLC0

0X01 X010b

001Eh Processor Mode Register 2

001Fh

PM2

XX00 0X01b

X: Undefined

Notes:

1.

The blank areas are reserved. No access is allowed.

2.

Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset

do not affect the following bits: bits PM01 and PM00 in the PM0 register.

3.

4.

5.

Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.

The state of bits in the RSTFR register depends on the reset type.

This is the reset value after hardware reset. Refer to the explanation of each register for details.

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M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.2

SFR Information (2) ⁽¹⁾

Register

Address

0020h

0021h

0022h

0023h

0024h

0025h

Symbol

Reset Value

0026h

0027h

0028h

0029h

Voltage Monitor Function Select Register

Voltage Detector 1 Level Select Register

VWCE

VD1LS

00h

0000 1010b⁽²⁾

1000 XX10b ⁽²⁾

1000 1010b⁽²⁾

002Ah Voltage Monitor 0 Control Register

002Bh Voltage Monitor 1 Control Register

VW0C

VW1C

VW2C

(2)

002Ch Voltage Monitor 2 Control Register

1000 0X10b

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

X: Undefined

Notes:

1.

2.

The blank areas are reserved. No access is allowed.

This is the reset value after hardware reset. Refer to the explanation of each register for details.

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M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.3

SFR Information (3) ⁽¹⁾

Register

Address

0040h

Symbol

Reset Value

0041h

0042h

0043h

INT7 Interrupt Control Register

INT6 Interrupt Control Register

INT7IC

INT6IC

XX00 X000b

0044h

0045h

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

INT3IC

TB5IC

XX00 X000b

XXXX X000b

Timer B4 Interrupt Control Register

UART1 Bus Collision Detection Interrupt Control Register

Timer B3 Interrupt Control Register

UART0 Bus Collision Detection Interrupt Control Register

SI/O4 Interrupt Control Register

INT5 Interrupt Control Register

TB4IC

U1BCNIC

TB3IC

U0BCNIC

S4IC

INT5IC

S3IC

INT4IC

0046h

0047h

0048h

0049h

XXXX X000b

XX00 X000b

SI/O3 Interrupt Control Register

INT4 Interrupt Control Register

004Ah UART2 Bus Collision Detection Interrupt Control Register

BCNIC

DM0IC

DM1IC

KUPIC

ADIC

XXXX X000b

004Bh DMA0 Interrupt Control Register

004Ch DMA1 Interrupt Control Register

004Dh Key Input Interrupt Control Register

004Eh A/D Conversion Interrupt Control Register

004Fh UART2 Transmit Interrupt Control Register

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer A3 Interrupt Control Register

Timer A4 Interrupt Control Register

005Ah Timer B0 Interrupt Control Register

005Bh Timer B1 Interrupt Control Register

005Ch Timer B2 Interrupt Control Register

005Dh INT0 Interrupt Control Register

005Eh INT1 Interrupt Control Register

005Fh INT2 Interrupt Control Register

INT0IC

INT1IC

INT2IC

XX00 X000b

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

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M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.4

SFR Information (4) ⁽¹⁾

Address

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

Register

Symbol

Reset Value

0069h

006Ah

DMA2 Interrupt Control Register

DMA3 Interrupt Control Register

DM2IC

DM3IC

XXXX X000b

UART5 Bus Collision Detection Interrupt Control Register

CEC1 Interrupt Control Register

UART5 Transmit Interrupt Control Register

CEC2 Interrupt Control Register

U5BCNIC

CEC1IC

S5TIC

CEC2IC

S5RIC

006Bh

XXXX X000b

006Ch

006Dh

XXXX X000b

UART5 Receive Interrupt Control Register

U6BCNIC

UART6 Bus Collision Detection Interrupt Control Register

Real-Time Clock Periodic Interrupt Control Register

006Eh

XXXX X000b

RTCTIC

S6TIC

UART6 Transmit Interrupt Control Register

006Fh

0070h

0071h

XXXX X000b

Real-Time Clock Compare Interrupt Control Register

UART6 Receive Interrupt Control Register

UART7 Bus Collision Detection Interrupt Control Register

Remote Control Signal Receiver 0 Interrupt Control Register

UART7 Transmit Interrupt Control Register

RTCCIC

S6RIC

U7BCNIC

PMC0IC

S7TIC

0072h

XXXX X000b

Remote Control Signal Receiver 1 Interrupt Control Register

UART7 Receive Interrupt Control Register

PMC1IC

S7RIC

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

XXXX X000b

I2C-bus Interface Interrupt Control Register

SCL/SDA Interrupt Control Register

IICIC

SCLDAIC

007Dh

007Eh

007Fh

0080h to

017Fh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

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M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.5

SFR Information (5) ⁽¹⁾

Address

0180h

Register

Symbol

SAR0

Reset Value

XXh

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

DMA0 Source Pointer

XXh

0Xh

XXh

0Xh

DMA0 Destination Pointer

DMA0 Transfer Counter

DAR0

TCR0

XXh

018Ch DMA0 Control Register

DM0CON

0000 0X00b

018Dh

018Eh

018Fh

0190h

XXh

0Xh

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

DMA1 Source Pointer

SAR1

XXh

0Xh

DMA1 Destination Pointer

DMA1 Transfer Counter

DAR1

TCR1

XXh

019Ch DMA1 Control Register

DM1CON

0000 0X00b

019Dh

019Eh

019Fh

01A0h

XXh

0Xh

01A1h DMA2 Source Pointer

01A2h

SAR2

01A3h

01A4h

XXh

0Xh

01A5h DMA2 Destination Pointer

01A6h

01A7h

DAR2

TCR2

01A8h

XXh

DMA2 Transfer Counter

01A9h

01AAh

01ABh

01ACh DMA2 Control Register

DM2CON

0000 0X00b

01ADh

01AEh

01AFh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 24 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.6

SFR Information (6) ⁽¹⁾

Register

Address

01B0h

Symbol

SAR3

Reset Value

XXh

01B1h DMA3 Source Pointer

XXh

01B2h

01B3h

01B4h

0Xh

XXh

0Xh

01B5h DMA3 Destination Pointer

01B6h

01B7h

DAR3

TCR3

01B8h

XXh

DMA3 Transfer Counter

01B9h

01BAh

01BBh

01BCh DMA3 Control Register

DM3CON

0000 0X00b

01BDh

01BEh

01BFh

01C0h

XXh

Timer B0-1 Register

01C1h

TB01

TB11

01C2h

Timer B1-1 Register

01C3h

01C4h

Timer B2-1 Register

01C5h

TB21

Pulse Period/Pulse Width Measurement Mode Function Select

Register 1

01C6h

01C7h

PPWFS1

XXXX X000b

01C8h Timer B Count Source Select Register 0

01C9h Timer B Count Source Select Register 1

TBCS0

TBCS1

00h

X0h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h Timer A Count Source Select Register 0

01D1h Timer A Count Source Select Register 1

01D2h Timer A Count Source Select Register 2

TACS0

TACS1

TACS2

00h

X0h

01D3h

01D4h 16-bit Pulse Width Modulation Mode Function Select Register

01D5h Timer A Waveform Output Function Select Register

PWMFS

TAPOFS

0XX0 X00Xb

XXX0 0000b

01D6h

01D7h

01D8h Timer A Output Waveform Change Enable Register

01D9h

01DAh Three-Phase Protect Control Register

TAOW

TPRC

XXX0 X00Xb

00h

01DBh

01DCh

01DDh

01DEh

01DFh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 25 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.7

SFR Information (7) ⁽¹⁾

Register

Address

01E0h

Symbol

TB31

Reset Value

XXh

Timer B3-1 Register

Timer B4-1 Register

Timer B5-1 Register

01E1h

01E2h

01E3h

01E4h

01E5h

XXh

TB41

TB51

Pulse Period/Pulse Width Measurement Mode Function Select Reg-

ister 2

01E6h

01E7h

PPWFS2

XXXX X000b

01E8h Timer B Count Source Select Register 2

01E9h Timer B Count Source Select Register 3

TBCS2

TBCS3

00h

X0h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h PMC0 Function Select Register 0

01F1h PMC0 Function Select Register 1

01F2h PMC0 Function Select Register 2

01F3h PMC0 Function Select Register 3

01F4h PMC0 Status Register

01F5h PMC0 Interrupt Source Select Register

01F6h PMC0 Compare Control Register

01F7h PMC0 Compare Data Register

01F8h PMC1 Function Select Register 0

01F9h PMC1 Function Select Register 1

01FAh PMC1 Function Select Register 2

01FBh PMC1 Function Select Register 3

01FCh PMC1 Status Register

01FDh PMC1 Interrupt Source Select Register

01FEh

PMC0CON0

PMC0CON1

PMC0CON2

PMC0CON3

PMC0STS

PMC0INT

PMC0CPC

PMC0CPD

PMC1CON0

PMC1CON1

PMC1CON2

PMC1CON3

PMC1STS

PMC1INT

00h

00XX 0000b

0000 00X0b

00h

XXX0 X000b

00h

XXX0 X000b

XXXX 0X00b

0000 00X0b

00h

X000 X00Xb

01FFh

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

Interrupt Source Select Register 3

Interrupt Source Select Register 2

Interrupt Source Select Register

IFSR3A

IFSR2A

IFSR

00h

020Eh Address Match Interrupt Enable Register

020Fh Address Match Interrupt Enable Register 2

AIER

AIER2

XXXX XX00b

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 26 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.8

SFR Information (8) ⁽¹⁾

Register

Address

0210h

Symbol

Reset Value

00h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

Address Match Interrupt Register 0

Address Match Interrupt Register 1

Address Match Interrupt Register 2

RMAD0

RMAD1

RMAD2

RMAD3

00h

X0h

00h

X0h

00h

X0h

00h

X0h

021Dh Address Match Interrupt Register 3

021Eh

021Fh

0000 0001b

(Other than user boot mode)

0010 0001b

0220h

Flash Memory Control Register 0

FMR0

(User boot mode)

00X0 XX0Xb

XXXX 0000b

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

Flash Memory Control Register 1

Flash Memory Control Register 2

FMR1

FMR2

Flash Memory Control Register 6

FMR6

XX0X XX00b

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 27 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.9

SFR Information (9) ⁽¹⁾

Register

Address

0240h

0241h

0242h

0243h

Symbol

Reset Value

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

U0SMR4

U0SMR3

U0SMR2

U0SMR

U0MR

00h

000X 0X0Xb

X000 0000b

00h

U0BRG

XXh

UART0 Transmit Buffer Register

U0TB

024Ch UART0 Transmit/Receive Control Register 0

024Dh UART0 Transmit/Receive Control Register 1

U0C0

U0C1

0000 1000b

00XX 0010b

XXh

024Eh

UART0 Receive Buffer Register

024Fh

U0RB

XXh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

UART Transmit/Receive Control Register 2

UCON

X000 0000b

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

U1SMR4

U1SMR3

U1SMR2

U1SMR

U1MR

00h

000X 0X0Xb

X000 0000b

00h

U1BRG

XXh

UART1 Transmit Buffer Register

U1TB

025Ch UART1 Transmit/Receive Control Register 0

025Dh UART1 Transmit/Receive Control Register 1

U1C0

U1C1

0000 1000b

00XX 0010b

XXh

025Eh

UART1 Receive Buffer Register

025Fh

U1RB

XXh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

00h

000X 0X0Xb

X000 0000b

00h

U2BRG

XXh

UART2 Transmit Buffer Register

U2TB

026Ch UART2 Transmit/Receive Control Register 0

026Dh UART2 Transmit/Receive Control Register 1

U2C0

U2C1

0000 1000b

0000 0010b

XXh

026Eh

UART2 Receive Buffer Register

026Fh

U2RB

XXh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 28 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.10

SFR Information (10) ⁽¹⁾

Register

Address

Symbol

S3TRR

Reset Value

XXh

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

SI/O3 Transmit/Receive Register

SI/O3 Control Register

SI/O3 Bit Rate Register

SI/O4 Transmit/Receive Register

S3C

S3BRG

S4TRR

0100 0000b

XXh

SI/O4 Control Register

SI/O4 Bit Rate Register

SI/O3, 4 Control Register 2

S4C

S4BRG

S34C2

0100 0000b

XXh

00XX X0X0b

UART5 Special Mode Register 4

UART5 Special Mode Register 3

UART5 Special Mode Register 2

UART5 Special Mode Register

UART5 Transmit/Receive Mode Register

UART5 Bit Rate Register

U5SMR4

U5SMR3

U5SMR2

U5SMR

U5MR

00h

000X 0X0Xb

X000 0000b

00h

U5BRG

XXh

UART5 Transmit Buffer Register

U5TB

028Ch UART5 Transmit/Receive Control Register 0

028Dh UART5 Transmit/Receive Control Register 1

U5C0

U5C1

0000 1000b

0000 0010b

XXh

028Eh

UART5 Receive Buffer Register

028Fh

U5RB

XXh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h

029Ah

029Bh

UART6 Special Mode Register 4

UART6 Special Mode Register 3

UART6 Special Mode Register 2

UART6 Special Mode Register

UART6 Transmit/Receive Mode Register

UART6 Bit Rate Register

U6SMR4

U6SMR3

U6SMR2

U6SMR

U6MR

00h

000X 0X0Xb

X000 0000b

00h

U6BRG

XXh

UART6 Transmit Buffer Register

U6TB

029Ch UART6 Transmit/Receive Control Register 0

029Dh UART6 Transmit/Receive Control Register 1

U6C0

U6C1

0000 1000b

0000 0010b

XXh

029Eh

UART6 Receive Buffer Register

029Fh

U6RB

XXh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 29 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.11

SFR Information (11) ⁽¹⁾

Register

Address

02A0h

02A1h

02A2h

02A3h

Symbol

Reset Value

02A4h UART7 Special Mode Register 4

02A5h UART7 Special Mode Register 3

02A6h UART7 Special Mode Register 2

02A7h UART7 Special Mode Register

02A8h UART7 Transmit/Receive Mode Register

02A9h UART7 Bit Rate Register

U7SMR4

U7SMR3

U7SMR2

U7SMR

U7MR

00h

000X 0X0Xb

X000 0000b

00h

U7BRG

XXh

02AAh

XXh

UART7 Transmit Buffer Register

02ABh

U7TB

02ACh UART7 Transmit/Receive Control Register 0

02ADh UART7 Transmit/Receive Control Register 1

U7C0

U7C1

0000 1000b

0000 0010b

XXh

02AEh

UART7 Receive Buffer Register

02AFh

U7RB

S00

XXh

02B0h I2C0 Data Shift Register

02B1h

02B2h I2C0 Address Register 0

02B3h I2C0 Control Register 0

02B4h I2C0 Clock Control Register

02B5h I2C0 Start/Stop Condition Control Register

02B6h I2C0 Control Register 1

02B7h I2C0 Control Register 2

02B8h I2C0 Status Register 0

02B9h I2C0 Status Register 1

02BAh I2C0 Address Register 1

02BBh I2C0 Address Register 2

02BCh

S0D0

S1D0

S20

S2D0

S3D0

S4D0

S10

S11

S0D1

S0D2

0000 000Xb

00h

0001 1010b

0011 0000b

00h

0001 000Xb

XXXX X000b

0000 000Xb

02BDh

02BEh

02BFh

02C0h to

02FFh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 30 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.12

SFR Information (12) ⁽¹⁾

Register

Address

Symbol

TBSR

Reset Value

000X XXXXb

0300h

0301h

0302h

0303h

0304h

0305h

0306h

0307h

0308h

0309h

Timer B3/B4/B5 Count Start Flag

XXh

00h

Timer A1-1 Register

Timer A2-1 Register

Timer A4-1 Register

TA11

TA21

TA41

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

INVC0

INVC1

IDB0

IDB1

DTT

030Ah Three-Phase Output Buffer Register 0

030Bh Three-Phase Output Buffer Register 1

030Ch Dead Time Timer

XX11 1111b

XXh

030Dh Timer B2 Interrupt Generation Frequency Set Counter

030Eh Position-Data-Retain Function Control Register

030Fh

ICTB2

PDRF

XXh

XXXX 0000b

0310h

XXh

Timer B3 Register

0311h

TB3

TB4

TB5

0312h

Timer B4 Register

0313h

0314h

Timer B5 Register

0315h

0316h

0317h

0318h

0319h

031Ah

Port Function Control Register

PFCR

0011 1111b

031Bh Timer B3 Mode Register

031Ch Timer B4 Mode Register

031Dh Timer B5 Mode Register

031Eh

TB3MR

TB4MR

TB5MR

00XX 0000b

031Fh

0320h

0321h

0322h

0323h

0324h

0325h

0326h

0327h

0328h

0329h

032Ah

032Bh

032Ch

032Dh

032Eh

032Fh

Count Start Flag

TABSR

00h

One-Shot Start Flag

Trigger Select Register

Increment/Decrement Flag

ONSF

TRGSR

UDF

00h

XXh

Timer A0 Register

Timer A1 Register

Timer A2 Register

Timer A3 Register

Timer A4 Register

TA0

TA1

TA2

TA3

TA4

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 31 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.13

SFR Information (13) ⁽¹⁾

Register

Address

0330h

Symbol

TB0

Reset Value

XXh

Timer B0 Register

Timer B1 Register

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

XXh

TB1

TB2

Timer B2 Register

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

00h

033Ah Timer A4 Mode Register

033Bh Timer B0 Mode Register

033Ch Timer B1 Mode Register

033Dh Timer B2 Mode Register

033Eh Timer B2 Special Mode Register

033Fh

00h

00XX 0000b

X000 0000b

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

Real-Time Clock Second Data Register

Real-Time Clock Minute Data Register

Real-Time Clock Hour Data Register

Real-Time Clock Day Data Register

Real-Time Clock Control Register 1

Real-Time Clock Control Register 2

Real-Time Clock Count Source Select Register

RTCSEC

RTCMIN

RTCHR

RTCWK

RTCCR1

RTCCR2

RTCCSR

00h

X000 0000b

XX00 0000b

XXXX X000b

0000 X00Xb

X000 0000b

XXX0 0000b

Real-Time Clock Second Compare Data Register

Real-Time Clock Minute Compare Data Register

RTCCSEC

RTCCMIN

RTCCHR

X000 0000b

034Ah Real-Time Clock Hour Compare Data Register

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

CEC Function Control Register 1

CEC Function Control Register 2

CEC Function Control Register 3

CEC Function Control Register 4

CEC Flag Register

CEC Interrupt Source Select Register

CEC Transmit Buffer Register 1

CEC Transmit Buffer Register 2

CEC Receive Buffer Register 1

CEC Receive Buffer Register 2

CECC1

CECC2

CECC3

CECC4

CECFLG

CISEL

CCTB1

CCTB2

CCRB1

CCRB2

CRADRI1

CRADRI2

XXXX X000b

00h

XXXX 0000b

00h

XXXX XX00b

00h

XXXX X000b

00h

035Ah CEC Receive Follower Address Set Register 1

035Bh CEC Receive Follower Address Set Register 2

00h

035Ch

035Dh

035Eh

035Fh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 32 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.14

SFR Information (14) ⁽¹⁾

Register

Address

Symbol

PUR0

PUR1

Reset Value

00h

0000 0000b⁽²⁾

0360h

0361h

Pull-Up Control Register 0

Pull-Up Control Register 1

0000 0010b

00h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

Pull-Up Control Register 2

PUR2

Port Control Register

PCR

0000 0XX0b

XXXX X000b

NMI/SD Digital Filter Register

NMIDF

PWM Control Register 0

PWMCON0

00h

PWM0 Prescaler

PWM0 Register

PWM1 Prescaler

PWM1 Register

PWMPRE0

PWMREG0

PWMPRE1

PWMREG1

PWMCON1

00h

PWM Control Register 1

037Ch Count Source Protection Mode Register

037Dh Watchdog Timer Refresh Register

037Eh Watchdog Timer Start Register

037Fh Watchdog Timer Control Register

0380h to

CSPR

WDTR

WDTS

WDC

00h ⁽³⁾

XXh

00XX XXXXb

038Fh

X: Undefined

Notes:

1.

2.

The blank areas are reserved. No access is allowed.

Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows:

- 00000000b when a low-level signal is input to the CNVSS pin

- 00000010b when a high-level signal is input to the CNVSS pin

Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop

detect reset are as follows:

- 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode).

- 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b

(microprocessor mode).

3.

When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 33 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.15

SFR Information (15) ⁽¹⁾

Register

Address

Symbol

DM2SL

Reset Value

00h

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

DMA2 Source Select Register

DMA3 Source Select Register

DM3SL

00h

DMA0 Source Select Register

DM0SL

DM1SL

00h

039Ah DMA1 Source Select Register

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h Open-Circuit Detection Assist Function Register

AINRST

XX00 XXXXb

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

XXXX XXXXb

00XX XXXXb

0XXX XXX0b

SFR Snoop Address Register

03B5h

CRCSAR

CRCMR

03B6h CRC Mode Register

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

XXh

CRC Data Register

03BDh

CRCD

CRCIN

03BEh CRC Input Register

03BFh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 34 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.16

SFR Information (16) ⁽¹⁾

Register

Address

03C0h

Symbol

AD0

Reset Value

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

A/D Register 0

A/D Register 1

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

03D4h A/D Control Register 2

03D5h

ADCON2

0000 X00Xb

03D6h A/D Control Register 0

03D7h A/D Control Register 1

03D8h D/A0 Register

03D9h

ADCON0

ADCON1

DA0

0000 0XXXb

0000 X000b

00h

03DAh D/A1 Register

03DBh

03DCh D/A Control Register

03DDh

DA1

00h

DACON

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

P0

P1

PD0

PD1

P2

XXh

00h

XXh

00h

XXh

00h

XXh

00h

Port P3 Register

P3

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

PD2

PD3

P4

Port P5 Register

P5

03EAh Port P4 Direction Register

03EBh Port P5 Direction Register

03ECh Port P6 Register

03EDh Port P7 Register

03EEh Port P6 Direction Register

03EFh Port P7 Direction Register

PD4

PD5

P6

P7

PD6

PD7

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

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Page 35 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.17

SFR Information (17) ⁽¹⁾

Register

Address

Symbol

P8

P9

PD8

PD9

P10

Reset Value

XXh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

Port P8 Register

Port P9 Register

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

XXh

00h

XXh

Port P10 Direction Register

PD10

00h

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 36 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.18

SFR Information (18) ⁽¹⁾

Register

Address

D080h

D081h

D082h

D083h

Symbol

Reset Value

0000 0000b

XXXX X000b

0000 0000b

XXXX X000b

00h

PMC0 Header Pattern Set Register (Min)

PMC0 Header Pattern Set Register (Max)

PMC0HDPMIN

PMC0HDPMAX

D084h PMC0 Data 0 Pattern Set Register (Min)

D085h PMC0 Data 0 Pattern Set Register (Max)

D086h PMC0 Data 1 Pattern Set Register (Min)

D087h PMC0 Data 1 Pattern Set Register (Max)

PMC0D0PMIN

PMC0D0PMAX

PMC0D1PMIN

PMC0D1PMAX

00h

D088h

00h

PMC0 Measurements Register

D089h

PMC0TIM

D08Ah

D08Bh

D08Ch PMC0 Receive Data Store Register 0

D08Dh PMC0 Receive Data Store Register 1

D08Eh PMC0 Receive Data Store Register 2

D08Fh PMC0 Receive Data Store Register 3

D090h PMC0 Receive Data Store Register 4

D091h PMC0 Receive Data Store Register 5

D092h PMC0 Receive Bit Count Register

D093h

PMC0DAT0

PMC0DAT1

PMC0DAT2

PMC0DAT3

PMC0DAT4

PMC0DAT5

PMC0RBIT

00h

XX00 0000b

D094h

0000 0000b

XXXX X000b

0000 0000b

XXXX X000b

00h

PMC1 Header Pattern Set Register (Min)

D095h

PMC1HDPMIN

PMC1HDPMAX

D096h

PMC1 Header Pattern Set Register (Max)

D097h

D098h PMC1 Data 0 Pattern Set Register (Min)

D099h PMC1 Data 0 Pattern Set Register (Max)

D09Ah PMC1 Data 1 Pattern Set Register (Min)

D09Bh PMC1 Data 1 Pattern Set Register (Max)

PMC1D0PMIN

PMC1D0PMAX

PMC1D1PMIN

PMC1D1PMAX

00h

D09Ch

00h

PMC1 Measurements Register

D09Dh

PMC1TIM

D09Eh

D09Fh

X: Undefined

Note:

1.

The blank areas are reserved. No access is allowed.

R01DS0032EJ0200 Rev.2.00

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Page 37 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

4.2

4.2.1

Notes on SFRs

Register Settings

Table 4.19 lists Registers with Write-Only Bits and registers whose function differs between reading and

writing. Set these registers with immediate values. Do not use read-modify-write instructions. When

establishing the next value by altering the existing value, write the existing value to the RAM as well as

to the register. Transfer the next value to the register after making changes in the RAM.

Read-modify-write instructions can be used when writing to the no register bits.

Table 4.19

Registers with Write-Only Bits

Address

Register

Symbol

U0BRG

U0TB

U1BRG

U1TB

U2BRG

U2TB

S3BRG

S4BRG

U5BRG

U5TB

U6BRG

U6TB

U7BRG

U7TB

S3D0

S10

0249h

024Bh to 024Ah

0259h

UART0 Bit Rate Register

UART0 Transmit Buffer Register

UART1 Bit Rate Register

UART1 Transmit Buffer Register

UART2 Bit Rate Register

UART2 Transmit Buffer Register

SI/O3 Bit Rate Register

025Bh to 025Ah

0269h

026Bh to 026Ah

0273h

0277h

SI/O4 Bit Rate Register

0289h

UART5 Bit Rate Register

UART5 Transmit Buffer Register

UART6 Bit Rate Register

UART6 Transmit Buffer Register

UART7 Bit Rate Register

UART7 Transmit Buffer Register

I2C0 Control Register 1

028Bh to 028Ah

0299h

029Bh to 029Ah

02A9h

02ABh to 02AAh

02B6h

02B8h

I2C0 Status Register 0

0303h to 0302h

0305h to 0304h

0307h to 0306h

030Ah

Timer A1-1 Register

TA11

Timer A2-1 Register

TA21

Timer A4-1 Register

TA41

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

IDB0

030Bh

IDB1

030Ch

DTT

030Dh

Timer B2 Interrupt Generation Frequency Set Counter

Timer A0 Register

ICTB2

TA0

0327h to 0326h

0329h to 0328h

032Bh to 032Ah

032Dh to 032Ch

032Fh to 032Eh

037Dh

Timer A1 Register

TA1

Timer A2 Register

TA2

Timer A3 Register

TA3

Timer A4 Register

TA4

Watchdog Timer Refresh Register

Watchdog Timer Start Register

WDTR

WDTS

037Eh

R01DS0032EJ0200 Rev.2.00

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Page 38 of 88

M16C/64A Group

4. Special Function Registers (SFRs)

Table 4.20

Read-Modify-Write Instructions

Function

Mnemonic

Transfer

MOVDir

Bit processing

Shifting

BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS

ROLC, RORC, ROT, SHA, and SHL

ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,

SBB, and SUB

Arithmetic operation

Decimal operation

Logical operation

Jump

DADC, DADD, DSBB, and DSUB

AND, NOT, OR, and XOR

ADJNZ, SBJNZ

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 39 of 88

M16C/64A Group

5. Electrical Characteristics

5.1

5.1.1

Electrical Characteristics (Common to 3 V and 5 V)

Absolute Maximum Rating

Table 5.1

Absolute Maximum Ratings

Symbol

V_CC1

Parameter

Condition

Rated Value

Unit

V

Supply voltage

V_CC1= AV_CC

−0.3 to 6.5

−0.3 to V_CC1+ 0.1 ⁽¹⁾

−0.3 to 6.5

V_CC2

AV_CC

V_REF

V_I

Supply voltage

V_CC1= AV_CC

V

Analog supply voltage

Analog reference voltage

−0.3 to V_CC1+ 0.1 ⁽¹⁾

−0.3 to V_CC1+ 0.3 ⁽¹⁾

Input voltage RESET, CNVSS, BYTE,

P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN

−0.3 to V_CC2+ 0.3 ⁽¹⁾

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7

V

P7_0, P7_1, P8_5

−0.3 to 6.5

−0.3 to V_CC1+ 0.3 ⁽¹⁾

V

V_O

Output voltage P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

XOUT

−0.3 to V_CC2+ 0.3 ⁽¹⁾

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7

V

P7_0, P7_1, P8_5

Power consumption

−0.3 to 6.5

V

P_d

−

40°C < T

≤

85

°C

300

mW

opr

T_opr

Operating

temperature

When the MCU is operating

Flash program erase

−20 to 85/−40 to 85 °C

0 to 60

Program area

Data area

−20 to 85/−40 to 85

T_stg

Storage temperature

−65 to 150

°C

Note:

1. Maximum value is 6.5 V.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 40 of 88

M16C/64A Group

5. Electrical Characteristics

5.1.2

Recommended Operating Conditions

Table 5.2

Recommended Operating Conditions (1/3)

V_CC1= V_CC2= 2.7 to 5.5 V at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified.

Standard

Typ.

Symbol

Parameter

Unit

Min.

2.7

Max.

5.5

CEC function is not used

CEC function is used

V_CC1

,

Supply voltage (V_CC1≥ V_CC2

)

5.0

V

V_CC2

2.7

3.63

AV_CC

V_SS

Analog supply voltage

Supply voltage

V_CC1

0

V

AV_SS

V_IH

Analog supply voltage

High input

voltage

0.8V_CC2

V_CC2

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(in single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

0.5V_CC2

0.8V_CC1

V_CC2

V_CC1

6.5

V

(data input in memory expansion and microprocessor

modes

)

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS, BYTE

P7_0, P7_1, P8_5

0.8V_CC1

V

CEC

0.7V_CC1

V_IL

Low input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7

0

0.2V_CC2

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(in single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

0

0.16V

V

CC2

(data input in memory expansion and microprocessor mode)

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7

0.2V_CC1

XIN, RESET, CNVSS, BYTE

CEC

0.26V_CC1

-40.0

V

I_OH(sum)High peak

output

mA

Sum of I_OH(peak)at P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7

current

Sum of I_OH(peak)at P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7

-40.0

−10.0

mA

Sum of I_OH(peak)at P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4

Sum of I_OH(peak)at P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7

I_OH(peak)High peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

output

P4_0 to P4_7, P5_0 to P5_7,

current

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

I_OH(avg)High

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

−5.0

mA

average

output

current ⁽¹⁾

Note:

1. The average output current is the mean value within 100 ms.

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M16C/64A Group

5. Electrical Characteristics

Table 5.3

Recommended Operating Conditions (2/3)

V_CC1= V_CC2= 2.7 to 5.5 V at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified.

Standard

Typ.

Symbol

Parameter

Unit

mA

Min.

Max.

80.0

I_OL(sum)Low peak Sum of I_OL(peak)at P0_0 to P0_7, P1_0 to P1_7,

output

current

P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7

I_OL(peak)Low peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

10.0

5.0

20

mA

output

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

I_OL(avg)Low

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

average

output

current ⁽¹⁾

f_(XIN)

Main clock input

V_CC1= 2.7 V to 5.5 V

2

MHz

oscillation frequency

f_(XCIN)

f_(PLL)

Sub clock oscillation frequency

32.768

50

25

kHz

PLL clock oscillation

frequency

V_CC1= 2.7 V to 5.5 V

10

2

MHz

f_(BCLK)

CPU operation clock

25

2

MHz

ms

t_SU(PLL)PLL frequency

synthesizer

V_CC1= 5.0 V

V_CC1= 3.0 V

3

ms

stabilization wait time

Note:

1. The average output current is the mean value within 100 ms.

(1)

Table 5.4

Recommended Operating Conditions (3/3)

V_CC1= 2.7 to 5.5 V, V_SS= 0 V, and T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified.

The ripple voltage must not exceed V_r(VCC1)and/or dV_r(VCC1)/dt.

Standard

Symbol

V_r(VCC1)

Parameter

Unit

Min.

Typ.

Max.

Allowable ripple voltage

0.5

0.3

Vp-p

V/ms

V_CC1= 5.0 V

V_CC1= 3.0 V

V_CC1= 5.0 V

V_CC1= 3.0 V

dV_r(VCC1)/dt Ripple voltage falling gradient

Note:

1. The device is operationally guaranteed under these operating conditions.

V_CC1

V_{r( V}

)

CC1

Figure 5.1

Ripple Waveform

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 42 of 88

M16C/64A Group

5. Electrical Characteristics

5.1.3

A/D Conversion Characteristics

(1)

Table 5.5

A/D Conversion Characteristics (1/2)

V_CC1= AV_CC= 3.0 to 5.5 V ≥ V_CC2≥ V_REF, V_SS= AV_SS= 0 V at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise

specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

10

-

Resolution

Integral non-linearity error 10bit

AV_CC= V_CC1≥ V_CC2≥ V_REF

Bits

I_NL

V_CC1= AN0 to AN7 input,

±3

LSB

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

5.0 V

V_CC1

3.3 V

=

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

LSB

V_CC1

3.0 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

-

Absolute accuracy

10bit

V_CC1

5.0 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

V_CC1

3.3 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

V_CC1= AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

3.0 V

Notes:

1. Use when AV_CC= V_CC1

.

2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and

connect them to V_SS. See Figure 5.2 “A/D Accuracy Measure Circuit”.

AN

Analog input

AN: One of the analog input pin

P0 to P10: I/O pins other than AN

P0 to P10

Figure 5.2

A/D Accuracy Measure Circuit

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Feb 07, 2011

Page 43 of 88

M16C/64A Group

5. Electrical Characteristics

(1)

Table 5.6

A/D Conversion Characteristics (2/2)

V_CC1= AV_CC= 3.0 to 5.5 V≥ V_CC2≥ V_REF, V_SS= AV_SS= 0 V at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise

specified.

Standard

Symbol

φAD

Parameter

Measuring Condition

Unit

Min.

2

Typ.

Max.

25

A/D operating clock AN0 to AN7 input, 4.0 V ≤ V_CC1≤ 5.5 V

MHz

kΩ

frequency

ANEX0 to ANEX1

input

3.2 V ≤ V_CC1≤ 4.0 V

3.0 V ≤ V_CC1≤ 3.2 V

4.0 V ≤ V_CC2≤ 5.5 V

3.2 V ≤ V_CC2≤ 4.0 V

3.0 V ≤ V_CC2≤ 3.2 V

2

16

2

10

2

25

AN0_0 to AN0_7

input, AN2_0 to

AN2_7 input

2

16

2

10

-

Tolerance level impedance

Differential non-linearity error

3

(4)

D_NL

±1

±3

LSB

-

Offset error

LSB

μs

-

Gain error

t_CONV

t_SAMP

V_REF

V_IA

10-bit conversion time

Sampling time

Reference voltage

V_CC1= 5 V, φAD = 25 MHz

1.60

0.60

3.0

0

μs

V_CC1

V_REF

V

Analog input voltage ^{(2), (3)}

V

Notes:

1. Use when AV_CC= V_CC1

.

2. When V_CC1≥ V_CC2, set as below:

Analog input voltage (AN0 to AN7, ANEX0, and ANEX1) ≤ V_CC1

Analog input voltage (AN0_0 to AN0_7 and AN2_0 to AN2_7) ≤ V_CC2

.

3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.

4. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and

connect them to V_SS. See Figure 5.2 “A/D Accuracy Measure Circuit”.

5.1.4

D/A Conversion Characteristics

Table 5.7

D/A Conversion Characteristics

V_CC1= AV_CC= V_REF= 3.0 to 5.5 V, V_SS= AV_SS= 0 V at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

8

-

Resolution

Bits

LSB

μs

Absolute Accuracy

Setup Time

2.5

3

t_SU

R_O

Output Resistance

5

6

8.2

1.5

kΩ

I_VREF

Reference Power Supply Input Current

See Notes 1 and 2

mA

Notes:

1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.

2. The current consumption of the A/D converter is not included. Also, the I_VREFof the D/A converter will flow even

if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 44 of 88

M16C/64A Group

5. Electrical Characteristics

5.1.5

Flash Memory Electrical Characteristics

Table 5.8

CPU Clock When Operating Flash Memory (f_(BCLK))

V_CC1= 2.7 to 5.5 V, T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified.

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

Max.

10 ⁽¹⁾

5 ⁽³⁾

-

CPU rewrite mode

MHz

kHz

f(SLOW_R) Slow read mode

-

Low current consumption read mode

Data flash read

fC(32.768)

35

16 ⁽²⁾

20 ⁽²⁾

2.7 V ≤ V_CC1≤ 3.0 V

3.0 V < V_CC1≤ 5.5 V

MHz

Notes:

1. Set the PM17 bit in the PM1 register to 1 (one wait).

2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in

the PM1 register to 1 (one wait)

3. Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as

the CPU clock source, a wait is not necessary.

Table 5.9

Flash Memory (Program ROM 1, 2) Electrical Characteristics

V_CC1= 2.7 to 5.5 V at T_opr= 0°C to 60°C (option: -40°C to 85°C), unless otherwise specified.

Standard

Typ.

Symbol

Parameter

Conditions

Unit

Min.

Max.

Program and erase cycles ^{(1), (3), (4)}

2 word program time

Lock bit program time

Block erase time

1,000 ⁽²⁾

V_CC1= 3.3 V, T_opr= 25°C

-

times

μs

s

V_CC1= 3.3 V, T_opr= 25°C

150

70

4000

3000

3.0

0.2

Program, erase voltage

Read voltage

2.7

0

5.5

V

T_opr= -20°C to 85°C/-40°C to 85°C

5.5

V

Program, erase temperature

60

°C

μs

year

t_PS

Flash memory circuit stabilization wait time

Ambient temperature = 55°C

50

Data hold time ⁽⁶⁾

-

20

Notes:

1. Definition of program and erase cycles:

The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n

(n = 1,000), each block can be erased n times. For example, if a block is erased after writing 2 word data 16,384

times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the

same address more than once without erasing the block (rewrite prohibited).

2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresses in turn so that as much of the block as possible is used up before performing an erase

operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase

operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least three times until the erase error does not occur.

5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time that the power supply is off or the clock is not supplied.

R01DS0032EJ0200 Rev.2.00

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M16C/64A Group

5. Electrical Characteristics

Table 5.10

Flash Memory (Data Flash) Electrical Characteristics

V_CC1= 2.7 to 5.5 V at T_opr= -20 to 85°C/-40 to 85°C, unless otherwise specified.

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Program and erase cycles ^{(1), (3), (4)}

2 word program time

10,000 ⁽²⁾

-

V_CC1= 3.3 V, T_opr= 25°C

times

μs

300

140

0.2

4000

3000

Lock bit program time

Block erase time

μs

3.0

5.5

85

s

V

-

Program, erase voltage

Read voltage

2.7

V

Program, erase temperature

°C

μs

−20/−40

t_PS

-

Flash memory circuit stabilization wait time

Ambient temperature = 55 °C

50

Data hold time ⁽⁶⁾

20

year

Notes:

1. Definition of program and erase cycles

The program and erase cycles refer to the number of per-block erasures.

If the program and erase cycles are n (n = 10,000), each block can be erased n times.

For example, if a 4 KB block is erased after writing 2 word data 1,024 times, each to a different address, this

counts as one program and erase cycles. Data cannot be written to the same address more than once without

erasing the block (rewrite prohibited).

2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresses in turn so that as much of the block as possible is used up before performing an erase

operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be

minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the

erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain

data on the erasure cycles of each block and limit the number of erase operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least three times until the erase error does not occur.

5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.

6. The data hold time includes time that the power supply is off or the clock is not supplied.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 46 of 88

M16C/64A Group

5. Electrical Characteristics

5.1.6

Voltage Detector and Power Supply Circuit Electrical Characteristics

Table 5.11

Voltage Detector 0 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20°C to 85°C/-40°C to 85°C, unless otherwise specified.

Standard

Symbol

V_det0

Parameter

Condition

Unit

Min.

1.60

2.55

Typ. Max.

Voltage detection level Vdet0_0 ⁽¹⁾

Voltage detection level Vdet0_2 ⁽¹⁾

Voltage detector 0 response time ⁽³⁾

When V_CC1is falling.

1.90

2.85

2.20

3.15

V

-

When V_CC1falls from 5 V

to (Vdet0_0 - 0.1) V

200

μs

μA

μs

-

Voltage detector self power consumption

VC25 = 1, V_CC1= 5.0 V

1.8

t_d(E-A)

Waiting time until voltage detector operation

starts ⁽²⁾

100

Notes:

1. Select the voltage detection level with the VDSEL1 bit in the OFS1 address.

2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2

register to 0.

3. Time from when passing the V_det0until when a voltage monitor 0 reset is generated.

Table 5.12

Voltage Detector 1 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20°C to 85°C/-40°C to 85°C, unless otherwise specified.

Standard

Symbol

V_det1

Parameter

Condition

Unit

Min.

2.79

3.54

3.94

Typ. Max.

Voltage detection level Vdet1_6 ⁽¹⁾

Voltage detection level Vdet1_B ⁽¹⁾

Voltage detection level Vdet1_F ⁽¹⁾

When V_CC1is falling.

3.09

3.84

4.44

3.39

4.14

4.94

V

-

Hysteresis width when V_CC1of voltage detector

1 is rising

0.15

V

Voltage detector 1 response time ⁽³⁾

When V_CC1falls from 5 V

to (Vdet1_0 - 0.1) V

200

100

μs

μA

μs

-

Voltage detector self power consumption

VC26 = 1, V_CC1= 5.0 V

1.8

t_d(E-A)

Waiting time until voltage detector operation

starts ⁽²⁾

Notes:

1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC26 bit in the VCR2

register to 0.

3. Time from when passing the V_det1until when a voltage monitor 1 reset is generated.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 47 of 88

M16C/64A Group

5. Electrical Characteristics

Table 5.13

Voltage Detector 2 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20°C to 85°C/-40°C to 85°C, unless otherwise specified.

Standard

Symbol

V_det2

Parameter

Condition

Unit

V

Min.

3.50

Typ. Max.

When V_CC1is falling

4.00

4.50

Voltage detection level Vdet2_0

-

Hysteresis width at the rising of V_CC1in voltage

detector 2

0.15

V

Voltage detector 2 response time ⁽²⁾

-

When V_CC1falls from 5

V to (Vdet2_0 - 0.1) V

VC27 = 1, V_CC1= 5.0 V

200

100

μs

-

Voltage detector self power consumption

1.8

μA

μs

Waiting time until voltage detector operation starts ⁽¹⁾

t_d(E-A)

Notes:

1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2

register to 0.

2. Time from when passing the V_det2until when a voltage monitor 2 reset is generated.

Table 5.14

Power-On Reset Circuit

The measurement condition is V_CC1= 2.0 to 5.5 V, T_opr= -20°C to 85°C/ -40°C to 85°C, unless otherwise specified.

Standard

Symbol

V_por1

Parameter

Condition

Unit

V

Min.

Typ.

Max.

0.1

Voltage at which power-on reset enabled ⁽¹⁾

External power V_CC1rise gradient

t_rth

2.0

50000 mV/ms

ms

t_w(por)

Time necessary to enable power-on reset

300

Note:

1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address

to 0. Also, set the VDSEL1 bit to 0 (Vdet0_2).

(1)

V_det0

t _rth

V_CC1

Vpor1

Voltage detection 0

circuit response time

t_w(por)

Internal

reset signal

1

× 32

f_OCO-S

Note:

1. V_det0indicates the voltage detection level of the voltage detection 0 circuit.

Figure 5.3 Power-On Reset Circuit Electrical Characteristics

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 48 of 88

M16C/64A Group

5. Electrical Characteristics

Table 5.15

Power Supply Circuit Timing Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V and T_opr= 25°C, unless otherwise specified.

Standard

Symbol

Parameter

Condition

Unit

Min. Typ. Max.

Internal power supply stability time when power is on ⁽¹⁾

STOP release time

t_d(P-R)

t_d(R-S)

t_d(W-S)

5

ms

μs

150

Low power mode wait mode release time

Note:

1. Waiting time until the internal power supply generator stabilizes when power is on.

Recommended

operation voltage

t_d(P-R)

Internal power supply stability

time when power is on

V_CC1

t_d(P-R)

CPU clock

Interrupt for

t_d(R-S)

(a) Stop mode release

STOP release time

or

(b) Wait mode release

t_d(W-S)

Low power mode

wait mode release time

CPU clock

(a)

t_d(R-S)

(b)

t_d(W-S)

t_d(E-A)

Voltage detector

VC25, VC26, VC27

operation start time

Stop

Operate

Voltage detector

t_d(E-A)

Figure 5.4

Power Supply Circuit Timing Diagram

R01DS0032EJ0200 Rev.2.00

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Page 49 of 88

M16C/64A Group

5. Electrical Characteristics

5.1.7

Oscillator Electrical Characteristics

Table 5.16

125 kHz On-Chip Oscillator Electrical Characteristics

V_CC1= 2.7 to 5.5 V, T_opr= −20°C to 85°C/−40°C to 85°C, unless otherwise specified.

Standard

Unit

Symbol Parameter Condition

Min. Typ. Max.

f_OCO-S

tsu(f_OCO-S

125 kHz on-chip oscillator frequency Average frequency in a 10 ms period

100 125 150 kHz

)

Wait time until 125 kHz on-chip

oscillator stabilizes

20

μs

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Feb 07, 2011

Page 50 of 88

M16C/64A Group

5. Electrical Characteristics

5.2

5.2.1

Electrical Characteristics (V

= V

= 5 V)

CC1

CC2

Electrical Characteristics

V

= V

= 5 V

CC1

CC2

(1)

Table 5.17

Electrical Characteristics (1)

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20°C to 85°C/−40°C to 85°C, f_(BCLK)= 25 MHz unless otherwise

specified.

Standard

Measuring

Condition

Symbol

V_OH

Parameter

Unit

V

Min.

Typ. Max.

V_CC1

High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, I_OH= −5 mA

V_CC1− 2.0

V_CC2− 2.0

V_CC1− 0.3

V_CC2− 0.3

voltage

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, I_OH= −5 mA

V_CC2

V_CC1

V_CC2

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

V_OH

High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, I_OH= −200 μA

V

voltage

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, I_OH= −200 μA

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

V_OH

High output voltage XOUT

HIGH POWER

LOW POWER

HIGH POWER

I_OH= −1 mA

V_CC1− 2.0

V_CC1

V

I_OH= −0.5 mA

High output voltage XCOUT

With no load

applied

2.6

LOW POWER

With no load

applied

2.2

V_OL

Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, I_OL= 5 mA

2.0

V

voltage

P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, I_OL= 5 mA

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

2.0

Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, I_OL= 200 μA

0.45

voltage

P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

I_OL= 200 μA

Low output voltage XOUT

HIGH POWER

LOW POWER

HIGH POWER

I_OL= 1 mA

2.0

V

I_OL= 0.5 mA

2.0

Low output voltage XCOUT

With no load

applied

0

LOW POWER

With no load

applied

0

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

R01DS0032EJ0200 Rev.2.00

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Page 51 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC1

CC2

(1)

Table 5.18

Electrical Characteristics (2)

V_CC1=V_CC2=4.2to5.5V, V_SS=0VatT_opr=−20°Cto85°C/−40°Cto 85°C, f_(BCLK)= 25 MHz unless otherwise specified.

Standard

Typ. Max.

2.0

Measuring

Condition

Symbol

Parameter

Unit

V

Min.

0.5

V

_T+- V_T-Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,

INT0 to INT7, NMI, ADTRG, CTS0 to CTS2,

CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7,

SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7,

TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7,

SIN3, SIN4, SD, PMC0, PMC1, SCLMM,

SDAMM, CEC, ZP, IDU, IDV, IDW

V_T+- V_T-Hysteresis RESET

0.5

2.5

V

I_IHHigh input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 5 V

5.0 μA

−5.0 μA

100 kΩ

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS, BYTE

I_IL

Low input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

V_I= 0 V

XIN, RESET, CNVSS, BYTE

R_PULLUPPull-up

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 0 V

30

50

resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

R_fXIN

Feedback resistance XIN

Feedback resistance XCIN

RAM retention voltage

1.5

8

MΩ

V

R_fXCIN

V_RAM

In stop mode

1.8

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 52 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Table 5.19

Electrical Characteristics (3)

R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB,

R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB

V_CC1=V_CC2= 4.2to5.5 V,V_SS=0VatT_opr=−20°Cto85°C/−40°Cto85°C,f_(BCLK)= 25 MHz unless otherwise specified.

Standard

Typ.

Symbol

I_CC

Parameter

Power supply current High-speed mode f_(BCLK)= 25 MHz

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

_(BCLK)=25 MHz, A/D conversion

Measuring Condition

Unit

Min.

Max.

20.0

mA

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f

20.7

16.0

mA

μA

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

f

_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stopped

Main clock stopped

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

125 kHz on-chip

oscillator mode

500.0

Low-power mode

f_(BCLK)= 32 kHz

In low-power mode

FMR22 = FMR23 = 1

On flash memory ⁽¹⁾

f_(BCLK)= 32 kHz

160.0

45.0

20.0

μA

In low-power mode

On RAM ⁽¹⁾

Main clock stopped

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

Wait mode

f_(BCLK)= 32 kHz (oscillation capacity High)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

11.0

6.0

μA

f

_(BCLK)= 32 kHz (oscillation capacity Low)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stopped

125 kHz on-chip oscillator stopped

Peripheral clock stopped

T_opr= 25°C

1.7

During flash

memory program

f

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

20.0

30.0

mA

V

During flash

memory erase

V

Note:

1.

This indicates the memory in which the program to be executed exists.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 53 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Table 5.20

Electrical Characteristics (4)

R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB

R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20°C to 85°C/−40°C to 85°C, f_(BCLK)= 25 MHz unless otherwise specified.

Standard

Typ.

Symbol

I_CC

Parameter

Measuring Condition

f_(BCLK)= 25 MHz

Unit

Min.

Max.

Power supply current High-speed mode

22.0

mA

μA

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

f_(BCLK)= 25 MHz, A/D conversion

In single-chip, mode,

the output pin are

open and other pins

are V_SS

22.7

17.0

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

f_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stopped

Main clock stopped

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

f_(BCLK)= 32 kHz

125 kHz on-chip

oscillator mode

550.0

Low-power mode

In low-power mode

FMR22 = FMR23 = 1

on flash memory ⁽¹⁾

f_(BCLK)= 32 kHz

170.0

45.0

20.5

μA

In low-power mode

on RAM ⁽¹⁾

Main clock stopped

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

Wait mode

f

_(BCLK)= 32 kHz (oscillation capacity High)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

11.0

6.0

μA

f_(BCLK)= 32 kHz (oscillation capacity low)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stopped

125 kHz on-chip oscillator stopped

Peripheral clock stopped

T_opr= 25°C

1.7

During flash memory f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

program

During flash memory f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

erase

20.0

30.0

mA

V

_CC1= 5.0 V

V_CC1= 5.0 V

Note:

1. This indicates the memory in which the program to be executed exists.

R01DS0032EJ0200 Rev.2.00

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Page 54 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

5.2.2

Timing Requirements (Peripheral Functions and Others)

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.2.1

Reset Input (RESET Input)

Table 5.21

Reset Input (RESET Input)

Parameter

Standard

Symbol

t_w(RSTL)

Unit

μs

Min.

10

Max.

RESET input low pulse width

RESET input

t_w(RTSL)

Figure 5.5

Reset Input (RESET Input)

5.2.2.2

External Clock Input

(1)

Table 5.22

External Clock Input (XIN Input)

Standard

Symbol

Parameter

Unit

Min.

Max.

t_c

External clock input cycle time

External clock input high pulse width

External clock input low pulse width

External clock rise time

50

20

ns

t_w(H)

t_w(L)

t_r

9

t_f

External clock fall time

Note:

1. The condition is V_CC1= V_CC2= 3.0 to 5.0 V.

XIN input

t_f

t_r

t_w(H)

t_w(L)

t_c

Figure 5.6

External Clock Input (XIN Input)

R01DS0032EJ0200 Rev.2.00

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Page 55 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.2.3

Timer A Input

Table 5.23

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

40

Table 5.24

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.25

Timer A Input (External Trigger Input in One-Shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.26

Timer A Input (External Trigger Input in Pulse Width Modulation Mode and

Programmable Output Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

ns

t_c(TA)

t_w(TAH)

TAiIN input

t_w(TAL)

t_c(UP)

t_w(UPH)

TAiOUT input

t_w(UPL)

Figure 5.7

Timer A Input

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M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

Table 5.27

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

t_c(TA)

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

ns

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

Two-phase pulse input in event counter mode

TAiIN input

t_c(TA)

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

t_{su(TAIN-TAOUT)}

TAiOUT input

t_{su(TAOUT-TAIN)}

Figure 5.8

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 57 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.2.4

Timer B Input

Table 5.28

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

t_c(TB)

TBiIN input cycle time (counted on one edge)

ns

t_w(TBH)

t_w(TBL)

t_c(TB)

TBiIN input high pulse width (counted on one edge)

TBiIN input low pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input high pulse width (counted on both edges)

TBiIN input low pulse width (counted on both edges)

40

200

80

t_w(TBH)

t_w(TBL)

80

Table 5.29

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

Table 5.30

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

t_c(TB)

t_w(TBH)

TBiIN input

t_w(TBL)

Figure 5.9

Timer B Input

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 58 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.2.5

Serial Interface

Table 5.31

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

80

t_c(CK)

CLKi input cycle time

CLKi input high pulse width

CLKi input low pulse width

TXDi output delay time

TXDi hold time

ns

t_w(CKH)

t_w(CKL)

t_d(C-Q)

t_h(C-Q)

t_su(D-C)

t_h(C-D)

0

RXDi input setup time

RXDi input hold time

70

90

t_c(CK)

t _w(CKH)

CLKi

t _w(CKL)

t_h(C-Q)

TXDi

RXDi

t_d(C-Q)

t_su(D-C)

t_h(C-D)

Figure 5.10 Serial Interface

5.2.2.6

External Interrupt INTi Input

Table 5.32

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

250

Max.

t_w(INH)

t_w(INL)

INTi input high pulse width

INTi input low pulse width

ns

t_w(INL)

INTi input

t_w(INH)

Figure 5.11 External Interrupt INTi Input

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 59 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

2

5.2.2.7

Multi-master I C-bus

2

Table 5.33

Multi-master I C-bus

Standard Clock Mode

Fast-mode

Symbol

Parameter

Unit

Min.

4.7

4.0

4.7

Max.

Min.

Max.

t_BUF

Bus free time

1.3

μs

ns

μs

ns

μs

t_HD;STA

t_LOW

t_R

Hold time in start condition

Hold time in SCL clock 0 status

SCL, SDA signals’ rising time

Data hold time

0.6

1.3

1000

300

20 + 0.1 Cb

300

0.9

t_HD;DAT

t_HIGH

f_F

0

0.6

Hold time in SCL clock 1 status

SCL, SDA signals’ falling time

Data setup time

4.0

20 + 0.1 Cb

100

300

t_su;DAT

t_su;STA

t_su;STO

250

4.7

4.0

Setup time in restart condition

Stop condition setup time

0.6

SDA

t_su;STO

t_HD;STA

t_BUF

t_LOW

t_R

t_F

p

Sr

p

s

SCL

t_HD;STA

t_HD;DATt_HIGH

t_su;DAT

t_su;STA

2

Figure 5.12 Multi-master I C-bus

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 60 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.3

Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)

Table 5.34

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

t_ac1(RD-DB)

t_ac2(RD-DB)

t_ac3(RD-DB)

t_su(DB-RD)

Data input access time (for setting with no wait)

Data input access time (for setting with 1 to 3 waits)

Data input access time (when accessing multiplex bus area)

Data input setup time

(Note 1)

(Note 2)

(Note 3)

ns

40

80

0

t_su(RDY-BCLK)

t_h(RD-DB)

RDY input setup time

Data input hold time

t_h(BCLK-RDY)

RDY input hold time

0

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 45[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

(n + 0.5) × 10⁹

------------------------------------ – 4 5 [ns]

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

f_(BCLK)

3. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 45[ns]

n is 2 for 2 waits setting, and 3 for 3 waits setting.

f_(BCLK)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 61 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 5 V

Memory Expansion Mode and Microprocessor Mode

(Effective in wait state setting)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

t_su(RDY-BCLK)

t_h(BCLK-RDY)

Measuring conditions

y V_CC1= V_CC2= 5 V

y Input timing voltage: V = 1.0 V, V = 4.0 V

IL

IH

y Output timing voltage: V = 2.5 V, V = 2.5 V

OL

OH

Figure 5.13 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 62 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

5.2.4

Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.4.1

In No Wait State Setting

Table 5.35

Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

25

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

25

15

25

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

−4

0

ALE signal output hold time

See

Figure 5.14

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 40[ns] f_(BCLK)is 12.5 MHz or less.

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off, and does not

show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up (pull-down)

resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = −CR × ln(1−V_OL/V_CC2

)

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold time of output

low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 63 of 88

M16C/64A Group

5. Electrical Characteristics

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

30 pF

Figure 5.14 Ports P0 to P10 Measurement Circuit

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 64 of 88

M16C/64A Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in no wait state setting)

V_CC1= V_CC2= 5V

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

t_h(RD-AD)

-4ns(min.)

15ns(max.)

0ns(min.)

ALE

RD

t_h(BCLK-RD)

t_d(BCLK-RD)

0ns(min.)

25ns(max.)

t_ac1(RD-DB)

(0.5 × t

-45)ns(max.)

cyc

Hi-Z

DBi

t_su(DB-RD)

40ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

15ns(max.)

(0.5 × t

-10)ns(min.)

cyc

ALE

t_d(BCLK-WR)

25ns(max.)

t_h(BCLK-WR)

0ns(min.)

WR, WRL,

WRH

t_d(BCLK-DB)

40ns(max.)

t_h(BCLK-DB)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

cyc

t_h(WR-DB)

(0.5 × t

-40)ns(min.) (0.5 × t

-10)ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

y V_CC1= V_CC2= 5V

y Input timing voltage: V = 0.8 V, V = 2.0 V

IL

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.15 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 65 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

CC2

5.2.4.2

In 1 to 3 Waits Setting and When Accessing External Area

Table 5.36

Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When

Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

25

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 2)

25

15

25

40

Chip select output hold time (in relation to BCLK)

0

-4

0

t_d(BCLK-ALE)ALE signal output delay time

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

RD signal output delay time

RD signal output hold time

See

Figure 5.14

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR)⁽³⁾

t_h(WR-DB)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

When n = 1, f_(BCLK)is 12.5 MHz or less.

----------------------------------- – 40[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

t = −CR × ln(1 − V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold

time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 66 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 5V

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

15ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

25ns(max.)

RD

t_ac2(RD-DB)

{(n+0.5) × t -45}ns(max.)

cyc

Hi-Z

DBi

t_h(RD-DB)

0ns(min.)

t_su(DB-RD)

40ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

15ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

25ns(max.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

t_h(WR-DB)

(0.5 × t -10)ns(min.)

cyc

{(n-0.5) × t -40}ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 5V

y Input timing voltage: V_IL= 0.8 V, V = 2.0 V

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.16 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 67 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

CC2

5.2.4.3

Table 5.37

Symbol

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

(5)

Accessing External Area and Using Multiplexed Bus)

Standard

Measuring

Condition

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

25

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

(Note 1)

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_h(RD-CS)

25

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

0

(Note 1)

t_h(WR-CS)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

25

40

RD signal output hold time

0

WR signal output delay time

See

Figure 5.14

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of address

WR signal output delay from the end of address

Address output floating start time

0

(Note 2)

(Note 1)

t_h(WR-DB)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(AD-ALE)

t_h(AD-ALE)

t_d(AD-RD)

15

−4

(Note 3)

(Note 4)

0

t_d(AD-WR)

0

t_dz(RD-AD)

8

Notes:

1.

2.

3.

4.

5.

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 40[ns] n is 2 for 2-wait setting, 3 for 3-wait setting.

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 25[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 15[ns]

f_(BCLK)

When using multiplex bus, set f_(BCLK)12.5 MHz or less.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 68 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 5V

Memory Expansion Mode and Microprocessor Mode

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus)

Read timing

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

t_h(RD-CS)

t_cyc

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(AD-ALE)

t_h(ALE-AD)

(0.5 × t -15ns(min.)

cyc

(0.5 × t -25ns(min.)

cyc

ADi

/DBi

Address

Data input

Address

t_dz(RD-AD)

t_h(RD-DB)

0ns(min.)

8ns(max.)

t_su(DB-RD)

40ns(min.)

t_ac3(RD-DB)

{(n-0.5) × t -45}ns(max.)

cyc

t_d(AD-RD)

t_d(BCLK-AD)

0ns(min.)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(RD-AD)

15ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

RD

t_d(BCLK-RD)

t_h(BCLK-RD)

25ns(max.)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

t_cyc

t_h(WR-CS)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(BCLK-DB)

t_h(BCLK-DB)

0ns(min.)

40ns(max.)

ADi

/DBi

Address

Data output

t_d(DB-WR)

Address

t_h(WR-DB)

t_d(AD-ALE)

(0.5 × t -25ns(min.)

cyc

{(n-0.5) × t -40}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)t_h(BCLK-ALE)

t_d(AD-WR)

t_h(WR-AD)

(0.5 × t -10)ns(min.)

cyc

15ns(max.)

-4ns(min.)

0ns(min.)

ALE

t_h(BCLK-WR)

t_d(BCLK-WR)

0ns(min.)

25ns(max.)

WR, WRL,

WRH

n: 2 (when 2 waits)

3 (when 3 waits)

Measuring conditions

y V_CC1= V_CC2= 5V

y Input timing voltage: V = 0.8 V, V = 2.0 V

IL

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.17 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 69 of 88

M16C/64A Group

5. Electrical Characteristics

5.3

5.3.1

Electrical Characteristics (V

= V

= 3 V)

CC1

CC2

Electrical Characteristics

VCC1 = VCC2 = 3 V

(1)

Table 5.38

Electrical Characteristics (1)

V_CC1=V_CC2= 2.7 to 3.3 V, V_SS= 0V at T_opr=-20°Cto 85°C/-40°Cto 85°C, f_(BCLK)= 25 MHz unless otherwise specified.

Standard

Symbol

V_OH

Parameter

Measuring Condition

Unit

V

Min.

Typ. Max.

V_CC1

High

output

voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

I_OH= −1 mA

V_CC1− 0.5

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

I_OH= −1 mA

V_CC2− 0.5

V_CC2

V_OH

High output voltage XOUT

High output voltage XCOUT

HIGH POWER

LOW POWER

I_OH= −0.1 mA

V_CC1− 0.5

V_CC1

V

I_OH= −50 μA

HIGH POWER

LOW POWER

With no load applied

I_OL= 1 mA

2.6

2.2

0.5

V

V_OL

Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to

voltage

P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7

I_OL= 1 mA

0.5

CEC

I_OL= 1 mA

0

0.5

V

V_OL

Low output voltage XOUT

Low output voltage XCOUT

HIGH POWER

LOW POWER

I_OL= 0.1 mA

I_OL= 50 μA

HIGH POWER

LOW POWER

With no load applied

0

V

_T+-V_T-Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to

0.2

1.0

INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7,

SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5

to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to

KI3, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD,

PMC0, PMC1, SCLMM, SDAMM, ZP, IDU, IDV, IDW

CEC

0.2

0.5

1.0

1.8

4.0

V

RESET

I_IH

High input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 3 V

μA

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS, BYTE

−

Leakage current in powered-off state

CEC

V_CC1= 0 V

V_I= 0 V

1.8

μA

I_IL

Low input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

−4.0 μA

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

XIN, RESET, CNVSS, BYTE

R_PULLUPPull-up

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 0 V

50

80

150

kΩ

resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

R_fXIN

Feedback resistance XIN

Feedback resistance XCIN

RAM retention voltage

3.0

16

MΩ

V

R_fXCIN

V_RAM

In stop mode

1.8

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 70 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Table 5.39

Electrical Characteristics (2)

R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB,

R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB

V

= V

= 2.7 to 3.3 V, V = 0 V at T

=

−

20

°

C to 85

°

C/

−

40

°

C to 85

°

C, f =

25 MHz unless otherwise specified.

Standard

CC1

CC2

SS

opr

(BCLK)

Symbol

I_CC

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

Power supply current High-speed mode f_(BCLK)= 25 MHz

20.0

mA

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f

_(BCLK)= 25 MHz, A/D conversion

20.7

16.0

mA

μA

XIN = 4.2 MHz (square wave), PLL multiplied by 6

125 kHz on-chip oscillator stopped

f_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stopped

Main clock stopped

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

125 kHz on-chip

oscillator mode

450.0

Low-power mode f_(BCLK)= 32 MHz

In low-power mode

FMR 22 = FMR23 = 1

On flash memory ⁽¹⁾

160.0

40.0

20.0

μA

f_(BCLK)= 32 MHz

In low-power mode

On RAM ⁽¹⁾

Main clock stopped

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

Wait mode

f_(BCLK)= 32 MHz (oscillation capacity High)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

8.0

4.0

1.6

μA

f_(BCLK)= 32 kHz (oscillation capacity Low)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stopped

125 kHz on-chip oscillator stopped

Peripheral clock stopped

T_opr= 25°C

During flash

memory program

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 3.0 V

20.0

30.0

mA

During flash

memory erase

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 3.0 V

Note:

1.

This indicates the memory in which the program to be executed exists.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 71 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Table 5.40

Electrical Characteristics (3)

R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB

R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB

V_CC1=V_CC2=2.7to3.3V, V_SS=0VatT_opr=−20°Cto85°C/−40°Cto85°C,f_(BCLK)= 25 MHz unless otherwise specified.

Standard

Symbol

I_CC

Parameter

Power supply current High-speed mode f_(BCLK)= 25 MHz

XIN = 4.2 MHz (square wave),

Measuring Condition

Unit

Min.

Typ.

Max.

In single-chip, mode,

the output pin are

open and other pins

are V_SS

PLL multiplied by 6

125 kHz on-chip oscillator stopped

22.0

mA

f_(BCLK)= 25 MHz, A/D conversion

XIN = 4.2 MHz (square wave),

PLL multiplied by 6

22.7

mA

125 kHz on-chip oscillator stopped

f_(BCLK)= 20 MHz

17.0

500.0

170.0

mA

μA

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stopped

Main clock stopped

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

125 kHz on-chip

oscillator mode

Low-power mode

f_(BCLK)= 32 MHz

In low-power mode, FMR 22 = FMR23 = 1

on flash memory ⁽¹⁾

f

_(BCLK)= 32 MHz

40.0

20.0

μA

In low-power mode,

on RAM ⁽¹⁾

Wait mode

Main clock stopped

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

f_(BCLK)= 32 MHz (oscillation capacity High)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

8.0

4.0

1.6

μA

f_(BCLK)= 32kHz (oscillation capacity Low)

125 kHz on-chip oscillator stopped

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stopped

125 kHz on-chip oscillator stopped

Peripheral clock stopped

T_opr= 25°C

During flash

memory program

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 3.0 V

20.0

30.0

mA

During flash

memory erase

f

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 3.0 V

Note:

1. This indicates the memory in which the program to be executed exists.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 72 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

5.3.2

Timing Requirements (Peripheral Functions and Others)

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.2.1

Reset Input (RESET Input)

Table 5.41

Reset Input (RESET Input)

Parameter

Standard

Symbol

t_w(RSTL)

Unit

Min.

10

Max.

RESET input low pulse width

μs

RESET input

t_w(RTSL)

Figure 5.18 Reset Input (RESET Input)

5.3.2.2

External Clock Input

(1)

Table 5.42

External Clock Input (XIN Input)

Standard

Symbol

Parameter

Unit

Min.

50

Max.

t_c

External clock input cycle time

External clock input high pulse width

External clock input low pulse width

External clock rise time

ns

t_w(H)

t_w(L)

t_r

20

9

t_f

External clock fall time

Note:

1.

The condition is V_CC1= V_CC2= 2.7 to 3.0 V.

XIN input

t_f

t_r

t_w(H)

t_w(L)

t_c

Figure 5.19 External Clock Input (XIN Input)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 73 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.2.3

Timer A Input

Table 5.43

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

60

Table 5.44

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.45

Timer A Input (External Trigger Input in One-Shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

300

150

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.46

Timer A Input (External Trigger Input in Pulse Width Modulation Mode and

Programmable Output Mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

ns

t_c(TA)

t_w(TAH)

TAiIN input

t_w(TAL)

t_c(UP)

t_w(UPH)

TAiOUT input

t_w(UPL)

Figure 5.20 Timer A Input

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 74 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

Table 5.47

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2

Max.

t_c(TA)

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

μs

ns

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

500

Two-phase pulse input in event counter mode

TAiIN input

t_c(TA)

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

t_{su(TAIN-TAOUT)}

TAiOUT input

t_{su(TAOUT-TAIN)}

Figure 5.21 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 75 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.2.4

Timer B Input

Table 5.48

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

t_c(TB)

TBiIN input cycle time (counted on one edge)

ns

t_w(TBH)

t_w(TBL)

t_c(TB)

TBiIN input high pulse width (counted on one edge)

TBiIN input low pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input high pulse width (counted on both edges)

TBiIN input low pulse width (counted on both edges)

60

300

120

t_w(TBH)

t_w(TBL)

Table 5.49

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

Table 5.50

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t^w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

t_c(TB)

t_w(TBH)

TBiIN input

t_w(TBL)

Figure 5.22 Timer B Input

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 76 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.2.5

Serial Interface

Table 5.51

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

160

t_c(CK)

CLKi input cycle time

CLKi input high pulse width

CLKi input low pulse width

TXDi output delay time

TXDi hold time

ns

t_w(CKH)

t_w(CKL)

t_d(C-Q)

t_h(C-Q)

t_su(D-C)

t_h(C-D)

0

RXDi input setup time

RXDi input hold time

100

90

t_c(CK)

t _w(CKH)

CLKi

t _w(CKL)

t_h(C-Q)

TXDi

RXDi

t_d(C-Q)

t_su(D-C)

t_h(C-D)

Figure 5.23 Serial Interface

5.3.2.6

External Interrupt INTi Input

Table 5.52

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

380

Max.

t_w(INH)

t_w(INL)

ns

INTi input high pulse width

INTi input low pulse width

t_w(INL)

INTi input

t_w(INH)

Figure 5.24 External Interrupt INTi Input

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 77 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

2

5.3.2.7

Multi-master I C-bus

2

Table 5.53

Multi-master I C-bus

Standard Clock Mode

Fast-mode

Symbol

Parameter

Unit

Min.

4.7

4.0

4.7

Max.

Min.

Max.

t_BUF

Bus free time

1.3

μs

ns

μs

ns

μs

t_HD;STA

t_LOW

t_R

Hold time in start condition

Hold time in SCL clock 0 status

SCL, SDA signals’ rising time

Data hold time

0.6

1.3

1000

300

20 + 0.1 Cb

300

0.9

t_HD;DAT

t_HIGH

f_F

0

0.6

Hold time in SCL clock 1 status

SCL, SDA signals’ falling time

Data setup time

4.0

20 + 0.1 Cb

100

300

t_su;DAT

t_su;STA

t_su;STO

250

4.7

4.0

Setup time in restart condition

Stop condition setup time

0.6

SDA

t_su;STO

t_HD;STA

t_BUF

t_LOW

t_R

t_F

p

Sr

p

s

SCL

t_HD;STA

t_HD;DATt_HIGH

t_su;DAT

t_su;STA

2

Figure 5.25 Multi-master I C-bus

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 78 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.3

Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)

Table 5.54

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

t_ac1(RD-DB)

t_ac2(RD-DB)

t_ac3(RD-DB)

t_su(DB-RD)

Data input access time (for setting with no wait)

Data input access time (for setting with wait)

Data input access time (when accessing multiplex bus area)

Data input setup time

(Note 1)

(Note 2)

(Note 3)

ns

50

85

0

t

RDY input setup time

su(RDY-BCLK)

t_h(RD-DB)

Data input hold time

t_h(BCLK-RDY)

RDY input hold time

0

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 60[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

(n + 0.5) × 10⁹

------------------------------------ – 6 0 [ns] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

f_(BCLK)

3. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 60[ns] n is 2 for 2 waits setting, 3 for 3 waits setting.

f_(BCLK)

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 79 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 3 V

Memory Expansion Mode and Microprocessor Mode

(Effective in wait state setting)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

t_su(RDY-BCLK)

t_h(BCLK-RDY)

Measuring conditions

y V_CC1= V_CC2= 3 V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.26 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 80 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

5.3.4

Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.4.1

In No Wait State Setting

Table 5.55

Memory Expansion and Microprocessor Modes (in No Wait State Setting)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

30

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

30

25

30

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

−4

0

ALE signal output hold time

See

Figure 5.27

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

f_(BCLK)

--------------------- – 40[ns]

f_(BCLK)is 12.5 MHz or less.

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = −CR × ln(1 − V_OL/V_CC2

)

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 81 of 88

M16C/64A Group

5. Electrical Characteristics

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

30 pF

Figure 5.27 Ports P0 to P10 Measurement Circuit

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 82 of 88

M16C/64A Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in no wait state setting)

V_CC1= V_CC2= 3V

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

30ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

t_h(RD-AD)

-4ns(min.)

25ns(max.)

0ns(min.)

ALE

RD

t_h(BCLK-RD)

t_d(BCLK-RD)

0ns(min.)

30ns(max.)

t_ac1(RD-DB)

(0.5 × t -60)ns(max.)

cyc

Hi-Z

DBi

t_su(DB-RD)

t_h(RD-DB)

0ns(min.)

50ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_h(BCLK-AD)

t_d(BCLK-AD)

30ns(max.)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_d(BCLK-WR)

30ns(max.)

t_h(BCLK-WR)

0ns(min.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

cyc

t_h(WR-DB)

(0.5 × t -40)ns(min.) (0.5 × t -10)ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

y V_CC1= V_CC2= 3V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.28 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 83 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.4.2

In 1 to 3 Waits Setting and When Accessing External Area

Table 5.56

Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When

Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

30

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

30

25

30

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

-4

0

ALE signal output hold time

See

Figure 5.27

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

When n = 1, f_(BCLK)is 12.5 MHz or less.

----------------------------------- – 40[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

t=−CR × ln(1−V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold

time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 84 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 3V

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

30ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

25ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

30ns(max.)

RD

t_ac2(RD-DB)

{(n+0.5) × t -60}ns(max.)

cyc

Hi-Z

DBi

t_h(RD-DB)

0ns(min.)

t_su(DB-RD)

50ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

30ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

30ns(max.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

t_h(WR-DB)

(0.5 × t -10)ns(min.)

cyc

{(n-0.5) × t -40}ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 3V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V_OL= 1.5 V, V = 1.5 V

OH

Figure 5.29 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 85 of 88

M16C/64A Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.4.3

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Table 5.57

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

(5)

Accessing External Area and Using Multiplexed Bus)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

50

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

(Note 1)

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_h(RD-CS)

50

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

0

(Note 1)

t_h(WR-CS)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

40

50

RD signal output hold time

0

WR signal output delay time

See

Figure 5.27

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of address

WR signal output delay from the end of address

Address output floating start time

0

(Note 2)

(Note 1)

t_h(WR-DB)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(AD-ALE)

t_h(AD-ALE)

t_d(AD-RD)

25

−4

(Note 3)

(Note 4)

0

t_d(AD-WR)

0

t_dz(RD-AD)

8

Notes:

0.5 × 10⁹

f_(BCLK)

1.

2.

Calculated according to the BCLK frequency as follows: --------------------- – 10[ns]

Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 50[ns]

n is 2 for 2 waits setting, 3 for 3 waits setting.

f_(BCLK)

0.5 × 10⁹

f_(BCLK)

3.

Calculated according to the BCLK frequency as follows: --------------------- – 40[ns]

0.5 × 10⁹

f_(BCLK)

4.

5.

Calculated according to the BCLK frequency as follows: --------------------- – 15[ns]

When using multiplexed bus, set f_(BCLK)12.5 MHz or less.

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 86 of 88

M16C/64A Group

5. Electrical Characteristics

V_CC1= V_CC2= 3V

Memory Expansion Mode and Microprocessor Mode

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus)

Read timing

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

t_h(RD-CS)

t_cyc

50ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(AD-ALE)

t_h(ALE-AD)

(0.5 × t -15ns(min.)

cyc

(0.5 × t -40ns(min.)

cyc

ADi

/DBi

Address

Data input

Address

t_dz(RD-AD)

t_h(RD-DB)

0ns(min.)

8ns(max.)

t_su(DB-RD)

50ns(min.)

t_ac3(RD-DB)

{(n-0.5) × t -60}ns(max.)

cyc

t_d(AD-RD)

t_d(BCLK-AD)

0ns(min.)

50ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(RD-AD)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

RD

t_d(BCLK-RD)

t_h(BCLK-RD)

40ns(max.)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

t_cyc

t_h(WR-CS)

50ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(BCLK-DB)

t_h(BCLK-DB)

0ns(min.)

50ns(max.)

ADi

/DBi

Address

Data output

t_d(DB-WR)

Address

t_h(WR-DB)

t_d(AD-ALE)

(0.5 × t -40ns(min.)

cyc

{(n-0.5) × t -50}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

50ns(max.)

ADi

BHE

t_d(BCLK-ALE)t_h(BCLK-ALE)

t_d(AD-WR)

t_h(WR-AD)

(0.5 × t -10)ns(min.)

cyc

25ns(max.)

-4ns(min.)

0ns(min.)

ALE

t_h(BCLK-WR)

t_d(BCLK-WR)

0ns(min.)

40ns(max.)

WR, WRL,

WRH

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 3V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.30 Timing Diagram

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 87 of 88

M16C/64A Group

Appendix 1. Package Dimensions

The information on the latest package dimensions or packaging may be obtained from “Packages“ on the

Renesas Electronics website.

JEITA Package Code

P-QFP100-14x20-0.65

RENESAS Code

PRQP0100JD-B

Previous Code

100P6F-A

MASS[Typ.]

1.8g

H_D

*1

D

80

51

81

50

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Dimension in Millimeters

Reference

Symbol

Min Nom Max

100

D

E

A₂

H_D

H_E

A

19.8 20.0 20.2

13.8 14.0 14.2

2.8

22.5 22.8 23.1

16.5 16.8 17.1

3.05

31

1

30

Z_D

Index mark

F

A₁

b_p

c

0.1 0.2

0.3 0.4

0

0.25

0.2

10°

0.13 0.15

0°

L

*3

e

b_p

y

x

Detail F

e

x

y

0.65

0.13

0.10

Z_D

Z_E

L

0.575

0.825

0.4 0.6 0.8

JEITA Package Code

RENESAS Code

PLQP0100KB-A

Previous Code

MASS[Typ.]

0.6g

P-LQFP100-14x14-0.50

100P6Q-A / FP-100U / FP-100UV

H_D

*1

D

51

75

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

76

50

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

A₂

H_D

H_E

A

13.9 14.0 14.1

1.4

15.8 16.0 16.2

1.7

Terminal cross section

100

26

A₁

b_p

b₁

c

0.1

0.05

0.15

1

25

Index mark

0.15 0.20 0.25

0.18

Z_D

F

0.145

0.09

0.20

c₁

0.125

0°

8°

e

0.5

y

*3

x

y

L

0.08

b_p

e

x

L₁

Z_D

Z_E

L

1.0

0.5

1.0

Detail F

0.35

0.65

L₁

R01DS0032EJ0200 Rev.2.00

Feb 07, 2011

Page 88 of 88

REVISION HISTORY

M16C/64A Group Datasheet

Description

Summary

Rev.

Date

Page

-

1.01

1.10

Feb 03, 2009

Jul 15, 2009

First Edition issued.

-

Watchdog Timer Reset Register → Watchdog Timer Refresh Register

Table 1.2 Specifications for the 100-Pin Package (2/2) partially modified

Table 1.3 Product List partially modified

3

4

5

Figure 1.2 Marking Diagram (Top View) partially modified

Figure 3.2 Memory Map 13800h → 13000h

18

20

21

29

37

38

39

40

41

42

44

Table 4.1 “SFR Information (1/16)” reset value in VCR1 modified

Table 4.2 “SFR Information (2/16)” partially modified

Table 4.10 “SFR Information (10/16)” reset value in S11 modified

Table 5.1 Absolute Maximum Ratings partially modified

Table 5.2 Recommended Operating Conditions (1/3) partially modified

Table 5.3 Recommended Operating Conditions (2/3) partially modified

Table 5.4 Recommended Operating Conditions (3/3) added

Figure 5.1 Ripple Waveform added

Table 5.5 A/D Conversion Characteristics (1/2) partially modified

Figure 5.2 A/D Accuracy Measure Circuit added

Table 5.6 A/D Conversion Characteristics (2/2) partially modified

Table 5.8 CPU Clock When Operating Flash Memory (f_(BCLK)) partially modified

44

46

47

48

50

53

54

55

69

70

71

73

Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics notes modified

Table 5.11 Voltage Detector 0 Electrical Characteristics partially modified

Table 5.12 Voltage Detector 1 Electrical Characteristics partially modified

Table 5.13 Voltage Detector 2 Electrical Characteristics partially modified

Table 5.14 Power-On Reset Circuit partially modified

Figure 5.3 Power-On Reset Circuit Electrical Characteristics partially modified

Table 5.16 125 kHz On-Chip Oscillator Circuit Electrical Characteristics partially modified

Table 5.19 Electrical Characteristics (3) partially modified

Table 5.20 Electrical Characteristics (4) partially modified

5.2.2.1 Reset Input (RESET Input) added

Table 5.37 Electrical Characteristics (1) partially modified

Table 5.38 Electrical Characteristics (2) partially modified

Table 5.39 Electrical Characteristics (3) partially modified

5.3.2.1 Reset Input (RESET Input) added

Same modifications made to both 3 V and 5 V specifications.

2.00

Feb 07, 2011

Overall

001Ah Voltage Detector Operation Enable Register: Changed reset value from “000X

0000b”.

Overall

002Ah Voltage Monitor 0 Control Register: Changed reset value from “1100 XX10b”.

002Bh Voltage Monitor 1 Control Register: Changed reset value from “1000 1X10b”.

0324h Increment/Decrement Flag: Changed name from Up/Down Flag.

033Eh Timer B2 Special Mode Register: Changed reset value from “XX00 0000b”.

03A2h Open-Circuit Detection Assist Function Register: Changed reset value from “XXXX

XX00b”.

Overall

03DCh D/A Control Register: Changed reset value from “XXXX XX00b”.

D08Ah to D08Bh PMC0 Counter Value Register: Deleted.

D09Eh to D09Fh PMC1 Counter Value Register: Deleted.

Changed “high-speed clock mode” to “fast-mode”.

Overall

Overview

3

4

Table 1.2 Specifications for the 100-Pin Package (2/2): Deleted note 1.

Table 1.3 Product List: Added the new part numbers.

5

Figure 1.1 Part No., with Memory Size and Package: Added “K” to the Memory capacity.

11

Table 1.6 Pin Functions for the 100-Pin Package (1/3): Changed the description of HOLD

pin.

A - 1

REVISION HISTORY

M16C/64A Group Datasheet

Description

Summary

Rev.

2.00

Date

Page

Feb 07, 2011 Address Space

18 Figure 3.2 Memory Map:

• Added the address of 384 KB version.

• Added note 1 and 3 to the reserved areas.

Special Function Registers (SFRs)

Table 4.1 SFR Information (1) ⁽¹⁾

:

20

• Deleted “the VCR1 register, the VCR2 register” from note 2.

• Deleted notes 5 to 6 and added note 5.

Table 4.2 SFR Information (2) ⁽¹⁾: Deleted notes 2 to 7 and added note 2.

4.2.1 Register Settings: Added the description regarding read-modify-write instructions.

Table 4.20 Read-Modify-Write Instructions: Added.

21

38

39

Electrical Characteristics

40

Table 5.1 Absolute Maximum Ratings:

Added a row for the data area value to T (Flash program erase).

opr

41

Table 5.2 Recommended Operating Conditions (1/3):

Added rows for the CEC value to V

, V , V , and V .

CC1 CC2 IH IL

45

48

Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics:

Added a condition to the Read voltage row.

Table 5.14 Power-On Reset Circuit:

• Added the t

row.

w(por)

• Added the last line in note 1.

48

52

Figure 5.3 Power-On Reset Circuit Electrical Characteristics: Deleted note 2.

Table 5.18 Electrical Characteristics (2) ⁽¹⁾: Added “ZP, IDU, IDV, IDW” to the V_T+-V_T-row.

Table 5.20 Electrical Characteristics (4): Added new part numbers above the table.

Table 5.33 and Table 5.53 Multi-master I²C-bus: Added.

54

60, 78

61

Table 5.34 Memory Expansion Mode and Microprocessor Mode:

Changed RDY input setup time from 30.

61 to 68, Table 5.34 to Table 5.37 and Table 5.54 to Table 5.57 Memory Expansion Mode and

Microprocessor Mode:

Deleted the following:

• HOLD input setup time

• HOLD input hold time

• HLDA output delay time

79 to 86

62, 80

70

Figure 5.13 and Figure 5.26 Timing Diagram:

Deleted lower figure (Common to wait state and no wait state settings).

Table 5.38 Electrical Characteristics (1) ⁽¹⁾

• Added rows for the CEC value to Leakage current in powered-off state, V_T+-V_T-, and

V_OL

:

.

• Added “ZP, IDU, IDV, IDW” to the V_T+-V_T-row.

71

72

Table 5.39 Electrical Characteristics (2): Changed “VCC1 = 5.0 V” to "VCC1 = 3.0 V" in the

During flash memory program and During flash memory erase rows.

Table 5.40 Electrical Characteristics (3):

• Added new part numbers above the table.

• Changed “VCC1 = 5.0 V” to "VCC1 = 3.0 V" in the During flash memory program and

During flash memory erase rows.

79

Table 5.54 Memory Expansion Mode and Microprocessor Mode:

Changed RDY input setup time from 40.

All trademarks and registered trademarks are the property of their respective owners.

IEBus is a registered trademark of NEC Electronics Corporation.

HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC.

A - 2

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or

technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics

assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific":

Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and

malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the

possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics

products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes

no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Tel: +1-905-898-5441, Fax: +1-905-898-3220

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-65030, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China

Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

7F, No. 363 Fu Shing North Road Taipei, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632

Tel: +65-6213-0200, Fax: +65-6278-8001

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141

Colophon 1.0


型号：	R5F364AKNFA#U0
厂家：	RENESAS TECHNOLOGY CORP
描述：	16-bit Microcomputers (Non Promotion), QFP, / 微控制器外围集成电路
文件：	总92页 (文件大小：736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F364AKNFA#U0 [RENESAS]

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