R5F36506DFA_技术文档

REJ03B0257-0110

Rev.1.10

M16C/65 Group

RENESAS MCU

Sep 24, 2009

1. Overview

1.1

Features

The M16C/65 Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash

memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address

space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the

CPU core boasts a multiplier for high-speed operation processing.

This MCU consumes low power, and supports operating modes that allow additional power control. The

MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed

to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including

the multifunction timer and serial interface, the number of system components has been reduced.

1.1.1

Applications

This MCU can be used in audio components, cameras, televisions, household appliances, office

equipment, communication devices, mobile devices, industrial equipment, and other applications.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 1 of 109

M16C/65 Group

1. Overview

1.2

Specifications

The M16C/65 Group includes 128-pin and 100-pin packages. Table 1.1 to Table 1.4 list specifications.

Table 1.1

Item

Specifications for the 128-Pin Package (1/2)

Function

Description

M16C/60 Series core

(multiplier: 16-bit × 16-bit ꢀ 32-bit,

multiply and accumulate instruction: 16-bit × 16-bit + 32-bit ꢀ 32-bit)

•Number of basic instructions: 91

CPU

Central processing unit

•Minimum instruction execution time:

31.25 ns (f(BCLK) = 32 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)

•Operating modes: Single-chip, memory expansion, and microprocessor

Memory

ROM, RAM, data flash

Voltage detector

See Table 1.5 “Product List (1/2)” and Table 1.6 “Product List (2/2)”.

•Power-on reset

Voltage

Detection

•3 voltage detection points (detection level of voltage detection 0 and 1

selectable)

•5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),

high-speed on-chip oscillator (40 MHz ±10%), PLL frequency synthesizer

•Oscillation stop detection: Main clock oscillation stop/reoscillation

detection function

Clock

Clock generator

•Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16

•Power saving features: Wait mode, stop mode

•Real-time clock

•Address space: 1 MB

•External bus interface: 0 to 8 waits inserted, 4 chip select outputs,

memory area expansion function (expandable to 4 MB), 3 V and 5 V

interfaces

•Bus format: Separate bus or multiplexed bus selectable, data bus width

selectable (8 or 16 bits), number of address buses selectable (12, 16, or

20)

External Bus

Expansion

Bus memory expansion

Programmable I/O ports

•CMOS I/O ports: 111 (selectable pull-up resistors)

•N-channel open drain ports: 3

I/O Ports

Interrupts

•Interrupt vectors: 70

•External interrupt inputs: 13 (NMI, INT × 8, key input × 4)

•Interrupt priority levels: 7

15-bit timer × 1 (with prescaler)

Automatic reset start function selectable

Watchdog Timer

•4 channels, cycle steal mode

DMA

DMAC

•Trigger sources: 43

•Transfer modes: 2 (single transfer, repeat transfer)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 2 of 109

M16C/65 Group

1. Overview

Table 1.2

Specifications for the 128-Pin Package (2/2)

Item

Function

Description

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse width

modulation (PWM) mode

Event counter two-phase pulse signal processing (two-phase encoder

input) × 3

Timer A

Timer B

Programmable output mode × 3

16-bit timer × 6

Timer mode, event counter mode, pulse period measurement mode,

pulse width measurement mode

• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)

• On-chip dead time timer

Timers

Three-phase motor control

timer functions

Real-time clock

PWM function

Count: seconds, minutes, hours, days of the week

8 bits × 2

• 2 circuits

• 4 wave pattern matchings (differentiate wave pattern for headers, data

0, data 1, and special data)

Remote control signal receiver

• 6-byte receive buffer (1 circuit only)

• Operating frequency of 32 kHz

Clock synchronous/asynchronous × 6 channels

I²C-bus, IEBus ⁽¹⁾, special mode 2

SIM (UART2)

UART0 to UART2, UART5 to

UART7

Serial

Interface

SI/O3, SI/O4

Clock synchronization only × 2 channels

1 channel

Multi-master I²C-bus Interface

CEC transmit/receive, arbitration lost detection, ACK automatic output,

operation frequency of 32 kHz

CEC Functions ⁽³⁾

10-bit resolution × 26 channels, including sample and hold function

Conversion time: 1.72 µs

A/D Converter

D/A Converter

CRC Calculator

8-bit resolution × 2 circuits

CRC-CCITT (X¹⁶+ X¹²+ X⁵+ 1),

CRC-16 (X¹⁶+ X¹⁵+ X²+ 1) compliant

• Program and erase power supply voltage: 2.7 to 5.5 V

• Program and erase cycles: 1,000 times (program ROM 1, program

ROM 2), 10,000 times (data flash)

Flash Memory

• Program security: ROM code protect, ID code check

Debug Functions

On-chip debug, on-board flash rewrite, address match interrupt × 4

32 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1

Described in 5. “Electrical Characteristics”

Operation Frequency/Supply Voltage

Current Consumption

Operating Temperature

Package

-20°C to 85°C, -40°C to 85°C ⁽²⁾

128-pin LQFP: PLQP0128KB-A (Previous package code: 128P6Q-A)

Notes:

1. IEBus is a registered trademark of NEC Electronics Corporation.

2. See Table 1.5 “Product List (1/2)” and Table 1.6 “Product List (2/2)” for the operating temperature.

3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized

by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are

registered trademarks of HDMI Licensing, LLC.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 3 of 109

M16C/65 Group

1. Overview

Table 1.3

Specifications for the 100-Pin Package (1/2)

Item

Function

Description

M16C/60 Series core

(multiplier: 16-bit × 16-bit ꢀ 32-bit,

multiply and accumulate instruction: 16-bit × 16-bit + 32-bit ꢀ 32-bit)

•Number of basic instructions: 91

CPU

Central processing unit

•Minimum instruction execution time:

31.25 ns (f(BCLK) = 32 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)

•Operating modes: Single-chip, memory expansion, and microprocessor

Memory

ROM, RAM, data flash

Voltage detector

See Table 1.5 “Product List (1/2)” and Table 1.6 “Product List (2/2)”.

•Power-on reset

Voltage

Detection

•3 voltage detection points (detection level of voltage detection 0 and 1

selectable)

•5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),

high-speed on-chip oscillator (40 MHz ±10%), PLL frequency synthesizer

•Oscillation stop detection: Main clock oscillation stop/reoscillation

detection function

Clock

Clock generator

•Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16

•Power saving features: Wait mode, stop mode

•Real-time clock

•Address space: 1 MB

•External bus interface: 0 to 8 waits inserted, 4 chip select outputs,

memory area expansion function (expandable to 4 MB), 3 V and 5 V

interfaces

•Bus format: Separate bus or multiplexed bus selectable, data bus width

selectable (8 or 16 bits), number of address buses selectable (12, 16, or

20)

External Bus

Expansion

Bus memory expansion

Programmable I/O ports

•CMOS I/O ports: 85 (selectable pull-up resistors)

•N-channel open drain ports: 3

I/O Ports

Interrupts

•Interrupt vectors: 70

•External interrupt inputs: 13 (NMI, INT × 8, key input × 4)

•Interrupt priority levels: 7

15-bit timer × 1 (with prescaler)

Automatic reset start function selectable

Watchdog Timer

•4 channels, cycle steal mode

DMA

DMAC

•Trigger sources: 43

•Transfer modes: 2 (single transfer, repeat transfer)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 4 of 109

M16C/65 Group

1. Overview

Table 1.4

Specifications for the 100-Pin Package (2/2)

Item

Function

Description

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse width

modulation (PWM) mode

Event counter two-phase pulse signal processing (two-phase encoder

input) × 3

Timer A

Timer B

Programmable output mode × 3

16-bit timer × 6

Timer mode, event counter mode, pulse period measurement mode,

pulse width measurement mode

• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)

• On-chip dead time timer

Timers

Three-phase motor control

timer functions

Real-time clock

PWM function

Count: seconds, minutes, hours, days of the week

8 bits × 2

• 2 circuits

• 4 wave pattern matchings (differentiate wave pattern for headers, data

0, data 1, and special data)

Remote control signal receiver

• 6-byte receive buffer (1 circuit only)

• Operating frequency of 32 kHz

Clock synchronous/asynchronous × 6 channels

I²C-bus, IEBus ⁽¹⁾, special mode 2

SIM (UART2)

Serial

Interface

UART0 to UART2, UART5 to

UART7

SI/O3, SI/O4

Clock synchronization only × 2 channels

1 channel

Multi-master I²C-bus Interface

CEC transmit/receive, arbitration lost detection, ACK automatic output,

operation frequency of 32 kHz

CEC Functions ⁽³⁾

10-bit resolution × 26 channels, including sample and hold function

Conversion time: 1.72 µs

A/D Converter

D/A Converter

CRC Calculator

8-bit resolution × 2 circuits

CRC-CCITT (X¹⁶+ X¹²+ X⁵+ 1),

CRC-16 (X¹⁶+ X¹⁵+ X²+ 1) compliant

• Program and erase power supply voltage: 2.7 to 5.5 V

• Program and erase cycles: 1,000 times (program ROM 1, program

ROM 2), 10,000 times (data flash)

Flash Memory

• Program security: ROM code protect, ID code check

Debug Functions

On-chip debug, on-board flash rewrite, address match interrupt × 4

25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1

32 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1

Operation Frequency/Supply Voltage

Current Consumption

Operating Temperature

Described in 5. “Electrical Characteristics”

-20°C to 85°C, -40°C to 85°C ⁽²⁾

100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)

100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)

Package

Notes:

1. IEBus is a registered trademark of NEC Electronics Corporation.

2. See Table 1.5 “Product List (1/2)” and Table 1.6 “Product List (2/2)” for the operating temperature.

3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized

by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are

registered trademarks of HDMI Licensing, LLC.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 5 of 109

M16C/65 Group

1. Overview

1.3

Product List

Table 1.5 and Table 1.6 list product information. Figure 1.1 shows the Part No., with Memory Size and

Package, and Figure 1.2 shows the Marking Diagram (Top View).

Table 1.5

Product List (1/2)

As of September 2009

Package Code Remarks

Operating

ROM Capacity

RAM

Capacity

Part No.

Program

ROM 1

Program

ROM 2

Data flash

R5F36506NFA

R5F36506NFB

R5F36506DFA

R5F36506DFB

PRQP0100JD-B

PLQP0100KB-A

PRQP0100JD-B

temperature

-20°C to 85°C

4 KB

× 2 blocks

128 KB

16 KB

12 KB

20 KB

Operating

temperature

-40°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

R5F3651ENFC

R5F3650ENFA

R5F3650ENFB

R5F3651EDFC

R5F3650EDFA

R5F3650EDFB

R5F3651KNFC

R5F3650KNFA

R5F3650KNFB

R5F3651KDFC

R5F3650KDFA

R5F3650KDFB

R5F3651MNFC

R5F3650MNFA

R5F3650MNFB

R5F3651MDFC

R5F3650MDFA

R5F3650MDFB

R5F3651NNFC

R5F3650NNFA

R5F3650NNFB

R5F3651NDFC

R5F3650NDFA

R5F3650NDFB

R5F3651RNFC

R5F3650RNFA

R5F3650RNFB

R5F3651RDFC

R5F3650RDFA

R5F3650RDFB

(D)

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB

× 2 blocks

256 KB

384 KB

512 KB

640 KB

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB

× 2 blocks

16 KB

31 KB

47 KB

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB

× 2 blocks

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB × 2

blocks

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB

× 2 blocks

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

(D): Under development

(P): Planning

Note:

1. Previous package codes are as follows:

PLQP0128KB-A: 128P6Q-A

PRQP0100JD-B: 100P6F-A

PLQP0100KB-A: 100P6Q-A

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 6 of 109

M16C/65 Group

1. Overview

Table 1.6

Product List (2/2)

As of September 2009

ROM Capacity

RAM

Capacity

Part No.

Package Code

Remarks

Program

ROM 2

Data flash

ROM 1

R5F3651TNFC

R5F3650TNFA

R5F3650TNFB

R5F3651TDFC

R5F3650TDFA

R5F3650TDFB

PLQP0128KB-A

Operating

PRQP0100JD-B temperature

-20°C to 85°C

PLQP0100KB-A

PLQP0128KB-A

4 KB

× 2 blocks

768 KB

16 KB

47 KB

Operating

PRQP0100JD-B temperature

-40°C to 85°C

PLQP0100KB-A

(D): Under development

(P): Planning

Note:

1. Previous package codes are as follows:

PLQP0128KB-A: 128P6Q-A

PRQP0100JD-B: 100P6F-A

PLQP0100KB-A: 100P6Q-A

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 7 of 109

M16C/65 Group

Part No.

1. Overview

R 5 F 3 6 5

0

6

D

FA

Package type

FC: Package PLQP0128KB-A (128P6Q-A)

FA: Package PRQP0100JD-B (100P6F-A)

FB: Package PLQP0100KB-A (100P6Q-A)

Property Code

N: Operating temperature: -20°C to 85°C

D: Operating temperature: -40°C to 85°C

Memory capacity

Program ROM 1/RAM

6: 128 KB/12 KB

E: 256 KB/20 KB

K: 384 KB/31 KB

M: 512 KB/31 KB

N: 512 KB/47 KB

R: 640 KB/47 KB

T: 768 KB/47 KB

Number of pins

0: 100 pins

1: 128 pins

M16C/65 Group

16-bit MCU

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.1

Part No., with Memory Size and Package

M1 6 C

R 5 F 3 6 5 0 6 D F A

X X X X X X X

(See Figure 1.1 “Part No., with Memory Size and Package”)

Type No.

Running No. 0 to 9, A to Z (except for I, O, Q)

Week code (from 01 to 54)

Last one digit of year

Figure 1.2

Marking Diagram (Top View)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 8 of 109

M16C/65 Group

1. Overview

1.4

Block Diagram

Figure 1.3 to Figure 1.4 show block diagrams.

8

Port P0

Port P1

Port P2

Port P3 Port P4 Port P5

VCC2 ports

Port P12 Port P13

Internal peripheral functions

System clock generator

UART or

clock synchronous serial I/O

(6 channels)

XIN-XOUT

XCIN-XCOUT

Timer (16-bit)

PLL frequency synthesizer

On-chip oscillator (125 kHz)

High-speed on-chip oscillator

Outputs (timer A): 5

Inputs (timer B): 6

Clock synchronous serial I/O

(8-bit x 2 channels)

Multi-master I²C-bus interface

(1 channel)

Three-phase

motor control circuit

DMAC

(4 channels)

Real-time clock

CRC arithmetic circuit

(CRC-CCITT or CRC-16)

CEC function

PWM function (8-bit x 2)

Voltage detector

Power-on reset

Remote control signal

receiver (2 circuits)

Watchdog timer

(15-bit)

On-chip debugger

Memory

ROM ⁽¹⁾

A/D converter

(10-bit resolution x 26

channels)

M16C/60 Series CPU core

SB

USP

ISP

R0H

R1H

R0L

R1L

R2

R3

D/A converter

(8-bit resolution x 2

circuits)

RAM ⁽²⁾

INTB

PC

FLG

A0

A1

FB

Multiplier

VCC1 ports

Port P10 Port P9 Port P8 Port P7

Port P14

2

Port P11

8

Port P6

8

Notes:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Figure 1.3

Block Diagram for the 128-Pin Package

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 9 of 109

M16C/65 Group

1. Overview

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

VCC2 ports

Internal peripheral functions

System clock generator

UART or

clock synchronous serial I/O

(6 channels)

XIN-XOUT

Timer (16-bit)

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator (125 kHz)

High-speed on-chip oscillator

Outputs (timer A): 5

Inputs (timer B): 6

Clock synchronous serial I/O

(8-bit x 2 channels)

Multi-master I²C-bus interface

(1 channel)

Three-phase motor control

circuit

DMAC (4 channels)

Real-time clock

CRC arithmetic circuit

(CRC-CCITT or CRC-16)

CEC function

PWM function (8-bit x 2)

Voltage detector

Power-on reset

Remote control signal

receiver (2 circuits)

Watchdog timer

(15-bit)

On-chip debugger

A/D converter

(10-bit resolution x 26

channels)

Memory

ROM ⁽¹⁾

M16C/60 Series CPU core

SB

USP

ISP

R0H

R1H

R0L

R1L

D/A converter

(8-bit resolution x 2

circuits)

R2

R3

RAM ⁽²⁾

INTB

PC

FLG

A0

A1

FB

Multiplier

VCC1 ports

Port P8

Port P10

8

Port P9

8

Port P7

8

Port P6

8

Notes:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Figure 1.4

Block Diagram for the 100-Pin Package

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 10 of 109

M16C/65 Group

1. Overview

1.5

Pin Assignments

Figure 1.5 to Figure 1.7 show pin assignments. Table 1.7 to Table 1.11 list pin names.

(See Note 3)

P1_0/CTS6/RTS6/D8

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

P12_5

P12_6

P12_7

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P13_0

P13_1

P13_2

VCC2 ports

M16C/65 Group

P11_7

P11_6

P11_5

P11_4

P13_3

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P13_4

P13_5

P13_6

P13_7

P6_0/RTCOUT/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

PLQP0128KB-A

(128P6Q-A)

(top view)

P11_3

P11_2

P11_1

P11_0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

VCC1 ports

VSS

P10_0/AN0

Notes:

1. N-channel open drain output.

2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.

3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two

separate functional signals.

Figure 1.5

Pin Assignment for the 128-Pin Package

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 11 of 109

M16C/65 Group

1. Overview

Table 1.7

Pin Names for the 128-Pin Package (1/3)

I/O Pin for Peripheral Function

Bus Control

Pin No. Control Pin Port

A/D converter,

D/A converter

Interrupt

Timer

Serial interface

1

VREF

2

AVCC

3

4

5

6

7

8

9

P9_7

P9_6

P9_5

P9_4

P9_3

P9_2

P9_1

P9_0

P14_1

P14_0

SIN4

SOUT4

CLK4

ADTRG

ANEX1

ANEX0

DA1

TB4IN/PWM1

TB3IN/PWM0

TB2IN/PMC0

TB1IN/PMC1

TB0IN

DA0

SOUT3

SIN3

CLK3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

BYTE

CNVSS

XCIN

XCOUT

RESET

XOUT

VSS

P8_7

P8_6

XIN

VCC1

P8_5 NMI

P8_4 INT2

P8_3 INT1

P8_2 INT0

P8_1

P8_0

P7_7

P7_6

P7_5

P7_4

P7_3

P7_2

P7_1

P7_0

P6_7

SD

ZP

CEC

TA4IN/U

TA4OUT/U

TA3IN

TA3OUT

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA0IN/TB5IN

TA0OUT

CTS5/RTS5

RXD5/SCL5

CLK5

TXD5/SDA5

CTS2/RTS2

CLK2

RXD2/SCL2/SCLMM

TXD2/SDA2/SDAMM

TXD1/SDA1

VCC1

VSS

P6_6

RXD1/SCL1

P6_5

P6_4

P6_3

P6_2

P6_1

P6_0

P13_7

P13_6

P13_5

P13_4

CLK1

CTS1/RTS1/CTS0/CLKS1

TXD0/SDA0

RXD0/SCL0

CLK0

RTCOUT

CTS0/RTS0

CLKOUT P5_7

RDY

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 12 of 109

M16C/65 Group

1. Overview

Table 1.8

Pin Names for the 128-Pin Package (2/3)

I/O Pin for Peripheral Function

Control

Pin No.

Port

A/D converter,

D/A converter

Bus Control Pin

Interrupt

Timer

Serial interface

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P5_6

P5_5

P5_4

P13_3

P13_2

P13_1

P13_0

P5_3

P5_2

P5_1

P5_0

P12_7

P12_6

P12_5

P4_7

P4_6

P4_5

P4_4

P4_3

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

P12_4

P12_3

P12_2

P12_1

P12_0

ALE

HOLD

HLDA

BCLK

RD

WRH/BHE

WRL/WR

PWM1

PWM0

TXD7/SDA7

RXD7/SCL7

CLK7

CS3

CS2

CS1

CS0

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

CTS7/RTS7

VCC2

VSS

P3_0

A8, [A8/D7]

P2_7

P2_6

P2_5 INT7

P2_4 INT6

P2_3

P2_2

P2_1

P2_0

P1_7 INT5

P1_6 INT4

P1_5 INT3

P1_4

AN2_7

A7, [A7/D7], [A7/D6]

A6, [A6/D6], [A6/D5]

A5, [A5/D5], [A5/D4]

A4[A4/D4], [A4/D3]

A3, [A3/D3], [A3/D2]

A2, [A2/D2], [A2/D1]

A1, [A1/D1], [A1/D0]

A0, [A0/D0], A0

D15

D14

D13

D12

D11

AN2_6

AN2_5

AN2_4

AN2_3

AN2_2

AN2_1

AN2_0

IDU

IDW

IDV

P1_3

TXD6/SDA6

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 13 of 109

M16C/65 Group

1. Overview

Table 1.9

Pin Names for the 128-Pin Package (3/3)

I/O Pin for Peripheral Function

No.

Control

Port

A/D converter,

D/A converter

Bus Control Pin

Interrupt

Timer

Serial interface

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

P1_2

P1_1

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

P11_7

P11_6

P11_5

P11_4

P11_3

P11_2

P11_1

P11_0

RXD6/SCL6

CLK6

CTS6/RTS6

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

AN0_7

AN0_6

AN0_5

AN0_4

AN0_3

AN0_2

AN0_1

AN0_0

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

AN7

AN6

AN5

AN4

AN3

AN2

AN1

P10_2

P10_1

127 AVSS

128

P10_0

AN0

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 14 of 109

M16C/65 Group

1. Overview

(See Note 3)

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P4_4/CTS7/RTS7/CS0

P4_5/CLK7/CS1

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

VCC2 ports

P4_6/PWM0/RXD7/SCL7/CS2

P4_7/PWM1/TXD7/SDA7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/RTCOUT/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

M16C/65 Group

PRQP0100JD-B

(100P6F-A)

(top view)

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG/SIN4

VCC1 ports

Notes:

1. N-channel open drain output.

2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.

3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two

separate functional signals.

Figure 1.6

Pin Assignment for the 100-Pin Package

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 15 of 109

M16C/65 Group

1. Overview

(See Note 3)

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P1_2/RXD6/SCL6/D10

P1_1/CLK6/D9

P1_0/CTS6/RTS6/D8

P4_2/A18

P4_3/A19

P4_4/CTS7/RTS7/CS0

P4_5/CLK7/CS1

P4_6/PWM0/RXD7/SCL7/CS2

P4_7/PWM1/TXD7/SDA7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/RTCOUT/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P7_0/TXD2/SDA2/SDAMM/TA0OUT ⁽¹⁾

P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN ⁽¹⁾

P7_2/CLK2/TA1OUT/V

VCC2 ports

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

M16C/65 Group

PLQP0100KB-A

(100P6Q-A)

(top view)

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

P9_5/ANEX0/CLK4

VCC1 ports

Notes:

1. N-channel open drain output.

2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.

3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two

separate functional signals.

Figure 1.7

Pin Assignment for the 100-Pin Package

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 16 of 109

M16C/65 Group

1. Overview

Table 1.10

Pin Names for the 100-Pin Package (1/2)

I/O Pin for Peripheral Function

Pin No.

Bus Control

Control Pin Port

A/D converter,

D/A converter

ANEX1

ANEX0

DA1

FA FB

Interrupt

Timer

Serial interface

1

2

3

99

100

1

P9_6

P9_5

P9_4

P9_3

P9_2

SOUT4

CLK4

TB4IN/PWM1

TB3IN/PWM0

TB2IN/PMC0

TB1IN/PMC1

TB0IN

4

2

DA0

5

3

SOUT3

SIN3

CLK3

6

4

P9_1

P9_0

7

5

8

6

BYTE

9

7

CNVSS

10

11

8

9

XCIN

XCOUT

P8_7

P8_6

12 10 RESET

13 11 XOUT

14 12 VSS

15 13 XIN

16 14 VCC1

17 15

18 16

19 17

20 18

21 19

P8_5 NMI

P8_4 INT2

P8_3 INT1

P8_2 INT0

P8_1

SD

ZP

CEC

TA4IN/U

TA4OUT/U

TA3IN

CTS5/RTS5

RXD5/SCL5

CLK5

22 20

23 21

P8_0

P7_7

24 22

P7_6

TA3OUT

TXD5/SDA5

25 23

26 24

27 25

P7_5

P7_4

P7_3

TA2IN/W

TA2OUT/W

TA1IN/V

CTS2/RTS2

CLK2

28 26

29 27

30 28

31 29

32 30

33 31

P7_2

P7_1

P7_0

P6_7

P6_6

P6_5

TA1OUT/V

TA0IN/TB5IN

TA0OUT

RXD2/SCL2/SCLMM

TXD2/SDA2/SDAMM

TXD1/SDA1

RXD1/SCL1

CLK1

CTS1/RTS1/CTS0/

CLKS1

34 32

P6_4

35 33

36 34

37 35

38 36

P6_3

P6_2

P6_1

P6_0

TXD0/SDA0

RXD0/SCL0

CLK0

RTCOUT

CTS0/RTS0

39 37 CLKOUT P5_7

RDY

40 38

41 39

42 40

43 41

44 42

45 43

46 44

47 45

48 46

49 47

50 48

P5_6

P5_5

P5_4

P5_3

P5_2

P5_1

P5_0

P4_7

P4_6

P4_5

P4_4

ALE

HOLD

HLDA

BCLK

RD

WRH/BHE

WRL/WR

CS3

CS2

CS1

CS0

PWM1

PWM0

TXD7/SDA7

RXD7/SCL7

CLK7

CTS7/RTS7

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 17 of 109

M16C/65 Group

1. Overview

Table 1.11

Pin Names for the 100-Pin Package (2/2)

I/O Pin for Peripheral Function

Pin No.

Control

Port

A/D converter,

D/A converter

Bus Control Pin

FA FB

Interrupt

Timer

Serial interface

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

P4_3

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

VCC2

VSS

P3_0

A8, [A8/D7]

P2_7

P2_6

P2_5 INT7

P2_4 INT6

P2_3

P2_2

P2_1

P2_0

P1_7 INT5

P1_6 INT4

P1_5 INT3

P1_4

P1_3

P1_2

P1_1

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

AN2_7

A7, [A7/D7], [A7/D6]

A6, [A6/D6], [A6/D5]

A5, [A5/D5], [A5/D4]

A4, [A4/D4], [A4/D3]

A3, [A3/D3], [A3/D2]

A2, [A2/D2], [A2/D1]

A1, [A1/D1], [A1/D0]

A0, [A0/D0], A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

AN2_6

AN2_5

AN2_4

AN2_3

AN2_2

AN2_1

AN2_0

IDU

IDW

IDV

TXD6/SDA6

RXD6/SCL6

CLK6

CTS6/RTS6

AN0_7

AN0_6

AN0_5

AN0_4

AN0_3

AN0_2

AN0_1

AN0_0

AN7

AN6

AN5

AN4

AN3

D4

D3

D2

D1

D0

P10_2

P10_1

AN2

AN1

AVSS

P10_0

P9_7

AN0

VREF

AVCC

100 98

SIN4

ADTRG

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 18 of 109

M16C/65 Group

1. Overview

1.6

Pin Functions

Table 1.12

Pin Functions for the 128-Pin Package (1/3)

Signal Name

Pin Name

I/O

Power Supply

Description

VCC1,

VCC2,

VSS

Power supply

input

Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2),

and 0 V to the VSS pin.

I

-

This is the power supply for the A/D and D/A converters.

Connect the AVCC pin to VCC1, and connect the AVSS pin

to VSS.

Analog power

supply input

AVCC,

AVSS

I

VCC1

Reset input

Driving this pin low resets the MCU.

RESET

Input pin to switch processor modes. After a reset, to start

operating in single-chip mode, connect the CNVSS pin to

VSS via a resistor. To start operating in microprocessor

mode, connect the pin to VCC1.

CNVSS

I

VCC1

Input pin to select the data bus of the external area. The data

bus is 16 bits when it is low and 8 bits when it is high. This

pin must be fixed either high or low. Connect the BYTE pin to

VSS in single-chip mode.

External data bus

width select input

BYTE

I

VCC1

VCC2

Inputs or outputs data (D0 to D7) while accessing an

external area with a separate bus.

D0 to D7

I/O

Inputs or outputs data (D8 to D15) while accessing an

external area with a 16-bit separate bus.

D8 to D15

A0 to A19

I/O

O

VCC2

Outputs address bits A0 to A19.

Inputs or outputs data (D0 to D7) and outputs address bits

(A0 to A7) by timesharing, while accessing an external area

with an 8-bit multiplexed bus.

A0/D0 to

A7/D7

I/O

VCC2

Inputs or outputs data (D0 to D7) and outputs address bits

(A1 to A8) by timesharing, while accessing an external area

with a 16-bit multiplexed bus.

A1/D0 to

A8/D7

I/O

O

VCC2

Outputs chip-select signals CS0 to CS3 to specify an

external area.

CS0 to CS3

Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and

WRH can be switched with BHE and WR.

• WRL, WRH, and RD selected

Bus control

pins

If the external data bus is 16 bits, data is written to an even

address in an external area when WRL is driven low. Data

is written to an odd address when WRH is driven low. Data

is read when RD is driven low.

WRL/WR

WRH/BHE

RD

O

VCC2

• WR, BHE, and RD selected

Data is written to an external area when WR is driven low.

Data in an external area is read when RD is driven low. An

odd address is accessed when BHE is driven low. Select

WR, BHE, and RD when using an 8-bit external data bus.

ALE

HOLD

HLDA

RDY

O

I

VCC2

Output ALE signal to latch address.

The MCU is placed in hold state while the HOLD pin is

driven low.

O

I

In a hold state, HLDA outputs a low-level signal.

The MCU bus is placed in wait state while the RDY pin is

driven low.

Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration

allows VCC2 to interface at a different voltage than VCC1.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 19 of 109

M16C/65 Group

1. Overview

Table 1.13

Pin Functions for the 128-Pin Package (2/3)

Signal Name

Pin Name

XIN

I/O

I

Power Supply

VCC1

Description

I/O for the main clock oscillator. Connect a ceramic

resonator or crystal between pins XIN and XOUT. ⁽¹⁾

Input an external clock to XIN pin and leave XOUT

pin open.

Main clock input

Main clock output

Sub clock input

XOUT

XCIN

O

I

VCC1

I/O for a sub clock oscillator. Connect a crystal

between pins XCIN and XCOUT. ⁽¹⁾Input an external

clock to XCIN pin and leave XCOUT pin open.

Sub clock output

BCLK output

Clock output

XCOUT

BCLK

O

VCC1

VCC2

Outputs the BCLK signal.

Outputs a clock with the same frequency as fC, f1, f8,

or f32.

CLKOUT

I

VCC1

VCC2

VCC1

INT0 to INT2

INT3 to INT7

NMI

INT interrupt input

NMI interrupt input

Input for the INT interrupt.

Input for the NMI interrupt.

Key input

interrupt input

I

VCC1

Input for the key input interrupt.

KI0 to KI3

TA0OUT to

TA4OUT

I/O for timers A0 to A4 (TA0OUT is N-channel open

drain output).

I/O

Timer A

Timer B

TA0IN to TA4IN

ZP

I

VCC1

VCC2

Input for timers A0 to A4.

Input for Z-phase.

TB0IN to TB5IN

U, U, V, V, W, W

SD

I

Input for timers B0 to B5.

Output for the three-phase motor control timer.

Forced cutoff input.

O

I

Three-phase motor

control timer

IDU, IDV, IDW

I

Input for the position data.

Real-time clock

output

RTCOUT

O

I

VCC1

Output for the real-time clock.

PWM output

PWM0, PWM1

PMC0, PMC1

VCC1, VCC2 PWM output.

Remote control

signal receiver input

VCC1

Input for the remote control signal receiver.

CTS0 to CTS2,

I

VCC1

VCC2

VCC1

VCC2

VCC1

VCC2

VCC1

VCC2

VCC1

VCC2

VCC1

CTS5

Input pins to control data transmission.

CTS6, CTS7

RTS0 to RTS2,

O

I/O

I

RTS5

Output pins to control data reception.

Transmit/receive clock I/O.

Serial data input.

RTS6, RTS7

CLK0 to CLK2,

CLK5

Serial interface

UART0 to UART2,

UART5 to UART7

CLK6, CLK7

RXD0 to RXD2,

RXD5

RXD6, RXD7

I

TXD0 to TXD2,

TXD5

O

Serial data output. ⁽²⁾

TXD6, TXD7

CLKS1

Output for the transmit/receive clock multiple-pin

output function.

Notes:

1. Contact the oscillator manufacturer regarding the oscillation characteristics.

2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be

selected as CMOS output pins or N-channel open drain output pins.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 20 of 109

M16C/65 Group

1. Overview

Table 1.14

Pin Functions for the 128-Pin Package (3/3)

Signal Name

Pin Name

I/O Power Supply

Description

SDA0 to SDA2,

SDA5

I/O

VCC1

VCC2

VCC1

UART0 to

UART2,

UART5 to

UART7

I²C mode

Serial data I/O for I²C mode.

SDA6, SDA7

SCL0 to SCL2,

SCL5

Transmit/receive clock I/O for I²C mode.

SCL6, SCL7

CLK3, CLK4

SIN3, SIN4

I/O

I

VCC2

VCC1

Transmit/receive clock I/O.

Serial data input.

Serial interface

SI/O3, SI/O4

SOUT3, SOUT4

O

Serial data output.

SDAMM

I/O

VCC1

Serial data I/O (N-channel open drain output).

Multi-master I²C-

bus interface

SCLMM

CEC

I/O

VCC1

Transmit/receive clock I/O (N-channel open drain output).

CEC I/O (N-channel open drain output).

CEC I/O

Reference

voltage input

VREF

I

VCC1

VCC2

Reference voltage input for the A/D and D/A converters.

AN0 to AN7

Analog input for the A/D converter.

AN0_0 to AN0_7

AN2_0 to AN2_7

A/D converter

D/A converter

I

VCC1

External A/D trigger input.

ADTRG

ANEX0, ANEX1

DA0, DA1

Extended analog input for the A/D converter.

Output pin the D/A converter.

O

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

P12_0 to P12_7

P13_0 to P13_7

8-bit CMOS I/O ports. A direction register determines

whether each pin is used as an input port or an output

port. A pull-up resistor may be enabled or disabled for

input ports in 4-bit units.

I/O

VCC2

I/O ports

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_7

P9_0 to P9_7

P10_0 to P10_7

P11_0 to P11_7

8-bit I/O ports having equivalent functions to P0. However,

P7_0, P7_1, and P8_5 are N-channel open drain output

ports. No pull-up resistor is provided. P8_5 is an input port

for verifying the NMI pin level and shares a pin with NMI.

I/O

VCC1

P14_0, P14_1

I/O ports having equivalent functions to P0.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 21 of 109

M16C/65 Group

1. Overview

Table 1.15

Pin Functions for the 100-Pin Package (1/3)

Signal Name

Pin Name

I/O

Power Supply

Description

Power supply

input

VCC1,

VCC2, VSS

Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2)

and 0 V to the VSS pin.

I

-

This is the power supply for the A/D and D/A converters.

Connect the AVCC pin to VCC1, and connect the AVSS pin

to VSS.

Analog power

supply input

AVCC, AVSS

I

VCC1

Reset input

Driving this pin low resets the MCU.

RESET

Input pin to switch processor modes. After a reset, to start

operating in single-chip mode, connect the CNVSS pin to

VSS via a resistor. To start operating in microprocessor

mode, connect the pin to VCC1.

CNVSS

I

VCC1

Input pin to select the data bus of the external area. The data

bus is 16 bits when it is low, and 8 bits when it is high. This

pin must be fixed either high or low. Connect the BYTE pin to

VSS in single-chip mode.

External data bus

width select input

BYTE

I

VCC1

VCC2

Inputs or outputs data (D0 to D7) while accessing an

external area with a separate bus.

D0 to D7

I/O

Inputs or outputs data (D8 to D15) while accessing an

external area with a 16-bit separate bus.

D8 to D15

A0 to A19

I/O

O

VCC2

Outputs address bits A0 to A19.

Inputs or outputs data (D0 to D7) and outputs address bits

(A0 to A7) by timesharing, while accessing an external area

with an 8-bit multiplexed bus.

A0/D0 to

A7/D7

I/O

VCC2

Inputs or outputs data (D0 to D7) and outputs address bits

(A1 to A8) by timesharing, while accessing an external area

with a 16-bit multiplexed bus.

A1/D0 to

A8/D7

I/O

O

VCC2

Outputs chip-select signals CS0 to CS3 to specify an

external area.

CS0 to CS3

Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and

WRH can be switched with BHE and WR.

• WRL, WRH, and RD selected

Bus control pins

If the external data bus is 16 bits, data is written to an even

address in an external area when WRL is driven low. Data

is written to an odd address when WRH is driven low. Data

is read when RD is driven low.

WRL/WR

WRH/BHE

RD

O

VCC2

• WR, BHE, and RD selected

Data is written to an external area when WR is driven low.

Data in an external area is read when RD is driven low. An

odd address is accessed when BHE is driven low. Select

WR, BHE, and RD when using an 8-bit external data bus.

ALE

HOLD

HLDA

RDY

O

I

VCC2

Outputs ALE signal to latch address.

The MCU is placed in a hold state while the HOLD pin is

driven low.

O

I

In a hold state, HLDA outputs a low-level signal.

The MCU bus is placed in a wait state while the RDY pin is

driven low.

Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration

allows VCC2 to interface at a different voltage than VCC1.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 22 of 109

M16C/65 Group

1. Overview

Table 1.16

Pin Functions for the 100-Pin Package (2/3)

Signal Name

Pin Name

XIN

I/O Power Supply

Description

I/O for the main clock oscillator. Connect a ceramic

resonator or crystal between pins XIN and XOUT. ⁽¹⁾

Input an external clock to XIN pin and leave XOUT pin

open.

Main clock input

I

O

I

VCC1

Main clock output

Sub clock input

XOUT

XCIN

I/O for a sub clock oscillator. Connect a crystal between

XCIN pin and XCOUT pin. ⁽¹⁾Input an external clock to

XCIN pin and leave XCOUT pin open.

Sub clock output

BCLK output

Clock output

XCOUT

BCLK

O

VCC1

VCC2

Outputs the BCLK signal.

Outputs a clock with the same frequency as fC, f1, f8, or

f32.

CLKOUT

I

VCC1

VCC2

VCC1

INT0 to INT2

INT3 to INT7

NMI

INT interrupt input

NMI interrupt input

Input for the INT interrupt.

Input for the NMI interrupt.

Key input interrupt

input

I

VCC1

Input for the key input interrupt.

KI0 to KI3

I/O for timers A0 to A4 (TA0OUT is N-channel open drain

output).

TA0OUT to

TA4OUT

I/O

Timer A

Timer B

TA0IN to TA4IN

ZP

I

VCC1

VCC2

Input for timers A0 to A4.

Input for Z-phase.

TB0IN to TB5IN

U, U, V, V, W, W

SD

I

Input for timers B0 to B5.

Output for the three-phase motor control timer.

Forced cutoff input.

O

I

Three-phase motor

control timer

IDU, IDV, IDW

I

Input for the position data.

Real-time clock

output

RTCOUT

O

I

VCC1

Output for the real-time clock.

PWM output

PWM0, PWM1

PMC0, PMC1

VCC1, VCC2 PWM output.

Remote control

signal receiver input

VCC1

Input for the remote control signal receiver.

CTS0 to CTS2,

I

VCC1

VCC2

VCC1

CTS5

Input pins to control data transmission.

Output pins to control data reception.

CTS6, CTS7

RTS0 to RTS2,

O

RTS5

RTS6, RTS7

O

I/O

I

VCC2

VCC1

VCC2

VCC1

VCC2

VCC1

VCC2

VCC1

CLK0 to CLK2,

CLK5

Serial interface

UART0 to UART2,

UART5 to UART7

Transmit/receive clock I/O.

Serial data input.

CLK6, CLK7

RXD0 to RXD2,

RXD5

RXD6, RXD7

I

TXD0 to TXD2,

TXD5

O

Serial data output. ⁽²⁾

TXD6, TXD7

CLKS1

Output for the transmit/receive clock multiple-pin output

function.

Notes:

1. Contact the oscillator manufacturer regarding the oscillation characteristics.

2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be

selected as CMOS output pins or N-channel open drain output pins.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 23 of 109

M16C/65 Group

1. Overview

Table 1.17

Pin Functions for the 100-Pin Package (3/3)

Signal Name

Pin Name

I/O Power Supply

Description

SDA0 to SDA2,

SDA5

I/O

VCC1

VCC2

VCC1

UART0 to

UART2,

UART5 to

UART7

I²C mode

Serial data I/O for I²C mode.

SDA6, SDA7

SCL0 to SCL2,

SCL5

Transmit/receive clock I/O for I²C mode.

SCL6, SCL7

CLK3, CLK4

SIN3, SIN4

I/O

I

VCC2

VCC1

Transmit/receive clock I/O.

Serial data input.

Serial

interface

SI/O3, SI/O4

SOUT3, SOUT4

O

Serial data output.

Multi-master

I²C-bus

interface

SDAMM

I/O

VCC1

Serial data I/O (N-channel open drain output).

SCLMM

CEC

I/O

VCC1

Transmit/receive clock I/O (N-channel open drain output).

CEC I/O (N-channel open drain output).

CEC I/O

Reference

voltage input

VREF

I

VCC1

VCC2

Reference voltage input for the A/D and D/A converters.

AN0 to AN7

Analog input for the A/D converter.

AN0_0 to AN0_7

AN2_0 to AN2_7

A/D

converter

I

VCC1

External A/D trigger input.

ADTRG

ANEX0, ANEX1

Extended analog input for the A/D converter.

D/A

converter

DA0, DA1

O

VCC1

Output for the D/A converter.

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

8-bit CMOS I/O ports. A direction register determines

whether each pin is used as an input port or an output port. A

pull-up resistor may be enabled or disabled for input ports in

4-bit units.

I/O

VCC2

I/O ports

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_7

P9_0 to P9_7

P10_0 to P10_7

8-bit I/O ports having equivalent functions to P0. However,

P7_0, P7_1, and P8_5 are N-channel open drain output

ports. No pull-up resistor is provided. P8_5 is an input port for

verifying the NMI pin level and shares a pin with NMI.

I/O

VCC1

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 24 of 109

M16C/65 Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a

register bank, and there are two register banks.

b31

b15

b8b7

b0

R2

R3

R0H (high-order bits of R0)

R1H (high-order bits of R1)

R0L (low-order bits of R0)

R1L (low-order bits of R1)

R2

Data registers ⁽¹⁾

R3

A0

A1

FB

Address registers ⁽¹⁾

Frame base registers ⁽¹⁾

b19

b15

b0

INTBH

INTBL

Interrupt table register

Program counter

INTBH is the 4 high-order bits of the INTB register and

INTBL is the 16 low-order bits.

b19

b0

PC

b15

b0

USP

User stack pointer

Interrupt stack pointer

Static base register

ISP

SB

b15

b0

FLG

O

Flag register

b15

b8 b7

U

IPL

I

B

S

Z

D

C

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Note:

1. These registers compose a register bank. There are two register banks.

Figure 2.1

CPU Registers

2.1

Data Registers (R0, R1, R2, and R3)

R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can

be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data

registers.

R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers

R2R0 and R3R1, respectively.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 25 of 109

M16C/65 Group

2. Central Processing Unit (CPU)

2.2

Address Registers (A0 and A1)

A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and

logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register that is used for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.

2.5

Program Counter (PC)

The PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register used for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register that indicates the CPU state.

2.8.1

Carry Flag (C Flag)

The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.

2.8.2

Debug Flag (D Flag)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z Flag)

The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.

2.8.4

Sign Flag (S Flag)

The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes

0.

2.8.5

Register Bank Select Flag (B Flag)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.

2.8.6

Overflow Flag (O Flag)

The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.

2.8.7

Interrupt Enable Flag (I Flag)

The I flag enables maskable interrupts.

Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0

when an interrupt request is accepted.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 26 of 109

M16C/65 Group

2. Central Processing Unit (CPU)

2.8.8

Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0. USP is selected when the U flag is 1.

The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software

interrupt number 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.

If a requested interrupt has higher priority than IPL, the interrupt request is enabled.

2.8.10 Reserved Areas

Only set these bits to 0. The read value is undefined.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 27 of 109

M16C/65 Group

3. Address Space

3.1

Address Space

The M16C/65 Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to 4

MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external areas

from bank 0 to bank 7. Figure 3.1 shows the Address Space. Areas that can be accessed vary depending

on processor mode and the status of each control bit.

Memory expansion mode

00000h

SFR

00400h

Internal RAM is allocated from

address 00400h higher.

Internal RAM

Reserved area

04000h

External area

0D000h

SFR

0D800h

External area

In 4-MB mode

0E000h

10000h

Internal ROM

(data flash)

When data flash is enabled

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

When program ROM 2

is enabled

Internal ROM

(program ROM 2)

1 MB

address space

14000h

27000h

28000h

External area

Reserved area

40000h

BFFFFh

External area

Bank 0

512 KB × 8

D0000h

FFFFFh

Reserved area

Internal ROM

(program ROM 1)

Program ROM 1 is allocated from

address FFFFFh lower.

Notes:

1. Do not access reserved areas.

2. The figure above applies under the following conditions:

- The PM13 bit in the PM1 register is 0

(addresses 04000h to 0CFFFh and 80000h to CFFFFh are used as external areas)

- The IRON bit in the PRG2C register is 0

(addresses 40000h to 7FFFFh are used as an external area)

Figure 3.1

Address Space

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Page 28 of 109

M16C/65 Group

3. Address Space

3.2

Memory Map

Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to

0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.

Do not access these areas.

Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from

00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when

subroutines are called or when an interrupt request is accepted.

The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,

and program ROM 2.

The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but

can also store programs.

Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh and lower,

with the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh.

The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS

instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.

The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.

The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table

for interrupts.

Figure 3.2 shows the Memory Map.

00000h

SFR

00400h

Internal RAM

XXXXXh

Address XXXXXh

033FFh

Size

Reserved area

12 KB

20 KB

31 KB

47 KB

053FFh

0D000h

0D800h

SFR

07FFFh

External area

0BFFFh

0E000h

10000h

13000h

Internal ROM

(data flash)

On-chip debugger

monitor area

13FF0h

13FFFh

Internal ROM

(program ROM 2)

User boot code area

14000h

External area

27000h

28000h

Reserved area

Relocatable vector table

External area

256 bytes beginning with the

start address set in the INTB

register

Program ROM 1

Address YYYYYh

E0000h

Size

40000h

128 KB

Reserved area

256 KB

384 KB

512 KB

640 KB

C0000h

A0000h

FFE00h

FFFD8h

Special page vector table

Reserved area

YYYYYh

FFFFFh

80000h

60000h

40000h

FFFDCh

Internal ROM

(program ROM 1)

Fixed vector table

Address for ID code stored

OFS1 address

768 KB

FFFFFh

Notes:

1. Do not access reserved areas.

2. The figure above applies under the following conditions:

- Memory expansion mode

- The PM10 bit in the PM1 register is 1

(addresses 0E000h to 0FFFFh are used as data flash)

- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)

- The PM13 bit in the PM1 register is 1

(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)

- The IRON bit in the PRG2C register is 1

(program ROM 1 in addresses 40000h to 7FFFFh enabled)

Figure 3.2

Memory Map

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Page 29 of 109

M16C/65 Group

3. Address Space

3.3

Accessible Area in Each Mode

Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure

3.3 shows the Accessible Area in Each Mode.

In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.

In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.

Address space is expandable to 4 MB with the memory area expansion function.

In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is

expandable to 4 MB with the memory area expansion function. Allocate ROM to the fixed vector table

from FFFDCh to FFFFFh.

Single-Chip Mode

SFR

Memory Expansion Mode

Microprocessor Mode

SFR

00000h

00400h

00000h

00400h

00000h

SFR

00400h

Internal RAM

Reserved area

SFR

Reserved area

SFR

Reserved area

SFR

0D000h

0D800h

0D000h

0D800h

0E000h

0D800h

0E000h

Reserved area

External area

Internal ROM

(data flash)

Internal ROM

(data flash)

External area

10000h

14000h

10000h

Internal ROM

(program ROM 2)

Internal ROM

(program ROM 2)

14000h

27000h

28000h

External area

27000h

28000h

Reserved area

External area

Reserved area

80000h

External area

Reserved area

Internal ROM

(program ROM 1)

Internal ROM

(program ROM 1)

FFFFFh

Notes:

FFFFFh

1. Do not access reserved areas.

2. The figure above applies under the following conditions:

Single-chip mode and memory expansion mode

- The PM10 bit in the PM1 register is 1

(addresses 0E000h to 0FFFFh are used as data flash)

- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)

- The PM13 bit in the PM1 register is 1

(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)

- The IRON bit in the PRG2C register is 1

(program ROM 1 in addresses 40000h to 7FFFFh enabled)

Microprocessor mode

- The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area)

- The PRG2C0 bit is 1 (program ROM 2 disabled)

Figure 3.3

Accessible Area in Each Mode

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 30 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

4.1

SFRs

An SFR is a control register for a peripheral function. Table 4.1 to Table 4.15 list SFR information.

Table 4.1

SFR Information (1/16) ⁽¹⁾

Address

0000h

Register

Symbol

Reset Value

0001h

0002h

0003h

0000 0000b (CNVSS pin is low)

0000 0011b (CNVSS pin is high) ⁽²⁾

0004h

Processor Mode Register 0

PM0

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register

External Area Recovery Cycle Control Register

Protect Register

PM1

CM0

CM1

CSR

EWR

PRCR

DBR

CM2

0000 1000b

0100 1000b

0010 0000b

01h

XXXX XX00b

00h

Data Bank Register

00h

0X00 0010b ⁽³⁾

Oscillation Stop Detection Register

Program 2 Area Control Register

PRG2C

EWC

XXXX XX00b

00h

External Area Wait Control Expansion Register

Peripheral Clock Select Register

PCLKR

0000 0011b

Clock Prescaler Reset Flag

CPSRF

0XXX XXXXb

XX00 001Xb (hardware reset) ⁽⁴⁾

0000 1000b ⁽²⁾

Reset Source Determine Register

Voltage Detector 2 Flag Register

RSTFR

VCR1

000X 0000b ^{(2, 5)}

001X 0000b ^{(2, 6)}

00h

001Ah

Voltage Detector Operation Enable Register

VCR2

001Bh

001Ch

001Dh

001Eh

001Fh

Chip Select Expansion Control Register

PLL Control Register 0

CSE

PLC0

0X01 X010b

Processor Mode Register 2

PM2

XX00 0X01b

X: Undefined

Notes:

1.

2.

The blank areas are reserved. No access is allowed.

Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following

bits and registers: the VCR1 register, the VCR2 register, and bits PM01 and PM00 in the PM0 register.

Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.

The state of bits in the RSTFR register depends on the reset type.

This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset.

3.

4.

5.

6.

This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 31 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.2

SFR Information (2/16) ⁽¹⁾

Address

0020h

Register

Symbol

FRA0

Reset Value

XXXX XX00b

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

40 MHz On-Chip Oscillator Control Register 0

00h ⁽⁵⁾

Voltage Monitor Function Select Register

Voltage Detector 1 Level Select Register

VWCE

VD1LS

0000 1010b ⁽⁵⁾

(

2, 3)

1100 XX10b

002Ah

002Bh

Voltage Monitor 0 Control Register

VW0C

1100 XX11b ^{(2, 4)}

1000 1X10b ⁽⁶⁾

1000 XX10b ^{(2, 7)}

1000 0X10b ⁽²⁾

Voltage Monitor 1 Control Register

Voltage Monitor 2 Control Register

VW1C

VW2C

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

0042h

0043h

INT7IC

INT6IC

INT3IC

XX00 X000b

XXXX X000b

INT7 Interrupt Control Register

INT6 Interrupt Control Register

0044h

0045h

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

TB5IC

TB4IC

Timer B4 Interrupt Control Register

0046h

0047h

0048h

0049h

XXXX X000b

XX00 X000b

UART1 Bus Collision Detection Interrupt Control Register

Timer B3 Interrupt Control Register

UART0 Bus Collision Detection Interrupt Control Register

U1BCNIC

TB3IC

U0BCNIC

S4IC

INT5IC

SI/O4 Interrupt Control Register

INT5 Interrupt Control Register

S3IC

INT4IC

SI/O3 Interrupt Control Register

INT4 Interrupt Control Register

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

UART2 Bus Collision Detection Interrupt Control Register

BCNIC

DM0IC

DM1IC

KUPIC

ADIC

XXXX X000b

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

UART2 Transmit Interrupt Control Register

S2TIC

Notes:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

2.

Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following

registers or bit: the VW0C register, the VW1C2 bit in the VW1C register, and bits VW2C2 and VW2C3 in the VW2C register.

This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset

This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset.

This is the reset value after hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, or voltage monitor 2 reset (The

value does not change after oscillator detect reset, watchdog timer reset, or software reset.)

3.

4.

5.

6.

7.

This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset

This is the reset value after voltage monitor 1 reset, voltage monitor 2 reset, oscillator stop detect reset, watchdog timer reset, or software reset

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 32 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.3

SFR Information (3/16) ⁽¹⁾

Address

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

Register

Symbol

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

INT2IC

Reset Value

XXXX X000b

XX00 X000b

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer A3 Interrupt Control Register

Timer A4 Interrupt Control Register

Timer B0 Interrupt Control Register

Timer B1 Interrupt Control Register

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

DMA2 Interrupt Control Register

DM2IC

DM3IC

XXXX X000b

DMA3 Interrupt Control Register

UART5 Bus Collision Detection Interrupt Control Register

CEC1 Interrupt Control Register

U5BCNIC

CEC1IC

S5TIC

CEC2IC

S5RIC

006Bh

XXXX X000b

UART5 Transmit Interrupt Control Register

CEC2 Interrupt Control Register

006Ch

006Dh

006Eh

XXXX X000b

UART5 Receive Interrupt Control Register

UART6 Bus Collision Detection Interrupt Control Register

Real-Time Clock Periodic Interrupt Control Register

UART6 Transmit Interrupt Control Register

Real-Time Clock Compare Interrupt Control Register

UART6 Receive Interrupt Control Register

UART7 Bus Collision Detection Interrupt Control Register

Remote Control Signal Receiver 0 Interrupt Control Register

UART7 Transmit Interrupt Control Register

Remote Control Signal Receiver 1 Interrupt Control Register

UART7 Receive Interrupt Control Register

U6BCNIC

RTCTIC

S6TIC

RTCCIC

S6RIC

006Fh

0070h

0071h

XXXX X000b

U7BCNIC

PMC0IC

S7TIC

PMC1IC

S7RIC

0072h

XXXX X000b

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

I2C-bus Interface Interrupt Control Register

SCL/SDA Interrupt Control Register

IICIC

XXXX X000b

007Ch

SCLDAIC

007Dh

007Eh

007Fh

0080h to 017Fh

Note:

X: Undefined

1.

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 33 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.4

SFR Information (4/16) ⁽¹⁾

Address

Register

Symbol

SAR0

Reset Value

XXh

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

DMA2 Source Pointer

DMA2 Destination Pointer

DMA2 Transfer Counter

DMA2 Control Register

XXh

0Xh

DAR0

TCR0

XXh

0Xh

XXh

DM0CON

SAR1

0000 0X00b

XXh

0Xh

DAR1

XXh

0Xh

TCR1

XXh

DM1CON

SAR2

0000 0X00b

XXh

0Xh

DAR2

XXh

0Xh

TCR2

XXh

DM2CON

0000 0X00b

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 34 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.5

SFR Information (5/16) ⁽¹⁾

Address

Register

Symbol

SAR3

Reset Value

XXh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

DMA3 Source Pointer

DMA3 Destination Pointer

DMA3 Transfer Counter

DMA3 Control Register

XXh

0Xh

DAR3

TCR3

XXh

0Xh

XXh

DM3CON

0000 0X00b

Timer B0-1 Register

TB01

TB11

XXh

Timer B1-1 Register

XXh

Timer B2-1 Register

TB21

XXh

Pulse Period/Pulse Width Measurement Mode Function Select Register 1

PPWFS1

XXXX X000b

Timer B Count Source Select Register 0

Timer B Count Source Select Register 1

TBCS0

TBCS1

00h

X0h

Timer AB Division Control Register 0

TCKDIVC0

0000 X000b

Timer A Count Source Select Register 0

Timer A Count Source Select Register 1

Timer A Count Source Select Register 2

TACS0

TACS1

TACS2

00h

X0h

16-Bit Pulse Width Modulation Mode Function Select Register

Timer A Waveform Output Function Select Register

PWMFS

TAPOFS

0XX0 X00Xb

XXX0 0000b

Timer A Output Waveform Change Enable Register

Three-Phase Protect Control Register

TAOW

TPRC

XXX0 X00Xb

00h

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 35 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.6

SFR Information (6/16) ⁽¹⁾

Address

Register

Symbol

TB31

Reset Value

XXh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh

020Fh

Timer B3-1 Register

Timer B4-1 Register

Timer B5-1 Register

XXh

TB41

TB51

XXh

Pulse Period/Pulse Width Measurement Mode Function Select Register 2

PPWFS2

XXXX X000b

Timer B Count Source Select Register 2

Timer B Count Source Select Register 3

TBCS2

TBCS3

00h

X0h

PMC0 Function Select Register 0

PMC0 Function Select Register 1

PMC0 Function Select Register 2

PMC0 Function Select Register 3

PMC0 Status Register

PMC0CON0

PMC0CON1

PMC0CON2

PMC0CON3

PMC0STS

PMC0INT

00h

00XX 0000b

0000 00X0b

00h

PMC0 Interrupt Source Select Register

PMC0 Compare Control Register

PMC0 Compare Data Register

PMC1 Function Select Register 0

PMC1 Function Select Register 1

PMC1 Function Select Register 2

PMC1 Function Select Register 3

PMC1 Status Register

00h

PMC0CPC

PMC0CPD

PMC1CON0

PMC1CON1

PMC1CON2

PMC1CON3

PMC1STS

PMC1INT

XXX0 X000b

00h

XXX0 X000b

XXXX 0X00b

0000 00X0b

00h

X000 X00Xb

PMC1 Interrupt Source Select Register

Interrupt Source Select Register 3

Interrupt Source Select Register 2

Interrupt Source Select Register

IFSR3A

IFSR2A

IFSR

00h

Address Match Interrupt Enable Register

Address Match Interrupt Enable Register 2

AIER

XXXX XX00b

AIER2

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 36 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.7

SFR Information (7/16) ⁽¹⁾

Address

Register

Symbol

RMAD0

Reset Value

0210h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

021Fh

Address Match Interrupt Register 0

Address Match Interrupt Register 1

Address Match Interrupt Register 2

Address Match Interrupt Register 3

00h

X0h

RMAD1

RMAD2

RMAD3

00h

X0h

00h

X0h

00h

X0h

0000 0001b

(Other than user boot mode)

0010 0001b

0220h

Flash Memory Control Register 0

FMR0

(User boot mode)

00X0 XX0Xb

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

Flash Memory Control Register 1

Flash Memory Control Register 2

FMR1

FMR2

XXXX 0000b

Flash Memory Control Register 6

FMR6

XX0X XX00b

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 37 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.8

SFR Information (8/16) ⁽¹⁾

Address

0240h

Register

Symbol

Reset Value

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

024Ch

024Dh

024Eh

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

026Ch

026Dh

026Eh

026Fh

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

U0SMR4

U0SMR3

U0SMR2

U0SMR

U0MR

00h

000X 0X0Xb

X000 0000b

00h

U0BRG

U0TB

XXh

UART0 Transmit Buffer Register

XXh

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

0000 1000b

00XX 0010b

XXh

UART Transmit/Receive Control Register 2

UART Clock Select Register

UCON

X000 0000b

UCLKSEL0

X0h

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

U1SMR4

U1SMR3

U1SMR2

U1SMR

U1MR

00h

000X 0X0Xb

X000 0000b

00h

U1BRG

U1TB

XXh

UART1 Transmit Buffer Register

XXh

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

U1C0

U1C1

U1RB

0000 1000b

00XX 0010b

XXh

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

00h

000X 0X0Xb

X000 0000b

00h

U2BRG

U2TB

XXh

UART2 Transmit Buffer Register

XXh

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

U2C0

U2C1

U2RB

0000 1000b

0000 0010b

XXh

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 38 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.9

SFR Information (9/16) ⁽¹⁾

Address

Register

Symbol

S3TRR

Reset Value

XXh

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h

029Ah

029Bh

029Ch

029Dh

029Eh

029Fh

SI/O3 Transmit/Receive Register

SI/O3 Control Register

S3C

0100 0000b

XXh

SI/O3 Bit Rate Register

S3BRG

S4TRR

SI/O4 Transmit/Receive Register

XXh

SI/O4 Control Register

SI/O4 Bit Rate Register

SI/O3, 4 Control Register 2

S4C

0100 0000b

XXh

S4BRG

S34C2

00XX X0X0b

UART5 Special Mode Register 4

UART5 Special Mode Register 3

UART5 Special Mode Register 2

UART5 Special Mode Register

UART5 Transmit/Receive Mode Register

UART5 Bit Rate Register

U5SMR4

U5SMR3

U5SMR2

U5SMR

U5MR

00h

000X 0X0Xb

X000 0000b

00h

U5BRG

U5TB

XXh

UART5 Transmit Buffer Register

XXh

UART5 Transmit/Receive Control Register 0

UART5 Transmit/Receive Control Register 1

UART5 Receive Buffer Register

U5C0

U5C1

U5RB

0000 1000b

0000 0010b

XXh

UART6 Special Mode Register 4

UART6 Special Mode Register 3

UART6 Special Mode Register 2

UART6 Special Mode Register

UART6 Transmit/Receive Mode Register

UART6 Bit Rate Register

U6SMR4

U6SMR3

U6SMR2

U6SMR

U6MR

00h

000X 0X0Xb

X000 0000b

00h

U6BRG

U6TB

XXh

UART6 Transmit Buffer Register

XXh

UART6 Transmit/Receive Control Register 0

UART6 Transmit/Receive Control Register 1

UART6 Receive Buffer Register

U6C0

U6C1

U6RB

0000 1000b

0000 0010b

XXh

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 39 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.10

SFR Information (10/16) ⁽¹⁾

Address

02A0h

02A1h

02A2h

02A3h

Register

Symbol

Reset Value

02A4h

02A5h

02A6h

02A7h

02A8h

02A9h

02AAh

02ABh

02ACh

02ADh

02AEh

02AFh

02B0h

02B1h

02B2h

02B3h

02B4h

02B5h

02B6h

02B7h

02B8h

02B9h

02BAh

02BBh

02BCh

02BDh

02BEh

02BFh

02C0h to

02FFh

0300h

0301h

0302h

0303h

0304h

0305h

0306h

0307h

0308h

0309h

030Ah

030Bh

030Ch

030Dh

030Eh

030Fh

UART7 Special Mode Register 4

UART7 Special Mode Register 3

UART7 Special Mode Register 2

UART7 Special Mode Register

UART7 Transmit/Receive Mode Register

UART7 Bit Rate Register

U7SMR4

U7SMR3

U7SMR2

U7SMR

U7MR

00h

000X 0X0Xb

X000 0000b

00h

U7BRG

U7TB

XXh

UART7 Transmit Buffer Register

XXh

UART7 Transmit/Receive Control Register 0

UART7 Transmit/Receive Control Register 1

UART7 Receive Buffer Register

U7C0

U7C1

U7RB

0000 1000b

0000 0010b

XXh

I2C0 Data Shift Register

S00

XXh

I2C0 Address Register 0

I2C0 Control Register 0

S0D0

S1D0

S20

0000 000Xb

00h

I2C0 Clock Control Register

I2C0 Start/Stop Condition Control Register

I2C0 Control Register 1

00h

S2D0

S3D0

S4D0

S10

0001 1010b

0011 0000b

00h

I2C0 Control Register 2

I2C0 Status Register 0

0001 000Xb

XXXX X000b

0000 000Xb

I2C0 Status Register 1

S11

I2C0 Address Register 1

I2C0 Address Register 2

S0D1

S0D2

Timer B3/B4/B5 Count Start Flag

Timer A1-1 Register

TBSR

TA11

TA21

TA41

000X XXXXb

XXh

Timer A2-1 Register

XXh

Timer A4-1 Register

XXh

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

INVC0

INVC1

IDB0

00h

XX11 1111b

XXh

IDB1

DTT

Timer B2 Interrupt Generation Frequency Set Counter

Position-Data-Retain Function Control Register

ICTB2

PDRF

XXh

XXXX 0000b

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 40 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.11

SFR Information (11/16) ⁽¹⁾

Address

Register

Symbol

TB3

Reset Value

XXh

0310h

0311h

0312h

0313h

0314h

0315h

0316h

0317h

0318h

0319h

031Ah

031Bh

031Ch

031Dh

031Eh

031Fh

0320h

0321h

0322h

0323h

0324h

0325h

0326h

0327h

0328h

0329h

032Ah

032Bh

032Ch

032Dh

032Eh

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

Timer B3 Register

Timer B4 Register

XXh

TB4

TB5

XXh

Timer B5 Register

XXh

Port Function Control Register

PFCR

0011 1111b

Timer B3 Mode Register

Timer B4 Mode Register

Timer B5 Mode Register

TB3MR

TB4MR

TB5MR

00XX 0000b

Count Start Flag

TABSR

00h

One-Shot Start Flag

Trigger Select Register

Up/Down Flag

ONSF

TRGSR

UDF

00h

Timer A0 Register

Timer A1 Register

Timer A2 Register

Timer A3 Register

Timer A4 Register

Timer B0 Register

Timer B1 Register

Timer B2 Register

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

XXh

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

Timer A4 Mode Register

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

Timer B2 Special Mode Register

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

00h

00XX 0000b

X000 0000b

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 41 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.12

SFR Information (12/16) ⁽¹⁾

Address

Register

Symbol

RTCSEC

RTCMIN

RTCHR

Reset Value

00h

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

Real-Time Clock Second Data Register

Real-Time Clock Minute Data Register

Real-Time Clock Hour Data Register

Real-Time Clock Day Data Register

Real-Time Clock Control Register 1

Real-Time Clock Control Register 2

Real-Time Clock Count Source Select Register

X000 0000b

XX00 0000b

XXXX X000b

0000 X00Xb

X000 0000b

XXX0 0000b

RTCWK

RTCCR1

RTCCR2

RTCCSR

Real-Time Clock Second Compare Data Register

Real-Time Clock Minute Compare Data Register

Real-Time Clock Hour Compare Data Register

RTCCSEC

RTCCMIN

RTCCHR

X000 0000b

CEC Function Control Register 1

CEC Function Control Register 2

CEC Function Control Register 3

CEC Function Control Register 4

CEC Flag Register

CECC1

CECC2

CECC3

CECC4

CECFLG

CISEL

XXXX X000b

00h

XXXX 0000b

00h

CEC Interrupt Source Select Register

CEC Transmit Buffer Register 1

CEC Transmit Buffer Register 2

CEC Receive Buffer Register 1

CEC Receive Buffer Register 2

CEC Receive Follower Address Set Register 1

CEC Receive Follower Address Set Register 2

00h

CCTB1

CCTB2

CCRB1

CCRB2

CRADRI1

CRADRI2

00h

XXXX XX00b

00h

XXXX X000b

00h

Pull-Up Control Register 0

Pull-Up Control Register 1

PUR0

PUR1

00h

(2)

0000 0000b

0361h

0000 0010b

00h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

Pull-Up Control Register 2

Pull-Up Control Register 3

PUR2

PUR3

00h

Port Control Register

PCR

0000 0XX0b

XXXX X000b

NMIDF

NMI/SD Digital Filter Register

Notes:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

2.

Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows:

- 00000000b when a low-level signal is input to the CNVSS pin

- 00000010b when a high-level signal is input to the CNVSS pin

Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detect reset are as follows:

- 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode).

- 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode).

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 42 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.13

SFR Information (13/16) ⁽¹⁾

Address

Register

Symbol

PWMCON0

Reset Value

00h

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

PWM Control Register 0

PWM0 Prescaler

PWM0 Register

PWMPRE0

PWMREG0

PWMPRE1

PWMREG1

PWMCON1

00h

PWM1 Prescaler

PWM1 Register

PWM Control Register 1

(2)

Count Source Protection Mode Register

Watchdog Timer Refresh Register

Watchdog Timer Start Register

CSPR

WDTR

WDTS

WDC

00h

XXh

Watchdog Timer Control Register

00XX XXXXb

DMA2 Source Select Register

DMA3 Source Select Register

DM2SL

DM3SL

00h

DMA0 Source Select Register

DMA1 Source Select Register

DM0SL

DM1SL

00h

Notes:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

2.

When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 43 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.14

SFR Information (14/16) ⁽¹⁾

Address

03A0h

Register

Symbol

AINRST

Reset Value

XX00 XXXXb

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

Open-Circuit Detection Assist Function Register

SFR Snoop Address Register

CRC Mode Register

CRCSAR

CRCMR

XXXX XXXXb

00XX XXXXb

0XXX XXX0b

CRC Data Register

CRC Input Register

CRCD

CRCIN

XXh

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

XXXX XXXXb

0000 00XXb

A/D Register 0

A/D Register 1

AD0

AD1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

AD2

AD3

AD4

AD5

AD6

AD7

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 44 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.15

SFR Information (15/16) ⁽¹⁾

Address

03D0h

03D1h

03D2h

03D3h

Register

Symbol

Reset Value

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

0400h to

D07Fh

A/D Control Register 2

ADCON2

0000 X00Xb

A/D Control Register 0

A/D Control Register 1

D/A0 Register

ADCON0

ADCON1

DA0

0000 0XXXb

0000 X000b

00h

D/A1 Register

DA1

00h

D/A Control Register

DACON

XXXX XX00b

Port P0 Register

P0

P1

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

PD0

PD1

P2

Port P3 Register

P3

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

PD2

PD3

P4

Port P5 Register

P5

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

PD4

PD5

P6

Port P7 Register

P7

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

PD6

PD7

P8

Port P9 Register

P9

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

PD8

PD9

P10

P11

PD10

PD11

P12

P13

PD12

PD13

P14

Port P11 Register

Port P10 Direction Register

Port P11 Direction Register

Port P12 Register

Port P13 Register

Port P12 Direction Register

Port P13 Direction Register

Port P14 Register

Port P14 Direction Register

PD14

XXXX XX00b

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 45 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

Table 4.16

SFR Information (16/16) ⁽¹⁾

Address

Register

Symbol

PMC0HDPMIN

Reset Value

0000 0000b

XXXX X000b

0000 0000b

XXXX X000b

0000 0000b

00h

D080h

D081h

D082h

D083h

D084h

D085h

D086h

D087h

D088h

D089h

D08Ah

D08Bh

D08Ch

D08Dh

D08Eh

D08Fh

D090h

D091h

D092h

D093h

D094h

D095h

D096h

D097h

D098h

D099h

D09Ah

D09Bh

D09Ch

D09Dh

D09Eh

D09Fh

PMC0 Header Pattern Set Register (Min)

PMC0 Header Pattern Set Register (Max)

PMC0HDPMAX

PMC0 Data 0 Pattern Set Register (Min)

PMC0 Data 0 Pattern Set Register (Max)

PMC0 Data 1 Pattern Set Register (Min)

PMC0 Data 1 Pattern Set Register (Max)

PMC0 Measurements Register

PMC0D0PMIN

PMC0D0PMAX

PMC0D1PMIN

PMC0D1PMAX

PMC0TIM

0000 0000b

00h

PMC0 Counter Value Register

PMC0BC

00h

PMC0 Receive Data Store Register 0

PMC0 Receive Data Store Register 1

PMC0 Receive Data Store Register 2

PMC0 Receive Data Store Register 3

PMC0 Receive Data Store Register 4

PMC0 Receive Data Store Register 5

PMC0 Receive Bit Count Register

PMC0DAT0

PMC0DAT1

PMC0DAT2

PMC0DAT3

PMC0DAT4

PMC0DAT5

PMC0RBIT

00h

XX00 0000b

PMC1 Header Pattern Set Register (Min)

PMC1 Header Pattern Set Register (Max)

PMC1HDPMIN

PMC1HDPMAX

0000 0000b

XXXX X000b

0000 0000b

XXXX X000b

00h

PMC1 Data 0 Pattern Set Register (Min)

PMC1 Data 0 Pattern Set Register (Max)

PMC1 Data 1 Pattern Set Register (Min)

PMC1 Data 1 Pattern Set Register (Max)

PMC1 Measurements Register

PMC1D0PMIN

PMC1D0PMAX

PMC1D1PMIN

PMC1D1PMAX

PMC1TIM

00h

PMC1 Counter Value Register

PMC1BC

00h

Note:

1.

X: Undefined

The blank areas are reserved. No access is allowed.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 46 of 109

M16C/65 Group

4. Special Function Registers (SFRs)

4.2

4.2.1

Notes on SFRs

Register Settings

Table 4.17 lists Registers with Write-Only Bits and registers whose function differs between reading and

writing. Set these registers with immediate values. When establishing the next value by altering the

existing value, write the existing value to the RAM as well as to the register. Transfer the next value to

the register after making changes in the RAM.

Table 4.17

Registers with Write-Only Bits

Register

Symbol

WDTR

WDTS

TA0

Address

037Dh

Watchdog Timer Refresh Register

Watchdog Timer Start Register

Timer A0 Register

037Eh

0327h to 0326h

0329h to 0328h

032Bh to 032Ah

032Dh to 032Ch

032Fh to 032Eh

0303h to 0302h

0305h to 0304h

0307h to 0306h

030Ah

Timer A1 Register

TA1

Timer A2 Register

TA2

Timer A3 Register

TA3

Timer A4 Register

TA4

Timer A1-1 Register

TA11

Timer A2-1 Register

TA21

Timer A4-1 Register

TA41

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

IDB0

IDB1

030Bh

DTT

030Ch

Timer B2 Interrupt Generation Frequency Set Counter

UART0 Bit Rate Register

UART1 Bit Rate Register

UART2 Bit Rate Register

UART5 Bit Rate Register

UART6 Bit Rate Register

UART7 Bit Rate Register

UART0 Transmit Buffer Register

UART1 Transmit Buffer Register

UART2 Transmit Buffer Register

UART5 Transmit Buffer Register

UART6 Transmit Buffer Register

UART7 Transmit Buffer Register

SI/O3 Bit Rate Register

ICTB2

U0BRG

U1BRG

U2BRG

U5BRG

U6BRG

U7BRG

U0TB

U1TB

U2TB

U5TB

U6TB

U7TB

S3BRG

S4BRG

S3D0

S10

030Dh

0249h

0259h

0269h

0289h

0299h

02A9h

024Bh to 024Ah

025Bh to 025Ah

026Bh to 026Ah

028Bh to 028Ah

029Bh to 029Ah

02ABh to 02AAh

0273h

SI/O4 Bit Rate Register

0277h

I2C0 Control Register 1

02B6h

I2C0 Status Register 0

02B8h

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 47 of 109

M16C/65 Group

5. Electrical Characteristics

5.1

5.1.1

Electrical Characteristics (Common to 3 V and 5 V)

Absolute Maximum Rating

Table 5.1

Absolute Maximum Ratings

Symbol

V_CC1

Parameter

Condition

Rated Value

Unit

V

Supply voltage

V_CC1= AV_CC

−0.3 to 6.5

−0.3 to V_CC1+ 0.1 ⁽¹⁾

−0.3 to 6.5

V_CC2

AV_CC

V_REF

V_I

Supply voltage

V_CC1= AV_CC

V

Analog supply voltage

Analog reference voltage

−0.3 to V_CC1+ 0.1 ⁽¹⁾

−0.3 to V_CC1+ 0.3 ⁽¹⁾

Input voltage RESET, CNVSS, BYTE,

P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

XIN

−0.3 to V_CC2+ 0.3 ⁽¹⁾

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

V

P7_0, P7_1, P8_5

−0.3 to 6.5

−0.3 to V_CC1+ 0.3 ⁽¹⁾

V

V_O

Output voltage P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

XOUT

−0.3 to V_CC2+ 0.3 ⁽¹⁾

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

V

P7_0, P7_1, P8_5

Power consumption

−0.3 to 6.5

V

P_d

−40°C < T

≤

300

mW

opr

85°C

T_opr

Operating

temperature

When the MCU is operating

Flash program erase

−20 to 85/−40 to 85 °C

0 to 60

T_stg

Storage temperature

−65 to 150

°C

Note:

1. Maximum value is 6.5 V.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 48 of 109

M16C/65 Group

5. Electrical Characteristics

5.1.2

Recommended Operating Conditions

Table 5.2

Recommended Operating Conditions (1/3)

V_CC1= V_CC2= 2.7 to 5.5 V at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified.

Standard

Unit

Symbol

Parameter

Min.

2.7

Typ.

5.0

Max.

5.5

V_CC1

,

Supply voltage (V_CC1≥ V_CC2

)

V

V_CC2

AV_CC

V_SS

Analog supply voltage

Supply voltage

V_CC1

V

0

AV_SS

V_IH

Analog supply voltage

High input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

0.8V_CC2

0.5V_CC2

V_CC2

voltage

P12_0 to P12_7, P13_0 to P13_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(in single-chip mode)

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(data input in memory expansion and microprocessor

modes

)

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P14_0, P14_1

0.8V_CC1

V_CC1

V

XIN, RESET, CNVSS, BYTE

P7_0, P7_1, P8_5

0.8V_CC1

0

6.5

V

V_IL

Low input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

0.2V_CC2

voltage

P12_0 to P12_7, P13_0 to P13_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(in single-chip mode)

0

0.2V_CC2

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

0.16V

CC2

(data input in memory expansion and microprocessor

mode

)

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,P11_0 to P11_7,

P14_0, P14_1

0

0.2V_CC1

-40.0

V

XIN, RESET, CNVSS, BYTE

I_OH(sum)High peak

output

mA

Sum of I_OH(peak)at P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7

current

Sum of I_OH(peak)at P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P12_0 to P12_7, and P13_0 to P13_7

Sum of I_OH(peak)at P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4

-40.0

−10.0

mA

Sum of I_OH(peak)at P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P14_0 to P14_1

I_OH(peak)High peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

output

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

current

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

I_OH(avg)High

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7

−5.0

mA

average

output

current ⁽¹⁾

Note:

1. The average output current is the mean value within 100 ms.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 49 of 109

M16C/65 Group

5. Electrical Characteristics

Table 5.3

Recommended Operating Conditions (2/3)

V_CC1= V_CC2= 2.7 to 5.5 V at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified.

Symbol Parameter

I_OL(sum)Low peak Sum of I_OL(peak)at P0_0 to P0_7, P1_0 to P1_7,

Standard

Unit

Min.

Typ.

Max.

80.0

mA

output

current

P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P14_0 to P14_1

Sum of I_OL(peak)at P3_0 to P3_7, P4_0 to P4_7,

80.0

10.0

P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_5, P12_0 to P12_7, P13_0 to P13_7

I_OL(peak)Low peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

output

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

I_OL(avg)Low

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

5.0

20

mA

average

output

current ⁽¹⁾

f_(XIN)

Main clock input

V_CC1= 2.7 V to 5.5 V

2

MHz

oscillation frequency

f_(XCIN)

f_(PLL)

Sub clock oscillation frequency

32.768

50

32

kHz

PLL clock oscillation

frequency

V_CC1= 2.7 V to 5.5 V

10

2

MHz

f_(BCLK)

CPU operation clock

32

2

MHz

ms

t_SU(PLL)PLL frequency

synthesizer

V_CC1= 5.0 V

V_CC1= 3.0 V

3

ms

stabilization wait time

Note:

1. The average output current is the mean value within 100 ms.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 50 of 109

M16C/65 Group

5. Electrical Characteristics

(1)

Table 5.4

Recommended Operating Conditions (3/3)

V_CC1= 2.7 to 5.5 V, V_SS= 0 V, and T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified.

The ripple voltage must not excess V_r(VCC1)and/or dV_r(VCC1)/dt.

Standard

Typ.

Symbol

V_r(VCC1)

Parameter

Unit

Min.

Max.

0.5

Allowable ripple voltage

Vp-p

V/ms

V_CC1= 5.0 V

_CC1= 3.0 V

V_CC1= 5.0 V

_CC1= 3.0 V

0.3

V

dV_r(VCC1)/dt Ripple voltage falling gradient

V

Note:

1. The device is operationally guaranteed under these operating conditions.

V

CC1

V _r(VCC1)

Figure 5.1

Ripple Waveform

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 51 of 109

M16C/65 Group

5. Electrical Characteristics

5.1.3

A/D Conversion Characteristics

(1)

Table 5.5

A/D Conversion Characteristics (1/2)

V_CC1= AV_CC= 3.0 to 5.5 V ≥ V_CC2≥ V_REF, V_SS= AV_SS= 0 V at T_opr= -20 to 85°C/-40 to 85°C unless

otherwise specified.

Standard

Typ.

Symbol

Parameter

Measuring Condition

Unit

Min.

Max.

10

-

Resolution

Integral non-linearity error 10bit

AV_CC= V_CC1≥ V_CC2≥ V_REF

Bits

I_NL

V_CC1= AN0 to AN7 input,

±3

LSB

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

5.0 V

V_CC1

3.3 V

=

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

LSB

V_CC1

3.0 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

-

Absolute accuracy

10bit

V_CC1

5.0 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

V_CC1

3.3 V

AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

V_CC1= AN0 to AN7 input,

AN0_0 to AN0_7 input,

AN2_0 to AN2_7 input,

ANEX0, ANEX1 input

(Note 2)

3.0 V

Notes:

1. Use when AV_CC= V_CC1

.

2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and

connect them to V_SS. See Figure 5.2 “A/D Accuracy Measure Circuit”.

AN

Analog input

AN: One of the analog input pin

P0 to P14: I/O pins other than AN

P0 to P14

Figure 5.2

A/D Accuracy Measure Circuit

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5. Electrical Characteristics

(1)

Table 5.6

A/D Conversion Characteristics (2/2)

V_CC1= AV_CC= 3.0 to 5.5 V ≥ V_CC2≥ V_REF, V_SS= AV_SS= 0 V at T_opr= -20 to 85°C/-40 to 85°C unless

otherwise specified.

Symbol

φAD

Standard

Typ.

Parameter

Measuring Condition

Unit

Min.

2

Max.

25

A/D operating clock AN0 to AN7 input, 4.0 V ≤ V_CC1≤ 5.5 V

MHz

kΩ

frequency

ANEX0 to ANEX1

input

3.2 V ≤ V_CC1≤ 4.0 V

3.0 V ≤ V_CC1≤ 3.2 V

4.0 V ≤ V_CC2≤ 5.5 V

3.2 V ≤ V_CC2≤ 4.0 V

3.0 V ≤ V_CC2≤ 3.2 V

2

16

2

10

2

25

AN0_0 to AN0_7

input, AN2_0 to

AN2_7 input

2

16

2

10

-

Tolerance level impedance

Differential non-linearity error

3

(4)

D_NL

±1

±3

LSB

-

Offset error

LSB

μs

-

Gain error

t_CONV

t_SAMP

V_REF

V_IA

10-bit conversion time

Sampling time

Reference voltage

V_CC1= 5 V, φAD = 25 MHz

1.60

0.60

3.0

0

μs

V_CC1

V_REF

V

Analog input voltage ^{(2), (3)}

V

Notes:

1. Use when AV_CC= V_CC1

.

2. When V_CC1≥ V_CC2, set as below:

Analog input voltage (AN0 to AN7, ANEX0, and ANEX1) ≤ V_CC1

Analog input voltage (AN0_0 to AN0_7 and AN2_0 to AN2_7) ≤ V_CC2

.

3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.

4. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and

connect them to V_SS. See Figure 5.2 “A/D Accuracy Measure Circuit”.

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5. Electrical Characteristics

5.1.4

D/A Conversion Characteristics

Table 5.7

D/A Conversion Characteristics

V_CC1= AV_CC= V_REF= 3.0 to 5.5 V, V_SS= AV_SS= 0 V at T_opr= -20 to 85°C/-40 to 85°C unless otherwise

specified.

Standard

Typ.

Symbol

Parameter

Measuring Condition

Unit

Min.

Max.

8

-

Resolution

Bits

LSB

μs

Absolute Accuracy

Setup Time

2.5

3

t_SU

R_O

Output Resistance

5

6

8.2

1.5

kΩ

I_VREF

Reference Power Supply Input Current

See Notes 1 and 2

mA

Notes:

1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.

2. The current consumption of the A/D converter is not included. Also, the I_VREFof the D/A converter will flow even

if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).

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5. Electrical Characteristics

5.1.5

Flash Memory Electrical Characteristics

Table 5.8

CPU Clock When Operating Flash Memory (f_(BCLK))

V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified.

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

Max.

10 ⁽¹⁾

5 ⁽³⁾

35

-

CPU rewrite mode

MHz

kHz

f(SLOW_R) Slow read mode

-

Low current consumption read mode

Data flash read

fC(32.768)

16 ⁽²⁾

20 ⁽²⁾

2.7 V ≤ V_CC1≤ 3.0 V

3.0 V < V_CC1≤ 5.5 V

MHz

Notes:

1. Set the PM17 bit in the PM1 register to 1 (one wait).

2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in

the PM1 register to 1 (one wait)

3. Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as

the CPU clock source, a wait is not necessary.

Table 5.9

Flash Memory (Program ROM 1, 2) Electrical Characteristics

V_CC1= 2.7 to 5.5 V at T_opr= 0 to 60°C (option: -40°C to 85°C), unless otherwise specified.

Standard

Symbol

Parameter

Conditions

Unit

Min.

Typ.

Max.

Program and erase cycles ^{(1), (3), (4)}

Two words program time

Lock bit program time

Block erase time

1,000 ⁽²⁾

-

V_CC1= 3.3 V, T_opr= 25°C

times

μs

s

150

70

4000

3000

3.0

V

_CC1= 3.3 V, T_opr= 25°C

V

0.2

Program, erase voltage

Read voltage

2.7

0

5.5

V

5.5

V

Program, erase temperature

60

°C

μs

year

t_PS

-

Flash Memory Circuit Stabilization Wait Time

Ambient temperature = 55°C

50

Data hold time ⁽⁶⁾

20

Notes:

1. Definition of program and erase cycles:

The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n

(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word

data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be

written to the same address more than once without erasing the block (rewrite prohibited).

2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresses in turn so that as much of the block as possible is used up before performing an erase

operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase

operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least three times until the erase error does not occur.

5. Customers desiring program/erase failure rate information should contact their Renesas technical support

representative.

6. The data hold time includes time that the power supply is off or the clock is not supplied.

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5. Electrical Characteristics

Table 5.10

Flash Memory (Data Flash) Electrical Characteristics

V_CC1= 2.7 to 5.5 V at T_opr= -20 to 85°C/-40 to 85°C, unless otherwise specified.

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Program and erase cycles ^{(1), (3), (4)}

Two words program time

Lock bit program time

10,000 ⁽²⁾

-

V_CC1= 3.3 V, T_opr= 25°C

times

μs

V_CC1= 3.3 V, T_opr= 25°C

300

140

0.2

4000

3000

μs

Block erase time

3.0

5.5

85

s

V

-

Program, erase voltage

Read voltage

2.7

V

Program, erase temperature

°C

μs

−20/−40

t_PS

-

Flash Memory Circuit Stabilization Wait Time

Ambient temperature = 55 °C

50

Data hold time ⁽⁶⁾

20

year

Notes:

1. Definition of program and erase cycles

The program and erase cycles refer to the number of per-block erasures.

If the program and erase cycles are n (n = 10,000), each block can be erased n times.

For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this

counts as one program and erase cycles. Data cannot be written to the same address more than once without

erasing the block (rewrite prohibited).

2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresses in turn so that as much of the block as possible is used up before performing an erase

operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be

minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the

erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain

data on the erasure cycles of each block and limit the number of erase operations to a certain number.

4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least three times until the erase error does not occur.

5. Customers desiring program/erase failure rate information should contact their Renesas technical support

representative.

6. The data hold time includes time that the power supply is off or the clock is not supplied.

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5. Electrical Characteristics

5.1.6

Voltage Detector and Power Supply Circuit Electrical Characteristics

Table 5.11

Voltage Detector 0 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C, unless otherwise

specified.

Symbol

V_det0

Standard

Typ. Max.

Parameter

Condition

Unit

Min.

1.60

2.55

Voltage detection level Vdet0_0 ⁽¹⁾

Voltage detection level Vdet0_2 ⁽¹⁾

Voltage detector 0 response time ⁽³⁾

When V_CC1is falling.

1.90

2.85

2.20

3.15

V

-

When V_CC1falls from 5 V

to (Vdet0_0 - 0.1) V

200

μs

μA

μs

-

Voltage detector self power consumption

VC25 = 1, V_CC1= 5.0 V

1.8

t_d(E-A)

Waiting time until voltage detector operation

starts ⁽²⁾

100

Notes:

1. Select the voltage detection level with the VDSEL1 bit in the OFS1 address.

2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2

register to 0.

3. Time from when passing the V_det0until when a voltage monitor 0 reset is generated.

Table 5.12

Voltage Detector 1 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C, unless otherwise

specified.

Symbol

V_det1

Standard

Typ. Max.

Parameter

Condition

Unit

Min.

2.79

3.54

3.94

Voltage detection level Vdet1_6 ⁽¹⁾

Voltage detection level Vdet1_B ⁽¹⁾

Voltage detection level Vdet1_F ⁽¹⁾

When V_CC1is falling.

3.09

3.84

4.44

3.39

4.14

4.94

V

-

Hysteresis width when V_CC1of voltage detector

1 is rising

0.15

V

Voltage detector 1 response time ⁽³⁾

When V_CC1falls from 5 V

to (Vdet1_0 - 0.1) V

200

100

μs

μA

μs

-

Voltage detector self power consumption

VC26 = 1, V_CC1= 5.0 V

1.8

t_d(E-A)

Waiting time until voltage detector operation

starts ⁽²⁾

Notes:

1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC26 bit in the VCR2

register to 0.

3. Time from when passing the V_det1until when a voltage monitor 1 reset is generated.

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5. Electrical Characteristics

Table 5.13

Voltage Detector 2 Electrical Characteristics

The measurement condition is V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C, unless otherwise

specified.

Symbol

V_det2

Standard

Typ. Max.

Parameter

Condition

Unit

V

Min.

3.50

When V_CC1is falling

4.00

4.50

Voltage detection level Vdet2_0

-

Hysteresis width at the rising of V_CC1in voltage

detector 2

0.15

V

Voltage detector 2 response time ⁽²⁾

-

When V_CC1falls from 5

V to (Vdet2_0 - 0.1) V

200

100

μs

-

Voltage detector self power consumption

VC27 = 1, V_CC1= 5.0 V

1.8

μA

μs

Waiting time until voltage detector operation starts ⁽¹⁾

t_d(E-A)

Notes:

1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2

register to 0.

2. Time from when passing the V_det2until when a voltage monitor 2 reset is generated.

Table 5.14

Power-On Reset Circuit

The measurement condition is V_CC1= 2.0 to 5.5 V, T_opr= -20 to 85°C/ -40 to 85°C, unless otherwise

specified.

Symbol

V_por1

Standard

Typ.

Parameter

Condition

Unit

V

Min.

2.0

Max.

0.1

Voltage at which power-on reset enabled ⁽¹⁾

External power V_CC1rise gradient

t_rth

50000 mV/ms

Note:

1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address

to 0.

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5. Electrical Characteristics

(1)

V_det0

t_rth

V

External Power

CC1

Vpor1

Voltage detection 0

circuit response time

(2)

t_w(por)

Internal

reset signal

1

× 32

f_OCO-S

Notes:

1.

V_det0indicates the voltage detection level of the voltage detection 0 circuit. Refer to 7. “Voltage Detector” for

details.

2.

When using power-on reset, hold the external power V_CC1at or below V_por1 during t_w(por), and then turn it on.

t_w(por)is 30 s or more when -20°C ≤ T_opr≤ 85°C, and 3000 s or more when -40°C ≤ T_opr< -20°C.

Figure 5.3

Power-On Reset Circuit Electrical Characteristics

Power Supply Circuit Timing Characteristics

Table 5.15

The measurement condition is V_CC1= 2.7 to 5.5 V and T_opr= 25°C, unless otherwise specified.

Standard

Symbol

Parameter

Condition

Unit

Min. Typ. Max.

Internal power supply stability time when power is on ⁽¹⁾

STOP release time

t_d(P-R)

t_d(R-S)

t_d(W-S)

5

ms

μs

150

Low power mode wait mode release time

Note:

1. Waiting time until the internal power supply generator stabilizes when power is on.

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5. Electrical Characteristics

Recommended

t_d(P-R)

Internal power supply stability

time when power is on

operation voltage

V_cc1

t_d(P-R)

CPU clock

Interrupt for

t_d(R-S)

STOP release time

(a) Stop mode release

or

(b) Wait mode release

t_d(W-S)

Low power mode

wait mode release time

CPU clock

(a)

(b)

t_d(R-S)

t_d(W-S)

t_d(E-A)

Voltage detector

operation start time

VC25, VC26, VC27

Voltage detector

Stop

Operate

t_d(E-A)

Figure 5.4

Power Supply Circuit Timing Diagram

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M16C/65 Group

5. Electrical Characteristics

5.1.7

Oscillation Circuit Electrical Characteristics

Table 5.16

40 MHz On-Chip Oscillator Circuit Electrical Characteristics (1/2)

R5F36506NFA, R5F36506NFB, R5F36506DFA, R5F36506DFB, R5F3651ENFC, R5F3650ENFA,

R5F3650ENFB, R5F3651EDFC, R5F3650EDFA, R5F3650EDFB, R5F3651KNFC, R5F3650KNFA,

R5F3650KNFB, R5F3651KDFC, R5F3650KDFB, R5F3650KDFA, R5F3651MNFC, R5F3650MNFA,

R5F3650MNFB, R5F3651MDFC, R5F3650MDFA, R5F3650MDFB, R5F3651NNFC, R5F3650NNFA,

R5F3650NNFB, R5F3651NDFC, R5F3650NDFA, R5F3650NDFB

V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C, unless otherwise specified.

Standard

Symbol

f_OCO40M

Parameter

Condition

Unit

Min.

36

Typ. Max.

40 MHz on-chip oscillator frequency Average frequency in a 10 ms period

40

44

MHz

ms

tsu(f_OCO40M) Wait time until 40 MHz on-chip

oscillator stabilizes

2

Table 5.17

40 MHz On-Chip Oscillator Circuit Electrical Characteristics (2/2)

R5F3651RNFC, R5F3650RNFA, R5F3650RNFB, R5F3651RDFC, R5F3650RDFA, R5F3650RDFB,

R5F3651TNFC, R5F3650TNFA, R5F3650TNFB, R5F3651TDFC, R5F3650TDFA, R5F3650TDFB

V_CC1= 2.7 to 5.5 V, T_opr= -20 to 85°C/-40 to 85°C, unless otherwise specified.

Standard

Symbol

f_OCO40M

Parameter

Condition

Unit

Min.

36

1

Typ. Max.

40 MHz on-chip oscillator frequency Average frequency in a 10 ms period

40

44

60

2

MHz

ms

2.7 V ≤ V_CC1< 5.5 V, T_opr= 25 °C

Average frequency in a 10 ms period

tsu(f_OCO40M) Wait time until 40 MHz on-chip

oscillator stabilizes

Table 5.18

125 kHz On-Chip Oscillator Circuit Electrical Characteristics

V_CC1= 2.7 to 5.5 V, T_opr= −20 to 85°C/−40 to 85°C, unless otherwise specified.

Standard

Symbol

Parameter

Condition

Unit

Min. Typ. Max.

f_OCO-S

tsu(f_OCO-S

125 kHz on-chip oscillator frequency Average frequency in a 10 ms period

100 125 150 kHz

)

Wait time until 125 kHz on-chip

oscillator stabilizes

20 μs

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5. Electrical Characteristics

5.2

5.2.1

Electrical Characteristics (V

= V

= 5 V)

CC1

CC2

Electrical Characteristics

V

= V

= 5 V

CC1

CC2

(1)

Table 5.19

Electrical Characteristics (1)

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise specified.

Standard

Measuring

Condition

Symbol

V_OH

Parameter

Unit

V

Min.

Typ. Max.

V_CC1

High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

I

_OH= −5 mA

_OH= −200 μA

V_CC1− 2.0

V_CC2− 2.0

V_CC1− 0.3

V_CC2− 0.3

voltage

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

V_CC2

V_CC1

V_CC2

V_OH

High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

V

voltage

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

V_OH

High output voltage XOUT

HIGHPOWER

LOWPOWER

HIGHPOWER

I_OH= −1 mA

V_CC1− 2.0

V_CC1

V

I_OH= −0.5 mA

High output voltage XCOUT

With no load

applied

2.6

LOWPOWER

With no load

applied

2.2

V_OL

Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

I

_OL= 5 mA

_OL= 200 μA

2.0

V

voltage

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

2.0

Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

0.45

voltage

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

Low output voltage XOUT

HIGHPOWER

LOWPOWER

HIGHPOWER

I_OL= 1 mA

2.0

V

I_OL= 0.5 mA

2.0

Low output voltage XCOUT

With no load

applied

0

LOWPOWER

With no load

applied

0

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

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M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC1

CC2

(1)

Table 5.20

Electrical Characteristics (2)

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise specified.

Standard

Typ. Max.

2.0

Measuring

Condition

Symbol

V

Parameter

Unit

V

Min.

0.5

_T+- V_T-Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,

INT0 to INT7, NMI, ADTRG, CTS0 to CTS2,

CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7,

SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7,

TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7,

SIN3, SIN4, SD, PMC0, PMC1, SCLMM,

SDAMM, CEC

V_T+- V_T-Hysteresis RESET

0.5

2.5

V

I_IH

High input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 5 V

5.0 μA

−5.0 μA

100 kΩ

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_0, P14_1

XIN, RESET, CNVSS, BYTE

I_IL

Low input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

V_I= 0 V

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_0, P14_1

XIN, RESET, CNVSS, BYTE

R_PULLUPPull-up

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

V_I= 0 V

30

50

resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_0, P14_1

R_fXIN

V_RAM

Feedback resistance XIN

RAM retention voltage

1.5

MΩ

In stop mode

1.8

V

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 63 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Table 5.21

Electrical Characteristics (3)

R5F36506NFA, R5F36506NFB, R5F36506DFA, R5F36506DFB, R5F3651ENFC, R5F3650ENFA,

R5F3650ENFB, R5F3651EDFC, R5F3650EDFA, R5F3650EDFB

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

R_fXCINFeedback resistance

XCIN

8

MΩ

I_CC

Power supply current High-speed mode f_(BCLK)= 32 MHz

24.0

24.7

16.0

17.0

mA

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f_(BCLK)= 32 MHz, A/D conversion

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

500.0

μA

Low-power mode

f_(BCLK)= 32 kHz

In low-power mode

FMR22 = FMR23 = 1

On flash memory ⁽¹⁾

f_(BCLK)= 32 kHz

160.0

45.0

μA

In low-power mode

On RAM ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operation

20.0

11.0

6.0

μA

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity Low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

1.7

T

_opr= 25°C

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

During flash

memory program

20.0

30.0

mA

V

During flash

memory erase

f

V

Note:

1.

This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 64 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Table 5.22

Electrical Characteristics (4)

R5F3651KNFC, R5F3650KNFA, R5F3650KNFB, R5F3651KDFC, R5F3650KDFB, R5F3650KDFA,

R5F3651MNFC, R5F3650MNFA, R5F3650MNFB, R5F3651MDFC, R5F3650MDFA, R5F3650MDFB,

R5F3651NNFC, R5F3650NNFA, R5F3650NNFB, R5F3651NDFC, R5F3650NDFA, R5F3650NDFB

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 3225 MHz unless otherwise

specified.

Standard

Min. Typ. Max.

Symbol

Parameter

Measuring Condition

Unit

R_fXCINFeedback resistance

XCIN

8

MΩ

I_CC

Power supply current High-speed mode

f_(BCLK)= 32 MHz

26.0

27.0

17.0

18.0

mA

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f_(BCLK)= 32 MHz, A/D conversion

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

f_(BCLK)= 32 kHz

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

550.0

μA

Low-power mode

In low-power mode

FMR22 = FMR23 = 1

on flash memory ⁽¹⁾

f_(BCLK)= 32 kHz

170.0

45.0

μA

In low-power mode

on RAM ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operation

20.5

11.0

6.0

μA

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

f

_(BCLK)= 32 kHz (oscillation capacity low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

1.7

T

_opr= 25°C

During flash memory f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

program

During flash memory f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

erase

20.0

30.0

mA

V

_CC1= 5.0 V

V_CC1= 5.0 V

Note:

1. This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 65 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

(1)

Table 5.23

Electrical Characteristics (5)

R5F3651RNFC, R5F3650RNFA, R5F3650RNFB, R5F3651RDFC, R5F3650RDFA, R5F3650RDFB,

R5F3651TNFC, R5F3650TNFA, R5F3650TNFB, R5F3651TDFC, R5F3650TDFA, R5F3650TDFB

V_CC1= V_CC2= 4.2 to 5.5 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise specified.

Standard

Min. Typ. Max.

Symbol

Parameter

Measuring Condition

Unit

R_fXCINFeedback resistance

XCIN

15

MΩ

I_CC

Power supply current High-speed mode f_(BCLK)= 32 MHz

32.0

32.7

21.0

23.0

mA

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f_(BCLK)= 32 MHz, A/D conversion

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

750.0

μA

Low-power mode

f_(BCLK)= 32 kHz

In low-power mode

FMR22 = FMR23 = 1

on flash memory ⁽¹⁾

f_(BCLK)= 32 kHz

250.0

45.0

μA

In low-power mode

on RAM ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operation

21.0

11.0

6.0

μA

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity Low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operation

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

1.7

T

_opr= 25°C

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

_CC1= 5.0 V

During flash

memory program

20.0

30.0

mA

V

During flash

memory erase

f

V

Note:

1. This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 66 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

5.2.2

Timing Requirements (Peripheral Functions and Others)

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.2.1

Reset Input (RESET Input)

Table 5.24

Reset Input (RESET Input)

Parameter

Standard

Symbol

t_w(RSTL)

Unit

μs

Min.

10

Max.

RESET input low pulse width

RESET input

t_w(RTSL)

Figure 5.5

Reset Input (RESET Input)

5.2.2.2

External Clock Input

(1)

Table 5.25

External Clock Input (XIN Input)

Standard

Symbol

Parameter

Unit

Min.

Max.

t_c

External clock input cycle time

External clock input high pulse width

External clock input low pulse width

External clock rise time

50

20

ns

t_w(H)

t_w(L)

t_r

9

t_f

External clock fall time

Note:

1. The condition is V_CC1= V_CC2= 3.0 to 5.0 V.

XIN input

t_f

t_r

t_w(H)

t_w(L)

t_c

Figure 5.6

External Clock Input (XIN Input)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 67 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.2.3

Timer A Input

Table 5.26

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

40

Table 5.27

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.28

Timer A Input (External Trigger Input in One-Shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.29

Timer A Input (External Trigger Input in Pulse Width Modulation Mode and

Programmable Output Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

ns

t_c(TA)

t_w(TAH)

TAiIN input

t_w(TAL)

t_c(UP)

t_w(UPH)

TAiOUT input

t_w(UPL)

Figure 5.7

Timer A Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 68 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

Table 5.30

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

t_c(TA)

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

ns

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

Two-phase pulse input in event counter mode

TAiIN input

t_c(TA)

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

t_{su(TAIN-TAOUT)}

TAiOUT input

t_{su(TAOUT-TAIN)}

Figure 5.8

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 69 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.2.4

Timer B Input

Table 5.31

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

t_c(TB)

TBiIN input cycle time (counted on one edge)

ns

t_w(TBH)

t_w(TBL)

t_c(TB)

TBiIN input high pulse width (counted on one edge)

TBiIN input low pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input high pulse width (counted on both edges)

TBiIN input low pulse width (counted on both edges)

40

200

80

t_w(TBH)

t_w(TBL)

80

Table 5.32

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

Table 5.33

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

t_c(TB)

t_w(TBH)

TBiIN input

t_w(TBL)

Figure 5.9

Timer B Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 70 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.2.5

Serial Interface

Table 5.34

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

80

t_c(CK)

CLKi input cycle time

CLKi input high pulse width

CLKi input low pulse width

TXDi output delay time

TXDi hold time

ns

t_w(CKH)

t_w(CKL)

t_d(C-Q)

t_h(C-Q)

t_su(D-C)

t_h(C-D)

0

RXDi input setup time

RXDi input hold time

70

90

t_c(CK)

t _w(CKH)

CLKi

t _w(CKL)

t_h(C-Q)

TXDi

RXDi

t_d(C-Q)

t_su(D-C)

t_h(C-D)

Figure 5.10 Serial Interface

5.2.2.6

External Interrupt INTi Input

Table 5.35

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

250

Max.

t_w(INH)

t_w(INL)

INTi input high pulse width

INTi input low pulse width

ns

t_w(INL)

INTi input

t_w(INH)

Figure 5.11 External Interrupt INTi Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 71 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.3

Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)

Table 5.36

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

t

Data input access time (for setting with no wait)

Data input access time (for setting with 1 to 3 waits)

Data input access time (when accessing multiplex bus area)

Data input access time (for setting with 2φ + 3φ or more)

Data input setup time

(Note 1)

(Note 2)

(Note 3)

(Note 4)

ns

ac1(RD-DB)

t

ac2(RD-DB)

t

ac3(RD-DB)

t

ac4(RD-DB)

t

40

30

40

0

su(DB-RD)

t

RDY input setup time

su(RDY-BCLK)

t

HOLD input setup time

su(HOLD-BCLK)

t

Data input hold time

h(RD-DB)

t

RDY input hold time

0

h(BCLK-RDY)

t

HOLD input hold time

0

h(BCLK-HOLD)

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 45[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

(n + 0.5) × 10⁹

------------------------------------ – 4 5 [ns]

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

f_(BCLK)

3. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 45[ns]

n is 2 for 2 waits setting, and 3 for 3 waits setting.

f_(BCLK)

4. Calculated according to the BCLK frequency as follows:

n × 10⁹

f_(BCLK)

----------------- – 45[ns]

n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 72 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 5 V

Memory Expansion Mode and Microprocessor Mode

(Effective in wait state setting)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

t_su(RDY-BCLK)

t_h(BCLK-RDY)

(Common to wait state and no wait state settings)

BCLK

t_{su(HOLD-BCLK)}

t_h(BCLK-HOLD)

HOLD input

HLDA input

t_d(BCLK-HLDA)

P0, P1, P2,

P3, P4,

Hi−Z

P5_0 to P5_2 ⁽¹⁾

Note:

1. These pins are high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register,

and PM11 bit in PM1 register.

Measuring conditions

y V_CC1= V_CC2= 5 V

y Input timing voltage: V = 1.0 V, V = 4.0 V

IL

IH

y Output timing voltage: V = 2.5 V, V = 2.5 V

OL

OH

Figure 5.12 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 73 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

5.2.4

Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)

(V_CC1= V_CC2= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.2.4.1

In No Wait State Setting

Table 5.37

Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

25

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

25

15

25

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

−4

0

ALE signal output hold time

See

Figure 5.13

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t_d(BCLK-HLDA)

40

HLDA output delay time

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 40[ns] f_(BCLK)is 12.5 MHz or less.

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off, and does not

show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up (pull-down)

resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = −CR × ln(1−V_OL/V_CC2

)

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold time of output

low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 74 of 109

M16C/65 Group

5. Electrical Characteristics

P0

P1

P2

P3

P4

30 pF

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

Figure 5.13 Ports P0 to P14 Measurement Circuit

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 75 of 109

M16C/65 Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in no wait state setting)

V_CC1= V_CC2= 5 V

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

t_h(RD-AD)

-4ns(min.)

15ns(max.)

0ns(min.)

ALE

RD

t_h(BCLK-RD)

t_d(BCLK-RD)

0ns(min.)

25ns(max.)

t_ac1(RD-DB)

(0.5 × t -45)ns(max.)

cyc

Hi-Z

DBi

t_su(DB-RD)

40ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

15ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_d(BCLK-WR)

25ns(max.)

t_h(BCLK-WR)

0ns(min.)

WR, WRL,

WRH

t_d(BCLK-DB)

40ns(max.)

t_h(BCLK-DB)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

cyc

t_h(WR-DB)

(0.5 × t -10)ns(min.)

cyc

(0.5 × t -40)ns(min.)

1

t_cyc

=

f_(BCLK)

Measuring conditions

y V_CC1= V_CC2= 5 V

y Input timing voltage: V_IL= 0.8 V, V = 2.0 V

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.14 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 76 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

CC2

5.2.4.2

In 1 to 3 Waits Setting and When Accessing External Area

Table 5.38

Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When

Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

25

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 2)

25

15

25

40

Chip select output hold time (in relation to BCLK)

0

-4

0

t_d(BCLK-ALE)ALE signal output delay time

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

RD signal output delay time

RD signal output hold time

See

Figure 5.13

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR)⁽³⁾

t_h(WR-DB)

t

HLDA output delay time

40

d(BCLK-HLDA)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

When n = 1, f_(BCLK)is 12.5 MHz or less.

----------------------------------- – 40[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-

up (pull-down) resistance value.

Hold time of data bus is expressed in

R

C

t = −CR × ln(1 − V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 77 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 5 V

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

15ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

25ns(max.)

t_ac2(RD-DB)

RD

{(n+0.5) × t

- 45}ns(max.)

cyc

Hi-Z

DBi

t_h(RD-DB)

0ns(min.)

t_su(DB-RD)

40ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

25ns(max.)

CSi

t_cyc

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

15ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

25ns(max.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

t_h(WR-DB)

{(n-0.5) × t

- 40}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 5 V

y Input timing voltage: V_IL= 0.8 V, V = 2.0 V

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.15 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 78 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

CC2

5.2.4.3

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Table 5.39

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

(5)

Accessing External Area and Using Multiplexed Bus)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

25

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

(Note 1)

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_h(RD-CS)

25

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

0

(Note 1)

t_h(WR-CS)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

25

40

RD signal output hold time

0

WR signal output delay time

WR signal output hold time

See

Figure 5.13

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

0

(Note 2)

(Note 1)

t_h(WR-DB)

t_d(BCLK-HLDA)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(AD-ALE)

t_h(AD-ALE)

t_d(AD-RD)

40

15

HLDA output delay time

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of address

WR signal output delay from the end of address

Address output floating start time

−4

(Note 3)

(Note 4)

0

t_d(AD-WR)

0

t_dz(RD-AD)

8

Notes:

1.

2.

3.

4.

5.

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 40[ns] n is 2 for 2-wait setting, 3 for 3-wait setting.

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 25[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 15[ns]

f_(BCLK)

When using multiplex bus, set f_(BCLK)12.5 MHz or less.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 79 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 5 V

Memory Expansion Mode and Microprocessor Mode

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus)

Read timing

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

t_h(RD-CS)

t_cyc

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(AD-ALE)

t_h(ALE-AD)

(0.5 × t -25ns(min.)

cyc

(0.5 × t -15ns(min.)

cyc

ADi

/DBi

Address

Data input

Address

t_dz(RD-AD)

t_h(RD-DB)

0ns(min.)

8ns(max.)

t_su(DB-RD)

40ns(min.)

t_ac3(RD-DB)

{(n-0.5) × t -45}ns(max.)

cyc

t_d(AD-RD)

t_d(BCLK-AD)

0ns(min.)

25ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

15ns(max.)

t_h(RD-AD)

(0.5 × t -10)ns(min.)

cyc

ALE

RD

t_d(BCLK-RD)

t_h(BCLK-RD)

25ns(max.)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

t_cyc

t_h(WR-CS)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(BCLK-DB)

t_h(BCLK-DB)

0ns(min.)

40ns(max.)

ADi

/DBi

Address

Data output

t_d(DB-WR)

Address

t_h(WR-DB)

t_d(AD-ALE)

(0.5 × t -25ns(min.)

{(n-0.5) × t

- 40}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)t_h(BCLK-ALE)

t_d(AD-WR)

t_h(WR-AD)

15ns(max.)

-4ns(min.)

0ns(min.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

t_d(BCLK-WR)

0ns(min.)

25ns(max.)

WR,WRL,

WRH

n: 2 (when 2 waits)

3 (when 3 waits)

Measuring conditions

y V_CC1= V_CC2= 5 V

y Input timing voltage: V = 0.8 V, V = 2.0 V

IL

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

Figure 5.16 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 80 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

CC2

5.2.4.4

In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When

Accessing External Area

Table 5.40

Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2 φ + 3 φ, 2 φ

+ 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

25

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 2)

25

15

25

40

Chip select output hold time (in relation to BCLK)

0

-4

0

t_d(BCLK-ALE)ALE signal output delay time

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

RD signal output delay time

RD signal output hold time

See

Figure 5.13

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t

HLDA output delay time

40

d(BCLK-HLDA)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 40[ns]

n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-

up (pull-down) resistance value.

Hold time of data bus is expressed in

R

C

t = −CR × ln(1 − V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 81 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 5 V

Memory Expansion Mode and Microprocessor Mode

(in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and

when accessing external area)

Read timing

t_cyc

BCLK

t_h(BCLK-CS)

2ns(min.)

t_d(BCLK-CS)

25ns(max.)

CSi

t_d(BCLK-AD)

25ns(max.)

t_h(BCLK-AD)

2ns(min.)

ADi

BHE

t_d(BCLK-ALE)

15ns(max.)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

RD

t_d(BCLK-RD)

25ns(max.)

t_h(BCLK-RD)

0ns(min.)

t_ac4(RD-DB)

(n × t_cyc-45)ns(max.)

Hi-Z

DBi

t_su(DB-RD)

40ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

BCLK

t_cyc

t_d(BCLK-CS)

25ns(max.)

t_h(BCLK-CS)

2ns(min.)

CSi

t_h(BCLK-AD)

2ns(min.)

t_d(BCLK-AD)

25ns(max.)

ADi

BHE

t_h(WR-AD)

(0.5 × t_cyc-10)ns(min.)

t_d(BCLK-ALE)

15ns(max.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

25ns(max.)

WR, WRL

WRH

t_d(BCLK-DB)

40ns(min.)

t_h(BCLK-DB)

2ns(min.)

Hi-Z

DBi

t_h(WR-DB)

(0.5 × t_cyc-10)ns(min.)

t_d(DB-WR)

{(n-0.5) × t_cyc-40}ns(min.)

1

t_{cyc =}

f_(BCLK)

Measuring conditions

n: 3 (when 2φ + 3φ)

4 (when 2φ + 4φ or 3φ + 4φ)

5 (when 4φ + 5φ)

y V_CC1= V_CC2= 5 V

y Input timing voltage: V_IL= 0.8 V, V = 2.0 V

y Output timing voltage: V = 0.4 V, V = 2.4 V

IH

OL

OH

Figure 5.17 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 82 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 5 V

CC2

CC1

Switching Characteristics

(V_CC1= V

= 5 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

CC2

5.2.4.5

In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When

Inserting 1 to 3 Recovery Cycles and Accessing External Area

Table 5.41

Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ,

3φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing

External Area)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

Address output delay time

25

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 4)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

25

15

25

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

-4

0

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

See

Figure 5.13

RD signal output delay time

RD signal output hold time

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t_d(BCLK-HLDA)

HLDA output delay time

40

Notes:

1.

Calculated according to the BCLK frequency as follows:

n × 10⁹

f_(BCLK)

----------------- – 40[ns]

n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

2.

3.

Calculated according to the BCLK frequency as follows:

m × 10⁹

f_(BCLK)

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

------------------ – 10[ns]

This standard value shows the timing when the output is off, and does not

show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up (pull-down)

resistance value.

Hold time of data bus is expressed in

R

C

t = −CR × ln(1−V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold time of output

low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

4.

Calculated according to the BCLK frequency as follows:

m × 10⁹

f_(BCLK)

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

------------------ + 10[ns]

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 83 of 109

M16C/65 Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and when

V_CC1= V_CC2= 5 V

inserting 1 to 3 recovery cycles and accessing external area)

Read timing

t_cyc

BCLK

t_h(BCLK-CS)

2ns(min.)

t_d(BCLK-CS)

25ns(max.)

CSi

t_h(BCLK-AD)

2ns(min.)

t_d(BCLK-AD)

25ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

(m × t_cyc+0)ns(min.)

t_h(BCLK-ALE)

15ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

25ns(max.)

RD

t_ac4(RD-DB)

(n × t_cyc-45)ns(max.)

Hi-Z

DBi

t_su(DB-RD)

40ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

t_cyc

BCLK

t_h(BCLK-CS)

2ns(min.)

t_d(BCLK-CS)

25ns(max.)

CSi

t_d(BCLK-AD)

25ns(max.)

ADi

t_h(BCLK-AD)

2ns(min.)

BHE

t_d(BCLK-ALE)

15ns(max.)

t_h(WR-AD)

(m × t_cyc-10)ns(min.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

25ns(max.)

WR, WRL

WRH

t_d(BCLK-DB)

40ns(max.)

t_h(BCLK-DB)

2ns(min.)

Hi-Z

DBi

t_h(WR-DB)

(m × t_cyc-10)ns(min.)

t_d(DB-WR)

(n × t_cyc-40)ns(min.)

1

t_{cyc =}

f_(BCLK)

Measuring conditions

n: 3 (when 2φ + 3φ)

4 (when 2φ + 4φ or 3φ + 4φ)

5 (when 4φ + 5φ)

y V_CC1= V_CC2= 5 V

y Input timing voltage: V_IL= 0.8 V, V = 2.0 V

IH

y Output timing voltage: V = 0.4 V, V = 2.4 V

OL

OH

m: 1 (when 1 recovery cycle inserted )

2 (when 2 recovery cycles inserted)

3 (when 3 recovery cycles inserted)

Figure 5.18 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 84 of 109

M16C/65 Group

5. Electrical Characteristics

5.3

5.3.1

Electrical Characteristics (V

= V

= 3 V)

CC1

CC2

Electrical Characteristics

V

= V

= 3 V

CC1

CC2

(1)

Table 5.42

Electrical Characteristics (1)

V_CC1= V_CC2= 2.7 to 3.3 V, V_SS= 0 V at T_opr= -20 to 85°C/-40 to 85°C, f_(BCLK)= 32 MHz unless otherwise

specified.

Standard

Symbol

V_OH

Parameter

Measuring Condition

Unit

V

Min.

Typ. Max.

V_CC1

High

output

voltage

P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1

I_OH= −1 mA

V_CC1− 0.5

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

I

_OH= −1 mA

V_CC2− 0.5

V_CC2

V_OH

High output voltage XOUT

HIGHPOWER

LOWPOWER

I_OH= −0.1 mA

I_OH= −50 μA

V_CC1− 0.5

V_CC1

V

High output voltage XCOUT

HIGHPOWER

LOWPOWER

With no load applied

I_OL= 1 mA

2.6

2.2

0.5

V

V_OL

Lowoutput P6_0 to P6_7, P7_0 to P7_7,

voltage

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

I

_OL= 1 mA

0.5

V_OL

Low output voltage XOUT

HIGHPOWER

LOWPOWER

I_OL= 0.1 mA

0.5

V

I_OL= 50 μA

Low output voltage XCOUT

HIGHPOWER

LOWPOWER

With no load applied

0

V

0

V

_T+-V_T-Hysteresis HOLD, RDY, TA0IN to TA4IN,

0.2

1.0

TB0IN to TB5IN, INT0 to INT7, NMI,

ADTRG, CTS0 to CTS2, CTS5 to CTS7,

SCL0 to SCL2, SCL5 to SCL7,

SDA0 to SDA2, SDA5 to SDA7,

CLK0 to CLK7, TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2,

RXD5 to RXD7, SIN3, SIN4, SD, PMC0,

PMC1, SCLMM, SDAMM, CEC

V

_T+-V_T-Hysteresis RESET

0.2

1.8

4.0

V

I_IH

High input P0_0 to P0_7, P1_0 to P1_7,

V_I= 3 V

μA

current

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

XIN, RESET, CNVSS, BYTE

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 85 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

(1)

Table 5.43

Electrical Characteristics (2)

V_CC1= V_CC2= 2.7 to 3.3 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise

specified.

Standard

Symbol

I_IL

Parameter

Measuring Condition

V_I= 0 V

Unit

Min.

Typ. Max.

−4.0 μA

Low input P0_0 to P0_7, P1_0 to P1_7,

current

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

XIN, RESET, CNVSS, BYTE

R_PULLUPPull-up

P0_0 to P0_7, P1_0 to P1_7,

V_I= 0 V

50

80

150 kΩ

resistance P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_0, P14_1

R_fXIN

V_RAM

Feedback resistance XIN

RAM retention voltage

3.0

MΩ

In stop mode

1.8

V

Note:

1. When V_CC1≠ V_CC2, refer to 5 V or 3 V standard depending on the voltage.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 86 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Table 5.44

Electrical Characteristics (3)

R5F36506NFA, R5F36506NFB, R5F36506DFA, R5F36506DFB, R5F3651ENFC, R5F3650ENFA,

R5F3650ENFB, R5F3651EDFC, R5F3650EDFA, R5F3650EDFB

V_CC1= V_CC2= 2.7 to 3.3 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise

specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

R_fXCINFeedback resistance

XCIN

16

MΩ

I_CC

Power supply current High-speed mode f_(BCLK)= 32 MHz

24.0

24.7

16.0

17.0

mA

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f

_(BCLK)= 32 MHz, A/D conversion

XIN = 4 MHz (square wave), PLL multiplied by 8

125 kHz on-chip oscillator stop

f

_(BCLK)= 20 MHz

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

450.0

μA

Low-power mode f_(BCLK)= 32 MHz

160.0

40.0

μA

In low-power mode

FMR 22 = FMR23 = 1On flash memory ⁽¹⁾

f_(BCLK)= 32 MHz

In low-power mode

On RAM ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

20.0

8.0

4.0

1.6

μA

f_(BCLK)= 32 MHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

f_(BCLK)= 32 kHz (oscillation capacity Low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

T_opr= 25°C

During flash

memory program

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

20.0

30.0

mA

V_CC1= 5.0 V

During flash

memory erase

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 5.0 V

Note:

1.

This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 87 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Table 5.45

Electrical Characteristics (4)

R5F3651KNFC, R5F3650KNFA, R5F3650KNFB, R5F3651KDFC, R5F3650KDFA, R5F3650KDFB,

R5F3651MNFC, R5F3650MNFA, R5F3650MNFB, R5F3651MDFC, R5F3650MDFA, R5F3650MDFB,

R5F3651NNFC, R5F3650NNFA, R5F3650NNFB, R5F3651NDFC, R5F3650NDFA, R5F3650NDFB

V_CC1= V_CC2= 2.7 to 3.3 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise

specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

R_fXCINFeedback resistance

XCIN

16

MΩ

I_CC

Power supply current High-speed mode f_(BCLK)= 32 MHz

XIN = 4 MHz (square wave),

PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 32 MHz, A/D conversion

26.0

27.0

mA

In single-chip, mode,

the output pin are

open and other pins

are V_SS

XIN = 4 MHz (square wave),

PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 20 MHz

17.0

18.0

mA

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

f_(BCLK)= 32 MHz

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

500.0

μA

Low-power mode

In low-power mode,

FMR 22 = FMR23 = 1

on flash memory ⁽¹⁾

170.0

40.0

μA

f

_(BCLK)= 32 MHz

In low-power mode,

on RAN ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

20.0

8.0

4.0

1.6

μA

f

_(BCLK)= 32 MHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

f

_(BCLK)= 32kHz (oscillation capacity Low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

T_opr= 25°C

During flash

memory program

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

20.0

30.0

mA

V_CC1= 5.0 V

During flash

memory erase

f_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 5.0 V

Note:

1. This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 88 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Table 5.46

Electrical Characteristics (5)

R5F3651RNFC, R5F3650RNFA, R5F3650RNFB, R5F3651RDFC, R5F3650RDFB, R5F3650RDFA,

R5F3651TNFC, R5F3650TNFA, R5F3650TNFB, R5F3651TDFC, R5F3650TDFA, R5F3650TDFB

V_CC1= V_CC2= 2.7 to 3.3 V, V_SS= 0 V at T_opr= −20 to 85°C/−40 to 85°C, f_(BCLK)= 32 MHz unless otherwise specified.

Standard

Symbol

Parameter

Measuring Condition

Unit

Min.

Typ.

Max.

R_fXCINFeedback resistance

XCIN

25

MΩ

I_CC

Power supply current High-speed mode f_(BCLK)= 32 MHz

XIN = 4 MHz (square wave),

PLL multiplied by 8

125 kHz on-chip oscillator stop

32.0

32.7

mA

In single-chip, mode,

the output pin are

open and other pins

are V_SS

f_(BCLK)= 32 MHz, A/D conversion

XIN = 4 MHz (square wave),

PLL multiplied by 8

125 kHz on-chip oscillator stop

f_(BCLK)= 20 MHz

21.0

23.0

mA

XIN = 20 MHz (square wave)

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator on, no division

125 kHz on-chip oscillator stop

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on, no division

FMR22 = 1 (slow read mode)

f_(BCLK)= 32 MHz

40 MHz on-chip

oscillator mode

125 kHz on-chip

oscillator mode

750.0

μA

Low-power mode

In low-power mode,

FMR 22 = FMR23 = 1

on flash memory ⁽¹⁾

f_(BCLK)= 32 MHz

300.0

40.0

μA

In low-power mode,

on RAM ⁽¹⁾

Wait mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator on

Peripheral clock operating

T_opr= 25°C

20.0

8.0

4.0

1.6

μA

f

_(BCLK)= 32 MHz (oscillation capacity High)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

f

_(BCLK)= 32kHz (oscillation capacity Low)

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock operating

T_opr= 25°C

Stop mode

Main clock stop

40 MHz on-chip oscillator stop

125 kHz on-chip oscillator stop

Peripheral clock stop

T_opr= 25°C

During flash

memory program

f

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 5.0 V

_(BCLK)= 10 MHz, PM17 = 1 (one wait)

V_CC1= 5.0 V

20.0

30.0

mA

During flash

memory erase

f

Note:

1. This indicates the memory in which the program to be executed exists.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 89 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

5.3.2

Timing Requirements (Peripheral Functions and Others)

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.2.1

Reset Input (RESET Input)

Table 5.47

Reset Input (RESET Input)

Parameter

Standard

Symbol

t_w(RSTL)

Unit

Min.

10

Max.

RESET input low pulse width

μs

RESET input

t_w(RTSL)

Figure 5.19 Reset Input (RESET Input)

5.3.2.2

External Clock Input

(1)

Table 5.48

External Clock Input (XIN Input)

Standard

Symbol

Parameter

Unit

Min.

50

Max.

t_c

External clock input cycle time

External clock input high pulse width

External clock input low pulse width

External clock rise time

ns

t_w(H)

t_w(L)

t_r

20

9

t_f

External clock fall time

Note:

1.

The condition is V_CC1= V_CC2= 2.7 to 3.0 V.

XIN input

t_f

t_r

t_w(H)

t_w(L)

t_c

Figure 5.20 External Clock Input (XIN Input)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 90 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.2.3

Timer A Input

Table 5.49

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

60

Table 5.50

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.51

Timer A Input (External Trigger Input in One-Shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

300

150

t_c(TA)

TAiIN input cycle time

ns

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

Table 5.52

Timer A Input (External Trigger Input in Pulse Width Modulation Mode and

Programmable Output Mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t_w(TAH)

t_w(TAL)

TAiIN input high pulse width

TAiIN input low pulse width

ns

t_c(TA)

t_w(TAH)

TAiIN input

t_w(TAL)

t_c(UP)

t_w(UPH)

TAiOUT input

t_w(UPL)

Figure 5.21 Timer A Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 91 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

Table 5.53

Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2

Max.

t_c(TA)

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

μs

ns

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

500

Two-phase pulse input in event counter mode

TAiIN input

t_c(TA)

t_{su(TAIN-TAOUT)}

t_{su(TAOUT-TAIN)}

t_{su(TAIN-TAOUT)}

TAiOUT input

t_{su(TAOUT-TAIN)}

Figure 5.22 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 92 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.2.4

Timer B Input

Table 5.54

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

t_c(TB)

TBiIN input cycle time (counted on one edge)

ns

t_w(TBH)

t_w(TBL)

t_c(TB)

TBiIN input high pulse width (counted on one edge)

TBiIN input low pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input high pulse width (counted on both edges)

TBiIN input low pulse width (counted on both edges)

60

300

120

t_w(TBH)

t_w(TBL)

Table 5.55

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t_w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

Table 5.56

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t_c(TB)

TBiIN input cycle time

ns

t_w(TBH)

t^w(TBL)

TBiIN input high pulse width

TBiIN input low pulse width

t_c(TB)

t_w(TBH)

TBiIN input

t_w(TBL)

Figure 5.23 Timer B Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 93 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.2.5

Serial Interface

Table 5.57

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

160

t_c(CK)

CLKi input cycle time

CLKi input high pulse width

CLKi input low pulse width

TXDi output delay time

TXDi hold time

ns

t_w(CKH)

t_w(CKL)

t_d(C-Q)

t_h(C-Q)

t_su(D-C)

t_h(C-D)

0

RXDi input setup time

RXDi input hold time

100

90

t_c(CK)

t _w(CKH)

CLKi

t _w(CKL)

t_h(C-Q)

TXDi

RXDi

t_d(C-Q)

t_su(D-C)

t_h(C-D)

Figure 5.24 Serial Interface

5.3.2.6

External Interrupt INTi Input

Table 5.58

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

380

Max.

t_w(INH)

t_w(INL)

ns

INTi input high pulse width

INTi input low pulse width

t_w(INL)

INTi input

t_w(INH)

Figure 5.25 External Interrupt INTi Input

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 94 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

Timing Requirements

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.3

Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)

Table 5.59

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

t_ac1(RD-DB)

t_ac2(RD-DB)

t_ac3(RD-DB)

t_ac4(RD-DB)

t_su(DB-RD)

Data input access time (for setting with no wait)

Data input access time (for setting with wait)

Data input access time (when accessing multiplex bus area)

Data input access time (for setting with 2 φ + 3 φ or more)

Data input setup time

(Note 1)

(Note 2)

(Note 3)

(Note 4)

ns

50

40

50

0

t

RDY input setup time

su(RDY-BCLK)

t

HOLD input setup time

su(HOLD-BCLK)

t_h(RD-DB)

Data input hold time

t_h(BCLK-RDY)

RDY input hold time

0

t

HOLD input hold time

0

h(BCLK-HOLD)

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 60[ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

(n + 0.5) × 10⁹

------------------------------------ – 6 0 [ns] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

f_(BCLK)

3. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 60[ns] n is 2 for 2 waits setting, 3 for 3 waits setting.

f_(BCLK)

4. Calculated according to the BCLK frequency as follows:

n × 10⁹

f_(BCLK)

----------------- – 60[ns]

n is 3 for 2 φ + 3 φ, 4 for 2 φ + 4 φ, 4 for 3 φ + 4 φ, 5 for 4 φ + 5 φ,.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 95 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 3 V

Memory Expansion Mode and Microprocessor Mode

(Effective in wait state setting)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

t_su(RDY-BCLK)

t_h(BCLK-RDY)

(Common to wait state and no wait state settings)

BCLK

t_{su(HOLD-BCLK)}

t_h(BCLK-HOLD)

HOLD input

HLDA input

t_d(BCLK-HLDA)

P0, P1, P2,

P3, P4,

Hi−Z

P5_0 to P5_2 ⁽¹⁾

Note:

1. These pins are high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register,

and PM11 bit in PM1 register.

Measuring conditions

y V_CC1= V_CC2= 3 V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.26 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 96 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC2

CC1

5.3.4

Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.1

In No Wait State Setting

Table 5.60

Memory Expansion and Microprocessor Modes (in No Wait State Setting)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

30

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

30

25

30

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

−4

0

ALE signal output hold time

See

Figure 5.27

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t_d(BCLK-HLDA)

40

HLDA output delay time

Notes:

1. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 40[ns] f f_(BCLK)is 12.5 MHz or less.

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = −CR × ln(1 − V_OL/V_CC2

)

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 97 of 109

M16C/65 Group

5. Electrical Characteristics

P0

P1

P2

P3

P4

30 pF

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

Figure 5.27 Ports P0 to P14 Measurement Circuit

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 98 of 109

M16C/65 Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in no wait state setting)

V_CC1= V_CC2= 3 V

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

30ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

t_h(RD-AD)

-4ns(min.)

25ns(max.)

0ns(min.)

ALE

RD

t_h(BCLK-RD)

t_d(BCLK-RD)

0ns(min.)

30ns(max.)

t_ac1(RD-DB)

(0.5 × t -60)ns(max.)

cyc

Hi-Z

DBi

t_su(DB-RD)

50ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

30ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_h(BCLK-ALE)

t_d(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_d(BCLK-WR)

30ns(max.)

t_h(BCLK-WR)

0ns(min.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

cyc

t_h(WR-DB)

(0.5 × t -40)ns(min.) (0.5 × t -10)ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

y V_CC1= V_CC2= 3 V

y Input timing voltage: V = 0.6 V, V = 2.4 V

IL

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.28 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 99 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.2

In 1 to 3 Waits Setting and When Accessing External Area

Table 5.61

Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When

Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

30

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

t_h(WR-AD)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

30

25

30

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

-4

0

ALE signal output hold time

See

Figure 5.27

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t

40

HLDA output delay time

d(BCLK-HLDA)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n + 0.5) × 10⁹

n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.

When n = 1, f_(BCLK)is 12.5 MHz or less.

------------------------------------ – 4 0 [ns]

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3.

This standard value shows the timing when the output is

off, and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-

up (pull-down) resistance value.

R

C

Hold time of data bus is expressed in

t=−CR × ln(1−V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 100 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 3 V

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

Read timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

30ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

25ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

30ns(max.)

t_ac2(RD-DB)

{(n+0.5) × t -60}ns(max.)

RD

cyc

t_ac2(RD-DB)

{(n+0.5) × t -60}ns(max.)

cyc

Hi-Z

DBi

t_h(RD-DB)

0ns(min.)

t_su(DB-RD)

50ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

30ns(max.)

CSi

t_cyc

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

30ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

t_h(WR-AD)

25ns(max.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

30ns(max.)

WR, WRL,

WRH

t_d(BCLK-DB)

t_h(BCLK-DB)

40ns(max.)

0ns(min.)

Hi-Z

DBi

t_d(DB-WR)

t_h(WR-DB)

{(n-0.5) × t -40}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 3 V

y Input timing voltage: V_IL= 0.6 V, V = 2.4 V

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.29 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 101 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.3

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Table 5.62

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

(5)

Accessing External Area and Using Multiplexed Bus)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

t_h(BCLK-AD)

t_h(RD-AD)

Address output delay time

50

ns

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

(Note 1)

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_h(RD-CS)

50

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

0

(Note 1)

t_h(WR-CS)

t_d(BCLK-RD)

t_h(BCLK-RD)

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

40

50

RD signal output hold time

0

WR signal output delay time

WR signal output hold time

See

Figure 5.27

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

0

(Note 2)

(Note 1)

t_h(WR-DB)

t_d(BCLK-HLDA)

t_d(BCLK-ALE)

t_h(BCLK-ALE)

t_d(AD-ALE)

t_h(AD-ALE)

t_d(AD-RD)

40

25

HLDA output delay time

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of address

WR signal output delay from the end of address

Address output floating start time

−4

(Note 3)

(Note 4)

0

t_d(AD-WR)

0

t_dz(RD-AD)

8

Notes:

1.

2.

3.

4.

5.

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 50[ns]

n is 2 for 2 waits setting, 3 for 3 waits setting.

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 40[ns]

f_(BCLK)

Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 15[ns]

f_(BCLK)

When using multiplexed bus, set f_(BCLK)12.5 MHz or less.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 102 of 109

M16C/65 Group

5. Electrical Characteristics

V_CC1= V_CC2= 3 V

Memory Expansion Mode and Microprocessor Mode

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus)

Read timing

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

t_h(RD-CS)

t_cyc

50ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(AD-ALE)

t_h(ALE-AD)

(0.5 × t -40ns(min.)

cyc

(0.5 × t -15ns(min.)

cyc

ADi

/DBi

Address

Data input

Address

t_dz(RD-AD)

t_h(RD-DB)

0ns(min.)

8ns(max.)

t_su(DB-RD)

50ns(min.)

t_ac3(RD-DB)

{(n-0.5) × t -60}ns(max.)

cyc

t_d(AD-RD)

t_d(BCLK-AD)

0ns(min.)

50ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_d(BCLK-ALE)

t_h(BCLK-ALE)

-4ns(min.)

25ns(max.)

t_h(RD-AD)

(0.5 × t -10)ns(min.)

cyc

ALE

RD

t_d(BCLK-RD)

t_h(BCLK-RD)

40ns(max.)

0ns(min.)

Write timing

BCLK

t_d(BCLK-CS)

t_h(BCLK-CS)

0ns(min.)

t_cyc

t_h(WR-CS)

50ns(max.)

(0.5 × t -10)ns(min.)

cyc

CSi

t_d(BCLK-DB)

t_h(BCLK-DB)

0ns(min.)

50ns(max.)

ADi

/DBi

Address

Data output

t_d(DB-WR)

Address

t_h(WR-DB)

t_d(AD-ALE)

(0.5 × t -40ns(min.)

{(n-0.5) × t -50}ns(min.)

cyc

(0.5 × t -10)ns(min.)

cyc

t_d(BCLK-AD)

t_h(BCLK-AD)

0ns(min.)

50ns(max.)

ADi

BHE

t_d(BCLK-ALE)t_h(BCLK-ALE)

t_d(AD-WR)

t_h(WR-AD)

25ns(max.)

-4ns(min.)

0ns(min.)

(0.5 × t -10)ns(min.)

cyc

ALE

t_h(BCLK-WR)

t_d(BCLK-WR)

0ns(min.)

40ns(max.)

WR,WRL,

WRH

1

t_cyc

=

f_(BCLK)

Measuring conditions

n: 2 (when 2 waits)

3 (when 3 waits)

y V_CC1= V_CC2= 3 V

y Input timing voltage: V_IL= 0.6 V, V = 2.4 V

IH

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.30 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 103 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.4

In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When

Accessing External Area

Table 5.63

Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ,

3φ + 4φ, and 4φ + 5φ, and When Accessing External Area)

Standard

Measuring

Condition

Symbol

Parameter

Address output delay time

Unit

Min.

Max.

t_d(BCLK-AD)

30

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

t_d(BCLK-CS)

t_h(BCLK-CS)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 2)

30

25

30

40

Chip select output hold time (in relation to BCLK)

0

-4

0

t_d(BCLK-ALE)ALE signal output delay time

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

RD signal output delay time

RD signal output hold time

See

Figure 5.13

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t

HLDA output delay time

40

d(BCLK-HLDA)

Notes:

1. Calculated according to the BCLK frequency as follows:

(n – 0.5) × 10⁹

----------------------------------- – 40[ns]

n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

f_(BCLK)

2. Calculated according to the BCLK frequency as follows:

0.5 × 10⁹

--------------------- – 10[ns]

f_(BCLK)

3.

This standard value shows the timing when the output is

off, and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-

up (pull-down) resistance value.

R

C

Hold time of data bus is expressed in

t = −CR × ln(1 − V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 104 of 109

M16C/65 Group

5. Electrical Characteristics

Memory Expansion Mode, Microprocessor Mode

(in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and

when accessing external area)

V_CC1= V_CC2= 3 V

Read timing

t_cyc

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

30ns(max.)

CSi

t_d(BCLK-AD)

30ns(max.)

t_h(BCLK-AD)

0ns(min.)

ADi

BHE

t_d(BCLK-ALE)

25ns(max.)

t_h(RD-AD)

0ns(min.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

RD

t_d(BCLK-RD)

30ns(max.)

t_h(BCLK-RD)

0ns(min.)

t_ac4(RD-DB)

(n × t_cyc-60)ns(max.)

Hi-Z

DBi

t_su(DB-RD)

50ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

BCLK

t_cyc

t_d(BCLK-CS)

30ns(max.)

t_h(BCLK-CS)

0ns(min.)

CSi

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

30ns(max.)

ADi

BHE

t_h(WR-AD)

(0.5 × t_cyc-10)ns(min.)

t_d(BCLK-ALE)

25ns(max.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

30ns(max.)

WR, WRL

WRH

t_d(BCLK-DB)

40ns(min.)

t_h(BCLK-DB)

0ns(min.)

Hi-Z

DBi

t_h(WR-DB)

(0.5 × t_cyc-10)ns(min.)

t_d(DB-WR)

{(n-0.5) × t_cyc-40}ns(min.)

1

t_{cyc =}

f_(BCLK)

Measuring conditions

n: 3 (when 2φ + 3φ)

y V_CC1= V_CC2= 3 V

y Input timing voltage: V_IL= 0.6 V, V = 2.4 V

y Output timing voltage: V = 1.5 V, V = 1.5 V

4 (when 2φ + 4φ or 3φ + 4φ)

5 (when 4φ + 5φ)

IH

OL

OH

Figure 5.31 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 105 of 109

M16C/65 Group

5. Electrical Characteristics

V

= V

= 3 V

CC1

CC2

Switching Characteristics

(V_CC1= V_CC2= 3 V, V_SS= 0 V, at T_opr= -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.5

In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1

to 3 Recovery Cycles and Accessing External Area

Table 5.64

Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2φ + 3φ, 2φ +

4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External

Area)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t_d(BCLK-AD)

Address output delay time

30

ns

t_h(BCLK-AD

t_h(RD-AD

t_h(WR-AD)

)

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

0

)

(Note 4)

(Note 2)

t_d(BCLK-CS)

t_h(BCLK-CS)

t_d(BCLK-ALE)

30

25

30

40

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

0

-4

0

t_h(BCLK-ALE

t_d(BCLK-RD)

t_h(BCLK-RD)

)

ALE signal output hold time

See

Figure 5.13

RD signal output delay time

RD signal output hold time

t_d(BCLK-WR)

t_h(BCLK-WR)

t_d(BCLK-DB)

t_h(BCLK-DB)

t_d(DB-WR)

WR signal output delay time

WR signal output hold time

0

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) ⁽³⁾

Data output delay time (in relation to WR)

0

(Note 1)

(Note 2)

Data output hold time (in relation to WR) ⁽³⁾

t_h(WR-DB)

t_d(BCLK-HLDA)

HLDA output delay time

40

Notes:

1.

2.

3.

Calculated according to the BCLK frequency as follows:

n × 10⁹

f_(BCLK)

----------------- – 40[ns]

n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.

Calculated according to the BCLK frequency as follows:

m × 10⁹

f_(BCLK)

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

------------------ – 10[ns]

This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

t = −CR × ln(1 − V_OL/V_CC2

)

DBi

by a circuit of the right figure.

For example, when V_OL= 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold time

of output low level is

t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2

)

= 6.7 ns.

4.

Calculated according to the BCLK frequency as follows:

m × 10⁹

f_(BCLK)

m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and

3 when 3 recovery cycles are inserted.

------------------ + 10[ns]

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 106 of 109

M16C/65 Group

5. Electrical Characteristics

Memory Expansion Mode and Microprocessor Mode

(in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and

V_CC1= V_CC2= 3 V

when inserting 1 to 3 recovery cycles and accessing external area)

Read timing

t_cyc

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

30ns(max.)

CSi

t_h(BCLK-AD)

0ns(min.)

t_d(BCLK-AD)

30ns(max.)

ADi

BHE

t_d(BCLK-ALE)

t_h(RD-AD)

(m × t_cyc+0)ns(min.)

t_h(BCLK-ALE)

25ns(max.)

-4ns(min.)

ALE

t_h(BCLK-RD)

0ns(min.)

t_d(BCLK-RD)

30ns(max.)

RD

t_ac4(RD-DB)

(n × t_cyc-60)ns(max.)

Hi-Z

DBi

t_su(DB-RD)

50ns(min.)

t_h(RD-DB)

0ns(min.)

Write timing

t_cyc

BCLK

t_h(BCLK-CS)

0ns(min.)

t_d(BCLK-CS)

30ns(max.)

CSi

t_d(BCLK-AD)

30ns(max.)

ADi

t_h(BCLK-AD)

0ns(min.)

BHE

t_d(BCLK-ALE)

25ns(max.)

t_h(WR-AD)

(m × t_cyc-10)ns(min.)

t_h(BCLK-ALE)

-4ns(min.)

ALE

t_h(BCLK-WR)

0ns(min.)

t_d(BCLK-WR)

30ns(max.)

WR, WRL

WRH

t_d(BCLK-DB)

40ns(max.)

t_h(BCLK-DB)

0ns(min.)

Hi-Z

DBi

t_h(WR-DB)

(m × t_cyc-10)ns(min.)

t_d(DB-WR)

(n × t_cyc-40)ns(min.)

1

t_{cyc =}

f_(BCLK)

n: 3 (when 2φ + 3φ)

4 (when 2φ + 4φ or 3φ + 4φ)

5 (when 4φ + 5φ)

Measuring conditions

y V_CC1= V_CC2= 3 V

y Input timing voltage: V_IL= 0.6 V, V = 2.4 V

IH

m: 1 (when 1 recovery cycle inserted )

2 (when 2 recovery cycles inserted)

3 (when 3 recovery cycles inserted)

y Output timing voltage: V = 1.5 V, V = 1.5 V

OL

OH

Figure 5.32 Timing Diagram

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 107 of 109

M16C/65 Group

Appendix 1. Package Dimensions

The information on the latest package dimensions or packaging may be obtained from “Packages“ on the

Renesas Technology Website.

JEITA Package Code

RENESAS Code

PLQP0128KB-A

Previous Code

128P6Q-A

MASS[Typ.]

0.9g

P-LQFP128-14x20-0.50

H_D

*1

D

102

65

103

64

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

bp

b₁

Dimension in Millimeters

Reference

Terminal cross section

Symbol

Min Nom Max

D

E

A₂

H_D

H_E

A

19.9 20.0 20.1

13.9 14.0 14.1

1.4

21.8 22.0 22.2

15.8 16.0 16.2

1.7

128

39

1

38

Z_D

Index mark

A₁

b_p

b₁

c

0.2

0.125

0.05

F

0.17 0.22 0.27

0.20

0.145

0.125

0.09

0.20

c₁

L

0°

8°

L₁

*3

y

b_p

e

x

y

0.5

x

DetailF

0.10

Z_D

Z_E

L

0.75

0.5

0.35

0.65

L₁

1.0

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 108 of 109

M16C/65 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

PRQP0100JD-B

Previous Code

100P6F-A

MASS[Typ.]

1.8g

P-QFP100-14x20-0.65

H_D

*1

D

80

51

81

50

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Dimension in Millimeters

Reference

Symbol

Min Nom Max

100

D

E

A₂

H_D

H_E

A

19.8 20.0 20.2

13.8 14.0 14.2

2.8

22.5 22.8 23.1

16.5 16.8 17.1

3.05

31

1

30

Z_D

Index mark

F

A₁

b_p

c

0.1 0.2

0.3 0.4

0

0.25

0.2

10°

0.13 0.15

0°

L

*3

e

b_p

y

x

Detail F

e

x

y

0.65

0.13

0.10

Z_D

Z_E

L

0.575

0.825

0.4 0.6 0.8

JEITA Package Code

RENESAS Code

PLQP0100KB-A

Previous Code

MASS[Typ.]

0.6g

P-LQFP100-14x14-0.50

100P6Q-A / FP-100U / FP-100UV

H_D

*1

D

51

75

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

76

50

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

A₂

H_D

H_E

A

13.9 14.0 14.1

1.4

15.8 16.0 16.2

1.7

Terminal cross section

100

26

A₁

b_p

b₁

c

0.1

0.05

0.15

1

25

Index mark

0.15 0.20 0.25

0.18

Z_D

F

0.145

0.09

0.20

c₁

0.125

0°

8°

e

0.5

y

*3

x

y

L

0.08

b_p

e

x

L₁

Z_D

Z_E

L

1.0

0.5

1.0

Detail F

0.35

0.65

L₁

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 109 of 109

REVISION HISTORY

M16C/65 Group Datasheet

Description

Summary

Rev.

Date

Page

-

1.00 Feb 02, 2009

1.10 Sep 24, 2009

First Edition issued.

3

Table 1.2 Specifications for the 128-Pin Package (2/2) partially modified

Table 1.4 Specifications for the 100-Pin Package (2/2) partially modified

Table 1.5 Product List (1/2) partially modified

5

6

7

Table 1.6 Product List (2/2) partially modified

8

Figure 1.2 Marking Diagram (Top View) partially modified

Figure 3.2 Memory Map 13800h → 13000h

29

32

48

49

50

51

52

53

Table 4.2 “SFR Information (2/16)”notes partially modified

Table 5.1 Absolute Maximum Ratings partially modified

Table 5.2 Recommended Operating Conditions (1/3) partially modified

Table 5.3 Recommended Operating Conditions (2/3) partially modified

Table 5.4 Recommended Operating Conditions (3/3) added

Figure 5.1 Ripple Waveform added

Table 5.5 A/D Conversion Characteristics (1/2) partially modified

Figure 5.2 A/D Accuracy Measure Circuit added

Table 5.6 A/D Conversion Characteristics (2/2) partially modified

Table 5.8 CPU Clock When Operating Flash Memory (f

modified

) partially

(BCLK)

55

56

Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics

partially modified

Table 5.10 Flash Memory (Data Flash) Electrical Characteristics notes

modified

57

58

Table 5.11 Voltage Detector 0 Electrical Characteristics partially modified

Table 5.12 Voltage Detector 1 Electrical Characteristics partially modified

Table 5.13 Voltage Detector 2 Electrical Characteristics partially modified

Table 5.14 Power-On Reset Circuit partially modified

Figure 5.3 Power-On Reset Circuit Electrical Characteristics 0.1 V →

V^por1

59

61

Table 5.16 40 MHz On-Chip Oscillator Circuit Electrical Characteristics

(1/2) partially modified

Table 5.17 40 MHz On-Chip Oscillator Circuit Electrical Characteristics

(2/2) added

Table 5.18 125 kHz On-Chip Oscillator Circuit Electrical Characteristics

partially modified

63

64

65

66

67

85

87

Table 5.20 Electrical Characteristics (2) partially modified

Table 5.21 Electrical Characteristics (3) partially modified

Table 5.22 Electrical Characteristics (4) partially modified

Table 5.23 Electrical Characteristics (5) partially modified

Table 5.24 Reset Input (RESET Input) partially modified

Table 5.42 Electrical Characteristics (1) partially modified

Table 5.44 Electrical Characteristics (3) partially modified

A - 1

REVISION HISTORY

M16C/65 Group Datasheet

Description

Rev.

Date

Page

88

Summary

Table 5.45 Electrical Characteristics (4) partially modified

Table 5.46 Electrical Characteristics (5) partially modified

Table 5.47 Reset Input (RESET Input) partially modified

89

90

All trademarks and registered trademarks are the property of their respective owners.

IEBus is a registered trademark of NEC Electronics Corporation.

HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing,

LLC.

A - 2

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Notes:

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes

warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property

rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,

but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass

destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws

and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this

document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,

please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be

disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a

result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability

of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular

application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications

or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

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Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898

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7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2377-3473

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399

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1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

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Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon .7.2


型号：	R5F36506DFA
厂家：	RENESAS TECHNOLOGY CORP
描述：	RENESAS MCU 瑞萨MCU
文件：	总112页 (文件大小：988K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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