R5F523E6AGNF_技术文档

Datasheet

R01DS0330EJ0100

Rev.1.00

RX23E-A Group

Renesas MCUs

Aug 30, 2019

32-MHz, 32-bit RX MCUs with up to 256-KB flash memory,

2 low-noise and low-drift 24-bit delta-sigma A/D converters,

rail-to-rail programmable gain instrumentation amplifiers,

a low-drift voltage reference, and on-chip excitation current sources

Features

■ 32-bit RXv2 CPU core

 Max. operating frequency: 32 MHz

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

Capable of 64 DMIPS in operation at 32 MHz

 Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-

subtract instructions supported

 Built-in FPU: 32-bit single-precision floating point (compliant to

IEEE754)

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

PWQN0040KC-A 6 × 6 mm, 0.5 mm pitch

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions, ultra-compact code

 On-chip debugging circuit

■ Up to 12 extended-function timers

 Memory protection unit (MPU) supported

 16-bit MTU: input capture, output compare, complementary PWM

output, phase counting mode (six channels)

 8-bit TMR (four channels)

■ Low power design and architecture

 Operation from a single 1.8-V to 5.5-V supply

 Three low power consumption modes

 16-bit compare-match timers (two channels)

 Low power timer (LPT) that operates during the software standby state

■ Analog functions

 Two 24-bit delta-sigma A/D converters

 A/D converter with up to 23-bit effective resolution (gain = 1, output

data rate = 7.6 SPS)

■ On-chip flash memory for code

 Read cycle of 31.25 ns in 32-MHz operation

 No waiting time when the CPU is reading at full speed

 128-Kbyte to 256-Kbyte capacities

 On-board or off-board user programming

 Programmable at 1.8 V

 For instructions and operands

■ On-chip data flash memory

 High-precision programmable gain instrumentation amplifier,

30 nV

(gain = 128, output data rate = 7.6 SPS)

RMS

 Rail-to-rail programmable gain instrumentation amplifier

(gain = 1 to 128)

 Two operating modes and programmable data rates,

Normal mode: Output data rate of 7.6 SPS to 15625 SPS,

Low power mode: Output data rate of 1.9 SPS to 3906 SPS

 Offset drift 10 nV/°C (gain = 128)

 Gain drift 1 ppm/°C (gain = 1 (PGA), gain = 2 to 128)

 Up to six differential inputs, 11 single-ended inputs

 Fourth-order sinc filter

 8 Kbytes (1,000,000 program/erase cycles (typ.))

 BGO (Background Operation)

■ On-chip SRAM, no wait states

 16- to 32-Kbyte size capacities

■ Data transfer functions

 DMAC: Incorporates four channels

 DTC: Four transfer modes

■ ELC

 Module operation can be initiated by event signals without using

interrupts.

 Linked operation between modules is possible while the CPU is

sleeping.

 Simultaneous 50 Hz/60 Hz rejection (output data rate = 10, 54 SPS)

 Offset error and gain error calibration

 Inter-unit A/D conversion synchronized start

 Delta-sigma A/D input disconnect detection assist

 Delta-sigma A/D reference voltage external input

 Voltage reference

output voltage: 2.5 V ±0.1%,

temperature drift: 4 ppm/°C, output current: ±10 mA

 Excitation current sources: Up to four,

Output current: 50 μA to 1000 μA, current matching: ±0.2%, drift

matching: 5 ppm/°C

 Bias voltage generator

output voltage: (AVCC0 + AVSS0)/2

■ Reset and supply management

 Seven types of reset, including the power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 Main clock oscillator frequency: 1 MHz to 20 MHz

 External clock input frequency: Up to 20 MHz

 PLL circuit input: 4 MHz to 8 MHz

 On-chip low- and high-speed oscillators, dedicated on-chip low-speed

oscillator for the IWDT

 Temperature sensor: Accuracy ±5°C

 Low-side switch: 10 Ω on-resistance

 Low power-supply-voltage detectors

 Delta-sigma A/D input voltage fault detectors

 Delta-sigma A/D reference voltage fault detectors and disconnect

detectors

 Clock frequency accuracy measurement circuit (CAC)

 Excitation current source disconnect detectors

■ Independent watchdog timer

 15-kHz on-chip oscillator produces a dedicated clock signal to drive

■ 12-bit A/D converter

 Capable of conversion within 1.4 μs

 Six channels

 Sampling time can be set for each channel

 Self-diagnostic function and analog input disconnect detection

assistance function

IWDT operation.

■ Useful functions for IEC60730 compliance

 Self-diagnostic and disconnect detection assistance functions for the A/

D converter, clock frequency accuracy measurement circuit,

independent watchdog timer, RAM test assistance functions using the

DOC, etc.

■ General I/O ports

 5-V tolerant, open drain, input pull-up, switching of driving capacity

■ MPC

 Input/output functions selectable from multiple pins

■ Operating temperature range

 –40°C to +85°C

■ Up to eight communication functions

 CAN (one channel) compliant to ISO11898-1:

Transfer at up to 1 Mbps

 –40°C to +105°C

■ Applications

 General industrial and consumer equipment

 SCI with many useful functions (up to four channels),

asynchronous mode, clock synchronous mode, smart card interface,

reduction of errors in communications using the bit rate modulation

function

2

 I C bus interface: Transfer at up to 400 kbps, capable of SMBus

operation (one channel)

 RSPI (one channel): Transfer at up to 16 Mbps

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Page 1 of 98

RX23E-A Group

1. Overview

1.

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1

Outline of Specifications (1/4)

Classification Module/Function

Description

CPU

 Maximum operating frequency: 32 MHz

 32-bit RX CPU (RX v2)

 Minimum instruction execution time: One instruction per clock cycle

 Address space: 4-Gbyte linear

 Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75 (variable-length instruction format)

 Floating-point instructions: 11

 DSP instructions: 23

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

 On-chip divider: 32-bit ÷ 32-bit → 32 bits

 Barrel shifter: 32 bits

 Memory protection unit (MPU)

FPU

 Single precision (32-bit) floating point

 Data types and exceptions in conformance with the IEEE754 standard

Memory

ROM

 Capacity: 128/256 Kbytes

 32 MHz: No-wait access

 Programming/erasing method:

Serial programming (asynchronous serial communication), self-programming

RAM

 Capacity: 16/32 Kbytes

 32 MHz, no-wait memory access

E2 DataFlash

 Capacity: 8 Kbytes

 Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode

Single-chip mode

Clock

Clock generation circuit  Main clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, PLL

frequency synthesizer, and IWDT-dedicated on-chip oscillator

 Oscillation stop detection: Available

 Clock frequency accuracy measurement circuit (CAC)

 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and

FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the

system clock (ICLK): 32 MHz (at max.)

MTU2a runs in synchronization with the PCLKA: 32 MHz (at max.)

The ADCLK for the S12AD runs in synchronization with the PCLKD: 32 MHz (at max.)

Peripheral modules other than MTU2a and S12AD run in synchronization with the

PCLKB: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

Resets

RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer

reset, and software reset

Voltage

Voltage detection circuit  When the voltage on VCC falls below the voltage detection level, an internal reset or

detection

(LVDAb)

internal interrupt is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

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RX23E-A Group

1. Overview

Table 1.1

Outline of Specifications (2/4)

Classification Module/Function

Description

Low power

Low power consumption  Module stop function

consumption

functions

 Three low power consumption modes

Sleep mode, deep sleep mode, and software standby mode

 Low power timer that operates during the software standby state

Function for lower

operating power

consumption

 Operating power control modes

High-speed operating mode and middle-speed operating mode

Interrupt

DMA

Interrupt controller

(ICUb)

 Interrupt vectors: 256

 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)

 Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage

monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)

 16 levels specifiable for the order of priority

DMA controller

(DMACA)

 4 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

Data transfer controller

(DTCa)

 Transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Interrupts

 Chain transfer function

I/O ports

General I/O ports

48-pin/40-pin

I/O: 20/16

 Input: 1/1

Pull-up resistors: 20/16

 Open-drain outputs: 20/16

 5-V tolerance: 2/2

Event link controller (ELC)

 Event signals of 56 types can be directly connected to the module

 Operations of timer modules are selectable at event input

 Capable of event link operation for port B

Multi-function pin controller (MPC)

Capable of selecting the input/output function from multiple pins

Timers

Multi-function timer

 (16 bits × 6 channels) × 1 unit

pulse unit 2 (MTU2a)

 Up to 16 pulse-input/output lines and three pulse-input lines are available based on the

six 16-bit timer channels

 Select from among eight or seven counter-input clock signals for each channel (PCLK/1,

PCLK/4, PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,

MTCLKD) other than channel 5, for which only four signals are available.

 Input capture function

 21 output compare/input capture registers

 Pulse output mode

PWM/complementary PWM/reset synchronous PWM

 Phase-counting mode

 Capable of generating conversion start triggers for the A/D converter

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

Compare match timer

(CMT)

 (16 bits × 2 channels) × 1 unit

 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Count clock: Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 1, 16, 32, 64, 128, or 256

Low power timer (LPT)

8-bit timer (TMR)

 16 bits × 1 channel

 Clock source: Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 2, 4, 8, 16, or 32

 (8 bits × 2 channels) × 2 units

 Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and

PCLK/8192) and an external clock can be selected

 Pulse output and PWM output with any duty cycle are available

 Two channels can be cascaded and used as a 16-bit timer

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RX23E-A Group

1. Overview

Table 1.1

Outline of Specifications (3/4)

Classification Module/Function

Description

Communication Serial communications

 4 channels (channel 1, 5, 6: SCIg, channel 12: SCIh)

functions

interfaces (SCIg, SCIh)  SCIg

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Start-bit detection: Level or edge detection is selectable.

Simple I²C

Simple SPI

9-bit transfer mode

Bit rate modulation

Event linking by the ELC (only on channel 5)

 SCIh (The following functions are added to SCIg)

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

I²C bus interface

(RIICa)

 1 channel

 Communications formats: I²C bus format/SMBus format

 Master mode or slave mode selectable

 Supports fast mode

Serial peripheral

interface (RSPIb)

 1 channel

 Transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) enables serial transfer through SPI operation (four lines) or

clock-synchronous operation (three lines)

 Capable of handling serial transfer as a master or slave

 Data formats

 Choice of LSB-first or MSB-first transfer

The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20,

24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

 Double buffers for both transmission and reception

CAN module (RSCAN)

 1 channel

 Compliance with the ISO11898-1 specification (standard frame and extended frame)

 16 Message boxes

24-bit delta-sigma A/D converter (DSAD)  24 bits (6 channels × 2 units)

 Type of A/D conversion: delta-sigma

 Post filter: Fourth-order sinc filter

 24-bit resolution

 Input types: Differential, pseudo-differential, or single-ended

 Operating modes

Normal mode/low-power mode

 Modulator clock: 500 kHz (typ.; 125 kHz in low-power mode)

 Oversampling ratio: 32 to 65536 (only multiples of 16)

 Includes a programmable gain instrumentation amplifier (PGA)

Gain settings: ×1, ×2, ×4, ×8, ×16, ×32, ×64, ×128

PGA bypass function: with or without an analog input buffer

 Configuration settings per channel

 Conditions for starting A/D conversion:

software trigger or ELC

 Disconnect detection assist

 Selectable reference voltage

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RX23E-A Group

1. Overview

Table 1.1

Outline of Specifications (4/4)

Classification Module/Function

Description

Analog front end (AFE)

 Voltage reference (VREF)

Output voltage: 2.5V

 Output from bias voltage source (VBIAS)

Output voltage: (AVCC0 + AVSS0)/2

 Internal temperature sensor (TEMPS)

 Excitation current sources (IEXC)

Two channels (up to 1000 μA) or four channels (up to 500 μA)

Output current settings: 50 μA, 100 μA, 250 μA, 500 μA, 750 μA, 1000 μA

 Analog multiplexer (AMUX)

Select from among external pins, bias voltage sources, internal temperature sensor, or

excitation current sources

 Low-side switch (LSW)

On-resistance: 10 Ω (max.)

Allowable current: 30 mA (max.)

 Voltage detector (VDET)

Voltage monitoring of AVCC0

Detection of abnormal voltages at analog inputs

Detection of abnormal reference voltages and assistance in detecting disconnection

Assistance in detecting disconnection for excitation current source output

12-bit A/D converter (S12ADE)

 12 bits (6 channels × 1 unit)

 12-bit resolution

 Minimum conversion time: 1.4 µs per channel when the ADCLK is operating at 32 MHz

 Operating modes

Scan mode (single scan mode, continuous scan mode, and group scan mode)

Group A priority control (only for group scan mode)

 Sampling variable

Sampling time can be set up for each channel.

 Self-diagnostic function

 Double trigger mode (A/D conversion data duplicated)

 Detection of analog input disconnection

 A/D conversion start conditions

A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC

 Event linking by the ELC

CRC calculator (CRC)

 CRC code generation for arbitrary amounts of data in 8-bit units

 Select any of three generating polynomials:

X⁸+ X²+ X + 1, X¹⁶+ X¹⁵+ X²+ 1, or X¹⁶+ X¹²+ X⁵+ 1

 Generation of CRC codes for use with LSB-first or MSB-first communications is

selectable.

Data operation circuit (DOC)

Comparison, addition, and subtraction of 16-bit data

Power supply voltages/Operating

frequencies

VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 5.5 V: 32 MHz

AVCC0 = 2.7 to 5.5 V (1.8 to 5.5 V when only S12AD is operating)

Operating temperature range

Packages

D version: –40 to +85°C, G version: –40 to +105°C

48-pin LFQFP (PLQP0048KB-B) 7 × 7 mm, 0.5 mm pitch

40-pin HWQFN (PWQN0040KC-A) 6 × 6 mm, 0.5 mm pitch

Debugging interface

One-wire type FINE interface

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RX23E-A Group

1. Overview

Table 1.2

Comparison of Functions for Different Packages

RX23E-A Group

48 Pins

Module/Functions

Interrupts

40 Pins

NMI, IRQ0 to IRQ7

4 channels (DMAC0 to DMAC3)

Available

External interrupts

DMA

DMA controller

Data transfer controller

Multi-function timer pulse unit 2

Port output enable 2

8-bit timer

Timers

6 channels (MTU0 to MTU5)

POE0# to POE3#, POE8#

2 channels × 2 units

2 channels × 1 unit

1 channel

Compare match timer

Low power timer

Independent watchdog timer

Available

Communication

functions

Serial communications interfaces

(SCIg)

3 channels

(SCI1, 5, 6)

2 channels

(SCI1, 5)

Serial communications interfaces

(SCIh)

1 channel (SCI12)

I²C bus interface

CAN module

1 channel

Serial peripheral interface

1 channel

24-bit delta-sigma A/D converter

6 channels × 2 units

Available

Analog front end

Voltage reference

Excitation current sources

Analog multiplexer

Temperature sensor

Voltage detector

Available

12-bit A/D converter

6 channels

4 channels

(including high-precision channels)

(6 channels)

(4 channels)

CRC calculator

Available

Event link controller

Packages

48-pin LFQFP

40-pin HWQFN

R01DS0330EJ0100 Rev.1.00

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RX23E-A Group

1. Overview

1.2

List of Products

Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package

type.

Table 1.3

List of Products

ROM

RAM

Operating

Group

Part No.

Order Part No.

Package

Capacity

E2 DataFlash Frequency Temperature

RX23E-A

R5F523E6ADFL

R5F523E6ADNF

R5F523E5ADFL

R5F523E5ADNF

R5F523E6AGFL

R5F523E6AGNF

R5F523E5AGFL

R5F523E5AGNF

R5F523E6ADFL#30 PLQP0048KB-B

R5F523E6ADNF#U0 PWQN0040KC-A

R5F523E5ADFL#30 PLQP0048KB-B

R5F523E5ADNF#U0 PWQN0040KC-A

R5F523E6AGFL#30 PLQP0048KB-B

R5F523E6AGNF#U0 PWQN0040KC-A

R5F523E5AGFL#30 PLQP0048KB-B

R5F523E5AGNF#U0 PWQN0040KC-A

256 Kbytes

128 Kbytes

256 Kbytes

128 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

16 Kbytes

8 Kbytes

32 MHz

–40 to +85°C

–40 to +105°C

R

5

F

5 2

3 E

6

A

D

F L

Package type, number of pins, and pin pitch

FL: LFQFP/48/0.50

NF: HWQFN/40/0.50

Range of ambient temperatures for guaranteed operation

D: Operating ambient temperature: –40 to +85°C

G: Operating ambient temperature: –40 to +105°C

Target sensor

A: Temperature (thermocouple or resistive temperature

detector)

ROM, RAM, and E2 DataFlash capacity

6: 256 Kbytes/32 Kbytes/8 Kbytes

5: 128 Kbytes/16 Kbytes/8 Kbytes

Group name

3E: RX23E Group

Series name

52: RX200 Series

Type of memory

F: Flash memory version

Renesas MCU

Renesas semiconductor product

Figure 1.1

How to Read the Product Part Number

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RX23E-A Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

E2 DataFlash

IWDTa

RSCAN

LPT

ELC

24-bit delta-sigma A/D converter × 6

channels (unit 0)

CRC

24-bit delta-sigma A/D converter × 6

channels (unit 1)

SCIg × 3 channels

SCIh × 1 channel

RSPIb × 1 channel

RIICa × 1 channel

MTU2a × 6 channels

POE2a

Voltage reference

Excitation current sources

Analog multiplexer

Voltage detector

TMR ×2 channels (unit 0)

TMR ×2 channels (unit 1)

CMT ×2 channels (unit 0)

12-bit A/D converter ×6 channels

DOC

ICUb

ROM

RAM

DTCa

CAC

DMACA

× 4 channels

Port 1

Port 2

Port 3

Port B

Port C

Port H

RX CPU

MPU

Clock

generation

circuit

LVDAb

ICUb:

Interrupt controller

Data transfer controller

DMA controller

Independent watchdog timer

Event link controller

MTU2a:

POE2a:

CMT:

DOC:

CAC:

MPU:

TMR:

RSCAN:

LPT:

Multi-function timer pulse unit 2

Port output enable 2

Compare match timer

Data operation circuit

Clock frequency accuracy measurement circuit

Memory protection unit

8-bit timer

DTCa:

DMACA:

IWDTa:

ELC:

CRC:

CRC (cyclic redundancy check) calculator

SCIg/SCIh: Serial communications interface

RSPIb:

RIICa:

Serial peripheral interface

I²C bus interface

CAN module

Low power timer

LVDAb:

Voltage detection circuit

Figure 1.2

Block Diagram

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RX23E-A Group

1. Overview

1.4

Pin Functions

Table 1.4 lists the pin functions.

Table 1.4

Pin Functions (1/3)

Classifications Pin Name

I/O

Description

Power supply

VCC

VCL

Input

—

Power supply pin. Connect it to the system power supply.

Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to

stabilize the internal power supply. Place the capacitor close to the pin.

VSS

Input

Ground pin. Connect it to the system power supply (0 V).

Clock

XTAL

Output Pins for connecting a crystal. An external clock can be input through the

EXTAL pin.

EXTAL

CLKOUT

Input

Clock output pin.

Output

Input

Operating mode MD

control

Pin for setting the operating mode. The signal levels on this pin must not

be changed during operation.

System control

CAC

RES#

Input

I/O

Reset pin. This MCU enters the reset state when this signal goes low.

Input pin for the clock frequency accuracy measurement circuit.

FINE interface pin.

CACREF

FINED

On-chip

emulator

Interrupts

NMI

Input

I/O

Non-maskable interrupt request pin.

Interrupt request pins.

IRQ0 to IRQ7

MTIOC0A, MTIOC0B,

Multi-function

timer pulse unit 2 MTIOC0C, MTIOC0D

The TGRA0 to TGRD0 input capture input/output compare output/PWM

output pins.

MTIOC1A, MTIOC1B

I/O

The TGRA1 and TGRB1 input capture input/output compare output/PWM

output pins.

MTIOC2A, MTIOC2B

The TGRA2 and TGRB2 input capture input/output compare output/PWM

output pins.

MTIOC3A, MTIOC3B,

MTIOC3C, MTIOC3D

The TGRA3 to TGRD3 input capture input/output compare output/PWM

output pins.

MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D

The TGRA4 to TGRD4 input capture input/output compare output/PWM

output pins.

MTIC5U, MTIC5V, MTIC5W Input

The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input

pins.

MTCLKA, MTCLKB,

MTCLKC, MTCLKD

Input

Input pins for the external clock.

Port output

enable 2

POE0# to POE3#, POE8#

Input pins for request signals to place the MTU pins in the high impedance

state.

8-bit timer

TMO0 to TMO3

TMCI0 to TMCI3

TMRI0 to TMRI3

Output Compare match output pins.

Input

Input pins for the external clock to be input to the counter.

Counter reset input pins.

Serial

 Asynchronous mode/clock synchronous mode

communications

interface (SCIg)

SCK1, SCK5, SCK6

RXD1, RXD5, RXD6

TXD1, TXD5, TXD6

I/O

Input/output pins for the clock.

Input pins for received data.

Input

Output Output pins for transmitted data.

Input Input pins for controlling the start of transmission and reception.

Output Output pins for controlling the start of transmission and reception.

CTS1#, CTS5#, CTS6#

RTS1#, RTS5#, RTS6#

 Simple I²C mode

SSCL1, SSCL5, SSCL6

SSDA1, SSDA5, SSDA6

I/O

Input/output pins for the I²C clock.

Input/output pins for the I²C data.

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RX23E-A Group

1. Overview

Table 1.4

Pin Functions (2/3)

Classifications Pin Name

I/O

Description

Serial

communications

interface (SCIg)

 Simple SPI mode

SCK1, SCK5, SCK6

I/O

Input/output pins for the clock.

SMISO1, SMISO5, SMISO6 I/O

SMOSI1, SMOSI5, SMOSI6 I/O

Input/output pins for slave transmit data.

Input/output pins for master transmit data.

Slave-select input pins.

SS1#, SS5#, SS6#

Input

Serial

 Asynchronous mode/clock synchronous mode

communications

interface (SCIh)

SCK12

I/O

Input/output pin for the clock.

Input pin for receiving data.

RXD12

Input

TXD12

Output Output pin for transmitting data.

Input Input pin for controlling the start of transmission and reception.

Output Output pin for controlling the start of transmission and reception.

CTS12#

RTS12#

 Simple I²C mode

SSCL12

I/O

Input/output pin for the I²C clock.

Input/output pin for the I²C data.

SSDA12

 Simple SPI mode

SCK12

I/O

Input/output pin for the clock.

SMISO12

SMOSI12

SS12#

I/O

Input/output pin for slave transmit data.

Input/output pin for master transmit data.

Slave-select input pin.

I/O

Input

 Extended serial mode

RXDX12

Input

Input pin for data reception by SCIh.

TXDX12

Output Output pin for data transmission by SCIh.

SIOX12

I/O

Input/output pin for data reception or transmission by SCIh.

I²C bus interface SCL

Input/output pin for I²C bus interface clocks. Bus can be directly driven by

the N-channel open drain output.

SDA

I/O

Input/output pin for I²C bus interface data. Bus can be directly driven by

the N-channel open drain output.

Serial peripheral RSPCKA

I/O

Input/output pin for the RSPI clock.

interface

MOSIA

Input/output pin for transmitting data from the RSPI master.

Input/output pin for transmitting data from the RSPI slave.

Input/output pin to select the slave for the RSPI.

MISOA

SSLA0

SSLA1 to SSLA3

CRXD0

Output Output pins to select the slave for the RSPI.

Input Input pin

Output Output pin

CAN module

CTXD0

12-bit A/D con-

verter

AN000 to AN005

ADTRG0#

Input

Analog input pins for the 12-bit A/D converter.

Input pin for the external trigger signal that start the A/D conversion.

Analog front end REF0P, REF1P

REF0N, REF1N

Positive input pins of the reference voltage for the 24-bit delta-sigma A/D

converter.

Input

Negative input pins of the reference voltage for the 24-bit delta-sigma A/D

converter.

REFOUT

Output Internal reference voltage output pin.

Connect this to AVSS0 via a capacitor (0.47 µF) for stabilizing the internal

reference voltage. Place the capacitor close to the pin.

IEXC0 to IEXC3

AIN0 to AIN11

LSW

Output Excitation current source output pins.

I/O

Analog input/output pins.

Output Low-side-switch output pin.

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RX23E-A Group

1. Overview

Table 1.4

Pin Functions (3/3)

Classifications Pin Name

I/O

Description

Analog power

supply

AVCC0

Input

I/O

Analog voltage supply pin. Connect this pin to VCC when not using.

Analog ground pin. Connect this pin to VSS when not using.

Analog reference voltage supply pin for the 12-bit A/D converter.

Analog reference ground pin for the 12-bit A/D converter.

4-bit input/output pins.

AVSS0

VREFH0

VREFL0

I/O ports

P14 to P17

P26, P27

I/O

2-bit input/output pins.

P30, P31, P35 to P37

PB0, PB1

I/O

5-bit input/output pins (P35 input pin).

2-bit input/output pins.

I/O

PC4 to PC7

PH0 to PH3

I/O

4-bit input/output pins.

I/O

4-bit input/output pins.

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RX23E-A Group

1. Overview

1.5

Pin Assignments

Figure 1.3 and Figure 1.4 show the pin assignments. Table 1.5 and Table 1.6 show the lists of pins and pin functions.

REF0N

REF0P

AIN0

37

38

39

40

41

42

43

44

45

46

47

48

24

23

PH0

PH1

PH2

PH3

P14

P15

P16

P17

P26

P27

P30

P31

22

21

20

19

18

AIN1

RX23E-A Group

PLQP0048KB-B

(48-pin LFQFP)

(Top view)

AIN2

AIN3

AIN4/REF1N

AIN5/REF1P

AIN6

17

16

15

14

13

AIN7

AIN8/VREFL0

AIN9/VREFH0

Note:

This figure indicates the power supply pins and I/O port pins.

For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP)”.

Figure 1.3

Pin Assignments of the 48-Pin LFQFP

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RX23E-A Group

1. Overview

REF0N 31

20

19

18

17

16

15

14

13

12

11

PH0

PH1

P14

P15

P16

P17

P26

P27

P30

P31

32

33

34

35

REF0P

AIN0

RX23E-A Group

PWQN0040KC-A

(40-pin HWQFN)

(Top view)

AIN1

AIN4/REF1N

AIN5/REF1P 36

AIN6 37

AIN7

38

AIN8/VREFL0 39

AIN9/VREFH0 40

Note:

This figure indicates the power supply pins and I/O port pins.

For the pin configuration, see the table “List of Pins and Pin Functions (40-Pin HWQFN)”.

It is recommended that the exposed die pad of HWQFN should be connected to VSS.

Figure 1.4

Pin Assignments of the 40-Pin HWQFN

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Page 13 of 98

RX23E-A Group

1. Overview

Table 1.5

List of Pins and Pin Functions (48-Pin LFQFP) (1/2)

Power Supply,

Analog

No.

Clock, System

Control

Timers

Communications

(SCIg, SCIh, RSPI, RIIC, CAN)

(S12AD, VREF,

IEXC, DSAD, AMUX) Others

I/O Port

(MTU, TMR, CMT, POE, CAC)

1

AIN10/AN004/IEXC0

to IEXC3

2

AIN11/AN005/IEXC0

to IEXC3

3

AVSS0

AVCC0

RES#

XTAL

VSS

4

5

6

P37

P36

7

8

EXTAL

VCC

9

10

11

12

13

14

VCL

MD

FINED

NMI

P35

P31

P30

MTIOC1A/MTIOC4D/TMO3

CTS1#/RTS1#/SS1#

IRQ1

IRQ0

MTIOC0A/MTIOC4B/TMCI3/

POE8#

RXD1/SMISO1/SSCL1

15

16

17

P27

P26

P17

MTIOC2B/MTIOC4A/TMRI3

MTIOC2A/MTIOC4C/TMO0

SCK1

IRQ3

IRQ2

IRQ7

TXD1/SMOSI1/SSDA1

SCK1/MISOA/SDA

MTIOC3A/MTIOC3B/TMO1/

POE8#

18

19

20

P16

P15

P14

MTIOC3C/MTIOC3D/TMO2

MTIOC0B/MTCLKB/TMCI2

MTIOC3A/MTCLKA/TMRI2

TXD1/SMOSI1/SSDA1/MOSIA/

SCL

IRQ6/ADTRG0#

RXD1/SMISO1/SSCL1/SSLA1/

CRXD0

IRQ5

IRQ4

CTS1#/RTS1#/SS1#/SSLA3/

CTXD0

21

22

23

24

PH3

PH2

PH1

PH0

MTIC5W/MTCLKB/TMCI0/POE2# CTS6#/RTS6#/SS6#/RSPCKA

MTIC5V/MTCLKA/TMRI0

SCK5/MOSIA

IRQ1

MTIC5U/MTCLKD/TMO0/POE2#

TXD5/SMOSI5/SSDA5/SSLA0

RXD5/SMISO5/SSCL5/SSLA2

IRQ0/CLKOUT

MTIOC0D/MTCLKC/TMRI0/

CACREF

25

PC7

MTIOC3A/MTCLKB/TMO2/

CACREF

TXD6/SMOSI6/SSDA6/MISOA

26

27

28

PC6

PC5

PC4

MTIOC3C/MTCLKA/TMCI2

MTIOC3B/MTCLKD/TMRI2

RXD6/SMISO6/SSCL6/MOSIA

SCK5/SCK6/SCK12/RSPCKA

MTIOC3D/MTCLKC/TMCI1/

POE0#

CTS5#/RTS5#/SS5#/CTS12#/

RTS12#/SS12#/SSLA0

29

PB1

PB0

MTIOC1B/MTIOC2A/TMRI1/

POE1#

TXD12/TXDX12/SIOX12/

SMOSI12/SSDA12

30

31

VCC

MTIOC0C/TMCI0/POE3#

RXD12/RXDX12/SMISO12/

SSCL12

IRQ4

32

33

34

35

36

37

38

39

40

41

42

43

VSS

AVCC0

AVSS0

REFOUT

LSW

REF0N

REF0P

AIN0/IEXC0 to IEXC3

AIN1/IEXC0 to IEXC3

AIN2/IEXC0 to IEXC3

AIN3/IEXC0 to IEXC3

AIN4/IEXC0 to

IEXC3/REF1N

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RX23E-A Group

1. Overview

Table 1.5

List of Pins and Pin Functions (48-Pin LFQFP) (2/2)

Power Supply,

Analog

No.

Clock, System

Control

Timers

Communications

(SCIg, SCIh, RSPI, RIIC, CAN)

(S12AD, VREF,

IEXC, DSAD, AMUX) Others

I/O Port

(MTU, TMR, CMT, POE, CAC)

44

45

46

47

48

AIN5/IEXC0 to

IEXC3/REF1P

AIN6/AN000/IEXC0

to IEXC3

AIN7/AN001/IEXC0

to IEXC3

VREFL0

VREFH0

AIN8/AN002/IEXC0

to IEXC3

AIN9/AN003/IEXC0

to IEXC3

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Page 15 of 98

RX23E-A Group

1. Overview

Table 1.6

List of Pins and Pin Functions (40-Pin HWQFN)

Power Supply,

Analog

No.

Clock, System

Control

Timers

Communications

(SCIg, SCIh, RSPI, RIIC, CAN)

(S12AD, VREF,

IEXC, DSAD, AMUX) Others

I/O Port

(MTU, TMR, CMT, POE, CAC)

1

AVSS0

AVCC0

RES#

XTAL

VSS

2

3

4

P37

P36

5

6

EXTAL

VCC

7

8

VCL

9

MD

FINED

NMI

10

11

12

P35

P31

P30

MTIOC1A/MTIOC4D/TMO3

CTS1#/RTS1#/SS1#

IRQ1

IRQ0

MTIOC0A/MTIOC4B/TMCI3/

POE8#

RXD1/SMISO1/SSCL1

13

14

15

P27

P26

P17

MTIOC2B/MTIOC4A/TMRI3

MTIOC2A/MTIOC4C/TMO0

SCK1

IRQ3

IRQ2

IRQ7

TXD1/SMOSI1/SSDA1

SCK1/MISOA/SDA

MTIOC3A/MTIOC3B/TMO1/

POE8#

16

17

18

P16

P15

P14

MTIOC3C/MTIOC3D/TMO2

MTIOC0B/MTCLKB/TMCI2

MTIOC3A/MTCLKA/TMRI2

MTCLKD/TMO0/POE2#

TXD1/SMOSI1/SSDA1/MOSIA/

SCL

IRQ6/ADTRG0#

RXD1/SMISO1/SSCL1/SSLA1/

CRXD0

IRQ5

CTS1#/RTS1#/SS1#/SSLA3/

CTXD0

IRQ4

19

20

PH1

PH0

TXD5/SMOSI5/SSDA5/SSLA0

RXD5/SMISO5/SSCL5/SSLA2

IRQ0/CLKOUT

MTIOC0D/MTCLKC/TMRI0/

CACREF

21

22

PC5

PC4

MTIOC3B/MTCLKD/TMRI2

SCK5/SCK12/RSPCKA

MTIOC3D/MTCLKC/TMCI1/

POE0#

CTS5#/RTS5#/SS5#/CTS12#/

RTS12#/SS12#/SSLA0

23

PB1

PB0

MTIOC1B/MTIOC2A/TMRI1/

POE1#

TXD12/TXDX12/SIOX12/

SMOSI12/SSDA12

24

25

VCC

MTIOC0C/TMCI0/POE3#

RXD12/RXDX12/SMISO12/

SSCL12

IRQ4

26

27

28

29

30

31

32

33

34

35

VSS

AVCC0

AVSS0

REFOUT

LSW

REF0N

REF0P

AIN0/IEXC0 to IEXC3

AIN1/IEXC0 to IEXC3

AIN4/IEXC0 to

IEXC3/REF1N

36

37

38

39

40

AIN5/IEXC0 to

IEXC3/REF1P

AIN6/AN000/IEXC0

to IEXC3

AIN7/AN001/IEXC0

to IEXC3

VREFL0

VREFH0

AIN8/AN002/IEXC0

to IEXC3

AIN9/AN003/IEXC0

to IEXC3

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Page 16 of 98

RX23E-A Group

2. Electrical Characteristics

2.

Electrical Characteristics

2.1

Absolute Maximum Ratings

Table 2.1

Absolute Maximum Ratings

Conditions: VSS = AVSS0 = VREFL0 = 0 V

Item

Symbol

VCC

V_in

Value

Unit

V

Power supply voltage

–0.3 to +6.5

Input voltage

P16 and P17 (5-V tolerant)

Ports other than above

V

–0.3 to VCC + 0.3

–0.3 to AVCC0 + 0.3

–0.3 to +6.5

Reference power supply voltage

Analog power supply voltage

VREFH0

AVCC0

V

Analog input voltage

V_AN

–0.3 to AVCC0 + 0.3

–40 to +105

Reference voltage for 24-bit delta-sigma A/D converter

REF0P, REF1P

REF0N, REF1N

T_j

Junction temperature

Storage temperature

D version

G version

°C

–40 to +112

T_stg

–55 to +125

Caution: Exceeding absolute maximum ratings may permanently damage the MCU.

To preclude malfunctions due to noise interference, insert capacitors with high frequency characteristics between the VCC and

VSS pins, between the AVCC0 and AVSS0 pins, and between the VREFH0 and VREFL0 pins. Place capacitors with values of

about 0.1 μF as close as possible to every power supply pin and use the shortest and widest possible traces.

Connect the VCL pin to a VSS pin via a 4.7-μF capacitor. The capacitor must be placed close to the pin. For details, refer to

section 2.12.1, Connecting VCL Capacitor and Bypass Capacitors.

Do not input signals to ports other than 5-V tolerant ports while power is not being supplied to the MCU.

The current injection that results from the input of such a signal may lead to malfunctions and the abnormal current that passes

through the MCU at such times may cause degradation of internal elements.

However, even if –0.3 to +6.5 V is input to a 5-V tolerant port, this will not cause problems such as damage to the MCU.

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RX23E-A Group

2. Electrical Characteristics

2.2

Recommended Operating Conditions

Table 2.2

Recommended Operating Conditions (1)

Item

Symbol

VCC^{*1, *2}

VSS

Min.

1.8

—

Typ.

—

0

Max.

5.5

Unit

V

Power supply voltages

—

Analog power supply voltages

AVCC0^{*1, *2}

AVSS0

1.8

—

0

5.5

V

—

VREFH0

VREFL0

T_opr

1.8

—

0

AVCC0

—

Operating temperature

D version

G version

–40

—

85

°C

105

Note 1. Use AVCC0 and VCC under the following conditions:

While VCC > 2.4 V: AVCC0 and VCC can be set independently when AVCC0 ≥ 2.4 V

While VCC ≤ 2.4 V: AVCC0 and VCC can be set independently when AVCC0 ≥ VCC

Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin.

Table 2.3

Recommended Operating Conditions (2)

Item

VCL pin external capacitance

Symbol

C_VCL

Value

4.7 µF ± 30%*¹

Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 4.7 µF and a capacitance tolerance is ±30% or better.

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RX23E-A Group

2. Electrical Characteristics

2.3

DC Characteristics

Table 2.4

DC Characteristics (1)

Conditions: 2.7 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Conditions

Item

Symbol

V_IH

Min.

Typ.

—

Max.

Unit

V

Schmitt trigger

input voltage

RIIC input pin

0.7 × VCC

5.8

(except for SMBus, 5-V tolerant)

P16 and P17 (5-V tolerant)

0.8 × VCC

—

5.8

P14, P15, P26, P27, P30, P31,

P35 to P37, PB0, PB1,

PC4 to PC7, PH0 to PH3, and

RES#

VCC + 0.3

RIIC input pin (except for

SMBus)

V_IL

–0.3

—

0.3 × VCC

Other than RIIC input pin

–0.3

—

0.2 × VCC

—

Hysteresis of

Schmitt trigger

input

RIIC input pin (except for

SMBus)

ΔV_T

0.05 × VCC

P16 and P17

0.05 × VCC

0.1 × VCC

0.9 × VCC

0.8 × VCC

2.1

—

Other than RIIC input pin

MD

—

High-level input

voltage (except for

Schmitt trigger

input pins)

V_IH

VCC + 0.3

0.1 × VCC

0.2 × VCC

0.8

V

EXTAL (external clock input)

RIIC input pin (SMBus)

MD

Low-level input

voltage (except for

Schmitt trigger

input pins)

V_IL

–0.3

EXTAL (external clock input)

RIIC input pin (SMBus)

–0.3

Table 2.5

DC Characteristics (2)

Conditions: 1.8 V ≤ VCC < 2.7 V, 1.8 V ≤ AVCC0 < 2.7 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Conditions

Item

Symbol

V_IH

Min.

Typ.

Max.

Unit

V

Schmitt trigger

input voltage

P16 and P17 (5-V tolerant)

0.8 × VCC

—

5.8

P14, P15, P26, P27, P30, P31,

P35 to P37, PB0, PB1,

PC4 to PC7, PH0 to PH3, and

RES#

VCC + 0.3

P14 to P17, P26, P27, P30, P31,

P35 to P37, PB0, PB1,

PC4 to PC7, PH0 to PH3, and

RES#

V_IL

ΔV_T

V_IH

V_IL

–0.3

—

0.2 × VCC

Hysteresis of

Schmitt trigger

input

P14 to P17, P26, P27, P30, P31,

P35 to P37, PB0, PB1,

PC4 to PC7, PH0 to PH3, and

RES#

0.01 × VCC

—

High-level input

voltage (except for

Schmitt trigger

input pins)

MD

0.9 × VCC

0.8 × VCC

—

VCC + 0.3

V

EXTAL (external clock input)

Low-level input

voltage (except for

Schmitt trigger

input pins)

MD

–0.3

—

0.1 × VCC

0.2 × VCC

EXTAL (external clock input)

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Page 19 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.6

DC Characteristics (3)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

|I_in|

Min.

—

Typ.

—

Max.

1.0

0.2

15

Unit

μA

Test Conditions

V_in= 0 V, VCC

V_in= 0 V, 5.8V

V_in= 0 V, VCC

Input leakage current

RES#, MD, and P35

P16 and P17

Three-state leakage

current (off-state)

|I_TSI

|

—

μA

Ports other than P16 and P17

—

Input capacitance

P14 to P17, P26, P27, P30, P31,

P36, P37, PB0, PB1, PC4 to PC7,

PH0 to PH3, MD, and RES#

C_in

—

pF

V

V_in= 20 mV,

f = 1 MHz,

T_a= 25°C

P35

—

30

—

Output voltage of the VCL pin

V_CL

2.12

Table 2.7

DC Characteristics (4)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

R_U

Min.

10

Typ.

20

Max.

50

Unit

kΩ

Test Conditions

V_in= 0 V

Input pull-up resistor

All ports (except for P35)

Table 2.8

DC Characteristics (5)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Typ.

*

Test

Conditions

Item

Symbol

I_CC

Max. Unit

4

Supply High-speed

Normal

No peripheral modules ICLK = 32 MHz

current operating mode operating mode are operating.*²

4.1

2.9

2.2

1.9

16.3

9.1

5.5

3.7

—

mA

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 4 MHz

1

*

—

All peripheral modules ICLK = 32 MHz*³

are in normal

ICLK = 16 MHz*³

operation.

—

ICLK = 8 MHz*³

—

ICLK = 4 MHz*³

—

All peripheral modules ICLK = 32 MHz*³

are in full operation.

30.3

Sleep mode

No peripheral modules ICLK = 32 MHz

2.4

1.9

1.6

1.5

8.9

5.4

3.5

2.5

1.5

1.3

1.2

7.2

4.4

2.8

2.1

2.5

—

are operating.*²

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 4 MHz

All peripheral modules ICLK = 32 MHz*³

are in normal

ICLK = 16 MHz*³

operation.

ICLK = 8 MHz*³

ICLK = 4 MHz*³

Deep sleep

mode

No peripheral modules ICLK = 32 MHz

are operating.*²

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 4 MHz

All peripheral modules ICLK = 32 MHz*³

are in normal

ICLK = 16 MHz*³

operation.

ICLK = 8 MHz*³

ICLK = 4 MHz*³

Increase during BGO operation*⁵

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Page 20 of 98

RX23E-A Group

2. Electrical Characteristics

Typ.

*

Test

Conditions

Item

No peripheral modules ICLK = 12 MHz

Symbol

I_CC

Max. Unit

4

Supply Middle-speed

Normal

2.1

1.7

1.4

1.1

6.8

5.0

3.1

1.6

—

mA

current operating mode operating mode are operating.*⁶

ICLK = 8 MHz

ICLK = 4 MHz

ICLK = 1 MHz

1

*

—

All peripheral modules ICLK = 12 MHz

are in normal

ICLK = 8 MHz

operation.*⁷

—

ICLK = 4 MHz

—

ICLK = 1 MHz

—

All peripheral modules ICLK = 12 MHz

are in full operation.*⁷

13.5

Sleep mode

No peripheral modules ICLK = 12 MHz

1.4

1.2

1.1

1.0

4.0

3.0

2.1

1.3

1.0

0.9

0.8

3.3

2.6

1.8

1.2

2.5

—

are operating.*⁶

ICLK = 8 MHz

ICLK = 4 MHz

ICLK = 1 MHz

All peripheral modules ICLK = 12 MHz

are in normal

ICLK = 8 MHz

operation.*⁷

ICLK = 4 MHz

ICLK = 1 MHz

Deep sleep

mode

No peripheral modules ICLK = 12 MHz

are operating.*⁶

ICLK = 8 MHz

ICLK = 4 MHz

ICLK = 1 MHz

All peripheral modules ICLK = 12 MHz

are in normal

ICLK = 8 MHz

operation.*⁷

ICLK = 4 MHz

ICLK = 1 MHz

Increase during BGO operation*⁵

Note 1. Supply current values do not include the output charge/discharge current from all pins. The values apply when internal pull-up

resistors are disabled.

Note 2. Peripheral module clocks are stopped. This does not include BGO operation. The clock source is PLL. FCLK and PCLK are set

to divided by 64.

Note 3. Peripheral module clocks are supplied. This does not include BGO operation. The clock source is PLL. FCLK and PCLK are the

same frequency as that of ICLK.

Note 4. Conditions for typical values are at VCC = 3.3 V and T_a= 25°C.

Note 5. The increase is caused by program/erase operation to the ROM or E2 DataFlash during the execution of a user program.

Note 6. Peripheral module clocks are stopped. The clock source is PLL when ICLK is 12 MHz and HOCO for other cases. FCLK and

PCLK are set to divided by 64.

Note 7. Peripheral module clocks are supplied. The clock source is PLL when ICLK is 12 MHz and HOCO for other cases. FCLK and

PCLK are the same frequency of that of the ICLK.

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RX23E-A Group

2. Electrical Characteristics

40

30

20

10

0

Ta = 105°C, ICLK = 32 MHz

Ta = 25°C, ICLK = 32 MHz

Ta = 105°C, ICLK = 16 MHz

Ta = 105°C, ICLK = 8 MHz

Ta = 25°C, ICLK = 16 MHz

Ta = 105°C, ICLK = 4 MHz

Ta = 25°C, ICLK = 8 MHz

Ta = 25°C, ICLK = 4 MHz

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC [V]

Ta = 25°C, ICLK = 32 MHz*¹

Ta = 25°C, ICLK = 16 MHz*¹

Ta = 25°C, ICLK = 8 MHz *¹

Ta = 25°C, ICLK = 4 MHz *¹

Ta = 105°C, ICLK = 32 MHz*²

Ta = 105°C, ICLK = 16 MHz*²

Ta = 105°C, ICLK = 8 MHz*²

Ta = 105°C, ICLK = 4 MHz*²

Note 1. This result applies when all peripheral modules are in normal operation but BGO is not in use. Indicates the

average of the typical samples through actual measurement during product evaluation.

Note 2. This result applies when all peripheral modules are in full operation but BGO is not in use. Indicates the average

of the upper-limit samples through actual measurement during product evaluation.

Figure 2.1

Voltage Dependence in High-Speed Operating Mode (Reference Data)

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2. Electrical Characteristics

20

Ta = 105°C, ICLK = 12 MHz

10

Ta = 105°C, ICLK = 8 MHz

Ta = 25°C, ICLK = 12 MHz

Ta = 105°C, ICLK = 4 MHz

Ta = 25°C, ICLK = 8 MHz

Ta = 25°C, ICLK = 4 MHz

Ta = 105°C, ICLK = 1 MHz

Ta = 25°C, ICLK = 1 MHz

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC [V]

Ta = 25°C, ICLK = 12 MHz*¹

Ta = 25°C, ICLK = 8 MHz*¹

Ta = 25°C, ICLK = 4 MHz*¹

Ta = 105°C, ICLK = 12 MHz*²

Ta = 105°C, ICLK = 8 MHz*²

Ta = 105°C, ICLK = 4 MHz*²

Ta = 25°C, ICLK = 1 MHz*¹

Ta = 105°C, ICLK = 1 MHz*²

Note 1. This result applies when all peripheral modules are in normal operation but BGO is not in use. Indicates the

average of the typical samples through actual measurement during product evaluation.

Note 2. This result applies when all peripheral modules are in full operation but BGO is not in use. Indicates the average

of the upper-limit samples through actual measurement during product evaluation.

Figure 2.2

Voltage Dependence in Middle-Speed Operating Mode (Reference Data)

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RX23E-A Group

2. Electrical Characteristics

Table 2.9

DC Characteristics (6)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

I_CC

Typ.*³

0.4

Max.

2.6

Unit

μA

Test Conditions

Supply

Software standby T_a= 25°C

current*¹mode*²

T_a= 55°C

T_a= 85°C

T_a= 105°C

0.8

3.0

2.5

12.6

31.2

—

6.3

Increment for IWDT operation

Increment for LPT operation

0.4

—

Use IWDT-Dedicated On-Chip Oscillator for

clock source

Note 1. Supply current values were obtained with no load on any output pin and all internal pull-up resistors disabled.

Note 2. The IWDT and LVD are stopped.

Note 3. Conditions for typical values are at VCC = 3.3 V.

100

Ta = 105°C *²

10

1

Ta = 85°C *²

Ta = 105°C *¹

Ta = 85°C *¹

Ta = 55°C *²

Ta = 55°C *¹

Ta = 25°C *²

Ta = 25°C *¹

0.1

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC [V]

Ta = 25°C *¹

Ta = 25°C *²

Ta = 55°C *¹

Ta = 55°C *²

Ta = 85°C *¹

Ta = 85°C *²

Ta = 105°C *¹

Ta = 105°C *²

Note 1. Indicates the average of the typical samples through actual measurement during product evaluation.

Note 2. Indicates the average of the upper-limit samples through actual measurement during product evaluation.

Figure 2.3

Voltage Dependence in Software Standby Mode (Reference Data)

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RX23E-A Group

2. Electrical Characteristics

100

10

1

0.1

–40

–20

0

20

40

60

80

100

Ta [°C]

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.4

Table 2.10

Temperature Dependence in Software Standby Mode (Reference Data)

DC Characteristics (7)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

l_LVD

Min.

—

Typ.*¹

0.10

Max.

—

Unit

μA

Test Conditions

LVD

LVD0

LVD1

LVD2

—

0.10

—

0.20

—

Note 1. Conditions for typical values are at VCC = AVCC0 = 3.3 V and T_a= 25°C.

Table 2.11

DC Characteristics (8)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_RAM

Min.

1.8

Typ.

—

Max.

—

Unit

V

Test Conditions

RAM standby voltage

Table 2.12

DC Characteristics (9)

Conditions: 0 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

SrVCC

Min.

0.02

Typ.

—

Max.

20.00

2.00

—

Unit

ms/V

Test Conditions

VCC ramp-up rate at At normal startup*¹

power-on

During fast startup time*²

—

Voltage monitoring 0 reset

enabled at startup*^3,

—

4

*

Note 1. When the OFS1.LVDAS and OFS1.FASTSTUP bits are 1

Note 2. When the OFS1.LVDAS bit is 1 and the OFS1.FASTSTUP bit is 0

Note 3. When the OFS1.LVDAS bit is 0

Note 4. Turn on the power supply voltage according to the normal startup rising gradient because the settings in the OFS1 register are

not read in boot mode.

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RX23E-A Group

2. Electrical Characteristics

Table 2.13

DC Characteristics (10)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

The result of any ripple must be within the limit on allowable ripple frequency f

where the ripple voltage is within the range

r (VCC)

between the VCC upper limit and lower limit. The result of any ripple must be within the limit on the allowable VCC ramp rate in

power fluctuation (dt/dVCC) where the change in VCC exceeds VCC ±10%.

Item

Symbol

f_{r (VCC)}

Min.

—

Typ.

—

Max.

10

Unit

kHz

Test Conditions

Allowable ripple frequency

Figure 2.5

V_{r (VCC)}≤ 0.2 × VCC

—

1

MHz

ms/V

Figure 2.5

V_{r (VCC)}≤ 0.08 × VCC

10

—

Figure 2.5

V_{r (VCC)}≤ 0.06 × VCC

Allowable VCC ramp rate at dt/dVCC

power fluctuation

1.0

When VCC change exceeds VCC ±10%

1 / f_{r (VCC)}

VCC

V_{r (VCC)}

Figure 2.5

Ripple Waveform

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Aug 30, 2019

Page 26 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.14

DC Characteristics (11)

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

Min.

—

Typ.

Max.

660

Unit

µA

Test Conditions

Operating current of Gain = 1

I_AVCC0

500*¹

Figure 2.6, Figure 2.7

1 unit, external reference

in use, reference buffer

disabled,

24-bit delta-sigma

A/D converter

(normal mode)

(PGA disabled, BUF disabled)

OPCR.DSADLVM bit = 0

(DSAD)

Gain = 1 to 16 (PGA enabled)

OPCR.DSADLVM bit = 0

—

840*¹

1050*¹

490*²

1130

1360

850

AVCC0 = 3.6 to 5.5 V

Gain = 32 to 128

OPCR.DSADLVM bit = 0

Gain = 1

(PGA disabled, BUF disabled)

OPCR.DSADLVM bit = 1

Figure 2.8, Figure 2.9

1 unit, external reference

in use, reference buffer

disabled,

Gain = 1 to 16 (PGA enabled)

OPCR.DSADLVM bit = 1

—

820*²

1040*²

250*¹

1320

1560

280

AVCC0 = 2.7 to 5.5 V

Gain = 32 to 128

OPCR.DSADLVM bit = 1

Operating current of Gain = 1

µA

Figure 2.10, Figure 2.11

1 unit, external reference

in use, reference buffer

disabled,

24-bit delta-sigma

A/D converter

(low power mode)

(PGA disabled, BUF disabled)

OPCR.DSADLVM bit = 0

Gain = 1 to 16 (PGA enabled)

OPCR.DSADLVM bit = 0

—

390*¹

430*¹

240*²

480

520

350

AVCC0 = 3.6 to 5.5 V

Gain = 32 to 128

OPCR.DSADLVM bit = 0

Gain = 1

(PGA disabled, BUF disabled)

OPCR.DSADLVM bit = 1

Figure 2.12, Figure 2.13

1 unit, external reference

in use, reference buffer

disabled,

Gain = 1 to 16 (PGA enabled)

OPCR.DSADLVM bit = 1

—

380*²

420*²

45

550

590

75

AVCC0 = 2.7 to 5.5 V

Gain = 32 to 128

OPCR.DSADLVM bit = 1

Operating current of voltage reference

Operating current of temperature sensor

Operating current of bias voltage generator

Operating current of excitation current source

Operating current of Normal mode

I_AVCC0

(VREF)

I_AVCC0

(TEMPS)

I_AVCC0

(VBIAS)

I_AVCC0

(IEXC)

µA

Figure 2.18

Figure 2.19

Figure 2.20

Figure 2.21

15

40

15

25

55

70

I_AVCC0

(BUF)

—

85

25

85

25

5

130

40

130

40

9

Figure 2.14, 1 unit

Figure 2.15, 1 unit

Figure 2.16, 1 unit

Figure 2.17, 1 unit

1 unit

analog input buffer

Low power mode

Operating current of Normal mode

I_AVCC0

µA

reference buffer

(REFBUF)

Low power mode

Operating current of Low voltage detector for power

I_AVCC0

(LVDET)

I_AVCC0

voltage detector

supply

Excitation current source

disconnect detector

—

1

5

2

7

(IEXCDET)

I_AVCC0

DSAD input voltage fault

detector

(DSIDET)

I_AVCC0

DSAD reference voltage fault

detector

10

15

(DSRDET)

Note 1. Conditions for this value is at AVCC0 = 5.0 V and T_a= 25°C.

Note 2. Conditions for this value is at AVCC0 = 3.3 V and T_a= 25°C.

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RX23E-A Group

2. Electrical Characteristics

1400

1200

1000

800

600

400

200

0

1400

1200

1000

800

600

400

200

0

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 128

–50 –25

0

25

50

75

100 125

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Temperature [°C]

AVCC0 [V]

Figure 2.6

Temperature Dependence of Operating

Current of 24-Bit Delta-Sigma A/D

Converter (AVCC0 = 5.0 V, Normal Mode,

OPCR.DSADLVM bit = 0)

Figure 2.7

Power-Supply Voltage Dependence of

Operating Current of 24-Bit Delta-Sigma

A/D Converter (T_a= 25°C, Normal Mode,

OPCR.DSADLVM bit = 0)

1400

1200

1000

800

600

400

200

0

1400

1200

1000

800

600

400

200

0

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 128

–50 –25

0

25

50

75

100 125

2.5 3.0

3.5 4.0

4.5 5.0

5.5 6.0

Temperature [°C]

AVCC0 [V]

Figure 2.8

Temperature Dependence of Operating

Current of 24-Bit Delta-Sigma A/D

Converter (AVCC0 = 5.0 V, Normal Mode,

OPCR.DSADLVM bit = 1)

Figure 2.9

Power-Supply Voltage Dependence of

Operating Current of 24-Bit Delta-Sigma

A/D Converter (T_a= 25°C, Normal Mode,

OPCR.DSADLVM bit = 1)

600

500

400

300

200

100

0

600

500

400

300

200

100

0

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 128

–50 –25

0

25

50

75

100 125

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Temperature [°C]

AVCC0 [V]

Figure 2.10

Temperature Dependence of Operating

Current of 24-Bit Delta-Sigma A/D

Converter (AVCC0 = 5.0 V, Low Power

Mode, OPCR.DSADLVM bit = 0)

Figure 2.11

Power-Supply Voltage Dependence of

Operating Current of 24-Bit Delta-Sigma

A/D Converter (T_a= 25°C, Low Power

Mode, OPCR.DSADLVM bit = 0)

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RX23E-A Group

2. Electrical Characteristics

600

500

400

300

200

100

0

600

500

400

300

200

100

0

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 1

(PGA disabled, BUF disabled)

Gain = 16

Gain = 128

–50 –25

0

25

50

75

100 125

2.5 3.0 3.5 4.0

AVCC0 [V]

Power-Supply Voltage Dependence of

4.5 5.0

5.5 6.0

Temperature [°C]

Figure 2.12

Temperature Dependence of Operating

Current of 24-Bit Delta-Sigma A/D

Converter (AVCC0 = 5.0 V, Low Power

Mode, OPCR.DSADLVM bit = 1)

Figure 2.13

Operating Current of 24-Bit Delta-Sigma

A/D Converter (T_a= 25°C, Low Power

Mode, OPCR.DSADLVM bit = 1)

100

90

80

70

60

50

30

20

10

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

–50 –25

0

25

50 75 100 125 150

–50 –25

0

25 50

75 100 125 150

Temperature [°C]

Figure 2.14

Temperature Dependence of Operating

Current of Analog Input Buffer

(Normal Mode)

Figure 2.15

Temperature Dependence of Operating

Current of Analog Input Buffer

(Low Power Mode)

100

90

80

70

60

50

30

20

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

10

–50 –25

0

25

50

75 100 125 150

–50 –25

0

25

50

75 100 125 150

Temperature [°C]

Figure 2.16

Temperature Dependence of Operating

Current of Reference Buffer

(Normal Mode)

Figure 2.17

Temperature Dependence of Operating

Current of Reference Buffer

(Low Power Mode)

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RX23E-A Group

2. Electrical Characteristics

60

50

40

30

20

10

0

AVCC0 = 2.7 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

AVCC0 = 2.7 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

20

–50 –25

0

25

50

75 100 125 150

–50 –25

0

25

50

75 100 125 150

Temperature [°C]

Figure 2.18

Temperature Dependence of Operating

Current of Voltage Reference

Figure 2.19

Temperature Dependence of Operating

Current of Temperature Sensor

30

70

20

10

0

60

50

40

AVCC0 = 2.7 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

AVCC0 = 2.7 V

AVCC0 = 3.3 V

AVCC0 = 5.0 V

AVCC0 = 5.5 V

–50 –25

0

25

50

75 100 125 150

–50 –25

0

25

50

75 100 125 150

Temperature [°C]

Figure 2.20

Temperature Dependence of Operating

Current of Bias Voltage Generator

Figure 2.21

Temperature Dependence of Operating

Current of Excitation Current Source

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RX23E-A Group

2. Electrical Characteristics

Table 2.15

DC Characteristics (12)

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

Min.

—

Typ.*¹

1.1

Max.

1.8

Unit

Test Conditions

12-bit A/D converter During A/D conversion

I_AVCC0

mA

operating current

(in high-speed conversion)

(S12AD)

During A/D conversion

(in low-current mode)

—

0.6

71

—

1.1

122

60

Reference power

supply current

During A/D conversion

(in high-speed conversion)

I_REFH0

µA

nA

µA

Current while waiting for A/D

conversion (all units)

AVCC0 power down current

I_STBY

—

2.2

Note 1. Conditions for typical values are at AVCC0 = 5.0 V and T_a= 25°C.

Table 2.16

Permissible Output Currents (1)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +85°C

a

Item

Symbol

I_OL

Max.

4.0

Unit

Permissible low-level output

P36 and P37

mA

current (average value per pin)

Ports other than above

Normal drive output mode

4.0

High-drive output mode

8.0

Permissible low-level output

P36 and P37

4.0

current (maximum value per pin)

Ports other than above

Normal drive output mode

High-drive output mode

4.0

8.0

Permissible low-level output

current

Total of P14 to P17, P26, P27, P30, P31, P36, and P37

Total of PB0, PB1, PC4 to PC7, and PH0 to PH3

Total of all output pins

ΣI_OL

40

80

Permissible high-level output

current (average value per pin)

P36 and P37

I_OH

–4.0

–8.0

–4.0

–8.0

–40

–80

Ports other than above

Normal drive output mode

High-drive output mode

Permissible high-level output

current (maximum value per pin)

P36 and P37

Ports other than above

Normal drive output mode

High-drive output mode

Permissible high-level output

current

Total of P14 to P17, P26, P27, P30, P31, P36, and P37

Total of PB0, PB1, PC4 to PC7, and PH0 to PH3

Total of all output pins

ΣI_OH

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RX23E-A Group

2. Electrical Characteristics

Table 2.17

Permissible Output Currents (2)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

I_OL

Max.

4.0

Unit

mA

Permissible low-level output

P36 and P37

current (average value per pin)

Ports other than above

Normal drive output mode

High-drive output mode

4.0

8.0

Permissible low-level output

P36 and P37

4.0

current (maximum value per pin)

Ports other than above

Normal drive output mode

High-drive output mode

4.0

8.0

Permissible low-level output

current

Total of P14 to P17, P26, P27, P30, P31, P36, and P37

Total of PB0, PB1, PC4 to PC7, and PH0 to PH3

Total of all output pins

ΣI_OL

30

60

Permissible high-level output

current (average value per pin)

P36 and P37

I_OH

–4.0

–8.0

–4.0

–8.0

–30

–60

Ports other than above

Normal drive output mode

High-drive output mode

Permissible high-level output

current (maximum value per pin)

P36 and P37

Ports other than above

Normal drive output mode

High-drive output mode

Permissible high-level output

current

Total of P14 to P17, P26, P27, P30, P31, P36, and P37

Total of PB0, PB1, PC4 to PC7, and PH0 to PH3

Total of all output pins

ΣI_OH

Table 2.18

Output Voltage (1)

Conditions: 1.8 V ≤ VCC = AVCC0 < 2.7 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Low-level output All output ports

Symbol

V_OL

Min.

—

Max.

Unit

V

Test Conditions

I_OL= 0.5 mA

Normal drive output mode

High-drive output mode

Normal drive output mode

High-drive output mode

0.3

—

voltage

—

I_OL= 1.0 mA

High-level output All output ports

voltage

V_OH

VCC – 0.3

V

I_OH= –0.5 mA

—

I

_OH= –1.0 mA

Table 2.19

Output Voltage (2)

Conditions: 2.7 V ≤ VCC = AVCC0 < 4.0 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Low-level output All output ports

voltage (except for RIIC

Symbol

V_OL

Min.

—

Max.

0.5

Unit

V

Test Conditions

Normal drive output mode

High-drive output mode

I_OL= 1.0 mA

—

0.5

I

_OL= 2.0 mA

_OL= 3.0 mA

pins)

RIIC pins

Normal drive output mode

High-drive output mode

Normal drive output mode

High-drive output mode

—

0.4

0.6

—

I

—

I_OL= 6.0 mA

I_OH= –1.0 mA

I_OH= –2.0 mA

High-level output All output ports

voltage

V_OH

VCC – 0.5

V

—

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2. Electrical Characteristics

Table 2.20

Output Voltage (3)

Conditions: 4.0 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Low-level output All output ports

voltage (except for RIIC

Symbol

V_OL

Min.

—

Max.

0.8

Unit

V

Test Conditions

I_OL= 2.0 mA

Normal drive output mode

High-drive output mode

—

0.8

I_OL= 4.0 mA

pins)

RIIC pins

Normal drive output mode

High-drive output mode

Normal drive output mode

High-drive output mode

—

0.4

0.6

—

I_OL= 3.0 mA

I_OL= 6.0 mA

I_OH= –2.0 mA

—

High-level output All output ports

voltage

V_OH

VCC – 0.8

V

—

I

_OH= –4.0 mA

Table 2.21

Item

Thermal resistance

Thermal Resistance Value (Reference)

Package

Symbol

Max.

50.7

18.8

1.07

0.07

Unit

Test Conditions

48-pin LFQFP (PLQP0048KB-B)

40-pin HWQFN (PWQN0040KC-A)

48-pin LFQFP (PLQP0048KB-B)

40-pin HWQFN (PWQN0040KC-A)

_ja

°C/W

JESD51-2 and

JESD51-7 compliant

_jt

°C/W

JESD51-2 and

JESD51-7 compliant

Note:

The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of

the board. For details, refer to the JEDEC standards.

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2. Electrical Characteristics

2.3.1

Typical I/O Pin Output Characteristics (1)

Figure 2.22 to Figure 2.26 show the characteristics when normal drive output is selected by the drive capacity control

register.

I_OH/I_OLvs V_OH/V_OL

50

VCC = 5.5V

40

30

VCC = 3.3V

20

VCC = 2.7V

10

VCC = 1.8V

0

VCC = 1.8V

–10

VCC = 2.7V

–20

VCC = 3.3V

–30

–40

–50

VCC = 5.5V

–60

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.22

V_OH/V_OLand I_OH/I_OLVoltage Characteristics at T_a= 25°C When Normal Drive Output is Selected

(Reference Data)

I_OH/I_OLvs V_OH/V_OL

8

6

Ta = –40°C

Ta = 25°C

4

Ta = 105°C

2

0

–2

Ta = 105°C

–4

–6

–8

Ta = 25°C

Ta = –40°C

1.6

1.8

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

2.0

V_OH/V_OL[V]

Figure 2.23

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 1.8 V When Normal Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

20

15

10

5

Ta = –40°C

Ta = 25°C

Ta = 105°C

0

–5

Ta = 105°C

–10

Ta = 25°C

–15

Ta = –40°C

–20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_OH/V_OL[V]

Figure 2.24

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 2.7 V When Normal Drive Output is

Selected (Reference Data)

I_OH/I_OLvs V_OH/V_OL

30

20

Ta = –40°C

Ta = 25°C

Ta = 105°C

10

0

–10

Ta = 105°C

–20

–30

Ta = 25°C

Ta = –40°C

3.5

0.0

0.5

1.0

1.5

2.0

3.0

2.5

V_OH/V_OL[V]

Figure 2.25

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 3.3 V When Normal Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

60

40

Ta = –40°C

Ta = 25°C

Ta = 105°C

20

0

–20

Ta = 105°C

–40

Ta = 25°C

Ta = –40°C

–60

0

1

2

5

3

4

6

V_OH/V_OL[V]

Figure 2.26

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 5.5 V When Normal Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

2.3.2

Typical I/O Pin Output Characteristics (2)

Figure 2.27 to Figure 2.31 show the characteristics when high-drive output is selected by the drive capacity control

register.

I_OH/I_OLvs V_OH/V_OL

150

VCC = 5.5V

100

VCC = 3.3V

50

VCC = 2.7V

VCC = 1.8V

0

VCC = 1.8V

VCC = 2.7V

–50

VCC = 3.3V

–100

VCC = 5.5V

–150

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.27

V_OH/V_OLand I_OH/I_OLVoltage Characteristics at T_a= 25°C When High-Drive Output is Selected

(Reference Data)

I_OH/I_OLvs V_OH/V_OL

16

12

8

Ta = –40°C

Ta = 25°C

Ta = 105°C

4

0

–4

Ta = 105°C

–8

–12

–16

Ta = 25°C

Ta = –40°C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

V_OH/V_OL[V]

Figure 2.28

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 1.8 V When High-Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

50

40

30

20

10

0

Ta = –40°C

Ta = 25°C

Ta = 105°C

–10

–20

Ta = 105°C

Ta = 25°C

–30

–40

–50

Ta = –40°C

3.0

1.0

1.5

2.5

0.0

0.5

2.0

V_OH/V_OL[V]

Figure 2.29

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 2.7 V When High-Drive Output is

Selected (Reference Data)

I_OH/I_OLvs V_OH/V_OL

60

40

20

0

Ta = –40°C

Ta = 25°C

Ta = 105°C

–20

Ta = 105°C

–40

Ta = 25°C

Ta = –40°C

–60

3.0

3.5

1.0

1.5

2.5

0.0

0.5

2.0

V_OH/V_OL[V]

Figure 2.30

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 3.3 V When High-Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

150

100

Ta = –40°C

Ta = 25°C

Ta = 105°C

50

0

–50

Ta = 105°C

–100

–150

Ta = 25°C

Ta = –40°C

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.31

V_OH/V_OLand I_OH/I_OLTemperature Characteristics at VCC = 5.5 V When High-Drive Output is

Selected (Reference Data)

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2. Electrical Characteristics

2.3.3

Typical I/O Pin Output Characteristics (3)

Figure 2.32 to Figure 2.35 show the characteristics of the RIIC output pin.

I_OLvs V_OL

120

VCC = 5.5V

100

80

60

VCC = 3.3V

40

VCC = 2.7V

20

0

1

2

3

4

5

6

V_OL[V]

Figure 2.32

V_OLand I_OLVoltage Characteristics of RIIC Output Pin at T_a= 25°C (Reference Data)

I_OLvs V_OL

40

35

30

25

20

15

10

5

Ta = –40°C

Ta = 25°C

Ta = 105°C

0

0.0

2.5

0.5

1.0

1.5

2.0

3.0

V_OL[V]

Figure 2.33

V_OLand I_OLTemperature Characteristics of RIIC Output Pin at VCC = 2.7 V (Reference Data)

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2. Electrical Characteristics

I_OLvs V_OL

60

Ta = –40°C

Ta = 25°C

Ta = 105°C

50

40

30

20

10

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_OL[V]

Figure 2.34

V_OLand I_OLTemperature Characteristics of RIIC Output Pin at VCC = 3.3 V (Reference Data)

I_OLvs V_OL

140

Ta = –40°C

Ta = 25°C

120

100

80

Ta = 105°C

60

40

20

0

1

2

3

4

5

6

V_OL[V]

Figure 2.35

V_OLand I_OLTemperature Characteristics of RIIC Output Pin at VCC = 5.5 V (Reference Data)

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2. Electrical Characteristics

2.4

AC Characteristics

2.4.1

Clock Timing

Table 2.22

Operating Frequency Value (High-Speed Operating Mode)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

VCC

Item

Symbol

f_max

Unit

1.8 V ≤ VCC 2.4 V ≤ VCC 2.7 V ≤ VCC

< 2.4 V

< 2.7 V

≤ 5.5 V

Maximum operating

frequency*³

System clock (ICLK)

8

16

32

MHz

FlashIF clock (FCLK)*^1,

*

16

32

2

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKD)

16

32

16

32

16

32

Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When FCLK is in use at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of FCLK must be within ±3.5%.

Note 3. The maximum operating frequency listed above does not include errors of the external oscillator and internal oscillator. For

details on the range for the guaranteed operation, see Table 2.24, Clock Timing.

Table 2.23

Operating Frequency Value (Middle-Speed Operating Mode)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

VCC

Item

Symbol

f_max

Unit

1.8 V ≤ VCC 2.4 V ≤ VCC 2.7 V ≤ VCC

< 2.4 V

< 2.7 V

≤ 5.5 V

Maximum operating

frequency*³

System clock (ICLK)

8

12

MHz

FlashIF clock (FCLK)*^1,

*

12

2

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKD)

12

Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below 4

MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of FCLK must be within ±3.5%.

Note 3. The maximum operating frequency listed above does not include errors of the external oscillator and internal oscillator. For

details on the range for the guaranteed operation, see Table 2.24, Clock Timing.

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2. Electrical Characteristics

Table 2.24

Clock Timing

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Item

Symbol

t_Xcyc

t_XH

Min.

50

20

—

0.5

1

Typ.

—

3

Max.

—

5

Unit

ns

Test Conditions

Figure 2.36

EXTAL external clock input cycle time

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rise time

ns

t_XL

ns

t_Xr

ns

EXTAL external clock fall time

t_Xf

5

ns

EXTAL external clock input wait time*¹

t_XWT

f_MAIN

—

20

8

μs

Main clock oscillator oscillation

frequency*²

2.4 ≤ VCC ≤ 5.5

1.8 ≤ VCC < 2.4

MHz

1

Main clock oscillation stabilization time (crystal)*²

t_MAINOSC

—

ms

μs

Figure 2.37

Figure 2.38

Main clock oscillation stabilization time (ceramic

resonator)*²

50

LOCO clock oscillation frequency

f_LOCO

t_LOCO

f_ILOCO

t_ILOCO

f_HOCO

3.44

—

4.00

—

4.56

0.5

MHz

μs

LOCO clock oscillation stabilization time

IWDT-dedicated clock oscillation frequency

IWDT-dedicated clock oscillation stabilization time

HOCO clock oscillation frequency

12.75

—

15.00

—

17.25

50

kHz

μs

Figure 2.39

31.52

31.68

31.36

—

32.00

—

32.48

32.32

32.64

41.3

8

MHz

T_a= –40 to +85°C

T_a= –20 to +85°C

T_a= –40 to +105°C

Figure 2.41

HOCO clock oscillation stabilization time

PLL input frequency*³

t_HOCO

f_PLLIN

f_PLL

μs

4

—

MHz

μs

PLL circuit oscillation frequency*³

PLL clock oscillation stabilization time

PLL free-running oscillation frequency

24

—

32

t_PLL

—

74.4

—

Figure 2.42

f_PLLFR

—

8

MHz

Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating).

Note 2. Reference values when an 8-MHz resonator is used.

When specifying the main clock oscillator stabilization time, set the MOSCWTCR register with a stabilization time value that is

equal to or greater than the resonator-manufacturer-recommended value.

After the MOSCCR.MOSTP bit is changed to enable the main clock oscillator, confirm that the OSCOVFSR.MOOVF flag has

become 1, and then start using the main clock.

Note 3. The VCC range should be 2.4 to 5.5 V when the PLL is used.

t_Xcyc

t_XH

t_XL

EXTAL external clock input

0.5 × VCC

t_Xr

t_Xf

Figure 2.36

EXTAL External Clock Input Timing

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2. Electrical Characteristics

MOSCCR.MOSTP

t_MAINOSC

Main clock oscillator output

Figure 2.37

Main Clock Oscillation Start Timing

LOCOCR.LCSTP

t_LOCO

LOCO clock oscillator output

Figure 2.38

LOCO Clock Oscillation Start Timing

ILOCOCR.ILCSTP

t_ILOCO

IWDT-dedicated clock oscillator output

Figure 2.39

IWDT-Dedicated Clock Oscillation Start Timing

RES#

Internal reset

t_RESWT

OFS1.HOCOEN

HOCO clock

Figure 2.40

HOCO Clock Oscillation Start Timing

(After Release from a Reset by Setting OFS1.HOCOEN Bit to 0)

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2. Electrical Characteristics

HOCOCR.HCSTP

HOCO clock

t_HOCO

Figure 2.41

HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting HOCOCR.HCSTP Bit)

MOSCCR.MOSTP

t_MAINOSC

Main clock oscillator output

PLLCR2.PLLEN

t_PLL

PLL clock

Figure 2.42

PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has Been

Stabled)

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2. Electrical Characteristics

2.4.2

Reset Timing

Table 2.25

Reset Timing

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Item

Symbol

t_RESWP

t_RESW

Min.

3

Typ. Max.

Unit

ms

μs

Test Conditions

Figure 2.43

Figure 2.44

Figure 2.43

RES# pulse width

At power-on

Other than above

—

30

—

Wait time after release At normal startup*¹

t_RESWT

8.5

650

ms

μs

from the RES# pin

During fast startup time*²

reset (at power-on)

—

Wait time after release from the RES# pin reset

(from a warm start)

t_RESWT

—

310

1

—

μs

Figure 2.44

Independent watchdog timer reset period

t_RESWIW

IWDT clock Figure 2.45

cycle

Software reset period

t_RESWSW

t_RESWT2

—

1

—

ICLK cycle

μs

Wait time after release from the independent watchdog timer

reset*³

350

Wait time after release from the software reset

t_RESWT2

—

220

—

μs

Note 1. When the OFS1.LVDAS and OFS1.FASTSTUP bits are 1

Note 2. When the OFS1.LVDAS and/or OFS1.FASTSTUP bits are 0

Note 3. When the IWDTCR.CKS[3:0] bits are 0000b

VCC

RES#

t_RESWP

Internal reset

t_RESWT

Figure 2.43

Figure 2.44

Figure 2.45

Reset Input Timing at Power-On

t_RESW

RES#

Internal reset

t_RESWT

Reset Input Timing (1)

t_RESWIW, t_RESWSW

Independent watchdog timer reset

Software reset

Internal reset

t_RESWT2

Reset Input Timing (2)

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2. Electrical Characteristics

2.4.3

Timing of Recovery from Low Power Consumption Modes

Table 2.26

Timing of Recovery from Low Power Consumption Modes (1)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Test

Conditions

Item

Symbol Min.

Typ. Max.

Unit

Recovery time

from software

standby mode*¹

High-speed

mode

Crystal connected to Main clock oscillator t_SBYMC

main clock oscillator operating*²

—

2

3

ms Figure 2.46

μs

External clock input Main clock oscillator t_SBYEX

35

50

to main clock

oscillator

operating*³

HOCO clock oscillator operating

LOCO clock oscillator operating

t_SBYHO

t_SBYLO

—

40

55

μs

Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. When multiple

oscillators are operating, the recovery time varies depending on the operating state of the oscillators that are not selected as the

system clock source. The above table applies when only the corresponding clock is operating.

Note 2. When the frequency of the crystal is 20 MHz

When the main clock oscillator wait control register (MOSCWTCR) is set to 04h

Note 3. When the frequency of the external clock is 20 MHz

When the main clock oscillator wait control register (MOSCWTCR) is set to 00h

Table 2.27

Timing of Recovery from Low Power Consumption Modes (2)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Test

Conditions

Item

Symbol Min.

Typ. Max.

Unit

Recovery time

from software

standby mode*¹

Middle-speed Crystal connected to Main clock oscillator t_SBYMC

mode

main clock oscillator operating*²

—

2

3

ms Figure 2.46

ms

Main clock oscillator t_SBYPC

and PLL circuit

operating*³

External clock input Main clock oscillator t_SBYEX

—

3

4

μs

to main clock

oscillator

operating*⁴

Main clock oscillator t_SBYPE

and PLL circuit

65

85

operating*⁵

HOCO clock oscillator operating*⁶

LOCO clock oscillator operating

t_SBYHO

t_SBYLO

—

40

5

50

7

μs

Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. When multiple

oscillators are operating, the recovery time varies depending on the operating state of the oscillators that are not selected as the

system clock source. The above table applies when only the corresponding clock is operating.

Note 2. When the frequency of the crystal is 12 MHz

When the main clock oscillator wait control register (MOSCWTCR) is set to 04h

Note 3. This is the case when PLL is selected as the system clock and its frequency division is set to be 12 MHz.

When the main clock oscillator wait control register (MOSCWTCR) is set to 04h

Note 4. When the frequency of the external clock is 12 MHz

When the main clock oscillator wait control register (MOSCWTCR) is set to 00h

Note 5. This is the case when PLL is selected as the system clock and its frequency division is set to be 12 MHz.

When the main clock oscillator wait control register (MOSCWTCR) is set to 00h

Note 6. This is the case when HOCO is selected as the system clock and its frequency division is set to be 8 MHz.

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2. Electrical Characteristics

Oscillator

ICLK

IRQ

Software standby mode

t_SBYMC,t_SBYPC,t_SBYEX,

t_SBYPE,t_SBYHO,t_SBYLO

Figure 2.46

Software Standby Mode Recovery Timing

Table 2.28

Timing of Recovery from Low Power Consumption Modes (3)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Item

Symbol

t_DSLP

Min.

—

Typ.

2.0

Max.

3.5

Unit

μs

Test Conditions

Figure 2.47

Recovery time from deep High-speed mode*²

sleep mode*¹

Middle-speed mode*³

t_DSLP

—

3.0

4.0

μs

Note 1. Oscillators continue oscillating in deep sleep mode.

Note 2. When the frequency of the system clock is 32 MHz

Note 3. When the frequency of the system clock is 12 MHz

Oscillator

ICLK

IRQ

Deep sleep mode

t_DSLP

Figure 2.47

Table 2.29

Deep Sleep Mode Recovery Timing

Operating Mode Transition Time

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Transition Time

Mode before Transition

Mode after Transition

ICLK Frequency

Unit

Min.

—

Typ.

10.0

37.5

Max.

—

High-speed operating mode

Middle-speed operating modes

High-speed operating mode

8 MHz

μs

Middle-speed operating modes

—

Note:

Values when the frequencies of PCLKA, PCLKB, PCLKD, and FCLK are not divided.

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2. Electrical Characteristics

2.4.4

Control Signal Timing

Table 2.30

Control Signal Timing

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

Min.

200

Typ. Max.

Unit

ns

Test Conditions

NMI pulse width t_NMIW

—

NMI digital filter is disabled

(NMIFLTE.NFLTEN = 0)

2 × t_Pcyc≤ 200 ns

2 × t_Pcyc> 200 ns

3 × t_NMICK≤ 200 ns

3 × t_NMICK> 200 ns

2 × t_Pcyc≤ 200 ns

2 × t_Pcyc> 200 ns

3 × t_IRQCK≤ 200 ns

3 × t_IRQCK> 200 ns

1

2 × t_Pcyc

200

*

NMI digital filter is enabled

(NMIFLTE.NFLTEN = 1)

2

3.5 × t_NMICK

*

IRQ pulse width t_IRQW

200

ns

IRQ digital filter is disabled

(IRQFLTE0.FLTENi = 0)

1

2 × t_Pcyc

200

*

IRQ digital filter is enabled

(IRQFLTE0.FLTENi = 1)

3

3.5 × t_IRQCK

*

Note:

200 ns minimum in software standby mode.

Note 1.

Note 2.

t

_Pcycindicates the cycle of PCLKB.

_NMICKindicates the cycle of the NMI digital filter sampling clock.

Note 3. t_IRQCKindicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).

NMI

t_NMIW

Figure 2.48

NMI Interrupt Input Timing

IRQi

t_IRQW

Figure 2.49

IRQ Interrupt Input Timing

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RX23E-A Group

2. Electrical Characteristics

2.4.5

Timing of On-Chip Peripheral Modules

Table 2.31

Timing of On-Chip Peripheral Modules (1)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

*1

Item

Symbol

Min.

1.5

2.5

—

Typ.

—

Max.

—

Unit

Test Conditions

I/O ports Input data pulse width

t

Figure 2.50

Figure 2.51

PRW

Pcyc

MTU

Input capture input pulse

width

Single-edge setting

Both-edge setting

t

—

TICW

—

Input capture input rise/fall time

Timer clock pulse width

t

,

—

0.1

µs/V

TICr

t

TICf

Single-edge setting

Both-edge setting

t

,

1.5

2.5

—

t

Figure 2.52

TCKWH

Pcyc

t

TCKWL

Phase counting

mode

Timer clock rise/fall time

t

,

—

0.1

µs/V

TCKr

t

TCKf

POE

POE# input pulse width

POE# input rise/fall time

t

1.5

—

t

Figure 2.53

POEW

Pcyc

t

,

0.1

µs/V

POEr

t

POEf

Output disable time

Transition of the

POE# signal level

t

—

5 PCLKB +

0.24

µs

Figure 2.54

POEDI

When detecting falling

edges (ICSRm.POEnM[1:0]

= 00 (m = 1, 2; n = 0 to 3, 8))

Simultaneous

conduction of

output pins

t

—

3 PCLKB +

0.2

µs

Figure 2.55

POEDO

Register setting

t

1 PCLKB +

0.2

Figure 2.56

Time for access to the

register is not included.

POEDS

Oscillation stop

detection

t

21

Figure 2.57

POEDOS

TMR

SCI

Timer clock pulse width

Single-edge setting

Both-edge setting

t

,

1.5

2.5

—

t

Pcyc

Figure 2.58

TMCWH

TMCWL

Timer clock rise/fall time

Input clock cycle time

t

,

0.1

µs/V

TMCr

t

TMCf

Asynchronous

t

4

6

—

t

Figure 2.59

Figure 2.60

Scyc

Pcyc

Clock synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

t

0.4

—

16

4

0.6

20

—

SCKW

Scyc

t

ns

SCKr

t

ns

SCKf

Output clock cycle time

Asynchronous

t

Scyc

Pcyc

Clock synchronous

—

Output clock pulse width

Output clock rise time

Output clock fall time

t

0.4

—

0.6

20

40

SCKW

Scyc

t

ns

SCKr

t

ns

SCKf

Transmit data Clock synchronous

t

TXD

delay time

(master)

Transmit data Clock

VCC ≥ 2.7 V

—

65

ns

delay time

(slave)

synchronous

VCC < 2.7 V

100

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RX23E-A Group

2. Electrical Characteristics

*1

Item

Receive data Clock

Symbol

Min.

65

Typ.

—

Max.

—

Unit

Test Conditions

SCI

VCC ≥ 2.7 V

VCC < 2.7 V

t

ns

Figure 2.60

RXS

setup time

(master)

synchronous

90

—

ns

Receive data Clock synchronous

40

—

ns

setup time

(slave)

Receive data Clock synchronous

hold time

t

40

—

ns

RXH

A/D

converter

Trigger input pulse width

t

1.5

t

Figure 2.61

TRGW

Pcyc

2

CAC

CACREF input pulse width

t

≤ t

> t

*

t

4.5 t +

cac

ns

Pcyc

cac

CACREF

3 t

Pcyc

*

5 t

+

cac

Pcyc

cac

6.5 t

Pcyc

CACREF input rise/fall time

t

,

—

0.1

—

µs/V

ns

CACREFr

CACREFf

4

CLKOUT CLKOUT pin output cycle*

VCC ≥ 2.7 V

VCC < 2.7 V

VCC ≥ 2.7 V

VCC < 2.7 V

VCC ≥ 2.7 V

VCC < 2.7 V

t

62.5

125

15

—

Figure 2.62

Ccyc

CLKOUT pin high pulse

t

—

ns

CH

3

width*

30

CLKOUT pin low pulse

t

15

CL

3

width*

30

CLKOUT pin output rise time VCC ≥ 2.7 V

VCC < 2.7 V

t

—

12

25

12

25

Cr

CLKOUT pin output fall time VCC ≥ 2.7 V

VCC < 2.7 V

t

—

Cf

Note 1.

Note 2.

t

: PCLK cycle

Pcyc

: CAC count clock source cycle

cac

Note 3. When the LOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 000b), set the clock output division ratio

selection to divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).

Note 4. When the EXTAL external clock input or an oscillator is used with divided by 1 (the CKOCR.CKOSEL[2:0] bits are 010b and the

CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.

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RX23E-A Group

2. Electrical Characteristics

Table 2.32

Timing of On-Chip Peripheral Modules (2)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C, C = 30 pF, when high-drive output is

a

selected by the drive capacity control register

Item

Master

Test

Conditions

Symbol

t_SPcyc

Min.

Max.

Unit

1

RSPI RSPCK clock

cycle

2

6

4096

—

t_Pcyc*

Figure 2.63

Slave

RSPCK clock

high pulse width

Master

t_SPCKWH(t_SPcyc– t_SPCKr

t_SPCKf)/2 – 3

–

—

ns

Slave

Master

Slave

(t_SPcyc– t_SPCKr

—

t

_SPCKf)/2

t_SPCKWL(t_SPcyc– t_SPCKr

_SPCKf)/2 – 3

(t_SPcyc– t_SPCKr

RSPCK clock

low pulse width

ns

t

_SPCKf)/2

RSPCK clock

rise/fall time

Output VCC ≥ 2.7 V

VCC < 2.7 V

Input

t_SPCKr

,

—

10

15

0.1

—

t_SPCKf

—

μs/V

Data input setup Master VCC ≥ 2.7 V

time

t_SU

10

ns Figure 2.64

to

VCC < 2.7 V

30

—

Figure 2.67

Slave

25

—

Data input hold Master RSPCK set to a division ratio

t_H

t_HF

t_H

t_Pcyc

—

ns

time

other than PCLKB divided by 2

RSPCK set to PCLKB divided

by 2

0

—

Slave

20

—

SSL setup time Master

Slave

t_LEAD–30 + N*²× t_SPcyc

6

ns

t_Pcyc

ns

—

SSL hold time

Master

Slave

t_LAG

–30 + N*³× t_SPcyc

—

6

—

0

—

t_Pcyc

ns

Data output

delay time

Master VCC ≥ 2.7 V

VCC < 2.7 V

t_OD

14

30

65

105

—

Slave VCC ≥ 2.7 V

VCC < 2.7 V

Data output hold Master

t_OH

ns

time

Slave

0

—

Successive

transmission

delay time

Master

t_TD

t_SPcyc+ 2 × t_Pcyc8 × t_SPcyc+ 2 ×

t_Pcyc

Slave

6 × t_Pcyc

—

10

15

1

MOSI and MISO Output VCC ≥ 2.7 V

t

_Dr, t_Df

ns

rise/fall time

VCC < 2.7 V

—

Input

—

μs

ns

μs

SSL rise/fall

time

Output VCC ≥ 2.7 V

VCC < 2.7 V

Input

t_SSLr

t_SSLf

,

—

10

15

1

—

Slave access time

VCC ≥ 2.7 V

VCC < 2.7 V

t_SA

—

6

t_PcycFigure 2.66,

Figure 2.67

—

7

Slave output release

time

VCC ≥ 2.7 V

VCC < 2.7 V

t_REL

—

5

t_Pcyc

—

6

Note 1. t_Pcyc: PCLK cycle

Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)

Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)

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2. Electrical Characteristics

Table 2.33

Timing of On-Chip Peripheral Modules (3)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Unit*¹

Item

Symbol

t_SPcyc

Min.

Max.

Conditions

Simple SCK clock cycle output (master)

4

6

65536

—

t_Pcyc

t_SPcyc

ns

Figure 2.63

SPI

SCK clock cycle input (slave)

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise/fall time

t_SPCKWH

t_SPCKWL

t_SPCKr, t_SPCKf

t_SU

0.4

—

65

95

40

3

0.6

20

—

Data input setup time (master)

VCC ≥ 2.7 V

VCC < 2.7 V

ns

Figure 2.64,

Figure 2.65

—

Data input setup time (slave)

Data input hold time

—

t_H

—

ns

SSL input setup time

t_LEAD

t_LAG

t_OD

—

t_SPcyc

ns

SSL input hold time

3

—

Data output delay time (master)

Data output delay time (slave)

—

–10

–20

–10

—

40

65

100

—

VCC ≥ 2.7 V

VCC < 2.7 V

VCC ≥ 2.7 V

VCC < 2.7 V

Data output hold time (master)

t_OH

ns

—

Data output hold time (slave)

Data rise/fall time

—

t

_Dr, t_Df

_SSLr, t_SSLf

t_SA

20

6

ns

SSL input rise/fall time

Slave access time

t

t_Pcyc

Figure 2.66,

Figure 2.67

Slave output release time

t_REL

6

Note 1. t_Pcyc: PCLK cycle

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RX23E-A Group

2. Electrical Characteristics

Table 2.34

Timing of On-Chip Peripheral Modules (4)

Conditions: 2.7 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Conditions

2

Item

Symbol

Min.*^1,

*

Max.

Unit

RIIC

(Standard

mode, SMBus)

SCL cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 1300

—

ns

pF

ns

pF

Figure 2.68

SCL high pulse width

SCL low pulse width

3 (6) × t_IICcyc+ 300

—

3 (6) × t_IICcyc+ 300

—

SCL, SDA rise time

—

1000

SCL, SDA fall time

t_Sf

—

300

SCL, SDA spike pulse removal time

SDA bus free time

t_SP

0

1 (4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

3 (6) × t_IICcyc+ 300

—

START condition hold time

Repeated START condition setup time

STOP condition setup time

Data setup time

t_IICcyc+ 300

—

1000

—

1000

—

t_IICcyc+ 50

—

Data hold time

0

—

SCL, SDA capacitive load

SCL cycle time

—

400

RIIC

(Fast mode)

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 600

—

Figure 2.68

SCL high pulse width

SCL low pulse width

3 (6) × t_IICcyc+ 300

—

3 (6) × t_IICcyc+ 300

—

SCL, SDA rise time

—

300

SCL, SDA fall time

t_Sf

—

300

SCL, SDA spike pulse removal time

SDA bus free time

t_SP

0

1 (4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

3 (6) × t_IICcyc+ 300

—

START condition hold time

Repeated START condition setup time

STOP condition setup time

Data setup time

t_IICcyc+ 300

300

—

300

—

t_IICcyc+ 50

—

Data hold time

0

—

SCL, SDA capacitive load

—

400

Note:

t_IICcyc: RIIC internal reference clock (IICφ) cycle

Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE

bit = 1.

Note 2. C_bis the total capacitance of the bus lines.

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2. Electrical Characteristics

Table 2.35

Timing of On-Chip Peripheral Modules (5)

Conditions: 2.7 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Conditions

Item

Symbol

Min.*¹

Max.

Unit

Simple I²C

(Standard mode)

SDA rise time

t_Sr

t_Sf

—

0

1000

300

ns

pF

ns

pF

Figure 2.68

SDA fall time

SDA spike pulse removal time

Data setup time

t_SP

4 × t_Pcyc

—

t_SDAS

t_SDAH

C_b

250

0

Data hold time

—

SCL, SDA capacitive load

SDA rise time

—

0

400

Simple I²C

(Fast mode)

t_Sr

300

Figure 2.68

SDA fall time

t_Sf

300

SDA spike pulse removal time

Data setup time

t_SP

4 × t_Pcyc

—

t_SDAS

t_SDAH

C_b

100

0

Data hold time

—

SCL, SDA capacitive load

—

400

Note:

t_Pcyc: PCLK cycle

Note 1. C_bis the total capacitance of the bus lines.

PCLK

Port

t_PRW

Figure 2.50

I/O Port Input Timing

PCLK

Output

compare output

Input capture

input

t_TICW

t_TICr

t_TICf

Figure 2.51

MTU Input/Output Timing

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2. Electrical Characteristics

PCLK

MTCLKA to MTCLKD

t_TCKWL

t_TCKWH

t_TCKr

t_TCKf

Figure 2.52

MTU Clock Input Timing

PCLK

POEn# input

t_POEW

t_POEf

t_POEr

Figure 2.53

POE Input Timing (n = 0 to 3, 8)

POEn# input

t_POEW

Outputs disabled

MTU PWM output pins

t_POEDI

Figure 2.54

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Simultaneous active-level outputs detected*¹

Outputs

MTU PWM output pins

disabled

t_POEDO

Note 1. When the active level is set to low.

Figure 2.55

Output Disable Time for POE in Response to the Simultaneous Conduction of Output Pins

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2. Electrical Characteristics

Corresponding bit in

the SPOER register

Outputs disabled

MTU PWM output pins

t_POEDS

Figure 2.56

Output Disable Time for POE in Response to the Register Setting

Main clock

Oscillation stop detection

signal (internal signal)

Outputs disabled

MTU PWM output pins

t_POEDOS

Figure 2.57

Output Disable Time for POE in Response to the Oscillation Stop Detection

PCLK

TMCI0 to TMCI3

t_TMCWL

t_TMCWH

t_TMCr

t_TMCf

Figure 2.58

TMR Clock Input Timing

t_SCKW

t_SCKr

t_SCKf

SCKn

t_Scyc

Figure 2.59

SCK Clock Input Timing (n = 1, 5, 6, 12)

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2. Electrical Characteristics

SCKn

TXDn

RXDn

t_TXD

t_RXSt_RXH

Figure 2.60

SCI Input/Output Timing: Clock Synchronous Mode (n = 1, 5, 6, 12)

PCLK

ADTRG0#

t_TRGW

Figure 2.61

A/D Converter External Trigger Input Timing

t_Ccyc

t_CH

t_Cf

CLKOUT pin output

t_Cr

t_CL

Test conditions: V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, I_OH= -1.0 mA, I_OL= 1.0 mA, C = 30 pF

Figure 2.62

CLKOUT Output Timing

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RX23E-A Group

2. Electrical Characteristics

t_SPCKr

t_SPCKf

t_SPCKWH

RSPI

Simple SPI

V_OH

V_OL

V_OH

V_OL

t_SPCKWL

V_OL

RSPCKA

Master select output

SCKn

Master select output

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

V_IL

t_SPCKWL

V_IL

RSPCKA

Slave select input

SCKn

Slave select input

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.63

RSPI Clock Timing and Simple SPI Clock Timing (n = 1, 5, 6, 12)

RSPI

Simple SPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 0

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 2.64

RSPI Timing (Master, CPHA = 0) and Simple SPI Clock Timing (Master, CKPH = 1) (n = 1, 5, 6, 12)

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2. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 1

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 2.65

RSPI Timing (Master, CPHA = 1) and Simple SPI Clock Timing (Master, CKPH = 0) (n = 1, 5, 6, 12)

RSPI

Simple SPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 0

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOA

output

SMISOn

output

MSB OUT

t_H

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

Figure 2.66

RSPI Timing (Slave, CPHA = 0) and Simple SPI Clock Timing (Slave, CKPH = 1) (n = 1, 5, 6, 12)

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RX23E-A Group

2. Electrical Characteristics

RSPI

Simple SPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 1

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

LSB OUT

(Last data)

MISOA

output

SMISOn

output

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

t_SU

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

LSB IN

MSB IN

Figure 2.67

RSPI Timing (Slave, CPHA = 1) and Simple SPI Clock Timing (Slave, CKPH = 0) (n = 1, 5, 6, 12)

V_IH

V_IL

SDA

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL

*1

P

S

Sr^*1

P

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Test conditions

V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Note 1. S, P, and Sr indicate the following conditions, respectively.

S: START condition

P: STOP condition

Sr: Repeated START condition

Figure 2.68

RIIC Bus Interface Input/Output Timing and Simple I²C Bus Interface Input/Output Timing

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RX23E-A Group

2. Electrical Characteristics

2.5

Characteristics of Power-On Reset Circuit and Voltage Detection Circuit

Table 2.36

Characteristics of Power-On Reset Circuit and Voltage Detection Circuit (1)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Power-on reset (POR)

Symbol

V_POR

Min.

1.35

3.67

2.70

2.37

1.80

4.12

3.98

3.86

3.68

2.99

2.89

2.79

2.68

2.57

2.47

2.37

2.10

1.86

1.80

4.08

3.95

3.82

3.62

Typ.

1.50

3.84

2.82

2.51

1.90

4.29

4.14

4.02

3.84

3.10

3.00

2.90

2.79

2.68

2.58

2.48

2.20

1.96

1.86

4.29

4.14

4.02

3.84

Max.

1.65

3.97

3.00

2.67

1.99

4.42

4.28

4.16

3.98

3.29

3.19

3.09

2.98

2.87

2.67

2.57

2.30

2.06

1.96

4.48

4.35

4.22

4.02

Unit

V

Test Conditions

Voltage detection

level

Figure 2.69, Figure 2.70

Voltage detection circuit

(LVD0)*¹

V_{det0_0}

V_{det0_1}

V_{det0_2}

V_{det0_3}

V_{det1_0}

V_{det1_1}

V_{det1_2}

V_{det1_3}

V_{det1_4}

V_{det1_5}

V_{det1_6}

V_{det1_7}

V_{det1_8}

V_{det1_9}

V_{det1_A}

V_{det1_B}

V_{det1_C}

V_{det1_D}

V_{det2_0}

V_{det2_1}

V_{det2_2}

V_{det2_3}

V

Figure 2.71

At falling edge VCC

Voltage detection circuit

(LVD1)*²

V

Figure 2.72

At falling edge VCC

Voltage detection circuit

(LVD2)*³

V

Figure 2.73

At falling edge VCC

Note:

These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage

detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used

for voltage detection.

Note 1. n in the symbol Vdet0_n denotes the value of the OFS1.VDSEL[1:0] bits.

Note 2. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.

Note 3. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[1:0] bits.

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 62 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.37

Characteristics of Power-On Reset Circuit and Voltage Detection Circuit (2)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

t_POR

Min.

—

Typ.

9.1

Max.

—

Unit

ms

Test Conditions

Figure 2.70

Wait time after

release from the

power-on reset

At normal startup

During fast startup time

t_POR

—

1.6

—

Wait time after release from voltage monitoring 0

reset

t_LVD0

t_LVD1

t_LVD2

—

600

150

—

μs

Figure 2.71

Figure 2.72

Figure 2.73

Figure 2.69

Wait time after release from voltage monitoring 1

reset

Wait time after release from voltage monitoring 2

reset

Response delay time

t_det

—

350

—

μs

Minimum VCC down time*¹

t_VOFF

350

Figure 2.69, VCC = 1.0 V or

above

Power-on reset enable time

t_W(POR)

Td_(E-A)

1

—

ms

μs

Figure 2.70, VCC = below 1.0

V

LVD operation stabilization time (after LVD is

enabled)

—

300

Figure 2.72, Figure 2.73

Hysteresis width (power-on rest (POR))

V_PORH

V_LVH

—

110

70

—

mV

Hysteresis width (voltage detection circuit: LVD0,

LVD1 and LVD2)

When Vdet1_0 to Vdet1_4 is

selected

—

60

50

40

60

—

When Vdet1_5 to Vdet1_9 is

selected

When Vdet1_A or Vdet1_B is

selected

When Vdet1_C or Vdet1_D is

selected

When LVD0 or LVD2 is

selected

Note:

These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage

detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used

for voltage detection.

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0

,

V_det1, and V_det2for the POR/LVD.

t_VOFF

VCC

V_PORH

V_POR

1.0V

Internal reset signal

(active-low)

t_det

t_dett_POR

Figure 2.69

Voltage Detection Reset Timing

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 63 of 98

RX23E-A Group

2. Electrical Characteristics

V_PORH

V_POR

VCC

1.0 V

t_w(POR)

*1

Internal reset signal

(active-low)

t_dett_POR

Note 1. t_w(POR)is the time required for a power-on reset to be enabled while the external power VCC is being held below the

valid voltage (1.0 V).

When turning the VCC on, maintain a voltage below 1.0V for at least 1.0ms.

Figure 2.70

Power-On Reset Timing

t_VOFF

V_LVH

VCC

V_det0

Internal reset signal

(active-low)

t_det

t_LVD0

t_det

Figure 2.71

Voltage Detection Circuit Timing (Vdet0)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 64 of 98

RX23E-A Group

2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det1

LVD1E

T_d(E-A)

LVD1

Comparator output

LVD1CMPE

LVD1MON

Internal reset signal

(active-low)

When LVD1RN = L

t_det

t_LVD1

t_det

When LVD1RN = H

t_LVD1

Figure 2.72

Voltage Detection Circuit Timing (V_det1

)

t_VOFF

V_LVH

VCC

V_det2

LVD2E

T_d(E-A)

LVD2

Comparator output

LVD2CMPE

LVD2MON

Internal reset signal

(active-low)

When LVD2RN = L

t_det

t_LVD2

When LVD2RN = H

t_LVD2

Figure 2.73

Voltage Detection Circuit Timing (V_det2)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 65 of 98

RX23E-A Group

2. Electrical Characteristics

2.6

Oscillation Stop Detection Timing

Table 2.38

Oscillation Stop Detection Timing

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C

a

Item

Symbol

t_dr

Min.

—

Typ.

—

Max.

1

Unit

ms

Test Conditions

Figure 2.74

Detection time

Main clock

t_dr

OSTDSR.OSTDF

PLL clock

OSTDSR.OSTDF

Low-speed clock

ICLK

Low-speed clock

ICLK

When the main clock is selected

When the PLL clock is selected

Figure 2.74

Oscillation Stop Detection Timing

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 66 of 98

RX23E-A Group

2. Electrical Characteristics

2.7

ROM (Code Flash Memory) Characteristics

Table 2.39

ROM (Code Flash Memory) Characteristics (1)

Item

Program/erase cycles*¹

Symbol

N_PEC

t_DRP

Min.

Typ.

—

Max.

—

Unit

Times

Year

Conditions

1000

3

Data retention

After 1000 times of erase

20*^2,

*

—

T_a= 85°C

Note 1. Definition of program/erase cycle:

The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block

can be erased n times. For instance, when 4-byte program is performed 256 times for different addresses in a 1-Kbyte block and

then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more

than once before the next erase cycle (overwriting is prohibited).

Note 2. Characteristic when using the flash programmer and the self-programming library provided from Renesas Electronics.

Note 3. This result is obtained from reliability testing.

Table 2.40

ROM (Code Flash Memory) Characteristics (2) (High-Speed Operating Mode)

Conditions: 2.7 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V

Temperature range for the programming/erasure operation: T = –40 to +105°C

a

FCLK = 1 MHz

FCLK = 32 MHz

Item

8-byte

Symbol

Unit

Min.

—

Typ.

112.0

8.7

Max.

967.0

278.1

9813.6

Min.

—

Typ.

52.3

5.5

Max.

490.5

214.6

1049.2

Program time

Erase time

t_P8

t_E2K

μs

ms

2-Kbyte

—

256-Kbyte

t_E256K

—

469.1

—

41.2

(when block erase

command is used)

256-Kbyte

t_EA256K

—

463.9

9609.0

—

36.0

839.5

ms

(when all-block erase

command is used)

Blank check time

8-byte

t_BC8

t_BC2K

t_SED

t_SAS

t_AWS

t_DIS

—

55.0

1840.0

18.0

566.5

—

16.1

135.7

10.7

433.5

—

μs

ms

μs

2-Kbyte

Erase operation forced stop time

Start-up area switching time

—

12.3

—

6.2

—

Access window setting time

—

ROM mode transition wait time 1

ROM mode transition wait time 2

2.0

5.0

2.0

5.0

t_MS

—

Note:

The time until each operation of the flash memory is started after instructions are executed by software is not included.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be within ±3.5%.

Note:

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 67 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.41

ROM (Code Flash Memory) Characteristics (3) (Middle-Speed Operating Mode)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V

Temperature range for the programming/erasure operation: T = –40 to +85°C

a

FCLK = 1 MHz

FCLK = 8 MHz

Unit

Item

8-byte

Symbol

Min.

—

Typ.

152.0

8.8

Max.

1367.0

279.7

Min.

—

Typ.

97.9

5.9

Max.

936.0

220.8

2260.1

Program time

Erase time

t_P8

t_E2K

μs

ms

2-Kbyte

—

256-Kbyte

t_E256K

—

469.2

9816.9

—

100.5

(when block erase

command is used)

256-Kbyte

t_EA256K

—

464.0

9610.7

—

95.3

2053.7

ms

(when all-block erase

command is used)

Blank check time

8-byte

t_BC8

t_BC2K

t_SED

t_SAS

t_AWS

t_DIS

—

85.0

1870.0

28.0

573.3

—

50.9

401.5

21.3

450.1

—

μs

ms

μs

2-Kbyte

Erase operation forced stop time

Start-up area switching time

—

13.0

—

7.7

—

Access window setting time

—

ROM mode transition wait time 1

ROM mode transition wait time 2

2.0

3.0

2.0

3.0

t_MS

—

Note:

The time until each operation of the flash memory is started after instructions are executed by software is not included.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be within ±3.5%.

Note:

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 68 of 98

RX23E-A Group

2. Electrical Characteristics

2.8

E2 DataFlash (Data Flash Memory) Characteristics

Table 2.42

E2 DataFlash Characteristics (1)

Item Symbol

Program/erase cycles*¹

N_DPEC

Data retention After 10000 times of erase t_DDRP

Min.

Typ.

1000000

—

Max.

—

Unit

Conditions

100000

Times

Year

20*^2,

*

—

T_a= 85°C

3

After 100000 times of erase

After 1000000 times of erase

5*^2,

—

*

—

3

1*^2,

*

—

T_a= 25°C

Note 1. Definition of program/erase cycle:

The program/erase cycle is the number of erasing for each block. When the number of program/erase cycle is n, each block can

be erased n times. For instance, when 1-byte program is performed 1000 times for different addresses in a 1-Kbyte block and

then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more

than once before the next erase cycle (overwriting is prohibited).

Note 2. Characteristic when the flash programmer is used and the self-programming library is provided from Renesas Electronics.

Note 3. These results are obtained from reliability testing.

Table 2.43

E2 DataFlash Characteristics (2) (High-Speed Operating Mode)

Conditions: 2.7 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V

Temperature range for the programming/erasure operation: T = –40 to +105°C

a

FCLK = 1 MHz

FCLK = 32 MHz

Item

Symbol

Unit

Min.

—

Typ.

95.0

19.5

119.8

—

Max.

797.0

498.5

2555.7

55.0

Min.

—

Typ.

40.8

6.2

12.9

—

Max.

375.5

229.4

367.2

16.1

Program time

Erase time

1 byte

t_DP1

t_DE1K

t_DE8K

t_DBC1

t_DBC1K

t_DSED

t_DSTOP

μs

ms

μs

1 Kbyte

8 Kbyte

1 byte

—

Blank check time

—

1 Kbyte

—

7216.0

16.0

—

495.7

10.7

Erase operation forced stop time

DataFlash STOP recovery time

—

5.0

—

5.0

—

Note:

The time until each operation of the flash memory is started after instructions are executed by software is not included.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be within ±3.5%.

Note:

Table 2.44

E2 DataFlash Characteristics (3) (Middle-Speed Operating Mode)

Conditions: 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V

Temperature range for the programming/erasure operation: T = –40 to +85°C

a

FCLK = 1 MHz

FCLK = 8 MHz

Item

Programming time

Symbol

Unit

Min.

—

Typ.

135.0

19.6

119.9

—

Max.

1197.0

500.1

2557.4

85.0

Min.

—

Typ.

86.5

8.0

27.7

—

Max.

822.5

264.1

668.2

50.9

1 byte

t_DP1

t_DE1K

t_DE8K

t_DBC1

t_DBC1K

t_DSED

t_DSTOP

μs

ms

μs

Erasure time

1 Kbyte

8 Kbyte

1 byte

—

Blank check time

—

1 Kbyte

—

7246.0

28.0

—

1457.5

21.3

Erase operation forced stop time

DataFlash STOP recovery time

—

0.72

—

0.72

—

Note:

The time until each operation of the flash memory is started after instructions are executed by software is not included.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be within ±3.5%.

Note:

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 69 of 98

RX23E-A Group

2. Electrical Characteristics

2.9

24-Bit Delta-Sigma A/D Converter Characteristics

Table 2.45

24-Bit Delta-Sigma A/D Converter Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, V

= 2.5 V, T = –40 to +105°C

REF

a

Unit

—

Item

Symbol

Gain

f_DR

Min.

Typ.

Max.

Test Conditions

Gain

1, 2, 4, 8, 16, 32, 64, 128

Output data

rate

Normal mode

7.6

—

15625

SPS

Low power mode

1.9

24

—

3906

—

Resolution (no missing codes)

RMS noise

—

Bits

—

V_N

Table 2.46,

Table 2.48

—

Figure 2.75 to Figure 2.91

Integral non- Gain = 1 (PGA enabled),

INL

—

±7

±4

±5

±7

±15

±20

±30

ppmFSR Figure 2.92, Figure 2.93

AVCC0 = 3.6 to 5.5 V

linearity

Normal/low power mode,

OPCR.DSADLVM bit = 0

Gain = 2 to 64,

Normal/low power mode,

OPCR.DSADLVM bit = 0

Gain = 128,

Normal mode,

OPCR.DSADLVM bit = 0

Gain = 128,

Low power mode,

OPCR.DSADLVM bit = 0

Gain = 1 to 128

AVCC0 = 2.7 to 5.5 V

(PGA enabled),

Normal/low power mode,

OPCR.DSADLVM bit = 1

Gain = 1

(PGA disabled, BUF disabled)

—

±7

—

±20

—

AVCC0 = 2.7 to 5.5 V,

V_I< 2.6 V

Gain = 1

(PGA disabled, BUF enabled)

Offset error

Offset drift

Before calibration

E_O

±10

µV

Figure 2.94

AVCC0 = 5.0 V, T_a= 25°C,

Normal mode, Gain = 2

After calibration

—

Less than or

equal to the

RMS noise

—

Gain = 1 or 2 (PGA enabled)

Gain = 4 to 8

dE_O

—

60

40

15

10

50

220

140

40

nV/°C

Figure 2.94

Gain = 16 to 32

Gain = 64 to 128

25

Gain = 1

140

(PGA disabled, BUF disabled)

Gain error

Gain = 1 to 64

(PGA enabled)

E_G

—

±0.01

±0.03

%

Figure 2.95

T_a= 25°C

Gain = 128

—

±0.01

±0.04

Gain = 1

±0.015

(PGA disabled, BUF disabled)

Gain = 1

(PGA disabled, BUF enabled)

—

±0.03

—

After calibration of gain errors

Less than or

equal to the

RMS noise

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 70 of 98

RX23E-A Group

2. Electrical Characteristics

Item

Symbol

dE_G

Min.

—

Typ.

1

Max.

3

Unit

Test Conditions

Gain drift

Gain = 1 to 128

ppm/°C Figure 2.95

(PGA enabled),

OPCR.DSADLVM bit = 0

Gain = 1 to 128

(PGA enabled),

OPCR.DSADLVM bit = 1

—

1

5

AVCC0 = 3.0 to 5.5 V

—

10

AVCC0 < 3.0 V

Gain = 1 (PGA disabled)

—

1.4

—

Figure 2.95

V_I< 2.6 V

Power supply Gain = 1 (PGA enabled)

PSRR

80

89

88

95

—

dB

V_ID= 1 V/Gain (DC)

rejection ratio

Gain = 2 to 16

Gain = 32 to 128

102

68

115

88

Gain = 1

V_ID= 1 V (DC)

(PGA disabled, BUF disabled)

Gain = 1

(PGA disabled, BUF enabled)

—

95

78

100

120

130

100

120

130

88

—

Common

mode

rejection ratio

Gain = 1 to 8 (PGA enabled),

OPCR.DSADLVM bit = 0

CMRR

dB

V_ID= 1 V/Gain (DC)

Gain = 16 to 32,

OPCR.DSADLVM bit = 0

110

120

80

Gain = 64 to 128,

OPCR.DSADLVM bit = 0

Gain = 1 to 8 (PGA enabled),

OPCR.DSADLVM bit = 1

Gain = 16 to 32,

OPCR.DSADLVM bit = 1

88

Gain = 64 to 128,

OPCR.DSADLVM bit = 1

100

60

Gain = 1

(PGA disabled, BUF disabled)

V_ID= 1 V (DC)

Gain = 1

(PGA disabled, BUF enabled)

—

78

Normal mode External clock, 50 Hz, 60 Hz

rejection ratio

NMRR

120

75

—

dB

10 SPS, 50 ± 1 Hz,

60 ± 1 Hz

—

54 SPS, 50 ± 1 Hz,

60 ± 1 Hz

External clock, 50 Hz

External clock, 60 Hz

120

110

—

50SPS, 50 ± 1 Hz

60 SPS, 60 ± 1 Hz

Internal clock (HOCO),

50 Hz, 60 Hz

10 SPS, 50 ± 1 Hz,

60 ± 1 Hz

70

—

54 SPS, 50 ± 1 Hz,

60 ± 1 Hz

Internal clock (HOCO), 50 Hz

Internal clock (HOCO), 60 Hz

Burnout current

110

—

50 SPS, 50 ± 1 Hz

60 SPS, 60 ± 1 Hz

I_BO

0.5, 2, 4, 20

500

µA

Modulator

clock

Normal mode

f_MOD

430

570

kHz

Low power mode

107.5

125.0

142.5

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 71 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.46

Conditions: AVCC0 = 5.0 V, T = 25°C, f

Typical Noise Characteristics (Normal Mode)

= 500 kHz, V = 0 V, V = 2.5 V

REF

a

MOD

ID

f_DR

(SPS)

Gain = 1 Gain = 1 Gain = 1

OSR

Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128

(Bypass)

(BUF)

(PGA)

7.6

10

65536

0.383

(2.39)

0.524

(2.69)

0.601

(3.89)

0.563

(3.59)

0.284

(2.02)

0.166

(1.08)

0.097

(0.60)

0.052

(0.34)

0.036

(0.28)

0.029

(0.20)

50048

9984

9216

8320

4992

2560

1024

512

0.426

(2.64)

0.671

(3.96)

0.680

(4.40)

0.618

(4.18)

0.322

(2.53)

0.185

(1.15)

0.108

(0.71)

0.056

(0.40)

0.041

(0.27)

0.033

(0.20)

50

0.878

(5.42)

1.117

(7.59)

1.308

(9.76)

1.196

(7.59)

0.667

(5.15)

0.369

(2.51)

0.230

(1.69)

0.121

(0.92)

0.084

(0.61)

0.072

(0.52)

54

0.929

(6.35)

1.225

(9.71)

1.359

(10.5)

1.254

(9.52)

0.702

(4.85)

0.392

(2.85)

0.240

(1.70)

0.127

(0.88)

0.090

(0.59)

0.076

(0.51)

60

0.973

(7.31)

1.279

(8.99)

1.450

(10.7)

1.345

(9.27)

0.723

(4.50)

0.426

(3.30)

0.258

(1.48)

0.129

(1.07)

0.093

(0.59)

0.080

(0.58)

100

195

488

977

1953

3906

7813

15625

1.228

(8.67)

1.673

(11.4)

1.873

(13.0)

1.673

(9.76)

0.904

(5.96)

0.536

(3.46)

0.327

(2.41)

0.172

(1.19)

0.128

(0.96)

0.100

(0.68)

1.681

(12.7)

2.206

(18.6)

2.530

(16.7)

2.378

(16.7)

1.277

(8.45)

0.710

(4.65)

0.460

(3.15)

0.238

(1.55)

0.176

(1.16)

0.139

(0.90)

2.697

(17.3)

3.311

(22.4)

3.954

(29.3)

3.881

(27.4)

2.007

(13.5)

1.175

(8.52)

0.723

(4.73)

0.355

(2.28)

0.264

(1.80)

0.231

(1.55)

3.691

(27.5)

4.740

(29.0)

5.758

(36.5)

5.442

(35.7)

2.871

(20.0)

1.656

(12.0)

1.025

(6.67)

0.522

(3.53)

0.389

(2.57)

0.321

(2.21)

256

5.734

(35.3)

6.572

(42.5)

8.535

(55.3)

7.438

(48.9)

4.130

(28.2)

2.308

(15.8)

1.434

(9.34)

0.768

(4.85)

0.567

(4.05)

0.476

(2.71)

128

7.446

(51.1)

9.607

(65.8)

12.32

(70.0)

11.15

(76.5)

5.778

(38.6)

3.476

(27.2)

2.237

(14.7)

1.162

(7.83)

0.831

(5.98)

0.669

(4.21)

64

13.60

(102)

15.91

(110)

21.39

(143)

19.22

(120)

10.43

(67.6)

5.971

(39.0)

3.760

(26.4)

2.161

(13.9)

1.482

(11.0)

1.112

(6.96)

32

120.5

(644)

117.5

(720)

112.5

(735)

67.81

(347)

36.42

(218)

17.96

(109)

9.766

(58.7)

5.812

(37.6)

3.726

(22.2)

2.498

(16.9)

Note:

“Bypass” indicates the state where both PGA and BUF are disabled, “BUF” indicates the state where PGA is disabled and BUF

is enabled, and “PGA” indicates the state where PGA is enabled.

The upper rows indicate RMS noise (µV_RMS) and the lower rows (in parentheses) indicate peak-to-peak noise (µV_PP).

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 72 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.47

Conditions: AVCC0 = 5.0 V, T = 25°C, f

Effective Resolution (Normal Mode)

= 500 kHz, V = 0 V, V = 2.5 V

REF

a

MOD

ID

f_DR

(SPS)

Gain = 1 Gain = 1 Gain = 1

OSR

Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128

(Bypass)

(BUF)

(PGA)

7.6

10

65536

23.6

(21.0)

23.1

(20.8)

23.0

(20.3)

22.1

(19.4)

22.1

(19.2)

21.8

(19.1)

21.6

(19.0)

21.5

(18.8)

21.0

(18.1)

20.4

(17.6)

50048

9984

9216

8320

4992

2560

1024

512

23.5

(20.9)

22.8

(20.2)

22.8

(20.1)

22.0

(19.2)

21.9

(18.9)

21.7

(19.1)

21.5

(18.7)

21.4

(18.6)

20.9

(18.2)

20.2

(17.6)

50

22.4

(19.8)

22.0

(19.3)

21.9

(19.0)

21.0

(18.3)

20.8

(17.9)

20.7

(17.9)

20.4

(17.5)

20.3

(17.4)

19.8

(17.0)

19.0

(16.2)

54

22.4

(19.6)

21.9

(18.9)

21.8

(18.9)

20.9

(18.0)

20.8

(18.0)

20.6

(17.7)

20.3

(17.5)

20.2

(17.5)

19.7

(17.0)

19.0

(16.2)

60

22.3

(19.4)

21.8

(19.0)

21.7

(18.8)

20.8

(18.0)

20.7

(18.1)

20.5

(17.5)

20.2

(17.7)

20.2

(17.2)

19.7

(17.0)

18.9

(16.1)

100

195

488

977

1953

3906

7813

15625

22.0

(19.1)

21.5

(18.7)

21.4

(18.6)

20.5

(18.0)

20.4

(17.7)

20.2

(17.5)

19.9

(17.0)

19.8

(17.0)

19.2

(16.3)

18.6

(15.8)

21.5

(18.6)

21.1

(18.0)

21.0

(18.2)

20.0

(17.2)

19.9

(17.2)

19.8

(17.0)

19.4

(16.6)

19.3

(16.6)

18.8

(16.0)

18.1

(15.4)

20.8

(18.1)

20.5

(17.7)

20.3

(17.4)

19.3

(16.5)

19.3

(16.5)

19.0

(16.2)

18.7

(16.0)

18.8

(16.1)

18.2

(15.4)

17.4

(14.6)

20.4

(17.5)

20.0

(17.3)

19.7

(17.1)

18.8

(16.1)

18.7

(15.9)

18.5

(15.7)

18.2

(15.5)

18.2

(15.4)

17.6

(14.9)

16.9

(14.1)

256

19.7

(17.1)

19.5

(16.8)

19.2

(16.5)

18.4

(15.6)

18.2

(15.4)

18.1

(15.3)

17.7

(15.0)

17.6

(15.0)

17.1

(14.2)

16.3

(13.8)

128

19.4

(16.6)

18.9

(16.2)

18.6

(16.1)

17.8

(15.0)

17.7

(15.0)

17.5

(14.5)

17.1

(14.4)

17.0

(14.3)

16.5

(13.7)

15.8

(13.2)

64

18.5

(15.6)

18.2

(15.4)

17.8

(15.1)

17.0

(14.3)

16.9

(14.2)

16.7

(14.0)

16.3

(13.5)

16.1

(13.5)

15.7

(12.8)

15.1

(12.5)

32

15.3

15.4

15.2

15.1

15.0

14.7

14.4

13.9

(12.9)

(12.7)

(12.8)

(12.5)

(12.4)

(12.0)

(11.8)

(11.2)

Effective resolution = log (full-scale voltage/RMS noise)

2

Noise-free resolution = log (full-scale voltage/peak-to-peak noise)

2

Note:

“Bypass” indicates the state where both PGA and BUF are disabled, “BUF” indicates the state where PGA is disabled and BUF

is enabled, and “PGA” indicates the state where PGA is enabled.

Note:

The upper rows indicate effective resolution (bits) and the lower rows (in parentheses) indicate noise-free resolution (bits).

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 73 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.48

Conditions: AVCC0 = 5.0 V, T = 25°C, f

Typical Noise Characteristics (Low Power Mode)

= 125 kHz, V = 0 V, V = 2.5 V

REF

a

MOD

ID

f_DR

(SPS)

Gain = 1 Gain = 1 Gain = 1

OSR

Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128

(Bypass)

(BUF)

(PGA)

1.9

10

65536

0.463

(3.29)

0.640

(4.19)

0.892

(5.38)

0.708

(4.63)

0.444

(2.62)

0.245

(1.72)

0.140

(0.90)

0.070

(0.47)

0.048

(0.34)

0.038

(0.25)

12512

2496

2304

2080

1248

640

1.053

(7.03)

1.313

(8.79)

1.596

(11.4)

1.492

(10.6)

0.797

(5.27)

0.437

(2.86)

0.286

(1.79)

0.143

(1.00)

0.109

(0.72)

0.085

(0.61)

50

2.412

(15.7)

2.883

(18.4)

3.390

(21.7)

3.093

(22.5)

1.669

(11.0)

0.954

(5.96)

0.592

(3.86)

0.317

(2.35)

0.228

(1.69)

0.187

(1.22)

54

2.558

(19.4)

3.098

(20.5)

3.544

(23.9)

3.139

(19.4)

1.719

(11.3)

0.962

(6.39)

0.637

(3.92)

0.333

(2.12)

0.242

(1.81)

0.199

(1.39)

60

2.491

(16.3)

3.230

(20.8)

3.598

(26.4)

3.348

(25.0)

1.810

(13.6)

1.024

(7.38)

0.645

(4.50)

0.346

(2.30)

0.257

(1.88)

0.207

(1.37)

100

195

488

977

1953

3906

3.237

(21.7)

3.843

(26.6)

4.794

(32.5)

4.274

(27.1)

2.319

(15.3)

1.357

(9.35)

0.872

(6.37)

0.454

(2.98)

0.338

(2.29)

0.268

(1.83)

4.663

(37.7)

5.666

(37.7)

6.826

(46.5)

5.799

(39.7)

3.245

(21.3)

1.930

(12.9)

1.164

(7.50)

0.627

(4.61)

0.474

(3.31)

0.371

(2.68)

256

7.451

(46.6)

9.151

(62.5)

10.30

(70.9)

9.404

(59.6)

5.216

(35.7)

2.934

(20.2)

1.869

(13.6)

1.006

(6.13)

0.729

(5.46)

0.599

(4.56)

128

10.37

(72.4)

13.13

(83.1)

15.63

(111)

13.71

(93.3)

7.605

(63.0)

4.383

(30.3)

2.796

(18.0)

1.510

(9.78)

1.099

(7.60)

0.908

(7.23)

64

16.80

(117)

19.92

(153)

25.41

(177)

22.23

(138)

12.30

(94.9)

7.226

(50.9)

4.520

(30.6)

2.531

(16.2)

1.927

(13.6)

1.499

(11.1)

32

120.9

(720)

120.4

(761)

126.6

(634)

73.29

(507)

36.82

(216)

19.83

(124)

11.22

(78.4)

6.332

(39.1)

4.427

(27.3)

3.143

(20.0)

Note:

“Bypass” indicates the state where both PGA and BUF are disabled, “BUF” indicates the state where PGA is disabled and BUF

is enabled, and “PGA” indicates the state where PGA is enabled.

The upper rows indicate RMS noise (µV_RMS) and the lower rows (in parentheses) indicate peak-to-peak noise (µV_PP).

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 74 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.49

Conditions: AVCC0 = 5.0 V, T = 25°C, f

Effective Resolution (Low Power Mode)

= 125 kHz, V = 0 V, V = 2.5 V

REF

a

MOD

ID

f_DR

(SPS)

Gain = 1 Gain = 1 Gain = 1

OSR

Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128

(Bypass)

(BUF)

(PGA)

1.9

10

65536

23.4

(20.5)

22.8

(20.1)

22.4

(19.8)

21.8

(19.0)

21.4

(18.9)

21.3

(18.5)

21.1

(18.4)

21.1

(18.4)

20.6

(17.8)

20.0

(17.3)

12512

2496

2304

2080

1248

640

22.2

(19.4)

21.8

(19.1)

21.6

(18.7)

20.7

(17.9)

20.6

(17.9)

20.5

(17.7)

20.1

(17.4)

20.1

(17.3)

19.5

(16.7)

18.8

(16.0)

50

21.0

(18.3)

20.7

(18.0)

20.5

(17.8)

19.6

(16.8)

19.5

(16.8)

19.3

(16.7)

19.0

(16.3)

18.9

(16.0)

18.4

(15.5)

17.7

(15.0)

54

20.9

(18.0)

20.6

(17.8)

20.4

(17.7)

19.6

(17.0)

19.5

(16.8)

19.3

(16.6)

18.9

(16.3)

18.8

(16.2)

18.3

(15.4)

17.6

(14.8)

60

20.9

(18.2)

20.5

(17.8)

20.4

(17.5)

19.5

(16.6)

19.4

(16.5)

19.2

(16.4)

18.9

(16.1)

18.8

(16.1)

18.2

(15.3)

17.5

(14.8)

100

195

488

977

1953

3906

20.6

(17.8)

20.3

(17.5)

20.0

(17.2)

19.2

(16.5)

19.0

(16.3)

18.8

(16.0)

18.5

(15.6)

18.4

(15.7)

17.8

(15.1)

17.2

(14.4)

20.0

(17.0)

19.7

(17.0)

19.5

(16.7)

18.7

(15.9)

18.6

(15.8)

18.3

(15.6)

18.0

(15.4)

17.9

(15.1)

17.3

(14.5)

16.7

(13.8)

256

19.4

(16.7)

19.0

(16.2)

18.9

(16.1)

18.0

(15.4)

17.9

(15.1)

17.7

(14.9)

17.4

(14.5)

17.3

(14.6)

16.7

(13.8)

16.0

(13.1)

128

18.9

(16.1)

18.5

(15.8)

18.3

(15.4)

17.5

(14.7)

17.3

(14.3)

17.1

(14.3)

16.8

(14.1)

16.7

(14.0)

16.1

(13.3)

15.4

(12.4)

64

18.2

(15.4)

17.9

(14.9)

17.6

(14.8)

16.8

(14.2)

16.6

(13.7)

16.4

(13.6)

16.1

(13.3)

15.9

(13.2)

15.3

(12.5)

14.7

(11.8)

32

15.3

15.1

14.9

14.8

14.6

14.1

13.6

(12.8)

(12.6)

(12.9)

(12.3)

(12.5)

(12.3)

(12.0)

(11.5)

(10.9)

Effective resolution = log (full-scale voltage/RMS noise)

2

Noise-free resolution = log (full-scale voltage/peak-to-peak noise)

2

Note:

“Bypass” indicates the state where both PGA and BUF are disabled, “BUF” indicates the state where PGA is disabled and BUF

is enabled, and “PGA” indicates the state where PGA is enabled.

Note:

The upper rows indicate effective resolution (bits) and the lower rows (in parentheses) indicate noise-free resolution (bits).

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 75 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.50

24-Bit Delta-Sigma A/D Converter Analog Input Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_IDR

Min.

−V

Typ.

—

Max.

Unit

V

Test Conditions

V = V

REF

+V

Differential input

voltage range

Gain = 1 (PGA disabled)

Gain = 1 (PGA enabled)

REF

(REFnP)

(REFnN)

− V

(n = 0, 1), or

= V

Whichever is

greater of the values

Whichever is

smaller of the

—

V

REF

REFOUT

of −V

and

values of +V

and

REF

−(AVCC0 – AVSS0

– 0.5V)

+(AVCC0 – AVSS0

– 0.5V)

−V

/ Gain

+V

/ Gain

Gain ≥ 2

—

REF

Absolute input

voltage range

Gain = 1 (PGA disabled,

BUF disabled)

V_I

AVSS0 – 0.05

AVSS0 + 0.1

AVSS0 – 0.05

—

AVCC0 + 0.05

AVCC0 – 0.1

AVCC0 + 0.05

±25

V

Gain = 1 (PGA disabled,

BUF enabled)

—

±5

±1

Gain = 1 to 128

(PGA enabled)

Input bias current Gain = 1 to 128

(PGA enabled)

I_IB

nA

Figure 2.96

T_a= 25°C

Gain = 1 (PGA disabled,

—

±5

BUF disabled),

OPCR.DSADLVM = 0

Gain = 1 (PGA disabled,

BUF enabled)

—

±1

±5

Gain = 1 (PGA disabled,

BUF disabled),

±1.5

±3.0

μA

nA

OPCR.DSADLVM = 1

Input offset

current

Gain = 1 to 128

(PGA enabled)

I_IO

—

±3

±0.5

5

±10

±2.0

10

Figure 2.97

T_a= 25°C

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 1 (PGA disabled,

BUF disabled)

μA/V

Input bias current Gain = 1 to 16

dI_IB

50

180

pA/°C

drift

(PGA enabled)

Gain = 32 to 128

—

70

50

200

100

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 1 (PGA disabled,

BUF disabled),

OPCR.DSADLVM = 0

—

50

100

500

Gain = 1 (PGA disabled,

BUF disabled),

300

OPCR.DSADLVM = 1

Input offset

current drift

Gain = 1 to 128

(PGA enabled)

dI_IO

—

50

45

200

80

pA/°C

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 1 (PGA disabled,

BUF disabled)

170

350

pA/V/°C

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 76 of 98

RX23E-A Group

2. Electrical Characteristics

350

300

250

200

150

100

50

0.15

0.10

0.05

0.00

–0.05

–0.10

–0.15

0

500

1000

1500

2000

–0.15 –0.10 –0.05

0.00

0.05

0.10

0.15

sample

Noise [µV]

Figure 2.75

Noise Histogram (AVCC0 = 5.0 V, T_a=

25°C, Normal Mode, Gain = 128, f_DR= 7.6

SPS, V_ID= 0V, V_REF= 2.5V)

Figure 2.76

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

Normal Mode, Gain = 128, f_DR= 7.6 SPS,

V_ID= 0V, V_REF= 2.5V)

350

300

250

200

150

100

50

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–0.6

500

1000

1500

2000

–0.4

–0.2

0.0

0.2

0.4

0.6

sample

Noise [µV]

Figure 2.77

Noise Histogram (AVCC0 = 5.0 V, T_a=

25°C, Normal Mode, Gain = 16, f_DR= 7.6

SPS, V_ID= 0V, V_REF= 2.5V)

Figure 2.78

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

Normal Mode, Gain = 16, f_DR= 7.6 SPS,

V_ID= 0V, V_REF= 2.5V)

700

600

500

400

300

200

100

0

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

0

500

1000

1500

2000

–2.4 –1.8 –1.2 –0.6 0.0

0.6 1.2 1.8 2.4

sample

Noise [µV]

Figure 2.79

Noise Histogram (AVCC0 = 5.0 V, T_a=

Figure 2.80

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

25°C, Normal Mode, Gain = 1 (PGA

disabled, BUF disabled), f_DR= 7.6 SPS,

Normal Mode, Gain = 1 (PGA disabled,

BUF disabled), f_DR= 7.6 SPS, V_ID= 0V,

V_ID= 0V, V_REF= 2.5V)

V_REF= 2.5V)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 77 of 98

RX23E-A Group

2. Electrical Characteristics

350

300

250

200

150

100

50

0.20

0.15

0.10

0.05

0.00

–0.05

–0.10

–0.15

–0.20

0

–0.24 –0.18 –0.12 –0.06 0.00 0.06 0.12 0.18 0.24

0

500

1000

1500

2000

sample

Noise [µV]

Figure 2.81

Noise Histogram (AVCC0 = 5.0 V, T_a=

25°C, Low Power Mode, Gain = 128, f_DR

1.9 SPS, V_ID= 0V, V_REF= 2.5V)

Figure 2.82

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

Low Power Mode, Gain = 128, f_DR= 1.9

SPS, V_ID= 0V, V_REF= 2.5V)

=

350

300

250

200

150

100

50

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

0

–0.8 –0.6 –0.4 –0.2 0.0

0.2 0.4 0.6 0.8

500

1000

1500

2000

sample

Noise [µV]

Figure 2.83

Noise Histogram (AVCC0 = 5.0 V, T_a=

25°C, Low Power Mode, Gain = 16, f_DR

1.9 SPS, V_ID= 0V, V_REF= 2.5V)

Figure 2.84

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

Low Power Mode, Gain = 16, f_DR= 1.9

SPS, V_ID= 0V, V_REF= 2.5V)

=

600

500

400

300

200

100

0

3

2

1

0

–1

–2

–3

0

500

1000

1500

2000

–3.0 –2.4 –1.8 –1.2 –0.6 0.0 0.6 1.2 1.8 2.4 3.0

sample

Noise [µV]

Figure 2.85

Noise Histogram (AVCC0 = 5.0 V, T_a=

25°C, Low Power Mode, Gain = 1 (PGA

Figure 2.86

Plot of Noise (AVCC0 = 5.0 V, T_a= 25°C,

Low Power Mode, Gain = 1 (PGA

disabled, BUF disabled), f_DR= 1.9 SPS,

V_ID= 0V, V_REF= 2.5V)

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RX23E-A Group

2. Electrical Characteristics

Gain = 1 (PGA disabled,

BUF disabled)

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 1

(PGA enabled)

Gain = 1 (PGA disabled,

BUF disabled)

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 1

(PGA enabled)

Gain = 2

Gain = 4

Gain = 8

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 128

Gain = 32

Gain = 64

Gain = 16

Gain = 128

Gain = 32

Gain = 64

24

22

20

18

16

14

12

1000

100

10

1

0.1

0.01

1

10

100

1000

10000

100000

1

10

100

1000

10000

100000

Data rate [SPS]

Figure 2.87

Data Rate Dependence of RMS Noise

(AVCC0 = 5.0 V, T_a= 25°C, Normal Mode,

Figure 2.88

Data Rate Dependence of Effective

Resolution (AVCC0 = 5.0 V, T_a= 25°C,

V

_ID= 0V, V_REF= 2.5V)

Normal Mode, V_ID= 0V, V_REF= 2.5V)

Gain = 1 (PGA disabled,

BUF disabled)

Gain = 2

Gain = 16

Gain = 128

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 4

Gain = 1

Gain = 1 (PGA disabled,

BUF disabled)

Gain = 2

Gain = 16

Gain = 128

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 4

Gain = 1

(PGA enabled )

Gain = 8

Gain = 64

Gain = 8

Gain = 64

Gain = 32

1000

100

10

24

22

20

18

16

14

1

0.1

12

1

0.01

1

10

100

1000

10000

10

100

Data rate [SPS]

1000

10000

Data rate [SPS]

Figure 2.89

Data Rate Dependence of RMS Noise

(AVCC0 = 5.0 V, T_a= 25°C, Low Power

Figure 2.90

Data Rate Dependence of Effective

Resolution (AVCC0 = 5.0 V, T_a= 25°C,

Mode, V_ID= 0V, V_REF= 2.5V)

Low Power Mode, V_ID= 0V, V_REF= 2.5V)

3.0

2.5

2.0

1.5

Gain = 1

(PGA disabled, BUF disabled)

Gain = 2

1.0

–50 –40 –30 –20 –10

0

10

20

30

40

50

Input voltage [% of FSR]

Figure 2.91

Input Voltage Dependence of RMS Noise

(AVCC0 = 5.0 V, T_a= 25°C, Normal Mode,

f_DR= 122 SPS, V_REF= 2.5V)

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RX23E-A Group

2. Electrical Characteristics

8

6

8

6

4

2

0

–2

–4

–6

–8

–2

–4

–6

–8

–50 –40 –30 –20 –10

0

10 20 30 40 50

–50 –40 –30 –20 –10

0

10 20 30 40 50

Input voltage[% of FSR]

Figure 2.92

Input Voltage Dependence of Integral

Non-Linearity (AVCC0 = 5.0 V, T_a= 25°C,

Figure 2.93

Input Voltage Dependence of Integral

Non-Linearity (AVCC0 = 5.0 V, T_a= 25°C,

Normal Mode, Gain = 2,

OPCR.DSADLVM bit = 0, V_REF= 2.5V)

Normal Mode, Gain = 1 (PGA disabled,

BUF disabled), OPCR.DSADLVM bit = 0,

V_REF= 2.5V)

0.03

0.02

15

10

5

0.01

0.00

0

–0.01

–0.02

–0.03

–5

–10

Gain = 1

(PGA enabled)

Gain = 1

(PGA disabled,

BUF disabled)

Gain = 2

(PGA disabled,

BUF enabled)

Gain = 4

Gain = 1

(PGA disabled,

BUF disabled)

(PGA disabled,

BUF enabled)

(PGA enabled)

Gain = 8

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 32

Gain = 64

Gain = 16

Gain = 128

Gain = 32

Gain = 64

Gain = 128

–15

–50

–25

0

25

50

75

100

125

–25

0

25

50

75

100

125

Temperature [°C]

Figure 2.94

Temperature Dependence of Offset

Error (AVCC0 = 5.0 V, V_ID= 0V, V_REF

Figure 2.95

Temperature Dependence of Gain Error

(AVCC0 = 5.0 V, OPCR.DSADLVM bit = 0,

V_REF= 2.5V)

=

2.5V)

3

2

6

4

Gain = 1 (PGA disabled,

BUF disabled)

Gain = 1 (PGA enabled)

Gain = 4

Gain = 16

Gain = 64

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 2

Gain = 8

Gain = 32

Gain = 128

Gain = 1 (PGA disabled,

BUF enabled)

Gain = 2

Gain = 8

Gain = 32

Gain = 128

Gain = 1 (PGA enabled)

Gain = 4

Gain = 16

Gain = 64

1

2

0

–1

–2

–4

–3

–50

–6

–50

–25

0

25

50

75

100

125

–25

0

25

50

75

100

125

Temperature [°C]

Figure 2.96

Temperature Dependence of Analog

Input Bias Current (AVCC0 = 5.0 V)

Figure 2.97

Temperature Dependence of Analog

Input Offset Current (AVCC0 = 5.0 V)

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RX23E-A Group

2. Electrical Characteristics

2.10 Analog Front End Characteristics

Table 2.51

Voltage Reference Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_REFOUT

—

Min.

—

Typ.

2.5

—

Max.

—

Unit

V

Test Conditions

Figure 2.98

Output voltage

Initial accuracy

—

±0.1

%

Figure 2.99

T_a= 25°C

Temperature drift

—

4

5

10

12

ppm/°C

T_a= –40 to +85°C

T_a= –40 to +105°C

Load current

I_L

—

–35

±10

–50

mA

Load regulation

—

μV/mA

Figure 2.100

I_L= 0 to +10 mA

—

250

80

400

—

I_L= –10 to 0 mA

DC

Power supply rejection ratio

PSRR

70

dB

Table 2.52

Bias Voltage Generator Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Unit

Item

Symbol

V_BIAS

Min.

Typ.

Max.

Conditions

Output voltage

(AVCC0 + AVSS0)/2 (AVCC0 + AVSS0)/2 (AVCC0 + AVSS0)/2

V

– 0.02

—

+ 0.02

20

Startup time

t_START

—

μs/nF

Table 2.53

Temperature Sensor Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Test

Unit

Item

Symbol

Min.

Typ.

Max.

Conditions

Accuracy

—

±5

—

°C

°C/LSB²

°C/LSB

—

Figure 2.101

Voltage sensitivity coefficient

Second-order

First-order

TC_SNS

–6.2 × 10^–13

7.5 × 10^–5

Output code

—

3D4F50h

(4018000)

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RX23E-A Group

2. Electrical Characteristics

Table 2.54

Excitation Current Source Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

2 channels mode

4 channels mode

Symbol

IEXC

Min.

Typ.

Max.

Unit

Test Conditions

Figure 2.102

Output

current

50, 100, 250, 500, 750, 1000

μA

50, 100, 250, 500

±1

Initial accuracy

—

±5

60

%

Figure 2.103

T_a= 25°C

Temperature drift

Current matching

—

25

ppm/°C

%

±0.2

±2.0

Figure 2.104,

Figure 2.105

T_a= 25°C

Drift matching

—

5

30

ppm/°C

Matching between

IEXC0 and IEXC1

Matching between

IEXC2 and IEXC3

Line regulation

—

0.05

0.1

—

0.30

0.5

%/V

V

Load regulation

Compliance voltage

V_COMP

AVSS0 – 0.05

AVCC0 – 0.5

Figure 2.106

Output current error =

–2.0%

Table 2.55

External Reference Input Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_REF

Min.

1

Typ.

2.5

Max.

Unit

V

Test Conditions

Differential input voltage range

AVCC0

V_REF= V_(REFnP)

–

V_(REFnN)(n = 0, 1)

Absolute input

voltage range

Reference buffer

disabled

V_(REF0P)

,

AVSS0 – 0.05

—

7

AVCC0 + 0.05

V

V_(REF1P),

V_(REF0N)

V_(REF1N)

,

Reference buffer

enabled

AVSS0 + 0.1

AVCC0 – 0.1

Input current

Reference buffer

disabled

I_b

—

15

±3

μA/V

nA

Figure 2.107

T_a= 25°C

Reference buffer

enabled

±1

0.8

Figure 2.108

T_a= 25°C

Input current drift

Reference buffer

disabled

dI_b

1.5

nA/V/°C T_a= –40 to +105°C

Reference buffer

enabled

—

70

18

30

90

60

150

—

pA/°C

dB

T_a= –40 to +85°C

T_a= –40 to +105°C

Common mode

rejection ratio

Reference buffer

disabled

CMRR

Reference buffer

enabled

70

80

—

Table 2.56

Low Side Switch Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

On-state resistance

Symbol

R_ON

Min.

—

Typ.

—

Max.

10

Unit

Ω

Test Conditions

Off-state leakage current

Allowable current

I_lkg

—

0.1

30

μA

mA

I_LIMIT

—

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Aug 30, 2019

Page 82 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.57

Low Power-Supply Voltage Detector Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_DET0

Min.

1.88

1.74

—

Typ.

2.00

1.86

—

Max.

2.12

1.98

20

Unit

V

Test Conditions

Detection voltage DET0LVL = 0

Negative-going

AVCC0

(LVDET0)

DET0LVL = 1

Non-responsive period (LVDET0)

t_DET0

μs

V

Detection voltage DET1LVL[1:0] = 00b

V_DET1

2.75

2.65

3.60

3.50

—

2.91

2.82

3.80

3.70

—

3.07

2.99

4.00

3.90

20

Negative-going

AVCC0

(LVDET1)

DET1LVL[1:0] = 01b

DET1LVL[1:0] = 10b

DET1LVL[1:0] = 11b

Non-responsive period (LVDET1)

t_DET1

μs

Table 2.58

Input Voltage Fault Detector Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_IDETH

Min.

Typ.

Max.

—

Unit

V

Test Conditions

Upper detection level for the analog

input voltage

AVCC0 + 0.05 AVCC0 + 0.2

Lower detection level for the analog

input voltage

V_IDETL

t_IDET

—

AVSS0 – 0.2 AVSS0 – 0.05

20

V

Non-responsive period

—

μs

Table 2.59

Reference Voltage Fault Detector Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

V_RDET

Min.

0.70

Typ.

0.85

Max.

1.00

Unit

V

Test Conditions

Detection level for external reference

voltage differential

Upper detection level for the external

reference voltage

V_RDETH

V_RDETL

t_RDET

AVCC0 – 0.5 AVCC0 – 0.4

—

V

Lower detection level for the external

reference voltage

—

AVSS0 + 0.4 AVSS0 + 0.5

20

Non-responsive period

—

μs

Table 2.60

Excitation Current Source Disconnect Detector Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C

a

Item

Symbol

Min.

Typ.

Max.

—

Unit

V

Test Conditions

Detection level for disconnection of the

excitation current source

V_IEXCDETAVCC0 – 0.18 AVCC0 – 0.06

Non-responsive period

t_IEXCDET

—

20

μs

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RX23E-A Group

2. Electrical Characteristics

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

10

8

6

4

2

0

–50 –25

0

25

50

75

100 125

–0.15 –0.10 –0.05

0.00

0.05

0.10

0.15

Inital accuracy [%]

Temperature [°C]

Figure 2.98

Temperature Dependence of Output

Voltage of Voltage Reference

(AVCC0 = 5.0 V)

Figure 2.99

Initial Accuracy of Voltage Reference

(AVCC0 = 5.0 V, 30 samples)

2.0

1.5

1.003

1.002

1.001

1.000

0.999

0.998

0.997

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–15

–10

–5

0

5

10

15

–50

–25

0

25

50

75

100

125

I_L[mA]

Temperature [°C]

Figure 2.100 Load Regulation of Voltage Reference

(AVCC0 = 5.0 V, T_a= 25°C)

Figure 2.101 Accuracy of Temperature Sensor

(AVCC0 = 5.0 V)

1.5

1.0

0.5

0.0

30

20

10

0

–0.5

IEXC = 50 µA

IEXC = 100 µA

IEXC = 250 µA

–1.0

IEXC = 500 µA

IEXC = 750 µA

IEXC = 1000 µA

–1.5

–2.0 –1.6 –1.2 –0.8 –0.4 0.0 0.4 0.8 1.2 1.6 2.0

–50 –25

0

25

50

75

100 125

Initial accuracy [%]

Temperature [°C]

Figure 2.102 Temperature Dependence of Output

Current of Excitation Current Source

(AVCC0 = 5.0 V)

Figure 2.103 Initial Accuracy of Output Current of

Excitation Current Source

(AVCC0 = 5.0 V, T_a= 25°C, IEXC = 250

µA, 93 samples)

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RX23E-A Group

2. Electrical Characteristics

50

40

30

20

10

0.4

0.3

IEXC = 50 µA

IEXC = 100 µA

IEXC = 250 µA

IEXC = 500 µA

IEXC = 750 µA

IEXC = 1000 µA

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

0

–0.6

–0.4

–0.2

0.0

0.2

0.4

0.6

–50 –25

0

25

50

75

100 125

Current matching [%]

Temperature [°C]

Figure 2.104 Matching of Output Current of Excitation Figure 2.105 Temperature Dependence of Matching

Current Source (AVCC0 = 5.0 V, T_a=

of Output Current of Excitation Current

Source (AVCC0 = 5.0 V)

25°C, IEXC = 250 µA, 93 samples)

5

0

IEXC = 50 µA

IEXC = 250 µA

IEXC = 1000 µA

–5

–10

3.0

3.5

4.0

4.5

5.0

5.5

Output voltage [V]

Figure 2.106 IEXC Accuracy vs Compliance Voltage

(AVCC0 = 5.0 V, T_a= 25°C)

1.0

0.8

20

16

12

REF0P

REF0N

0.6

0.4

8

REF0P

REF0N

0.2

4

0

0.0

–4

–8

–0.2

–0.4

–0.6

–0.8

–1.0

–12

–16

–20

–50 –25

0

25

50

75

100 125

–50 –25

0

25

50

75

100 125

Temperature [°C]

Figure 2.107 Temperature Dependence of External

Reference Input Current (AVCC0 = 5.0 V,

Reference Buffer Disabled)

Figure 2.108 Temperature Dependence of External

Reference Input Current (AVCC0 = 5.0 V,

Reference Buffer Enabled)

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RX23E-A Group

2. Electrical Characteristics

2.11 12-Bit A/D Conversion Characteristics

VREFH0

5.5

VREFH0

5.5

5.0

4.0

3.0

A/D Conversion

Characteristics (1)

A/D Conversion

Characteristics (3)

4.0

3.0

A/D Conversion

Characteristics (4)

2.7

2.4

2.7

2.4

A/D Conversion

Characteristics (2)

A/D Conversion

Characteristics (5)

2.0

1.8

1.0

2.42.7

3.0

5.5

AVCC0

1.8 2.42.7

2.0 3.0

5.5

AVCC0

1.0

2.0

4.0

5.0

1.0

4.0

5.0

ADCSR.ADHSC = 0

ADCSR.ADHSC = 1

Figure 2.109

Table 2.61

AVCC0 to VREFH0 Voltage Range

12-Bit A/D Conversion Characteristics (1)

Conditions: 2.7 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, 2.7 V ≤ VREFH0 ≤ AVCC0, Reference voltage = VREFH0,

VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C, Source impedance = 0.3 kΩ

a

Item

Min.

1

Typ.

—

Max.

32

Unit

MHz

Bit

Test Conditions

Frequency

Resolution

—

12

Conversion time*¹

(Operation at PCLKD = 32 MHz)

1.41

—

μs

ADCSR.ADHSC bit = 0

ADSSTRn = 0Dh

Analog input capacitance Cs

—

0

—

25

2.5

pF

kΩ

Pin capacitance included

Analog input resistance

Rs

Analog input effective range

Offset error

—

VREFH0

±4.5

±4.50

—

V

—

±0.5

±0.75

± 0.5

±1.25

±1.0

LSB

Full-scale error

Quantization error

Absolute accuracy

±5.00

—

DNL differential nonlinearity error

INL integral nonlinearity error

±3.0

Note:

The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes

quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not

include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling

states is indicated.

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Aug 30, 2019

Page 86 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.62

Conditions: 2.4 V ≤ VCC ≤ 5.5 V, 2.4 V ≤ AVCC0 ≤ 5.5 V, 2.4 V ≤ VREFH0 ≤ AVCC0, Reference voltage = VREFH0,

VSS = AVSS0 = VREFL0 = 0 V, T = –40 to +105°C, Source impedance = 1.3 kΩ

12-Bit A/D Conversion Characteristics (2)

a

Item

Min.

1

Typ.

—

Max.

16

Unit

MHz

Bit

Test Conditions

Frequency

Resolution

—

12

Conversion time*¹

(Operation at PCLKD = 16 MHz)

2.82

—

μs

ADCSR.ADHSC bit = 0

ADSSTRn = 0Dh

Analog input

capacitance

Cs

—

25

pF

kΩ

Pin capacitance included

Analog input

resistance

Rs

2.5

Analog input effective range

Offset error

0

—

VREFH0

±4.5

±4.50

—

V

—

±0.5

±0.75

±0.5

±1.25

±1.0

LSB

Full-scale error

Quantization error

Absolute accuracy

±5.00

—

DNL differential nonlinearity error

INL integral nonlinearity error

±4.5

Note:

The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes

quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not

include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling

states is indicated.

Table 2.63

12-Bit A/D Conversion Characteristics (3)

Conditions: 2.7 V ≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, 2.7 V ≤ VREFH0 ≤ AVCC0, Reference voltage = VREFH0,

VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C, Source impedance = 1.1 kΩ

Item

Min.

1

Typ.

—

Max.

27

Unit

MHz

Bit

Test Conditions

Frequency

Resolution

—

3

—

12

Conversion time*¹

—

μs

ADCSR.ADHSC bit = 1

ADSSTRn = 28h

(Operation at PCLKD = 27 MHz)

Analog input

capacitance

Cs

—

25

pF

kΩ

Pin capacitance included

Analog input

resistance

Rs

2.5

Analog input effective range

Offset error

0

—

VREFH0

±4.5

±4.50

—

V

—

±0.5

±0.75

±0.5

±1.25

±1.0

LSB

Full-scale error

Quantization error

Absolute accuracy

±5.00

—

DNL differential nonlinearity error

INL integral nonlinearity error

±3.0

Note:

The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes

quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not

include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling

states is indicated.

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 87 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.64

12-Bit A/D Conversion Characteristics (4)

Conditions: 2.4 V ≤ VCC ≤ 5.5 V, 2.4 V ≤ AVCC0 ≤ 5.5 V, 2.4 V ≤ VREFH0 ≤ AVCC0, Reference voltage = VREFH0,

VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C, Source impedance = 2.2 kΩ

Item

Min.

1

Typ.

—

Max.

16

Unit

MHz

Bit

Test Conditions

Frequency

Resolution

—

12

Conversion time*¹

(Operation at PCLKD = 16 MHz)

5.06

—

μs

ADCSR.ADHSC bit = 1

ADSSTRn = 28h

Analog input

capacitance

Cs

—

25

pF

kΩ

Pin capacitance included

Analog input

resistance

Rs

2.5

Analog input effective range

Offset error

0

—

VREFH0

±4.5

±4.50

—

V

—

±0.5

±0.75

±0.5

±1.25

±1.0

LSB

Full-scale error

Quantization error

Absolute accuracy

±5.00

—

DNL differential nonlinearity error

INL integral nonlinearity error

±3.0

Note:

The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes

quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not

include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling

states is indicated.

Table 2.65

12-Bit A/D Conversion Characteristics (5)

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, 1.8 V ≤ VREFH0 ≤ AVCC0, Reference voltage = VREFH0,

VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C, Source impedance = 5 kΩ

Item

Min.

1

Typ.

—

Max.

8

Unit

MHz

Bit

Test Conditions

Frequency

Resolution

—

12

—

Conversion time*¹

10.13

—

μs

ADCSR.ADHSC bit = 1

ADSSTRn = 28h

(Operation at PCLKD = 8 MHz)

Analog input

capacitance

Cs

—

25

pF

kΩ

Pin capacitance included

Analog input

resistance

Rs

2.5

Analog input effective range

Offset error

0

—

VREFH0

±7.5

—

V

—

±1.0

±1.5

±0.5

±3.0

±1.0

±1.25

LSB

Full-scale error

Quantization error

Absolute accuracy

±8.0

—

DNL differential nonlinearity error

INL integral nonlinearity error

±3.00

Note:

The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes

quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not

include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling

states is indicated.

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 88 of 98

RX23E-A Group

2. Electrical Characteristics

Table 2.66

12-Bit A/D Converter Channel Classification

Classification

Analog input channel

Channel

Conditions

Remarks

AN000 to AN005

AVCC0 = 1.8 to 5.5 V

MCU

R0

Rs

12b - ADC

Cs

Figure 2.110

Equivalent Circuit

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 89 of 98

RX23E-A Group

2. Electrical Characteristics

FFFh

Full-scale error

Integral nonlinearity

error (INL)

A/D converter

output code

Ideal line of actual A/D

conversion characteristic

Actual A/D conversion

characteristic

Ideal A/D conversion

characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

000h

Offset error

0

Analog input voltage

VREFH0

(full-scale)

Figure 2.111

Illustration of A/D Converter Characteristic Terms

Absolute accuracy

Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the

actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog

input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D

conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and if reference

voltage (VREFH0 = 3.072 V), then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, 1.5 mV, ... are used as analog

input voltages.

If analog input voltage is 6 mV, absolute accuracy = ±5 LSB means that the actual A/D conversion result is in the range

of 003h to 00Dh though an output code, 008h, can be expected from the theoretical A/D conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale

errors are zeroed, and the actual output code.

R01DS0330EJ0100 Rev.1.00

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RX23E-A Group

2. Electrical Characteristics

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics

and the width of the actual output code.

Offset error

Offset error is the difference between a transition point of the ideal first output code and the actual first output code.

Full-scale error

Full-scale error is the difference between a transition point of the ideal last output code and the actual last output code.

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 91 of 98

RX23E-A Group

2. Electrical Characteristics

2.12 Usage Notes

2.12.1

Connecting VCL Capacitor and Bypass Capacitors

This MCU integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the

internal MCU automatically to the optimum level. A 4.7-μF capacitor needs to be connected between this internal

voltage-down power supply (VCL pin) and the VSS pin. Figure 2.112 and Figure 2.113 shows how to connect external

capacitors. Place an external capacitor close to the pins. Do not apply the power supply voltage to the VCL pin.

Insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. Implement a

bypass capacitor as closer to the MCU power supply pins as possible. Use a recommended value of 0.1 μF as the

capacitance of the capacitors. For the capacitors related to crystal oscillation, see section 9, Clock Generation Circuit

in the User’s Manual: Hardware. For the capacitors related to analog modules, also see section 33, Analog Front

End (AFE), and section 35, 12-Bit A/D Converter (S12ADE) in the User’s Manual: Hardware.

For notes on designing the printed circuit board, see the descriptions of the application note, the Hardware Design Guide

(R01AN1411EJ). The latest version can be downloaded from the Renesas Electronics website.

Bypass

capacitor capacitor

0.1 µF 0.1 µF

Bypass

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

RX23E-A Group

PLQP0048KB-B

(48-pin LFQFP)

(Top view)

19

18

17

16

15

14

13

Bypass

capacitor

0.1 µF

Bypass

capacitor

External capacitor

0.1 µF

for power supply

stabilization 4.7 µF

Note:

Do not apply the power supply voltage to the VCL pin.

Use a 4.7-µF multilayer ceramic capacitor for the VCL pin and place it close to the pin.

A recommended value is shown for the capacitance of the bypass capacitors.

Figure 2.112

Connecting Capacitors (48 Pins)

R01DS0330EJ0100 Rev.1.00

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RX23E-A Group

2. Electrical Characteristics

Bypass

capacitor capacitor

0.1 µF 0.1 µF

Bypass

31

32

33

34

35

36

37

38

39

40

20

19

18

17

16

15

14

13

12

11

RX23E-A Group

PWQN0040KC-A

(40-pin HWQFN)

(Top view)

Bypass

capacitor

0.1 µF

Bypass

capacitor

External capacitor

0.1 µF

for power supply

stabilization 4.7 µF

Note:

Do not apply the power supply voltage to the VCL pin.

Use a 4.7-µF multilayer ceramic capacitor for the VCL pin and place it close to the pin.

A recommended value is shown for the capacitance of the bypass capacitors.

Figure 2.113

Connecting Capacitors (40 Pins)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 93 of 98

RX23E-A Group

Appendix 1. Package Dimensions

Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas

Electronics Corporation website.

Figure A 48-Pin LFQFP (PLQP0048KB-B)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 94 of 98

RX23E-A Group

Appendix 1. Package Dimensions

JEITA Package code

RENESAS code

Previous code

MASS(TYP.)[g]

P-HWQFN40-6x6-0.50

PWQN0040KC-A

P40K8-50-4B4-5

0.09

D

21

30

20

31

DETAIL OF A PART

E

A

40

11

A₁

c₂

10

1

INDEX AREA

A

S

y

S

Dimension in Millimeters

Referance

Symbol

Nom

6.00

Max

6.05

0.80

Min

5.95

D

E

D₂

A

Lp

EXPOSED DIE PAD

A

1

10

A₁

b

0.00

0.18

0.30

11

0.25

0.50

0.40

40

e

0.30

0.15

0.50

0.05

Lp

x

B

E₂

y

Z_D

Z_E

c₂

0.75

0.20

4.50

Z_E

20

31

0.25

30

21

D₂

E₂

Z_D

e

M

b

x

S

A B

Figure B 40-Pin HWQFN (PWQN0040KC-A)

R01DS0330EJ0100 Rev.1.00

Aug 30, 2019

Page 95 of 98

General Precautions in the Handling of Microprocessing Unit and Microcontroller

Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the

products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps

must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be

adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.

Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of

register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset

pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins

in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the

level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O

pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal

elements. Follow the guideline for input signal during power-off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are

generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of

the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal

become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program

execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal

produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V_IL

(Max.) and V_IH(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the

input level is fixed, and also in the transition period when the input level passes through the area between V_IL(Max.) and V_IH(Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these

addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.

The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms

of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-

evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all

liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	R5F523E6AGNF
厂家：	RENESAS TECHNOLOGY CORP
描述：	32-MHz, 32-bit RX MCUs with up to 256-KB flash memory,
文件：	总98页 (文件大小：1423K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F523E6AGNF [RENESAS]

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