R7FA2A1AB3CFM [RENESAS]
32-Bit MCU Renesas Advanced (RA) Family Renesas RA2 Series;型号: | R7FA2A1AB3CFM |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 32-Bit MCU Renesas Advanced (RA) Family Renesas RA2 Series |
文件: | 总100页 (文件大小:1258K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Cover
Renesas RA2A1 Group
32
Datasheet
32-Bit MCU
Renesas Advanced (RA) Family
Renesas RA2 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.10 Mar 2020
Features
RA2A1 Group
Datasheet
Ultra-low power 48-MHz Arm® Cortex®-M23 core, up to 256-KB code flash memory, 32-KB SRAM, Capacitive Touch
Sensing Unit, 16-bit A/D Converter, 24-bit sigma-delta A/D Converter, 12-bit D/A Converter, 8-bit D/A Converter,
Operational Amplifier, security and safety features.
Features
■ Arm Cortex-M23 Core
Armv8-M architecture
Maximum operating frequency: 48 MHz
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: DWT, FPB, and CoreSight™ MTB-M23
CoreSight Debug Port: SW-DP
■ System and Power Management
Low power modes
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
■ Memory
Low Voltage Detection (LVD) with voltage settings
Up to 256-KB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
Up to 32-KB SRAM
■ Security and Encryption
AES128/256
True Random Number Generator (TRNG)
Flash Cache (FCACHE)
Memory Protection Unit (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
■ Connectivity
USB 2.0 Full-Speed (USBFS) module
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 3
- UART
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 5.5 V)
(1 to 4 MHz when VCC = 1.6 to 5.5 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
Controller Area Network (CAN) module
■ Analog
16-bit A/D Converter (ADC16)
- 1.2 Msps
- Differential input mode
- Single-ended input mode
24-bit Sigma-Delta A/D Converter (SDADC24)
- 15.6 ksps
- Differential input mode
- Single-ended input mode
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8) × 2
High-Speed Analog Comparator (ACMPHS)
Low-Power Analog Comparator (ACMPLP) × 2
Operational Amplifier (OPAMP) × 3
Temperature Sensor (TSN)
■ General Purpose I/O Ports
Up to 49 input/output pins
- Up to 3 CMOS input
- Up to 46 CMOS input/output
- Up to 9 input/output 5 V tolerant
- Up to 3 high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 36-pin BGA (5 mm × 5 mm, 0.8 mm pitch)
Ta = -40°C to +105°C
■ Timers
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 32-pin LQFP (7 mm × 7 mm, 0.8 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
General PWM Timer 32-bit (GPT32)
General PWM Timer 16-bit (GPT16) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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RA2A1 Datasheet
1. Overview
1.
Overview
®
The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
®
The MCU in this series incorporates an energy-efficient Arm Cortex -M23 32-bit core that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
Up to 256-KB code flash memory
32-KB SRAM
16-bit A/D Converter (ADC16)
24-bit Sigma-Delta A/D Converter (SDADC24)
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8)
Operational Amplifier (OPAMP) with configurable switches
Security features.
1.1
Function Outline
Table 1.1
Feature
Arm core
Functional description
Arm Cortex-M23 core
Maximum operating frequency: up to 48 MHz
Arm Cortex-M23 core:
- Revision: r1p0-00rel0
- Armv8-M architecture profile
- Single-cycle integer multiplier
- 17-cycle integer divider.
Arm Memory Protection Unit (Arm MPU):
- Armv8 Protected Memory System Architecture
- 8 protect regions.
SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Data flash memory
Memory Mirror Function (MMF)
256 KB of code flash memory. See section 43, Flash Memory in User’s Manual.
8 KB of data flash memory. See section 43, Flash Memory in User’s Manual.
The Memory Mirror Function (MMF) can be configured to mirror the desired application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. Your application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF) in User’s Manual.
Option-setting memory
SRAM
The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory in User’s Manual.
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). See section
42, SRAM in User’s Manual.
Table 1.3
Feature
System (1 of 2)
Functional description
Operating modes
Two operating modes:
Single-chip mode
SCI or USB boot mode.
See section 3, Operating Modes in User’s Manual.
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RA2A1 Datasheet
1. Overview
Table 1.3
System (2 of 2)
Feature
Functional description
Resets
13 resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
See section 6, Resets in User’s Manual.
Low Voltage Detection (LVD)
Clocks
The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin and
the detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD) in User’s Manual.
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator
Clock out support.
See section 9, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s
Manual.
Interrupt Controller Unit (ICU)
Key Interrupt Function (KINT)
Low power modes
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in
User’s Manual.
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 19, Key Interrupt Function
(KINT) in User’s Manual.
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
stopping modules, selecting power control mode in normal operation, and transitioning to low
power modes. See section 11, Low Power Modes in User’s Manual.
Register write protection
Memory Protection Unit (MPU)
Watchdog Timer (WDT)
The register write protection function protects important registers from being overwritten due to
software errors. See section 12, Register Write Protection in User’s Manual.
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.
The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 24, Watchdog Timer (WDT) in User’s
Manual.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail-safe mechanism when the system runs out of control. The
IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the
count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s
Manual.
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RA2A1 Datasheet
1. Overview
Table 1.4
Event Link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 17, Event Link Controller (ELC) in
User’s Manual.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 16, Data Transfer Controller (DTC) in User’s Manual.
Table 1.6
Feature
Timers
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with one channel and a 16-bit timer with six
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms can be generated for controlling
brushless DC motors. The GPT can also be used as a general-purpose timer. See section 21,
General PWM Timer (GPT) in User’s Manual.
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 20, Port Output Enable for GPT (POEG) in
User’s Manual.
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 22, Asynchronous General Purpose Timer (AGT) in User’s Manual.
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 23, Realtime Clock (RTC) in User’s Manual.
Table 1.7
Feature
Communication interfaces (1 of 2)
Functional description
Serial Communications Interface
(SCI)
The Serial Communication Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 27, Serial Communications Interface (SCI) in User’s Manual.
I2C bus interface (IIC)
The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 28, I2C Bus Interface (IIC) in
User’s Manual.
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-
duplex synchronous serial communications with multiple processors and peripheral devices.
See section 30, Serial Peripheral Interface (SPI) in User’s Manual.
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RA2A1 Datasheet
1. Overview
Table 1.7
Feature
Communication interfaces (2 of 2)
Functional description
Controller Area Network (CAN)
module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 29, Controller Area Network (CAN) Module in User’s Manual.
USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a device controller. The module
supports full-speed and low-speed transfer as defined in the Universal Serial Bus Specification
2.0. The module has an internal USB transceiver and supports all of the transfer types defined
in the Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of five pipes. Pipe 0 and
pipe 4 to pipe 7 can be assigned any endpoint number based on the peripheral devices used
for communication or based on your system.
The MCU supports Battery Charging Specification revision 1.2. Because the MCU can be
powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply
3.3 V. See section 26, USB 2.0 Full-Speed Module (USBFS) in User’s Manual.
Table 1.8
Feature
Analog (1 of 2)
Functional description
16-bit A/D Converter (ADC16)
A successive approximation 16-bit A/D Converter (ADC16) is provided. Up to 17 single-ended/
4 differential analog input channels are selectable. Reference voltage of SDADC24,
temperature sensor output, and internal reference voltage are selectable for conversion. The
calibration function calculates capacitor array DAC and gain/offset correction values under the
usage conditions to enable accurate
A/D conversion. See section 32, 16-Bit A/D Converter (ADC16) in User’s Manual.
24-bit Sigma-Delta A/D Converter
(SDADC24)
A 24-bit Sigma-Delta A/D Converter (SDADC24) with a programmable gain instrumentation
amplifier is provided. Up to 10 single-ended/5 differential analog input channels are selectable.
The 2 single-ended/1 differential analog input channels of these analog input channels are
inputs from internal OPAMP. Analog input multiplexer is input to the sigma-delta A/D converter
by the programmable gain instrumentation amplifier (PGA). The A/D conversion result is
filtered by the SINC3 digital filter, and then stored in an output register. The calibration function
calculates gain error and offset error correction values under the usage conditions to enable
accurate A/D conversion. See section 33, 24-Bit Sigma-Delta A/D Converter (SDADC24) in
User’s Manual.
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8)
Temperature Sensor (TSN)
A 12-bit D/A Converter (DAC12) is provided. See section 34, 12-Bit D/A Converter (DAC12) in
User’s Manual.
An 8-bit D/A Converter (DAC8) is provided. See section 35, 8-Bit D/A Converter (DAC8) in
User’s Manual.
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC16 for conversion and can be further used by the end
application. See section 36, Temperature Sensor (TSN) in User’s Manual.
High-Speed Analog Comparator
(ACMPHS)
The High-Speed Analog Comparator (ACMPHS) compares a reference voltage with an analog
input voltage. The comparison result can be read by software and also be output externally.
The reference voltage can be selected from either an input to the IVREFi (i = 0 to 2) pin, an
output from internal D/A converter, or from the internal reference voltage (Vref) generated
internally in the MCU.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 38, High-
Speed Analog Comparator (ACMPHS) in User’s Manual.
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares a reference voltage with an analog
input voltage. The comparison result can be read by software and also be output externally.
The reference voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin, an
internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated internally
in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed
mode decreases the response delay time, but increases current consumption. Setting low-
speed mode increases the response delay time, but decreases current consumption. See
section 39, Low-Power Analog Comparator (ACMPLP) in User’s Manual.
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RA2A1 Datasheet
1. Overview
Table 1.8
Analog (2 of 2)
Feature
Functional description
Operational Amplifier (OPAMP)
The Operational Amplifier (OPAMP) can be used to amplify small analog input voltages and
output the amplified voltages. A total of three differential operational amplifier units with two
input pins and one output pin are provided. All units have switches that can select input
signals. Additionally, operational amplifier 0 has a switch that can select the output pin. See
section 37, Operational Amplifier (OPAMP) in User’s Manual.
Table 1.9
Feature
Human machine interfaces
Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do
not come into direct contact with the electrodes. See section 40, Capacitive Touch Sensing
Unit (CTSU) in User’s Manual.
Table 1.10
Feature
Data processing
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generating polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 31, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 41,
Data Operation Circuit (DOC) in User’s Manual.
Table 1.11
Security
Feature
Functional description
AES
See section 44, AES Engine in User’s Manual.
See section 45, True Random Number Generator (TRNG) in User’s Manual.
True Random Number Generator
(TRNG)
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RA2A1 Datasheet
1. Overview
1.2
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the
features.
Bus
Memory
Arm Cortex-M23
MPU
System
256 KB code flash
Clocks
MPU
POR/LVD
Reset
MOSC/SOSC
8 KB data flash
32 KB SRAM
NVIC
(H/M/L) OCO
Mode control
Power control
ICU
System timer
Test and DBG I/F
DMA
DTC
CAC
Register write
protection
KINT
Timers
Communication interfaces
Human machine interfaces
CTSU
GPT32 × 1
GPT16 × 6
CAN × 1
SCI × 3
IIC × 2
SPI × 2
AGT × 2
RTC
USBFS
with Battery
Charging
revision1.2
WDT/IWDT
Event link
ELC
Data processing
Analog
CRC
ADC16
TSN
OPAMP × 3
SDADC24
DAC12 × 1
DAC8 × 2
ACMPHS × 1
ACMPLP × 2
DOC
Security
AES + TRNG
Figure 1.1
Block diagram
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RA2A1 Datasheet
1. Overview
1.3
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a
list of products.
# A A
R 7 F A 2 A 1 A B 3 C F M
0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FM: LQFP 64 pins
FJ: LQFP 32 pins
BT: BGA 36 pins
NE: QFN 48 pins
NF: QFN 40 pins
Quality Grade
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
B: 256 KB
Feature set
Group number
Series name
RA family
Flash memory
Renesas microcontroller
Figure 1.2
Part numbering scheme
Product list
Table 1.12
Operating
Product part number
R7FA2A1AB3CFM
R7FA2A1AB3CNE
R7FA2A1AB3CNF
R7FA2A1AB2CBT
R7FA2A1AB3CFJ
Orderable part number
R7FA2A1AB3CFM#AA0
R7FA2A1AB3CNE#AC0
R7FA2A1AB3CNF#AC0
R7FA2A1AB2CBT#AC0
R7FA2A1AB3CFJ#AA0
Package code
Code flash Data flash
256 KB 8 KB
SRAM
temperature
-40 to +105°C
-40 to +105°C
-40 to +105°C
-40 to +85°C
-40 to +105°C
PLQP0064KB-C
PWQN0048KB-A
PWQN0040KC-A
PLBG0036GA-A
PLQP0032GB-A
32 KB
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RA2A1 Datasheet
1. Overview
1.4
Function Comparison
Table 1.13
Function comparison
Part numbers
Pin count
R7FA2A1AB3CFM
R7FA2A1AB3CNE
R7FA2A1AB3CNF
40
R7FA2A1AB2CBT
R7FA2A1AB3CFJ
64
48
36
32
Package
LQFP
QFN
QFN
BGA
LQFP
Code flash memory
Data flash memory
SRAM
256 KB
8 KB
32 KB
Parity
16 KB
ECC
16 KB
System
CPU clock
48 MHz
Sub-clock
oscillator
Yes
No
3
ICU
Yes
4
KINT
8
6
6
6
4
3
Event control
DMA
ELC
Yes
Yes
1
DTC
Timers
GPT32
GPT16
AGT
4
4
2
RTC
Yes
Yes
3
WDT/IWDT
SCI
Communication
IIC
2
SPI
2
1
2
CAN
Yes
USBFS
ADC16
SDADC24
DAC12
DAC8
ACMPHS
ACMPLP
OPAMP
TSN
Yes
No
1
1
1
1
1
Analog
17 (4* )
12 (3* )
8 (1* )
5 (1* )
5 (1* )
1
1
1
1
1
8 (4* )
6 (3* )
4 (2* )
2 (1* )
2 (1* )
1
2
3
2
2*
2*
1
2
3
2
1
1
9
1
Yes
HMI
CTSU
CRC
26
16
11
Yes
11
Data processing
DOC
Yes
Security
AES and TRNG
Note 1. The number of channels of the differential analog input.
Note 2. Pin output function of DA8_1 cannot be used.
Note 3. Pin output function of DA8_0 and DA8_1 cannot be used.
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RA2A1 Datasheet
1. Overview
1.5
Pin Functions
Table 1.14
Pin functions (1 of 4)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply. Connect it
to VSS by a 0.1-μF capacitor. Place the capacitor close to the pin.
VCL
I/O
Connect this pin to VSS through a smoothing capacitor used to stabilize
the internal power supply. Place the capacitor close to the pin.
VSS
Input
Ground pin. Connect to the system power supply (0 V).
Clock
XTAL
Output
Input
Pins for a crystal resonator. An external clock signal can be input through
the EXTAL pin.
EXTAL
XCIN
Input
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
XCOUT
CLKOUT
Output
Output
Input
Clock output pin
Operating mode control MD
Pins for setting the operating mode. The signal level on this pin must not
be changed during operation mode transition on release from the reset
state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal
goes low.
CAC
CACREF
SWDIO
Input
I/O
Measurement reference clock input pin
Serial wire debug data input/output pin
Serial wire clock pin
On-chip debug
SWCLK
NMI
Input
Input
Input
Input
Interrupt
GPT
Non-maskable interrupt request pin
Maskable interrupt request pins
External trigger input pin
IRQ0 to IRQ7
GTETRGA,
GTETRGB
GTIOC0A to
GTIOC6A,
GTIOC0B to
GTIOC6B
I/O
Input capture, output compare, or PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
Output
Output
Output
Output
Output
Output
3-phase PWM output for BLDC motor control (positive U phase)
3-phase PWM output for BLDC motor control (negative U phase)
3-phase PWM output for BLDC motor control (positive V phase)
3-phase PWM output for BLDC motor control (negative V phase)
3-phase PWM output for BLDC motor control (positive W phase)
3-phase PWM output for BLDC motor control (negative W phase)
External event input enable
AGT
RTC
AGTEE0, AGTEE1 Input
AGTIO0, AGTIO1
AGTO0, AGTO1
I/O
External event input and pulse output
Output
Pulse output
AGTOA0, AGTOA1 Output
AGTOB0, AGTOB1 Output
Output compare match A output
Output compare match B output
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
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Mar 16, 2020
Page 11 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (2 of 4)
Function
Signal
I/O
Description
SCI
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (clock synchronous mode)
RXD0, RXD1,
RXD9
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXD0, TXD1, TXD9 Output
Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0,
CTS1_RTS1,
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0, SCL1, SCL9 I/O
Input/output pins for the IIC clock (simple IIC)
Input/output pins for the IIC data (simple IIC)
SDA0, SDA1,
SDA9
I/O
I/O
I/O
I/O
SCK0, SCK1,
SCK9
Input/output pins for the clock (simple SPI)
MISO0, MISO1,
MISO9
Input/output pins for slave transmission of data (simple SPI)
Input/output pins for master transmission of data (simple SPI)
MOSI0, MOSI1,
MOSI9
SS0, SS1, SS9
SCL0, SCL1
SDA0, SDA1
Input
I/O
Chip-select input pins (simple SPI), active-low
Input/output pins for clock
IIC
I/O
Input/output pins for data
SPI
RSPCKA, RSPCKB I/O
Clock input/output pin
MOSIA, MOSIB
MISOA, MISOB
SSLA0, SSLB0
I/O
Inputs or outputs data output from the master
Inputs or outputs data output from the slave
Input or output pin for slave selection
Output pin for slave selection
I/O
I/O
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output
CAN
CRX0
Input
Output
Input
Input
I/O
Receive data
CTX0
Transmit data
USBFS
VSS_USB
VCC_USB_LDO
VCC_USB
Ground pins
Power supply pin for USB LDO regulator
Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM
USB_VBUS
I/O
D- I/O pin of the USB on-chip transceiver. This pin should be connected to
the D- pin of the USB bus.
Input
USB cable connection monitor pin. This pin should be connected to VBUS
of the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a device controller.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 12 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (3 of 4)
Function
Signal
I/O
Description
Analog power supply
AVCC0
Input
Analog voltage supply pin for the ADC16, DAC12, DAC8, ACMPHS,
ACMPLP, and OPAMP
AVSS0
Input
Analog ground pin for the ADC16, DAC12, DAC8, ACMPHS, ACMPLP,
and OPAMP
AVCC1
AVSS1
VREFH0
Input
Input
Input
Analog voltage supply pin for the SDADC24
Analog ground pin for the SDADC24
Analog reference voltage supply pin for the ADC16. Connect this pin to
AVCC0 when not using the ADC16.
VREFL0
Input
Analog reference ground pin for the ADC16. Connect this pin to AVSS0
when not using the ADC16.
VREFH
VREFL
Input
Input
Input
Analog reference voltage supply pin for the DAC12
Analog reference ground pin for the DAC12
ADC16
AN000 to AN008,
AN016 to AN023
Input pins for the analog signals to be processed by the A/D converter
ADTRG0
Input
Input
Input
Input pins for the external trigger signals that start the A/D conversion,
active-low
SDADC24
ANSD0P to
ANSD3P
Input pins for the analog signals to be processed by the SDADC24
ANSD0N to
ANSD3N
Input pins for the analog signals to be processed by the SDADC24
ADREG
SBIAS
Output
Output
Input
Regulator capacitance for the SDADC24
Sensor power supply
VREFI
External reference voltage supply pin for the SDADC24
DAC12
DAC8
DA12_0
Output
Output pin for the analog signals to be processed by the 12-bit D/A
converter
DA8_0, DA8_1
VCOUT
Output
Output
Output pins for the analog signals to be processed by the 8-bit D/A
converter
Comparator output
ACMPHS
Comparator output pin
IVREF0 to IVREF2 Input
IVCMP0 to IVCMP2 Input
Reference voltage input pin
Analog voltage input pin
Reference voltage input pins
ACMPLP
OPAMP
CMPREF0,
CMPREF1
Input
CMPIN0, CMPIN1
AMP0+ to AMP2+
AMP0- to AMP2-
Input
Input
Input
Analog voltage input pins
Analog voltage input pins
Analog voltage input pins
AMP0O to AMP2O Output
Analog voltage output pins
CTSU
KINT
TS00 to TS25
TSCAP
Input
-
Capacitive touch detection pins (touch pins)
Secondary power supply pin for the touch driver
Key interrupt input pins
KR00 to KR07
Input
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 13 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (4 of 4)
Function
Signal
I/O
Description
I/O ports
P000 to P003,
P012 to P015
I/O
General-purpose input/output pins
P100 to P112
P200
I/O
General-purpose input/output pins
General-purpose input pin
Input
I/O
P201, P204 to
General-purpose input/output pins
P206, P212, P213
P214, P215
Input
I/O
General-purpose input pins
P300 to P304
General-purpose input/output pins
General-purpose input/output pins
P400 to P403,
P407 to P411
I/O
P500 to P502
P914, P915
I/O
I/O
General-purpose input/output pins
General-purpose input/output pins
1.6
Pin Assignments
Figure 1.3 to Figure 1.7 show the pin assignments.
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P500
P300/SWCLK
P301
50
P501
51
P502
P302
52
P015
P303
53
P014/VREFL
P304
54
P013/VREFH
P200
55
P012
P201/MD
RES
56
AVCC0
R7FA2A1AB3CFM
57
58
59
60
61
62
63
64
AVSS0
VREFL0
VREFH0
P003
P204
P205
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VSS_USB
P002
P001
P000
P109
Figure 1.3
Pin assignment for LQFP 64-pin
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Mar 16, 2020
Page 14 of 100
RA2A1 Datasheet
1. Overview
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P500
P501
P300/SWCLK
P301
P502
P302
P015
P200
P014/VREFL
P013/VREFH
AVCC0
AVSS0
P201/MD
RES
R7FA2A1AB3CNE
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VSS_USB
VREFL0
VREFH0
P000
P109
Figure 1.4
Pin assignment for QFN 48-pin
20
19
18
17
16
15
14
13
12
11
31
P300/SWCLK
P301
P500
P501
32
33
P200
P502
34
P201/MD
P013
AVCC0
35
RES
R7FA2A1AB3CNF
36
37
38
39
40
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VSS_USB
AVSS0
VREFL0
VREFH0
P000
P109
Figure 1.5
Pin assignment for QFN 40-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 15 of 100
RA2A1 Datasheet
1. Overview
R7FA2A1AB2CBT
A
B
C
D
E
F
SBIAS
/VREFI
P108
/SWDIO /SWCLK
P300
6
5
4
3
2
1
P500
P100
P101
6
5
4
3
2
1
P501
P502
AVCC1
AVCC0
AVSS0
AVSS1
P110
P000
P109
ADREG
P301
P200
VCC_USB
P915
/USB_DM
P201/MD
VCC_USB
_LDO
P914
/USB_DP
VREFL0
VREFH0
P400
VSS
P214
/XCOUT
VCC
RES
/VSS_USB
P215
/XCIN
P213
/XTAL
P212
/EXTAL
VCL
A
P408
E
P407
F
B
C
D
Figure 1.6
Pin assignment for BGA 36-pin (top view, pad side down)
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
P500
P501
P300/SWCLK
P301
P200
P502
P201/MD
RES
AVCC0
AVSS0
VREFL0
VREFH0
P109
R7FA2A1AB3CFJ
P204
P205
P206
Figure 1.7
Pin assignment for LQFP 32-pin
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Mar 16, 2020
Page 16 of 100
RA2A1 Datasheet
1. Overview
1.7
Pin Lists
Pin number
Timers
Communication Interfaces
Analogs
HMI
1
1
1
D3
1
P400
AGTEE0 GTETR GTIOC1 RTCOUT
CTS0_RT SDA1_A MOSIA_A
CMPIN0
TS00
KR02/
_A
GA_A
A_A
_C
S0_D/
IRQ0_A
SS0_D/
RXD1_C/
MISO1_C/
SCL1_C
2
3
2
-
-
-
-
-
-
-
P401
P402
AGTEE1 GTIU_A GTIOC4
SCK0_D/ SDA0_C SSLB1_A
SCK9_A
VCOUT_
B
TS01
TS02
KR03/
IRQ5_B
_A
A_A
GTIV_A GTIOC0
A_D
CTS9_RT
S9_C/
SSLB2_A
SS9_C
4
-
-
-
-
P403
GTIW_A GTIOC0
B_C
SCK1_B
SSLB3_A
TS03
5
6
7
8
9
3
4
5
6
7
2
3
4
5
6
A1
B1
B2
D2
C1
2
-
VCL
XCIN
XCOUT
VSS
P215
P214
-
3
4
XTAL
P213
P212
AGTEE1 GTETR GTIOC0
_B GA_B A_B
RXD1_D/
MISO1_D/
SCL1_D
IRQ2_B
IRQ3_B
10
8
7
D1
5
EXTAL
VCC
AGTIO0 GTETR GTIOC0
TXD1_D/
MOSI1_D/
SDA1_D
_A
GB_B
B_B
11
12
9
-
8
-
E2
-
6
-
P411
P410
GTIOC5
A_A
TXD0_F/
MOSI0_F/
SDA0_F/
RXD1_B/
MISO1_B/
SCL1_B
SSLA3_A
SSLA2_A
TS04
TS05
13
-
-
-
-
GTIOC5
B_A
CTS0_RT
S0_A/
SS0_A/
TXD1_B/
MOSI1_B/
SDA1_B
14 10
15 11
-
-
-
P409
P408
AGTO1_
A
GTIOC0
A_C
CTX0_B SCK0_A/ SCL0_B SSLA1_A
TSCAP_E IRQ7_A
CTS1_RT
S1_B/
SS1_B
9
E1
7
AGTO0_ GTOUU GTIOC0
P_A A_A
CRX0_B RXD0_A/ SDA0_B SSLA0_A
CMPIN1
TS06
IRQ1_A
A
MISO0_A/
SCL0_A/
TXD1_C/
MOSI1_C/
SDA1_C
16 12 10 F1
8
CACREF P407
_B
AGTIO0 GTOUL GTIOC0
_C O_A B_A
USB_VB TXD0_A/ SCL0_A RSPCKB
TSCAP_D IRQ1_B
US/
MOSI0_A/
_B
CTX0_D SDA0_A/
TXD9_A/
MOSI9_A/
SDA9_A
17 13 11 D2
18 14 12 F4
19 15 13 F3
20 16 14 F5
-
-
-
-
VSS_USB
P915
USB_DM
USB_DP
P914
VCC_US
B
21 17 15 E3
-
VCC_US
B_LDO
22 18
-
-
-
-
-
-
9
P206
P205
P204
AGTIO0 GTOVU GTIOC3
_B P_A A_A
CTS0_RT SCL1_B SSLB0_A
S0_C/
SS0_C/
TXD1_A/
MOSI1_A/
SDA1_A
TS07
TS08
TS09
IRQ6_A
IRQ0_C
23
24
-
-
10
11
GTOVL GTIOC3
TXD0_C/ SDA1_B MISOB_B
O_A
B_A
MOSI0_C/
SDA0_C/
CTS1_RT
S1_A/
SS1_A
RXD0_C/
MISO0_C/
SCL0_C/
SCK9_B
MOSIB_B
25 19 16 F2 12 RES
26 20 17 E4 13 MD
27 21 18 E5 14
P201
P200
P304
NMI
28
-
-
-
-
-
-
-
-
-
-
GTIOC6
A_A
CTX0_A SCK0_B/
TXD9_C/
MISOA_B
MOSIA_B
TS10
TS11
TS12
KR07
MOSI9_C/
SDA9_C
29
-
P303
GTIOC6
B_A
CRX0_A CTS0_RT
S0_B/
KR06
SS0_B/
SCK1_A
30 22
CACREF P302
_A
AGTOA1 GTOVL GTIOC3
_A O_B B_B
TXD0_B/
MOSI0_B/
SDA0_B/
RXD1_A/
MISO1_A/
SCL1_A
RSPCKB
_A
KR05/
IRQ4_B
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 17 of 100
RA2A1 Datasheet
1. Overview
Pin number
Timers
Communication Interfaces
Analogs
HMI
31 23 19 D4 15
P301
AGTOB1 GTOWU GTIOC2 RTCOUT
RXD0_B/ SDA0_A MOSIB_A
TS13
KR04/
_A
P_A
A_B
_A
MISO0_B/
SCL0_B/
CTS9_RT
S9_B/
IRQ5_A
SS9_B
32 24 20 F6 16 SWCLK P300
33 25 21 E6 17 SWDIO P108
34 26 22 C4 18 CLKOUT_ P110
A
AGTOB0 GTOWL GTIOC2
CTX0_C TXD0_D/ SDA1_D RSPCKA ADTRG0_
CMPREF
1
TSCAP_A IRQ2_A
_A
O_A
B_B
MOSI0_D/
SDA0_D/
RXD9_B/
MISO9_B/
SCL9_B
_A
A
35
36
-
-
-
-
-
-
-
-
P111
RTCOUT
_B
SCL1_C RSPCKA
_B
TS14
IRQ6_B
CLKOUT_ P112
B
SDA1_C SSLA0_B
TSCAP_B IRQ7_B
37 27 23 D5 19 ADREG
38 28 24 D6 20 SBIAS/
VREFI
39 29 25 B5 21 AVCC1
40 30 26 C5 22 AVSS1
41
42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P107
P106
P105
P104
P103
AN023
AN022
ANSD3N
ANSD3P
ANSD2N
ANSD2P
ANSD1N
43 31
44 32
MOSIB_C AN021
MISOB_C AN020
TS18
TS19
TS20
IRQ7_C
IRQ6_C
45 33 27
GTIOC6
A_B
RSPCKB AN019
_C
46 34 28
-
-
P102
P101
P100
P500
P501
P502
GTIOC6
B_B
CTS9_RT
S9_D/
SS9_D
SSLB0_C AN018
ANSD1P
ANSD0N
ANSD0P
TS21
TS22
TS23
TS24
TS25
47 35 29 C6 23
48 36 30 B6 24
49 37 31 A6 25
50 38 32 A5 26
51 39 33 A4 27
GTIOC5
A_B
RXD9_C/
MISO9_C/
SCL9_C
AN017
IVREF2
IVCMP2
IRQ5_C
IRQ4_C
IRQ3_C
IRQ2_C
IRQ1_C
GTIOC5
B_B
TXD9_D/
MOSI9_D/
SDA9_D
AN016
GTIOC5
A_C
RXD0_D/
MISO0_D/
SCL0_D
AN000
DA12_0 IVCMP0 AMP0+
GTIOC5
B_C
TXD0_E/
MOSI0_E/
SDA0_E
AN001
IVREF0
AMP0-
CTS0_RT
S0_E/
AN002
AMP0O
SS0_E
52 40
53 41
-
-
-
-
-
-
P015
P014
AN003
AN004
AMP1O
AMP1-
VREFL
VREFH
GTIOC6
A_C
IVREF1
54 42 34
55
-
-
-
-
P013
P012
GTIOC6
B_C
AN005
AN008
DA8_0
IVCMP1 AMP1+
AMP2O
-
-
56 43 35 B4 28 AVCC0
57 44 36 B3 29 AVSS0
58 45 37 A3 30 VREFL0
59 46 38 A2 31 VREFH0
60
61
62
-
-
-
-
-
-
-
-
-
-
-
-
P003
P002
P001
AN006
AN007
AMP2-
AMP2+
DA8_1
RTCOUT
_D
CTS9_RT
S9_A/
SS9_A
RSPCKB
_D
TS15
TS16
TS17
IRQ0_B
63 47 39 C3
-
P000
P109
AGTIO1
_A
GTIOC4
B_B
RXD9_A/ SCL0_C MISOB_A
MISO9_A/
SCL9_A
KR00/
IRQ4_A
64 48 40 C2 32
AGTOA0 GTETR GTIOC1
_A GB_A B_B
SCK0_C/ SCL1_A MISOA_A ADTRG0_
CMPREF
0/
VCOUT_
A
KR01/
IRQ3_A
TXD9_B/
MOSI9_B/
SDA9_B
B
Note:
Several pin names have the added suffix of _A, _B, _C, _D, _E and _F. The suffix can be ignored when assigning
functionality.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 18 of 100
RA2A1 Datasheet
2. Electrical Characteristics
2.
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = AVCC1 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5 V
VREFH = VREFH0 = 1.6 to AVCC0
VSS = AVSS0 = AVSS1 = VREFL = VREFL0 = VSS_USB = 0 V
Ta = T
.
opr
Note 1. The typical condition is set to VCC = 3.3 V.
Note 2. When USBFS is not used.
Figure 2.1 shows the timing conditions.
For example, P300
C
VOH = VCC × 0.7, VOL = VCC × 0.3
IH = VCC × 0.7, VIL = VCC × 0.3
V
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The measurement conditions for the timing specifications of each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities of each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function
pin is mixed, the A/C specification of each function is not guaranteed.
2.1
Absolute Maximum Ratings
Table 2.1
Absolute maximum ratings (1 of 2)
Parameter
Symbol
VCC
Vin
Value
Unit
V
Power supply voltage
Input voltage
-0.5 to +6.5
-0.3 to +6.5
-0.3 to AVCC0 + 0.3
5 V-tolerant ports*1
V
P002, P003,
P012 to P015,
P500 to P502
Vin
V
P100 to P107
Others
Vin
-0.3 to AVCC1 + 0.3
-0.3 to VCC + 0.3
-0.3 to +6.5
V
V
V
V
V
V
Vin
Reference power supply voltage
VREFH0
VREFH
VREFI
-0.3 to +6.5
-0.3 to AVCC1 + 0.3
-0.5 to +6.5
Analog power supply voltage
AVCC0, AVCC1*5
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Mar 16, 2020
Page 19 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.1
Absolute maximum ratings (2 of 2)
Parameter
Symbol
Value
Unit
USB power supply voltage
VCC_USB
VCC_USB_LDO
VAN
-0.5 to +6.5
V
V
V
-0.5 to +6.5
Analog input voltage
When AN000 to AN008 are
used
-0.3 to AVCC0 + 0.3
When AN016 to AN023 are
used
-0.3 to AVCC1 + 0.3
-0.3 to AVCC1 + 0.3
V
V
When ANSD0P to ANSD3P
and ANSD0N to ANSD3N
are used
Operating temperature*2 *3 *4
Storage temperature
Topr
Tstg
-40 to +85
-40 to +105
°C
°C
-55 to +125
Note 1. Ports P000, P111, P112, P205, P206, P301, P401, P407, and P409 are 5 V tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input
of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might
cause degradation of internal elements.
Note 2. See section 2.2.1, Tj/Ta Definition.
Note 3. Contact Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
Note 4. The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering.
Note 5. Use AVCC0 and AVCC1 under the same conditions:
AVCC0 = AVCC1
Caution:
Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors with high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the
AVCC1 and AVSS1 pins, between the VCC_USB and VSS_USB pins, between the VREFH and VREFL
pins, and between the VREFH0 and VREFL0 pins when VREFH0 is selected as the high potential
reference voltage for the ADC16. Place capacitors of the following value as close as possible to every
power supply pin and use the shortest and heaviest possible traces:
- VCC and VSS: about 0.1 μF
- AVCC0 and AVSS0: about 0.1 μF
- AVCC1 and AVSS1: about 0.1 μF
- VREFH and VREFL: about 0.1 μF
- VREFH0 and VREFL0: about 10 μF.
Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7 μF capacitor. Connect the VREFH0 pin to a VREFL0 pin by
1 µF (-25% to +25%) capacitor when VREFADC is selected as the high potential reference voltage of
the ADC16. Connect the ADREG pin to a AVSS1 pin by a 0.47 µF (-50% to +20%) capacitor. Connect
the SBIAS/VREFI pin to a AVSS1 pin by a 0.22 µF (-20% to +20%) capacitor. Every capacitor must be
placed close to the pin.
Table 2.2
Recommended operating conditions (1 of 2)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC*1, *2
When USBFS is not
used
1.6
-
5.5
V
When USBFS is used VCC_USB
USB Regulator
Disable
-
3.6
5.5
-
V
V
V
When USBFS is used VCC_USB
-
USB Regulator
Enable
_LDO
VSS
-
0
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Page 20 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.2
Recommended operating conditions (2 of 2)
Parameter
Symbol
Value
Min
Typ
Max
Unit
USB power supply voltages
VCC_USB
When USBFS is not
used
-
VCC
-
V
When USBFS is used 3.0
USB Regulator
Disable
3.3
3.6
V
(Input)
VCC_USB_LDO
When USBFS is not
used
-
-
VCC
VCC
-
-
V
V
When USBFS is used
USB Regulator
Disable
When USBFS is used 3.8
USB Regulator
Enable
-
5.5
V
VSS_USB
AVCC0*1, *2
AVSS0
-
0
-
V
V
V
V
V
V
V
V
V
V
Analog power supply voltages
1.6
-
5.5
-
-
-
0
-
AVCC1*1, *2
AVSS1
AVCC0
-
0
-
-
VREFH0
VREFL0
VREFH
When used as
ADC16 Reference
1.7
-
AVCC0
0
-
-
When used as
DAC12 Reference
1.7
-
AVCC0
VREFL
0
-
-
VREFI
When used as
SDADC24
Reference*3
0.8
2.4
Note 1. Use AVCC0, AVCC1, and VCC under the following conditions:
AVCC0, AVCC1, and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 = AVCC1 ≥ 2.2 V.
AVCC0 = AVCC1 = VCC when VCC < 2.2 V or AVCC0 = AVCC1 < 2.2 V.
Note 2. When powering on the VCC and AVCC0 and AVCC1 pins, power them on at the same time or the VCC pin first and then the
AVCC0 and AVCC1 pins.
Note 3. The condition when using external input for the reference voltage of SDADC24.
2.2
DC Characteristics
Tj/Ta Definition
2.2.1
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
125
Unit
Test conditions
Permissible junction temperature
Tj
-
°C
High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
105*1
SubOSC-speed mode
Note:
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL
+ ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C, otherwise it is
125°C.
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.2
I/O VIH, VIL
Table 2.4
I/O VIH, VIL
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Test
Parameter
Symbol
VIH
Min
Typ
Max
Unit
Conditions
Schmitt trigger
input voltage
IIC (except for SMBus)*1
VCC × 0.7
-
-
-
-
-
-
-
5.8
V
-
VIL
-
VCC × 0.3
ΔVT
VIH
VCC × 0.05
VCC × 0.8
-
-
RES, NMI
Other peripheral input pins
excluding IIC
-
VIL
VCC × 0.2
ΔVT
VIH
VCC × 0.1
2.2
-
-
Input voltage
(except for
IIC (SMBus)*2
VCC = 3.6 to
5.5 V
Schmitt trigger
input pin)
VIH
VIL
2.0
-
-
-
-
VCC =2.7 to
3.6 V
0.8
VCC = 2.7 to
5.5 V
5 V-tolerant ports*3
VIH
VIL
VIH
VIL
VCC × 0.8
-
-
-
-
5.8
-
-
VCC × 0.2
P002, P003,
P012 to P015,
P500 to P502
AVCC0 × 0.8
-
-
AVCC0 × 0.2
P100 to P107
VIH
VIL
VIH
AVCC1 × 0.8
-
-
-
-
-
AVCC1 × 0.2
P914, P915
VCC_USB ×
0.8
VCC_USB +
0.3
VIL
-
-
VCC_USB ×
0.2
EXTAL
VIH
VIL
VCC × 0.8
-
-
-
-
Input ports pins except for
P002, P003, P012 to P015,
P100 to P107, P500 to P502,
P914, P915
VCC × 0.2
Note 1. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_C, SCL1_B, SCL1_C, SDA1_B, SDA1_C (total 9 pins)
Note 2. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins)
Note 3. P000, P111, P112, P205, P206, P301, P401, P407, P409 (total 9 pins)
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.3
I/O IOH, IOL
Table 2.5
I/O IOH, IOL
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Symbol
IOH
Min
Typ
Max
-4.0
4.0
Unit
mA
mA
mA
mA
mA
mA
Permissible output current Ports P212, P213
(average value per pin)
-
-
-
-
-
-
-
-
-
-
-
-
-
IOL
Ports P407, P408, P409
Low drive*1
IOH
-4.0
4.0
IOL
Middle drive for IIC IOH
-8.0
8.0
Fast mode and
SPI*4
IOL
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
IOL
IOH
IOL
IOH
IOL
IOH
IOL
IOH
IOL
IOH
IOL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-20.0
20.0
-4.0
4.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Ports P914, P915
Other output pins*3
Low drive*1
Middle drive*2
-
-4.0
4.0
-8.0
8.0
Permissible output current Ports P212, P213
(max value per pin)
-4.0
4.0
Ports P407, P408, P409
Low drive*1
-4.0
4.0
Middle drive for IIC IOH
Fast mode and
SPI*4
-8.0
8.0
IOL
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-20.0
20.0
-4.0
4.0
-4.0
4.0
-8.0
8.0
-30
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOL
Ports P914, P915
Other output pins*3
IOH
IOL
Low drive*1
IOH
IOL
Middle drive*2
IOH
IOL
Permissible output current Total of ports P002, P003, P012 to P015, P500 to
ΣIOH (max)
ΣIOL (max)
ΣIOH (max)
ΣIOL (max)
ΣIOH
(max value total pins)
P502
Total of ports P100 to P107
-30
30
Total of ports P914, P915
Total of all output pin*5
-4.0
4.0
-60
60
ΣIOL
ΣIOH (max)
ΣIOL (max)
Note 1. This is the value when low driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Except for Ports P200, P214, P215, which are input ports.
Note 4. This is the value when middle driving ability for IIC Fast mode and SPI is selected with the Port Drive Capability bit in PmnPFS
register.
Note 5. For details on the permissible output current used with CTSU, see section 2.12, CTSU Characteristics.
Caution:
To protect the reliability of the MCU, the output current values should not exceed the values in Table
2.5. The average output current indicates the average current value measured during 100 μs.
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.4
I/O VOH, VOL, and Other Characteristics
Table 2.6
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 4.0 to 5.5 V
Parameter
Symbol Min
Typ Max Unit Test conditions
Output voltage IIC*1
VOL
VOL*2,*5
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.4
0.6
-
V
IOL = 3.0 mA
IOL = 6.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -4.0 mA
IOL = 4.0 mA
IOH = -20 mA
IOL = 20 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -4.0 mA
IOL = 4.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -4.0 mA
IOL = 4.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -4.0 mA
IOL = 4.0 mA
-
Ports P407, P408,
P409
Low drive
VCC - 0.8
-
0.8
-
Middle drive for IIC
Fast mode and SPI*5
VCC - 0.8
-
0.8
-
Middle drive*2,*3
Low drive
VCC - 1.0
-
1.0
-
Ports P002, P003,
P012 to P015,
P500 to P502
AVCC0 - 0.8
-
0.8
-
Middle drive
Low drive
AVCC0 - 0.8
-
0.8
-
Ports P100 to P107
AVCC1 - 0.8
-
0.8
-
Middle drive
AVCC1 - 0.8
-
0.8
-
Ports P914, P915
Other output pins*4
VCC_USB - 0.8
-
0.8
-
Low drive
VCC - 0.8
-
0.8
-
Middle drive*6
VCC - 0.8
-
0.8
Note 1. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins).
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Based on characterization data, not tested in production.
Note 4. Except for P200, P214, P215, which are input ports.
Note 5. This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in PmnPFS register for
P407, P408, and P409.
Note 6. Except for P212, P213.
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.7
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 2.7 to 4.0 V
Parameter
Symbol Min
Typ Max
Unit Test conditions
Output voltage IIC*1
VOL
-
-
-
-
-
-
-
-
0.4
0.6
-
V
IOL = 3.0 mA
IOL = 6.0 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
VOL*2,*5
VOH
-
Ports P407, P408,
P409
Low drive
VCC - 0.5
VOL
-
0.5
-
Middle drive for IIC
Fast mode and SPI*5
VOH
VCC - 0.5
-
VOL
0.5
-
Middle drive*2,*3
VOH
VCC - 1.0
IOH = -20 mA
VCC = 3.3 V
VOL
-
-
1.0
IOL = 20 mA
VCC = 3.3 V
Ports P002, P003,
P012 to P015,
P500 to P502
Low drive
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
AVCC0 - 0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -2.0 mA
IOL = 2.0 mA
-
0.5
-
Middle drive
Low drive
AVCC0 - 0.5
-
0.5
-
Ports P100 to P107
AVCC1 - 0.5
-
0.5
-
Middle drive
AVCC1 - 0.5
-
0.5
-
Ports P914, P915
Other output pins*4
VCC_USB - 0.5
-
0.5
-
Low drive
VCC - 0.5
-
0.5
-
Middle drive*6
VCC - 0.5
-
0.5
Note 1. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins).
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Based on characterization data, not tested in production.
Note 4. Except for P200, P214, P215, which are input ports.
Note 5. This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in PmnPFS register for
P407, P408, and P409.
Note 6. Except for P212, P213.
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.8
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V
Parameter
Symbol Min
VCC - 0.3
Typ
Max Unit Test conditions
Output voltage Ports P407, P408,
P409
Low drive
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
IOH = -0.5 mA
IOL = 0.5 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -0.5 mA
IOL = 0.5 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -0.5 mA
IOL = 0.5 mA
IOH = -1.0 mA
IOL = 1.0 mA
IOH = -0.5 mA
IOL = 0.5 mA
IOH = -0.5 mA
IOL = 0.5 mA
IOH = -1.0 mA
IOL = 1.0 mA
-
0.3
-
Middle drive for IIC
Fast mode and SPI*2
VCC - 0.3
-
0.3
-
Ports P002, P003,
P012 to P015,
P500 to P502
Low drive
AVCC0 - 0.3
-
0.3
-
Middle drive
AVCC0 - 0.3
-
0.3
-
Ports P100 to P107 Low drive
AVCC0 - 0.3
-
0.3
-
Middle drive
AVCC0 - 0.3
-
0.3
-
Ports P914, P915
VCC_USB - 0.3
-
0.3
-
Other output pins*1 Low drive
VCC - 0.3
-
0.3
-
Middle drive*3
VCC - 0.3
-
0.3
Note 1. Except for ports P200, P214, P215, which are input ports.
Note 2. This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in the
PmnPFS register for P407, P408, and P409.
Note 3. Except for P212, P213.
Table 2.9
I/O other characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Symbol
| Iin
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, ports P200, P214, P215
5 V-tolerant ports
|
-
-
1.0
μA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
| ITSI
|
-
-
1.0
1.0
50
μA
Vin = 0 V
Vin = 5.8 V
Other ports
-
-
Vin = 0 V
Vin = VCC
Input pull-up resistor
Input capacitance
All ports
(except for P200, P214, P215,
P914, P915)
RU
Cin
10
20
kΩ
Vin = 0 V
P012 to P015, P200, P502,
P914, P915
-
-
-
-
30
15
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Other input pins
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.5
Output Characteristics for I/O Pins (Low Drive Capacity)
IOH/IOL vs VOH/VOL
60
50
40
30
20
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
10
0
VCC = 1.6 V
VCC = 1.6 V
-10
-20
-30
-40
VCC = 2.7 V
VCC = 3.3 V
-50
-60
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.2
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
3
Ta = -40C
Ta = 25C
2
Ta = 105C
1
0
-1
-2
Ta = 105C
Ta = 25C
Ta = -40C
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.3
V
OH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data, except for P914 and P915)
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Page 27 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
20
15
10
5
Ta = -40C
Ta = 25C
Ta = 105C
0
-5
Ta = 105C
-10
-15
Ta = 25C
Ta = -40C
-20
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.4
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
30
Ta = -40C
Ta = 25C
20
Ta = 105C
10
0
-10
Ta = 105C
Ta = 25C
Ta = -40C
-20
-30
0
0.5
1
1.5
VOH/VOL [V]
2
2.5
3
3.5
Figure 2.5
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data, except for P914 and P915)
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Mar 16, 2020
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RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
40
20
Ta = -40C
Ta = 25C
Ta = 105C
0
-20
-40
Ta = 105C
Ta = 25C
Ta = -40C
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.6
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data, except for P914 and P915)
2.2.6
Output Characteristics for I/O Pins (Middle Drive Capacity)
IOH/IOL vs VOH/VOL
140
120
VCC = 5.5 V
100
80
60
VCC = 3.3 V
40
VCC = 2.7 V
20
VCC = 1.6 V
0
VCC = 1.6 V
-20
VCC = 2.7 V
-40
VCC = 3.3 V
-60
-80
-100
-120
VCC = 5.5 V
-140
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.7
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data, except for P914 and P915)
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RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
6
4
Ta = -40C
Ta = 25C
Ta = 105C
2
0
-2
-4
Ta = 105C
Ta = 25C
Ta = -40C
-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
40
Ta = -40C
Ta = 25C
30
Ta = 105C
20
10
0
-10
-20
Ta = 105C
Ta = 25C
-30
Ta = -40C
-40
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.9
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data, except for P914 and P915)
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RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
40
20
Ta = -40C
Ta = 25C
Ta = 105C
0
-20
-40
Ta = 105C
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
VOH/VOL [V]
2
2.5
3
3.5
Figure 2.10
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
140
Ta = -40C
Ta = 25C
120
100
Ta = 105C
80
60
40
20
0
-20
-40
-60
-80
Ta = 105C
-100
Ta = 25C
-120
Ta = -40C
-140
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.11
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data, except for P914 and P915)
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.7
Output Characteristics for P407, P408 and P409 I/O Pins (Middle Drive
Capacity)
IOH/IOL vs VOH/VOL
200
180
160
140
120
100
80
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
60
40
20
0
-20
-40
-60
VCC = 2.7 V
VCC = 3.3 V
-80
-100
-120
-140
-160
-180
-200
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.12
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
Ta = 105C
40
20
0
-20
-40
Ta = 105C
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.13
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
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RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
100
80
Ta = -40C
Ta = 25C
Ta = 105C
60
40
20
0
-20
-40
Ta = 105C
Ta = 25C
-60
-80
Ta = -40C
-100
0
0.5
1
1.5
VOH/VOL [V]
2
2.5
3
3.5
Figure 2.14
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
220
Ta = -40C
180
140
100
Ta = 25C
Ta = 105C
60
20
-20
-60
-100
-140
-180
-220
Ta = 105C
Ta = 25C
Ta = -40C
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.15
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.8
Output Characteristics for IIC I/O Pins
IOL vs VOL
120
110
100
90
VCC = 5.5 V (Middle drive)
80
70
60
50
40
30
20
10
VCC = 3.3 V (Middle drive)
VCC = 5.5 V (Low drive)
VCC = 2.7 V (Middle drive)
VCC = 3.3 V (Low drive)
VCC = 2.7 V (Low drive)
0
0
1
2
3
4
5
6
VOL [V]
Figure 2.16
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
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RA2A1 Datasheet
2. Electrical Characteristics
2.2.9
Operating and Standby Current
Table 2.10
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Test
10
Parameter
Symbol Typ*
ICC
Max
Unit Conditions
Supply
current*1
High-speed
mode*2
Normal mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 48 MHz
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
5.2
3.8
2.3
1.6
12.1
8.3
4.6
2.8
12.6
10.9
5.9
3.4
-
-
mA
*7, *11
-
-
-
All peripheral clocks
disabled, CoreMark code
executing from flash*5
-
-
-
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
-
*9, *11
*8, *11
-
-
-
All peripheral clocks
enabled, code executing
from flash*5
28.5
*9, *11
7
*
Sleep mode
All peripheral clocks
disabled*5
ICLK = 48 MHz
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
2.7
2.1
1.5
1.1
9.8
8.9
5.0
2.9
2.5
1.6
1.3
-
-
-
-
-
-
-
-
-
-
-
9
*
All peripheral clocks
enabled*5
8
*
Increase during BGO operation*6
-
Middle-speed Normal mode
mode*2
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 12 MHz
ICLK = 8 MHz
ICC
mA
*7, *11
All peripheral clocks
disabled, CoreMark code
executing from flash*5
ICLK = 12 MHz
ICLK = 8 MHz
3.4
2.6
-
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 12 MHz
ICLK = 8 MHz
4.3
3.1
-
-
*8, *11
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 12 MHz
-
12.6
7
*
Sleep mode
All peripheral clocks
disabled*5
ICLK = 12 MHz
ICLK = 8 MHz
ICLK = 12 MHz
ICLK = 8 MHz
1.0
0.9
3.6
2.7
2.5
-
-
-
-
-
8
*
All peripheral clocks
enabled*5
Increase during BGO operation*6
-
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.10
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Test
10
Parameter
Symbol Typ*
Max
Unit Conditions
Supply
current*1
Low-speed
mode*3
Normal mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz
ICLK = 1 MHz
ICLK = 1 MHz
ICLK = 1 MHz
ICC
ICC
ICC
0.3
0.4
0.5
-
-
mA
mA
μA
*7, *11
All peripheral clocks
disabled, CoreMark code
executing from flash*5
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
-
*8, *11
All peripheral clocks
enabled, code executing
from flash*5
2.5
7
*
Sleep mode
All peripheral clocks
disabled*5
ICLK = 1 MHz
ICLK = 1 MHz
ICLK = 4 MHz
0.2
0.4
1.5
-
-
-
8
*
All peripheral clocks
enabled*5
Low-voltage
mode*3
Normal mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
*7, *11
All peripheral clocks
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz
ICLK = 4 MHz
ICLK = 4 MHz
2.2
2.5
-
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
-
*8, *11
All peripheral clocks
enabled, code executing
from flash*5
7.0
7
*
Sleep mode
All peripheral clocks
disabled*5
ICLK = 4 MHz
1.3
2.3
6.5
-
-
-
8
*
All peripheral clocks
enabled*5
ICLK = 4 MHz
Subosc-
speed
mode*4
Normal mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
*8, *11
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
ICLK = 32.768 kHz
12.1
-
-
All peripheral clocks
enabled, code executing
from flash*5
190.0
8
*
Sleep mode
All peripheral clocks
disabled*5
ICLK = 32.768 kHz
ICLK = 32.768 kHz
4.5
-
-
8
*
All peripheral clocks
enabled*5
10.2
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. FCLK, PCLKB, and PCLKD are set to divided by 64.
Note 8. FCLK, PCLKB, and PCLKD are the same frequency as that of ICLK.
Note 9. FCLK and PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK.
Note 10. VCC = 3.3 V.
Note 11. The flash cache is operating.
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RA2A1 Datasheet
2. Electrical Characteristics
30
25
20
15
10
5
Ta = 105Ԩ, ICLK = 48MHz*2
Ta = 105Ԩ, ICLK = 32MHz*2
Ta = 25Ԩ, ICLK = 48MHz*1
Ta = 105Ԩ, ICLK = 16MHz*2
Ta = 25Ԩ, ICLK = 32MHz*1
Ta = 105Ԩ, ICLK = 8MHz*2
Ta = 25Ԩ, ICLK = 16MHz*1
㻢㻚㻜
Ta = 105Ԩ, ICLK = 4MHz*2
Ta = 25Ԩ, ICLK = 8MHz*1
Ta = 25Ԩ, ICLK = 4MHz*1
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
VCC (V)
Ta = 25Ԩ, ICLK = 48MHz *1
Ta = 25Ԩ, ICLK = 32MHz *1
Ta = 25Ԩ, ICLK = 16MHz *1
Ta = 25Ԩ, ICLK = 8MHz *1
Ta = 25, ICLK = 4MHz *1
Ta = 105Ԩ, ICLK = 48MHz *2
Ta = 105Ԩ, ICLK = 32MHz *2
Ta = 105Ԩ, ICLK = 16MHz *2
Ta = 105Ԩ, ICLK = 8MHz *2
Ta = 105, ICLK = 4MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.17
Voltage dependency in high-speed operating mode (reference data)
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RA2A1 Datasheet
2. Electrical Characteristics
10
9
8
7
6
5
4
3
2
1
Ta = 105, ICLK = 12MHz*2
Ta = 105, ICLK = 8MHz*2
Ta = 25, ICLK = 12MHz*1
Ta = 105, ICLK = 4MHz*2
Ta = 25, ICLK = 8MHz*1
Ta = 25, ICLK = 4MHz*1
Ta = 105, ICLK = 1MHz*2
Ta = 25, ICLK = 1MHz*1
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
VCC (V)
Ta = 25Ԩ, ICLK = 12MHz *1
Ta = 25Ԩ, ICLK = 8MHz *1
Ta = 25Ԩ, ICLK = 4MHz *1
Ta = 25, ICLK = 1MHz *1
Ta = 105Ԩ, ICLK = 12MHz *2
Ta = 105Ԩ, ICLK = 8MHz *2
Ta = 105Ԩ, ICLK = 4MHz *2
Ta = 105, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.18
Voltage dependency in middle-speed operating mode (reference data)
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RA2A1 Datasheet
2. Electrical Characteristics
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Ta = 105, ICLK = 1MHz*2
Ta = 25, ICLK = 1MHz*1
0.0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
VCC (V)
Ta = 25, ICLK = 1MHz *1
Ta = 105, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.19
Voltage dependency in low-speed operating mode (reference data)
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RA2A1 Datasheet
2. Electrical Characteristics
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Ta = 105, ICLK = 4MHz*2
Ta = 25, ICLK = 4MHz*1
Ta = 105, ICLK = 1MHz*2
Ta = 25, ICLK = 1MHz*1
0.0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
VCC (V)
Ta = 25Ԩ, ICLK = 4MHz *1
Ta = 25, ICLK = 1MHz *1
Ta = 105Ԩ, ICLK = 4MHz *2
Ta = 105, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.20
Voltage dependency in low-voltage operating mode (reference data)
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Mar 16, 2020
Page 40 of 100
RA2A1 Datasheet
2. Electrical Characteristics
180
160
140
120
100
80
Ta = 105, ICLK = 32kHz*2
Ta = 25, ICLK = 32kHz*1
60
40
20
Ta = 25, ICLK = 32kHz*1*3
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
VCC (V)
Ta = 25Ԩ, ICLK = 32kHz *1
Ta = 25, ICLK = 32kHz *1*3
Ta = 105Ԩ, ICLK = 32kHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Note 3. MOCO and DAC are stopped.
Figure 2.21
Voltage dependency in subosc-speed operating mode (reference data)
Operating and standby current (2)
Table 2.11
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Symbol Typ*3
Max
2.0
7.0
17.0
45.0
-
Unit
Test conditions
Supply
current*1
Software Standby Ta = 25°C
ICC
0.5
0.8
1.8
4.4
0.4
μA
-
mode*2
Ta = 55°C
Ta = 85°C
Ta = 105°C
Increment for RTC operation with
low-speed on-chip oscillator*4
-
Increment for RTC operation with
sub-clock oscillator*4
0.5
1.3
-
-
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
SOMCR.SODRV[1:0] are 00b
(normal mode)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOS transistors are in the off state.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the low-speed on-chip oscillator or sub-oscillation circuit current.
R01DS0354EJ0110 Rev.1.10
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Page 41 of 100
RA2A1 Datasheet
2. Electrical Characteristics
100
10
1
0.1
㻙㻠㻜
㻙㻞㻜
㻜
㻞㻜
㻠㻜
㻢㻜
㻤㻜
㻝㻜㻜
Ta (Ԩ)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.22
Temperature dependency in Software Standby mode (reference data)
10
Normal drive capacity*1
Low drive capacity*1
1
0
㻙㻠㻜
㻙㻞㻜
㻜
㻞㻜
㻠㻜
㻢㻜
㻤㻜
㻝㻜㻜
Ta (Ԩ)
Low drive capacity*1
Normal drive capacity*1
Note:
Average value of the tested middle samples during product evaluation.
Figure 2.23
Temperature dependency of RTC operation (reference data)
R01DS0354EJ0110 Rev.1.10
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.12
Operating and standby current (3)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Test
Parameter
Symbol Min Typ
Max
1.5
Unit
mA
mA
mA
μA
conditions
Analog power
supply current
During 16-bit A/D conversion
IAVCC0
-
-
-
-
-
-
-
-
-
-
-
-
During 8-bit D/A conversion (per channel) *1
During 12-bit D/A conversion (per channel) *1
1.6
0.9
Waiting for 16-bit A/D, 8-bit D/A and 12-bit D/A
conversion (all units) *5
2.0
During 24-bit sigma-delta A/D conversion
(at normal mode)
IAVCC1
-
-
-
-
-
-
1.29
1.06
0.9
mA
mA
mA
-
During 24-bit sigma-delta A/D conversion
(at low-power conversion)
G
G
SET1 = 8, or
TOTAL = 24,32
G
SET1, GTOTAL =
the others
Waiting for 24-bit sigma-delta A/D conversion*6
During 16-bit A/D conversion
-
-
-
-
-
-
-
-
-
-
-
-
1.0
80
μA
μA
nA
μA
nA
μA
-
-
-
-
-
Reference
power supply
current
IREFH0
IREFH
IREFI
Waiting for 16-bit A/D conversion
During 12-bit D/A conversion
60
650
100
30
Waiting for 12-bit D/A conversion
During 24-bit sigma-delta A/D conversion
External VREF
mode
Temperature Sensor (TSN) operating current
ITNS
-
-
-
-
75
15
10
2
-
-
-
-
μA
μA
μA
μA
-
-
-
-
Low-power
Analog
Window comparator (high-speed mode)
ICMPLP
Comparator (high-speed mode)
Comparator (low-speed mode)
Comparator
(ACMPLP)
operating
current
High-speed analog comparator (ACMPHS) operating current
ICPMHS
IAMP
-
-
-
-
-
-
-
-
-
-
-
-
70
100
16
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
μA
mA
AVCC0 ≥ 2.7 V
Operational
Amplifier
(OPAMP)
operating
current
Low power mode
Middle speed mode
High speed mode
1 unit operating
2 unit operating
3 unit operating
1 unit operating
2 unit operating
3 unit operating
1 unit operating
2 unit operating
3 unit operating
10
-
-
-
-
-
-
-
-
-
-
-
19
30
28
44
280
530
770
0.74
1.41
2.07
65
360
690
1020
0.91
1.74
2.57
130
-
Internal reference voltage for ADC16 operating current
IVREFADC
2
USBFS
operating
current
During USB communication under the following
settings and conditions:
IUSBF
*
3.6 (VCC)
1.1 (VCC_USB)*4
Function controller is in Full-Speed mode and
- Bulk OUT transfer is (64 bytes) × 1
- Bulk IN transfer is (64 bytes) × 1
Host device is connected by a 1-meter USB cable
from the USB port.
3
During suspended state under the following setting
and conditions:
ISUSP
*
-
0.35 (VCC)
170 (VCC_USB)*4
-
μA
-
Function controller is in Full-Speed mode (the
USB_DP pin is pulled up)
Software Standby mode
Host device is connected through a 1-meter USB
cable from the USB port.
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. Current is consumed only by the USBFS.
Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition
to the current consumed by the MCU in the suspended state.
Note 4. When VCC = VCC_USB = 3.3 V.
Note 5. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC160 module-stop bit) is in the module-stop
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RA2A1 Datasheet
2. Electrical Characteristics
state.
Note 6. When the MCU is in the MSTPCRD.MSTPD17 (SDADC24 module-stop bit) is in the module-stop state.
2.2.10
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.13
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = AVCC1 = 0 to 5.5 V
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
SrVCC 0.02
-
2
-
ms/V
-
Voltage monitor 0 reset enabled at startup*1,
SCI/USB boot mode*2
*
2
2
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.14
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When the VCC change exceeds VCC ± 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple frequency
fr(VCC)
-
-
10
kHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.2
-
-
-
-
1
MHz
MHz
ms/V
Figure 2.24
V
r (VCC) ≤ VCC × 0.08
Figure 2.24
r (VCC) ≤ VCC × 0.06
When VCC change exceeds VCC ± 10%
-
10
-
V
Allowable voltage change rising and
falling gradient
dt/dVCC
1.0
1 / fr(VCC)
VCC
Vr(VCC)
Figure 2.24
Ripple waveform
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RA2A1 Datasheet
2. Electrical Characteristics
2.3
AC Characteristics
2.3.1
Frequency
Table 2.15
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max*7
48
Unit
Operation
frequency
System clock (ICLK)*6
2.7 to 5.5 V
2.4 to 2.7 V
2.7 to 5.5 V
2.4 to 2.7 V
f
0.032768
-
-
-
-
-
-
-
-
MHz
0.032768
16
FlashIF clock (FCLK)*1,*2,*6
0.032768
32
0.032768
16
Peripheral module clock (PCLKB)*5,*6 2.7 to 5.5 V
2.4 to 2.7 V
-
-
-
-
32
16
Peripheral module clock (PCLKD)*3,*6 2.7 to 5.5 V
2.4 to 2.7 V
64*4
16
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK
for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or
3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The upper-limit frequency of PCLKD is 32 MHz when the ADC16 is in use.
Note 5. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 6. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, PCLKD, and FCLK.
Note 7. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for
guaranteed operation, see Table 2.20, Clock timing.
Table 2.16
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max*6
12
12
8
Unit
Operation
frequency
System clock (ICLK)*5
2.7 to 5.5 V
2.4 to 2.7 V
1.8 to 2.4 V
2.7 to 5.5 V
2.4 to 2.7 V
1.8 to 2.4 V
2.7 to 5.5 V
2.4 to 2.7 V
1.8 to 2.4 V
2.7 to 5.5 V
2.4 to 2.7 V
1.8 to 2.4 V
f
0.032768
-
-
-
-
-
-
-
-
-
-
-
-
MHz
0.032768
0.032768
FlashIF clock (FCLK)*1,*2,*5
0.032768
12
12
8
0.032768
0.032768
Peripheral module clock (PCLKB)*4,*5
Peripheral module clock (PCLKD)*3,*5
-
-
-
-
-
-
12
12
8
12
12
8
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK
for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3
MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK must be ± 3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 5. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
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RA2A1 Datasheet
2. Electrical Characteristics
PCLKB, PCLKD, and FCLK.
Note 6. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for
guaranteed operation, see Table 2.20, Clock timing.
Table 2.17
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max*6
Unit
Operation
frequency
System clock (ICLK)*5
1.8 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
f
0.032768
-
-
-
-
1
1
1
1
MHz
FlashIF clock (FCLK) *1,*2,*5
0.032768
Peripheral module clock (PCLKB)*4,*5
Peripheral module clock (PCLKD)*3,*5
-
-
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of FCLK must be ± 3.5% while programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 5. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
Note 6. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.20, Clock timing.
Table 2.18
Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max*6
Unit
Operation
frequency
System clock (ICLK)*5
1.6 to 5.5 V
1.6 to 5.5 V
1.6 to 5.5 V
1.6 to 5.5 V
f
0.032768
-
-
-
-
4
4
4
4
MHz
FlashIF clock (FCLK)*1,*2,*5
0.032768
Peripheral module clock (PCLKB)*4,*5
Peripheral module clock (PCLKD)*3,*5
-
-
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer
frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 5. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
Note 6. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.20, Clock timing.
Table 2.19
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Operation
frequency
System clock (ICLK)*4
1.8 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
f
27.8528 32.768
27.8528 32.768
37.6832
37.6832
37.6832
37.6832
kHz
FlashIF clock (FCLK)*1,*4
Peripheral module clock (PCLKB)*3,*4
Peripheral module clock (PCLKD)*2,*4
-
-
-
-
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The ADC16 cannot be used.
Note 3. The SDADC24 cannot be used.
Note 4. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
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2. Electrical Characteristics
2.3.2
Clock Timing
Table 2.20
Clock timing (1 of 2)
Parameter
Symbol
tXcyc
tXH
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
EXTAL external clock input high pulse width
EXTAL external clock input low pulse width
EXTAL external clock rising time
50
-
-
ns
Figure 2.25
20
-
-
ns
tXL
20
-
-
ns
tXr
-
-
5
ns
EXTAL external clock falling time
tXf
-
-
5
ns
EXTAL external clock input wait time*1
EXTAL external clock input frequency
tEXWT
fEXTAL
0.3
-
-
μs
-
-
-
20
MHz
2.4 ≤ VCC ≤ 5.5
-
-
8
1.8 ≤ VCC < 2.4
-
-
1
1.6 ≤ VCC < 1.8
Main clock oscillator oscillation frequency
fMAIN
1
-
20
MHz
2.4 ≤ VCC ≤ 5.5
1
-
8
1.8 ≤ VCC < 2.4
1
-
4
1.6 ≤ VCC < 1.8
LOCO clock oscillation frequency
fLOCO
27.8528
32.768
37.6832
100
17.25
9.2
kHz
μs
-
LOCO clock oscillation stabilization time
IWDT-dedicated clock oscillation frequency
MOCO clock oscillation frequency
tLOCO
-
-
Figure 2.26
fILOCO
fMOCO
tMOCO
fHOCO24
12.75
6.8
15
8
kHz
MHz
μs
-
-
-
MOCO clock oscillation stabilization time
HOCO clock oscillation frequency
-
-
1
23.64
24
24.36
MHz
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
22.68
23.76
23.52
31.52
30.24
31.68
31.36
47.28
47.52
47.04
63.04
63.36
62.72
-
24
24
24
32
32
32
32
48
48
48
64
64
64
-
25.32
24.24
24.48
32.48
33.76
32.32
32.64
48.72
48.48
48.96
64.96
64.64
65.28
37.1
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
fHOCO32
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
3
fHOCO48
*
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
4
fHOCO64
*
Ta = -40 to -20°C
2.4 ≤ VCC ≤ 5.5
Ta = -20 to 85°C
2.4 ≤ VCC ≤ 5.5
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
HOCO clock oscillation
Except low-voltage
mode
tHOCO24
tHOCO32
μs
Figure 2.27
6
stabilization time*5,
*
tHOCO48
tHOCO64
-
-
-
-
-
-
43.3
80.6
100.9
Low-voltage mode
tHOCO24
tHOCO32
tHOCO48
tHOCO64
Sub-clock oscillator oscillation frequency
fSUB
-
32.768
-
kHz
-
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.20
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Sub-clock oscillation stabilization time*2
tSUBOSC
-
0.5
-
s
Figure 2.28
Note 1. Time until the clock can be used after the Main Clock Oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock
oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the
oscillator manufacturer.
Note 3. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
Note 4. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
Note 5. This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state.
When the HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs.
Note 6. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
tXf
Figure 2.25
EXTAL external clock input timing
LOCOCR.LCSTP
LOCO clock oscillator output
tLOCO
Figure 2.26
LOCO clock oscillation start timing
HOCOCR.HCSTP
HOCO clock
*1
tHOCOx
Note 1. x = 24, 32, 48, 64
Figure 2.27
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.28
Sub-clock oscillation start timing
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RA2A1 Datasheet
2. Electrical Characteristics
2.3.3
Reset Timing
Table 2.21
Reset timing
Test
Parameter
Symbol
tRESWP
tRESW
Min
Typ
-
Max
Unit
ms
μs
conditions
Figure 2.29
Figure 2.30
Figure 2.29
RES pulse width
At power-on
3
30
-
-
-
-
-
-
-
-
-
Not at power-on
LVD0 enabled*1
LVD0 disabled*2
LVD0 enabled*1
LVD0 disabled*2
LVD0 enabled*1
LVD0 disabled*2
-
Wait time after RES cancellation
(at power-on)
tRESWT
0.7
0.3
0.5
0.1
0.6
0.15
ms
-
Wait time after RES cancellation
(during powered-on state)
tRESWT2
-
ms
ms
Figure 2.30
Figure 2.31
-
Wait time after internal reset cancellation
(Watchdog timer reset, SRAM parity error
reset, SRAM ECC error reset, bus master
MPU error reset, bus slave MPU error reset,
stack pointer error reset, software reset)
tRESWT3
-
-
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.29
Figure 2.30
Figure 2.31
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Reset input timing (1)
tRESWIW, tRESWIR
Independent watchdog timer reset
Software reset
Internal reset
tRESWT3
Reset input timing (2)
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RA2A1 Datasheet
2. Electrical Characteristics
2.3.4
Wakeup Time
Table 2.22
Parameter
Timing of recovery from low power modes (1)
Test
conditions
Symbol Min Typ
Max Unit
2
Recovery time
from Software
Standby mode*1
High-speed
mode
Crystal
System clock source is tSBYMC
main clock oscillator
(20 MHz)*2
-
3
ms
Figure 2.32
resonator
connected to
main clock
oscillator
14
External clock
input to main
clock oscillator
System clock source is tSBYEX
main clock oscillator
(20 MHz)*3
-
25
μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO
tSBYHO
tSBYHO
tSBYMO
-
-
-
-
43
44
82
16
52
μs
μs
μs
μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
52
System clock source is HOCO*5
(HOCO clock is 64 MHz)
110
25
System clock source is MOCO
Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h.
Note 5. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h.
Table 2.23
Parameter
Timing of recovery from low power modes (2)
Test
conditions
Symbol Min Typ
Max Unit
Recovery time
from Software
Standby mode*
Middle-speed Crystal
mode resonator
System clock source is
main clock oscillator
(12 MHz)*
tSBYMC
-
2
3
ms
Figure 2.32
1
2
connected to
main clock
oscillator
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(12 MHz)*
tSBYEX
-
2.9
10
μs
3
System clock source is HOCO*4
tSBYHO
tSBYMO
-
-
38
50
μs
μs
System clock source is MOCO (8 MHz)
3.5
5.5
Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The system clock is 12 MHz.
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.24
Parameter
Timing of recovery from low power modes (3)
Test
Symbol Min Typ Max Unit conditions
Recovery time
from Software
Standby mode*
Low-speed
mode
Crystal
System clock source is
main clock oscillator
(1 MHz)*
tSBYMC
-
2
3
ms
Figure 2.32
resonator
connected to
main clock
oscillator
1
2
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*
tSBYEX
-
-
28
25
50
35
μs
μs
3
System clock source is MOCO (1 MHz)
tSBYMO
Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.25
Parameter
Timing of recovery from low power modes (4)
Test
conditions
Symbol Min Typ
Max
Unit
Recovery time
from Software
Standby mode*
Low-voltage
mode
Crystal
System clock source is tSBYMC
main clock oscillator
(4 MHz)*
-
2
3
ms
Figure 2.32
resonator
connected to
main clock
oscillator
1
2
External clock
input to main
clock oscillator
System clock source is tSBYEX
main clock oscillator
(4 MHz)*
-
-
108
108
130
130
μs
μs
3
System clock source is HOCO (4 MHz)
tSBYHO
Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.26
Parameter
Timing of recovery from low power modes (5)
Test
Symbol Min Typ Max Unit conditions
Recovery time
from Software
Standby mode*1
Subosc-speed mode
System clock source is sub-clock tSBYSC
oscillator (32.768 kHz)
-
0.85
1
ms
Figure 2.32
System clock source is LOCO
(32.768 kHz)
tSBYLO
-
0.85 1.2
ms
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.
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RA2A1 Datasheet
2. Electrical Characteristics
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.32
Software Standby mode cancellation timing
Timing of recovery from low power modes (6)
Table 2.27
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Recovery time from Software High-speed mode
tSNZ
-
36
45
μs
Figure 2.33
Standby mode to Snooze
mode
System clock source is HOCO
Middle-speed mode
System clock source is MOCO
(8 MHz)
tSNZ
-
1.3
10
87
3.6
13
μs
μs
μs
Low-speed mode
System clock source is MOCO
(1 MHz)
tSNZ
-
-
Low-voltage mode
System clock source is HOCO
(4 MHz)
tSNZ
110
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.33
Recovery timing from Software Standby mode to Snooze mode
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2. Electrical Characteristics
2.3.5
NMI and IRQ Noise Filter
Table 2.28
NMI and IRQ noise filter
Symbol Min
Parameter
Typ
Max
Unit
Test conditions
NMI pulse width
tNMIW
200
Pcyc × 2*
200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
NMI digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
tNMICK × 3 ≤ 200 ns
tNMICK × 3 > 200 ns
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
1
t
NMI digital filter enabled
IRQ digital filter disabled
IRQ digital filter enabled
2
tNMICK × 3.5*
200
IRQ pulse width
tIRQW
ns
1
tPcyc × 2*
200
t
IRQCK × 3 ≤ 200 ns
3
tIRQCK × 3.5*
tIRQCK × 3 > 200 ns
Note:
Note:
Note 1.
200 ns minimum in Software Standby mode.
If the clock source is switched, add 4 clock cycles of the switched source.
Pcyc indicates the PCLKB cycle.
t
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 2.34
NMI interrupt input timing
IRQ
tIRQW
Figure 2.35
IRQ interrupt input timing
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RA2A1 Datasheet
2. Electrical Characteristics
2.3.6
I/O Ports, POEG, GPT, AGT, KINT, and ADC16 Trigger Timing
Note:
Table 2.29
I/O Ports, POEG, GPT, AGT, KINT, and ADC16 trigger timing
Test
Parameter
I/O Ports
POEG
Symbol Min
Max
Unit
conditions
Figure 2.36
Figure 2.37
Figure 2.38
Input data pulse width
tPRW
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tPcyc
tPcyc
tPDcyc
POEG input trigger pulse width
Input capture pulse width
tPOEW
tGTICW
3
GPT
Single edge
Dual edge
1.5
2.5
1
AGT
AGTIO, AGTEE input cycle
2.7 V ≤ VCC ≤ 5.5 V tACYC
*
250
500
1000
2000
100
200
400
800
62.5
125
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 2.39
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTEE input high-level
width, low-level width
2.7 V ≤ VCC ≤ 5.5 V tACKWH,
tACKWL
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V tACYC2
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
AGTIO, AGTO, AGTOA, AGTOB
output cycle
Figure 2.39
1.6 V ≤ VCC < 1.8 V
500
1.5
-
-
-
ns
ADC16
KINT
16-bit A/D converter trigger input pulse width
KRn (n = 00 to 07) pulse width
tTRGW
tKR
tPcyc
ns
Figure 2.40
Figure 2.41
250
Note:
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.
Port
tPRW
Figure 2.36
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.37
POEG input trigger timing
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RA2A1 Datasheet
2. Electrical Characteristics
Input capture
tGTICW
Figure 2.38
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.39
AGT I/O timing
ADTRG0
tTRGW
Figure 2.40
ADC16 trigger input timing
KR00 to KR07
tKR
Figure 2.41
Key interrupt input timing
2.3.7
CAC Timing
Table 2.30
CAC timing
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Test
Parameter
Symbol Min
Typ
Max
Unit
ns
conditions
2
CAC
CACREF input pulse width
tPcyc
*
1 ≤ tcac
*
tCACREF 4.5 × tcac + 3 × tPcyc
5 × tcac + 6.5 × tPcyc
-
-
-
-
-
2
t
Pcyc*1 > tcac
*
ns
Note 1. tPcyc: PCLKB cycle.
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2. Electrical Characteristics
Note 2. tcac: CAC count clock source cycle.
2.3.8
SCI Timing
Table 2.31
SCI timing (1)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Symbol
Min
4
Max
-
Unit*1
Test conditions
SCI
Input clock cycle
Asynchronous
tScyc
tPcyc
Figure 2.42
Clock synchronous
6
-
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
tSCKW
tSCKr
tSCKf
tScyc
0.4
-
0.6
20
20
-
tScyc
ns
-
ns
Asynchronous
6
tPcyc
Clock synchronous
4
-
Output clock pulse width
Output clock rise time
tSCKW
0.4
-
0.6
20
30
20
30
40
45
55
60
100
125
-
tScyc
ns
1.8 V ≤ VCC ≤ 5.5 V tSCKr
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V tSCKf
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V tTXD
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V tRXS
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 2.7 V
-
Output clock fall time
-
ns
ns
ns
-
Transmit data delay Clock
-
Figure 2.43
(master)
synchronous
-
Transmit data delay Clock
-
(slave)
synchronous
-
-
-
Receive data setup
time (master)
Clock
synchronous
45
55
90
110
40
45
5
ns
ns
-
-
-
Receive data setup
time (slave)
Clock
synchronous
-
-
Receive data hold
time (master)
Clock synchronous
tRXH
-
ns
ns
Receive data hold
time (slave)
Clock synchronous
tRXH
40
-
Note 1. tPcyc: PCLKB cycle.
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2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0, 1, 9)
tScyc
Figure 2.42
SCK clock input timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 0, 1, 9
Figure 2.43
SCI input/output timing in clock synchronous mode
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.32
SCI timing (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Symbol
Min
4
Max
Unit*1
Test conditions
Figure 2.44
Simple SCK clock cycle output (master)
tSPcyc
65536
65536
0.6
tPcyc
SPI
SCK clock cycle input (slave)
6
SCK clock high pulse width
tSPCKWH
0.4
tSPcyc
SCK clock low pulse width
SCK clock rise and fall time
tSPCKWL
tSPCKr,
tSPCKf
0.4
0.6
20
30
tSPcyc
ns
-
-
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
Data input setup
time
Master
2.7 V ≤ VCC ≤ 5.5 V tSU
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 2.7 V
tH
45
55
80
110
40
45
33.3
40
1
-
-
-
-
-
-
-
-
-
ns
Figure 2.45 to
Figure 2.48
Slave
Data input hold time Master
Slave
ns
SS input setup time
tLEAD
tSPcyc
tSPcyc
ns
SS input hold time
tLAG
1
-
Data output delay
Master
Slave
1.8 V ≤ VCC ≤ 5.5 V tOD
1.6 V ≤ VCC < 1.8 V
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V tOH
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
-
40
50
65
100
125
-
-
-
-
-
Data output hold
time
Master
-10
-20
-30
-40
-10
-
ns
ns
-
-
-
Slave
-
Data rise and fall
time
Master
1.8 V ≤ VCC ≤ 5.5 V tDr, tDf
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
tSA
20
30
20
30
6
-
Slave
-
-
Simple Slave access time
SPI
-
tPcyc
tPcyc
Figure 2.48
Slave output release time
tREL
-
6
Note 1. tPcyc: PCLKB cycle.
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2. Electrical Characteristics
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
SCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
SCKn
slave select input
VIL
tSPCKWL
VIL
(n = 0, 1, 9)
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.44
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.45
SCI simple SPI mode timing (master, CKPH = 1)
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.46
SCI simple SPI mode timing (master, CKPH = 0)
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2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
(n = 0, 1, 9)
Figure 2.47
SCI simple SPI mode timing (slave, CKPH = 1)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
(n = 0, 1, 9)
Figure 2.48
SCI simple SPI mode timing (slave, CKPH = 0)
SCI timing (3)
Table 2.33
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Parameter
Symbol
tSr
Min
Max
Unit
ns
Test conditions
Simple IIC
(Standard mode)
SDA input rise time
-
1000
Figure 2.49
SDA input fall time
tSf
-
300
ns
1
SDA input spike pulse removal time
Data input setup time
tSP
0
4 × tIICcyc
*
ns
tSDAS
tSDAH
Cb*2
250
-
ns
Data input hold time
0
-
-
ns
SCL, SDA capacitive load
400
pF
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.33
SCI timing (3)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Parameter
Symbol
tSr
Min
Max
Unit
ns
Test conditions
Simple IIC
SDA input rise time
-
300
Figure 2.49
(Fast mode)
SDA input fall time
tSf
-
300
ns
1
SDA input spike pulse removal time
Data input setup time
tSP
0
4 × tIICcyc
*
ns
tSDAS
tSDAH
Cb*2
100
-
ns
Data input hold time
0
-
-
ns
SCL, SDA capacitive load
400
pF
Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Note 2. Cb indicates the total capacity of the bus line.
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
P*1
S*1
Sr*1
(n = 0, 1, 9)
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.49
SCI simple IIC mode timing
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2. Electrical Characteristics
2.3.9
SPI Timing
Table 2.34
SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
*1
Parameter
Symbol Min
Max
4096
4096
-
Unit
Test conditions
SPI RSPCK clock cycle Master
Slave
tSPcyc
2
6
tPcyc
Figure 2.50
C = 30 pF
RSPCK clock high
pulse width
Master
tSPCKWH (tSPcyc - tSPCKr
- tSPCKf) / 2 - 3
ns
ns
Slave
3 × tPcyc
-
-
RSPCK clock low
pulse width
Master
tSPCKWL (tSPcyc - tSPCKr
- tSPCKf) / 2 - 3
Slave
3 × tPcyc
-
RSPCK clock rise
and fall time
Output 2.7 V ≤ VCC ≤ 5.5 V tSPCKr,
-
-
-
-
-
10
15
20
30
1
ns
tSPCKf
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
µs
ns
Data input setup
time
Master
Slave
tSU
10
10
15
20
0
-
-
-
-
-
Figure 2.51 to
Figure 2.56
C = 30 pF
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Data input hold
time
Master
(RSPCK is PCLKB/2)
tHF
tH
ns
ns
Master
tPcyc
20
-
(RSPCK is not PCLKB/2)
Slave
tH
-
-
SSL setup time
Master 1.8 V ≤ VCC ≤ 5.5 V tLEAD
1.6 V ≤ VCC < 1.8 V
Slave
-30 + N ×
tSpcyc
2
*
-50 + N ×
tSpcyc
-
2
*
6 × tPcyc
-
-
ns
ns
SSL hold time
Master
tLAG
-30 + N ×
tSpcyc
3
*
Slave
6 × tPcyc
-
ns
ns
Data output delay
Master 2.7 V ≤ VCC ≤ 5.5 V tOD
2.4 V ≤ VCC < 2.7 V
-
14
20
25
30
50
60
85
110
-
-
1.8 V ≤ VCC < 2.4 V
-
1.6 V ≤ VCC < 1.8 V
-
Slave
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
-
-
-
-
Data output hold
time
Master
Slave
tOH
0
0
ns
ns
-
Successive
transmission delay
Master
tTD
tSPcyc + 2 ×
tPcyc
8 × tSPcyc
2 × tPcyc
+
Slave
6 × tPcyc
-
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2. Electrical Characteristics
Table 2.34
SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
*1
Parameter
MOSI and MISO
Symbol Min
Dr, tDf
Max
Unit
Test conditions
Output 2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
ns
Figure 2.51 to
Figure 2.56
C = 30 pF
SPI
rise and fall time
15
20
30
1
µs
ns
SSL rise and fall
time
Output 2.7 V ≤ VCC ≤ 5.5 V tSSLr,
10
tSSLf
2.4 V ≤ VCC < 2.7 V
15
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
20
30
1
µs
ns
Slave access time
2.4 V ≤ VCC ≤ 5.5 V tSA
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2 × tPcyc + 100
2 × tPcyc + 140
2 × tPcyc + 180
2 × tPcyc + 100
2 × tPcyc + 140
2 × tPcyc + 180
Figure 2.55 and
Figure 2.56
C = 30 pF
Slave output release time
2.4 V ≤ VCC ≤ 5.5 V tREL
1.8 V ≤ VCC < 2.4 V
ns
1.6 V ≤ VCC < 1.8 V
Note 1. tPcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
RSPCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
RSPCKn
slave select input
VIL
tSPCKWL
VIL
tSPcyc
(n = A or B)
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.50
SPI clock timing
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2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.51
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tHF
MISOn
input
LSB IN
MSB IN
DATA
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.52
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
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2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.53
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.54
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
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RA2A1 Datasheet
2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
(n = A or B)
Figure 2.55
SPI timing (slave, CPHA = 0)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
(n = A or B)
Figure 2.56
SPI timing (slave, CPHA = 1)
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2. Electrical Characteristics
2.3.10
IIC Timing
Table 2.35
IIC timing
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Test
Parameter
Symbol Min*1
Max
Unit conditions
IIC
SCL input cycle time
tSCL
tSCLH
tSCLL
tSr
6 (12) × tIICcyc + 1300
-
ns
ns
ns
ns
ns
ns
Figure 2.57
(Standard mode,
SMBus)
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
3 (6) × tIICcyc + 300
-
3 (6) × tIICcyc + 300
-
-
1000
tSf
-
300
SCL, SDA input spike pulse removal tSP
time
0
1 (4) × tIICcyc
SDA input bus free time
(when wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
-
-
-
-
ns
ns
ns
ns
ns
SDA input bus free time
(when wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
START condition input hold time
(when wakeup function is disabled)
tSTAH
tSTAH
tSTAS
tIICcyc + 300
START condition input hold time
(when wakeup function is enabled)
1 (5) × tIICcyc + tPcyc
300
+
Repeated START condition input
setup time
1000
STOP condition input setup time
Data input setup time
tSTOS
tSDAS
tSDAH
Cb
1000
-
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
tIICcyc + 50
-
Data input hold time
0
-
SCL, SDA capacitive load
SCL input cycle time
-
400
IIC
tSCL
tSCLH
tSCLL
tSr
6 (12) × tIICcyc + 600
-
Figure 2.57
(Fast mode)
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
3 (6) × tIICcyc + 300
-
3 (6) × tIICcyc + 300
-
-
300
tSf
-
300
SCL, SDA input spike pulse removal tSP
time
0
1 (4) × tIICcyc
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
-
-
-
-
ns
ns
ns
ns
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
START condition input hold time
(When wakeup function is disabled)
tSTAH
tSTAH
tSTAS
tIICcyc + 300
START condition input hold time
(When wakeup function is enabled)
1 (5) × tIICcyc + tPcyc
300
+
Repeated START condition input
setup time
300
STOP condition input setup time
Data input setup time
tSTOS
tSDAS
tSDAH
Cb
300
-
ns
ns
ns
pF
tIICcyc + 50
-
Data input hold time
0
-
-
SCL, SDA capacitive load
400
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
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2. Electrical Characteristics
VIH
VIL
SDA0 and SDA1
tBUF
tSCLH
tSTAS
tSTOS
tSTAH
tSP
SCL0 and SCL1
P*1
P*1
S*1
tSf
Sr*1
tSCLL
tSr
tSDAS
tSCL
tSDAH
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.57
I2C bus interface input/output timing
2.3.11
CLKOUT Timing
Table 2.36
CLKOUT timing
Parameter
Symbol Min
Max
Unit
Test conditions
CLKOUT
CLKOUT pin output cycle*1
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
tCcyc
tCH
tCL
tCr
62.5
125
250
15
30
150
15
30
150
-
-
ns
ns
ns
ns
ns
Figure 2.58
-
-
CLKOUT pin high pulse width*2 2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
-
-
1.6 V ≤ VCC < 1.8 V
-
CLKOUT pin low pulse width*2
CLKOUT pin output rise time
CLKOUT pin output fall time
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
-
-
-
12
25
50
12
25
50
-
-
tCf
-
-
-
Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.36 should be satisfied with 45% to
55% of input duty cycle.
Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division
ratio to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
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2. Electrical Characteristics
tCcyc
tCH
tCf
CLKOUT
tCr
tCL
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.58
CLKOUT output timing
2.4
USB Characteristics
2.4.1
USBFS Timing
Table 2.37
USB characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C
Parameter
Symbol
VIH
Min
2.0
-
Max
-
Unit
V
Test conditions
Input
characteristics
Input high level voltage
Input low level voltage
-
VIL
0.8
-
V
-
Differential input sensitivity VDI
0.2
0.8
V
| USB_DP - USB_DM |
-
Differential common mode VCM
range
2.5
V
Output
characteristics
Output high level voltage
Output low level voltage
Cross-over voltage
VOH
VOL
VCRS
tr
2.8
0.0
1.3
4
VCC_USB
0.3
V
IOH = -200 μA
V
IOL = 2 mA
2.0
V
Figure 2.59,
Figure 2.60,
Figure 2.61
Rise time
FS
LS
FS
LS
20
ns
75
4
300
Fall time
tf
20
ns
%
Ω
75
90
80
28
300
Rise/fall time ratio FS
LS
tr/tf
111.11
125
Output resistance
ZDRV
44
(Adjusting the resistance
of external elements is not
required.)
VBUS
VBUS input voltage
VIH
VCC × 0.8
-
V
-
characteristics
VIL
-
VCC × 0.2
24.80
1.575
3.09
175
V
-
Pull-up,
pull-down
Pull-down resistor
Pull-up resistor
RPD
14.25
0.9
1.425
25
kΩ
kΩ
kΩ
μA
μA
μA
V
-
RPUI
During idle state
RPUA
During reception
Battery charging
specification
version 1.2
D+ sink current
IDP_SINK
IDM_SINK
IDP_SRC
VDAT_REF
VDP_SRC
VDM_SRC
-
D- sink current
25
175
-
DCD source current
Data detection voltage
D+ source voltage
D- source voltage
7
13
-
0.25
0.5
0.5
0.4
-
0.7
V
Output current = 250 μA
Output current = 250 μA
0.7
V
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2. Electrical Characteristics
90%
90%
USB_DP,
USB_DM
VCRS
10%
10%
tr
tf
Figure 2.59
USB_DP and USB_DM output timing
Observation
point
USB_DP
50 pF
USB_DM
50 pF
Figure 2.60
Test circuit for Full-Speed (FS) connection
Observation
point
USB_DP
200 pF to
600 pF
3.6 V
1.5 K
USB_DM
200 pF to
600 pF
Observation
point
Figure 2.61
Test circuit for Low-Speed (LS) connection
2.4.2
USB External Supply
Table 2.38
Parameter
USB regulator
Min
Typ
Max
50
Unit
Test conditions
VCC_USB supply current
VCC_USB supply voltage
3.8 V ≤ VCC_USB_LDO < 4.5 V
4.5 V ≤ VCC_USB_LDO ≤ 5.5 V
-
-
-
-
-
mA
mA
V
-
-
-
100
3.6
3.0
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2. Electrical Characteristics
2.5
ADC16 Characteristics
Table 2.39
16-bit A/D conversion, power supply, and input range conditions
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1.5
-
Typ
3.3
Max
Unit
V
Test conditions
High-potential reference voltage
Low-potential reference voltage
Analog input voltage range
AVCC0
-
-
AVSS0
-
V
-
0
VREFH0
V
-
Input common-mode
range
Acm
0
VREFH0/2 VREFH0
V
Differential analog input
Analog input
capacitance*
Cs
Rs
-
-
-
-
-
-
-
-
-
-
4.3
0.7
1.5
2.5
3.8
pF
-
2
1
Analog input resistance*
kΩ
High-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
High-precision channel
1.7 V ≤ AVCC0 < 2.7 V
Normal-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
Normal-precision channel
1.7 V ≤ AVCC0 < 2.7 V
Note 1. These values are based on simulation. They are not production tested.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Figure 2.62 shows the equivalent circuit for analog input.
MCU
Analog input
Rs
ADC16
ANn
Vi
Cin
Cs
Figure 2.62
Table 2.40
Equivalent circuit for analog input
16-bit A/D conversion, timing parameters (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Frequency
ADCLK
1
1
1
1
1
-
-
32
MHz
3.0 V ≤ AVCC0 ≤ 5.5 V,
3.0 V ≤ VREFH0
-
-
-
-
-
24
2.7 V ≤ AVCC0 ≤ 5.5 V,
2.7 V ≤ VREFH0
16
2.4 ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
8
1.8 V ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
4
1.7 V ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
Conversion rate
Fs
1 / (tSPL + 18 / ADCLK)
S/s
-
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2. Electrical Characteristics
Table 2.40
16-bit A/D conversion, timing parameters (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Sampling time*1 Permissible signal tSPL
source impedance
0.25
-
-
μs
High-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
Max = 0.5 kΩ
3
-
-
-
-
-
-
High-precision channel
1.7 V ≤ AVCC0 < 2.7 V
3
Normal-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
10
Normal-precision channel
1.7 V ≤ AVCC0 < 2.7 V
Settling time*1
tSTART
-
-
-
-
-
-
1
μs
2.7 V ≤ AVCC0 ≤ 5.5 V
1.8 V ≤ AVCC0 < 2.7 V
1.7 V ≤ AVCC0 < 1.8 V
3.2
8.9
Note 1. These values are based on simulation. They are not production tested.
Table 2.41
16-bit A/D conversion, linearity parameters
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Symbol
Min
Typ
16
Max
-
Unit
Bit
Test conditions
Resolution
-
-
-
-
-
-
-
-
Integral non-linearity *1
INL
± 4
± 8
± 16
-
LSB
2.7 V ≤ AVCC0 ≤ 5.5 V, 2.7 V ≤ VREFH0
1.7 V ≤ AVCC0 < 2.7 V
Differential non-linearity*1
Offset error*1
DNL
Ofst
Gerr
-1 to +2
LSB
LSB
%
-
± 4
-
-
-
Gain error*1
±0.1
2.7 V ≤ VREFH0
Note:
The characteristics apply when no pin functions other than 16-bit A/D converter input are used. Offset error, full-scale error,
DNL differential non-linearity error, and INL integral non-linearity error do not include quantization errors.
Note 1. These values are based on simulation. They are not production tested.
Table 2.42
16-bit A/D conversion, dynamic parameters (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to VREFH0 and VREFL0.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Signal-to-noise and distortion*2
SINAD
67
81
-
dB
Differential input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
78
-
81
92
-
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V,
ADADC.ADC[2:0] = 101b
61
72
75
75
-
-
Single input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
Single input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
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2. Electrical Characteristics
Table 2.42
16-bit A/D conversion, dynamic parameters (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to VREFH0 and VREFL0.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Effective number of bits*2
ENOB
11
13.2
-
bit
Differential input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
12.7
-
13.2
15
-
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V,
ADADC.ADC[2:0] = 101b
10
12.2
12.2
-
-
Single input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
11.7
Single input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
Total harmonic distortion*1, *2
Common mode rejection ratio*2
THD
-
-
-
-100
-90
-
-
-
dB
dB
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V
Single input, Fin = 1 kHz,
AVCC0 = 3.3 V
CMRR
100
Differential input,
Acm = 0 to VREFH0 at 1 kHz,
AVCC0 = 3.3 V
Note:
The characteristics apply when no pin functions other than 16-bit A/D converter input are used.
Note 1. THD = HD2 + HD3 + HD4 + HD5.
Note 2. These values are based on simulation. They are not production tested.
Table 2.43
16-bit A/D conversion, dynamic parameters (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Signal-to-noise and distortion*1 SINAD
-
78.6
-
dB
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.5 V
-
-
-
-
-
76.6
74.2
12.8
12.4
12.0
-
-
-
-
-
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.0 V
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 1.5 V
Effective number of bits*1
ENOB
bit
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.5 V
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.0 V
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 1.5 V
Note:
The characteristics apply when no pin functions other than 16-bit A/D converter input are used.
Note 1. These values are based on simulation. They are not production tested.
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2. Electrical Characteristics
Table 2.44
16-bit A/D converter channel classification
Classification
Channel
Conditions
High-precision channel
AN000 to AN008
AVCC0 = 1.7 to 5.5 V
Normal-precision channel
Internal reference voltage input channel
Temperature sensor input channel
AN016 to AN023
Internal reference voltage
Temperature sensor output
AVCC0 = 2.0 to 5.5 V
AVCC0 = 2.0 to 5.5 V
Table 2.45
Internal reference voltage for 16-bit ADC (VREFADC) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Parameter
Min
Typ
Max
Unit
Test conditions
Output voltage range
1.41
1.5
1.59
V
VREFAMPCNT.VREFADCG[1:0] = 00b
AVCC0 1.7 V
1.88
2.35
2
2.12
2.65
VREFAMPCNT.VREFADCG[1:0] = 10b
AVCC0 2.2 V
2.5
VREFAMPCNT.VREFADCG[1:0] = 11b
AVCC0 2.7 V
BGR stabilization time*2 (after BGR is enabled)
-
-
-
-
150
μs
μs
VREFAMPCNT.BGREN = 1
VREF AMP stabilization time*2 (after VREFAMP is
enabled)
1500
VREFAMPCNT.VREFADCEN = 1
Detect over current*2
Load capacitance*1
-
20
1
40
mA
-
-
0.75
1.25
μF
Note 1. Connect capacitors as stabilization capacitance between the VREFH0 and VREFL0 pins when VREFADC is used.
Note 2. These values are based on simulation. They are not production tested.
Table 2.46
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = AVCC1 = VREFH0 = 2.0 to 5.5 V*1
Parameter
Min
1.36
5.0
Typ
1.43
-
Max
1.50
-
Unit
V
Test conditions
Internal reference voltage input channel*2
Sampling time*3
-
-
μs
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Note 2. The 16-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 16-bit A/D
converter.
Note 3. This is a parameter for ADC16 when the internal reference voltage is selected for an analog input channel in ADC16.
2.6
SDADC24 Characteristics
Table 2.47
Analog inputs characteristics (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Full-scale range
FSR
-
± 0.8 /
-
V
-
GTOTAL
Analog input in
differential input
mode
Differential
input voltage
range
VID
-0.8 / GTOTAL
-
0.8 / GTOTAL
V
V
V
VID = ANSDnP - ANSDnN, or
AMP0O - AMP1O
(n = 0 to 3), dOFR = 0 mV
Input voltage
range
VI
0.2
-
1.8
VI = ANSDnP, ANSDnN,
AMP0O, or AMP1O
(n = 0 to 3)
Common mode VCOM
Input voltage
range
0.2 + (|VID|
GSET1) / 2
1.0
1.8 - (|VID|
GSET1) / 2
dOFR = 0 mV
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RA2A1 Datasheet
2. Electrical Characteristics
Table 2.47
Analog inputs characteristics (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol Min
VI 0.2
Typ
Max
Unit
Test conditions
Analog Input in
single-ended
input mode
Input voltage
range*1
-
1.8
V
VI = ANSDnP, ANSDnN,
AMP0O, or AMP1O
(n = 0 to 3),
VCOM = 1.0 V,
dOFR = 0 mV,
GSET1 = 1, GSET2 = 1,
OSR = 256
Note 1. The single-ended input mode supports only dOFR = 0 mV, GSET1 = 1, GSET2 = 1 and OSR = 256.
Table 2.48
Programmable gain instrumentation amplifier and sigma-delta A/D converter (1)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol Min
Typ
24
1
Max
Unit
bits
Test conditions
Resolution
RES
Fos
-
-
-
-
-
-
Over sampling Normal A/D
MHz
frequency
conversion
mode
Low-powerA/D
conversion
mode
-
0.125
-
Output data rate
fDATA1
fDATA2
0.48828
-
-
15.625
ksps
sps
Normal A/D conversion
mode
61.03615
1953.125
Low-power A/D
conversion mode
Gain Setting range
1st Gain Setting range
2nd Gain Setting range
Offset adjust bit range
Offset adjust range
Offset adjust step
GTOTAL
GSET1
GSET2
dOFB
1
-
32
-
V/V
V/V
V/V
bits
GTOTAL = GSET1 × GSET2
-
1, 2, 3, 4, 8
-
-
1, 2, 4, 8
-
-
-
5
-
-
dOFR
-164.06 / GSET1
-
-
+164.06 / GSET1 mV
mV
Referred to input
Referred to input
dOFS
350 / 32 / GSET1 -
Table 2.49
Programmable gain instrumentation amplifier and sigma-delta A/D converter (2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at differential input mode, external clock input used, FOS = 1 MHz, dOFR = 0 mV,
unless otherwise specified.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SET1 = 1,
GSET2 = 1
SET1 = 8,
GSET2 = 4
SET1 = 1,
GSET2 = 1
SET1 = 8,
GSET2 = 4
SET1 = 1,
GSET2 = 1
Signal to Noise Ratio*1,*3 SNR
VID = 0 V
83
86
-
dB
G
OSR = 256
OSR = 1024
OSR = 256
OSR = 1024
81
82
79
74
84
85
82
80
-
-
-
-
dB
dB
dB
dB
G
Signal to Noise and
Distortion Ratio*1, *2,*3
fin = 50 Hz
SINAD
G
G
G
OSR = 256,
Single-ended input mode
Note:
The characteristics apply when no pin functions other than 24-bit sigma-delta A/D converter input are used.
Note 1. SNR and SINAD are the ratio to Full-Scale Range (FSR) of analog inputs. These do not include the noise of analog inputs.
Note 2. When VID is equal to ± 0.8 / GTOTAL actually, the digital output may overflow due to Gain Error (EG), Offset
Error (EOS), and so forth. As a result, SINAD is degraded. See Table 33.7 of 24-Bit Sigma-Delta A/D Converter (SDADC24) in
User’s Manual for the relation between analog input and digital output.
Note 3. Not production tested but is guaranteed by the design and characterization.
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2. Electrical Characteristics
SNR vs OSR
(Differential input mode, typical condition)
100
95
90
85
80
75
70
65
60
64
128
256
512
1024
2048
Oversampling Ratio (OSR)
GSET1 = 1, GSET2 = 1
SNR vs. OSR (reference data)
GSET1 = 8, GSET2 = 4
Figure 2.63
SINAD vs OSR
(Differential input mode, typical condition)
95
90
85
80
75
70
65
60
64
128
256
Oversampling Ratio (OSR)
GSET1 = 1, GSET2 = 1
512
1024
2048
GSET1 = 8, GSET2 = 4
Figure 2.64
Table 2.50
SINAD vs. OSR (reference data)
Programmable gain instrumentation amplifier and sigma-delta A/D converter (3) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at the differential input mode, with external clock input used, Fos = 1 MHz,
OSR = 256, and dOFR = 0 mV, unless otherwise specified.
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Gain error*2
(excluding SINC3 frequency
response characteristic)
EG
-0.5
-
0.5
%
After internal calibration,
excluding SBIAS error or VREFI
error,
GSET1 = 1, GSET2 = 1
-3
-
3
Single-ended input mode,
excluding SBIAS error or
VREFI error,
GSET1 = 1, GSET2 = 1
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2. Electrical Characteristics
Table 2.50
Programmable gain instrumentation amplifier and sigma-delta A/D converter (3) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at the differential input mode, with external clock input used, Fos = 1 MHz,
OSR = 256, and dOFR = 0 mV, unless otherwise specified.
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Gain drift*1, *2
dEG
EOS
-
6
22
ppm/°C Excluding SBIAS error or
VREFI error,
GSET1 = 1, GSET2 = 1
Offset error*2
-1
-50
-
-
1
mV
After internal calibration,
GSET1 = 1, GSET2 = 1, referred to
input
50
Single-ended input mode,
including SBIAS error,
GSET1 = 1, GSET2 = 1, referred to
input
Offset drift*1, *2
dEOS
-
-
2
-
6
μV/°C
Referred to input
120
Single-ended input mode,
including SBIAS error,
GSET1 = 1, GSET2 = 1
Integral non-linearity*2
INL
-
-
15
80
-
-
ppm
Input = DC,
of FSR OSR = 2048
Common mode
Rejection ratio*2
CMRR
dB
VCOM = 1.0 ± 0.8 V,
fin = 50 Hz,
GSET1 = 1, GSET2 = 1
Power supply
Rejection ratio*2
PSRR
-
70
-
dB
AVCC1 = 5.0 V + 0.1 Vpp_ripple
fin = 50 Hz,
,
GSET1 = 1, GSET2 = 1, excluding
SBIAS error or VREFI error
Input absolute current*2
Input offset current*2
Input impedance*2
IIN
-
2
-
nA
VI = 1 V
IINOFR
ZIN
-
1
-
nA
VID = 0 V, VCOM = 1 V
VID = 1 V, VCOM = 1 V
-
500
-
-
Mohm
%
Offset adjust gain error*2
dOFGE
-5
5
Including SBIAS error,
dOFR ≠ 0 mV
Offset adjust
integral non-linearity*2
dOFINL
-0.5
-
0.5
LSB
dOFR ≠ 0 mV
Note:
The characteristics apply when no pin functions other than 24-bit sigma-delta A/D converter input are used.
Note 1. Gain drift is calculated by (Max (EG (T (-40°C) to T (125°C))) - Min (EG (T (-40°C) to T (125°C)))) / (125°C - (-40°C))
Offset drift is calculated by (Max (EOS (T (-40°C) to T (125°C))) - Min (EOS (T (-40°C) to T (125°C)))) / (125°C - (-40°C)).
Note 2. Not production tested but is guaranteed by the design and characterization.
Table 2.51
2.1 V LDO linear regulator for ADC (ADREG) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Connect the ADREG pin to a AVSS1 pin by a 0.47 μF (-50% to +20%) capacitor.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
ADREG output voltage
VADREG
-
2.1
-
V
-
Table 2.52
ADC external reference voltage (VREFI) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
VREFI
VRSTEP
VRA
Min
0.8
-
Typ
Max
2.4
-
Unit
V
Test conditions
External reference voltage range*1
External reference voltage step
External reference voltage accuracy
-
SDADCSTC1.VREFSEL = 1
SDADCSTC1.VREFSEL = 1
SDADCSTC1.VREFSEL = 1
0.2
-
V
-3
3
%
Note 1. Select the reference voltage input value with STC1.VSBIAS[3:0].
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2. Electrical Characteristics
Table 2.53
Sensor bias (SBIAS) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Connect the SBIAS/VREFI pin to a AVSS1 pin by a 0.22 μF (-20% to +20%)
Parameter
Symbol
SBIAS
SVSTEP
SVA
Min
Typ
Max
2.2
-
Unit
V
Test conditions
Output voltage range*2
Output voltage step
Output voltage accuracy*1
Output current*1
0.8
-
-
-
0.2
-
V
-
-3
-
3
%
SIOUT = 1 mA
-
SIOUT
SISHORT
SLR
-
10
65
15
20
-
mA
mA
mV
mV
dB
Short current*1
-
35
-
SBIAS = 0 V
Load regulation*1
-
1 mA ≤ SIOUT ≤ 5 mA
1 mA ≤ SIOUT ≤ 10 mA
-
-
Power supply rejection ratio*1
Transition time of one step*1,*3
SPSRR
STTS
-
50
AVCC1 = 5.0 V + 0.1 Vpp_ripple
f = 100 Hz, SIOUT = 2.5 mA
,
-
-
80
μs
SBIAS < SVA ± 3%
1 mA ≤ SIOUT ≤ SIOUT_MAX
Note 1. Not production tested but is guaranteed by the design and characterization.
Note 2. Select the reference voltage output value for the sensor with STC1.VSBIAS[3:0].
Note 3. The load current of more than 1 mA is required because the output stage of SBIAS is Pch open drain. When the original load
current is small, additional external load resistance is required.
2.7
DAC12 Characteristics
Table 2.54
12-bit D/A conversion characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VREFH = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL = 0 V
Parameter
Min Typ Max
Unit Test conditions
Resolution
-
-
-
-
-
-
-
-
12
bit
μs
μs
μs
-
-
-
Charge pump stabilization time*1
SW stabilization time*1
Conversion time*1
100
50
DAC Ref. = AVCC or VREFH 2.7 V
1.0
Cload = 38 pF, @ 1 LSB step
Cload = 8 pF, @ full range
DAC Ref. = AVCC or VREFH < 2.7 V
-
-
-
-
-
-
-
2
-
-
-
1.2
1.0
± 12
±1.0
±2.0
±7.0
-
-
-
Wake-up time*1
-
μs
Absolute accuracy
-
LSB 2-MΩ resistive load
DNL differential non-linearity
error
DAC Ref. = AVCC or VREFH 2.7 V
-
LSB
-
-
-
-
-
-
-
DAC Ref. = AVCC or VREFH < 2.7 V
-
INL integral non-linearity error
RO output resistance
Load resistance
-
LSB
kΩ
3.5
2
38
8
-
MΩ
pF
Load capacitance
1 LSB step
Full range
-
-
Note 1. These values are based on simulation. They are not production tested.
2.8
DAC8 Characteristics
Table 2.55
8-bit D/A conversion characteristics (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Min
Typ
Max
8
Unit
Test conditions
Resolution
-
-
-
-
bit
-
-
Charge pump stabilization time*1
100
μs
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2. Electrical Characteristics
Table 2.55
8-bit D/A conversion characteristics (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Min
Typ
Max
50
Unit
μs
Test conditions
Switch stabilization time*1
Conversion time*1
-
-
-
-
-
-
-
-
-
-
AVCC0 = 2.7 to 5.5 V
AVCC0 = 1.7 to 2.7 V
AVCC0 = 2.7 to 5.5 V
AVCC0 = 1.7 to 2.7 V
AVCC0 = 2.7 to 5.5 V
AVCC0 = 1.7 to 2.7 V
-
3.0
μs
35-pF capacitive load
-
6.0
μs
Absolute accuracy
-
± 3.0
± 3.5
± 2.0
± 2.5
-
LSB
2-MΩ resistive load
-
-
LSB
4-MΩ resistive load
-
RO output resistance
7.4
kΩ
-
Note 1. These values are based on simulation. They are not production tested.
2.9
TSN Characteristics
Table 2.56
TSN characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.0 to 5.5 V
Parameter
Symbol
Min
Typ
± 1.5
± 2.0
-3.65
1.05
-
Max
Unit
°C
Test conditions
2.4 V or above
Below 2.4 V
Relative accuracy
-
-
-
-
-
°C
Temperature slope
-
-
-
mV/°C
V
-
Output voltage (at 25°C)
Temperature sensor start time
Sampling time
-
-
-
VCC = 3.3 V
-
tSTART
-
-
5
-
μs
5
-
μs
2.10 OSC Stop Detect Characteristics
Table 2.57
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
ms
Test conditions
Detection time
tdr
-
-
1
Figure 2.65
Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 2.65
Oscillation stop detection timing
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2. Electrical Characteristics
2.11 POR and LVD Characteristics
Table 2.58
Parameter
Power-on reset circuit and voltage detection circuit characteristics (1)
Symbol
Min
Typ
Max
Unit
Test Conditions
Voltage detection
level*1
Power-on reset (POR)
VPOR
1.27
1.42
1.57
V
Figure 2.66,
Figure 2.67
Voltage detection circuit (LVD0)*2
Vdet0_0
Vdet0_1
Vdet0_2
Vdet0_3
Vdet0_4
Vdet1_0
Vdet1_1
Vdet1_2
Vdet1_3
Vdet1_4
Vdet1_5
Vdet1_6
Vdet1_7
Vdet1_8
Vdet1_9
Vdet1_A
Vdet1_B
Vdet1_C
Vdet1_D
Vdet1_E
Vdet1_F
Vdet2_0
Vdet2_1
Vdet2_2
Vdet2_3
3.68
2.68
2.38
1.78
1.60
4.13
3.98
3.86
3.68
2.98
2.89
2.79
2.68
2.58
2.48
2.38
2.10
1.84
1.74
1.63
1.60
4.11
3.97
3.83
3.64
3.85
2.85
2.53
1.90
1.69
4.29
4.16
4.03
3.86
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.20
1.96
1.86
1.75
1.65
4.31
4.17
4.03
3.84
4.00
2.96
2.64
2.02
1.82
4.45
4.30
4.18
4.00
3.22
3.11
3.01
2.90
2.78
2.68
2.58
2.30
2.05
1.95
1.84
1.73
4.48
4.34
4.20
4.01
V
Figure 2.68
At falling edge
VCC
Voltage detection circuit (LVD1)*3
V
Figure 2.69
At falling edge
VCC
Voltage detection circuit (LVD2)*4
V
Figure 2.70
At falling edge
VCC
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage
detection.
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
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2. Electrical Characteristics
Table 2.59
Parameter
Power-on reset circuit and voltage detection circuit characteristics (2)
Symbol
Min
Typ
Max
Unit
Test Conditions
Wait time after power-on
reset cancellation
LVD0: enable
LVD0: disable
LVD0: enable*1
LVD0: disable*2
tPOR
-
1.7
-
ms
-
tPOR
-
-
-
1.3
0.6
0.2
-
-
-
ms
ms
ms
-
Wait time after voltage
monitor 0,1,2 reset
cancellation
tLVD0,1,2
tLVD1,2
-
-
Response delay*3
tdet
-
-
-
350
-
μs
μs
Figure 2.66, Figure 2.67
Minimum VCC down time
tVOFF
450
Figure 2.66,
VCC = 1.0 V or above
Power-on reset enable time
tW (POR)
Td (E-A)
1
-
-
-
-
ms
Figure 2.67,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
300
μs
Figure 2.69,
Figure 2.70
Hysteresis width (POR)
VPORH
VLVH
-
-
-
-
-
-
-
110
60
-
-
-
-
-
-
-
mV
mV
-
Hysteresis width (LVD0, LVD1 and LVD2)
LVD0 selected
100
60
Vdet1_0 to Vdet1_2 selected
Vdet1_3 to Vdet1_9 selected
50
Vdet1_A to Vdet1_B selected
40
Vdet1_C to Vdet1_F selected
LVD2 selected
60
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR
,
Vdet0, Vdet1, and Vdet2 for the POR/LVD.
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
tdet tPOR
Figure 2.66
Voltage detection reset timing
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2. Electrical Characteristics
VPOR
VCC
1.0 V
tw(POR)
*1
Internal reset signal
(active-low)
tdet tPOR
is the time required for a power-on reset to be enabled while the external power VCC is
Note 1. t
w(POR)
being held below the valid voltage (1.0 V).
When VCC turns on, maintain t
for 1.0 ms or more.
w(POR)
Figure 2.67
Power-on reset timing
tVOFF
VLVH
VCC
Vdet0
Internal reset signal
(active-low)
tdet
tdet
tLVD0
Figure 2.68
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tLVD1
tdet
When LVD1CR0.RN = 1
tLVD1
Figure 2.69
Voltage detection circuit timing (Vdet1)
tVOFF
VLVH
VCC
Vdet2
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.70
Voltage detection circuit timing (Vdet2)
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2. Electrical Characteristics
2.12 CTSU Characteristics
Table 2.60
CTSU characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
11
Unit
nF
Test conditions
External capacitance connected to TSCAP pin Ctscap
9
-
10
-
-
-
TS pin capacitive load
Cbase
50
pF
Permissible output high current
ΣIOH
-
-
-24
mA
When the mutual capacitance
method is applied and TS07 to TS14
are not used for transmit channel
-
-
-14
When the mutual capacitance
method is applied and TS07 to TS14
are used for transmit channel
2.13 Comparator Characteristics
Table 2.61
ACMPHS characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
VIOCMP
VICPM
Vref
Min
-
Typ
± 5
-
Max
Unit
Test conditions
Input offset voltage
Input voltage range
Internal reference voltage input*3
Input signal cycle
± 40
mV
V
-
0
AVCC0
-
1.36
10
-
1.43
-
1.50
V
AVCC0 ≥ 2.0 V
tPCMP
Td
-
μs
ns
ns
-
Output delay time
50
-
100
-
Input amplitude ± 100 mV
Input amplitude ± 100 mV
Stabilization wait time during input channel
switching*1
TWAIT
300
Operation stabilization wait time*2
Tcmp
1
3
-
-
-
-
μs
μs
3.3 V ≤ AVCC0 ≤ 5.5 V
2.7 V ≤ AVCC0 3.3 V
Note 1. Period from when the comparator input channel is switched until the switched result reflects in its output.
Note 2. Period from when comparator operation is enabled (CPMCTL.HCMPON = 1) until the comparator satisfies the DC/AC
characteristics.
Note 3. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Table 2.62
ACMPLP characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol Min
Typ
Max
Unit Test conditions
Input voltage range
IVREF0
VREF
0
-
VCC - 1.4*1
VCC - 1.4
VCC
V
V
-
IVREF1 (Standard mode)
IVREF1 (Window mode)
IVCMP0, IVCMP1
0
-
1.4*1
-
V
VI
-
0
-
VCC
V
Internal reference voltage*2
1.36
-
1.43
-
1.50
V
VCC ≥ 2.0 V
Output delay Comparator high-speed mode
Td
1.2
μs
VCC = 3.0 V
(Standard mode)
Slew rate of input
signal > 50 mV/μs
Comparator high-speed mode
(Window mode)
-
-
-
-
2.0
5.0
μs
μs
Comparator low-speed mode
(Standard mode)
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2. Electrical Characteristics
Table 2.62
ACMPLP characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol Min
Typ
Max
Unit Test conditions
Offset voltage
Comparator high-speed mode
(Standard mode)
-
-
-
50
mV
mV
mV
μs
-
Comparator high-speed mode
(Window mode)
-
-
-
-
60
40
-
Comparator low-speed mode
(Standard mode)
-
Operation stabilization wait time
Tcmp
100
-
Note 1. In window mode, be sure to satisfy the following condition: VIVREF1 - VIVREF0 0.2 V.
Note 2. The internal reference voltage cannot be selected for input channels when VCC < 2.0 V.
2.14 OPAMP Characteristics
Table 2.63
OPAMP characteristics (1 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Conditions
Min
1.7
2.1
2.4
-
Typ
Max
5.5
Unit
V
Supply voltage range
AVCC0
Low power mode
Middle-speed mode
High-speed mode
-
-
-
-
-
-
-
5.5
V
5.5
V
Charge pump stabilization time*1
SW stabilization time*1
Input voltage range
-
100
50
μs
μs
V
-
-
-
Vicm1
Vicm2
Vicm3
Volh1
Low power mode
Middle-speed mode
High-speed mode
AVSS0
AVCC0
Output voltage range
Low power mode,
Ilode = 100 μA
AVSS0
-
-
AVCC0
V
Volh2
Middle-speed mode,
Iload = 100 μA
Volh3
High-speed mode,
Iload = 100 μA
Input offset trimming range*1
Voffadj2l
Middle-speed mode,
Vin = 0.1 V,
-3
3
mV
Tj = 25°C
Voffadj2h
Voffadj3l
Voffadj3h
Middle-speed mode,
Vin = AVCC0 - 0.1 V,
Tj = 25°C
High-speed mode,
Vin = 0.1 V,
Tj = 25°C
High-speed mode,
Vin = AVCC0 - 0.1 V,
Tj = 25°C
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 85 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.63
OPAMP characteristics (2 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input offset*1
Vioff1a
Low power mode,
-5.0
-
5.0
mV
Vin < AVCC0 - 1.0 V
Vioff1b
Vioff2a
Vioff2b
Vioff3a
Vioff3b
Drift1a
Drift1b
Drift2a
Drift2b
Drift3a
Drift3b
Low power mode,
Vin ≥ AVCC0 - 1.0 V
-8.0
-3.0
-3.0
-2.5
-2.5
-70
-70
-30
-30
-30
-30
-
-
-
-
-
-
-
-
-
-
-
8.0
3.0
3.0
2.5
2.5
70
Middle-speed mode,
Vin < AVCC0 - 1.2 V
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
High-speed mode,
Vin < AVCC0 - 1.2 V
High-speed mode,
Vin ≥ AVCC0 - 1.2 V
Offset drift*1
Low power mode,
Vin < AVCC0 - 1.0 V
μV/°C
Low power mode,
Vin ≥ AVCC0 - 1.0 V
70
Middle-speed mode,
Vin < AVCC0 - 1.2 V
30
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
30
High-speed mode,
Vin < AVCC0 - 1.2 V
30
High-speed mode,
30
Vin ≥ AVCC0 - 1.2 V
Open gain*1
Av1
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
70
70
60
-
130
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
Av2
120
Av3
130
Gain bandwidth product*1
Phase margin*1
GBW1
GBW2
GBW3
PM1
PM2
PM3
GM1
GM2
GM3
Vind11
90
kHz
MHz
MHz
deg
-
2
-
4.8
35
35
35
10
10
10
-
-
-
-
Gain margin*1
-
dB
-
-
Input noise density*1
Low power mode,
f = 10 Hz
860
nV/√Hz
Vind12
Vind21
Vind22
Vind31
Vind32
Low power mode,
f = 1 kHz
-
-
-
-
-
260
50
-
-
-
-
-
Middle-speed mode,
f = 1 kHz
Middle-speed mode,
f = 100 kHz
30
High-speed mode,
f = 1 kHz
40
High-speed mode,
f = 100 kHz
20
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 86 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.63
OPAMP characteristics (3 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
PSRR1
PSRR2
PSRR3
CMRR1
CMRR2
CMRR3
Tset1
Conditions
Min
Typ
90
Max
Unit
Power supply rejection ratio*1
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
Low power mode
Middle-speed mode
High-speed mode
-
-
dB
-
90
-
-
90
-
Common mode rejection ratio*1
Settling time*1
-
90
-
dB
-
90
-
-
90
-
-
70
200
μS
Tset2
-
2.8
1.2
0.05
1.3
3.0
80
8
Tset3
-
3.2
Slew rate*1
SR1
0.02
0.8
1.8
-
-
V/μS
μS
SR2
-
SR3
-
Turn on time*1
Tturn1
Low power mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
220
Tturn2
Tturn3
Vioffst2
Middle-speed mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
-
-
3
10
4
High-speed mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
1.3
Input offset trimming step*1
Middle-speed mode,
Vin < AVCC0 - 1.2 V
0.3
0.459
0.58
0.56
0.65
0.61
mV/code
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
0.24
0.35
0.28
-
Vioffst3
High-speed mode,
Vin < AVCC0 - 1.2 V
0.52
-
High-speed mode,
Vin ≥ AVCC0 - 1.2 V
Wait time after trimming*1
Tturn_tm2
Tturn_tm3
IIoad
Middle-speed mode
-
-
-
-
-
-
-
-
1.5
1
μS
High-speed mode
Load current
-
-
100
20
μA
Load capacitance
CL
pF
Note 1. These values are based on simulation. They are not production tested.
2.15 Flash Memory Characteristics
2.15.1
Code Flash Memory Characteristics
Table 2.64
Code flash characteristics (1)
Parameter
Symbol
NPEC
Min
Typ
Max
Unit
Conditions
Reprogramming/erasure cycle*1
1000
20*2,
-
-
-
-
Times
Year
-
3
Data hold time
After 1000 times NPEC
tDRP
*
Ta = +85°C
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),
erasing can be performed n times for each block. For instance, when 4-byte programming is performed 256 times for different
addresses in 1-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled (overwriting is prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. This result is obtained from reliability testing.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 87 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.65
Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
FCLK = 1 MHz
FCLK = 32 MHz
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
506
222
16.6
140
10.7
447
447
447
-
Unit
μs
Programming time
Erasure time
8-byte
2-KB
tP8
-
116
998
287
56.8
1899
22.5
585
585
585
-
-
54
tE2K
tBC8
tBC2K
tSED
tSAS
tAWS
tOSIS
-
9.03
-
5.67
ms
μs
Blank check time
8-byte
2-KB
-
-
-
-
-
-
-
-
μs
Erase suspended time
-
-
-
-
μs
Startup area switching setting time
Access window time
-
21.9
21.9
21.9
-
-
12.1
12.1
12.1
-
ms
ms
ms
μs
-
-
OCD/serial programmer ID setting time
-
-
Flash memory mode transition wait time 1 tDIS
Flash memory mode transition wait time 2 tMS
2
5
2
5
-
-
-
-
μs
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note:
Table 2.66
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 1 MHz
FCLK = 8 MHz
Parameter
Symbol Min
Typ
Max
1411
289
87.7
1930
32.7
592
592
592
-
Min
Typ
Max
Unit
μs
Programming time
Erasure time
8-byte
2-KB
tP8
-
157
-
101
966
228
52.5
414
21.6
465
465
465
-
tE2K
tBC8
tBC2K
tSED
tSAS
tAWS
tOSIS
-
9.10
-
6.10
ms
μs
Blank check time
8-byte
2-KB
-
-
-
-
-
-
-
-
μs
Erase suspended time
-
-
-
-
μs
Startup area switching setting time
Access window time
-
22.8
22.8
22.8
-
-
14.2
14.2
14.2
-
ms
ms
ms
μs
-
-
OCD/serial programmer ID setting time
-
-
Flash memory mode transition wait time 1 tDIS
Flash memory mode transition wait time 2 tMS
2
2
720
-
-
720
-
-
ns
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note:
2.15.2
Data Flash Memory Characteristics
Table 2.67
Parameter
Data flash characteristics (1)
Symbol
NDPEC
tDDRP
Min
Typ
Max
Unit
Times
Year
Year
Year
Conditions
-
Reprogramming/erasure cycle*1
Data hold time After 10000 times of NDPEC
100000
1000000
-
-
-
-
-
20*2,
*
Ta = +85°C
3
3
After 100000 times of NDPEC
After 1000000 times of NDPEC
5*2,
-
*
-
1*2,
*
Ta = +25°C
3
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 88 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different
addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. These results are obtained from reliability testing.
Table 2.68
Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
FCLK = 4 MHz
FCLK = 32 MHz
Parameter
Symbol
tDP1
Min
Typ
Max
Min
Typ
Max
Unit
μs
Programming time
Erasure time
1-byte
1-KB
-
52.4
463
286
24.3
1872
13.0
-
-
42.1
387
237
16.6
512
10.7
-
tDE1K
-
8.98
-
6.42
ms
μs
Blank check time
1-byte
1-KB
tDBC1
-
-
-
-
-
-
-
-
-
-
tDBC1K
tDSED
tDSTOP
-
-
μs
Suspended time during erasing
Data flash STOP recovery time
-
-
μs
5
5
μs
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note:
Table 2.69
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 4 MHz
Typ Max
FCLK = 8 MHz
Parameter
Symbol
tDP1
Min
Min
Typ
Max
Unit
μs
Programming time
Erasure time
1-byte
1-KB
-
94.7
886
299
56.2
2.17
23.0
-
-
89.3
849
273
52.5
1.51
21.7
-
tDE1K
-
9.59
-
8.29
ms
μs
Blank check time
1-byte
1-KB
tDBC1
-
-
-
-
-
-
-
-
-
-
tDBC1K
tDSED
tDSTOP
-
-
ms
μs
Suspended time during erasing
Data flash STOP recovery time
-
-
720
720
ns
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Note:
2.15.3
Serial Wire Debug (SWD)
Table 2.70
SWD characteristics (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Parameter
Symbol
tSWCKcyc
tSWCKH
tSWCKL
tSWCKr
Min
80
35
35
-
Typ
Max
Unit
ns
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
-
-
-
-
-
-
Figure 2.71
-
ns
-
ns
5
5
ns
tSWCKf
-
ns
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 89 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Table 2.70
SWD characteristics (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Parameter
Symbol
tSWDS
tSWDH
tSWDD
Min
16
16
2
Typ
Max
Unit
ns
Test conditions
SWDIO setup time
SWDIO hold time
SWDIO data delay time
-
-
-
-
Figure 2.72
-
ns
70
ns
Table 2.71
SWD characteristics (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 2.4 V
Parameter
Symbol
tSWCKcyc
tSWCKH
tSWCKL
tSWCKr
tSWCKf
tSWDS
Min
250
120
120
-
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
SWDIO setup time
-
-
-
-
-
-
-
-
-
Figure 2.71
-
-
5
-
5
50
50
2
-
Figure 2.72
SWDIO hold time
tSWDH
-
SWDIO data delay time
tSWDD
150
tSWCKcyc
tSWCKH
tSWCKf
SWCLK
tSWCKr
tSWCKL
Figure 2.71
SWD SWCLK timing
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
tSWDD
tSWDD
SWDIO
(Output)
SWDIO
(Output)
SWDIO
(Output)
Figure 2.72
SWD input/output timing
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 90 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
0.3
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
Unit: mm
HD
*1
D
48
33
49
32
64
17
1
16
NOTE 4
Index area
NOTE 3
NOTE)
F
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
y
S
*3
Dimensions in millimeters
Min Nom Max
Reference
Symbol
b
p
e
M
D
E
A2
HD
HE
A
A1
bp
c
9.9
9.9
10.0 10.1
10.0 10.1
1.4
11.8
11.8
12.0 12.2
12.0 12.2
1.7
0.15
0.05
0.15
0.09
0q
0.20 0.27
3.5q
0.5
0.20
8q
Lp
L1
T
e
x
y
Lp
L1
Detail F
0.08
0.08
0.75
0.45
0.6
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.1
LQFP 64-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 91 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
A2
HD
HE
A
6.9 7.0 7.1
6.9 7.0 7.1
1.4
Terminal cross section
32
9
8.8 9.0 9.2
8.8 9.0 9.2
1.7
1
8
ZD
Index mark
A1
bp
b1
c
0.1 0.2
0
0.32 0.37 0.42
0.35
F
0.09
0.20
0.145
0.125
S
c1
L
L1
0°
8°
e
0.8
Detail F
y
S
x
0.20
0.10
*3
bp
x
e
y
ZD
ZE
L
0.7
0.7
0.3 0.5 0.7
1.0
L1
Figure 1.2
LQFP 32-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 92 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
P-LFBGA36-5x5-0.80
RENESAS Code
PLBG0036GA-A
Previous Code
36FHE
MASS[Typ.]
0.1g
b
S
AB
ZD
e
D
A
w
S A
A1
A
F
E
D
C
B
B
A
1
2
3
4
5
6
x4
Dimension in Millimeters
Reference
Symbol
v
Index mark
Min Nom Max
5.0
5.0
Index mark
(Laser mark)
S
D
E
v
0.15
0.20
1.4
w
A
A1
e
0.35
0.8
0.3
0.4
b
0.4 0.45
0.5
0.08
0.10
x
y
ZD
ZE
0.5
0.5
Figure 1.3
BGA 36-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 93 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
48PJN-A
P48K8-50-5B4-6
P-HWQFN48-7x7-0.50
PWQN0048KB-A
0.13
D
25
36
24
37
DETAIL OF A PART
E
A
A1
c2
13
48
12
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
7.00
7.00
Max
7.05
7.05
0.80
Min
6.95
6.95
D
E
D2
A
EXPOSED DIE PAD
Lp
A
12
1
A1
b
0.00
0.18
13
0.30
0.25
0.50
0.40
48
e
0.30
0.15
0.50
0.05
0.05
Lp
x
B
E2
y
ZD
ZE
c2
0.75
0.75
0.20
5.50
5.50
ZE
37
24
0.25
36
25
D2
E2
ZD
e
M
b
x
S A B
2013 Renesas Electronics Corporation. All rights reserved.
Figure 1.4
QFN 48-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 94 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
P-HWQFN40-6x6-0.50
PWQN0040KC-A
P40K8-50-4B4-5
0.09
D
21
30
20
31
DETAIL OF A PART
E
A
40
11
A1
c2
10
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
6.00
6.00
Max
6.05
6.05
0.80
Min
5.95
5.95
D
E
D2
A
Lp
EXPOSED DIE PAD
A
1
10
A1
b
0.00
0.18
0.30
11
0.25
0.50
0.40
40
e
0.30
0.15
0.50
0.05
0.05
Lp
x
B
E2
y
ZD
ZE
c2
0.75
0.75
0.20
4.50
4.50
ZE
20
31
0.25
30
21
D2
E2
ZD
e
M
b
x
S
A B
Figure 1.5
QFN 40-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 95 of 100
Revision History
RA2A1 Group Datasheet
Rev.
1.00
1.10
Date
Summary
Oct 8, 2019
First release
Mar 16, 2020 Updated for 1.10
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RA2A1 Microcontroller Group Datasheet
Publication Date:
Rev.1.10
Mar 16, 2020
Published by:
Renesas Electronics Corporation
Address List
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-
off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between V (Max.) and V (Min.) due to noise, for example, the device may malfunction. Take care to
IL
IH
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between V (Max.) and V (Min.).
IL
IH
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the given product.
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