R8C-20 [RENESAS]
MCU; MCU
| 型号： | R8C-20 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | MCU |
| 文件： | 总45页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R8C/20 Group, R8C/21 Group
RENESAS MCU
REJ03B0120-0200
Rev.2.00
Aug 27, 2008
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged
in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of
instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. This
Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group.
The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functions
are the same.
1.1
Applications
Automotive, etc.
Rev.2.00 Aug 27, 2008 Page 1 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and
Specifications for R8C/21 Group.
Table 1.1
Functions and Specifications for R8C/20 Group
Item
Specification
CPU
Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode
Address space
Memory capacity
Ports
Single-chip
1 Mbyte
Refer to Table 1.3 Product Information for R8C/20 Group
I/O ports: 41 pins, Input port: 3 pins
Timer RA: 8 bits x 1 channel,
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
1 channel (UART0)
Peripheral
Function
Timers
Serial interface
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface 1 channel
I2C bus interface(2), Clock synchronous serial I/O with chip
select
LIN module
Hardware LIN: 1 channel
(timer RA, UART0)
A/D converter
Watchdog timer
10-bit A/D converter: 1 circuit, 12 channels
15 bits x 1 channel (with prescaler)
Reset start selectable
Interrupt
Internal: 11 sources, External: 5 sources, Software: 4 sources,
Priority level: 7 levels
Clock generation circuits
2 circuits
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Oscillation stop detection
function
Stop detection of XIN clock oscillation
Voltage detection circuit
Power-on reset circuit include
Supply voltage
On-chip
On-chip
Electric
Characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
chip oscillator stopping)
Current consumption
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
endurance
100 times
Operating Ambient Temperature
-40 to 85°C
-40 to 125°C (option(1)
)
Package
NOTES:
48-pin mold-plastic LQFP
1. When using options, be sure to inquire about the specification.
2
2. I C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Rev.2.00 Aug 27, 2008 Page 2 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
Table 1.2
Functions and Specifications for R8C/21 Group
Item
Specification
CPU
Number of fundamental instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode
Address space
Memory capacity
Ports
Single-chip
1 Mbyte
Refer to Table 1.4 Product Information for R8C/21 Group
I/O ports: 41 pins, Input port: 3 pins
Timer RA: 8 bits x 1 channel,
Peripheral
Function
Timers
Timer RB: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits x 2 channel
(Circuits of input capture and output compare)
Timer RE: With compare match function
1 channel (UART0)
Serial interface
Clock synchronous I/O, UART
1 channel (UART1)
UART
Clock synchronous serial interface
LIN module
1 channel
I2C bus interface(2), Clock synchronous serial I/O with chip
select
Hardware LIN: 1 channel
(Timer RA, UART0)
A/D converter
Watchdog timer
10-bit A/D converter: 1 circuit, 12 channels
15 bits x 1 channel (with prescaler)
Reset start selectable
Interrupts
Internal: 11 sources, External: 5 sources, Software: 4 sources,
Priority level: 7 levels
Clock generation circuits
2 circuits
XIN clock generation circuit (with on-chip feedback resistor)
On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency adjustment
function.
Oscillation stop detection
function
Stop detection of XIN clock oscillation
Voltage detection circuit
Power-on reset circuit include
Supply voltage
On-chip
On-chip
Electric
Characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version)
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on-
chip oscillator stopping)
Current consumption
Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip
oscillator stopping)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
endurance
10,000 times (data flash)
1,000 times (program ROM)
-40 to 85°C
Operating Ambient Temperature
-40 to 125°C (option(1)
)
Package
NOTES:
48-pin mold-plastic LQFP
1. When using options, be sure to inquire about the specification.
2
2. I C bus is a registered trademark of Koninklijke Philips Electronics N.V.
Rev.2.00 Aug 27, 2008 Page 3 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
3
3
8
6
8
Port P0
Port P1
I/O port
Port P2
Port P3
Port P4
Port P6
System clock
generation circuit
A/D converter
(10 bits × 12 channels)
Timer
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Timer RA (8 bits)
Timer RB (8 bits)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
Timer RD (16bits×2 channels)
Timer RE (8 bits)
UART
(8 bits × 1 channel)
I2C bus interface or
clock synchronous serial I/O
with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
Watchdog timer
(15 bits)
Memory
R8C CPU core
ROM(1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM(2)
A0
A1
FB
Multiplier
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.1
Block Diagram
Rev.2.00 Aug 27, 2008 Page 4 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
1.4
Product Information
Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group.
Table 1.3
Product Information for R8C/20 Group
ROM Capacity RAM Capacity Package Type
Current of Aug. 2008
Type No.
Remarks
R5F21206JFP
R5F21207JFP
R5F21208JFP
R5F2120AJFP
R5F2120CJFP
R5F21206KFP
R5F21207KFP
R5F21208KFP
R5F2120AKFP
R5F2120CKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
PLQP0048KB-A J version
PLQP0048KB-A
Flash memory
version
PLQP0048KB-A
PLQP0048KB-A
(1)
(1)
PLQP0048KB-A
PLQP0048KB-A K version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
NOTE:
1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger.
Refer to 23. Notes on Emulator Debugger of Hardware Manual.
Part number R 5 F 21 20 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/20 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2
Type Number, Memory Size, and Package of R8C/20 Group
Rev.2.00 Aug 27, 2008 Page 5 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
Table 1.4
Product Information for R8C/21 Group
Current of Aug. 2008
ROM Capacity
Type No.
RAM Capacity Package Type
Remarks
Program ROM Data Flash
R5F21216JFP
R5F21217JFP
R5F21218JFP
R5F2121AJFP
R5F2121CJFP
R5F21216KFP
R5F21217KFP
R5F21218KFP
R5F2121AKFP
R5F2121CKFP
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
1 Kbyte X 2 2 Kbytes
1 Kbyte X 2 2.5 Kbytes
PLQP0048KB-A J version Flash
memory
version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A K version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
1 Kbyte X 2 3 Kbytes
1 Kbyte X 2 5 Kbytes
1 Kbyte X 2 6 Kbytes
1 Kbyte X 2 2 Kbytes
1 Kbyte X 2 2.5 Kbytes
1 Kbyte X 2 3 Kbytes
1 Kbyte X 2 5 Kbytes
1 Kbyte X 2 6 Kbytes
(1)
(1)
NOTE:
1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger.
Refer to 23. Notes on Emulator Debugger of Hardware Manual.
Part number R 5 F 21 21 6 J XXX FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin-pitch, 7 mm square body)
ROM number
Classification
J: Operating ambient temperature -40°C to 85°C (J version)
K: Operating ambient temperature -40°C to 125°C (K version)
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/21 Group
R8C/2x Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.3
Type Number, Memory Size, and Package of R8C/21 Group
Rev.2.00 Aug 27, 2008 Page 6 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
Pin assignments (top view)
P0_6/AN1
P0_5/AN2
P0_4/AN3
P4_2/VREF
P6_0/TREO
P6_2
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P1_3/KI3/AN11
P1_4/TXD0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0
P1_7/TRAIO/INT1
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
R8C/20 Group,
R8C/21 Group
P6_1
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
P3_7/SSO
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
Package: PLQP0048KB-A
0.5 mm pin pitch, 7 mm square body
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
Pin Assignments (Top View)
Rev.2.00 Aug 27, 2008 Page 7 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
1.6
Pin Functions
Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number.
Table 1.5
Type
Pin Functions
Symbol
I/O Type
I
Description
Power Supply Input
VCC
VSS
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the
VSS pin.
Analog Power Supply
Input
AVCC, AVSS
I
Applies the power supply for the A/D converter. Connect
a capacitor between AVCC and AVSS.
Reset Input
RESET
MODE
XIN
I
I
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
MODE
XIN Clock Input
XIN Clock Output
I
These pins are provided for the XIN clock generation
circuit I/O. Connect a ceramic resonator or a crystal
oscillator between the XIN and XOUT pins. To use an
externally derived clock, input it to the XIN pin and leave
the XOUT pin open.
XOUT
O
INT Interrupt Input
INT0 to INT3
I
INT interrupt input pins.
INT0 Timer RD input pins.
INT1 Timer RA input pins.
Key Input Interrupt
Timer RA
KI0 to KI3
TRAIO
TRAO
I
Key input interrupt input pins.
Timer RA I/O pin.
I/O
O
Timer RA output pin.
Timer RB output pin.
Timer RD I/O ports.
Timer RB
Timer RD
TRBO
O
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
TRDCLK
TREO
CLK0
I
External clock input pin.
Divided clock output pin.
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Clock I/O pin.
Timer RE
O
Serial Interface
I/O
I
RXD0, RXD1
TXD0, TXD1
SCL
O
I2C Bus Interface
I/O
I/O
I/O
I/O
I/O
I/O
I
SDA
Data I/O pin.
Clock Synchronous
Serial I/O with Chip
Select
SSI
Data I/O pin.
SCS
Chip-select signal I/O pin.
Clock I/O pin.
SSCK
SSO
Data I/O pin.
Reference Voltage Input VREF
Reference voltage input pin to A/D converter.
Analog input pins to A/D converter.
A/D Converter
I/O Port
AN0 to AN11
I
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
I/O
CMOS I/O ports. Each port contains an input/output
select direction register, allowing each pin in that port to
be directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by a program.
Input Port
P4_2, P4_6, P4_7
I
Input only ports.
I: Input
O: Output
I/O: Input and output
Rev.2.00 Aug 27, 2008 Page 8 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
1. Overview
Table 1.6
Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules
Pin
Number
Clock Synchronous
I2C Bus
Interface
Control Pin Port
Serial
Interface
A/D
Converter
Interrupt
Timer
Serial I/O
with Chip Select
SSCK
1
2
3
P3_5
P3_3
P3_4
SCL
SSI
SDA
SCS
4
5
6
7
MODE
P4_3
P4_4
RESET
8
9
XOUT
VSS/AVSS
XIN
P4_7
P4_6
10
11
12
13
14
15
16
17
18
19
20
VCC/AVCC
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/TRDCLK
TRAIO
INT1
21
22
P1_6
P1_5
CLK0
RXD0
(TRAIO)(1)
(INT1)(1)
23
24
P1_4
P1_3
TXD0
AN11
KI3
INT0
INT2
INT3
KI2
25
26
27
28
29
30
P4_5
P6_6
P6_7
P1_2
P1_1
P1_0
INT0
TXD1
RXD1
AN10
AN9
AN8
KI1
KI0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P3_1
P3_0
P6_5
P6_4
P6_3
P0_7
P0_6
P0_5
P0_4
P4_2
P6_0
P6_2
P6_1
P0_3
P0_2
P0_1
P0_0
P3_7
TRBO
TRAO
AN0
AN1
AN2
AN3
VREF
TREO
AN4
AN5
AN6
AN7
SSO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Rev.2.00 Aug 27, 2008 Page 9 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
comprise a register bank. Two sets of register banks are provided.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers(1)
R3
A0
Address registers(1)
A1
FB
Frame base registers(1)
b19
b15
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
b19
b0
PC
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
NOTE:
1. A register bank comprises these registers. Two sets of register banks are provided.
Figure 2.1
CPU Registers
Rev.2.00 Aug 27, 2008 Page 10 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The
same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register
(R2R0). The same applies R3R1 as R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also
are used for transfer, arithmetic and logic operations. The same applies to A1 as A0.
A1 can be combined with A0 to be used a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB, a 20-bit register, indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU status.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debug only. Set to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.
2.8.5
Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.
Rev.2.00 Aug 27, 2008 Page 11 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to
0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.2.00 Aug 27, 2008 Page 12 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
3. Memory
3. Memory
3.1
R8C/20 Group
Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future
user and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
01300h
02000h
Reserved area
0FFDCh
Undefined instruction
Overflow
03000h
BRK instruction
Internal RAM
Address match
Single step
0SSSSh
0YYYYh
Watchdog timer•oscillation stop detection•voltage detection
Address break
Internal ROM
(program ROM)
(Reserved)
Reset
0FFFFh
0FFFFh
Internal ROM(2)
(program ROM)
ZZZZZh
FFFFFh
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on
Emulator Debugger of Hardware Manual.
Internal RAM
Internal ROM
Part Number
Size
Address 0YYYYh Address ZZZZZh
Size
Address 0XXXXh Address 0SSSSh
R5F21206JFP, R5F21206KFP 32 Kbytes
R5F21207JFP, R5F21207KFP 48 Kbytes
R5F21208JFP, R5F21208KFP 64 Kbytes
R5F2120AJFP, R5F2120AKFP 96 Kbytes
R5F2120CJFP, R5F2120CKFP 128 Kbytes
08000h
04000h
04000h
04000h
04000h
-
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
-
-
-
13FFFh
1BFFFh
23FFFh
-
037FFh
03BFFh
Figure 3.1
Memory Map of R8C/20 Group
Rev.2.00 Aug 27, 2008 Page 13 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
3. Memory
3.2
R8C/21 Group
Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from
address 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated them. All addresses within the SFR, which have nothing allocated are reserved for future
use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
01300h
02000h
02400h
Reserved area
0FFDCh
Undefined instruction
Overflow
Internal ROM
(data flash)(1)
BRK instruction
Address match
02BFFh
03000h
Single step
Watchdog timer•oscillation stop detection•voltage detection
Address break
Internal RAM
0SSSSh
0YYYYh
Internal ROM
(program ROM)
(Reserved)
Reset
0FFFFh
0FFFFh
Internal ROM(3)
(program ROM)
ZZZZZh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on
Emulator Debugger of Hardware Manual.
Internal RAM
Internal ROM
Part Number
Size
Address 0YYYYh Address ZZZZZh
Size
Address 0XXXXh Address 0SSSSh
R5F21216JFP, R5F21216KFP 32 Kbytes
R5F21217JFP, R5F21217KFP 48 Kbytes
R5F21218JFP, R5F21218KFP 64 Kbytes
R5F2121AJFP, R5F2121AKFP 96 Kbytes
R5F2121CJFP, R5F2121CKFP 128 Kbytes
08000h
04000h
04000h
04000h
04000h
-
2 Kbytes
2.5 Kbytes
3 Kbytes
5 Kbytes
6 Kbytes
00BFFh
00DFFh
00FFFh
00FFFh
00FFFh
-
-
-
13FFFh
1BFFFh
23FFFh
-
037FFh
03BFFh
Figure 3.2
Memory Map of R8C/21 Group
Rev.2.00 Aug 27, 2008 Page 14 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function.
Table 4.1 to Table 4.6 list the SFR Information.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01101000b
00100000b
Protect Register
PRCR
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
00000100b
XXh
WDTR
WDTS
WDC
XXh
00X11111b
00h
RMAD0
00h
00h
00h
00h
00h
00h
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
Count Source Protect Mode Register
CSPR
00h
(8)
10000000b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
FRA0
FRA1
FRA2
00h
When shipping
00h
0030h
0031h
0032h
(2)
VCA1
VCA2
00001000b
Voltage Detection Register 1
(6)
(3)
Voltage Detection Register 2
00h
(4)
01000000b
0033h
0034h
0035h
0036h
(7)
(3)
VW1C
VW2C
Voltage Monitor 1 Circuit Control Register
0000X000b
(4)
0100X001b
00h
(5)
0037h
0038h
0039h
Voltage Monitor 2 Circuit Control Register
003Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1.
4. Power-on reset, voltage monitor 1 reset or the LVD0ON bit in the OFS register is set to 0.
5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
6. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7.
7. Software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6.
8. The CSPROINI bit in the OFS register is 0.
Rev.2.00 Aug 27, 2008 Page 15 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Symbol
After reset
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
TRD0IC
TRD1IC
TREIC
XXXXX000b
XXXXX000b
XXXXX000b
Key Input Interrupt Control Register
KUPIC
XXXXX000b
XXXXX000b
XXXXX000b
A/D Conversion Interrupt Control Register
ADIC
(2)
SSUIC/IICIC
SSU Interrupt Control Register/IIC Bus Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RA Interrupt Control Register
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.00 Aug 27, 2008 Page 16 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
After reset
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
00h
XXh
XXh
XXh
U0BRG
U0TB
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00001000b
00000010b
XXh
XXh
(2)
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
SSSR/ICSR
00h
SS Control Register H/IIC Bus Control Register 1
(2)
01111101b
00011000b
00h
SS Control Register L/IIC Bus Control Register 2
(2)
SS Mode Register/IIC Bus Mode Register 1
(2)
SS Enable Register/IIC Bus Interrupt Enable Register
(2)
00h/0000X000b
00h
SS Status Register/IIC Bus Status Register
(2)
SSMR2/SAR
SSTDR/ICDRT
SSRDR/ICDRR
SS Mode Register 2/Slave Address Register
(2)
FFh
SS Transmit Data Register/IIC Bus Transmit Data Register
(2)
FFh
SS Receive Data Register/IIC Bus Receive Data Register
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.00 Aug 27, 2008 Page 17 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After reset
A/D Register
AD
XXh
XXh
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00h
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P4 Direction Register
Port P6 Register
PD4
P6
00h
XXh
00h
Port P6 Direction Register
PD6
UART1 Function Select Register
U1SR
XXh
Port Mode Register
PMR
00h
00h
00h
00h
00h
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
INTEN
INTF
KIEN
PUR0
PUR1
XX00XX00b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Aug 27, 2008 Page 18 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
(1)
Table 4.5
SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
After reset
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
00h
00h
00h
FFh
FFh
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary
LINCR
LINST
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
Timer RE Counter Data Register
Timer RE Compare Data Register
TRESEC
TREMIN
00h
00h
Timer RE Control Register 1
Timer RE Control Register 2
TRECR1
TRECR2
TRECSR
00h
00h
Timer RE Count Source Select Register
00001000b
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
TRDSTR
TRDMR
11111100b
00001110b
10001000b
10000000b
FFh
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
01111111b
00h
00h
00h
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Aug 27, 2008 Page 19 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
4. Special Function Registers (SFRs)
(1)
Table 4.6
SFR Information (6)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
Register
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
After reset
Timer RD Control Register 0
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RD General Register A0
Timer RD General Register B0
Timer RD General Register C0
Timer RD General Register D0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
FFh
00h
Timer RD Control Register 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
10001000b
10001000b
11000000b
11100000b
11111000b
00h
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RD General Register A1
Timer RD General Register B1
Timer RD General Register C1
Timer RD General Register D1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
FFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Flash Memory Control Register 4
Flash Memory Control Register 1
Flash Memory Control Register 0
FMR4
FMR1
FMR0
01000000b
1000000Xb
00000001b
FFFFh
Option Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.2.00 Aug 27, 2008 Page 20 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Supply voltage
Condition
Rated value
Unit
V
VCC/AVCC
-0.3 to 6.5
-0.3 to VCC+0.3
-0.3 to VCC+0.3
300
VI
Input voltage
V
VO
Pd
Output voltage
V
Power dissipation
-40°C ≤ Topr ≤ 85°C
85°C < Topr ≤ 125°C
mW
mW
°C
125
Topr
Tstg
Operating ambient temperature
Storage temperature
-40 to 85 (J version) /
-40 to 125 (K version)
-65 to 150
°C
Table 5.2
Recommended Operating Conditions
Standard
Symbol
Parameter
Conditions
Unit
Min.
Typ.
−
Max.
VCC/AVCC
VSS/AVCC
VIH
Supply voltage
Supply voltage
Input “H” voltage
Input “L” voltage
2.7
5.5
−
V
V
−
0
0.8VCC
−
VCC
0.2VCC
-60
V
VIL
0
−
V
IOH(sum)
Peak sum output “H”
current
Sum of all
Pins IOH (peak)
−
−
mA
IOH(peak)
IOH(avg)
IOL(sum)
Peak output “H” current
−
−
−
−
−
−
-10
-5
mA
mA
mA
Average output “H” current
Peak sum output “L”
currents
Sum of all
Pins IOL (peak)
60
IOL(peak)
IOL(avg)
f(XIN)
Peak output “L” currents
Average output “L” current
−
−
0
−
−
−
10
5
mA
mA
XIN clock input oscillation frequency
3.0 V ≤ VCC ≤ 5.5 V
-40°C ≤ Topr ≤ 85°C
20
MHz
3.0 V ≤ VCC ≤ 5.5 V
0
−
16
MHz
-40°C ≤ Topr ≤ 125°C
2.7 V ≤ VCC < 3.0 V
0
0
−
−
10
20
MHz
MHz
−
System clock
OCD2 = 0
3.0 V ≤ VCC ≤ 5.5 V
-40°C ≤ Topr ≤ 85°C
When XIN
clock is
selected.
3.0 V ≤ VCC ≤ 5.5 V
-40°C ≤ Topr ≤ 125°C
0
−
16
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
kHz
OCD2 = 1
FRA01 = 0
−
125
−
When on-chip When low-speed on-
oscillator clock chip oscillator clock is
is selected.
selected.
FRA01 = 1
−
−
−
−
20
10
MHz
MHz
When high-speed on-
chip oscillator clock is
selected.
3.0 V ≤ VCC ≤ 5.5 V
-40°C ≤ Topr ≤ 85°C
FRA01 = 1
When high-speed on-
chip oscillator clock is
selected.
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.2.00 Aug 27, 2008 Page 21 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.3
A/D Converter Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min. Typ.
Max.
10
−
−
Resolution
Vref = AVCC
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Bits
LSB
LSB
LSB
LSB
kΩ
Absolute
Accuracy
10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 3.3 V
φAD = 10 MHz, Vref = AVCC = 3.3 V
Vref = AVCC
±3
8-bit mode
10-bit mode
8-bit mode
−
±2
−
±5
−
±2
Rladder
tconv
Resistor ladder
10
3.3
2.8
2.7
0
40
Conversion time 10-bit mode
8-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
µs
−
µs
Vref
VIA
−
Reference voltage
AVCC
AVCC
10
V
Analog input voltage(2)
V
A/D operating
clock frequency
Without sample & hold
With sample & hold
0.25
1
MHz
MHz
10
NOTES:
1. VCC = AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. When analog input voltage exceeds reference voltage, A/D conversion result is 3FFh in 10-bit mode, FFh in 8-bit mode.
P0
P1
30pF
P2
P3
P4
P6
Figure 5.1
Ports P0 to P4, P6 Timing Measurement Circuit
Rev.2.00 Aug 27, 2008 Page 22 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.4
Flash Memory (Program ROM) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
R8C/20 Group
Min.
Typ.
Max.
−
Program/erase endurance(2)
100(3)
−
−
−
times
times
µs
1,000(3)
R8C/21 Group
−
−
−
Byte program time
Block erase time
−
−
−
50
0.4
−
400
9
s
td(SR-SUS) Time delay from suspend request until
erase suspend
97 + CPU clock
µs
× 6 cycle
−
−
−
Interval from erase start/restart until
following suspend request
650
0
−
−
−
−
−
µs
ns
µs
Interval from program start/restart until
following suspend request
Time from suspend until program/erase
restart
−
3 + CPU clock
× 4 cycle
−
−
−
−
Program, erase voltage
Read voltage
2.7
2.7
0
−
−
−
−
5.5
5.5
60
−
V
V
Program, erase temperature
Data hold time(7)
°C
Ambient temperature = 55°C
20
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times.
For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is
erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more
than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure endurance can be reduced by writing to
sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For
example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to
128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each
block and limit the number of erase operations to a certain number.
5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at
least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.00 Aug 27, 2008 Page 23 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
(4)
Table 5.5
Flash Memory (Data Flash Block A, Block B) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
10,000(3)
−
Typ.
−
Max.
−
Program/erase endurance(2)
−
−
times
Byte program time
50
400
µs
(Program/erase endurance ≤ 1,000 times)
−
−
−
Byte program time
(Program/erase endurance > 1,000 times)
−
−
65
0.2
0.3
−
−
9
−
µs
s
Block erase time
(Program/erase endurance ≤ 1,000 times)
Block erase time
(Program/erase endurance > 1,000 times)
−
s
td(SR-SUS) Time delay from suspend request until
erase suspend
−
97 + CPU clock
µs
µs
ns
µs
× 6 cycle
−
−
−
Interval from erase start/restart until
following suspend request
650
0
−
−
Interval from program start/restart until
following suspend request
−
−
Time from suspend until program/erase
restart
−
−
3 + CPU clock
× 4 cycle
−
−
−
−
Program, erase voltage
Read voltage
2.7
2.7
-40
20
−
−
−
−
5.5
5.5
85(8)
−
V
V
Program, erase temperature
°C
Data hold time(9)
Ambient temperature = 55°C
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times.
For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is
erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more
than once per erase operation (overwriting prohibited).
3. MInimum endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
are the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure endurance can be reduced by writing to
sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For
example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to
128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B
can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block
and limit the number of erase operations to a certain number.
6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at
least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. 125°C for K version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.00 Aug 27, 2008 Page 24 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Suspend request
(Maskable interrupt request)
FMR46
Fixed time
Clock-dependent time
Access restart
td(SR-SUS)
Figure 5.2
Time delay until Suspend
Table 5.6
Voltage Detection 1 Circuit Electrical Characteristics
Standard
Symbol
Parameter
Voltage detection level(3, 4)
Condition
Unit
Min.
2.70
−
Typ.
2.85
40
Max.
3.00
200
−
Vdet1
td(Vdet1-A)
−
V
Voltage monitor 1 reset generation time(5)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(2)
µs
µA
µs
VCA26 = 1, VCC = 5.0 V
−
0.6
−
td(E-A)
−
100
Vccmin
MCU operating voltage minimum value
2.70
−
−
V
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
3. Hold Vdet2 > Vdet1.
4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power
supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V.
5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter,
its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the
voltage passes Vdet1 when the power supply falls.
Table 5.7
Voltage Detection 2 Circuit Electrical Characteristics
Standard
Typ.
Symbol
Parameter
Voltage detection level(4)
Condition
Unit
Min.
3.3
−
Max.
3.9
Vdet2
3.6
V
td(Vdet2-A)
Voltage monitor 2 reset/interrupt request generation
time(2, 5)
40
200
µs
−
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(3)
VCA27 = 1, VCC = 5.0V
−
−
0.6
−
µA
µs
td(E-A)
−
100
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version).
2. Time until the voltage monitor 2 reset/interrupt request is generated since the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
4. Hold Vdet2 > Vdet1.
5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this
time until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls.
Rev.2.00 Aug 27, 2008 Page 25 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
(3)
Table 5.8
Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Unit
Min.
−
Typ.
Max.
0.1
Power-on reset valid voltage(4)
Vpor1
Vpor2
trth
−
−
−
−
V
V
Power-on reset or voltage monitor 1 valid voltage
External power VCC rise gradient
0
Vdet1
−
20(2)
20(2)
VCC ≤ 3.6 V
VCC > 3.6 V
mV/msec
2,000 mV/msec
NOTES:
1. Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.
2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the
VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1)
for 3,000s or more if -40°C ≤ Topr < -20°C.
(3)
(3)
Vdet1
Vdet1
trth
2.0 V
trth
External power Vcc
Vpor1
td(Vdet1-A)
Vpor2
tw(por1)
Sampling time(1, 2)
Internal reset signal
(“L” valid)
1
1
× 32
× 32
fOCO-S
fOCO-S
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of
Hardware Manual for details.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Rev.2.00 Aug 27, 2008 Page 26 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.9
High-Speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Condition
Min.
39.2
Typ.
40
Max.
40.8
fOCO40M
High-speed on-chip oscillator frequency temperature VCC = 4.75 V to 5.25 V,
• supply voltage dependence
MHz
MHz
MHz
MHz
MHz
−
0°C ≤ Topr ≤ 60°C(2)
VCC = 3.0 V to 5.25 V,
-20°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 V to 5.5 V,
-40°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 V to 5.5 V,
-40°C ≤ Topr ≤ 125°C(2)
VCC = 2.7 V to 5.5 V,
-40°C ≤ Topr ≤ 125°C(2)
38.8
38.4
38.0
37.6
08h
−
40
40
41.2
41.6
42.0
42.4
F7h
−
40
40
−
−
The value of the FRA1 register when the reset is
deasserted
40
High-speed on-chip oscillator adjustment range
Adjust the FRA1 register to
-1 bit (the value when the
reset is deasserted)
+ 0.3
MHz
−
−
Oscillation stability time
−
−
10
100
µs
Self power consumption when high-speed on-chip
oscillator oscillating
VCC = 5.0 V, Topr = 25°C
600
−
µA
NOTES:
1. VCC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.
2. The standard value shows when the reset is deasserted for the FRA1 register.
Table 5.10
Low-Speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Typ.
125
Symbol
Parameter
Condition
Unit
Min.
40
−
Max.
250
100
−
fOCO-S
Low-speed on-chip oscillator frequency
Oscillation stability time
kHz
µs
−
−
10
Self power consumption when low-speed on-chip
oscillator oscillating
VCC = 5.0 V, Topr = 25°C
−
15
µA
NOTE:
1. VCC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified.
Table 5.11
Power Supply Circuit Timing Characteristics
Standard
Symbol
Parameter
Condition
Unit
Min.
1
Typ.
Max.
2000
td(P-R)
Time for internal power supply stabilization during
power-on(2)
−
µs
STOP exit time(3)
td(R-S)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless
otherwise specified.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode.
Rev.2.00 Aug 27, 2008 Page 27 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
(1)
Table 5.12
Timing Requirements of Clock Synchronous Serial I/O with Chip Select
Standard
Unit
Symbol
Parameter
SSCK clock cycle time
Conditions
Min.
Typ.
−
Max.
−
(2)
tCYC
tSUCYC
tHI
4
SSCK clock “H” width
SSCK clock “L” width
SSCK clock rising time
0.4
−
0.6
0.6
1
tSUCYC
tSUCYC
tLO
0.4
−
(2)
tRISE
Master
Slave
−
−
tCYC
−
−
1
µs
(2)
tFALL
SSCK clock falling time
Master
Slave
−
−
1
tCYC
−
100
−
1
µs
tSU
SSO, SSI data input setup time
SSO, SSI data input hold time
−
−
ns
(2)
tH
1
−
−
tCYC
tLEAD
Slave
Slave
1tCYC + 50
−
−
ns
ns
SCS setup time
tLAG
1tCYC + 50
−
−
SCS hold time
(2)
tOD
tSA
tOR
SSO, SSI data output delay time
SSI slave access time
SSI slave out open time
−
−
−
−
−
−
1
tCYC
1tCYC + 100
1tCYC + 100
ns
ns
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.00 Aug 27, 2008 Page 28 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
4-wire bus communication mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
SCS (output)
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
4-wire bus communication mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.00 Aug 27, 2008 Page 29 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
4-wire bus communication mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-wire bus communication mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.00 Aug 27, 2008 Page 30 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
SSI (input)
tOD
tSU
tH
Figure 5.6
I/O Timing of Clock Synchronous Serial I/O with Chip Select
(Clock Synchronous Communication Mode)
Rev.2.00 Aug 27, 2008 Page 31 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
2
(1)
Table 5.13
Timing Requirements of I C Bus Interface
Standard
Unit
Symbol
tSCL
Parameter
SCL input cycle time
Conditions
Min.
12tCYC +
600(2)
3tCYC +
300(2)
5tCYC +
300(2)
−
Typ.
Max.
−
−
ns
ns
ns
tSCLH
tSCLL
SCL input “H” width
SCL input “L” width
−
−
−
−
tsf
SCL, SDA input falling time
−
−
−
−
−
300
ns
ns
ns
ns
ns
(2)
tSP
SCL, SDA input spike pulse rejection time
SDA input bus-free time
−
1tCYC
(2)
tBUF
tSTAH
tSTAS
−
−
−
5tCYC
(2)
Start condition input hole time
3tCYC
(2)
3tCYC
Retransmit start condition input setup time
(2)
tSTOP
tSOAS
−
−
−
−
ns
ns
3tCYC
Stop condition input setup time
Data input setup time
1tCYC +
20(2)
0
tSDAH
Data input hold time
−
−
ns
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSP
tSTOP
tSCLH
tSTAS
SCL
P(2)
S(1)
tSf
Sr(3)
P(2)
tSCLL
tSr
tSDAS
tSCL
tSDAH
NOTES:
1. Start condition
2. Stop condition
3. Retransmit “Start” condition
2
Figure 5.7
I/O Timing of I C Bus Interface
Rev.2.00 Aug 27, 2008 Page 32 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.14
Electrical Characteristics (1) [VCC = 5 V]
Standard
Unit
Symbol
Parameter
Output “H” Voltage Except XOUT
Condition
Min.
Typ.
Max.
VCC
VCC
VCC
VOH
IOH = -5 mA
VCC − 2.0
VCC − 0.3
VCC − 2.0
−
−
−
V
V
V
IOH = -200 µA
XOUT
Drive capacity
HIGH
IOH = -1 mA
Drive capacity
LOW
IOH = -500 µA VCC − 2.0
−
VCC
V
VOL
Output “L” Voltage
Except XOUT
XOUT
IOL = 5 mA
−
−
−
−
−
2.0
0.45
2.0
V
V
V
IOL = 200 µA
Drive capacity
HIGH
IOL = 1 mA
−
Drive capacity
LOW
IOL = 500 µA
−
−
2.0
V
V
VT+-VT-
Hysteresis
0.1
0.5
−
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, SSI,
SCL, SDA, SSO
0.1
1.0
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 5 V, VCC = 5 V
VI = 0 V, VCC = 5 V
VI = 0 V, VCC = 5 V
−
−
−
−
5.0
-5.0
167
−
µA
µA
RPULLUP Pull-Up Resistance
30
−
50
1.0
kΩ
MΩ
RfXIN
Feedback
XIN
Resistance
VRAM
RAM Hold Voltage
During stop mode
2.0
−
−
V
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.00 Aug 27, 2008 Page 33 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.15
Electrical Characteristics (2) [VCC = 5 V]
(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.)
Standard
Symbol
Parameter
Power supply current High-clock
Condition
Unit
mA
Min.
Typ.
11.0
Max.
22.0
ICC
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
(VCC = 3.3 to 5.5 V)
In single-chip mode,
the output pins are
open and other pins
are VSS
mode
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
−
−
−
−
−
−
−
8.8
5.8
5.0
3.8
2.8
5.8
2.5
143
17.6
−
mA
mA
mA
mA
mA
mA
mA
µA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
XIN = 16MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
High-speed
on-chip
oscillator
mode
XIN clock off
11.6
−
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO= 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
XIN clock off
286
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
Wait mode
XIN clock off
−
−
53
38
106
76
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA20 = 0
VCA26 = VCA27 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA20 = 0
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
−
−
0.8
1.2
4.0
3.0
µA
µA
µA
Topr = 25°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
Topr = 85°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
Topr = 125°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Rev.2.00 Aug 27, 2008 Page 34 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 5.16
XIN Input
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(XIN)
XIN input cycle time
XIN input “H” width
XIN input “L” width
50
25
25
−
−
−
ns
ns
ns
tWH(XIN)
tWL(XIN)
Vcc = 5V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.8
XIN Input Timing Diagram when VCC = 5 V
Table 5.17
TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
tWH(TRAIO)
tWL(TRAIO)
40
Vcc = 5V
tc(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
Rev.2.00 Aug 27, 2008 Page 35 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.18
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXDi output delay time
TXDi hold time
200
100
100
−
−
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
50
−
0
RXDi input setup time
RXDi input hold time
50
90
−
−
i = 0 or 1
Vcc = 5V
tc(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
RXDi
th(C-D)
td(C-Q)
tsu(D-C)
i = 0 or 1
Figure 5.10
Serial Interface Timing Diagram when VCC = 5 V
Table 5.19
External Interrupt INTi (i = 0 to 3) Input
Standard
Min. Max.
Symbol
Parameter
Unit
250(1)
250(2)
tW(INH)
tW(INL)
−
−
ns
ns
INTi input “H” width
INTi input “L” width
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either
(1/digital filter clock frequency x 3) or the minimum value of standard.
2. When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either
(1/digital filter clock frequency x 3) or the minimum value of standard.
Vcc = 5V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V (i = 0 to 3)
Rev.2.00 Aug 27, 2008 Page 36 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.20
Electrical Characteristics (3) [VCC = 3 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage Except XOUT
Condition
Min.
Typ.
−
Max.
VCC
VCC
VOH
IOH = -1 mA
VCC − 0.5
V
V
XOUT
Drive capacity
HIGH
IOH = -0.1 mA VCC − 0.5
−
Drive capacity
LOW
IOH = -50 µA
VCC − 0.5
−
VCC
V
VOL
Output “L” voltage
Hysteresis
Except XOUT
XOUT
IOL = 1 mA
−
−
−
−
0.5
0.5
V
V
Drive capacity
HIGH
IOL = 0.1 mA
Drive capacity
LOW
IOL = 50 µA
−
−
0.5
V
V
VT+-VT-
0.1
0.3
−
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, SSI,
SCL, SDA, SSO
0.1
0.4
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 3 V, VCC = 3 V
VI = 0 V, VCC = 3 V
VI = 0 V, VCC = 3 V
−
−
−
−
4.0
-4.0
500
−
µA
µA
kΩ
MΩ
V
RPULLUP Pull-up resistance
66
−
160
3.0
−
RfXIN
VRAM
Feedback resistance XIN
RAM hold voltage
During stop mode
2.0
−
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.00 Aug 27, 2008 Page 37 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.21
Electrical Characteristics (4) [VCC = 3 V]
(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.)
Standard
Symbol
Parameter
Power supply current High-clock
Condition
Unit
mA
Min.
Typ.
10.5
Max.
21.0
ICC
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
(VCC = 2.7 to 3.3 V)
In single-chip mode,
the output pins are
open and other pins
are VSS
mode
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
−
−
−
−
−
−
−
8.3
5.3
4.5
3.3
2.3
5.6
2.4
138
16.6
10.6
−
mA
mA
mA
mA
mA
mA
mA
µA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
High-speed
on-chip
oscillator
mode
XIN clock off
11.2
−
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
XIN clock off
276
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
Wait mode
XIN clock off
−
−
48
35
96
70
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA20 = 0
VCA26 = VCA27 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA20 = 0
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
−
−
0.7
1.1
3.8
3.0
µA
µA
µA
Topr = 25°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
Topr = 85°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Stop mode
XIN clock off
−
Topr = 125°C High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA26 = VCA27 = 0
Rev.2.00 Aug 27, 2008 Page 38 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Timing Requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0V at Topr = 25°C) [VCC = 3 V]
Table 5.22
XIN Input
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(XIN)
XIN input cycle time
XIN input “H” width
XIN input “L” width
100
40
−
−
−
ns
ns
ns
tWH(XIN)
tWL(XIN)
40
Vcc = 3V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.12
XIN Input Timing Diagram when VCC = 3 V
Table 5.23
TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TRAIO)
TRAIO input Cycle time
TRAIO input “H” width
TRAIO input “L” width
300
120
120
−
−
−
ns
ns
ns
tWH(TRAIO)
tWL(TRAIO)
Vcc = 3V
tc(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
Rev.2.00 Aug 27, 2008 Page 39 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
5. Electrical Characteristics
Table 5.24
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXDi output delay time
TXDi hold time
300
150
150
−
−
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
80
−
0
RXDi input setup time
RXDi input hold time
70
90
−
−
i = 0 or 1
Vcc = 3V
tc(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 or 1
Figure 5.14
Serial Interface Timing Diagram when VCC = 3 V
Table 5.25
External Interrupt INTi (i = 0 to 3) Input
Standard
Min. Max.
Symbol
Parameter
Unit
380(1)
380(2)
tW(INH)
tW(INL)
−
−
ns
ns
INTi input “H” width
INTi input “L” width
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either
(1/digital filter clock frequency x 3) or the minimum value of standard.
2. When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either
(1/digital filter clock frequency x 3) or the minimum value of standard.
Vcc = 3V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V (i = 0 to 3)
Rev.2.00 Aug 27, 2008 Page 40 of 41
REJ03B0120-0200
R8C/20 Group, R8C/21 Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages”
section of the Renesas Technology website.
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
37
24
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
A2
HD
HE
A
6.9 7.0 7.1
6.9 7.0 7.1
1.4
Terminal cross section
48
13
8.8 9.0 9.2
8.8 9.0 9.2
1.7
1
12
Index mark
ZD
A1
bp
b1
c
0
0.1 0.2
F
0.17 0.22 0.27
0.20
c
0.145
0.125
0.09
0.20
L
c1
L1
0°
8°
e
0.5
y
*3
x
Detail F
0.08
0.10
bp
e
x
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
Rev.2.00 Aug 27, 2008 Page 41 of 41
REJ03B0120-0200
REVISION HISTORY
R8C/20 Group, R8C/21 Group Datasheet
Description
Summary
Rev.
Date
Page
0.10
0.20
Mar 08, 2005
Sep 29, 2005
−
−
First Edition issued
Words standardized
- Clock synchronous serial interface → Clock synchronous serial I/O
- Chip-select clock synchronous interface(SSU)
→ Clock synchronous serial I/O with chip select
2
2
- I C bus interface(IIC) → I C bus interface
2, 3
Table1.1 R8C/20 Group Performance, Table1.2 R8C/21 Group
Performance
Serial Interface revised:
- Clock Synchronous Serial Interface: 1 channel
2
I C bus Interface (3), Clock synchronous serial I/O with chip select
- Power-On Reset Circuit added
- Power Consumption value determined
5, 6
7
Table 1.3 Product Information of R8C/20 Group, Table 1.4 Product
Information of R8C/21 Group
Date revised.
Figure 1.4 Pin Assignment
Pin name revised:
- P3_5/SSCK(/SCL) → P3_5/ SCL/SSCK
- P3_4/SCS(/SDA) → P3_4/ SDA /SCS
- VSS → VSS/AVSS
- VCC → VCC/AVCC
- P1_5/RXD0/(TRAIO/INT1) → P1_5/RXD0/(TRAIO)/(INT1)
- P6_6/INT2/(TXD1) → P6_6/INT2/TXD1
- P6_7/INT3/(RXD1) → P6_7/INT3/RXD1
- NOTE2 added
8
9
Table 1.5 Pin Description
- Analog Power Supply Input: line added
2
2
- I C Bus Interface (IIC) → I C Bus Interface
- SSU → Clock Synchronous Serial I/O with Chip Select
Table 1.6 Pin Name Information by Pin Number revised
- Pin Number 1: (SCL) → SCL
- Pin Number 2: (SDA) → SDA
- Pin Number 9: VSS → VSS/AVSS
- Pin Number 11: VCC → VCC/AVCC
- Pin Number 26: (TXD1) → TXD1
- Pin Number 27: (RXD1) → RXD1
15
17
18
Table 4.1 SFR Information (1) revised
- 0013h: XXXXXX00b → 00h
Table 4.3 SFR Information (3) revised
- 00BCh: 0000X000b → 00h/0000X000b
Table 4.4 SFR Information (4) revised
- 00D6h: 00000XXXb → 00h
- 00F5h: UART1 Function Select Register added
19
Table 4.5 SFR Information (5) revised
- 0104h: TRATR → TRA
A - 1
REVISION HISTORY
R8C/20 Group, R8C/21 Group Datasheet
Description
Summary
Rev.
0.20
Date
Page
20
Sep 29, 2005
Table 4.6 SFR Information (6) revised
- 0145h: POCR0 → TRDPOCR0
- 0146h, 0147h: TRDCNT0 → TRD0
- 0148h, 0149h: GRA0 → TRDGRA0
- 014Ah, 014Bh: GRB0 → TRDGRB0
- 014Ch, 014Dh: GRC0 → TRDGRC0
- 014Eh, 014Fh: GRD0 → TRDGRD0
- 0155h: POCR1 -> TRDPOCR1
- 0156h, 0157h: TRDCNT1 → TRD1
- 0158h, 0159h: GRA1 → TRDGRA1
- 015Ah, 015Bh: GRB1 → TRDGRB1
- 015Ch, 015Dh: GRC1 → TRDGRC1
- 015Eh, 015Fh: GRD1 → TRDGRD1
22
5. Electrical Characteristics added
1.00
Nov 15, 2006 All pages “Preliminary” and “Under development” deleted
2
3
5
Table 1.1 Functions and Specifications for R8C/20 Group revised.
NOTE1 deleted.
Table 1.2 Functions and Specifications for R8C/21 Group revised.
NOTE1 deleted.
Table 1.3 Product Information for R8C/20 Group;
“R5F2120AJFP (D)”, “R5F2120CJFP (D)”, “R5F2120AKFP (D)”,
“R5F2120CKFP (D)”, and NOTE added.
Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group;
“A: 96 KB” and “C: 128 KB” added.
6
Table 1.4 Product Information for R8C/21 Group;
“R5F2121AJFP (D)”, “R5F2121CJFP (D)”, “R5F2121AKFP (D)”,
“R5F2121CKFP (D)”, and NOTE added.
Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group;
“A: 96 KB” and “C: 128 KB” added.
13
14
15
Figure 3.1 Memory Map of R8C/20 Group revised.
Figure 3.2 Memory Map of R8C/21 Group revised.
(1)
Table 4.1 SFR Information (1)
;
NOTE8; “The CSPROINI bit in the OFS register is set to 0.”
→ “The CSPROINI bit in the OFS register is 0.” revised.
21
26
Table 5.1 Absolute Maximum Ratings; Power dissipation revised.
Table 5.2 Recommended Operating Conditions; System clock revised.
Table 5.8 Voltage Monitor 1 Reset Circuit Electrical Characteristics
→ Table 5.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit
(1)
Electrical Characteristics replaced.
Table 5.8 revised.
NOTE3 added.
Table 5.9 Power-on Reset Circuit Electrical Characteristics deleted.
Figure 5.3 Power-on Reset Circuit Electrical Characteristics revised.
27
Table 5.10 High-Speed On-Chip Oscillator Circuit Electrical
Characteristics → Table 5.9 High-Speed On-Chip Oscillator Circuit
Electrical Characteristics revised.
A - 2
REVISION HISTORY
R8C/20 Group, R8C/21 Group Datasheet
Description
Summary
Rev.
1.00
Date
Page
33
Nov 15, 2006
Table 5.15 Electrical Characteristics (1) [VCC = 5 V]
→ Table 5.14 Electrical Characteristics (1) [VCC = 5 V] revised.
RAM Hold Voltage, Min.; “1.8” → “2.0” corrected.
34
37
38
Table 5.16 Electrical Characteristics (2) [Vcc = 5 V]
→ Table 5.15 Electrical Characteristics (2) [Vcc = 5 V] revised.
Wait mode revised.
Table 5.21 Electrical Characteristics (3) [VCC = 3 V
→ Table 5.20 Electrical Characteristics (3) [VCC = 3 V] revised.
RAM hold voltage, Min.;“1.8” → “2.0” corrected.
Table 5.22 Electrical Characteristics (4) [Vcc = 3 V]
→ Table 5.21 Electrical Characteristics (4) [Vcc = 3 V] revised.
Wait mode revised.
2.00
Aug 27, 2008
−
“RENESAS TECHNICAL UPDATE” reflected: TN-16C-A172A/E
5, 6
Table 1.3, Table 1.4 revised
Figure 1.2, Figure 1.3; ROM number “XXX” added
13, 14 Figure 3.1, Figure 3.2; “Expanding area” deleted
21
23
24
25
Table 5.2; NOTE2 revised
Table 5.4; NOTE2 and NOTE4 revised
Table 5.5; NOTE2 and NOTE5 revised
Table 5.6; “td(Vdet1-A)” added, NOTE5 added
Table 5.7; “td(Vdet2-A)” and NOTE2 revised, NOTE5 added
26
Table 5.8; “trth” and NOTE2 revised
Figure 5.3 revised
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A - 3
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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