R8C2H [RENESAS]
MCU; MCU
RENESAS TECHNOLOGY CORP 
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
Hardware Manual
16
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date: Mar 28, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/2H Group, R8C/2J Group. Make sure to refer to the latest versions of
these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web
site.
Document Type
Datasheet
Description
Document Title
Document No.
REJ03B0217
Hardware overview and electrical characteristics R8C/2H Group,
R8C/2J Group
Datasheet
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
R8C/2H Group,
This hardware
manual
R8C/2J Group
specifications, electrical characteristics, timing
charts) and operation description
Hardware Manual
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set
R8C/Tiny Series
Software Manual
REJ09B0001
Application note Information on using peripheral functions and
application examples
Available from Renesas
Technology Web site.
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3. Register Notation
The symbols and terms used in register diagrams are described below.
*1
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XXX
Address
XXX
After Reset
00h
0
RW
RW
Bit Symbol
XXX0
Bit Name
XXX bits
Function
*2
b1 b0
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
XXX1
(b2)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
*3
*4
Reserved bits
XXX bits
Set to 0.
RW
(b3)
XXX4
XXX5
Function varies according to the operating
mode.
RW
WO
RW
RO
XXX6
XXX7
0: XXX
1: XXX
XXX bit
*1
*2
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
*4
• Reserved bit
Reserved bit. Set to specified value.
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4. List of Abbreviations and Acronyms
Abbreviation
Full Form
ACIA
bps
Asynchronous Communication Interface Adapter
bits per second
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment Bus
Input / Output
IrDA
LSB
MSB
NC
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connect
PLL
PWM
SIM
UART
VCO
Phase Locked Loop
Pulse Width Modulation
Subscriber Identity Module
Universal Asynchronous Receiver / Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1.
Overview ......................................................................................................................................... 1
1.1
1.1.1
1.1.2
Features ..................................................................................................................................................... 1
Applications .......................................................................................................................................... 1
Specifications ........................................................................................................................................ 1
Product List ............................................................................................................................................... 4
Block Diagram .......................................................................................................................................... 6
Pin Assignment .......................................................................................................................................... 8
Pin Functions ........................................................................................................................................... 12
1.2
1.3
1.4
1.5
2.
Central Processing Unit (CPU) ..................................................................................................... 14
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Data Registers (R0, R1, R2, and R3) ...................................................................................................... 15
Address Registers (A0 and A1) ............................................................................................................... 15
Frame Base Register (FB) ....................................................................................................................... 15
Interrupt Table Register (INTB) .............................................................................................................. 15
Program Counter (PC) ............................................................................................................................. 15
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. 15
Static Base Register (SB) ........................................................................................................................ 15
Flag Register (FLG) ................................................................................................................................ 15
2.8.1
2.8.2
Carry Flag (C) ..................................................................................................................................... 15
Debug Flag (D) ................................................................................................................................... 15
Zero Flag (Z) ....................................................................................................................................... 15
Sign Flag (S) ....................................................................................................................................... 15
Register Bank Select Flag (B) ............................................................................................................ 15
Overflow Flag (O) .............................................................................................................................. 15
Interrupt Enable Flag (I) ..................................................................................................................... 16
Stack Pointer Select Flag (U) .............................................................................................................. 16
Processor Interrupt Priority Level (IPL) ............................................................................................. 16
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.10 Reserved Bit ........................................................................................................................................ 16
Memory ......................................................................................................................................... 17
Special Function Registers (SFRs) ............................................................................................... 19
Resets ........................................................................................................................................... 31
3.
4.
5.
5.1
Hardware Reset ....................................................................................................................................... 34
When Power Supply is Stable ............................................................................................................. 34
Power On ............................................................................................................................................ 34
Power-On Reset Function ....................................................................................................................... 36
Voltage Monitor 0 Reset ......................................................................................................................... 37
Voltage Monitor 1 Reset ......................................................................................................................... 37
Voltage Monitor 2 Reset ......................................................................................................................... 37
Watchdog Timer Reset ............................................................................................................................ 38
Software Reset ......................................................................................................................................... 38
5.1.1
5.1.2
5.2
5.3
5.4
5.5
5.6
5.7
6.
Voltage Detection Circuit .............................................................................................................. 39
6.1
VCC Input Voltage .................................................................................................................................. 47
6.1.1
Monitoring Vdet0 ............................................................................................................................... 47
A - 1
6.1.2
6.1.3
Monitoring Vdet1 ............................................................................................................................... 47
Monitoring Vdet2 ............................................................................................................................... 47
Voltage Monitor 0 Reset ......................................................................................................................... 48
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 49
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 51
6.2
6.3
6.4
7.
Comparator ................................................................................................................................... 53
7.1
7.2
7.3
Overview ................................................................................................................................................. 53
Register Description ................................................................................................................................ 55
Monitoring Comparison Results ............................................................................................................. 62
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.5
Monitoring Comparator 1 ................................................................................................................... 62
Monitoring Comparator 2 ................................................................................................................... 62
Functional Description ............................................................................................................................ 63
Comparator 1 ...................................................................................................................................... 63
Comparator 2 ...................................................................................................................................... 66
Comparator 1 and Comparator 2 Interrupts ............................................................................................ 69
Non-Maskable Interrupts .................................................................................................................... 69
Maskable Interrupts ............................................................................................................................ 69
Adjusting Internal Reference Voltage (Vref) .......................................................................................... 70
7.5.1
7.5.2
7.6
8.
9.
I/O Ports ........................................................................................................................................ 72
8.1
8.2
8.3
8.4
8.5
8.6
Functions of I/O Ports ............................................................................................................................. 73
Effect on Peripheral Functions ................................................................................................................ 73
Pins Other than Programmable I/O Ports ................................................................................................ 73
Port Setting .............................................................................................................................................. 83
Unassigned Pin Handling ........................................................................................................................ 89
Notes on I/O Ports ................................................................................................................................... 90
8.6.1
Port P4_3, P4_4 (for R8C/2H Group only) ........................................................................................ 90
Processor Mode ............................................................................................................................ 91
9.1
Processor Modes ...................................................................................................................................... 91
10. Bus ................................................................................................................................................ 92
11.
11.1
Clock Generation Circuit ............................................................................................................... 93
On-Chip Oscillator Clocks .................................................................................................................... 105
11.1.1 Low-Speed On-Chip Oscillator Clock .............................................................................................. 105
11.1.2 High-Speed On-Chip Oscillator Clock ............................................................................................. 105
11.2
11.3
XCIN Clock (for R8C/2H Group only) ................................................................................................. 106
CPU Clock and Peripheral Function Clock ........................................................................................... 107
11.3.1 System Clock .................................................................................................................................... 107
11.3.2 CPU Clock ........................................................................................................................................ 107
11.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ........................................................................... 107
11.3.4 fOCO ................................................................................................................................................. 107
11.3.5 fOCO-F ............................................................................................................................................. 107
11.3.6 fOCO-S ............................................................................................................................................. 107
11.3.7 fC4 and fC32 (for R8C/2H Group only) ........................................................................................... 107
11.4
Power Control ........................................................................................................................................ 108
11.4.1 Standard Operating Mode ................................................................................................................. 108
A - 2
11.4.2 Wait Mode ........................................................................................................................................ 110
11.4.3 Stop Mode ......................................................................................................................................... 112
11.5
Notes on Clock Generation Circuit ....................................................................................................... 116
11.5.1 Stop Mode ......................................................................................................................................... 116
11.5.2 Wait Mode ........................................................................................................................................ 116
11.5.3 Oscillation Circuit Constants ............................................................................................................ 116
12. Protection ..................................................................................................................................... 117
13. Interrupts ...................................................................................................................................... 118
13.1
Interrupt Overview ................................................................................................................................ 118
13.1.1 Types of Interrupts ............................................................................................................................ 118
13.1.2 Software Interrupts ........................................................................................................................... 119
13.1.3 Special Interrupts .............................................................................................................................. 120
13.1.4 Peripheral Function Interrupt ............................................................................................................ 120
13.1.5 Interrupts and Interrupt Vectors ........................................................................................................ 121
13.1.6 Interrupt Control ............................................................................................................................... 123
13.2
INT Interrupt ......................................................................................................................................... 131
13.2.1 INTi Interrupt (i = 0 or 1) ................................................................................................................. 131
13.2.2 INTi Input Filter (i = 0 or 1) ............................................................................................................. 133
13.3
Key Input Interrupt ................................................................................................................................ 134
Address Match Interrupt ........................................................................................................................ 136
Notes on Interrupts ................................................................................................................................ 138
13.4
13.5
13.5.1 Reading Address 00000h .................................................................................................................. 138
13.5.2 SP Setting .......................................................................................................................................... 138
13.5.3 External Interrupt and Key Input Interrupt ....................................................................................... 138
13.5.4 Changing Interrupt Sources .............................................................................................................. 139
13.5.5 Changing Interrupt Control Register Contents ................................................................................. 140
14. ID Code Areas ............................................................................................................................ 141
14.1
14.2
14.3
Overview ............................................................................................................................................... 141
Functions ............................................................................................................................................... 141
Notes on ID Code Areas ........................................................................................................................ 142
14.3.1 Setting Example of ID Code Areas ................................................................................................... 142
15. Option Function Select Area ....................................................................................................... 143
15.1
15.2
15.3
Overview ............................................................................................................................................... 143
OFS Register ......................................................................................................................................... 144
Notes on Option Function Select Area .................................................................................................. 145
15.3.1 Setting Example of Option Function Select Area ............................................................................. 145
16. Watchdog Timer .......................................................................................................................... 146
16.1
16.2
16.3
Count Source Protection Mode Disabled (R8C/2H Group) .................................................................. 153
Count Source Protection Mode Disabled (R8C/2J Group) ................................................................... 154
Count Source Protection Mode Enabled ............................................................................................... 155
17. Timers ......................................................................................................................................... 156
17.1 Timer RA ............................................................................................................................................... 158
17.1.1 Timer Mode ...................................................................................................................................... 161
A - 3
17.1.2 Pulse Output Mode ........................................................................................................................... 163
17.1.3 Event Counter Mode ......................................................................................................................... 165
17.1.4 Pulse Width Measurement Mode ...................................................................................................... 167
17.1.5 Pulse Period Measurement Mode ..................................................................................................... 170
17.1.6 Notes on Timer RA ........................................................................................................................... 173
17.2
Timer RB ............................................................................................................................................... 174
17.2.1 Timer Mode ...................................................................................................................................... 178
17.2.2 Programmable Waveform Generation Mode .................................................................................... 181
17.2.3 Programmable One-shot Generation Mode ...................................................................................... 184
17.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 188
17.2.5 Notes on Timer RB ........................................................................................................................... 191
17.3
Timer RE (for R8C/2H Group only) ..................................................................................................... 195
17.3.1 Real-Time Clock Mode .................................................................................................................... 196
17.3.2 Output Compare Mode ..................................................................................................................... 204
17.3.3 Notes on Timer RE (for R8C/2H Group only) ................................................................................. 210
17.4
Timer RF ............................................................................................................................................... 213
17.4.1 Input Capture Mode .......................................................................................................................... 218
17.4.2 Output Compare Mode ..................................................................................................................... 221
17.4.3 Notes on Timer RF ........................................................................................................................... 225
18. Serial Interface ............................................................................................................................ 226
18.1
Clock Synchronous Serial I/O Mode ..................................................................................................... 231
18.1.1 Polarity Select Function .................................................................................................................... 234
18.1.2 LSB First/MSB First Select Function ............................................................................................... 234
18.1.3 Continuous Receive Mode ................................................................................................................ 235
18.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 236
18.2.1 Bit Rate ............................................................................................................................................. 240
18.3
Notes on Serial Interface ....................................................................................................................... 241
19. Hardware LIN .............................................................................................................................. 242
19.1
19.2
19.3
19.4
Features ................................................................................................................................................. 242
Input/Output Pins .................................................................................................................................. 243
Register Configuration .......................................................................................................................... 244
Functional Description .......................................................................................................................... 246
19.4.1 Master Mode ..................................................................................................................................... 246
19.4.2 Slave Mode ....................................................................................................................................... 249
19.4.3 Bus Collision Detection Function ..................................................................................................... 253
19.4.4 Hardware LIN End Processing ......................................................................................................... 254
19.5
19.6
Interrupt Requests .................................................................................................................................. 255
Notes on Hardware LIN ........................................................................................................................ 256
20. Flash Memory ............................................................................................................................. 257
20.1
20.2
20.3
Overview ............................................................................................................................................... 257
Memory Map ......................................................................................................................................... 258
Functions to Prevent Rewriting of Flash Memory ................................................................................ 259
20.3.1 ID Code Check Function .................................................................................................................. 259
20.3.2 ROM Code Protect Function ............................................................................................................ 260
20.4
CPU Rewrite Mode ............................................................................................................................... 261
20.4.1 Register Description ......................................................................................................................... 262
A - 4
20.4.2 Status Check Procedure .................................................................................................................... 267
20.4.3 EW0 Mode ........................................................................................................................................ 268
20.5
20.6
20.7
Standard Serial I/O Mode ...................................................................................................................... 274
20.5.1 ID Code Check Function .................................................................................................................. 274
Parallel I/O Mode .................................................................................................................................. 276
20.6.1 ROM Code Protect Function ............................................................................................................ 276
Notes on Flash Memory ........................................................................................................................ 277
20.7.1 CPU Rewrite Mode ........................................................................................................................... 277
21. Reducing Power Consumption ................................................................................................... 278
21.1
Overview ............................................................................................................................................... 278
21.2
Key Points and Processing Methods for Reducing Power Consumption ............................................. 278
21.2.1 Voltage Detection Circuit ................................................................................................................. 278
21.2.2 Ports .................................................................................................................................................. 278
21.2.3 Clocks ............................................................................................................................................... 278
21.2.4 Selecting Oscillation Drive Capacity (for R8C/2H Group only) ...................................................... 278
21.2.5 Wait Mode, Stop Mode ..................................................................................................................... 278
21.2.6 Stopping Peripheral Function Clocks ............................................................................................... 278
21.2.7 Timers ............................................................................................................................................... 278
21.2.8 Reducing Internal Power Consumption ............................................................................................ 279
21.2.9 Stopping Flash Memory .................................................................................................................... 280
21.2.10 Low-Current-Consumption Read Mode ........................................................................................... 281
22. Electrical Characteristics ............................................................................................................ 282
22.1
22.2
R8C/2H Group ...................................................................................................................................... 282
R8C/2J Group ........................................................................................................................................ 299
23. Usage Notes ............................................................................................................................... 316
23.1 Notes on I/O Ports ................................................................................................................................. 316
23.1.1 Port P4_3, P4_4 (for R8C/2H Group only) ...................................................................................... 316
23.2
Notes on Clock Generation Circuit ....................................................................................................... 317
23.2.1 Stop Mode ......................................................................................................................................... 317
23.2.2 Wait Mode ........................................................................................................................................ 317
23.2.3 Oscillation Circuit Constants ............................................................................................................ 317
23.3
Notes on Interrupts ................................................................................................................................ 318
23.3.1 Reading Address 00000h .................................................................................................................. 318
23.3.2 SP Setting .......................................................................................................................................... 318
23.3.3 External Interrupt and Key Input Interrupt ....................................................................................... 318
23.3.4 Changing Interrupt Sources .............................................................................................................. 319
23.3.5 Changing Interrupt Control Register Contents ................................................................................. 320
23.4
23.5
23.6
Notes on ID Code Areas ........................................................................................................................ 321
23.4.1 Setting Example of ID Code Areas ................................................................................................... 321
Notes on Option Function Select Area .................................................................................................. 322
23.5.1 Setting Example of Option Function Select Area ............................................................................. 322
Notes on Timers .................................................................................................................................... 323
23.6.1 Notes on Timer RA ........................................................................................................................... 323
23.6.2 Notes on Timer RB ........................................................................................................................... 324
23.6.3 Notes on Timer RE (for R8C/2H Group only) ................................................................................. 328
23.6.4 Notes on Timer RF ........................................................................................................................... 331
A - 5
23.7
23.8
23.9
Notes on Serial Interface ....................................................................................................................... 332
Notes on Hardware LIN ........................................................................................................................ 333
Notes on Flash Memory ........................................................................................................................ 334
23.9.1 CPU Rewrite Mode ........................................................................................................................... 334
23.10 Notes on Noise ...................................................................................................................................... 335
23.10.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 335
23.10.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 335
24. Notes for On-Chip Debugger ...................................................................................................... 336
Appendix 1. Package Dimensions ........................................................................................................ 337
Appendix 2. Connection Examples with On-Chip Debugging Emulator ............................................... 338
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 339
Index ..................................................................................................................................................... 340
A - 6
SFR Page Reference
Address
0000h
0001h
0002h
0003h
Register
Symbol
Page
Address
0040h
Register
Symbol
VCMP1IC
Page
0041h Comparator 1 Interrupt Control Register
0042h Comparator 2 Interrupt Control Register
123
123
VCMP2IC
0043h
0044h
0045h
0046h
0047h
0048h
0049h
(2)
0004h Processor Mode Register 0
0005h Processor Mode Register 1
0006h System Clock Control Register 0
0007h System Clock Control Register 1
0008h
0009h
000Ah Protect Register
000Bh
000Ch
000Dh Watchdog Timer Reset Register
000Eh Watchdog Timer Start Register
000Fh Watchdog Timer Control Register
0010h Address Match Interrupt Register 0
0011h
0012h
0013h Address Match Interrupt Enable Register
0014h Address Match Interrupt Register 1
0015h
0016h
0017h
0018h
0019h
001Ah
PM0
91
91
96, 97
98, 99
PM1
CM0
CM1
PRCR
117
004Ah
004Bh
004Ch
TREIC
S2TIC
S2RIC
KUPIC
123
123
123
123
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
(2)
(2)
(2)
OCD
100
149
149
150
137
System Clock Select Register
WDTR
WDTS
WDC
004Dh Key Input Interrupt Control Register
004Eh
004Fh
0050h Compare 1 Interrupt Control Register
0051h UART0 Transmit Interrupt Control Register S0TIC
0052h UART0 Receive Interrupt Control Register S0RIC
0053h
0054h
0055h
0056h Timer RA Interrupt Control Register
0057h
0058h Timer RB Interrupt Control Register
0059h INT1 Interrupt Control Register
RMAD0
CMP1IC
123
123
123
AIER
RMAD1
137
137
TRAIC
123
TRBIC
INT1IC
123
124
005Ah
001Bh
005Bh Timer RF Interrupt Control Register
005Ch Compare 0 Interrupt Control Register
005Dh INT0 Interrupt Control Register
005Eh
TRFIC
CMP0IC
INT0IC
123
123
124
001Ch Count Source Protection Mode Register
CSPR
151
001Dh
001Eh
001Fh
005Fh Capture Interrupt Control Register
CAPIC
123
0020h High-Speed On-Chip Oscillator Control Register 0 HRA0
0021h High-Speed On-Chip Oscillator Control Register 1 HRA1
0022h High-Speed On-Chip Oscillator Control Register 2 HRA2
101
101
101
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0023h
0024h
0025h
0026h
0027h
(2)
0028h
CPSRF
102
102
Clock Prescaler Reset Flag
0029h High-Speed On-Chip Oscillator Control Register 4 FRA4
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6
002Ch
002Dh
002Eh BGR Trimming Auxiliary Register A
002Fh BGR Trimming Auxiliary Register B
0030h
0031h Voltage Detection Register 1
0032h Voltage Detection Register 2
102
BGRTRMA
BGRTRMB
55
55
VCA1
VCA2
42, 56
42, 56,
103
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register
0037h Voltage Monitor 2 Circuit Control Register
0038h Voltage Monitor 0 Circuit Control Register
0039h
003Ah
VW1C
VW2C
VW0C
44, 57
45, 58
43
003Bh Voltage Detection Circuit External Input Control
VCAB
59
Register
003Ch Comparator Mode Register
003Dh Voltage Monitor Circuit Edge Select Register
003Eh BGR Control Register
ALCMR
VCAC
BGRCR
BGRTRM
59
46, 60
60
003Fh BGR Trimming Register
61
NOTES:
1. The blank regions are reserved. Do not access locations in these
regions.
2. This register is not implemented in the R8C/2J Group.
B - 1
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
Register
Symbol
Page
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
Page
00A0h UART0 Transmit/Receive Mode Register
00A1h UART0 Bit Rate Register
00A2h UART0 Transmit Buffer Register
00A3h
00A4h UART0 Transmit/Receive Control Register 0 U0C0
00A5h UART0 Transmit/Receive Control Register 1 U0C1
U0MR
U0BRG
U0TB
228
228
229
Port P1 Register
P1
78, 79
78, 79
78, 79
Port P1 Direction Register
Port P3 Register
PD1
P3
229
230
230
00A6h UART0 Receive Buffer Register
U0RB
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Port P3 Direction Register
Port P4 Register
PD3
P4
78, 79
78, 79
Port P4 Direction Register
Port P6 Register
PD4
P6
78, 79
78, 79
78, 79
Port P6 Direction Register
PD6
Pin Select Register 2
PINSR2
80
Port Mode Register
PMR
INTEN
INTF
KIEN
PUR0
PUR1
81
131
132
135
82
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
82
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B - 2
Address
Register
Symbol
TRACR
TRAIOC
Page
159
Address
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
Register
Symbol
Page
0100h Timer RA Control Register
0101h Timer RA I/O Control Register
159, 161, 164,
166, 168, 171
0102h Timer RA Mode Register
0103h Timer RA Prescaler Register
0104h Timer RA Register
TRAMR
TRAPRE
TRA
160
160
160
0105h
0106h LIN Control Register
0107h LIN Status Register
0108h Timer RB Control Register
0109h Timer RB One-Shot Control Register
010Ah Timer RB I/O Control Register
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
244
245
175
175
176, 178, 182,
185, 189
010Bh Timer RB Mode Register
010Ch Timer RB Prescaler Register
010Dh Timer RB Secondary Register
010Eh Timer RB Primary Register
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
TRBMR
TRBPRE
TRBSC
TRBPR
176
177
177
177
0118h Timer RE Second Data Register / Counter TRESEC
198, 206
198, 206
(2)
Data Register
0119h Timer RE Minute Data Register / Compare TREMIN
(2)
Data Register
(2)
011Ah
011Bh
011Ch
011Dh
011Eh
TREHR
199
199
200, 207
201, 207
202, 208
202
Timer RE Hour Data Registe
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
(2)
TREWK
TRECR1
TRECR2
TRECSR
(2)
(2)
(2)
Timer RE Count Source Select Register
011Fh Timer RE Real-Time Clock Precision Adjust TREOPR
Register
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
NOTES:
1. The blank regions are reserved. Do not access locations in these
regions.
2. This register is not implemented in the R8C/2J Group.
B - 3
Address
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
Register
Symbol
U2MR
U2BRG
U2TB
Page
228
228
229
Address
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Register
Symbol
Page
(2)
UART2 Transmit/Receive Mode Register
(2)
UART2 Bit Rate Register
(2)
UART2 Transmit Buffer Register
(2)
(2)
U2C0
U2C1
U2RB
229
230
230
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
(2)
01B3h Flash Memory Control Register 4
01B4h
01B5h Flash Memory Control Register 1
01B6h
FMR4
266
265
262
FMR1
FMR0
01B7h Flash Memory Control Register 0
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
NOTES:
1. The blank regions are reserved. Do not access locations in these
regions.
2. This register is not implemented in the R8C/2J Group.
B - 4
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
Register
Symbol
Page
Address
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
Register
Symbol
Page
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B - 5
Address
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
Register
Symbol
Page
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
Register
Symbol
Page
TRF
215
(2)
0299h
TRFCR2
TRFCR0
TRFCR1
TRFM0
216
216
217
215
Timer RF Control Register 2
029Ah Timer RF Control Register 0
029Bh Timer RF Control Register 1
029Ch Capture and Compare 0 Register
029Dh
029Eh Compare 1 Register
029Fh
TRFM1
215
NOTES:
1. The blank regions are reserved. Do not access locations in these
regions.
2. This register is not implemented in the R8C/2J Group.
B - 6
Address
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
Register
Symbol
Page
02FBh Pin Select Register 4
02FCh
02FDh
02FEh
PINSR4
46, 61, 80
217
02FFh Timer RF Output Control Register
TRFOUT
OFS
FFFFh Option Function Select Register
33, 144,
152, 260
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B - 7
R8C/2H Group, R8C/2J Group
RENESAS MCU
REJ09B0388-0100
Rev.1.00
Mar 28, 2008
1. Overview
1.1
Features
The R8C/2H Group and R8C/2J Group of single-chip MCUs incorporate the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
1.1.1
Applications
Electric power meters, electronic household appliances, office equipment, audio equipment, consumer
equipment, etc.
1.1.2
Specifications
Table 1.1 outlines the Specifications for R8C/2H Group and Table 1.2 outlines the Specifications for R8C/2J
Group.
Rev.1.00 Mar 28, 2008 Page 1 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
1.Overview
Table 1.1
Specifications for R8C/2H Group
Item
CPU
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V)
250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/2H Group.
• Power-on reset
Memory
ROM, RAM
Power Supply Voltage detection
Voltage
Detection
Comparator
circuit
• Voltage detection 3
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input is available
• Output-only: 1
I/O Ports
Clock
• CMOS I/O ports: 15, selectable pull-up resistor
• 2 circuits: On-chip oscillator (high-speed, low-speed)
Clock generation
circuits
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (low-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts
• External: 3 sources, Internal: 17 sources, Software: 4 sources
• Priority levels: 7 levels
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RE
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Serial
Interface
LIN Module
Flash Memory
UART0, UART2
Clock synchronous serial I/O/UART × 2
Hardware LIN: 1 (timer RA, UART0)
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
System clock = 8 MHz (VCC = 2.7 to 5.5 V)
Operating Frequency/Supply
Voltage
Current consumption
System clock = 4 MHz (VCC = 2.2 to 5.5 V)
5 mA (VCC = 5 V, system clock = 8 MHz)
23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on))
0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled)
-20 to 85°C (N version)
Operating Ambient Temperature
Package
(1)
-40 to 85°C (D version)
20-pin LSSOP
Package code: PLSP0020JB-A (previous code: 20P2F-A)
NOTE:
1. Specify the D version if D version functions are to be used.
Rev.1.00 Mar 28, 2008 Page 2 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
1.Overview
Table 1.2
Specifications for R8C/2J Group
Item
CPU
Function
Specification
Central processing R8C/Tiny series core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V)
250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.4 Product List for R8C/2J Group.
• Power-on reset
Memory
ROM, RAM
Power Supply Voltage detection
Voltage
Detection
Comparator
circuit
• Voltage detection 3
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input is available
I/O Ports
Clock
CMOS I/O ports: 12, selectable pull-up resistor
Clock generation
circuits
• 1 circuits: On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed on-chip oscillator, low-speed on-chip
oscillator), wait mode, stop mode
Interrupts
• External: 3 sources, Internal: 14 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer
Timer
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Timer RA
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RE
Timer RF
Not implemented
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Serial
Interface
LIN Module
Flash Memory
UART0
Clock synchronous serial I/O/UART × 1
Hardware LIN: 1 (timer RA, UART0)
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
System clock = 8 MHz (VCC = 2.7 to 5.5 V)
Operating Frequency/Supply
Voltage
Current consumption
System clock = 4 MHz (VCC = 2.2 to 5.5 V)
5 mA (VCC = 5 V, system clock = 8 MHz)
23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on))
0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled)
-20 to 85°C (N version)
Operating Ambient Temperature
Package
(1)
-40 to 85°C (D version)
20-pin LSSOP
Package code: PLSP0020JB-A (previous code: 20P2F-A)
NOTE:
1. Specify the D version if D version functions are to be used.
Rev.1.00 Mar 28, 2008 Page 3 of 341
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R8C/2H Group, R8C/2J Group
1.Overview
1.2
Product List
Table 1.3 lists Product List for R8C/2H Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2H Group. Table 1.4 lists Product List for R8C/2J Group, Figure 1.2 shows a Part Number, Memory Size, and
Package of R8C/2J Group.
Table 1.3
Product List for R8C/2H Group
Current of Mar. 2008
Part No.
ROM Capacity
4 Kbytes
8 Kbytes
4 Kbytes
8 Kbytes
RAM Capacity
256 bytes
384 bytes
256 bytes
384 bytes
Package Type
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Remarks
N version
R5F212H1SNSP
R5F212H2SNSP
R5F212H1SDSP
R5F212H2SDSP
D version
Part No. R 5 F 21 2H 1 S N SP
Package type:
SP: PLSP0020JB-A
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version (other no symbols)
ROM capacity
1: 4 KB
2: 8 KB
R8C/2H Group
R8C/Tiny Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/2H Group
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R8C/2H Group, R8C/2J Group
1.Overview
Table 1.4
Product List for R8C/2J Group
Current of Mar. 2008
Part No.
ROM Capacity
2 Kbytes
4 Kbytes
2 Kbytes
4 Kbytes
RAM Capacity
256 bytes
384 bytes
256 bytes
384 bytes
Package Type
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Remarks
N version
R5F212J0SNSP
R5F212J1SNSP
R5F212J0SDSP
R5F212J1SDSP
D version
Part No. R 5 F 21 2J 1 S N SP
Package type:
SP: PLSP0020JB-A
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
S: Low-voltage version (other no symbols)
ROM capacity
0: 2 KB
1: 4 KB
R8C/2J Group
R8C/Tiny Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductor
Figure 1.2
Part Number, Memory Size, and Package of R8C/2J Group
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R8C/2H Group, R8C/2J Group
1.Overview
1.3
Block Diagram
Figure 1.3 shows a Block Diagram of R8C/2H Group and Figure 1.4 shows a Block Diagram of R8C/2J Group.
8
2
1
2
3
Port P1
I/O ports
Peripheral functions
Port P3
Port P4
Port P6
UART or
System clock
clock synchronous serial I/O
generation circuit
(8 bits × 2 channels)
Timers
High-speed on-chip oscillator
Low-Speed on-chip oscillator
XCIN-XCOUT
Timer RA (8 bits)
LIN module
(1 channel)
Timer RB (8 bits)
Timer RE (8 bits)
Timer RF (16 bits)
Voltage detection circuit
(3 circuits)
Comparator
(2 circuits)
Watchdog timer
(15 bits)
Memory
R8C/Tiny Series CPU core
ROM(1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM(2)
A0
A1
FB
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.3
Block Diagram of R8C/2H Group
Rev.1.00 Mar 28, 2008 Page 6 of 341
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1.Overview
8
1
2
1
Port P1
I/O ports
Port P3
Port P4
Port P6
Peripheral functions
UART or
System clock
clock synchronous serial I/O
generation circuit
(8 bits × 1 channels)
Timers
High-speed on-chip oscillator
Low-Speed on-chip oscillator
Timer RA (8 bits)
Timer RB (8 bits)
Timer RF (16 bits)
LIN module
(1 channel)
Voltage detection circuit
(3 circuits)
Comparator
(2 circuits)
Watchdog timer
(15 bits)
Memory
R8C/Tiny Series CPU core
ROM(1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM(2)
A0
A1
FB
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.4
Block Diagram of R8C/2J Group
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1.Overview
1.4
Pin Assignment
Figure 1.5 shows Pin Assignment (Top View) of R8C/2H Group. Table 1.5 outlines the Pin Name Information by
Pin Number of R8C/2H Group.
Figure 1.6 shows Pin Assignment (Top View) of R8C/2J Group. Table 1.6 outlines the Pin Name Information by
Pin Number of R8C/2J Group.
P6_4/RXD2
20
19
18
17
16
15
14
13
12
11
P6_3/TXD2
1
P3_3/TRFO10/TRFI
P1_0/KI0/TRFO00/VCMP1
P1_1/KI1/TRFO01/VCMP2
P6_5/CLK2/TREO
2
P3_7/TRAO/TRFO11
RESET
3
XCOUT/(P4_4)(1)
4
5
VSS
XCIN/(P4_3)(1)
VCC
P1_2/KI2/TRFO02/CVREF
P1_3/KI3/VCOUT1/TRBO
P1_4/TXD0
6
7
8
MODE
P4_5/INT0
P1_5/RXD0/(TRAIO)/(INT1)(1)
9
P1_7/TRAIO/INT1
P1_6/CLK0/VCOUT2
10
NOTES:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.5
Pin Assignment (Top View) of R8C/2H Group
Rev.1.00 Mar 28, 2008 Page 8 of 341
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1.Overview
Table 1.5
Pin Name Information by Pin Number of R8C/2H Group
I/O Pin Functions for of Peripheral Modules
Pin
Control Pin
Port
Number
Interrupt
Timer
Serial Interface
RXD2
Comparator
1
2
P6_4
P3_7
TRAO/TRFO11
3
4
5
RESET
XCOUT
VSS
(P4_4)
(P4_3)
6
XCIN
7
VCC
8
MODE
9
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P6_5
P1_1
P1_0
P3_3
P6_3
INT0
INT1
10
11
12
13
14
15
16
17
18
19
20
TRAIO
CLK0
RXD0
TXD0
VCOUT2
(1)
(1)
(TRAIO)
(INT1)
TRBO
TRFO02
TREO
VCOUT1
CVREF
KI3
KI2
CLK2
TXD2
TRFO01
TRFO00
TRFO10/TRFI
VCMP2
VCMP1
KI1
KI0
NOTE:
1. Can be assigned to the pin in parentheses by a program.
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R8C/2H Group, R8C/2J Group
1.Overview
NC
20
19
18
17
16
15
14
13
12
11
NC
1
P3_3/TRFO10/TRFI
2
P3_7/TRAO/TRFO11
P1_0/KI0/TRFO00/VCMP1
P1_1/KI1/TRFO01/VCMP2
P6_5
3
RESET
NC
4
5
VSS
NC
P1_2/KI2/TRFO02/CVREF
P1_3/KI3/VCOUT1/TRBO
P1_4/TXD0
6
7
VCC
8
MODE
P4_5/INT0
P1_5/RXD0/(TRAIO)/(INT1)(1)
9
P1_7/TRAIO/INT1
P1_6/CLK0/VCOUT2
10
NOTES:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
NC…Non-Connection
Figure 1.6
Pin Assignment (Top View) of R8C/2J Group
Rev.1.00 Mar 28, 2008 Page 10 of 341
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1.Overview
Table 1.6
Pin Name Information by Pin Number of R8C/2J Group
I/O Pin Functions for of Peripheral Modules
Pin
Number
Control Pin
Port
Interrupt
Timer
Serial Interface
Comparator
(2)
1
2
NC
P3_7
TRAO/TRFO11
3
RESET
(2)
4
NC
5
6
VSS
(2)
NC
7
VCC
8
MODE
9
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P6_5
P1_1
P1_0
P3_3
INT0
INT1
10
11
12
13
14
15
16
17
18
19
20
TRAIO
CLK0
RXD0
TXD0
VCOUT2
(1)
(1)
(TRAIO)
(INT1)
TRBO
TRFO02
VCOUT1
CVREF
KI3
KI2
TRFO01
TRFO00
VCMP2
VCMP1
KI1
KI0
TRFO10/TRFI
(2)
NC
NOTES:
1. Can be assigned to the pin in parentheses by a program.
2. NC(Non-Connection)
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1.Overview
1.5
Pin Functions
Table 1.7 lists Pin Functions of R8C/2H Group and Table 1.8 lists Pin Functions of R8C/2J Group.
Table 1.7
Type
Power supply input VCC, VSS
Pin Functions of R8C/2H Group
Symbol
I/O Type
Description
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
–
I
I
Reset input
MODE
XCIN clock input
RESET
MODE
XCIN
I
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
(1)
XCIN clock output XCOUT
O
pins. To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
INT interrupt input INT0, INT1
I
I
INT interrupt input pins
Key input interrupt input pins
Key input interrupt
KI0 to KI3
TRAIO
TRAO
TRBO
TREO
TRFI
Timer RA
I/O
O
O
O
I
Timer RA I/O pin
Timer RA output pin
Timer RB output pin
Divided clock output pin
Timer RF input pin
Timer RF output pins
Timer RB
Timer RE
Timer RF
TRFO00 to TRFO02,
TRFO10 to TRFO11
O
Serial interface
Comparator
I/O port
CLK0, CLK2
RXD0, RXD2
TXD0, TXD2
VCMP1, VCMP2
CVREF
I/O
I
O
I
Clock I/O pin
Serial data input pin
Serial data output pin
Analog input pins to comparator
Reference voltage input pin to comparator
Comparator output pins
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
I
VCOUT1, VCOUT2
O
I/O
P1_0 to P1_7,
P3_3, P3_7,
P4_3, P4_5,
P6_3 to P6_5
Any port set to input can be set to use a pull-up resistor or not
by a program.
Output port
P4_4
O
Output-only port
I: Input
NOTE:
O: Output
I/O: Input and output
1. Refer to the oscillator manufacturer for oscillation characteristics.
Rev.1.00 Mar 28, 2008 Page 12 of 341
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1.Overview
Table 1.8
Type
Power supply input VCC, VSS
Pin Functions of R8C/2J Group
Symbol
I/O Type
Description
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
–
I
I
Reset input
MODE
RESET
MODE
INT interrupt input INT0, INT1
I
I
INT interrupt input pins
Key input interrupt input pins
Key input interrupt
KI0 to KI3
TRAIO
TRAO
TRBO
TRFI
Timer RA
I/O
O
O
I
Timer RA I/O pin
Timer RA output pin
Timer RB output pin
Timer RF input pin
Timer RF output pins
Timer RB
Timer RF
TRFO00 to TRFO02,
TRFO10 to TRFO11
O
Serial interface
Comparator
I/O port
CLK0
RXD0
TXD0
VCMP1, VCMP2
CVREF
I/O
I
O
I
Clock I/O pin
Serial data input pin
Serial data output pin
Analog input pins to comparator
Reference voltage input pin to comparator
Comparator output pins
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
I
VCOUT1, VCOUT2
O
I/O
P1_0 to P1_7,
P3_3, P3_7,
P4_5, P6_5
Any port set to input can be set to use a pull-up resistor or not
by a program.
I: Input
O: Output
I/O: Input and output
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2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers(1)
R3
A0
A1
FB
Address registers(1)
Frame base register(1)
b19
b15
b0
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
PC
b15
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.1.00 Mar 28, 2008 Page 15 of 341
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2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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3.Memory
3. Memory
Figure 3.1 is a Memory Map of R8C/2H Group and Figure 3.2 is a Memory Map of R8C/2J Group. The R8C/2H group
has 1 Mbyte of address space from addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 4-Kbyte internal
ROM area is allocated addresses 0F000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 256-bytes internal
RAM area is allocated addresses 00400h to 004FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers
are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot
be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/voltage monitor/comparator
0YYYYh
0FFFFh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F212H1SNSP, R5F212H1SDSP
R5F212H2SNSP, R5F212H2SDSP
4 Kbytes
8 Kbytes
0F000h
0E000h
256 bytes
384 bytes
004FFh
0057Fh
Figure 3.1
Memory Map of R8C/2H Group
Rev.1.00 Mar 28, 2008 Page 17 of 341
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3.Memory
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/voltage monitor/comparator
0YYYYh
0FFFFh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F212J0SNSP, R5F212J0SDSP
R5F212J1SNSP, R5F212J1SDSP
2 Kbytes
4 Kbytes
0F800h
0F000h
256 bytes
384 bytes
004FFh
0057Fh
Figure 3.2
Memory Map of R8C/2J Group
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4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01011000b
00h
Protect Register
PRCR
00h
System Clock Select Register(3)
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
00000100b
XXh
WDTR
WDTS
WDC
XXh
00X11111b
00h
RMAD0
00h
00h
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
00h
RMAD1
00h
00h
00h
Count Source Protection Mode Register
CSPR
00h
10000000b(2)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
HRA0
HRA1
HRA2
00h
When Shipping
00h
Clock Prescaler Reset Flag(3)
High-Speed On-Chip Oscillator Control Register 4
CPSRF
FRA4
00h
When Shipping
High-Speed On-Chip Oscillator Control Register 6
FRA6
When Shipping
BGR Trimming Auxiliary Register A
BGR Trimming Auxiliary Register B
BGRTRMA
BGRTRMB
When Shipping
When Shipping
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The CSPROINI bit in the OFS register is set to 0.
3. This register is not implemented in the R8C/2J Group.
Rev.1.00 Mar 28, 2008 Page 19 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
0030h
0031h
0032h
Register
Symbol
After reset
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
00h(3)
00100000b(4)
0033h
0034h
0035h
0036h
0037h
0038h
Voltage Monitor 1 Circuit Control Register(5)
Voltage Monitor 2 Circuit Control Register(5)
Voltage Monitor 0 Circuit Control Register(2)
VW1C
VW2C
VW0C
00001010b
00000010b
1000X010b(3)
1100X011b(4)
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
Voltage Detection Circuit External Input Control Register
Comparator Mode Register
VCAB
00h
ALCMR
VCAC
00h
Voltage Monitor Circuit Edge Select Register
BGR Control Register
00h
00h
BGRCR
BGRTRM
BGR Trimming Register
When Shipping
Comparator 1 Interrupt Control Register
Comparator 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
Timer RE Interrupt Control Register(6)
UART2 Transmit Interrupt Control Register(6)
UART2 Receive Interrupt Control Register(6)
Key Input Interrupt Control Register
TREIC
S2TIC
S2RIC
KUPIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Compare 1 Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
CMP1IC
S0TIC
S0RIC
XXXXX000b
XXXXX000b
XXXXX000b
Timer RA Interrupt Control Register
TRAIC
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
TRBIC
INT1IC
XXXXX000b
XX00X000b
Timer RF Interrupt Control Register
Compare 0 Interrupt Control Register
INT0 Interrupt Control Register
TRFIC
CMP0IC
INT0IC
XXXXX000b
XXXXX000b
XX00X000b
Capture Interrupt Control Register
CAPIC
XXXXX000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
6. This register is not implemented in the R8C/2J Group.
Rev.1.00 Mar 28, 2008 Page 20 of 341
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R8C/2H Group, R8C/2J Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
Register
Symbol
After reset
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
00h
XXh
XXh
XXh
U0BRG
U0TB
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00000010b
XXh
XXh
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 21 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
Register
Symbol
After reset
Port P1 Register
P1
00h
00h
00h
Port P1 Direction Register
Port P3 Register
PD1
P3
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
00h
Port P4 Direction Register
Port P6 Register
PD4
P6
00h
00h
00h
Port P6 Direction Register
PD6
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 22 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.5
SFR Information (5)
Address
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
Register
Symbol
After reset
Pin Select Register 2
PINSR2
00h
Port Mode Register
PMR
00h
00h
00h
00h
00h
00h
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
INTEN
INTF
KIEN
PUR0
PUR1
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
00h
00h
00h
FFh
FFh
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
LINCR
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
Timer RE Second Data Register / Counter Data Register(2)
Timer RE Minute Data Register / Compare Data Register(2)
Timer RE Hour Data Register(2)
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
TREOPR
XXh
XXh
X0XXXXXXb
X0000XXXb
XXX0X0X0b
00XXXXXXb
00001000b
00h
Timer RE Day of Week Data Register(2)
Timer RE Control Register 1(2)
Timer RE Control Register 2(2)
Timer RE Count Source Select Register(2)
Timer RE Real-Time Clock Precision Adjust Register(2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions
2. This register is not implemented in the R8C/2J Group.
Rev.1.00 Mar 28, 2008 Page 23 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.6
SFR Information (6)
Address
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
Register
Symbol
After reset
UART2 Transmit/Receive Mode Register(2)
UART2 Bit Rate Register(2)
U2MR
00h
XXh
XXh
XXh
U2BRG
U2TB
UART2 Transmit Buffer Register(2)
UART2 Transmit/Receive Control Register 0(2)
UART2 Transmit/Receive Control Register 1(2)
UART2 Receive Buffer Register(2)
U2C0
U2C1
U2RB
00001000b
00000010b
XXh
XXh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. This register is not implemented in the R8C/2J Group.
Rev.1.00 Mar 28, 2008 Page 24 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.7
SFR Information (7)
Address
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
Register
Symbol
After reset
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 25 of 341
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R8C/2H Group, R8C/2J Group
4. Special Function Registers (SFRs)
(1)
Table 4.8
SFR Information (8)
Address
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
Register
Symbol
After reset
Flash Memory Control Register 4
Flash Memory Control Register 1
Flash Memory Control Register 0
FMR4
FMR1
FMR0
01000000b
1000000Xb
00000001b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 26 of 341
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4. Special Function Registers (SFRs)
(1)
Table 4.9
SFR Information (9)
Address
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
Register
Symbol
After reset
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 27 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
4. Special Function Registers (SFRs)
(1)
Table 4.10
SFR Information (10)
Address
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
Register
Symbol
After reset
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.00 Mar 28, 2008 Page 28 of 341
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R8C/2H Group, R8C/2J Group
4. Special Function Registers (SFRs)
(1)
Table 4.11
SFR Information (11)
Address
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
Register
Symbol
After reset
Timer RF Register
TRF
00h
00h
Timer RF Control Register 2(4)
Timer RF Control Register 0
Timer RF Control Register 1
Capture and Compare 0 Register
TRFCR2
TRFCR0
TRFCR1
TRFM0
00h
00h
00h
0000h(2)
FFFFh(3)
FFh
Compare 1 Register
TRFM1
FFh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
4. This register is not implemented in the R8C/2J Group.
Rev.1.00 Mar 28, 2008 Page 29 of 341
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R8C/2H Group, R8C/2J Group
4. Special Function Registers (SFRs)
(1)
Table 4.12
SFR Information (12)
Address
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
Register
Symbol
After reset
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
Pin Select Register 4
PINSR4
00h
00h
Timer RF Output Control Register
Option Function Select Register
TRFOUT
OFS
FFFFh
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.1.00 Mar 28, 2008 Page 30 of 341
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5.Resets
5. Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset,
voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit.
Table 5.1
Reset Names and Sources
Reset Name
Source
Hardware reset
Power-on reset
Input voltage of RESET pin is held “L”
VCC rises
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Watchdog timer reset
Software reset
VCC falls (monitor voltage: Vdet0)
VCC falls (monitor voltage: Vdet1)
VCC falls (monitor voltage: Vdet2)
Underflow of watchdog timer
Write 1 to PM03 bit in PM0 register
Hardware reset
SFRs
RESET
Bits VCA25,
VW0C0, and
VW0C6
SFRs
Bits VCA25,
VW0C0, and
VW0C6
Power-on reset
Power-on reset
VCC
circuit
Voltage monitor 0 reset
Voltage monitor 1 reset
SFRs
Voltage
detection
circuit
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Voltage monitor 2
reset
Watchdog timer
reset
Watchdog
timer
Pin, CPU, and
SFR bits other than
those listed above(1)
CPU
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
NOTE:
1. The following registers and bits are not reset.
• Registers TRESEC, TREMIN, TREWK, and TRECR2
• Bits PM, H12_H24, and TSTART in the TRECR1 register
Figure 5.1
Block Diagram of Reset Circuit
Rev.1.00 Mar 28, 2008 Page 31 of 341
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5.Resets
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Table 5.2
Pin Functions while RESET Pin Level is “L”
Pin Name Pin Functions
P1, P3_3, P3_7
Input port
Input port
Output port
Input port
(1)
P4_3, P4_5
(1)
P4_4
(1)
P6_3 to P6_5
NOTE:
1. Ports P4_3, P4_4, P6_3, and P6_4 are not available in the R8C/2J Group.
b15
b0
0000h
0000h
0000h
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
0000h
0000h
0000h
0000h
Address register(A0)
Address register(A1)
Frame base register(FB)
b19
b0
Interrupt table register(INTB)
Program counter(PC)
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
b0
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
0000h
0000h
0000h
b15
b0
b0
Flag register(FLG)
0000h
b15
b8 b7
IPL
U
I O B S Z D C
Figure 5.2
fOCO-S
CPU Register Status after Reset
RESET pin
10 cycles or more are needed(1)
fOCO-S clock × 32 cycles(2)
Internal reset
signal
Start time of flash memory
CPU clock × 28 cycles
(CPU clock × 14 cycles)
CPU clock
0FFFCh
0FFFEh
Address
(internal address
signal)
Content of reset vector
0FFFDh
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Figure 5.3
Reset Sequence
Rev.1.00 Mar 28, 2008 Page 32 of 341
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5.Resets
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
Address
0FFFFh
Bit Name
When Shipping
FFh(3)
Function
RW
RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
WDTON
—
Reserved bit
Set to 1.
RW
RW
RW
RW
(b1)
ROM code protect
disabled bit
ROM code protect bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
ROMCR
ROMCP1
—
(b4)
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
LVD0ON
RW
1 : Voltage monitor 0 reset disabled after hardw are
reset
—
Reserved bit
Set to 1.
RW
RW
(b6)
Count source protect
mode after reset select 1 : Count source protect mode disabled after reset
bit
0 : Count source protect mode enabled after reset
CSPROINI
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 5.4
OFS Register
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5.Resets
5.1
Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1
When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs.
(3) Apply “H” to the RESET pin.
5.1.2
Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 22. Electrical
Characteristics).
(4) Wait for 10 µs.
(5) Apply “H” to the RESET pin.
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5.Resets
VCC
2.2 V
VCC
0 V
RESET
RESET
0 V
0.2 VCC or below
td(P-R) + 10µs or more
NOTE:
1. Refer to 22. Electrical Characteristics.
Figure 5.5
Example of Hardware Reset Circuit and Operation
5 V
Supply voltage
detection circuit
VCC
2.2 V
RESET
VCC
0 V
5 V
RESET
0 V
td(P-R) + 10µs or more
Example when
VCC = 5 V
NOTE:
1. Refer to 22. Electrical Characteristics.
Figure 5.6
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
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5.Resets
5.2
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
VCC
4.7 kΩ
(reference)
RESET
(3)
Vdet0
(3)
Vdet0
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
1
× 32
× 32
fOCO-S
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 22. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.7
Example of Power-On Reset Circuit and Operation
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5.Resets
5.3
Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware reset.
Setting the LVD0ON bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4
Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5
Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
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5.Resets
5.6
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.
Refer to 16. Watchdog Timer for details of the watchdog timer.
5.7
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
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6. Voltage Detection Circuit
6. Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC
input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset,
voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator 1 and
comparator 2. Either voltage monitor 1 and voltage monitor 2 or comparator 1 and comparator 2 can be selected.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures
6.5 to 6.10 show the Associated Registers.
Table 6.1
Specifications of Voltage Detection Circuit
Item Voltage Detection 0 Voltage Detection 1
VCC Monitor Voltage to monitor Vdet0 Vdet1
Voltage Detection 2
Vdet2
Detection target
Whether passing
Passing through Vdet1 by Passing through Vdet2 by
through Vdet0 by falling rising or falling
rising or falling
Monitor
None
VW1C3 bit in VW1C
register
VCA13 bit in VCA1
register
Whether VCC is higher or Whether VCC is higher or
lower than Vdet1
Voltage monitor 0 reset Voltage monitor 1 reset
lower than Vdet2
Voltage monitor 2 reset
Reset at Vdet2 > VCC;
restart CPU operation
after a specified time
Process
Reset
When Voltage
is Detected
Reset at Vdet0 > VCC; Reset at Vdet1 > VCC;
restart CPU operation at restart CPU operation
VCC > Vdet0
None
after a specified time
Interrupt
Voltage monitor 1 interrupt Voltage monitor 2 interrupt
Interrupt request at both Interrupt request at both
or either of Vdet1 > VCC or either of Vdet2 > VCC
and VCC > Vdet1
Available
and VCC > Vdet2
Available
Digital Filter
Switch
enabled/disabled
Available
Sampling time
(Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S)
(Divide-by-n of fOCO-S)
× 2
n: 1, 2, 4, and 8
× 4
× 2
n: 1, 2, 4, and 8
n: 1, 2, 4, and 8
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6. Voltage Detection Circuit
Shared with comparator
VCC
VCA27
VCAB6 = 1
VCMP2
Voltage detection 2
signal
Noise
filter
+
-
VCAB6 = 0
≥ Vdet2
VCA1 register
b3
VCA13 bit
VCA26
VCAB5 = 1
VCMP1
Voltage detection 1
signal
Noise
filter
+
-
VCAB5 = 0
≥ Vdet1
VW1C register
b3
VW1C3 bit
VCA25
Voltage detection 0 signal
+
-
Internal
reference
voltage
≥ Vdet0
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW1C3: Bit in VW1C register
VCAB5, VCAB6: Bits in VCAB register
Figure 6.1
Block Diagram of Voltage Detection Circuit
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
Voltage detection 0 circuit
= 10b
= 11b
fOCO-S
1/2
1/2
1/2
VCA25
VW0C1
VCC
+
-
Digital
filter
Internal
reference
voltage
Voltage
detection 0
signal
Voltage detection 0
signal is held “H” when
VCA25 bit is set to 0
(disabled)
Voltage monitor 0
reset signal
VW0C1
VW0C0
VW0C6
VW0C7
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register
VCA25: Bit in VCA2 register
Figure 6.2
Block Diagram of Voltage Monitor 0 Reset Generation Circuit
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6. Voltage Detection Circuit
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0
= 00b
= 01b
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
= 10b
= 11b
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
fOCO-S
1/2
1/2
1/2
Voltage detection 1 circuit
VCA26
VW1C3
Watchdog
timer interrupt
signal
VCAB5 = 1
VCMP1
VW1C1 = 0
Digital
filter
+
VCC
Noise filter
VW1C2
VCAB5 = 0
Voltage
detection
1 signal
-
Edge
Selection
circuit
VW1C1 = 1
Internal reference
(Filter width: 200 ns)
voltage
Voltage monitor 1
interrupt signal
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Non-maskable
interrupt signal
Comparator
interrupt signal
VW1C0
VW1C6
Voltage monitor 1
reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
VCAB5: Bit in VCAB register
Figure 6.3
Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Voltage monitor 2 interrupt/reset generation circuit
VW2F1 to VW2F0
= 00b
= 01b
= 10b
VW2C2 bit is set to 0 (not detected) by
Voltage detection 2 circuit
writing 0 by a program.
= 11b
fOCO-S
VCA13
1/2
1/2
1/2
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
VCA27
Watchdog
timer interrupt
signal
VCAB6 = 1
VCMP2
VW2C1 = 0
VW2C1 = 1
Digital
filter
+
-
VCC
Noise filter
VW2C2
VCAB6 = 0
Voltage
detection
2 signal
Edge
Selection
circuit
Internal reference
voltage
(Filter width: 200 ns)
Voltage monitor 2
interrupt signal
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Non-maskable
interrupt signal
Comparator
interrupt signal
Watchdog timer block
VW2C3
Watchdog timer
underflow signal
VW2C0
This bit is set to 0 (not detected) by writing
by a program.
0
VW2C6
Voltage monitor 2
reset signal
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VCAB6: Bit in VCAB register
Figure 6.4
Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
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6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
Address
0031h
Bit Name
After Reset(2)
00001000b
Function
VCA1
Bit Symbol
—
RW
RW
Reserved bits
Set to 0.
(b2-b0)
Voltage detection 2 signal monitor
flag(1)
0 : VCC < Vdet2
1 : VCC Vdet2 or voltage detection 2
≥
VCA13
RO
circuit disabled
Set to 0.
—
(b7-b4)
Reserved bits
RW
NOTES:
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
≥
2. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
Address
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
Function
0 : Low consumption disabled
1 : Low consumption enabled(7)
: 00100000b
VCA2
0032h
Bit Name
Bit Symbol
RW
RW
Internal pow er low
VCA20
consumption enable bit(6)
—
Reserved bits
Set to 0.
RW
RW
RW
RW
(b4-b1)
Voltage detection 0 enable 0 : Voltage detection 0 circuit disabled
bit(2)
1 : Voltage detection 0 circuit enabled
Voltage detection 1 enable 0 : Voltage detection 1 circuit disabled
bit(3)
1 : Voltage detection 1 circuit enabled
Voltage detection 2 enable 0 : Voltage detection 2 circuit disabled
bit(4)
1 : Voltage detection 2 circuit enabled
VCA25
VCA26
VCA27
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in
Figure
.
11.12 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
Figure 6.5
Registers VCA1 and VCA2
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6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset(2)
0
Symbol
Address
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 1000X010b
: 1100X011b
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset
VW0C
Bit Symbol
0038h
Bit Name
Function
RW
RW
Voltage monitor 0 reset
0 : Disable
1 : Enable
VW0C0
VW0C1
VW0C2
enable bit(3)
Voltage monitor 0 digital filter 0 : Digital filter enabled mode
disable mode select bit
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
Reserved bit
Set to 0.
RW
RO
—
(b3)
Reserved bit
When read, the content is undefined.
Sampling clock select bits
b5 b4
VW0F0
VW0F1
RW
RW
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
Voltage monitor 0 circuit
mode select bit
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1.
VW0C6
VW0C7
RW
RW
Voltage monitor 0 reset
When the VW0C1 bit is set to 1 (digital filter
generation condition select disabled mode), set to 1.
bit(4)
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW0C register.
2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled).
Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
To set VW0C0 bit to 1 (enable), follow the procedure show n in
Table 6.2 Procedure for Setting Bits
.
Associated with Voltage Monitor 0 Reset
4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Figure 6.6
VW0C Register
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6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW1C
Bit Symbol
Address
After Reset(8)
00001010b
Function
0036h
Bit Name
RW
RW
Voltage monitor 1 interrupt/reset
0 : Disable
1 : Enable
VW1C0
enable bit(6)
Voltage monitor 1 digital filter
disable mode select bit(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
VW1C1
RW
Voltage change detection
flag(3, 4, 8)
0 : Not detected
VW1C2
VW1C3
RW
RO
1 : Vdet1 crossing detected
Voltage detection 1 signal monitor 0 : VCC < Vdet1
flag(3, 8)
1 : VCC Vdet1 or voltage detection 1
≥
circuit disabled
Sampling clock select bits
b5 b4
VW1F0
VW1F1
RW
RW
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode
0 : When VCC reaches Vdet1 or above
VW1C6
VW1C7
RW
RW
Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9) 1 : When VCC reaches Vdet1 or below
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW1C register.
When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the
VW1C register.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/reset enabled).
6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
To set VW1C0 bit to 1 (enable), follow the procedure show n in
Table 6.3 Procedure for Setting Bits
.
Associated with Voltage Monitor 1 Interrupt and Reset
7. The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Figure 6.7
VW1C Register
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6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW2C
Bit Symbol
Address
After Reset(8)
00000010b
Function
0037h
Bit Name
Voltage monitor 2 interrupt/reset
RW
RW
0 : Disable
1 : Enable
VW2C0
VW2C1
enable bit(6)
Voltage monitor 2 digital filter
disable mode select bit(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
Voltage change detection
flag(3, 4, 8)
WDT detection flag(4, 8)
0 : Not detected
VW2C2
VW2C3
RW
RW
1 : Vdet2 crossing detected
0 : Not detected
1 : Detected
Sampling clock select bits
b5 b4
VW2F0
VW2F1
RW
RW
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
Voltage monitor 2 circuit mode
select bit(5)
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode
0 : When VCC reaches Vdet2 or above
VW2C6
VW2C7
RW
RW
Voltage monitor 2 interrupt/reset
generation condition select bit(7, 9) 1 : When VCC reaches Vdet2 or below
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW2C register.
When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the
VW2C register.
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/reset enabled).
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
To set VW2C0 bit to 1 (enable), follow the procedure show n in
Table 6.4 Procedure for Setting Bits
.
Associated with Voltage Monitor 2 Interrupt and Reset
7. The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2
or below ). (Do not set to 0.)
Figure 6.8
VW2C Register
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6. Voltage Detection Circuit
Voltage Monitor Circuit Edge Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
003Dh
00h
VCAC
Bit Symbol
—
Bit Name
Function
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b0)
Voltage monitor 1 circuit edge
0 : One edge
VCAC1
VCAC2
RW
RW
—
select bit(1)
1 : Both edges
Voltage monitor 2 circuit edge
select bit(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : One edge
1 : Both edges
—
(b7-b3)
NOTES:
1. The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
2. The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
Figure 6.9
VCAC Register
Pin Select Register 4 (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
Address
02FBh
After Reset
00h
Function
PINSR4
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
RW
—
(b6-b2)
TREO pin select 2 bit(2)
0 : Disabled
1 : Enabled
TREOSEL2
NOTES:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
2. Set the TREOSEL2 bit to 1 (enabled) before using timer RE.
Pin Select Register 4 (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
PINSR4
Address
02FBh
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
—
—
(b6-b2)
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
Figure 6.10
PINSR4 Register
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6. Voltage Detection Circuit
6.1
6.1.1
VCC Input Voltage
Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2
Monitoring Vdet1
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed
(refer to 22. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.
6.1.3
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed
(refer to 22. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
Rev.1.00 Mar 28, 2008 Page 47 of 341
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6. Voltage Detection Circuit
6.2
Voltage Monitor 0 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.11 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C register to 1 (digital filter disabled).
Table 6.2
Step
Procedure for Setting Bits Associated with Voltage Monitor 0 Reset
When Using Digital Filter
When Not Using Digital Filter
1
2
Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to
3
by the VW0F0 to VW0F1 bits in the VW0C 1
register
Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to
(1)
4
0 (digital filter enabled)
1 (digital filter disabled)
(1)
Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
Set the VW0C2 bit in the VW0C register to 0
5
6
7
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of
the digital filter
−
8
9
− (No wait time required)
Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
NOTE:
1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet0
1
× 32
Sampling clock of
fOCO-S
digital filter × 4 cycles
When the VW0C1 bit is set
to 0 (digital filter enabled)
Internal reset signal
Internal reset signal
1
× 32
fOCO-S
When the VW0C1 bit is set
to 1 (digital filter disabled)
and the VW0C7 bit is set
to 1
VW0C1 and VW0C7: Bits in VW0C register
The above applies under the following conditions.
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.11
Example of Voltage Monitor 0 Reset Operation
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6. Voltage Detection Circuit
6.3
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.12
shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
Table 6.3
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 1 Voltage Monitor 1
Interrupt Reset
Step
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
1
2
3
Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2)
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW1C1 bit in the VW1C register to 1
by the VW1F0 to VW1F1 bits in the VW1C
(digital filter disabled)
4
register
Set the VW1C1 bit in the VW1C register to 0 −
(digital filter enabled)
(2)
5
Select the timing of the interrupt and reset
request by the VCAC1 bit in the VCAC
register and the VW1C7 bit in the VW1C
Select the timing of the interrupt and reset
request by the VCAC1 bit in the VCAC
register and the VW1C7 bit in the VW1C
6
(1)
(1)
register
register
Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in
the VW1C register to the VW1C register to the VW1C register to the VW1C register to
0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1
7
interrupt mode)
reset mode)
interrupt mode)
reset mode)
8
9
Set the VW1C2 bit in the VW1C register to 0 (Vdet1 crossing is not detected)
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
Wait for 2 cycles of the sampling clock of the − (No wait time required)
digital filter
10
11
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction).
Rev.1.00 Mar 28, 2008 Page 49 of 341
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6. Voltage Detection Circuit
VCC
Vdet1
2.2 V(1)
1
VW1C3 bit
0
2 cycles of sampling clock of
digital filter
2 cycles of sampling clock of
digital filter
1
0
VW1C2 bit
Set to 0 by a program
When the VW1C1 bit is set to 0
(digital filter enabled) and the
VCAC1 bit is set to 1 (both edges)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
Set to 0 by a program
1
0
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by a program
1
0
VW1C2 bit
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
Set to 0 by a program
1
0
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
When the VW1C1 bit is set to 1
(digital filter disabled) and the
VCAC1 bit is set to 1 (both edges)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
Set to 0 by a program
1
0
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by a program
1
0
VW1C2 bit
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.12
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
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R8C/2H Group, R8C/2J Group
6. Voltage Detection Circuit
6.4
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.13
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Table 6.4
Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 2 Voltage Monitor 2
Interrupt Reset
Step
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
1
2
3
Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2)
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW2C1 bit in the VW2C register to 1
4
by the VW2F0 to VW2F1 bits in the VW2C
register
(digital filter disabled)
(2)
Set the VW2C1 bit in the VW2C register to 0 −
(digital filter enabled)
5
6
7
Select the timing of the interrupt and reset
request by the VCAC2 bit in the VCAC
register and the VW2C7 bit in the VW2C
Select the timing of the interrupt and reset
request by the VCAC2 bit in the VCAC
register and the VW2C7 bit in the VW2C
(1)
(1)
register
register
Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in
the VW2C register to the VW2C register to the VW2C register to the VW2C register to
0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2
interrupt mode)
reset mode)
interrupt mode)
reset mode)
8
9
Set the VW2C2 bit in the VW2C register to 0 (Vdet2 crossing is not detected)
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
Wait for 2 cycles of the sampling clock of the − (No wait time required)
digital filter
10
11
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction).
Rev.1.00 Mar 28, 2008 Page 51 of 341
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6. Voltage Detection Circuit
VCC
Vdet2
2.2 V(1)
1
VCA13 bit
0
2 cycles of sampling clock of
digital filter
2 cycles of sampling clock of
digital filter
1
0
VW2C2 bit
Set to 0 by a program
When the VW2C1 bit is set to 0
(digital filter enabled) and the
VCAC2 bit is set to 1 (both edges)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
Set to 0 by a program
1
0
When the VW2C1 bit is set to 0
(digital filter enabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 0 (when
VCC reaches Vdet2 or above)
VW2C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by a program
1
0
VW2C2 bit
When the VW2C1 bit is set to 0
(digital filter enabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 1
(when VCC reaches Vdet2 or
below)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
Set to 0 by a program
1
0
VW2C2 bit
When the VW2C1 bit is set to 1
(digital filter disabled) and the
VCAC2 bit is set to 1 (both edges)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
Set to 0 by a program
1
0
When the VW2C1 bit is set to 1
(digital filter disabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 0
(when VCC reaches Vdet2 or
above)
VW2C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by a program
1
0
VW2C2 bit
When the VW2C1 bit is set to 1
(digital filter disabled), and the
VCAC2 bit is set to 0 (one edge),
and the VW2C7 bit is set to 1
(when VCC reaches Vdet2 or
below)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.13
Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Rev.1.00 Mar 28, 2008 Page 52 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
7. Comparator
The comparators compare a reference input voltage and an analog input voltage. Comparator 1 and comparator 2 are
independent of each other. Note that comparator 1 and comparator 2 share the voltage detection circuit with voltage
monitor 1 and voltage monitor 2. Either comparator 1 and comparator 2 or voltage monitor 1 and voltage monitor 2 can
be selected to use the voltage detection circuit.
7.1
Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
also can be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF
pin can be selected as the reference input voltage. The comparator 1 interrupt and comparator 2 interrupt also can
be used.
Table 7.1 lists the Specifications of Comparator, Figure 7.1 shows the Block Diagram of Comparator, and Table 7.2
lists the Pin Configuration of Comparator.
Table 7.1
Specifications of Comparator
Item Comparator 1
Input voltage to VCMP1 pin
Comparator 2
Input voltage to VCMP2 pin
Analog input voltage
Reference input voltage
Comparison target
Internal reference voltage or input voltage to CVREF pin
Whether passing thorough reference input voltage by rising or falling
Comparison result monitor
VW1C3 bit in VW1C register
Whether higher or lower than reference input voltage
VCA13 bit in VCA1 register
Interrupt
Comparator 1 interrupt (non-makable or
maskable selectable)
Comparator 2 interrupt (non-makable or
maskable selectable)
Interrupt request at both or either of
Interrupt request at both or either of
reference input voltage > input voltage to reference input voltage > input voltage to
VCMP1 pin and input voltage to VCMP1
pin > reference input voltage
VCMP2 pin and input voltage to VCMP2
pin > reference input voltage
Digital Switch
Available
Filter
enabled/disabled
Sampling time
(fOCO-S divided by n) × 2
n: 1, 2, 4, 8
Output from VCOUT1 pin (Whether the
Output from VCOUT2 pin (Whether the
Comparison result output
comparison result output is inverted or not comparison result output is inverted or not
can be selected)
can be selected)
Rev.1.00 Mar 28, 2008 Page 53 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
Shared with
voltage monitor 1
circuit
VW1F1 to VW1F0
= 00b
Sampling
clock
fOCO-S
= 01b
= 10b
= 11b
fOCO-S/2
fOCO-S/4
fOCO-S/8
LCM1POR
Pin output
selection circuit
VCA26
VCAB5
0
VW1C1
CM1OE
0
VCMP1
+
-
0
1
Digital filter
VCOUT1
1
1
VW1C2
VW1C3
Edge
selection
circuit
non-maskable
interrupts
Shared with
voltage monitor 2
circuit
maskable
interrupts
VW2F1 to VW2F0
= 00b
VW1C0
Sampling
clock
fOCO-S
IRQ1SEL
= 01b
= 10b
= 11b
fOCO-S/2
fOCO-S/4
fOCO-S/8
LCM2POR
VCA27
VCAB6
0
VW2C1
CM2OE
0
VCMP2
+
-
0
1
Digital filter
VCOUT2
1
1
VW2C2
VCA13
Edge
selection
circuit
non-maskable
interrupts
VCAB7
1
CVREF
maskable
interrupts
0
VW2C0
IRQ2SEL
Internal reference voltage
VCA13: Bit in VCA1 register
VCA26, VCA27: Bits in VCA2 register
VW1C0 to VW1C3, VW1F0 to VW1F1: Bits in VW1C register
VW2C0, VW2C2, VW2F0 to VW2F1: Bits in VW2C register
VCAB5 to VCAB7: Bits in VCAB register
LCM1POR, LCM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in ALCMR register
Figure 7.1
Table 7.2
Block Diagram of Comparator
Pin Configuration of Comparator
Pin Name
I/O
Function
VCMP1
VCOUT1
VCMP2
VCOUT2
CVREF
Input
Output
Input
Output
Input
Comparator 1 analog pin
Comparator 1 comparison result output pin
Comparator 2 analog pin
Comparator 2 comparison result output pin
Comparator reference voltage pin
Rev.1.00 Mar 28, 2008 Page 54 of 341
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7.Comparator
7.2
Register Description
Figures 7.2 to 7.11 show the registers associated with the comparator when comparator 1 or comparator 2 is selected.
BGR Trimming Auxiliary Register A
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BGRTRMA
Address
002Eh
After Reset
When Shipping
Function
RW
RO
Stores data for internal reference voltage (Vref) correction w hen VCC = 3.6 to 5.5 V. (The
value is the same as that of the BGRTRM register after a reset).
Optimal correction to match the voltage conditions can be achieved by transferring this value
to the BGRTRM register.
BGR Trimming Auxiliary Register B
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BGRTRMB
Address
002Fh
After Reset
When Shipping
Function
RW
RO
Stores data for internal reference voltage (Vref) correction w hen VCC = 2.2 to 3.6 V.
Optimal correction to match the voltage conditions can be achieved by transferring this value
to the BGRTRM register.
Figure 7.2
Registers BGRTRMA and BGRTRMB
Rev.1.00 Mar 28, 2008 Page 55 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
Address
0031h
Bit Name
After Reset(2)
00001000b
Function
VCA1
Bit Symbol
—
RW
RW
Reserved bits
Set to 0.
(b2-b0)
Comparator 2 signal monitor flag(1)
Reserved bits
0: VCMP2 < reference voltage
1: VCMP2 reference voltage or
≥
VCA13
RO
comparator 2 circuit disabled
Set to 0.
—
(b7-b4)
RW
NOTES:
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). The
VCA13 bit is set to 1 (VCMP2 reference voltage) w hen the VCA27 bit in the VCA2 register is set to 0 (comparator
2 circuit disabled).
≥
2. Softw are reset and w atchdog timer reset do not affect this register.
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
Address
After Reset(2)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or the LVD0ON bit in the OFS register is
set to 0, and hardw are reset
Function
0: Low consumption disabled
1: Low consumption enabled(7)
: 00100000b
VCA2
0032h
Bit Name
Bit Symbol
RW
RW
Internal pow er low
VCA20
consumption enable bit(3)
—
Reserved bits
Set to 0.
RW
RW
RW
RW
(b4-b1)
Voltage detection 0 enable 0: Voltage detection 0 circuit disabled
VCA25
VCA26
VCA27
bit(4)
1: Voltage detection 0 circuit enabled
0: Comparator 1 circuit disabled
1: Comparator 1 circuit enabled
0: Comparator 2 circuit disabled
1: Comparator 2 circuit enabled
Comparator 1 enable bit(5)
Comparator 2 enable bit(6)
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCA2 register.
2. Softw are reset and w atchdog timer reset do not affect this register.
3. Use the VCA20 bit only w hen the MCU enters w ait mode. To set the VCA20 bit, follow the procedure show n in
.
Figure 11.12 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
4. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. To use the comparator 1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the comparator 1 circuit w aits for td(E-A) to elapse before starting operation.
6. To use the comparator 2 interrupt or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the comparator 2 circuit w aits for td(E-A) to elapse before starting operation.
7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
Figure 7.3
Registers VCA1 and VCA2
Rev.1.00 Mar 28, 2008 Page 56 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
Voltage Monitor 1 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW1C
Bit Symbol
Address
0036h
Bit Name
After Reset(2)
00001010b
Function
RW
RW
Comparator 1 interrupt enable bit(3) 0: Disable
1: Enable
VW1C0
Comparator 1 digital filter disable 0: Digital filter enable mode
mode select bit(4)
(digital filter circuit enabled)
1: Digital filter disable mode
(digital filter circuit disabled)
VW1C1
RW
RW
Comparator 1 interrupt
flag(2, 5, 6)
[Source for setting this bit to 0]
0: Write 0
[Source for setting this bit to 0]
1: When interrupt request is generated
VW1C2
Comparator 1 signal monitor
flag(2, 5)
0: VCMP1 < reference voltage
1: VCMP1 reference voltage or
≥
VW1C3
VW1F0
RO
comparator 1 circuit disabled
Sampling clock select bits
b5 b4
RW
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
VW1F1
VW1C6
RW
RW
1 1: fOCO-S divided by 8
Reserved bit
Set to 0.
Comparator 1 interrupt generation 0: When VCMP1 reaches reference
condition select bit(7)
voltage or above
1: When VCMP1 reaches reference
voltage or below
VW1C7
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW1C register.
When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the
VW1C register.
2. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset or w atchdog timer reset.
3. The VW1C0 is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit enabled).
When the VCA26 bit is set to 0 (comparator 1 circuit disabled), set the VW1C0 bit to 0 (disable).
To set the VW1C0 bit to 1 (enable), follow the procedure show n in
Associated with Comparator 1 Interrupt.
Table 7.3 Procedure for Setting Bits
4. To use the comparator 1 interrupt to exit stop mode and to return again, w rite 1 to the VW1C1 bit after w riting 0.
5. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit
enabled).
6. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
7. The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
Figure 7.4
VW1C Register
Rev.1.00 Mar 28, 2008 Page 57 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
Voltage Monitor 2 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW2C
Bit Symbol
Address
0037h
Bit Name
After Reset(2)
00000010b
Function
RW
RW
Comparator 2 interrupt enable bit(3) 0: Disable
1: Enable
VW2C0
VW2C1
Comparator 2 digital filter disable 0: Digital filter enabled mode
mode select bit(4)
(digital filter circuit enabled)
1: Digital filter disabled mode
(digital filter circuit disabled)
RW
RW
Comparator 2 interrupt
flag(2, 5, 6)
[Source for setting this bit to 0]
0: Write 0
[Source for setting this bit to 0]
1: When interrupt request is generated
VW2C2
WDT detection flag(2, 6)
0: Not detected
1: Detected
VW2C3
VW2F0
RW
RW
Sampling clock select bits
b5 b4
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
VW2F1
VW2C6
RW
RW
Reserved bit
Set to 0.
Comparator 2 interrupt generation 0: When VCMP2 reaches reference
condition select bit(7)
voltage or above
1: When VCMP2 reaches reference
voltage or below
VW2C7
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW2C register.
When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the
VW2C register.
2. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset or w atchdog timer reset.
3. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). Set
the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (comparator 2 circuit disabled).
To set the VW2C0 bit to 1 (enable), follow the procedure show n in
Table 7.4 Procedure for Setting Bits
.
Associated with Comparator 2 Interrupt
4. To use the comparator 2 interrupt to exit stop mode and to return again, w rite 1 to the VW2C1 bit after w riting 0.
5. The VW2C2 is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled).
6. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
7. The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
Figure 7.5
VW2C Register
Rev.1.00 Mar 28, 2008 Page 58 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
7.Comparator
Voltage Detection Circuit External Input Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
Address
003Bh
Bit Name
After Reset
00h
Function
VCAB
Bit Symbol
—
RW
RW
Reserved bits
Set to 0.
(b4-b0)
VCMP1 comparison voltage external 0: Supply voltage (VCC)
input select bit 1: VCMP1 pin input voltage
VCMP2 comparison voltage external 0: Supply voltage (VCC)
input select bit 1: VCMP2 pin input voltage
Comparator circuit reference voltage 0: Internal reference voltage
select bit 1: CVREF pin input voltage
VCAB5
VCAB6
VCAB7
RW
RW
RW
NOTE:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCAB register.
Figure 7.6
VCAB Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ALCMR
Address
003Ch
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
VCOUT1 output polarity select 0: Non-inverted comparator 1 comparison
bit
result is output to VCOUT1
1: Inverted comparator 1 comparison
result is output to VCOUT1
LCM1POR
LCM2POR
VCOUT2 output polarity select 0: Non-inverted comparator 2 comparison
bit
result is output to VCOUT2
1: Inverted comparator 2 comparison
result is output to VCOUT2
RW
VCOUT1 output enable bit
VCOUT2 output enable bit
0: Output disabled
1: Output enabled
0: Output disabled
1: Output enabled
0: Non-maskable interrupt
1: Maskable interrupt
0: Non-maskable interrupt
1: Maskable interrupt
CM1OE
CM2OE
RW
RW
RW
RW
—
Comparator 1 interrupt type
select bit
Comparator 2 interrupt type
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
IRQ1SEL
IRQ2SEL
—
(b7-b6)
Figure 7.7
ALCMR Register
Rev.1.00 Mar 28, 2008 Page 59 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
Voltage Monitor Circuit Edge Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
00h
Function
003Dh
VCAC
Bit Symbol
—
Bit Name
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b0)
Comparator 1 circuit edge select
0: One edge
VCAC1
RW
RW
—
bit(1)
1: Both edges
Comparator 2 circuit edge select
bit(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0: One edge
1: Both edges
VCAC2
—
(b7-b3)
NOTES:
1. The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after
setting the VCAC1 bit to 0.
2. The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after
setting the VCAC2 bit to 0.
Figure 7.8
VCAC Register
BGR Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BGRCR
Address
003Eh
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
Internal reference voltage (Vref)
adjustment circuit (BGR trimming
circuit) enable bit(2)
0: Enabled
1: Disabled
BGRCR0
—
(b7-b1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRCR register.
2. When the BGRCR0 bit is set to 1 (disabled), the accuracy/precision of the follow ing is not guaranteed:
• Internal reference voltage for comparator 1 and comparator 2
• Detection voltage for voltage detection circuit 0 to voltage detection circuit 2
• Oscillation frequency of the high-speed on-chip oscillator
Use these functions w hile the BGRCR0 bit is set to 0 (enabled).
To set the BGRCR0 bit to 1 (disabled), first disable voltage detection circuits 0 to 2 and disable comparators 1 and 2
w ith the internal reference voltage selected. Also stop the high-speed on-chip oscillator. Then set the BGRCR0 bit to
1 (disabled).
Figure 7.9
BGRCR Register
Rev.1.00 Mar 28, 2008 Page 60 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
BGR Trimming Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BGRTRM
Address
003Fh
After Reset
When Shipping
Function
RW
RW
Bits 0 to 7 can be used to adjust the level of the internal reference voltage (Vref).
Write either of the follow ing values into the BGRTRM register.
• Value stored in the BGRTRMA register
• Value stored in the BGRTRMB register
• 15h
Do not w rite values other than the above into the BGRTRM register.
Follow the procedure show n in Figure 7.16 for w riting data to the BGRTRM register.
NOTE:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRTRM register.
Figure 7.10
BGRTRM Register
Pin Select Register 4 (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
Address
02FBh
After Reset
00h
Function
PINSR4
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
RW
—
(b6-b2)
TREO pin select 2 bit(2)
0 : Disabled
1 : Enabled
TREOSEL2
NOTES:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
2. Set the TREOSEL2 bit to 1 (enabled) before using timer RE.
Pin Select Register 4 (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
PINSR4
Address
02FBh
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
—
—
(b6-b2)
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
Figure 7.11
PINSR4 Register
Rev.1.00 Mar 28, 2008 Page 61 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
7.3
7.3.1
Monitoring Comparison Results
Monitoring Comparator 1
After the following settings are made, the comparison result of comparator 1 can be monitored by the VW1C3
bit in the VW1C register after td(E-A) has elapsed (refer to 22. Electrical Characteristics).
(1) Set the COMPSEL bit in the PINSR4 register is set to 1 (comparator 1, comparator 2).
(2) Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage).
(3) Set the VCA26 bit in the VCA2 register to 1 (comparator 1 circuit enabled).
7.3.2
Monitoring Comparator 2
After the following settings are made, the comparison result of comparator 2 can be monitored by the VCA13
bit in the VCA1 register after td(E-A) has elapsed (refer to 22. Electrical Characteristics).
(1) Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2).
(2) Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage).
(3) Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled).
Rev.1.00 Mar 28, 2008 Page 62 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
7.4
Functional Description
Comparator 1 and comparator 2 operate independently.
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
can also be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF
pin can be selected as the reference input voltage. The comparator 1 interrupt or the comparator 2 interrupt also can
be used by selecting non-maskable or maskable for each interrupt.
7.4.1
Comparator 1
Table 7.3 lists the Procedure for Setting Bits Associated with Comparator 1 Interrupt, Figure 7.12 shows an
Operating Example of Comparator 1 (When Digital Filter Enabled), and Figure 7.13 shows an Operating
Example of Comparator 1 (When Digital Filter Disabled).
Table 7.3
Procedure for Setting Bits Associated with Comparator 1 Interrupt
Step
When Using Digital Filter
When Not Using Digital Filter
1
2
3
4
5
6
Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2)
Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage)
Set the VCA26 bit in the VCA2 register to 1 (comparator 1 circuit enabled)
Wait for td(E-A)
Select the interrupt type by the IRQ1SEL bit in the ALCMR register
Select the sampling clock by bits VW1F0 Set the VW1C1 bit in the VW1C register to 1 (digital
and VW1F1 in the VW1C register
Set the VW1C1 bit in the VW1C register
to 0 (digital filter enabled)
filter disabled)
(1)
−
7
8
Select the interrupt request timing by the VCAC1 bit in the VCAC register and the VW1C7 bit in
the VW1C register
9
10
Set the VW1C2 bit in the VW1C register to 0
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on)
11
Wait for 2 cycles of the sampling clock of − (No wait time required)
the digital filter.
12
Set the VW1C0 bit in the VW1C register to 1 (comparator 1 interrupt enabled)
NOTE:
1. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one
instruction)
Rev.1.00 Mar 28, 2008 Page 63 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
VCMP1
Reference voltage
1
VW1C3 bit
VW1C2 bit
0
2 cycles of sampling clock
of digital filter
2 cycles of sampling clock
of digital filter
1
0
Set to 0 by a program
Set to 0 by interrupt request
When the VW1C1 bit is set to 0
(digital filter enabled) and the
VCAC1 bit is set to 1 (both edges)
acknowledgement, or by a program
1
0
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
1
0
VCOUT1 output
(LCM1POR = 0)
Set to 0 by a program
1
0
VW1C2 bit
Set to 0 by interrupt request
acknowledgement, or by a program
IR bit in
1
0
When the VW1C1 bit is set to 0
(digital filter enabled), the VCAC1
bit is set to 0 (one edge), and
VCMP1IC register
(IRQ1SEL = 1)
the VW1C7 bit is set to 0 (VCMP1
reaches reference voltage or above)
1
0
VCOUT1 output
(LCM1POR = 0)
Set to 0 by a program
1
0
VW1C2 bit
When the VW1C1 bit is set to 0
(digital filter enabled), the VCAC1
bit is set to 0 (one edge), and
Set to 0 by interrupt request
acknowledgement, or by a program
IR bit in
1
0
VCMP1IC register
(IRQ1SEL = 1)
the VW1C7 bit is set to 1 (VCMP1
reaches reference voltage or below)
1
0
VCOUT1 output
(LCM1POR = 1)
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
LCM1POR, IRQ1SEL: Bits in ALCMR register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled)
• CM1OE bit in ALCMR register = 1 (output enabled)
• VCAB5 bit in VCAB register = 1 (VCMP1 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
Figure 7.12
Operating Example of Comparator 1 (When Digital Filter Enabled)
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R8C/2H Group, R8C/2J Group
7.Comparator
VCMP1
Reference voltage
1
0
VW1C3 bit
Set to 0 by a program
1
0
VW1C2 bit
IR bit in
Set to 0 by interrupt request
acknowledgement, or by a program
1
0
When the VW1C1 bit is set to 1
(digital filter disabled) and the
VCAC1 bit is set to 1 (both edges)
VCMP1IC register
(IRQ1SEL = 1)
1
0
VCOUT1 output
(LCM1POR = 0)
Set to 0 by a program
1
VW1C2 bit
0
1
Set to 0 by interrupt request
When the VW1C1 bit is set to 1
(digital filter disabled), the VCAC1
bit is set to 0 (one edge), and
acknowledgement, or by a program
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
the VW1C7 bit is set to 0 (VCMP1
reaches reference voltage or above)
0
1
0
VCOUT1 output
(LCM1POR = 0)
Set to 0 by a program
1
0
1
0
1
0
VW1C2 bit
Set to 0 by interrupt request
When the VW1C1 bit is set to 1
(digital filter disabled), the VCAC1
bit is set to 0 (one edge), and
acknowledgement, or by a program
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
the VW1C7 bit is set to 1 (VCMP1
reaches reference voltage or below)
VCOUT1 output
(LCM1POR = 1)
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
LCM1POR, IRQ1SEL: Bits in ALCMR register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled)
• CM1OE bit in ALCMR register = 1 (output enabled)
• VCAB5 bit in VCAB register = 1 (VCMP1 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
Figure 7.13
Operating Example of Comparator 1 (When Digital Filter Disabled)
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R8C/2H Group, R8C/2J Group
7.Comparator
7.4.2
Comparator 2
Table 7.4 lists the Procedure for Setting Bits Associated with Comparator 2 Interrupt, Figure 7.14 shows an
Operating Example of Comparator 2 (When Digital Filter Enabled), and Figure 7.15 shows an Operating
Example of Comparator 2 (When Digital Filter Disabled).
Table 7.4
Procedure for Setting Bits Associated with Comparator 2 Interrupt
Step
When Using Digital Filter
When Not Using Digital Filter
1
2
3
4
5
Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2)
Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage)
Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled)
Wait for td(E-A)
Select the interrupt type by the IRQ2SEL bit in the ALCMR register
Select the sampling clock by bits VW2F0 Set the VW2C1 bit in the VW2C register to 1 (digital
and VW2F1 in the VW2C register
Set the VW2C1 bit in the VW2C register
to 0 (digital filter enabled)
6
filter disabled)
−
(1)
7
Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in
8
9
the VW2C register
Set the VW2C2 bit in the VW2C register to 0
Set the CM14 bit in the CM1 register to 0 −
(low-speed on-chip oscillator on)
10
Wait for 2 cycles of the sampling clock of − (No wait time required)
the digital filter.
11
12
Set the VW2C0 bit in the VW2C register to 1 (comparator 2 interrupt enabled)
NOTE:
1. When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one
instruction).
Rev.1.00 Mar 28, 2008 Page 66 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
VCMP2
Reference voltage
1
VCA13 bit
VW2C2 bit
0
2 cycles of sampling clock
of digital filter
2 cycles of sampling clock
of digital filter
1
0
Set to 0 by a program
Set to 0 by interrupt request
When the VW2C1 bit is set to 0
(digital filter enabled) and the
VCAC2 bit is set to 1 (both edges)
acknowledgement, or by a program
1
0
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
1
0
VCOUT2 output
(LCM2POR = 0)
Set to 0 by a program
1
0
VW2C2 bit
Set to 0 by interrupt request
acknowledgement, or by a program
IR bit in
1
0
When the VW2C1 bit is set to 0
(digital filter enabled), the VCAC2
bit is set to 0 (one edge), and
VCMP2IC register
(IRQ2SEL = 1)
the VW2C7 bit is set to 0 (VCMP2
reaches reference voltage or above)
1
0
VCOUT2 output
(LCM2POR = 0)
Set to 0 by a program
1
0
VW2C2 bit
When the VW2C1 bit is set to 0
(digital filter enabled), the VCAC2
bit is set to 0 (one edge), and
Set to 0 by interrupt request
acknowledgement, or by a program
IR bit in
1
0
VCMP2IC register
(IRQ2SEL = 1)
the VW2C7 bit is set to 1 (VCMP2
reaches reference voltage or below)
1
0
VCOUT2 output
(LCM2POR = 1)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
LCM2POR, IRQ2SEL: Bits in ALCMR register
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled)
• CM2OE bit in ALCMR register = 1 (output enabled)
• VCAB6 bit in VCAB register = 1 (VCMP2 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
Figure 7.14
Operating Example of Comparator 2 (When Digital Filter Enabled)
Rev.1.00 Mar 28, 2008 Page 67 of 341
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R8C/2H Group, R8C/2J Group
7.Comparator
VCMP2
Reference voltage
1
0
VCA13 bit
Set to 0 by a program
1
0
VW2C2 bit
IR bit in
Set to 0 by interrupt request
acknowledgement, or by a program
1
0
When the VW2C1 bit is set to 1
(digital filter disabled) and the
VCAC2 bit is set to 1 (both edges)
VCMP2IC register
(IRQ2SEL = 1)
1
0
VCOUT2 output
(LCM2POR = 0)
Set to 0 by a program
1
VW2C2 bit
0
1
Set to 0 by interrupt request
When the VW2C1 bit is set to 1
(digital filter disabled), the VCAC2
bit is set to 0 (one edge), and
acknowledgement, or by a program
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
the VW2C7 bit is set to 0 (VCMP2
reaches reference voltage or above)
0
1
0
VCOUT2 output
(LCM2POR = 0)
Set to 0 by a program
1
0
1
0
1
0
VW2C2 bit
Set to 0 by interrupt request
When the VW2C1 bit is set to 1
(digital filter disabled), the VCAC2
bit is set to 0 (one edge), and
acknowledgement, or by a program
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
the VW2C7 bit is set to 1 (VCMP2
reaches reference voltage or below)
VCOUT2 output
(LCM2POR = 1)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
LCM2POR, IRQ2SEL: Bits in ALCMR register
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled)
• CM2OE bit in ALCMR register = 1 (output enabled)
• VCAB6 bit in VCAB register = 1 (VCMP2 pin input)
• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)
Figure 7.15
Operating Example of Comparator 2 (When Digital Filter Disabled)
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7.Comparator
7.5
Comparator 1 and Comparator 2 Interrupts
Two interrupt requests are generated, one each for comparator 1 and comparator 2. Non-maskable or maskable can
be selected for each interrupt type. Refer to 13. Interrupts for interrupts.
7.5.1
Non-Maskable Interrupts
When IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 0, the comparator i interrupt functions as a non-
maskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is
set to 1. At this time, a non-maskable interrupt request for comparator i is generated.
7.5.2
Maskable Interrupts
When the IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 1, the comparator i interrupt functions as a
maskable interrupt. The comparator i interrupt uses the single VCMPiIC register (bits IR and ILVL0 to ILVL2)
and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is
set to 1. At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested).
Refer to 13.1.6 Interrupt Control for the VCMPiIC register and 13.1.5.2 Relocatable Vector Tables for
interrupt vectors.
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7.Comparator
7.6
Adjusting Internal Reference Voltage (Vref)
The level of the internal reference voltage (Vref) can be adjusted with the value of the BGRTRM register. The
values for correcting the Vref are stored in registers BGRTRMA and BGRTRMB before shipping the MCU. The
value of the BGRTRMA register is the same as that of the BGRTRM register after reset.
To use separate correction values to match the supply voltage ranges, transfer them from registers BGRTRMA and
BGRTRMB to the BGRTRM register. Figure 7.16 shows the Procedure for Adjusting Internal Reference Voltage
(Vref).
When the BGRCR0 bit in the BGRCR register to 1 (disabled), the internal reference voltage (Vref) adjustment
circuit (BGR trimming circuit) is disabled and the value of the BGRTRM register is also disabled.
When the BGR trimming circuit is disabled, the accuracy of the internal reference voltage (Vref) is not guaranteed.
Disable voltage detection circuits 0 to 2 and disable comparators 1 and 2 with the internal reference voltage
selected. The high-speed on-chip oscillator should also be stopped as necessary because the precision of its
oscillation frequency is not also guaranteed.
Start adjusting the internal reference voltage
(Vref)
Determine the supply voltage(1)
No
Vcc ≥ 3.6 V ?
Yes
Transfer the value of the BGRTRMA register
to the BGRTRM register
Transfer the value of the BGRTRMB register
to the BGRTRM register
Wait for 10µs
Adjustment of the internal reference voltage
(Vref) completed
NOTE:
1. The supple voltage can be determined by reading the monitor flag (VCA13 bit in VCA1
register) for voltage detection 2. Figure 7.17 shows an Example of Adjusting Internal
Reference Voltage (Vref) (Voltage Detection 2 Used for Determining Supply Voltage).
Figure 7.16
Procedure for Adjusting Internal Reference Voltage (Vref)
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7.Comparator
Start adjusting the internal reference voltage
(Vref)
Transfer the value of the BGRTRMA register to
the BGRTRM register
Wait for 10µs
Enable the voltage detection 2 circuit
(Set the VCA27 bit to 1 and the VW2C0 bit to 0)
Wait for td(E-A) or 100µs
No
VCA13 bit = 0 ?
Yes
Transfer the value of the BGRTRMB register to
the BGRTRM register
Wait for 10µs
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VW2C0: Bit in VW2C register
Adjustment of the internal reference voltage
(Vref) completed
Figure 7.17
Example of Adjusting Internal Reference Voltage (Vref) (Voltage Detection 2 Used for
Determining Supply Voltage)
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8. I/O Ports
8. I/O Ports
There are 15 input/output (I/O) ports P1, P3_3, P3_7, P4_3, P4_5, and P6_3 to P6_5 in the R8C/2H Group.
When the XCIN clock oscillation circuit is not used, P4_3 can be used as an I/O port and P4_4 can be used as an output
port.
Table 8.1 lists an Overview of I/O Ports for R8C/2H Group.
Table 8.1
Ports
P1
P3_3, P3_7
P4_3
P4_4
P4_5
P6_3
P6_4, P6_5
Overview of I/O Ports for R8C/2H Group
I/O
I/O
I/O
I/O
Type of Output
CMOS3 State
CMOS3 State
CMOS3 State
I/O Setting
Set per bit
Internal Pull-Up Resister
(1)
Set every 4 bits
(1)
Set per bit
Set per bit
Set per bit
Set per bit
Set per bit
Set per bit
Set every bit
(2)
Set every bit
(3)
Output CMOS3 State
None
Set every bit
Set every bit
(2)
I/O
I/O
I/O
CMOS3 State
CMOS3 State
CMOS3 State
(2)
(2)
Set every 2 bits
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR0
register.
2. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR1
register.
3. Do not use port P4_4 as an input port (input mode).
There are 12 input/output (I/O) ports P1, P3_3, P3_7, P4_5, and P6_5 in the R8C/2J Group.
Table 8.2 lists an Overview of I/O Ports for R8C/2H Group.
Table 8.2
Overview of I/O Ports for R8C/2J Group
Ports I/O Type of Output
I/O Setting
Set per bit
Set per bit
Set per bit
Set per bit
Internal Pull-Up Resister
Set every 4 bits
(1)
P1
I/O CMOS3 State
I/O CMOS3 State
I/O CMOS3 State
I/O CMOS3 State
(1)
P3_3, P3_7
P4_5
P6_5
Set every bit
(2)
Set every bit
(2)
Set every bit
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR0
register.
2. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR1
register.
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R8C/2H Group, R8C/2J Group
8. I/O Ports
8.1
Functions of I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 1, 3, 4, 6) register controls I/O of the following: Ports P1, P3_3, P3_7,
P4_3, P4_5, P6_3 to P6_5 in the R8C/2H Group and ports P1, P3_3, P3_7, P4_5, and P6_5 in the R8C/2J Group.
The Pi register consists of a port latch to hold output data and a circuit to read pin states.
Figures 8.1 to 8.3 show the Configurations of I/O Ports. Table 8.3 lists the Functions of I/O Ports. Also, Figure 8.5
shows the PDi (i = 1, 3, 4, or 6) Register (R8C/2H Group). Figure 8.6 shows the Pi (i = 1, 3, 4, or 6) Register (R8C/
2H Group), Figure 8.7 shows the PDi (i = 1, 3, 4, or 6) Register (R8C/2J Group), Figure 8.8 shows the Pi (i = 1, 3,
4, or 6) Register (R8C/2J Group), Figure 8.9 shows Registers PINSR2 and PINSR4, Figure 8.10 shows the PMR
Register, Figure 8.11 shows Registers PUR0 and PUR1.
Table 8.3
Functions of I/O Ports
(1)
Operation When
Accessing
Value of PDi_j Bit in PDi Register
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Pi Register
Reading
Read pin input level
Write to the port latch
Read the port latch
Write to the port latch. The value written to
Writing
the port latch is output from the pin.
i = 1, 3, 4, 6, j = 0 to 7
NOTE:
1. In the R8C/2H Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD6_0, and PD6_6 are reserved.
In the R8C/2J Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD4_3, PD4_4, PD6_0, PD6_3, PD6_4, and
PD6_6 are reserved.
8.2
Effect on Peripheral Functions
I/O ports function as I/O ports for peripheral functions (refer to Table 1.5 Pin Name Information by Pin Number
of R8C/2H Group and Table 1.6 Pin Name Information by Pin Number of R8C/2J Group).
Table 8.4 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, 6, j = 0
to 7). Refer to the description of each function for information on how to set peripheral functions.
Table 8.4
Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, 6, j = 0 to 7)
(1)
I/O of Peripheral Functions
Input
Output
PDi_j Bit Settings for Shared Pin Functions
Set this bit to 0 (input mode).
This bit can be set to either 0 or 1 (output regardless of the port setting)
NOTE:
1. In the R8C/2H Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD6_0, and PD6_6 are reserved.
In the R8C/2J Group, nothing is assigned to bits PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2,
and PD6_7. Bits PD3_0 to PD3_2, PD3_4 to PD3_6, PD4_3, PD4_4, PD6_0, PD6_3, PD6_4, and
PD6_6 are reserved.
8.3
Pins Other than Programmable I/O Ports
Figure 8.4 shows the Configuration of I/O Pins.
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P1_0 to P1_2
8. I/O Ports
Pull-up selection
1
Direction
register
(Note 1)
(Note 1)
Output from individual peripheral function
Port latch
Data bus
Input to individual peripheral function
Analog input
P1_3, P1_6,
Pull-up selection
P3_3, and P6_5 (for R8C/2H Group)
Direction
register
1
(Note 1)
Output from individual peripheral function
Port latch
Data bus
(Note 1)
Input to individual peripheral function
P1_4, P3_7, and P6_3 (for the R8C/2H Group only)
Pull-up selection
Direction
register
1
(Note 1)
(Note 1)
Output from individual peripheral function
Port latch
Data bus
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 8.1
Configuration of I/O Ports (1)
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P1_5 and P1_7
8. I/O Ports
Pull-up selection
1
Direction
register
(Note 1)
(Note 1)
Output from individual peripheral function
Port latch
Data bus
Digital
filter
INT1 input
Input to individual peripheral function
P4_5
Pull-up selection
Direction
register
(Note 1)
(Note 1)
Data bus
Port latch
Digital
filter
INT0 input
P6_4
(for the R8C/2H Group only)
Pull-up selection
Direction
register
(Note 1)
(Note 1)
Data bus
Port latch
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 8.2
Configuration of I/O Ports (2)
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R8C/2H Group, R8C/2J Group
P6_5 (for R8C/2J Group)
8. I/O Ports
Pull-up selection
Direction
register
(Note 1)
(Note 1)
Port latch
Data bus
P4_3/XCIN
(for the R8C/2H Group only)
Pull-up selection
Direction
register
(Note 1)
(Note 1)
Data bus
Port latch
Clocked inverter(2)
(Note 3)
P4_4/XCOUT
(for the R8C/2H Group only)
Direction
register
(Note 1)
(Note 1)
Data bus
Port latch
NOTES:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off.
3. When CM04 = 0 the feedback resistor is disconnected.
Figure 8.3
Configuration of I/O Ports (3)
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MODE
8. I/O Ports
MODE signal input
(Note 1)
(Note 1)
(Note 1)
RESET
RESET signal input
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 8.4
Configuration of I/O Pins
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R8C/2H Group, R8C/2J Group
8. I/O Ports
Port Pi Direction Register (i = 1, 3, 4, or 6)(1, 2, 3) (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD1
PD3
PD4
PD6
Bit Symbol
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Address
00E3h
00E7h
00EAh
00EEh
Bit Name
After Reset
00h
00h
00h
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi_0 direction bit
0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
Port Pi_1 direction bit
Port Pi_2 direction bit
Port Pi_3 direction bit
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit
Port Pi_7 direction bit
NOTES:
1. Bits PD3_0 to PD3_2 and PD3_4 to PD3_6 in the PD3 register are reserved. Set to 0.
2. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0.
To use port P4_4 as an output port, set the PD4_4 bit to 1 (output mode). Do not use port P4_4 as an input port.
3. Bits PD6_1, PD6_2, and PD6_7 in the PD6 register are unavailable on this MCU.
If it is necessary to set bits PD6_1, PD6_2, and PD6_7, set to 0 (input mode). When read, the content is 0.
Bits PD6_0 and PD6_6 are reserved. Set to 0.
Figure 8.5
PDi (i = 1, 3, 4, or 6) Register (R8C/2H Group)
Port Pi Register (i = 1, 3, 4, or 6)(1, 2, 3) (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P1
P3
P4
P6
Bit Symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Address
00E1h
00E5h
00E8h
00ECh
Bit Name
After Reset
00h
00h
00h
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit
Port Pi_7 bit
The pin level of any I/O port w hich is set
to input mode can be read by reading the
corresponding bit in this register. The pin
level of any I/O port w hich is set to output
mode can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
Pi_7
RW
NOTES:
1. Bits P3_0 to P3_2 and P3_4 to P3_6 in the P3 register are reserved. Set to 0.
2. Bits P4_0 to P4_2, P4_6, and P4_7 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_2, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.
3. Bits P6_1, P6_2, and P6_7 in the P6 register are unavailable on this MCU.
If it is necessary to set bits P6_1, P6_2, and P6_7, set to 0 (“L” level). When read, the content is 0.
Bits P6_0 and P6_6 are reserved. Set to 0.
Figure 8.6
Pi (i = 1, 3, 4, or 6) Register (R8C/2H Group)
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8. I/O Ports
Port Pi Direction Register (i = 1, 3, 4, or 6)(1, 2, 3) (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD1
PD3
PD4
PD6
Bit Symbol
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Address
00E3h
00E7h
00EAh
00EEh
Bit Name
After Reset
00h
00h
00h
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi_0 direction bit
0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
Port Pi_1 direction bit
Port Pi_2 direction bit
Port Pi_3 direction bit
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit
Port Pi_7 direction bit
NOTES:
1. Bits PD3_0 to PD3_2 and PD3_4 to PD3_6 in the PD3 register are reserved. Set to 0.
2. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0.
Bits PD4_3 and PD4_4 are reserved. Set to 0.
3. Bits PD6_1, PD6_2, and PD6_7 in the PD6 register are unavailable on this MCU.
If it is necessary to set bits PD6_1, PD6_2, and PD6_7, set to 0 (input mode). When read, the content is 0.
Bits PD6_0, PD6_3, PD6_4, and PD6_6 are reserved. Set to 0.
Figure 8.7
PDi (i = 1, 3, 4, or 6) Register (R8C/2J Group)
Port Pi Register (i = 1, 3, 4, or 6)(1, 2, 3) (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P1
P3
P4
P6
Bit Symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Address
00E1h
00E5h
00E8h
00ECh
Bit Name
After Reset
00h
00h
00h
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit
Port Pi_7 bit
The pin level of any I/O port w hich is set
to input mode can be read by reading the
corresponding bit in this register. The pin
level of any I/O port w hich is set to output
mode can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
Pi_7
RW
NOTES:
1. Bits P3_0 to P3_2 and P3_4 to P3_6 in the P3 register are reserved. Set to 0.
2. Bits P4_0 to P4_2, P4_6, and P4_7 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_2, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.
Bits P4_3 and P4_4 are reserved. Set to 0.
3. Bits P6_1, P6_2, and P6_7 in the P6 register are unavailable on this MCU.
If it is necessary to set bits P6_1, P6_2, and P6_7, set to 0 (“L” level). When read, the content is 0.
Bits P6_0, P6_3, P6_4, and P6_6 are reserved. Set to 0.
Figure 8.8
Pi (i = 1, 3, 4, or 6) Register (R8C/2J Group)
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8. I/O Ports
Pin Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
00F6h
Bit Name
After Reset
00h
Function
PINSR2
Bit Symbol
—
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO pin select bit(1)
(b3-b0)
0 : Disabled
1 : Enabled
TRAOSEL
RW
—
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Disabled
1 : Enabled
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b5)
TRBO pin select bit(2)
TRBOSEL
RW
—
—
(b7)
NOTES:
1. Set the TRAOSEL bit to 1 (enabled) before using timer RA.
2. Set the TRBOSEL bit to 1 (enabled) before using timer RB.
Pin Select Register 4 (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
PINSR4
Address
02FBh
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
RW
—
(b6-b2)
TREO pin select 2 bit(2)
0 : Disabled
1 : Enabled
TREOSEL2
NOTES:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
2. Set the TREOSEL2 bit to 1 (enabled) before using timer RE.
Pin Select Register 4 (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
PINSR4
Address
02FBh
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
TRFO11 pin select bit(1)
0 : Disabled
1 : Enabled
TRFOSEL
Voltage monitor/comparator
select bit
Reserved bits
0 : Voltage monitor 1, voltage monitor 2
1 : Comparator 1, comparator 2
Set to 0.
COMPSEL
RW
RW
—
—
(b6-b2)
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Set the TRFOSEL bit to 1 (enabled) before using timer RF.
Figure 8.9
Registers PINSR2 and PINSR4
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Port Mode Register
8. I/O Ports
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
00F8h
Bit Name
After Reset
00h
Function
PMR
Bit Symbol
—
RW
RW
Reserved bit
Set to 0.
(b0)
—
(b7-b1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Figure 8.10
PMR Register
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Pull-Up Control Register 0
8. I/O Ports
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PUR0
Bit Symbol
Address
00FCh
Bit Name
After Reset
00h
Function
RW
—
—
(b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b1)
Reserved bit
Set to 0.
RW
PU02
PU03
P1_0 to P1_3 pull-up(1)
P1_4 to P1_7 pull-up(1)
0 : Not pulled up
1 : Pulled up
RW
RW
—
(b5-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
PU06
PU07
P3_3 pull-up(1)
P3_7 pull-up(1)
0 : Not pulled up
1 : Pulled up
RW
RW
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1 (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Bit Symbol
PU10
Address
00FDh
Bit Name
After Reset
00h
Function
RW
RW
RW
P4_3 pull-up(1)
P4_5 pull-up(1)
0 : Not pulled up
1 : Pulled up
PU11
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b3-b2)
PU14
PU15
P6_3 pull-up(1)
0 : Not pulled up
1 : Pulled up
RW
RW
P6_4, P6_5 pull-up(1)
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1 (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
PUR1
Bit Symbol
Address
00FDh
Bit Name
After Reset
00h
Function
RW
RW
—
Reserved bit
Set to 0.
(b0)
P4_5 pull-up(1)
0 : Not pulled up
1 : Pulled up
PU11
RW
—
—
(b3-b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Reserved bit
Set to 0.
RW
RW
—
(b4)
P6_5 pull-up(1)
0 : Not pulled up
1 : Pulled up
PU15
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Figure 8.11
Registers PUR0 and PUR1
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8. I/O Ports
8.4
Port Setting
Table 8.5 to Table 8.22 list the port setting.
Table 8.5
Port P1_0/KI0/TRFO00/VCMP1
Register
Bit
PD1
PD1_0
0
1
X
TRFOUT
TRFOUT0
KIEN
KI0EN
0
0
0
VCAB
VCAB5
Function
Input port(1)
Output port
0
0
1
0
0
0
Setting
value
TRFO00 output
KI0 input(1, 2)
0
0
0
0
1
0
0
1
VCMP1 input(1)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Set bit 2 (reserved bit) in the PINSR4 register to 0.
Table 8.6
Port P1_1/KI1/TRFO01/VCMP2
Register
Bit
PD1
PD1_1
0
1
X
TRFOUT
TRFOUT1
KIEN
KI1EN
0
0
0
VCAB
VCAB6
Function
Input port(1)
Output port
0
0
1
0
0
0
Setting
value
TRFO01 output
KI1 input(1, 2)
0
0
0
0
1
0
0
1
VCMP2 input(1)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Set bit 3 (reserved bit) in the PINSR4 register to 0.
Table 8.7
Port P1_2/KI2/TRFO02/CVREF
Register
Bit
PD1
PD1_2
TRFOUT
TRFOUT2
KIEN
KI2EN
VCAB
VCAB7
Function
Input port(1)
Output port
0
1
X
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
Setting
value
TRFO02 output
KI2 input(1)
CVREF input(1)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
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8. I/O Ports
Table 8.8
Port P1_3/KI3/VCOUT1/TRBO
Register
Bit
PD1
PD1_3
0
1
0
Timer RB Setting
−
KIEN
KI3EN
0
0
1
ALCMR
CM1OE
Function
Input port(1)
Output port
KI3 input(1)
Other than TRBO usage conditions
Other than TRBO usage conditions
Other than TRBO usage conditions
Refer to Table 8.9 TRBO Pin Setting
Other than TRBO usage conditions
0
0
0
0
1
Setting
value
X
X
0
0
TRBO output
VCOUT1 output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 8.9
TRBO Pin Setting
Register
Bit
PINSR2
TRBOSEL
TRBIOC
TOCNT(1)
TRBMR
Function
TMOD1
TMOD0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
1
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Setting
value
P1_3 output port
Other than above
Other than TRBO usage conditions
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
Table 8.10
Port P1_4/TXD0
Register
Bit
PD1
PD1_4
0
1
U0MR
SMD1
Function
SMD2
SMD0
Input port(1)
Output port
0
0
0
0
0
0
0
1
0
1
0
Setting
value
0
1
TXD0 output(2)
X
1
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1.
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8. I/O Ports
Table 8.11
Port P1_5/RXD0/(TRAIO)/(INT1)
Register
Bit
PD1
PD1_5
TRAIOC
TIOSEL
TRAMR
TMOD1
INTEN
INT1EN
Function
TOPCR(3)
TMOD2
X
TMOD0
X
0
X
1
0
X
Input port(1)
0
0
1
0
1
0
0
0
X
0
X
X
0
X
X
0
X
X
0
X
1
0
0
0
0
1
Output port
1
0
Setting
value
RXD0 input(1)
1
0
0
1
Other than 001b
0
1
0
0
1
INT1 input(1, 2)
TRAIO input(1)
TRAIO input/INT1 input(1, 2)
TRAIO output
0
0
X
1
1
1
0
Other than 000b, 001b
Other than 000b, 001b
0
0
0
X
1
1
0
X
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set bit 0 (reserved bit) in the PMR register to 0.
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
Table 8.12
Port P1_6/CLK0/VCOUT2
Register
Bit
PD1
PD1_6
ALCMR
CM2OE
U0MR
Function
CKDIR
SMD2
X
SMD1
SMD0
X
0
1
X
0
1
X
Other than 001b
Input port(1)
0
0
X
Setting
value
1
X
0
Other than 001b
Output port
CLK0 output
CLK0 input(1)
VCOUT2 output
0
0
X
X
0
X
X
1
X
X
0
0
1
X
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 8.13
Port P1_7/TRAIO/INT1
Register
Bit
PD1
PD1_7
TRAIOC
TRAMR
TMOD1
X
INTEN
INT1EN
Function
TOPCR(3)
TIOSEL
1
TMOD2
X
TMOD0
X
1
0
X
0
0
1
0
0
0
X
1
0
X
0
0
1
Input port(1)
0
0
0
0
0
1
0
X
0
X
0
1
0
0
1
Output port
Setting
value
INT1 input(1, 2)
0
0
0
TRAIO input(1)
TRAIO input/INT1 input(1, 2)
TRAIO output
0
0
X
0
0
0
Other than 000b, 001b
Other than 000b, 001b
0
X
1
X
0
1
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set bit 0 (reserved bit) in the PMR register to 0.
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
Rev.1.00 Mar 28, 2008 Page 85 of 341
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8. I/O Ports
Table 8.14
Port P3_3/TRFO10/TRFI
Register
Bit
PD3
PD3_3
0
1
X
0
TRFOUT
TRFOUT3
Function
Input port(1)
Output port
TRFO10 output
TRFI input(1)
0
0
1
0
Setting
value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 8.15
Port P3_7/TRAO/TRFO11
Register
Bit
PD3
PD3_7
0
1
X
X
PINSR2
TRAOSEL
TRAIOC
TOENA
PINSR4
TRFOSEL
TRFOUT
TRFOUT4
Function
Input port(1)
Output port
TRAO output
X
X
1
0
0
1
0
X
X
X
1
0
0
0
1
Setting
value
X
TRFO11 output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Rev.1.00 Mar 28, 2008 Page 86 of 341
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8. I/O Ports
Table 8.16
Register
Bit
Port P4_3/(XCIN) (for R8C/2H Group only)
PD4
CM0
CM1
Circuit specifications
Oscillation
Function
Feedback
PD4_3
CM04
CM10
CM12
buffer
resistor
Input port(1, 2)
Output port(2)
0
1
0
0
X
X
X
X
OFF
OFF
OFF
OFF
XCIN clock oscillation (on-chip feedback
X
X
X
1
1
1
0
0
1
0
ON
ON
resistor enabled)
Setting
value
XCIN clock oscillation (on-chip feedback
resistor disabled)
1
ON
OFF
0
1
0
1
OFF
OFF
ON
ON
OFF
ON
XCIN clock oscillation stop
X
1
0
External XCIN clock input
ON
OFF
X: 0 or 1
NOTES:
1. Pulled up by setting the PU10 bit in the PUR1 register to 1.
2. Refer to 8.6.1 Port P4_3, P4_4 (for R8C/2H Group only).
Table 8.17
Port P4_4/(XCOUT) (for R8C/2H Group only)
Register
Bit
PD4
CM0
CM04
0
CM1
Circuit specifications
Function
Oscillation
buffer
Feedback
resistor
PD4_4
CM10
CM12
Output port(1)
1
X
0
X
0
OFF
ON
OFF
ON
XCIN clock oscillation (on-chip feedback
resistor enabled)
X
1
XCIN clock oscillation (on-chip feedback
resistor disabled)
X
X
X
1
1
1
0
1
0
1
ON
OFF
Setting
value
0
1
0
1
OFF
OFF
ON
ON
OFF
ON
XCIN clock oscillation stop
External XCOUT clock output (inverted
output of XCIN clock)
ON
OFF
X: 0 or 1
NOTE:
1. Refer to 8.6.1 Port P4_3, P4_4 (for R8C/2H Group only).
Table 8.18
Port P4_5/INT0
Register
Bit
PD4
PD4_5
INTEN
INT0EN
Function
Input port(1)
Output port
0
1
0
0
0
1
Setting
value
INT0 input
NOTE:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
Rev.1.00 Mar 28, 2008 Page 87 of 341
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8. I/O Ports
Table 8.19
Port P6_3/TXD2 (for R8C/2H Group only)
Register
Bit
PD6
PD6_3
U2MR
SMD1
0
0
Function
SMD2
SMD0
Input port(1)
Output port
0
1
0
0
0
0
0
1
0
1
0
Setting
value
0
1
TXD2 output(2)
X
1
X: 0 or 1
NOTES:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
Table 8.20
Port P6_4/RXD2 (for R8C/2H Group only)
Register
Bit
PD6
Function
PD6_4
Input port(1)
Output port
RXD2 input(1)
0
1
0
Setting
value
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 8.21
Port P6_5/CLK2/TREO (for R8C/2H Group)
Register
Bit
PD6
PD6_5
PINSR4
TREOSEL2
TRECR1
TOENA
U2MR
Function
Input port(1)
CKDIR
SMD2
X
SMD1
SMD0
0
1
X
0
1
X
Other than 001b
0
0
X
X
X
1
X
0
0
0
0
1
X
X
X
1
Other than 001b
Output port
Setting
value
0
X
X
0
X
X
1
X
X
CLK2 output
CLK2 input(1)
TREO output
X
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 8.22
Port P6_5 (for R8C/2J Group)
Register
Bit
Setting
value
PD6
PD6_5
0
1
Function
Input port(1)
Output port
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Rev.1.00 Mar 28, 2008 Page 88 of 341
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8. I/O Ports
8.5
Unassigned Pin Handling
Table 8.23 lists Unassigned Pin Handling.
Table 8.23
Unassigned Pin Handling
Pin Name
Connection
Ports P1, P3_3, P3_7,
• After setting to input mode, connect each pin to VSS via a resistor
(pull-down) or connect each pin to VCC via a resistor (pull-up).
(4)
(2)
P4_3 to P4_5, P6_3 to P6_5
(1, 2)
• After setting to output mode, leave these pins open.
(3)
(2)
RESET
Connect to VCC via a pull-up resistor
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
4. Ports P4_3, P4_4, P6_3, and P6_4 are not available in the R8C/2J Group. Leave NC pins open.
MCU
Port P1, P3_3, P3_7,
P4_3 to P4_5,
(Input mode )
:
:
:
:
P6_3 to P6_5
(Input mode)
(2)
(Output mode)
Open
RESET(1)
NOTES:
1. When the power-on reset function is in use.
2. Ports P4_3, P4_4, P6_3, and P6_4 are not available in the R8C/2J Group.
Leave NC pins open.
Figure 8.12
Unassigned Pin Handling
Rev.1.00 Mar 28, 2008 Page 89 of 341
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R8C/2H Group, R8C/2J Group
8. I/O Ports
8.6
8.6.1
Notes on I/O Ports
Port P4_3, P4_4 (for R8C/2H Group only)
Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset
period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can
be switched to the port functions by setting the CM04 bit in the CM0 register to 0 (ports P4_3 and P4_4) by a
program.
To use ports P4_3 and P4_4 as ports, note the following:
• Port P4_3
After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, a typical 10 MΩ impedance is
connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level
input or left floating, a shoot-through current flows into the oscillation driver.
• Port P4_4
Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset
until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate
potential of about 2.0 V.
Rev.1.00 Mar 28, 2008 Page 90 of 341
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R8C/2H Group, R8C/2J Group
9. Processor Mode
9. Processor Mode
9.1
Processor Modes
Single-chip mode can be selected as the processor mode.
Table 9.1 lists Features of Processor Mode. Figure 9.1 shows the PM0 Register and Figure 9.2 shows the PM1
Register.
Table 9.1
Features of Processor Mode
Accessible Areas
Processor Mode
Pins Assignable as I/O Port Pins
Single-chip mode
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
PM0
Address
0004h
After Reset
00h
Bit Symbol
—
(b2-b0)
Bit Name
Reserved bits
Function
RW
RW
Set to 0.
Softw are reset bit
The MCU is reset w hen this bit is set to 1.
When read, the content is 0.
PM03
RW
—
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 9.1
PM0 Register
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
PM1
Address
0005h
After Reset
00h
Bit Symbol
—
(b1-b0)
Bit Name
Function
RW
RW
Reserved bits
Set to 0.
WDT interrupt/reset sw itch bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset(2)
PM12
RW
—
—
(b6-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7)
Reserved bit
Set to 0.
RW
NOTES:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
2. The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Figure 9.2
PM1 Register
Rev.1.00 Mar 28, 2008 Page 91 of 341
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R8C/2H Group, R8C/2J Group
10.Bus
10. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 10.1 lists Bus Cycles by Access Space.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 10.2 lists Access Units and Bus Operations.
Table 10.1
Bus Cycles by Access Space
Access Area
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
SFR
ROM/RAM
Table 10.2
Access Units and Bus Operations
SFR
Area
ROM, RAM
Even address
Byte access
CPU clock
CPU
clock
Address
Data
Even
Data
Even
Odd
Address
Data
Data
Odd address
Byte access
CPU
clock
Address
CPU
clock
Odd
Address
Data
Data
Data
Data
Even address
Word access
CPU
clock
CPU
clock
Address
Data
Address
Data
Even
Data
Even + 1
Even
Data
Even + 1
Data
Data
Odd address
Word access
CPU
clock
CPU
clock
Odd
Data
Odd + 1
Data
Address
Data
Odd
Odd + 1
Data
Address
Data
Data
Rev.1.00 Mar 28, 2008 Page 92 of 341
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R8C/2H Group, R8C/2J Group
11. Clock Generation Circuit
11. Clock Generation Circuit
The clock generation circuit in the R8C/2H Group has:
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
The clock generation circuit in the R8C/2J Group has:
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 11.1 lists Specifications of Clock Generation Circuit for R8C/2H Group. Table 11.2 lists Specifications of Clock
Generation Circuit for R8C/2J Group. Figure 11.1 shows a Clock Generation Circuit for R8C/2H Group. Figure 11.2
shows a Clock Generation Circuit for R8C/2J Group. Figures 11.3 to 11.11 show clock associated registers. Figure
11.12 shows a Handling Procedure of Internal Power Low Consumption Using VCA20 Bit.
The XCIN clock oscillation circuit is not implemented in the R8C/2J Group.
The description about the XCIN clock oscillation circuit in this chapter applies to the R8C/2H Group only.
Table 11.1
Specifications of Clock Generation Circuit for R8C/2H Group
On-Chip Oscillator
High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator
Item
XCIN Clock Oscillation Circuit
Applications
• CPU clock source
• Peripheral function clock
source
• CPU clock source
• Peripheral function clock
source
• CPU clock source
• Peripheral function clock
source
Clock frequency 32.768 kHz
Approx. 8 MHz
−
Approx. 125 kHz
−
Connectable
oscillator
• Crystal oscillator
(1)
(1)
(1)
Oscillator
connect pins
XCIN, XCOUT
−
−
Oscillation stop, Usable
Usable
Stop
−
Usable
Oscillate
−
restart function
Oscillator status Oscillate
after reset
Others
• Externally generated clock can
(2)
be input
• On-chip feedback resistor
RfXCIN (connected/ not
connected, selectable)
NOTES:
1. These pins can be used as P4_3 or P4_4 when using the on-chip oscillator clock as the CPU clock while the
XCIN clock oscillation circuit is not used.
2. Set the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin) when an external clock is input.
Table 11.2
Specifications of Clock Generation Circuit for R8C/2J Group
On-Chip Oscillator
Item
High-Speed On-Chip Oscillator
Low-Speed On-Chip Oscillator
Applications
• CPU clock source
• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
Clock frequency
Oscillation stop, restart function Usable
Oscillator status after reset Stop
Approx. 8 MHz
Approx. 125 kHz
None
Oscillate
Rev.1.00 Mar 28, 2008 Page 93 of 341
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R8C/2H Group, R8C/2J Group
11. Clock Generation Circuit
fC4
fC32
fC
1/4
1/8
HRA1 register
HRA2 register
Clock prescaler
Frequency adjustable
High-speed
on-chip
HRA00
oscillator
fOCO-F
Watchdog
timer
On-chip oscillator
clock
HRA01 = 1
HRA01 = 0
INT0
Timer RA Timer RB Timer RE Timer RF
UART0
UART2
fOCO
Stop signal
Low-speed
Power-on
reset circuit
on-chip
CM14
oscillator
fOCO-S
Voltage
detection
circuit
f1
b
f2
f4
c
d
XCIN
f8
e
XCOUT
OCD2 = 1
OCD2 = 0
g
f32
a
CPU clock
Divider
CM04
XCIN
clock
System clock
CM02
CM10 = 1 (stop mode)
Q
Q
S
R
RESET
Power-on reset
Software reset
Interrupt request
g
e
d
c
b
S
R
1/2
1/2
a
1/2
1/2
1/2
WAIT instruction
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
h
CM06 = 0
CM17 to CM16 = 10b
CM02, CM04, CM06: Bits in CM0 register
CM06 = 0
CM17 to CM16 = 01b
CM10, CM14, CM16, CM17: Bits in CM1 register
OCD2: Bits in OCD register
HRA00, HRA01: Bits in HRA0 register
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Figure 11.1
Clock Generation Circuit for R8C/2H Group
Rev.1.00 Mar 28, 2008 Page 94 of 341
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11. Clock Generation Circuit
HRA1 register
HRA2 register
Frequency adjustable
High-speed
HRA00
on-chip
oscillator
fOCO-F
Watchdog
timer
On-chip oscillator
clock
HRA01 = 1
HRA01 = 0
INT0
Timer RA Timer RB Timer RF
UART0
fOCO
Low-speed
Power-on
reset circuit
on-chip
oscillator
fOCO-S
Voltage
detection
circuit
f1
b
f2
f8
c
d
f32
f
a
CPU clock
Divider
System clock
CM02
CM10 = 1 (stop mode)
Q
Q
S
RESET
R
Power-on reset
Software reset
Interrupt request
f
d
c
b
S
1/2
1/2
a
1/2
1/2
1/2
WAIT instruction
R
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
h
CM06 = 0
CM17 to CM16 = 10b
CM02, CM06: Bits in CM0 register
CM10, CM16, CM17: Bits in CM1 register
HRA00, HRA01: Bits in HRA0 register
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Figure 11.2
Clock Generation Circuit for R8C/2J Group
Rev.1.00 Mar 28, 2008 Page 95 of 341
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R8C/2H Group, R8C/2J Group
11. Clock Generation Circuit
System Clock Control Register 0(1) (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
CM0
Bit Symbol
Address
0006h
Bit Name
After Reset
01011000b
Function
RW
—
—
(b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Reserved bit
Set to 0.
RW
RW
(b1)
WAIT peripheral function clock 0 : Peripheral function clock does not stop
stop bit
in w ait mode
1 : Peripheral function clock stops in w ait
mode
CM02
XCIN-XCOUT drive capacity
select bit(2)
Port, XCIN-XCOUT sw itch bit(3, 4) 0 : Ports P4_3, P4_4
1 : XCIN-XCOUT pin
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : LOW
1 : HIGH
CM03
CM04
RW
RW
—
—
(b5)
Systemclock division select bit 0 : CM16, CM17 enabled
CM06
RW
RW
0(5)
1 : Divide-by-8 mode
Set to 0.
—
(b7)
Reserved bit
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. When entering stop mode, the CM03 bit is set to 1 (HIGH). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
3. P4_3 and P4_4 can be used as ports w hen the CM04 bit is set to 0 (ports P4_3 and P4_4).
To use the XCIN clock, set the CM04 bit to 1 (XCIN-XCOUT pin). Also, set port P4_3 as input ports w ithout pull-up.
4. If the CM10 bit in the CM1 register is set to 1 (stop mode), w hen the CM04 bit is set to 1 (XCIN-XCOUT pin), the
XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to
0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is
entered).
5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
Figure 11.3
CM0 Register (R8C/2H Group)
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11. Clock Generation Circuit
System Clock Control Register 0(1) (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 1
0
Symbol
CM0
Bit Symbol
Address
0006h
Bit Name
After Reset
01011000b
Function
RW
—
—
(b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Reserved bit
Set to 0.
RW
RW
(b1)
WAIT peripheral function clock 0 : Peripheral function clock does not stop
stop bit
in w ait mode
1 : Peripheral function clock stops in w ait
mode
CM02
—
Reserved bit
Reserved bit
Set to 1.
RW
RW
—
(b3)
—
(b4)
Set to 0.(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b5)
Systemclock division select bit 0 : CM16, CM17 enabled
CM06
RW
RW
0(2)
1 : Divide-by-8 mode
Set to 0.
—
(b7)
Reserved bit
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
3. The b4 bit is set to 1 after reset. Set this bit to 0 at the beginning of the program.
Figure 11.4
CM0 Register (R8C/2J Group)
Rev.1.00 Mar 28, 2008 Page 97 of 341
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11. Clock Generation Circuit
System Clock Control Register 1(1) (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
0007h
After Reset
00h
Bit Symbol
Bit Name
Function
0 : Clock operates
1 : Stops all clocks (stop mode)
RW
RW
All clock stop control bit(2, 3, 4)
CM10
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
RW
—
(b1)
XCIN-XCOUT on-chip feedback
resistor select bit
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled
CM12
—
(b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Low -speed on-chip oscillation stop 0 : Low -speed on-chip oscillator on
CM14
RW
—
bit(4, 5, 6, 7)
1 : Low -speed on-chip oscillator off
—
(b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Systemclock division select bits 1(8)
b7 b6
0 0 : No division mode
CM16
CM17
RW
RW
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
3. If the CM10 bit is set to 1 (stop mode), w hen the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the
XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to
0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is
entered).
4. When count source protection mode for the w atch dog timer is enabled (refer to
16.2 Count Source Protection
), the value remains unchanged even if bits CM10 and CM14 are set.
Mode Enabled
5. When the OCD2 bit in the OCD register is set to 0 (XCIN clock selected), the CM14 bit is set to 1 (low -speed on-chip
oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed
on-chip oscillator on). It remains unchanged even if 1 is w ritten to it.
6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
7. In count source protect mode enabled, the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains
unchanged even if 1 is w ritten to it.
8. When the CM06 bit in the CM0 register is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
Figure 11.5
CM1 Register (R8C/2H Group)
Rev.1.00 Mar 28, 2008 Page 98 of 341
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11. Clock Generation Circuit
System Clock Control Register 1(1) (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
CM1
Address
0007h
After Reset
00h
Bit Symbol
Bit Name
Function
0 : Clock operates
1 : Stops all clocks (stop mode)
RW
RW
All clock stop control bit(2)
CM10
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
RW
—
(b1)
—
(b2)
—
(b3)
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Reserved bit
Set to 0.
RW
—
(b4)
—
(b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
System clock division select bits 1(3)
b7 b6
0 0 : No division mode
CM16
CM17
RW
RW
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2. When count source protection mode for the w atch dog timer is enabled (refer to
16.3 Count Source Protection
), the value remains unchanged even if the CM10 bit is set.
Mode Enabled
3. When the CM06 bit in the CM0 register is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
Figure 11.6
CM1 Register (R8C/2J Group)
Rev.1.00 Mar 28, 2008 Page 99 of 341
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11. Clock Generation Circuit
System Clock Select Register(1) (for R8C/2H Group only)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
OCD
Bit Symbol
Address
000Ch
Bit Name
After Reset
00000100b
Function
RW
—
—
(b1-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
System clock select bit
0 : Selects XCIN clock
OCD2
RW
—
1 : Selects on-chip oscillator clock(2)
—
(b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Reserved bits
Set to 0.
RW
—
(b6-b4)
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
2. The CM14 in the CM1 register bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip
oscillator clock selected).
Figure 11.7
OCD Register (for R8C/2H Group only)
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11. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HRA0
Address
0020h
Bit Name
After Reset
00h
Bit Symbol
Function
RW
RW
High-speed on-chip oscillator
0 : High-speed on-chip oscillator off
1 : High-speed on-chip oscillator on
HRA00
enable bit
High-speed on-chip oscillator
select bit(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Selects low -speed on-chip oscillator(3)
1 : Selects high-speed on-chip oscillator
HRA01
RW
—
—
(b7-b2)
NOTES:
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA0 register.
1.
2. Change the HRA01 bit under the follow ing conditions.
• HRA00 = 1 (high-speed on-chip oscillation on)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
3. When setting the HRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the HRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time. Set the HRA00 bit to 0 after setting the HRA01 bit to 0.
High-Speed On-Chip Oscillator Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HRA1
Address
0021h
After Reset
When Shipping
Function
RW
RW
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.(2)
High-speed on-chip oscillator frequency = 8 MHz
(HRA1 register = value w hen shipping; fOCO-fast mode 0)
Setting the HRA1 register to a low er value results in a higher frequency.
Setting the HRA1 register to a higher value results in a low er frequency.
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA1 register.
2. When changing the values of the HRA1 register, adjust these bits not to exceed the maximum value of the system
clock.
High-Speed On-Chip Oscillator Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0
Symbol
HRA2
Bit Symbol
Address
0022h
Bit Name
After Reset
00h
Function
RW
RW
—
(b0)
Reserved bit
Set to 0.
High-speed on-chip oscillator
mode select bit(3)
0: fOCO-fast mode 0
(8 MHz w hen the HRA1 register is set to
the value w hen shipping )
1: fOCO-fast mode 2(2)
HRA21
RW
—
Reserved bits
Set to 0.
RW
—
(b4-b2)
—
(b7-b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA2 register.
2. Sw itching fOCO-fast mode 0 to fOCO-fast mode 2 multiplies the frequency by 0.5.
3. Set this bit not to exceed the maximum value of the system clock.
Figure 11.8
Registers HRA0, HRA1, and HRA2
Rev.1.00 Mar 28, 2008 Page 101 of 341
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R8C/2H Group, R8C/2J Group
11. Clock Generation Circuit
Clock Prescaler Reset Flag (for R8C/2H Group only)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Symbol
CPSRF
Bit Symbol
Address
0028h
Bit Name
After Reset
00h
Function
RW
RW
—
Reserved bits
Set to 0.
(b6-b0)
Clock prescaler reset flag(1)
Setting this bit to 1 initializes the clock
prescaler. (When read, the content is 0)
CPSR
RW
NOTE:
1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
Figure 11.9
CPSRF Register (for R8C/2H Group only)
High-Speed On-Chip Oscillator Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA4
Address
0029h
After Reset
When Shipping
Function
RW
RO
Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that
of the HRA1 register after a reset.) Optimal frequency correction to match the voltage
conditions can be achieved by transferring this value to the HRA1 register.
High-Speed On-Chip Oscillator Control Register 6
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA6
Address
002Bh
After Reset
When Shipping
Function
RW
RO
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the HRA1
register.
Figure 11.10 Registers FRA4 and FRA6
Rev.1.00 Mar 28, 2008 Page 102 of 341
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R8C/2H Group, R8C/2J Group
11. Clock Generation Circuit
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
Address
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
Function
0 : Low consumption disabled
1 : Low consumption enabled(7)
: 00100000b
VCA2
0032h
Bit Name
Bit Symbol
RW
RW
Internal pow er low
VCA20
consumption enable bit(6)
—
Reserved bits
Set to 0.
RW
RW
RW
RW
(b4-b1)
Voltage detection 0 enable 0 : Voltage detection 0 circuit disabled
bit(2)
1 : Voltage detection 0 circuit enabled
Voltage detection 1 enable 0 : Voltage detection 1 circuit disabled
bit(3)
1 : Voltage detection 1 circuit enabled
Voltage detection 2 enable 0 : Voltage detection 2 circuit disabled
bit(4)
1 : Voltage detection 2 circuit enabled
VCA25
VCA26
VCA27
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in
Figure
.
11.12 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
Figure 11.11 VCA2 Register
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11. Clock Generation Circuit
Exit wait mode by interrupt
In interrupt routine
(Note 1)
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed clock mode(4) or low-speed
on-chip oscillator mode
VCA20 ← 0 (internal power low consumption
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
disabled)(2)
If it is necessary to start
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (8) in the interrupt
routine.
Stop high-speed on-chip oscillator clock
Start high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
enabled)(2)
Enter wait mode(3)
Enter high-speed on-chip oscillator mode
Interrupt handling
VCA20 ← 0 (internal power low consumption
Step (5)
Step (6)
Step (7)
Step (8)
disabled)(2)
Enter low-speed clock mode(4) or
low-speed on-chip oscillator mode
Step (1)
Step (2)
Step (3)
Start high-speed on-chip oscillator clock
If high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
Stop high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter high-speed on-chip oscillator mode
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When entering wait mode, follow 11.5.2 Wait Mode.
4. Applicable to the R8C/2H Group only.
VCA20: Bit in VCA2 register
Figure 11.12 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
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11. Clock Generation Circuit
The clocks generated by the clock generation circuits are described below.
11.1 On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register.
11.1.1 Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
11.1.2 High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-F.
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is
started by setting the HRA00 bit in the HRA0 register to 1 (high-speed on-chip oscillator on). The frequency
can be adjusted by registers HRA1 and HRA2.
Furthermore, frequency correction data corresponding to the supply voltage ranges listed below is stored in
registers FRA4 and FRA6. To use separate correction values to match these voltage ranges, transfer them from
register FRA4 or FRA6 to the HRA1 register.
• FRA4 register: Stores data for frequency correction corresponding to VCC = 2.7 V to 5.5 V.
(The value is the same as that of the HRA1 register after a reset.)
• FRA6 register: Stores data for frequency correction corresponding to VCC = 2.2 V to 5.5 V.
Since there are differences in the amount of frequency adjustment among the bits in the HRA1 register, make
adjustments by changing the settings of individual bits. Adjust the HRA1 register so that the frequency of the
high-speed on-chip oscillator clock does not exceed the maximum value of the system clock.
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11. Clock Generation Circuit
11.2 XCIN Clock (for R8C/2H Group only)
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, peripheral function clock. The XCIN clock oscillation circuit is configured by connecting a resonator
between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor,
which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in
the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 11.13 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock oscillates.
The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (selects XCIN clock)
after the XCIN clock is oscillating stably.
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 11.4 Power Control for details.
MCU
MCU
(on-chip feedback resistor)
(on-chip feedback resistor)
XCIN
XCIN
XCOUT
XCOUT
Open
Rf(1)
Rd(1)
Externally derived clock
CIN
COUT
VCC
VSS
External clock input circuit
External crystal oscillator circuit
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Figure 11.13 Examples of XCIN Clock Connection Circuits
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11. Clock Generation Circuit
11.3 CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 11.1 Clock Generation Circuit for R8C/2H Group and Figure 11.2 Clock Generation Circuit for
R8C/2J Group.
11.3.1 System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XCIN clock (for
R8C/2H Group only) or the on-chip oscillator clock can be selected.
11.3.2 CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
The system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division.
Use the XCIN clock while the XCIN clock oscillation stabilizes (for the R8C/2H Group only).
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
11.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers
RA, RB, RE, and RF, and the serial interface.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
11.3.4 fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
11.3.5 fOCO-F
fOCO-F is generated by the high-speed on-chip oscillator and supplied by setting the HRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does not stop.
11.3.6 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-
chip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer,
fOCO-S does not stop.
11.3.7 fC4 and fC32 (for R8C/2H Group only)
The clock fC4 is used for timer RE and the clock fC32 is used for timer RA, timer RF, and watchdog timer.
Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
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11. Clock Generation Circuit
11.4 Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
11.4.1 Standard Operating Mode
Standard operating mode is further separated into three modes.
Table 11.3 lists the Settings and Modes of Clock Associated Bits for R8C/2H Group and Table 11.4 lists the
Settings and Modes of Clock Associated Bits for R8C/2J Group.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XCIN clock, allow sufficient wait time in a program until oscillation is
stabilized before exiting (for the R8C/2H Group only).
Table 11.3
Settings and Modes of Clock Associated Bits for R8C/2H Group
OCD Register
CM1 Register
CM17, CM16 CM14
CM0 Register
HRA0 Register
Modes
High-speed on-chip No division
OCD2
CM06
CM04 HRA01 HRA00
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
00b
01b
10b
−
−
−
−
−
−
0
0
0
0
0
−
−
−
−
−
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
oscillator mode
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
11b
00b
01b
10b
−
Low-speed on-chip No division
oscillator mode
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
11b
00b
01b
10b
−
Low-speed clock
mode
11b
−: Can be 0 or 1, no change in outcome
Table 11.4 Settings and Modes of Clock Associated Bits for R8C/2J Group
CM1 Register
CM17, CM16
CM0 Register
HRA0 Register
HRA01 HRA00
Modes
High-speed on-chip No division
CM06
00b
01b
10b
−
0
0
0
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
−
−
−
−
−
oscillator mode
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
11b
00b
01b
10b
−
Low-speed on-chip No division
oscillator mode
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
11b
−: Can be 0 or 1, no change in outcome
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11. Clock Generation Circuit
11.4.1.1 High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00 bit in the HRA0
register is set to 1 (high-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is set to 1. The on-
chip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed clock mode.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit (for R8C/2H Group only).
11.4.1.2 Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the HRA01 bit in the HRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit (for R8C/2H Group only).
In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1
(flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumption enabled) enables lower consumption current in wait mode.
Refer to 21. Reducing Power Consumption for how to reduce the power consumption.
11.4.1.3 Low-Speed Clock Mode (for R8C/2H Group only)
The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide
by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the HRA00 bit in the HRA0 register is set to 1 (high
speed on-chip oscillator on), fOCO can be used as timer RA.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1
(flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lower consumption current in wait mode.
Refer to 21. Reducing Power Consumption for how to reduce the power consumption.
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11. Clock Generation Circuit
11.4.2 Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count source protection mode is disabled, stop. The XCIN clock (for R8C/2H Group only) and on-
chip oscillator clock do not stop and the peripheral functions using these clocks continue operating.
11.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop
in wait mode. This reduces power consumption.
11.4.2.2 Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
11.4.2.3 Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
11.4.2.4 Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function interrupt.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Table 11.5 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 11.5
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt
Serial interface interrupt
CM02 = 0
Usable when operating with
internal or external clock
Usable
CM02 = 1
Usable when operating with external
clock
Key input interrupt
Timer RA interrupt
Usable
Usable in all modes
Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32
as count source.
(1)
Timer RB interrupt
Timer RE interrupt
Usable in all modes
Usable in all modes
(Do not use)
Usable when operating in real time
clock mode
(1)
Timer RF interrupt
INT0, INT1 interrupt
Usable in all modes
Usable
(Do not use)
Can be used if there is no filter
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Usable
Usable
Usable
Usable
NOTE:
1. Applicable to the R8C/2H Group only.
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Figure 11.14 shows the Time from Wait Mode to Interrupt Routine Execution.
11. Clock Generation Circuit
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,
as described in Figure 11.14.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
FMR0 Register
FMSTP Bit
Time until Flash Memory Time until CPU Clock Time for Interrupt
Remarks
is Activated (T1)
is Supplied (T2)
Sequence (T3)
Following total
time is the time
from wait mode
until an interrupt
routine is
0
Period of system clock
Period of CPU clock Period of CPU clock
× 12 cycles + 30 µs (max.)
× 6 cycles
× 20 cycles
(flash memory operates)
1
Period of system clock
Same as above
Same as above
× 12 cycles
(flash memory stops)
executed.
T1
T2
T3
Flash memory
Wait mode
CPU clock restart sequence
Interrupt sequence
activation sequence
Interrupt request generated
Figure 11.14 Time from Wait Mode to Interrupt Routine Execution
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11. Clock Generation Circuit
11.4.3 Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals continue operating.
Table 11.6 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 11.6
Interrupts to Exit Stop Mode and Usage Conditions
Interrupt Usage Conditions
Key input interrupt
−
INT0, INT1 interrupt
Timer RA interrupt
Can be used if there is no filter
When there is no filter and external pulse is counted in event counter
mode
Serial interface interrupt
Voltage monitor 1 interrupt
When external clock is selected
Usable in digital filter disabled mode (VW1C1 bit in VW1C register is
set to 1)
Voltage monitor 2 interrupt
Usable in digital filter disabled mode (VW2C1 bit in VW2C register is
set to 1)
11.4.3.1 Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode), the CM03 bit in the CM0 register is set to
1 (XCIN clock oscillator circuit drive capacity high) (for the R8C/2H Group only).
11.4.3.2 Pin Status in Stop Mode
The status before wait mode was entered is maintained.
In the R8C/2H Group, when the CM04 bit in the CM0 register is set to 1 (XCIN-XOUT pin), the XCIN (P4_3)
pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to 0
(I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop
mode is entered).
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11. Clock Generation Circuit
11.4.3.3 Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 11.15 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used
for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be
used for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMR0 Register
FMSTP Bit
Time until Flash Memory Time until CPU Clock
Time for Interrupt
Sequence (T4)
Remarks
is Activated (T2)
is Supplied (T3)
Following total
time of T0 to T4 is
the time from stop
mode until an
0
Period of system clock
Period of CPU clock Period of CPU clock
(flash memory operates) × 12 cycles + 30 µs (max.)
× 6 cycles
× 20 cycles
1
Period of system clock
interrupt handling
is executed.
Same as above
Same as above
(flash memory stops)
× 12 cycles
T0
T1
T2
T3
T4
Oscillation time of
Internal
power
Stop
Flash memory
CPU clock restart
sequence
CPU clock source
used immediately
before stop mode
Interrupt sequence
mode
activation sequence
stability time
150 µs
(max.)
Interrupt
request
generated
Figure 11.15 Time from Stop Mode to Interrupt Routine Execution
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11. Clock Generation Circuit
Figure 11.16 shows the State Transitions in Power Control Mode for R8C/2H Group and Figure 11.17 shows
the State Transitions in Power Control Mode for R8C/2J Group.
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM14 = 0
OCD2 = 1
HRA01 = 0
CM04 = 1
OCD2 = 0
CM14 = 0
OCD2 = 1
HRA01 = 0
Low-speed clock mode
CM04 = 1
HRA00 = 1
HRA01 = 1
CM14 = 0
HRA01 = 0
OCD2 = 0
CM04 = 1
OCD2 = 0
OCD2 = 1
HRA00 = 1
HRA01 = 1
High-speed on-chip oscillator mode
OCD2 = 1
HRA00 = 1
HRA01 = 1
Interrupt
WAIT instruction
Interrupt
CM10 = 1
Wait mode
Stop mode
CPU operation stops
All oscillators stop
CM04: Bit in CM0 register
CM10, CM14: Bits in CM1 register
OCD2: Bit in OCD register
HRA00, HRA01: Bits in HRA0 register
Figure 11.16 State Transitions in Power Control Mode for R8C/2H Group
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11. Clock Generation Circuit
Reset
Standard operating mode
Low-speed on-chip oscillator mode
HRA01 = 0
HRA00 = 1
HRA01 = 0
HRA01 = 1
High-speed on-chip oscillator mode
HRA00 = 1
HRA01 = 1
Interrupt
WAIT instruction
Interrupt
CM10 = 1
Wait mode
Stop mode
All oscillators stop
CPU operation stops
CM10: Bits in CM1 register
HRA00, HRA01: Bits in HRA0 register
Figure 11.17 State Transitions in Power Control Mode for R8C/2J Group
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11. Clock Generation Circuit
11.5 Notes on Clock Generation Circuit
11.5.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
LABEL_001 :
NOP
NOP
NOP
NOP
11.5.2 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
FSET
WAIT
NOP
1,FMR0
I
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
NOP
NOP
NOP
11.5.3 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
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12.Protection
12. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 12.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD (for the R8C/2H Group only), HRA0, HRA1, and
HRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, VW2C, VCAB, BGRCR, and BGRTRM
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
PRCR
Bit Symbol
Address
000Ah
Bit Name
After Reset
00h
Function
RW
RW
Protect bit 0
Writing to registers CM0, CM1, OCD (for the
R8C/2H Group only), HRA0, HRA1, and HRA2 is
enabled.
PRC0
0 : Disables w riting
1 : Enables w riting
Protect bit 1
Writing to registers PM0 and PM1 is enabled.
0 : Disables w riting
PRC1
RW
RW
1 : Enables w riting
—
(b2)
Reserved bit
Protect bit 3
Set to 0.
Writing to registers VCA2, VW0C, VW1C, VW2C,
VCAB, BGRCR, and BGRTRM is enabled.
0 : Disables w riting
PRC3
RW
1 : Enables w riting
—
Reserved bits
Set to 0.
RW
—
(b5-b4)
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. This PRC2 bit is set to 0 after w riting 1 to this bit and executing a w rite to any address. Since the other bits are not
set to 0, set them to 0 by a program.
Figure 12.1
PRCR Register
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13.Interrupts
13. Interrupts
13.1 Interrupt Overview
13.1.1 Types of Interrupts
Figure 13.1 shows the Types of Interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
(non-maskable interrupts)
INT instruction
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Comparator 1(2)
Comparator 2(2)
Single step(3)
Interrupts
Special
(non-maskable interrupts)
Hardware
Address break(3)
Address match
Peripheral functions(1)
(maskable interrupts)
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. When non-maskable interrupts is selected.
3. Do not use this interrupt. This is for use with development tools only.
Figure 13.1
Types of Interrupts
• Maskable Interrupts:
• Non-Maskable Interrupts:
The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
The interrupt enable flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
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13.Interrupts
13.1.2 Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
13.1.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
13.1.2.2 Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
13.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
13.1.2.4 INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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13.Interrupts
13.1.3 Special Interrupts
Special interrupts are non-maskable. However, the comparator 1 and comparator 2 can select maskable
interrupts, too.
13.1.3.1 Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. For details of the watchdog timer, refer to 16.
Watchdog Timer.
13.1.3.2 Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage monitor 1 circuit. For details of the voltage monitor
1 circuit, refer to 6. Voltage Detection Circuit.
13.1.3.3 Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage monitor 2 circuit. For details of the voltage monitor
2, refer to 6. Voltage Detection Circuit.
13.1.3.4 Comparator 1 Interrupt
The comparator 1 interrupt is generated by the comparator 1. The non-maskable interrupt or maskable interrupt
can be selected. For details of the comparator 1 interrupt, refer to 7. Comparator.
13.1.3.5 Comparator 2 Interrupt
The comparator 2 interrupt is generated by the comparator 2. The non-maskable interrupt or maskable interrupt
can be selected. For details of the comparator 2 interrupt, refer to 7. Comparator.
13.1.3.6 Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by development tools only.
13.1.3.7 Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to
1 (address match interrupt enable). For details of the address match interrupt, refer to 13.4 Address Match
Interrupt.
13.1.4 Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable
interrupt. Refer to Table 13.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to the descriptions of individual peripheral functions.
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13.Interrupts
13.1.5 Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 13.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low address
Mid address
0 0 0 0
0 0 0 0
High address
0 0 0 0
Vector address (H)
Figure 13.2
Interrupt Vector
13.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 13.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory.
Table 13.1
Fixed Vector Tables
Vector Addresses
Address (L) to (H)
0FFDCh to 0FFDFh Interrupt on UND
Interrupt Source
Remarks
Reference
Undefined instruction
R8C/Tiny Series Software
Manual
instruction
Overflow
0FFE0h to 0FFE3h Interrupt on INTO
instruction
BRK instruction
0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Address match
0FFE8h to 0FFEBh
13.4 Address Match
Interrupt
(1)
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
Single step
Watchdog timer,
Voltage monitor 1,
Voltage monitor 2,
Comparator 1,
16. Watchdog Timer
6. Voltage Detection Circuit
7. Comparator
Comparator 2
Address break
(1)
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
(Reserved)
Reset
5. Resets
NOTE:
1. Do not use these interrupts. They are for use by development tools only.
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13.Interrupts
13.1.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 13.2 lists the Relocatable Vector Tables.
Table 13.2
Relocatable Vector Tables
Software
Interrupt
Number
Vector Addresses(1)
Interrupt Control
Register
Interrupt Source
Reference
Address (L) to Address (H)
+0 to +3(0000h to 0003h)
BRK instruction(2)
0
−
R8C/Tiny Series Software
Manual
7. Comparator
Comparator 1
Comparator 2
(Reserved)
Timer RE(3)
+4 to +7(0004h to 0007h)
+8 to +11(0008h to 000Bh)
1
2
VCMP1IC
VCMP2IC
−
3 to 9
10
−
+40 to +43(0028h to 002Bh)
TREIC
17.3 Timer RE (for R8C/2H
Group only)
UART2 transmit(3)
UART2 receive(3)
Key input
+44 to +47(002Ch to 002Fh)
+48 to +51(0030h to 0033h)
+52 to +55(0034h to 0037h)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S2TIC
S2RIC
KUPIC
−
18. Serial Interface
13.3 Key Input Interrupt
−
(Reserved)
(Reserved)
−
−
Compare 1
+64 to +67(0040h to 0043h)
+68 to +71(0044h to 0047h)
+72 to +75(0048h to 004Bh)
CMP1IC
S0TIC
S0RIC
−
17.4 Timer RF
18. Serial Interface
UART0 transmit
UART0 receive
(Reserved)
−
(Reserved)
−
−
(Reserved)
−
−
Timer RA
+88 to +91(0058h to 005Bh)
TRAIC
−
17.1 Timer RA
−
(Reserved)
Timer RB
INT1
(Reserved)
Timer RF
Compare 0
+96 to +99(0060h to 0063h)
+100 to +103(0064h to 0067h)
TRBIC
INT1IC
17.2 Timer RB
13.2 INT Interrupt
−
+108 to +111(006Ch to 006Fh)
+112 to +115(0070h to 0073h)
+116 to +119(0074h to 0077h)
TRFIC
CMP0IC
INT0IC
17.4 Timer RF
INT0
13.2 INT Interrupt
−
(Reserved)
Capture
Software interrupt(2)
−
+124 to +127(007Ch to 007Fh)
CAPIC
−
17.4 Timer RF
+128 to +131(0080h to 0083h) to 32 to 63
R8C/Tiny Series Software
+252 to +255(00FCh to 00FFh)
Manual
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable these interrupts.
3. Applicable to the R8C/2H Group only.
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13.Interrupts
13.1.6 Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 13.3 shows the Interrupt Control Register and Figure 13.4 shows the INTiIC Register (i = 0 or 1).
Interrupt Control Register(2)
Symbol
Address
0041h
0042h
004Ah
004Bh
004Ch
004Dh
0050h
0051h
0052h
0056h
0058h
005Bh
005Ch
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
VCMP1IC
VCMP2IC
TREIC (for R8C/2H Group only)
S2TIC (for R8C/2H Group only)
S2RIC (for R8C/2H Group only)
KUPIC
CMP1IC
S0TIC
S0RIC
TRAIC
TRBIC
TRFIC
CMP0IC
b7 b6 b5 b4 b3 b2 b1 b0
005Fh
XXXXX000b
CAPIC
Bit Symbol
Bit Name
Interrupt priority level select bits
Function
RW
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
ILVL0
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
RW
RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
ILVL2
IR
1 1 1 : Level 7
Interrupt request bit
0 : Requests no interrupt
1 : Requests interrupt
RW(1)
—
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated.
Ref er to
.
13.5.5 Changing Interrupt Control Register Contents
Figure 13.3
Interrupt Control Register
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13.Interrupts
INTi Interrupt Control Register (i=0 or 1)(2)
Symbol
Address
0059h
After Reset
XX00X000b
b7 b6 b5 b4 b3 b2 b1 b0
0
INT1IC
INT0IC
Bit Symbol
005Dh
Bit Name
Interrupt priority level select bits
XX00X000b
Function
RW
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
ILVL0
ILVL1
ILVL2
0 1 0 : Level 2
0 1 1 : Level 3
RW
RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
Polarity sw itch bit(4)
Reserved bit
0 : Requests no interrupt
1 : Requests interrupt
IR
RW(1)
RW
RW
—
0 : Selects falling edge
POL
1 : Selects rising edge(3)
—
(b5)
—
(b7-b6)
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
NOTES:
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Ref er to
.
13.5.5 Changing Interrupt Control Register Contents
3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to
13.5.4 Changing Interrupt
.
Sources
Figure 13.4
INTiIC Register (i = 0 or 1)
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13.Interrupts
13.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
13.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
13.1.6.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 13.3 lists the Settings of Interrupt Priority Levels and Table 13.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 13.3
Settings of Interrupt Priority
Levels
Table 13.4
Interrupt Priority Levels Enabled by
IPL
ILVL2 to ILVL0 Bits
Interrupt Priority Level
Level 0 (interrupt disabled)
Priority Order
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Enabled Interrupt Priority Levels
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
000b
001b
010b
011b
100b
101b
110b
111b
−
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
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13.Interrupts
13.1.6.4 Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 13.5 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).
(1)
(2) The FLG register is saved to a temporary register in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
(1)
(4) The CPU’s internal temporary register is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CPU Clock
Address Bus
Data Bus
RD
Address
0000h
Undefined
SP-2 SP-1 SP-4
SP-3
VEC
VEC+1
VEC+2
PC
Interrupt
SP-3
VEC+1
VEC+2
SP-2
SP-1
SP-4
VEC
contents
Undefined
Undefined
contents contents contents
information
contents
contents
contents
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
Figure 13.5
NOTE:
Time Required for Executing Interrupt Sequence
1. This register cannot be used by user.
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13.Interrupts
13.1.6.5 Interrupt Response Time
Figure 13.6 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in the interrupt routine. The interrupt response time
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 13.6) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 13.6).
Interrupt request is generated. Interrupt request is acknowledged.
Time
Instruction in
Instruction
Interrupt sequence
interrupt routine
(a)
20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set
as the divisor)
(b) 21 cycles for address match and single-step interrupts.
Figure 13.6
Interrupt Response Time
13.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 13.5 is set in the
IPL.
Table 13.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 13.5
IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source Value Set in IPL
Watchdog timer, voltage monitor 1, voltage monitor 2,
7
(1)
(1)
comparator 1 , comparator 2 , address break
Software, address match, single-step
Not changed
NOTE:
1. When non-maskable interrupts is selected.
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13.Interrupts
13.1.6.7 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 13.7 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
(1)
instruction can save several registers in the register bank being currently used with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Stack
Stack
Address
Address
MSB
LSB
MSB
LSB
[SP]
m−4
m−3
m−4
m−3
PCL
New SP value
PCM
m−2
m−1
m
m−2
FLGL
m−1
FLGH
PCH
[SP]
m
SP value before
interrupt is generated
Previous stack contents
Previous stack contents
Previous stack contents
Previous stack contents
PCH
PCM
PCL
: 4 High-order bits of PC
: 8 Middle-order bits of PC
: 8 Low-order bits of PC
m+1
m+1
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
Stack state before interrupt request
is acknowledged
Stack state after interrupt request
is acknowledged
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Figure 13.7
Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 13.8 shows the Register Saving Operation.
Stack
Address
Sequence in which
order registers are
saved
[SP]−5
[SP]−4
[SP]−3
(3)
(4)
PCL
PCM
Saved, 8 bits at a time
[SP]−2
[SP]−1
(1)
(2)
FLGL
FLGH
PCH
PCH
PCM
PCL
: 4 High-order bits of PC
: 8 Middle-order bits of PC
: 8 Low-order bits of PC
[SP]
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
Completed saving
registers in four
operations.
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
Figure 13.8
Register Saving Operation
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13.Interrupts
13.1.6.8 Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
13.1.6.9 Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 13.9 shows the Priority Levels of Hardware Interrupts.
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the
instruction is executed.
High
Reset
Address break
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Comparator 1(1)
Comparator 2(1)
Peripheral function
Single step
Address match
Low
NOTE:
1. When non-maskable interrupts is selected.
Figure 13.9
Priority Levels of Hardware Interrupts
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13.Interrupts
13.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 13.10.
Priority level of interrupt
Highest
Level 0 (default value)
Compare 0
Timer RB
Timer RA
Comparator 2(1)
Capture
INT0
Timer RF
Priority of peripheral function interrupts
(if priority levels are same)
INT1
UART0 receive
Compare 1
UART2 receive(3)
Timer RE(3)
UART0 transmit
Key input
UART2 transmit(3)
Comparator 1(1)
IPL
Lowest
Interrupt request level
judgment output signal
Interrupt request
acknowledged
I flag
Address match
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Comparator 1(2)
Comparator 2(2)
NOTES:
1. When maskable interrupts is selected.
2. When non-maskable interrupts is selected.
3. Applicable to the R8C/2H Group only.
Figure 13.10 Interrupt Priority Level Judgement Circuit
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13.Interrupts
13.2 INT Interrupt
13.2.1 INTi Interrupt (i = 0 or 1)
The INTi interrupt is generated by an INTi input. Table 13.6 lists the Pin Configuration of INT Interrupt. When
using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 (enable). The edge polarity is selected
using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register.
Inputs can be passed through a digital filter with three different sampling clocks.
Figure 13.11 shows the INTEN Register. Figure 13.12 shows the INTF Register.
Table 13.6
Pin Configuration of INT Interrupt
Input/Output
Input
Input
Pin name
Function
INT0 interrupt input, Timer RB external trigger input
INT1 interrupt input
INT0 (P4_5)
INT1 (P1_5 or P1_7)
NOTE:
(1)
1. The INT1 pin is selected by the TIOSEL bit in the TRAIOC register. Refer to 8. I/O Ports for details.
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
INTEN
Address
00F9h
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
____
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
INT0 input enable bit
INT0EN
INT0PL
INT1EN
INT1PL
____
INT0 input polarity select bit(1, 2)
RW
RW
RW
RW
____
INT1 input enable bit
____
INT1 input polarity select bit(1, 2)
—
(b7-b4)
Reserved bits
Set to 0.
NOTES:
1. When setting the INTiPL bit (i = 0, 1) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to
13.5.4
.
Changing Interrupt Sources
Figure 13.11 INTEN Register
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_____
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
Address
00FAh
Bit Name
After Reset
00h
Function
INTF
Bit Symbol
RW
RW
_____
b1 b0
0 0 : No filter
INT0 input filter select bits
INT0F0
INT0F1
INT1F0
INT1F1
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
_____
b3 b2
0 0 : No filter
INT1 input filter select bits
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
—
(b7-b4)
Reserved bits
Set to 0.
Figure 13.12 INTF Register
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13.Interrupts
13.2.2 INTi Input Filter (i = 0 or 1)
The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for
every sampling clock and the sampled input level matches three times.
Figure 13.13 shows the Configuration of INTi Input Filter. Figure 13.14 shows an Operating Example of INTi
Input Filter.
INTiF1 to INTiF0
= 01b
= 10b
= 11b
f1
f8
f32
Sampling clock
INTiEN
Other than
INTiF1 to INTiF0
= 00b
INTi
INTi interrupt
Digital filter
(input level
matches 3x)
Port direction
register(1)
= 00b
INTiPL = 0
INTiPL = 1
Both edges
detection
circuit
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0 or 1
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin,
Port P1_7 direction register when using the P1_7 pin
Figure 13.13 Configuration of INTi Input Filter
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 by a program
NOTE:
1. This is an operation example when bits INTiF1 to INTiF0 in the INTF register is set to 01b, 10b, or 11b (passing digital filter).
i = 0 or 1
Figure 13.14 Operating Example of INTi Input Filter
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13.Interrupts
13.3 Key Input Interrupt
A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. Table 13.7 lists the Pin
Configuration of Key Input Interrupt. The key input interrupt can be used as a key-on wake-up function to exit wait
or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in
the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 13.15 shows a Block Diagram of Key Input Interrupt. Figure 13.16 shows the KIEN Register.
Table 13.7
Pin Configuration of Key Input Interrupt
Input/Output
Input
Pin name
Function
KI0 (P1_0)
KI1 (P1_1)
KI2 (P1_2)
KI3 (P1_3)
KI0 input
KI1 input
KI2 input
KI3 input
Input
Input
Input
PU02 bit in PUR0 register
PD1_3 bit in PD1 register
KUPIC register
Pull-up
transistor
KI3EN bit
PD1_3 bit
KI3PL = 0
KI3PL = 1
KI3
KI2EN bit
PD1_2 bit
Pull-up
transistor
KI2PL = 0
KI2PL = 1
Interrupt control
circuit
Key input interrupt
request
KI2
KI1
KI0
KI1EN bit
PD1_1 bit
Pull-up
transistor
KI1PL = 0
KI1PL = 1
KI0EN, KI1EN, KI2EN, KI3EN,
KI0EN bit
PD1_0 bit
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
Pull-up
transistor
KI0PL = 0
KI0PL = 1
Figure 13.15 Block Diagram of Key Input Interrupt
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13.Interrupts
Key Input Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIEN
Address
00FBh
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
KI0 input enable bit
0 : Disable
1 : Enable
0 : Falling edge
1 : Rising edge
0 : Disable
1 : Enable
0 : Falling edge
1 : Rising edge
0 : Disable
1 : Enable
0 : Falling edge
1 : Rising edge
0 : Disable
1 : Enable
0 : Falling edge
1 : Rising edge
KI0EN
KI0PL
KI1EN
KI1PL
KI2EN
KI2PL
KI3EN
KI0 input polarity select bit
KI1 input enable bit
RW
RW
RW
RW
RW
RW
RW
KI1 input polarity select bit
KI2 input enable bit
KI2 input polarity select bit
KI3 input enable bit
KI3 input polarity select bit
KI3PL
NOTE:
1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Ref er to
.
13.5.4 Changing Interrupt Sources
Figure 13.16 KIEN Register
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13.Interrupts
13.4 Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (refer to 13.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
• Change the content of the stack and use the REIT instruction.
• Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.
Then use a jump instruction.
Table 13.8 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged. Table 13.9 lists
the Correspondence Between Address Match Interrupt Sources and Associated Registers.
Figure 13.17 shows Registers AIER and RMAD0 to RMAD1.
Table 13.8
Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
(1)
Address Indicated by RMADi Register (i = 0 or 1)
PC Value Saved
(2)
• Instruction with 2-byte operation code
• Instruction with 1-byte operation code
Address indicated by
(2)
RMADi register + 2
ADD.B:S
OR.B:S
STNZ
#IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest STZX #IMM81,#IMM82,dest
#IMM8,dest PUSHM src POPM
#IMM8 JSRS #IMM8
#IMM,dest (however, dest = A0 or A1)
#IMM8,dest
CMP.B:S
JMPS
dest
MOV.B:S
Instructions other than the above
Address indicated by
RMADi register + 1
NOTES:
1. Refer to the 13.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 13.9
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0
Address match interrupt 1
AIER0
AIER1
RMAD0
RMAD1
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13.Interrupts
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
0013h
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
Address match interrupt 0 enable bit 0 : Disable
1 : Enable
AIER0
Address match interrupt 1 enable bit 0 : Disable
1 : Enable
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
AIER1
RW
—
—
(b7-b2)
Address Match Interrupt Register i (i = 0 or 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
0012h-0010h
0016h-0014h
After Reset
000000h
000000h
Function
Setting Range
RW
Address setting register for address match interrupt
00000h to FFFFFh
RW
—
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b7-b4)
Figure 13.17 Registers AIER and RMAD0 to RMAD1
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13.Interrupts
13.5 Notes on Interrupts
13.5.1 Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
13.5.2 SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
13.5.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0, INT1 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), Table 22.29 (VCC = 2.2V), Table
22.45 (VCC = 5V), Table 22.50 (VCC = 3V), and Table 22.55 (VCC = 2.2V) External Interrupt INTi (i = 0
or 1) Input.
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13.Interrupts
13.5.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 13.18 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts(2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 13.5.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 13.18 Example of Procedure for Changing Interrupt Sources
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13.Interrupts
13.5.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
NOP
NOP
; Set TRAIC register to 00h
;
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
AND.B #00H,0056H
MOV.W MEM,R0
I
; Disable interrupts
; Set TRAIC register to 00h
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B #00H,0056H
POPC FLG
I
; Disable interrupts
; Set TRAIC register to 00h
; Enable interrupts
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14. ID Code Areas
14. ID Code Areas
14.1 Overview
The ID code areas are used to implement a function that prevents the flash memory from being rewritten in
standard serial I/O mode. This function prevents the flash memory from read, rewritten, or erased.
The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the
respective vector highest-order addresses of the fixed vector table. Figure 14.1 shows the ID Code Areas.
ID code areas
Address
0FFDFh to 0FFDCh
0FFE3h to 0FFE0h
0FFE7h to 0FFE4h
0FFEBh to 0FFE8h
0FFEFh to 0FFECh
0FFF3h to 0FFF0h
0FFF7h to 0FFF4h
0FFFBh to 0FFF8h
0FFFFh to 0FFFCh
ID1
ID2
Undefined instruction vector
Overflow vector
BRK instruction vector
Address match vector
Single step vector
ID3
ID4
ID5
ID6
ID7
OFS
Watchdog timer/voltage monitor 1 and voltage
monitor 2/comparator 1 and comparator 2 vector
Address break vector
(Reserved)
Reset vector
4 bytes
Figure 14.1
ID Code Areas
14.2 Functions
The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses from 0FFFCh to 0FFFEh) of the
reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial
programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the
commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes
do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging
simulator, first write predetermined ID codes to the ID code areas.
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an
instruction. Write appropriate values when creating a program.
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14. ID Code Areas
14.3 Notes on ID Code Areas
14.3.1 Setting Example of ID Code Areas
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing
an instruction. Write appropriate values when creating a program. The following shows a setting example.
• To set 55h in all of the ID code areas
.org 00FFDCH
.lword dummy | (55000000h) ; UND
.lword dummy | (55000000h) ; INTO
.lword dummy ; BREAK
.lword dummy | (55000000h) ; ADDRESS MATCH
.lword dummy | (55000000h) ; SET SINGLE STEP
.lword dummy | (55000000h) ; WDT
.lword dummy | (55000000h) ; ADDRESS BREAK
.lword dummy | (55000000h) ; RESERVE
(Programming formats vary depending on the compiler. Check the compiler manual.)
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15. Option Function Select Area
15. Option Function Select Area
15.1 Overview
The option function select area is used to select the MCU state after reset or the function to prevent rewriting in
parallel I/O mode. The reset vector highest-order-address, 0FFFFh, is assigned as the option function select area.
Figure 15.1 shows the Option Function Select Area.
Option function select area
Address
0FFFFh to 0FFFCh
OFS
Reset vector
4 bytes
Figure 15.1
Option Function Select Area
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15. Option Function Select Area
15.2 OFS Register
The OFS register is used to select the MCU state after reset or the function to prevent rewriting in parallel I/O
mode. Figure 15.2 shows the OFS Register.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
Address
0FFFFh
Bit Name
When Shipping
FFh(3)
Function
RW
RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
WDTON
—
Reserved bit
Set to 1.
RW
RW
RW
RW
(b1)
ROM code protect
disabled bit
ROM code protect bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
ROMCR
ROMCP1
—
(b4)
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
LVD0ON
RW
1 : Voltage monitor 0 reset disabled after hardw are
reset
—
Reserved bit
Set to 1.
RW
RW
(b6)
Count source protect
mode after reset select 1 : Count source protect mode disabled after reset
bit
0 : Count source protect mode enabled after reset
CSPROINI
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 15.2
OFS Register
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15. Option Function Select Area
15.3 Notes on Option Function Select Area
15.3.1 Setting Example of Option Function Select Area
As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by
executing an instruction. Write appropriate values when creating a program. The following shows a setting
example.
• To set FFh in the OFS register
.org 00FFFCH
.lword reset | (0FF000000h)
; RESET
(Programming formats vary depending on the compiler. Check the compiler manual.)
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16. Watchdog Timer
16. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 16.1 lists information on the Watchdog Timer Specifications for R8C/2H Group and Table 16.2 lists information
on the Watchdog Timer Specifications for R8C/2J Group.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 16.1 shows the Block Diagram of Watchdog Timer for R8C/2H Group and Figure 16.2 shows the Block
Diagram of Watchdog Timer for R8C/2J Group. Figure 16.3 shows the Registers WDTR, and WDTS. Figure 16.4
shows the WDC Register. Figure 16.5 shows the CSPR Register. Figure 16.6 shows the OFS Register.
Table 16.1
Item
Watchdog Timer Specifications for R8C/2H Group
Count Source Protection
Mode Disabled
Count Source Protection
Mode Enabled
Count source
CPU clock
Decrement
XCIN clock divided by 32 Low-speed on-chip oscillator
(fC32)
clock
Count operation
Count start condition Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition Stop mode, wait mode Stop mode
None
Reset condition of
watchdog timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time Watchdog timer interrupt or watchdog timer reset
of underflow
Watchdog timer reset
Select functions
• Division ratio of prescaler (when select the CPU clock as the count source)
Selected by the WDC7 bit in the WDC register
• The default value of the watchdog timer (when select fC32 as the count source)
Selected by bits CVS0 to CVS1 in the CSPR register
• Count source protection mode
Whether count source protection mode is enabled or disabled after a reset can
be selected by the CSPROINI bit in the OFS register (flash memory). If count
source protection mode is disabled after a reset, it can be enabled or disabled by
the CSPRO bit in the CSPR register (program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
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16. Watchdog Timer
Prescaler
WDC7 = 0
1/16
CSS = 0
CSS = 1
CSPRO = 0
CSPRO = 1
PM12 = 0
Watchdog timer
interrupt request
1/128
CPU clock
WDC7 = 1
Watchdog timer
fC32
fOCO-S
PM12 = 1
Watchdog
timer reset
Set to
default
value(1)
Write to WDTR register
Internal reset signal
CSS, CSPRO: Bits in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
When the CSPRO bit is set to 0 (count source protection mode disabled), the initial value depends on the
settings of bits CVS0, CVS1, and CSS in the CSPR register.
Figure 16.1
Block Diagram of Watchdog Timer for R8C/2H Group
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16. Watchdog Timer
Table 16.2
Watchdog Timer Specifications for R8C/2J Group
Count Source Protection
Mode Disabled
CPU clock
Count Source Protection
Item
Mode Enabled
Low-speed on-chip oscillator
clock
Count source
Count operation
Count start condition
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition
Reset condition of watchdog
timer
Stop mode, wait mode
• Reset
None
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time of underflow Watchdog timer interrupt or
watchdog timer reset
Watchdog timer reset
Select functions
• Division ratio of prescaler (when select the CPU clock as the count
source)
Selected by the WDC7 bit in the WDC register
• Count source protection mode
Whether count source protection mode is enabled or disabled after
a reset can be selected by the CSPROINI bit in the OFS register
(flash memory). If count source protection mode is disabled after a
reset, it can be enabled or disabled by the CSPRO bit in the CSPR
register (program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
Prescaler
WDC7 = 0
1/16
CSPRO = 0
CSPRO = 1
PM12 = 0
Watchdog timer
interrupt request
CPU clock
1/128
Watchdog timer
WDC7 = 1
PM12 = 1
Watchdog
timer reset
fOCO-S
Set to
7FFFh(1)
Write to WDTR register
Internal
reset signal
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Figure 16.2
Block Diagram of Watchdog Timer for R8C/2J Group
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16. Watchdog Timer
Watchdog Timer Reset Register (R8C/2H Group)
b7
b0
Symbol
WDTR
Address
000Dh
After Reset
Undefined
Function
RW
WO
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The w atchdog timer initial value depends on the CSPR register setting.
CSPR register
Default value
CSPRO
CSS
CVS1
CVS0
0
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
X
7FFFh
01FFh
03FFh
07FFh
0FFFh
0FFFh
0
0
0
0
1(2)
X: 0 or 1
NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
Watchdog Timer Reset Register (R8C/2J Group)
b7
b0
Symbol
WDTR
Address
000Dh
After Reset
Undefined
Function
RW
WO
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)
NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000Eh
After Reset
Undefined
Function
The w atchdog timer starts counting after a w rite instruction to this register.
RW
WO
Figure 16.3
Registers WDTR, and WDTS
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16. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
WDC
Bit Symbol
Address
000Fh
Bit Name
After Reset
00X11111b
Function
RW
RO
—
(b4-b0)
High-order bits of w atchdog timer
—
Reserved bit
Set to 0. When read, the content is undefined.
Set to 0.
RW
RW
RW
(b5)
—
(b6)
Reserved bit
Prescaler select bit
0 : Divide-by-16
1 : Divide-by-128
WDC7
Figure 16.4
WDC Register
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16. Watchdog Timer
Count Source Protection Mode Register (R8C/2H Group)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSPR
Address
001Ch
Bit Name
After Reset(1)
00h
Function
Bit Symbol
RW
RW
Watchdog timer default value
b1 b0
select bit(2)
0 0 : 01FFh (512)
0 1 : 03FFh (1024)
1 0 : 07FFh (2048)
1 1 : 0FFFh (4096)
CVS0
CVS1
CSS
RW
Count source select bit(3)
0 : CPU clock
1 : fC32
RW
—
—
(b6-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Count source protection mode 0 : Count source protection mode disabled
select bit(4)
1 : Count source protection mode enabled
CSPRO
RW
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. When the CSS bit is set to 1 (fC32), Bits CVS0 to CVS1 are enabled.
3. When the CSPRO bit is set to 0 (count source protection mode disabled), the CSS bit is enabled.
4. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
Count Source Protection Mode Register (R8C/2J Group)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
CSPR
Bit Symbol
Address
001Ch
Bit Name
After Reset(1)
00h
Function
RW
RW
—
(b2-b0)
Reserved Bits
Set to 0.
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
(b6-b3)
Count Source Protection Mode 0 : Count source protection mode disabled
CSPRO
Select Bit(2)
1 : Count source protection mode enabled
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. Write 0 before w riting 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
Figure 16.5
CSPR Register
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16. Watchdog Timer
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
Address
0FFFFh
Bit Name
When Shipping
FFh(3)
Function
RW
Watchdog timer start
0 : Starts w atchdog timer automatically after reset
WDTON
RW
RW
RW
RW
RW
select bit
1 : Watchdog timer is inactive after reset
—
(b1)
Reserved bit
Set to 1.
ROM code protect
disabled bit
ROM code protect bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
ROMCR
ROMCP1
—
(b4)
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
LVD0ON
RW
1 : Voltage monitor 0 reset disabled after hardw are
reset
—
Reserved bit
Set to 1.
RW
RW
(b6)
Count source protect
mode after reset select 1 : Count source protect mode disabled after reset
bit
0 : Count source protect mode enabled after reset
CSPROINI
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 16.6
OFS Register
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16. Watchdog Timer
16.1 Count Source Protection Mode Disabled (R8C/2H Group)
The count source of the watchdog timer is either the CPU clock or the XCIN clock divided by 32 (fC32) can be
selected when count source protection mode for the R8C/2H Group is disabled. fC32 does not stop in wait mode,
the watchdog timer to count continues.
Table 16.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled) for R8C/2H
Group.
Table 16.3
Watchdog Timer Specifications (with Count Source Protection Mode Disabled) for
R8C/2H Group
Item
Count source
Specification
CPU clock
XCIN clock divided by 32 (fC32)
Count operation Decrement
Period
count value of watchdog
timer (32768)(1, 2)
Division ratio of prescaler (n)
32
---------------------------------------------------------------------------
----------------------------- count value of watchdog timer (m)(1)
×
×
CPU clock
XCIN clock
n: 16 or 128 (selected by WDC7 bit in WDC
register)
m: 512, 1024, 2048 or 4096 (selected by bits
CVS0 to CVS1 in the CSPR register)
Example: When the CPU clock frequency is 8 MHz Example: When the XCIN clock frequency is
and prescaler divided by 16, the period is
approximately 65.5 ms
32.768 kHz and the count value by
512, the period is 0.5 s
Reset condition • Reset
of watchdog
timer
Count start
condition
• Write 00h to the WDTR register before writing FFh
• Underflow
The WDTON bit(3) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a
reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset)
The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register
is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting)
The watchdog timer and prescaler start counting automatically after a reset
Count stop
condition
Stop and wait modes (inherit the count from the
held value after exiting modes)
Stop mode (inherit the count from the held
value after exiting modes)
Operation at
• When the PM12 bit in the PM1 register is set to 0
time of
Watchdog timer interrupt
underflow
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh.
2. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused
by the prescaler.
3. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh
with a flash programmer.
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16. Watchdog Timer
16.2 Count Source Protection Mode Disabled (R8C/2J Group)
The count source of the watchdog timer is the CPU clock when count source protection mode for the R8C/2J Group
is disabled.
Table 16.4 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled) for R8C/2J
Group.
Table 16.4
Watchdog Timer Specifications (with Count Source Protection Mode Disabled) for
R8C/2J Group
Item
Specification
Count source
CPU clock
Decrement
Count operation
Period
(1)
Division ratio of prescaler (n) × count value of watchdog timer (32768)
CPU clock
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 8 MHz and prescaler
divides by 16, the period is approximately 65.5 ms
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
(2)
Count start condition
The WDTON bit in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
The watchdog timer and prescaler start counting automatically after a
reset
Stop and wait modes (inherit the count from the held value after exiting
modes)
Count stop condition
Operation at time of underflow • When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
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16. Watchdog Timer
16.3 Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 16.5 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
Table 16.5
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Low-speed on-chip oscillator clock
Count source
Count operation
Period
Decrement
Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-
chip oscillator clock frequency is 125 kHz
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
(1)
Count start condition
The WDTON bit in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
Count stop condition
None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Operation at time of underflow
Registers, bits
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
• When setting the CSPPRO bit in the CSPR register to 1 (count
(2)
source protection mode is enabled) , the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
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17.Timers
17. Timers
The MCU has two 8-bit timers with 8-bit prescalers and one 16-bit timer. Additionally, a timer with a 4-bit counter and
an 8-bit counter are implemented in the R8C/2H Group. The two 8-bit timers with 8-bit prescalers are timer RA and
timer RB. These timers contain a reload register to store the default value of the counter. The one 16-bit timer is timer
RF and have input capture and output compare functions. The 4-bit and 8-bit counters in the R8C/2H Group compose
timer RE, which has an output compare function. All the timers operate independently.
Table 17.1 lists Functional Comparison of Timers.
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17.Timers
Table 17.1
Functional Comparison of Timers
Timer RE(2)
4-bit counter
Item
Timer RA
Timer RB
Timer RF
Configuration
8-bit timer with 8-bit
8-bit timer with 8-bit
16-bit timer (with
input capture and
output compare)
prescaler (with reload prescaler (with reload 8-bit counter
register)
register)
Decrement
Count
Decrement
Increment
Increment
Count sources
• f1
• f1
• f2
• f8
• f4
• f1
• f2
• f8
• f8
• f8
• f32
• f32
• fOCO
• Timer RA underflow • fC4
• fC32(3)
Function Count of the Timer mode
Timer mode
—
—
—
Output compare
mode
internal count
source
Count of the Event counter mode
—
—
—
externalcount
source
External
pulse width/
period
Pulse width
Input capture mode
measurement mode,
pulse period
measurement measurement mode
Pulse output mode(1)
,
PWM output
Programmable
waveform generation
mode
Programmable one-
shot generation mode,
Programmable wait
one-shot generation
mode
Output compare
mode(1)
Output compare
mode
Event counter mode(1)
—
One-shot
waveform
output
—
—
Timer
Timer mode (only fC32
count)
TRAIO
—
Real-time clock
mode
—
—
—
Input pin
TRFI
INT0
TRBO
Output pin
TRAO
TRFO00 to TRFO02,
TRAIO
Timer RA interrupt,
INT1 interrupt
TRFO10 to TRFO11
Related interrupt
Timer RB interrupt,
INT0 interrupt
Timer RE interrupt Timer RF interrupt,
Compare 0 interrupt,
Compare 1 interrupt,
Capture interrupt
Timer stop
NOTES:
Provided
Provided
Provided
Provided
1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L”
level widths of the pulses are the same.
2. Implemented in the R8C/2H Group only.
3. Available in the R8C/2H Group only.
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17.Timers
17.1 Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6
the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 17.1 shows a Block Diagram of Timer RA. Figures 17.2 and 17.3 show the registers associated with timer
RA.
Timer RA has the following five operating modes:
• Timer mode:
The timer counts the internal count source.
• Pulse output mode:
The timer counts the internal count source and outputs pulses of which
polarity inverted by underflow of the timer.
• Event counter mode:
The timer counts external pulses.
• Pulse width measurement mode:
• Pulse period measurement mode:
The timer measures the pulse width of an external pulse.
The timer measures the pulse period of an external pulse.
Data bus
TCK2 to TCK0
= 000b
Reload
register
Reload
register
TCKCUT
TMOD2 to TMOD0
= other than 010b
f1
f8
= 001b
= 010b
= 011b
= 100b
TCSTF
Underflow signal
Timer RA interrupt
fOCO
f2
Counter
Counter
TMOD2 to TMOD0
= 010b
fC32(1)
TRA register
TRAPRE register
TIPF1 to TIPF0
= 01b
= 10b
(timer)
(prescaler)
f1
f8
f32
= 11b
TMOD2 to TMOD0
= 011b or 100b
TIPF1 to TIPF0
= other than
000b
TIOSEL = 0
Digital
filter
Polarity
switching
Count control
circle
INT1/TRAIO (P1_7) pin
Measurement completion
signal
INT1/TRAIO (P1_5) pin
= 00b
TIOSEL = 1
TMOD2 to TMOD0 = 001b
TEDGSEL = 1
TOPCR
Q
Q
Toggle flip-flop CK
CLR
TOENA
TEDGSEL = 0
Write to TRAMR register
Write 1 to TSTOP bit
TRAOSEL = 0
TRAO (P3_7) pin
TRAOSEL = 1
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
TRAOSEL: Bit in the PINSR2 register
NOTE:
1. Available in the R8C/2H Group only.
Figure 17.1
Block Diagram of Timer RA
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17.Timers
Timer RA Control Register(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRACR
Address
0100h
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
Timer RA count start bit(1)
0 : Count stops
1 : Count starts
0 : Count stops
1 : During count
TSTART
TCSTF
TSTOP
Timer RA count status flag(1)
RO
RW
—
Timer RA count forcible stop
bit(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
—
(b3)
Active edge judgment
0 : Active edge not received
flag(3, 5)
1 : Active edge received
TEDGF
TUNDF
RW
(end of measurement period)
Timer RA underflow flag(3, 5)
0 : No underflow
1 : Underflow
RW
—
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. Ref er to
.
17.1.6 Notes on Timer RA
2. When the TSTOPbit is set to 1, bits TSTART and TCSTF and registers TRAPREand TRA are set to the values after a
reset.
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAIOC
Address
0101h
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
TRAIO polarity sw itch bit
Function varies depending on operating mode.
TEDGSEL
TOPCR
TOENA
TIOSEL
TRAIO output control bit
TRAO output enable bit
RW
RW
RW
RW
—
____
INT1/TRAIO select bit
TIPF0
TIPF1
—
(b7-b6)
TRAIO input filter select bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 17.2
Registers TRACR and TRAIOC
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17.Timers
Timer RA Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAMR
Bit Symbol
Address
0102h
Bit Name
After Reset
00h
Function
RW
RW
Timer RA operating mode
b2 b1 b0
0 0 0 : Timer mode
select bits
TMOD0
TMOD1
TMOD2
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse w idth measurement mode
1 0 0 : Pulse period measurement mode
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
RW
RW
—
—
(b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RA count source
select bits
b6 b5 b4
0 0 0 : f1
0 0 1 : f8
TCK0
TCK1
RW
0 1 0 : fOCO
0 1 1 : f2
RW
1 0 0 : fC32(2)
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
TCK2
RW
RW
Timer RA count source
cutoff bit
0 : Provides count source
1 : Cuts off count source
TCKCUT
NOTES:
1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
2. Do not set in the R8C/2J Group.
Timer RA Prescaler Register
b7
b0
Symbol
TRAPRE
Mode
Address
0103h
Function
After Reset
FFh(1)
Setting Range
00h to FFh
00h to FFh
00h to FFh
RW
RW
RW
RW
Timer mode
Counts an internal count source
Counts an internal count source
Counts an external count source
Counts internal count source
Pulse output mode
Event counter mode
Pulse w idth
measurement mode
00h to FFh
RW
Pulse period
measurement mode
00h to FFh
RW
NOTE:
1. When the TSTOPbit in the TRACR register is set to 1, the TRAPREregister is set to FFh.
Timer RA Register
b7
b0
Symbol
TRA
Address
0104h
After Reset
FFh(1)
Setting Range
Mode
Function
Counts on underflow of timer RA prescaler
register
RW
RW
All modes
00h to FFh
NOTE:
1. When the TSTOPbit in the TRACR register is set to 1, the TRA register is set to FFh.
Figure 17.3
Registers TRAMR, TRAPRE, and TRA
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17.Timers
17.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode
Specifications).
Figure 17.4 shows TRAIOC Register in Timer Mode.
Table 17.2
Timer Mode Specifications
Item
Specification
(1)
Count sources
f1, f2, f8, fOCO, fC32
Count operations
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Divide ratio
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
Count start condition
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
Programmable I/O port, or INT1 interrupt input
Programmable I/O port
function
TRAO pin function
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
NOTE:
1. Available in the R8C/2H Group only.
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
After Reset
00h
Function
RW
RW
TRAIO polarity sw itch bit
Set to 0 in timer mode.
TEDGSEL
TOPCR
TOENA
TIOSEL
TRAIO output control bit
TRAO output enable bit
RW
RW
RW
RW
—
____
____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
____
1 : INT1/TRAIO pin (P1_5)
TIPF0
TIPF1
—
(b7-b6)
TRAIO input filter select bits Set to 0 in timer mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 17.4
TRAIOC Register in Timer Mode
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17.Timers
17.1.1.1 Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 17.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
Count source
After writing, the reload register is
written to at the first count source.
Reloads register of
Previous value
New value (01h)
timer RA prescaler
Reload at
second count
source
Reload at
underflow
Counter of
06h
05h
04h
01h
00h
01h
00h
01h
00h
01h
00h
timer RA prescaler
After writing, the reload register is
written to at the first underflow.
Reloads register of
timer RA
Previous value
03h
New value (25h)
Reload at the second underflow
25h 24h
Counter of timer RA
02h
IR bit in TRAIC
register
0
The IR bit remains unchanged until underflow is
generated by a new value.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
Figure 17.5
Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
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17.Timers
17.1.2 Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode
Specifications).
Figure 17.6 shows TRAIOC Register in Pulse Output Mode.
Table 17.3
Pulse Output Mode Specifications
Item
Specification
(2)
Count sources
f1, f2, f8, fOCO, fC32
Count operations
• Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
(1)
INT1/TRAIO pin
Pulse output, programmable output port, or INT1 interrupt
function
(1)
Programmable I/O port or inverted output of TRAIO
The count value can be read by reading registers TRA and TRAPRE.
TRAO pin function
Read from timer
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write Control
during Count Operation).
Select functions
• TRAIO output polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse
(1)
output.
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO pin
(selectable by the TOENA bit in the TRAIOC register).
• TRAO pin select function
P3_7 is selected by the TRAOSEL bit in the PINSR2 register.
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
• INT1/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
NOTES:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
2. Available in the R8C/2H Group only.
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17.Timers
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
After Reset
00h
Function
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
RW
RW
TRAIO polarity sw itch bit
TEDGSEL
TRAIO output control bit
TRAO output enable bit
0 : TRAIO output
TOPCR
RW
RW
RW
1 : Port P1_7 or P1_5
0 : Port P3_7
1 : TRAO output
TOENA
TIOSEL
(inverted TRAIO output from P3_7)
____
____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
____
1 : INT1/TRAIO pin (P1_5)
TIPF0
TIPF1
TRAIO input filter select bits Set to 0 in pulse output mode.
RW
RW
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Figure 17.6
TRAIOC Register in Pulse Output Mode
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17.Timers
17.1.3 Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 17.4 Event
Counter Mode Specifications).
Figure 17.7 shows TRAIOC Register in Event Counter Mode.
Table 17.4
Event Counter Mode Specifications
Item
Specification
Count source
Count operations
External signal which is input to TRAIO pin (active edge selectable by a program)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
Count source input (INT1 interrupt input)
function
(1)
Programmable I/O port or pulse output
TRAO pin function
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write Control
during Count Operation).
Select functions
• NT1 input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
(1)
underflows (selectable by the TOENA bit in the TRAIOC register).
• TRAO pin select function
P3_7 is selected by the TRAOSEL bit in the PINSR2 register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
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17.Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
After Reset
00h
Function
RW
RW
TRAIO polarity sw itch bit
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
TEDGSEL
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”
TRAIO output control bit
TRAO output enable bit
Set to 0 in event counter mode.
TOPCR
TOENA
TIOSEL
RW
RW
RW
0 : Port P3_7
1 : TRAO output
____
____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF0
TIPF1
RW
—
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 17.7
TRAIOC Register in Event Counter Mode
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17.Timers
17.1.4 Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 17.5 Pulse Width Measurement Mode Specifications).
Figure 17.8 shows TRAIOC Register in Pulse Width Measurement Mode and Figure 17.9 shows an Operating
Example of Pulse Width Measurement Mode.
Table 17.5
Pulse Width Measurement Mode Specifications
Item Specification
(1)
Count sources
Count operations
f1, f2, f8, fOCO, fC32
• Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Count start condition
Count stop conditions
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows [timer RA interrupt].
Interrupt request
generation timing
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
Select functions
• Measurement level select
• The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTE:
1. Available in the R8C/2H Group only.
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17.Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
After Reset
00h
Function
RW
RW
TRAIO polarity sw itch bit
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
Set to 0 in pulse w idth measurement mode.
TEDGSEL
TOPCR
TOENA
TIOSEL
TRAIO output control bit
TRAO output enable bit
RW
RW
RW
____
____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
1 : INT1/TRAIO pin (P1_5)
____
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
TIPF0
TIPF1
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
—
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 17.8
TRAIOC Register in Pulse Width Measurement Mode
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17.Timers
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
FFFFh
n
Count start
Underflow
Count stop
Count stop
Count start
Count start
Period
0000h
Set to 1 by program
1
0
TSTART bit in
TRACR register
1
0
Measured pulse
(TRAIO pin input)
Set to 0 when interrupt request is acknowledged, or set by program
Set to 0 by program
1
0
IR bit in TRAIC
register
1
0
TEDGF bit in
TRACR register
Set to 0 by program
1
0
TUNDF bit in
TRACR register
The above applies under the following conditions.
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Figure 17.9
Operating Example of Pulse Width Measurement Mode
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17.Timers
17.1.5 Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 17.6 Pulse Period Measurement Mode Specifications).
Figure 17.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 17.11 shows an
Operating Example of Pulse Period Measurement Mode.
Table 17.6
Pulse Period Measurement Mode Specifications
Item Specification
(2)
Count sources
Count operations
f1, f2, f8, fOCO, fC32
• Decrement
• After the active edge of the measured pulse is input, the contents of the read-
out buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
Count start condition
Count stop conditions
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
Interrupt request
generation timing
(1)
INT1/TRAIO pin function
Measured pulse input (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.1.1.1 Timer Write
Control during Count Operation).
Select functions
• Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTES:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
2. Available in the R8C/2H Group only.
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17.Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
After Reset
00h
Function
RW
RW
TRAIO polarity sw itch bit
0 : Measures measurement pulse from one
rising edge to next rising edge
1 : Measures measurement pulse from one
falling edge to next falling edge
TEDGSEL
TRAIO output control bit
TRAO output enable bit
Set to 0 in pulse period measurement mode.
TOPCR
TOENA
TIOSEL
RW
RW
RW
____
____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF0
TIPF1
RW
—
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 17.10 TRAIOC Register in Pulse Period Measurement Mode
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17.Timers
Underflow signal of
timer RA prescaler
Set to 1 by program
Starts counting
1
0
TSTART bit in
TRACR register
1
0
Measurement pulse
(TRAIO pin input)
TRA reloads
TRA reloads
Contents of TRA
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
01h 00h 0Fh 0Eh
Underflow
Retained
0Dh
Retained
09h
Contents of read-out
buffer(1)
0Fh 0Eh
0Bh 0Ah
0Dh
01h 00h 0Fh 0Eh
TRA read(3)
(Note 2)
(Note 2)
(Note 4)
1
0
TEDGF bit in
TRACR register
Set to 0 by program
(Note 6)
1
0
TUNDF bit in
TRACR register
Set to 0 by program
(Note 5)
1
0
IR bit in TRAIC
register
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 17.11 Operating Example of Pulse Period Measurement Mode
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17.Timers
17.1.6 Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA other than the TCSTF bit. Timer RA
(1)
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
(1)
During this time, do not access registers associated with timer RA other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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17.Timers
17.2 Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 17.7 to 17.10 the
Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 17.12 shows a Block Diagram of Timer RB. Figures 17.13 to 17.15 show the registers associated with timer
RB.
Timer RB has four operation modes listed as follows:
• Timer mode:
The timer counts an internal count source (peripheral
function clock or timer RA underflows).
• Programmable waveform generation mode:
• Programmable one-shot generation mode:
• Programmable wait one-shot generation mode:
The timer outputs pulses of a given width successively.
The timer outputs a one-shot pulse.
The timer outputs a delayed one-shot pulse.
Data bus
TRBSC
TRBPR
register
register
Reload
register
Reload
register
Reload
register
TCK1 to TCK0
TCKCUT
= 00b
f1
Timer RB interrupt
INT0 interrupt
= 01b
f8
Timer RA underflow
f2
Counter
Counter (timer RB)
(Timer)
= 10b
= 11b
TRBPRE register
(prescaler)
TMOD1 to TMOD0
= 10b or 11b
TSTART
TOSSTF
Input polarity
selected to be one
edge or both edges
INT0 pin
Digital filter
Polarity
select
INT0PL
INT0EN
INOSEG
INOSTG
TMOD1 to TMOD0
= 01b, 10b, 11b
TOPL = 1
Toggle
flip-flop
TRBOSEL = 0
Q
Q
TOCNT = 0
CK
CLR
TRBO (P1_3) pin
P3_1 bit in P3 register
TOPL = 0
TRBOSEL = 1
TOCNT = 1
TCSTF
TMOD1 to TMOD0
= 01b, 10b, 11b
TSTART, TCSTF: Bits in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
TRBOSEL: Bit in PINSR2 register
Figure 17.12 Block Diagram of Timer RB
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17.Timers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBCR
Bit Symbol
Address
0108h
After Reset
00h
Function
Bit Name
RW
RW
Timer RB count start bit(1)
0 : Count stops
1 : Count starts
TSTART
TCSTF
TSTOP
Timer RB count status flag(1) 0 : Count stops
RO
RW
—
1 : During count(3)
Timer RB count forcible stop When this bit is set to 1, the count is forcibly
bit(1, 2)
stopped. When read, its content is 0.
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. Ref er to
for precautions regarding bits TSTART, TCSTF and TSTOP.
17.2.5 Notes on Timer RB
2. When the TSTOPbit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable one-
shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB One-Shot Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBOCR
Bit Symbol
Address
0109h
Bit Name
After Reset
00h
Function
RW
RW
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger
TOSST
TOSSP
TOSSTF
generated. When read, its content is 0.
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot
pulses (including programmable w ait one-shot
RW
pulses) stops. When read, its content is 0.
Timer RB one-shot status
flag(1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
RO
—
—
(b7-b3)
NOTES:
1. When 1 is set to the TSTOPbit in the TRBCR register, the TOSSTF bit is set to 0.
2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
Figure 17.13 Registers TRBCR and TRBOCR
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b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBIOC
Address
010Ah
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
Timer RB output level select Function varies depending on operating mode.
bit
TOPL
Timer RB output sw itch bit
TOCNT
INOSTG
INOSEG
RW
RW
RW
—
One-shot trigger control bit
One-shot trigger polarity
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4)
Timer RB Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBMR
Address
010Bh
Bit Name
Timer RB operating mode
select bits(1)
After Reset
00h
Function
Bit Symbol
RW
RW
b1 b0
0 0 : Timer mode
TMOD0
TMOD1
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable w ait one-shot generation mode
RW
—
(b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Timer RB w rite control bit(2) 0 : Write to reload register and counter
1 : Write to reload register only
TWRC
RW
Timer RB count source
b5 b4
select bits(1)
0 0 : f1
0 1 : f8
TCK0
RW
RW
1 0 : Timer RA underflow
1 1 : f2
TCK1
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Timer RB count source
0 : Provides count source
1 : Cuts off count source
TCKCUT
NOTES:
RW
cutoff bit(1)
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
Figure 17.14 Registers TRBIOC and TRBMR
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Timer RB Prescaler Register(1)
17.Timers
b7
b0
Symbol
TRBPRE
Mode
Address
010Ch
After Reset
FFh
Setting Range
00h to FFh
Function
Counts an internal count source or timer RA
underflow s
RW
RW
Timer mode
Programmable w aveform
generation mode
Programmable one-shot
generation mode
Programmable w ait one-shot
generation mode
00h to FFh
00h to FFh
00h to FFh
RW
RW
RW
NOTE:
1. When the TSTOPbit in the TRBCR register is set to 1, the TRBPREregister is set to FFh.
Timer RB Secondary Register(3, 4)
b7
b0
Symbol
TRBSC
Mode
Address
010Dh
Function
After Reset
FFh
Setting Range
00h to FFh
RW
—
Disabled
Timer mode
Programmable w aveform
generation mode
Programmable one-shot
generation mode
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode (one-shot w idth is counted)
Counts timer RB prescaler underflow s(1)
Disabled
00h to FFh
00h to FFh
00h to FFh
WO(2)
—
WO(2)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
3. When the TSTOPbit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
4. To w rite to the TRBSC register, perform the follow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
Timer RB Primary Register(2)
b7
b0
Symbol
TRBPR
Mode
Address
010Eh
Function
After Reset
FFh
Setting Range
00h to FFh
RW
RW
Counts timer RB prescaler underflow s
Timer mode
Programmable w aveform
generation mode
Programmable one-shot
generation mode
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode (w ait period w idth is counted)
Counts timer RB prescaler underflow s(1)
00h to FFh
00h to FFh
00h to FFh
RW
RW
RW
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. When the TSTOPbit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Figure 17.15 Registers TRBPRE, TRBSC, and TRBPR
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17.Timers
17.2.1 Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
17.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 17.16 shows TRBIOC Register in Timer Mode.
Table 17.7
Timer Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
Divide ratio
1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
1 (count starts) is written to the TSTART bit in the TRBCR register.
Count start condition
Count stop conditions
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
TRBO pin function
When timer RB underflows [timer RB interrupt].
Programmable I/O port
INT0 pin function
Read from timer
Write to timer
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 17.2.1.1 Timer Write Control during Count Operation.)
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
Address
010Ah
Bit Name
After Reset
00h
Function
TRBIOC
Bit Symbol
RW
RW
Timer RB output level select Set to 0 in timer mode.
bit
TOPL
Timer RB output sw itch bit
TOCNT
INOSTG
INOSEG
RW
RW
RW
—
One-shot trigger control bit
One-shot trigger polarity
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4)
Figure 17.16 TRBIOC Register in Timer Mode
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17.Timers
17.2.1.1 Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload register.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 17.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten during Count Operation.
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When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
Previous value
New value (01h)
timer RB prescaler
Reload with
Reload on
underflow
the second
count source
Counter of
06h
05h
04h
01h
00h
01h
00h
01h
00h
01h
00h
timer RB prescaler
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
03h
New value (25h)
Reload on the second
underflow
Counter of timer RB
02h
25h
24h
IR bit in TRBIC
register
0
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
New value (01h)
Reload on
underflow
Counter of
06h
05h
04h
03h
02h
01h
00h
01h
00h
01h
00h
01h
00h
01h
timer RB prescaler
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
03h
New value (25h)
Reload on
underflow
Counter of timer RB
02h
01h
00h
25h
IR bit in TRBIC
register
0
Only the prescaler values are updated,
extending the duration until timer RB underflow.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 17.17 Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
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17.Timers
17.2.2 Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table
17.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 17.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 17.19 shows an
Operating Example of Timer RB in Programmable Waveform Generation Mode.
Table 17.8
Programmable Waveform Generation Mode Specifications
Item
Count sources
Specification
f1, f2, f8, timer RA underflow
Count operations
• Decrement
• When the timer underflows, it reloads the contents of the primary reload and secondary
reload registers alternately before the count continues.
Width and period of
output waveform
Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition
Count stop conditions
1 (count start) is written to the TSTART bit in the TRBCR register.
• 0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
TRBO pin function
In half a cycle of the count source, after timer RB underflows during the secondary period
(at the same time as the TRBO output change) [timer RB interrupt]
Programmable output port or pulse output
INT0 pin function
Read from timer
Write to timer
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE.(1)
• When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation,
values are written to the reload registers only.(2)
Select functions
• Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary and
secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P1_3 latch output is selected by the TOCNT bit in the TRBIOC
register.(3)
• TRBO pin select function
P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after writing to
the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
• When counting starts.
• When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following primary period.
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Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRBIOC
Bit Symbol
Address
010Ah
Bit Name
After Reset
00h
Function
RW
RW
Timer RB output level select 0 : Outputs “H” for primary period
bit
Outputs “L” for secondary period
Outputs “L” w hen the timer is stopped
1 : Outputs “L” for primary period
Outputs “H” for secondary period
Outputs “H” w hen the timer is stopped
TOPL
Timer RB output sw itch bit
0 : Outputs timer RB w aveform
TOCNT
INOSTG
INOSEG
RW
RW
RW
—
1 : Outputs value in P1_3 port register
One-shot trigger control bit Set to 0 in programmable w aveform generation
mode.
One-shot trigger polarity
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4)
Figure 17.18 TRBIOC Register in Programmable Waveform Generation Mode
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17.Timers
Set to 1 by program
1
0
TSTART bit in TRBCR
register
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads
Timer RB primary reloads
Counter of timer RB
01h
00h
02h
01h
00h
01h
00h
02h
Set to 0 when interrupt
request is acknowledged,
or set by program.
1
0
IR bit in TRBIC
register
Set to 0 by program
1
0
TOPL bit in TRBIO
register
Waveform
Waveform output inverted
Waveform output starts
output starts
1
0
TRBO pin output
Primary period
Secondary period
Primary period
Initial output is the same level
as during secondary period.
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 17.19 Operating Example of Timer RB in Programmable Waveform Generation Mode
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17.Timers
17.2.3 Programmable One-shot Generation Mode
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 17.9 Programmable One-Shot Generation Mode
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 17.20 shows TRBIOC Register in Programmable One-Shot Generation Mode. Figure 17.21 shows an
Operating Example of Programmable One-Shot Generation Mode.
Table 17.9
Programmable One-Shot Generation Mode Specifications
Item
Count sources
Specification
f1, f2, f8, timer RA underflow
Count operations
• Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
output time
(n+1)(m+1)/fi
fi: Count source frequency,
(2)
n: Setting value in TRBPRE register, m: Setting value in TRBPR register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)
Interrupt request
generation timing
TRBO pin function
In half a cycle of the count source, after the timer underflows (at the same time as
the TRBO output ends) [timer RB interrupt]
Pulse output
INT0 pin functions
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer
Write to timer
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
(1)
following reload).
Select functions
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 17.2.3.1 One-Shot Trigger Selection.
• TRBO pin select function
P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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17.Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
Address
010Ah
Bit Name
Timer RB Output Level
Select Bit
After Reset
00h
Function
RW
RW
0 : Outputs one-shot pulse “H”
Outputs “L” w hen the timer is stopped
1 : Outputs one-shot pulse “L”
TOPL
Outputs “H” w hen the timer is stopped
Timer RB Output Sw itch Bit Set to 0 in programmable one-shot generation
TOCNT
INOSTG
INOSEG
RW
RW
RW
—
mode.
____
One-Shot Trigger Control
Bit(1)
0 : INT0 pin one-shot trigger disabled
____
1 : INT0 pin one-shot trigger enabled
One-Shot Trigger Polarity
0 : Falling edge trigger
1 : Rising edge trigger
Select Bit(1)
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, its content is 0.
NOTE:
1. Refer to
.
17.2.3.1 One-Shot Trigger Selection
Figure 17.20 TRBIOC Register in Programmable One-Shot Generation Mode
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Set to 1 by program
1
0
TSTART bit in TRBCR
register
Set to 0 when
counting ends
Set to 1 by INT0 pin
input trigger
Set to 1 by program
1
0
TOSSTF bit in TRBOCR
register
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Timer RB primary reloads
Timer RB primary reloads
Count starts
Count starts
Counter of timer RB
01h
00h
01h
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program
1
0
IR bit in TRBIC
register
Set to 0 by program
1
0
TOPL bit in
TRBIOC register
Waveform output starts Waveform output ends
Waveform output starts Waveform output ends
1
0
TRBIO pin output
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 17.21 Operating Example of Programmable One-Shot Generation Mode
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17.Timers
17.2.3.1 One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 13. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
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17.Timers
17.2.4 Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 17.10 Programmable Wait One-Shot
Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only
once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length
of time equal to the setting value in the TRBPR register.
Figure 17.22 shows TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 17.23 shows
an Operating Example of Programmable Wait One-Shot Generation Mode.
Table 17.10 Programmable Wait One-Shot Generation Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the contents of
timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents
of timer RB primary before the count completes and the TOSSTF bit is set to 0
(one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it
stops.
Wait time
(n+1)(m+1)/fi
fi: Count source frequency
(2)
n: Value set in the TRBPRE register, m Value set in the TRBPR register
One-shot pulse output time
Count start conditions
(n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger
is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).
Interrupt request generation
timing
In half a cycle of the count source after timer RB underflows during secondary period
(complete at the same time as waveform output from the TRBO pin) [timer RB
interrupt].
TRBO pin function
INT0 pin functions
Pulse output
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer
Write to timer
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(1)
Select functions
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse
waveform.
• One-shot trigger select function
Refer to 17.2.3.1 One-Shot Trigger Selection.
• TRBO pin select function
P1_3 is selected by the TRBOSEL bit in the PINSR2 register.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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17.Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
Address
010Ah
Bit Name
After Reset
00h
Function
RW
RW
Timer RB output level select 0: Outputs one-shot pulse “H”.
bit
Outputs “L” w hen the timer stops or during
w ait.
TOPL
1: Outputs one-shot pulse “L”.
Outputs “H” w hen the timer stops or during
w ait.
Timer RB output sw itch bit
One-shot trigger control bit(1)
Set to 0 in programmable w ait one-shot generation
TOCNT
INOSTG
INOSEG
RW
RW
RW
—
mode.
____
0 : INT0 pin one-shot trigger disabled
____
1 : INT0 pin one-shot trigger enabled
One-shot trigger polarity
select bit(1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Falling edge trigger
1 : Rising edge trigger
—
(b7-b4)
NOTE:
1. Ref er to
.
17.2.3.1 One-Shot Trigger Selection
Figure 17.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode
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17.Timers
Set to 1 by program
1
0
TSTART bit in TRBCR
register
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
Set to 0 when
counting ends
1
0
TOSSTF bit in TRBOCR
register
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads
Timer RB primary reloads
Count starts
Counter of timer RB
01h
00h
04h
03h
02h
01h
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program.
1
0
IR bit in TRBIC
register
Set to 0 by program
1
0
TOPL bit in
TRBIOC register
Wait starts
Waveform output starts
Waveform output ends
1
0
TRBIO pin output
Wait
(primary period)
One-shot pulse
(secondary period)
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 17.23 Operating Example of Programmable Wait One-Shot Generation Mode
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17.Timers
17.2.5 Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
(1)
During this time, do not access registers associated with timer RB other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
(1)
During this time, do not access registers associated with timer RB other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
17.2.5.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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17.Timers
17.2.5.2 Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 17.24 and 17.25.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 17.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
Primary period
Secondary period
TRBO pin output
IR bit in
Interrupt request is
acknowledged
(a)
Ensure sufficient time
TRBIC register
(b)
Interrupt
Instruction in
Set the secondary and then
Interrupt request
is generated
sequence interrupt routine
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 17.24 Workaround Example (a) When Timer RB interrupt is Used
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• Workaround example (b):
17.Timers
As shown in Figure 17.25 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
Primary period
Secondary period
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
Upon detecting (i), set the secondary and
then the primary register immediately.
is detected at the end of the
secondary period.
Figure 17.25 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
17.2.5.3 Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
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17.Timers
17.2.5.4 Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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17.Timers
17.3 Timer RE (for R8C/2H Group only)
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
• Real-time clock mode
Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
• Output compare mode
Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
Timer RE is not implemented in the R8C/2J Group.
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17.Timers
17.3.1 Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 17.26 shows
a Block Diagram of Real-Time Clock Mode and Table 17.11 lists the Real-Time Clock Mode Specifications.
Figures 17.27 to 17.31 and 17.33 to 17.35 show the Registers Associated with Real-Time Clock Mode. Table
17.12 lists the Interrupt Sources, Figure 17.32 shows the Definition of Time Representation and Figure 17.36
shows the Operating Example in Real-Time Clock Mode.
RCS6 to RCS4
= 000b
f2
= 001b
TREOSEL2=0
TREOSEL2=1
fC
f4
f8
= 010b
= 100b
= 011b
TREO (P6_5)
pin
TOENA
(1/256)
(1/16)
(1s) Overflow
fC4
1/2
4-bit counter
8-bit counter
(8.192kHz)
PLUS
MIN US
Data
(D5 to D0)
TREOPR
register
Data bus
Overflow
Overflow
Overflow
TRESEC
register
TREMIN
register
TREHR
register
TREWK
register
000
H12_H24 PM
WKIE
bit
bit
Timing
control
Timer RE
interrupt
DYIE
HRIE
INT
bit
MNIE
SEIE
BSY
bit
TOENA, H12_H24, PM, INT: Bits in TRECR1 register
SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register
BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register
RCS4 to RCS6: Bits in TRECSR register
TREOSEL2: Bit in PINSR4 register
Figure 17.26 Block Diagram of Real-Time Clock Mode
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17.Timers
Table 17.11 Real-Time Clock Mode Specifications
Item
Specification
Count source
fC4
Increment
Count operation
Count start condition
Count stop condition
1 (count starts) is written to TSTART bit in TRECR1 register
0 (count stops) is written to TSTART bit in TRECR1 register
Interrupt request generation Select any one of the following:
timing
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
TREO pin function
Read from timer
Programmable I/O ports or output of f2, fC, f4, f8 or, 1Hz
When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
Write to timer
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
Select function
• 12-hour mode/24-hour mode switch function
• Counter precision adjustment function
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17.Timers
Timer RE Second Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
After Reset
Undefined
Setting
Range
Bit Symbol
Bit Name
Function
RW
SC00
SC01
SC02
SC03
SC10
SC11
SC12
1st digit of second count bits
Count 0 to 9 every second. When the 0 to 9
RW
RW
RW
RW
RW
RW
RW
digit moves up, 1 is added to the 2nd (BCD
digit of second.
code)
2nd digit of second count bits When counting 0 to 5, 60 seconds
are counted.
0 to 5
(BCD
code)
Timer RE busy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
RO
Figure 17.27 TRESEC Register in Real-Time Clock Mode
Timer RE Minute Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
After Reset
Undefined
Setting
Range
Bit Symbol
Bit Name
Function
RW
MN00
MN01
MN02
MN03
MN10
MN11
MN12
1st digit of minute count bits
Count 0 to 9 every minute. When the 0 to 9
RW
RW
RW
RW
RW
RW
RW
digit moves up, 1 is added to the 2nd (BCD
digit of minute.
code)
2nd digit of minute count bits
Timer RE busy flag
When counting 0 to 5, 60 minutes are 0 to 5
counted.
(BCD
code)
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
RO
Figure 17.28 TREMIN Register in Real-Time Clock Mode
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17.Timers
Timer RE Hour Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREHR
Address
011Ah
After Reset
X0XXXXXXb
Setting
Range
Bit Symbol
Bit Name
Function
RW
HR00
HR01
HR02
HR03
1st digit of hour count bits
Count 0 to 9 every hour. When the
0 to 9
RW
RW
RW
RW
digit moves up, 1 is added to the 2nd (BCD
digit of hour.
code)
2nd digit of hour count bits
Count 0 to 1 w hen the H12_H24 bit is 0 to 2
set to 0 (12-hour mode). (BCD
Count 0 to 2 w hen the H12_H24 bit is code)
set to 1 (24-hour mode).
HR10
RW
RW
—
HR11
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer REbusy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
RO
Figure 17.29 TREHR Register in Real-Time Clock Mode
Timer RE Day of Week Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREWK
Address
011Bh
Bit Name
After Reset
X0000XXXb
Function
Bit Symbol
RW
RW
b2 b1 b0
Day of w eek count bits
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
WK0
WK1
WK2
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
RW
1 1 0 : Saturday
1 1 1 : Do not set.
RW
—
—
(b6-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer REbusy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
RO
Figure 17.30 TREWK Register in Real-Time Clock Mode
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17.Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
011Ch
Bit Name
After Reset
XXX0X0X0b
Function
TRECR1
Bit Symbol
—
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b0)
Timer REcount status flag
TREO pin output enable bit
Interrupt request timing bit
Timer REreset bit
0 : Count stopped
1 : Counting
0 : Disable clock output
1 : Enable clock output
TCSTF
TOENA
INT
RO
RW
RW
Set to 1 in real-time clock mode.
When setting this bit to 0, after setting it to 1, the
follow ings w ill occur.
• Regis ters TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
TRERST
RW
RW
A.m./p.m. bit
When the H12_H24 bit is set to 0
(12-hour mode)(1)
0 : a.m.
1 : p.m.
PM
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
Operating mode select bit
Timer REcount start bit
0 : 12-hour mode
1 : 24-hour mode
0 : Count stops
1 : Count starts
H12_H24
RW
RW
TSTART
NOTE:
1. This bit is automatically modified w hile timer REcounts.
Figure 17.31 TRECR1 Register in Real-Time Clock Mode
Noon
H12_H24 bit = 1
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17
10 11
(24-hour mode)
Contents of
TREHR Register
H12_H24 bit = 0
(12-hour mode)
0
1
2
3
4
5
0 (a.m.)
1 (p.m.)
Contents of PM bit
000 (Sunday)
Contents in TREWK register
Date changes
H12_H24 bit = 1
18 19 20 21 22 23
10 11
0
0
1
1
2
2
3
3
⋅⋅⋅
⋅⋅⋅
(24-hour mode)
Contents of
TREHR Register
H12_H24 bit = 0
(12-hour mode)
6
7
8
9
1 (p.m.)
000 (Sunday)
0 (a.m.)
001 (Monday)
⋅⋅⋅
⋅⋅⋅
Contents of PM bit
Contents in TREWK register
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 17.32 Definition of Time Representation
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Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECR2
Bit Symbol
Address
011Dh
Bit Name
Periodic interrupt triggered every
second enable bit(1)
After Reset
00XXXXXXb
Function
0 : Disable periodic interrupt triggered
every second
RW
RW
SEIE
MNIE
HRIE
DYIE
1 : Enable periodic interrupt triggered
every second
Periodic interrupt triggered every
minute enable bit(1)
0 : Disable periodic interrupt triggered
every minute
1 : Enable periodic interrupt triggered
every minute
RW
RW
RW
RW
Periodic interrupt triggered every
hour enable bit(1)
0 : Disable periodic interrupt triggered
every hour
1 : Enable periodic interrupt triggered
every hour
Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered
enable bit(1)
every day
1 : Enable periodic interrupt triggered
every day
Periodic interrupt triggered every
w eek enable bit(1)
0 : Disable periodic interrupt triggered
every w eek
1 : Enable periodic interrupt triggered
every w eek
WKIE
Compare match interrupt enable bit
Set to 0 in real-time clock mode.
COMIE
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6)
NOTE:
1. Do not set multiple enable bits to 1 (enable interrupt).
Figure 17.33 TRECR2 Register in Real-Time Clock Mode
Table 17.12 Interrupt Sources
Factor
Interrupt Source
Value in TREWK register is set to 000b (Sunday)
(1-week period)
Interrupt Enable Bit
Periodic interrupt
WKIE
DYIE
HRIE
MNIE
SEIE
triggered every week
Periodic interrupt
TREWK register is updated (1-day period)
triggered every day
Periodic interrupt
TREHR register is updated (1-hour period)
TREMIN register is updated (1-minute period)
TRESEC register is updated (1-second period)
triggered every hour
Periodic interrupt
triggered every minute
Periodic interrupt
triggered every second
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17.Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 0
Symbol
Address
011Eh
Bit Name
After Reset
00001000b
Function
TRECSR
Bit Symbol
RW
RW
Count source select bits
Set to 00b in real-time clock mode.
RCS0
RCS1
RCS2
RCS3
RCS4
RCS5
RW
RW
RW
RW
RW
4-bit counter select bit
Set to 0 in real-time clock mode.
Set to 1 in real-time clock mode.
Real-time clock mode select bit
Clock output select bits(1)
b6 b5 b4
0 0 0 : f2
0 0 1 : fC
0 1 0 : f4
0 1 1 : 1Hz
1 0 0 : f8
RCS6
RW
—
Other than above : Do not set.
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 17.34 TRECSR Register in Real-Time Clock Mode
Timer RE Real-Time Clock Precision Adjust Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREOPR
Address
011Fh
After Reset
00h
Setting
Range
00h to 3Ch RW
Bit Symbol
Bit Name
Function
RW
D0
D1
D2
D3
D4
D5
8-bit counter adjust bit
The correction value of the 8-bit
counter is stored.
When read, the content is 000000b.
RW
RW
RW
RW
RW
8-bit counter subtract bit(2)
8-bit counter add bit(2)
When this bit is set to 1, the correction value set
by D0 to D5 is subtracted from the 8-bit counter
value.
MINUS
PLUS
RW
RW
When read, the content is 0.
When this bit is set to 1, the correction value set
by D0 to D5 is added to the 8-bit counter value.
When read, the content is 0.
NOTES:
1. Use the MOV instruction for setting the TREOPR register.
Allow a period (s) of the XCIN clock × 2064 or more betw een w rites to the TREOPR register.
2. Write 1 to either the MINUS bit or the PLUS bit only once during each interrupt routine for the
w eek/day/hour/minute/second cycle.
When 00b or 11b is w ritten to bits MINUS and PLUS, the 8-bit counter value is not added or subtracted.
Figure 17.35 TREOPR Register in Real-Time Clock Mode
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17.Timers
1s
Approx.
62.5 ms
Approx.
62.5 ms
BSY bit
Bits SC12 to SC00 in
TRESEC register
58
59
00
04
Bits MN12 to MN00 in
TREMIN register
03
Bits HR11 to HR00 in
TREHR register
(Not changed)
1
0
PM bit in
(Not changed)
(Not changed)
TRECR1 register
Bits WK2 to WK0 in
TREWK register
Set to 0 by acknowledgement
of interrupt request
or a program
1
0
IR bit in TREIC register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
1
0
IR bit in TREIC register
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 17.36 Operating Example in Real-Time Clock Mode
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17.Timers
17.3.2 Output Compare Mode
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and
compare value match is detected with the 8-bit counter. Figure 17.37 shows a Block Diagram of Output
Compare Mode and Table 17.13 lists the Output Compare Mode Specifications. Figures 17.38 to 17.42 show
the Registers Associated with Output Compare Mode, and Figure 17.43 shows the Operating Example in
Output Compare Mode.
RCS6 to RCS4
f4
f8
=000b
f2
=001b
=010b
TREOSEL2=0
TREOSEL2=1
RCS1 to RCS0
= 00b
fC
TREO (P6_5)
pin
=100b
=110b
TOENA
= 01b
= 10b
= 11b
RCS2 = 1
RCS2 = 0
4-bit
1/2
counter
8-bit
T Q
f32
counter
R
fC4
Reset
TRERST
Match
signal
Comparison
circuit
Timer RE interrupt
COMIE
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TREOSEL2: Bit in PINSR4 register
TRESEC
TREMIN
Data bus
Figure 17.37 Block Diagram of Output Compare Mode
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17.Timers
Table 17.13 Output Compare Mode Specifications
Item
Specification
Count sources
f4, f8, f32, fC4
• Increment
Count operations
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues.
The count value is held while count stops.
Count period
• When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
Count start condition
Count stop condition
1 (count starts) is written to the TSTART bit in the TRECR1 register
0 (count stops) is written to the TSTART bit in the TRECR1 register
Interrupt request generation When the 8-bit counter content matches with the TREMIN register content
timing
TREO pin function
Select any one of the following:
• Programmable I/O ports
• Output f2, fC, f4, or f8
• Compare output
Read from timer
Write to timer
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Selectable functions
• Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
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17.Timers
Timer RE Counter Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
Function
After Reset
Undefined
RW
RO
8-bit counter data can be read.
Although Timer REstops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
Figure 17.38 TRESEC Register in Output Compare Mode
Timer RE Compare Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
Function
After Reset
Undefined
RW
RW
8-bit compare data is stored.
Figure 17.39 TREMIN Register in Output Compare Mode
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17.Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
Address
011Ch
Bit Name
After Reset
XXX0X0X0b
Function
TRECR1
Bit Symbol
—
RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b0)
Timer REcount status flag
TREO pin output enable bit
Interrupt request timing bit
Timer REreset bit
0 : Count stopped
1 : Counting
0 : Disable clock output
1 : Enable clock output
TCSTF
TOENA
INT
RO
RW
RW
Set to 0 in output compare mode.
When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Regis ters TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
TRERST
PM
RW
A.m./p.m. bit
Set to 0 in output compare mode.
RW
RW
H12_H24 Operating mode select bit
Timer REcount start bit
0 : Count stops
1 : Count starts
TSTART
RW
Figure 17.40 TRECR1 Register in Output Compare Mode
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
TRECR2
Address
011Dh
Bit Name
Periodic interrupt triggered every
second enable bit
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every
hour enable bit
After Reset
00XXXXXXb
Function
Bit Symbol
RW
RW
Set to 0 in output compare mode.
SEIE
MNIE
HRIE
RW
RW
RW
RW
RW
—
Periodic interrupt triggered every
day enable bit
Periodic interrupt triggered every
w eek enable bit
DYIE
WKIE
COMIE
Compare match interrupt enable bit
0 : Disable compare match interrupt
1 : Enable compare match interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6)
Figure 17.41 TRECR2 Register in Output Compare Mode
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17.Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECSR
Bit Symbol
Address
011Eh
After Reset
00001000b
Function
Bit Name
RW
RW
Count source select bits(1)
b1 b0
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : fC4
RCS0
RCS1
RW
4-bit counter select bit
0 : Not used
1 : Used
Set to 0 in output compare mode.
RCS2
RCS3
RCS4
RW
RW
RW
Real-time clock mode select bit
Clock output select bits(2)
b6 b5 b4
0 0 0 : f2
0 0 1 : fC
0 1 0 : f4
1 0 0 : f8
1 1 0 : Compare output
Other than above : Do not set.
RCS5
RCS6
RW
RW
—
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. Write to bits RCS0 to RCS1 w hen the TCSTF bit in the TRECR1 register is set to 0 (count stopped).
2. Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 17.42 TRECSR Register in Output Compare Mode
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Count starts
Matched
Matched
Matched
TREMIN register
setting value
00h
Time
Set to 1 by a program
1
0
TSTART bit in
TRECR1 register
2 cycles of maximum count source
1
0
TCSTF bit in
TRECR1 register
Set to 0 by acknowledgement of interrupt request
or a program
1
0
IR bit in
TREIC register
1
0
TREO output
Output polarity is inverted
when the compare matches
The above applies under the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Set the TREOSEL2 bit in the PINSR4 register to 1 (enabled)
Figure 17.43 Operating Example in Output Compare Mode
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17.Timers
17.3.3 Notes on Timer RE (for R8C/2H Group only)
17.3.3.1 Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
(1)
1. During this time, do not access registers associated with timer RE other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, TRECSR,
and TREOPR.
17.3.3.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 17.44 shows a Setting Example in Real-Time Clock Mode.
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17.Timers
TRERST in TRECR1 register = 1
Timer RE register
and control circuit reset
TRERST in TRECR1 register = 0
TSTART in TRECR1 register = 0
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
Disable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 0
TREIC register ← 00h
(disable timer RE interrupt)
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR, TREWK,
and bits H12_H24, PM, and INT
in TRECR1 register
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Setting of TRECR2 register
Select interrupt source
Setting of TREIC register (IR bit ← 0,
select interrupt priority level)
Enable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 1
TSTART in TRECR1 register = 1
Start timer RE operation
TCSTF in
TRECR1 register = 1?
Figure 17.44 Setting Example in Real-Time Clock Mode
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17.Timers
17.3.3.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
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17.Timers
17.4 Timer RF
Timer RF is a 16-bit timer. The count source for timer RF is the operating clock that regulates the timing of timer
operations. Figure 17.45 shows a Block Diagram of Timer RF. Figure 17.46 shows a Block Diagram of CMP
Waveform Generation Unit. Figure 17.47 shows a Block Diagram of CMP Waveform Output Unit.
Timer RF has two modes: input capture mode and output compare mode. Figures 17.48 to 17.51 show the timer RF
associated registers.
For R8C/2H Group only
fC32
TIPF1 to TIPF0
= 01b
= 10b
= 11b
f1
f8
f32
Sampling clock
TRFC20 = 1
= other than
00b
Edge
detection
Digital
filter
Capture interrupt
TRFI
TRFC20 = 0
= 00b
Capture signal
Capture, Compare 0 register
TRFM0 register
Compare 0
Comparator
interrupt
CMP waveform
TRFO00
TRFO01
TRFO02
TRFO10
output unit
TCK1 to TCK0
CMP waveform
output unit
= 00b
= 01b
= 10b
f1
f8
f32
Timer RF
interrupt
Counter
CMP
waveform
generation
unit
CMP waveform
output unit
TRF register
CCLR = 1
TSTART
CCLR = 0
CMP waveform
output unit
TRFOSEL = 0
TRFOSEL = 1
Timer RF counter
clear signal
CMP waveform
output unit
TRFO11 (P3_7)
Compare 1
interrupt
Comparator
Compare 1 register
TRFM1 register
TSTART, TCK0 to TCK1: Bits in TRFCR0 register
TIPF0 to TIPF1, CCLR: Bits in TRFCR1 register
TRFC20: Bit in TRFCR2 register
TRFOSEL: Bit in PINSR4 register
Figure 17.45 Block Diagram of Timer RF
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TRFC14
TRFC15
Compare 0 interrupt signal
Compare 1 interrupt signal
TRFC16
TRFC17
TRFC17 to TRFC16
= 11b
= 10b
= 01b
“H”
“L”
Inverted
T
Latch
R
CMP output
(internal signal)
D
Q
Reset
TRFC15 to TRFC14
= 01b
= 10b
= 11b
Inverted
“L”
“H”
TRFC14 to TRFC17: Bits in TRFC1 register
Figure 17.46 Block Diagram of CMP Waveform Generation Unit
TRFOUT6 = 0
CMP output
TRFOUT0 = 1
TRFOUT0 = 0
(Internal signal)
Inverted
TRFOUT6 = 1
TRFO00
P1_0 bit
This diagram is a block diagram of the TRFO00 waveform output unit.
The TRFO01 to TRFO02 and TRFO10 to TRFO12 waveform output units have the same configuration.
TRFOUT0 and TRFOUT6: Bits in TRFOUT register
P1_0: Bit in P1 register
Figure 17.47 Block Diagram of CMP Waveform Output Unit
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Timer RF Register(1)
17.Timers
(b15)
b7
(b8)
b0
b7
b0
Symbol
TRF
Address
After Reset
0000h
0291h-0290h
Function
RW
RO
Count source increment .
0000h can be read w hen the TSTART bit is set to 0 (count stops).
Count value can be read w hen the TSTART bit is set to 1 (count starts).
NOTE:
1. Access the TRF register in 16-bit units.
Capture and Compare 0 Register(1)
(b15)
b7
(b8)
b0
b7
b0
Symbol
TRFM0
Address
After Reset
0000h(2)
Setting Range
029Dh-029Ch
Mode
Function
RW
RO
When the active edge of the measured
pulse is input, store the value in the TRF
register
Input capture mode
Output compare mode(3)
―
Store the value compared w ith TRF
register (counter)
0000h to FFFFh
RW
NOTES:
1. Access the TRFM0 register in 16-bit units.
2. When the TMOD bit in the TRFCR1 register is set to 1, the value is set to FFFFh.
3. When setting a value in the TRFM0 register, set the TMOD bit in the TRFCR1 register to 1 (output compare mode).
When the TMOD bit is set to 0 (input capture mode), no value can be w ritten.
Compare 1 Register(1)
(b15)
b7
(b8)
b0
b7
b0
Symbol
TRFM1
Address
After Reset
FFFFh
Setting Range
0000h to FFFFh
029Fh-029Eh
Mode
Function
Store the value compared w ith TRF
register (counter)
RW
RW
Output compare mode
NOTE:
1. Access the TRFM1 register in 16-bit units.
Figure 17.48 Registers TRF, TRFM0, and TRFM1
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Timer RF Control Register 2 (for R8C/2H Group only)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRFCR2
Bit Symbol
Address
0299h
Bit Name
After Reset
00h
Function
RW
RW
Timer RF capture input select bit
0 : TRFI pin input
1 : fC32
TRFC20
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
RW
—
(b4-b1)
—
(b6-b5)
—
(b7)
Reserved bits
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RF Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRFCR0
Bit Symbol
Address
029Ah
Bit Name
After Reset
00h
Function
RW
RW
Timer RF count start bit
0 : Count stops
1 : Count starts
TSTART
Timer RF count source select
bits(1)
b2 b1
TCK0
RW
RW
RW
RW
0 0 : f1
0 1 : f8
1 0 : f32
TCK1
1 1 : Do not set.
Capture polarity select bits(1)
b4 b3
TRFC03
TRFC04
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Do not set.
CMPoutput select bit 0 w hen
count stops
0 : TRFC06 bit disabled
Holds output level before count stops
1 : TRFC06 bit enabled
TRFC05
TRFC06
RW
CMPoutput select bit 1 w hen
count stops
Reserved bit
0 : “L” output w hen count stops
1 : “H” output w hen count stops
Set to 0.
RW
RW
—
(b7)
NOTE:
1. Rew rite this bit w hen the TSTART bit is set to 0 (count stops).
Figure 17.49 Registers TRFCR2 (for R8C/2H Group only) and TRFCR0
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17.Timers
Timer RF Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRFCR1
Address
029Bh
After Reset
00h
Function
Bit Symbol
Bit Name
RW
RW
TRFI filter select bits(1)
b1 b0
0 0 : No filter
TIPF0
TIPF1
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
TRF register count operation 0 : Free-running operation
select bit(2, 3)
1 : Set TRF register to 0000h w hen compare
CCLR
TMOD
RW
RW
1 is matched.
Timer RF operation mode
select bit(3)
0 : Input capture mode(2, 4)
1 : Output compare mode
Compare 0 output select
b5 b4 CMPoutput w hen compare 0 is matched
bits(2)
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
TRFC14
RW
RW
1 1 : “H”
TRFC15
TRFC16
Compare 1 output select
bits(2)
b7 b6 CMPoutput w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
TRFC17
NOTES:
1. If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined.
2. When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0.
3. When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD.
4. When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0)
and set the IR bit to 0 (no interrupt requested).
Figure 17.50 TRFCR1 Register
Timer RF Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRFOUT
Bit Symbol
Address
02FFh
Bit Name
After Reset
00h
Function
RW
RW
RW
RW
RW
RW
TRFOUT0 TRFO00 output enable bit
TRFOUT1 TRFO01 output enable bit
TRFOUT2 TRFO02 output enable bit
TRFOUT3 TRFO10 output enable bit
TRFOUT4 TRFO11 output enable bit
0 : Output disabled
1 : Output enabled
—
Reserved bit
Set to 0.
RW
RW
RW
(b5)
TRFO00 to TRFO02 output invert
bit
TRFO10 to TRFO11 output invert
bit
0 : Output not inverted
1 : Output inverted
TRFOUT6
TRFOUT7
Figure 17.51 TRFOUT Register
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17.Timers
17.4.1 Input Capture Mode
In input capture mode, the edge of the TRFI pin input signal or fC32 is used as a trigger to latch the timer value
and the width or the period of external signal is measured. The TRFI input is equipped with a digital filter, and
this prevents errors caused by noise or the like from occurring. Table 17.14 shows the Input Capture Mode
Specifications. Figure 17.52 shows an Operating Example in Input Capture Mode.
Table 17.14 Input Capture Mode Specifications
Item
Count sources
Count operations
Specification
f1, f8, f32
• Increment
• Transfer the value in the TRF register to the TRFM0 register at the valid
edge of the measured pulse.
Count period
1/fk × 65536 fk: Frequency of count source
The TSTART bit in the TRFCR0 register is set to 1 (count starts).
The TSTART bit in the TRFCR0 register is set to 0 (count stops).
Count start condition
Count stop condition
Interrupt request
generation timing
TRFI pin function
TRFO00 to TRFO02,
TRFO11 pin functions
• The valid edge of TRFI input or fC32 [capture interrupt]
• When timer RF overflows [timer RF interrupt]
Measured pulse input
Programmable I/O port
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
Read from timer
• The count value can be read out by reading the TRF register.
• The count value at the measured pulse valid edge input can be read out by
reading the TRFM0 register.
Write to timer
Select functions
Write to the TRF and TRFM0 registers is disabled.
(1)
• TRFI or fC32 polarity selected
Selects the valid edge of the measured pulse.
(Bits TRFC03 to TRFC04 in the TRFCR0 register.)
• Digital filter function
The TRFI input is sampled, and when the sampled input level matches as
three times, the level is determined.
Selects the sampling clock of the digital filter.
(Bits TIPF0 to TIPF1 in the TRFCR1 register.)
NOTE:
1. Available in the R8C/2H Group only.
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17.Timers
Overflow
FFFFh
Count starts
← Measurement value 2
←
value 3
Measurement
← Measurement value 1
0000h
Time
Set to 0 by
a program
Set to 1 by a program
When the count
stops, the value
is set to 0000h.
1
0
TSTART bit in
TRFCR0 register
The delay caused by digital filter and
one count source cycle delay (max.).
1
0
Measured pulse
(TRFI pin input)
Measured
Undefined
Measured
value 3
TRFM0 register
Measured value 2
Undefined
value 1
Set to 0 when interrupt request is acknowledged, or set by a program.
1
0
IR bit in
CAPIC register
Set to 0 when interrupt request is
acknowledged, or set by a program.
1
0
IR bit in
TRFIC register
Measurement value 2 -
measurement value 1
(10000h - measurement value 2) +
measurement value 3
The above applies under the following conditions.
Bits TRFC04 to TRFC03 in TRFCR0 register = 01b (Capture input polarity is set for falling edge.)
TRFC20 bit in TRFCR2 register = 0 (TRFI pin input) (Applicable to the R8C/2H Group only)
Figure 17.52 Operating Example in Input Capture Mode
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17.Timers
17.4.1.1 Digital Filter
The TRFI input is sampled, and when the sampled input level matches three times, its level is determined.
Select the digital filter function and sampling clock by the TRFCR1 register.
Figure 17.53 shows a Block Diagram of Digital Filter.
TIPF1 to TIPF0
= 01b
f1
= 10b
f8
= 11b
TMOD
f32
TRFC04 to TRFC03
Sampling clock
TIPF1 to TIPF0
= 01b, 10b, 11b
C
C
C
C
Match
detection
circuit
Edge
detection
circuit
TRFI input
signal
D
Q
D
Q
D
Q
D
Q
Latch
Latch
Latch
Latch
= 00b
Count source
C
D
Q
Latch
Clock period selected by
bits TIPF1 to TIPF0
Sampling clock
TRFI input signal
Recognition of the
signal change with
three times match
Input signal
through digital
filtering
Signal transmission delayed
up to five sampling clock
Transmission cannot be performed
without three times match because the
input signal is assumed to be noise.
TRFC03 to TRFC04: Bits in TRFCR0 register
TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register
Figure 17.53 Block Diagram of Digital Filter
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17.Timers
17.4.2 Output Compare Mode
In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0
match) or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output
pin.
Table 17.15 shows the Output Compare Mode Specifications. Table 17.16 shows the Output in Output Compare
Mode (Example of TRFO00 Pin). Figure 17.54 shows an Operating Example in Output Compare Mode. Figure
17.55 shows an Operating Example in Output Compare Mode (“L” and “H” Held Output in Count Stops).
Table 17.15 Output Compare Mode Specifications
Item
Count sources
Count operations
PWM waveform
Specification
f1, f8, f32
Increment
PWM period: 1/fk × (n + 1)
“L” level width: 1/fk × (m + 1)
“H” level width: 1/fk × (n - m)
fk: Frequency of count source
m: Value set in the TRFM0 register
n: Value set in the TRFM1 register
m + 1
n - m
It applies under the following conditions.
• CMP output “H” when compare 0 is matched
• CMP output “L” when compare 1 is matched
• CMP output not inverted
n + 1
Count start condition
Count stop condition
Interrupt request generation
timing
The TSTART bit in the TRFCR0 register is set to 1 (count starts).
The TSTART bit in the TRFCR0 register is set to 0 (count stops).
• When compare 0 match is generated [compare 0 interrupt]
• When compare 1 match is generated [compare 1 interrupt]
• When time RF overflows [timer RF interrupt].
TRFO00 to TRFO11 pin
functions
Counter value reset timing
Programmable I/O port or output-compare output
In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to 0000h at
compare 1 match) in the compare 1 matches.
Read from timer
• The count value can be read out by reading the TRF register.
• The value in the compare register can be read out by reading registers TRFM0 and
TRFM1.
Write to timer
Select functions
Write to the TRF register is disabled
• Output-compare output pin selected
Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to TRFO11
(bits TRFOUT0 to TRFOUT4 in the TRFOUT register).
• Output level at the compare match
Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the TRFCR1
register).
• Output level inverted
Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7 in the
TRFOUT register).
• Output level at the count stops
Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0 register).
• Timing to set the TRF register to 0000h
Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the TRFCR1
register).
• TRFO11 pin select function
P3_7 is selected by the TRFOSEL bit in the PINSR4 register.
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17.Timers
Table 17.16 Output in Output Compare Mode (Example of TRFO00 Pin)
Bit Setting Value
TRFO00 Output
TRFCR0 Register
TRFOUT Register
P1 Register
TRFC06 TRFC05 TSTART TRFOUT6 TRFOUT0
P1_0
1
1
Counting CMP output
X
X
X
X
1
1
0
1
1
1
Inverted output of
CMP output
“L” output
X
X
X
X
X
0
1
1
0
0
1
X
1
1
1
0
0
1
“H” output
Count
stops
Holds output level
before count stops
“L” output
0
1
1
1
0
0
X
X
1
1
1
1
“H” output
X: 0 or 1
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17.Timers
Match
Value set in
TRFM1 register
Count starts
Match
Match
Value set in
TRFM0 register
0000h
Time
Set to 1 by a program
When the count
stops, the value
is set to 0000h.
1
0
TSTART bit in
TRFCR0 register
Set to 0 when interrupt request is acknowledged,
or set by a program.
1
0
IR bit in
CMP0IC register
Set to 0 when interrupt request is
acknowledged, or set by a program.
1
0
IR bit in
CMP1IC register
1
0
TRFO00 output
TRFO10 output
1
0
The above applies under the following conditions.
TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops)
CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence)
TMOD bit in TRFCR1 register = 1 (output compare mode)
Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match)
Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match)
TRFOUT6 bit in TRFOUT register = 0 (not inverted)
TRFOUT7 bit in TRFOUT register = 1 (inverted)
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
P1_0 bit in P1 register = 1 (“H”)
P3_3 bit in P3 register = 1 (“H”)
Figure 17.54 Operating Example in Output Compare Mode
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17.Timers
Set to 0 by a program
Set to 1 by a program
1
0
P1_0 bit in
P1 register
1
0
P3_3 bit in
P3 register
CMP output
(internal signal)
TRFO00 output
TRFO10 output
The above applies under the following conditions.
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted)
TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO11 output inverted)
TSTART bit in TRFCR0 register = 1 (count starts)
Figure 17.55 Operating Example in Output Compare Mode (“L” and “H” Held Output in Count
Stops)
In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and
TRFO10 to TRFO11 during count operation. Note that the output waveform can be inverted for pins TRFO00
to TRFO02 or for pins TRFO10 to TRFO11. The output can also be fixed at “L” or “H” for individual pins for
a given period.
The behavior when count operation stops can be selected from the following two options: the output level
before the count stops is maintained, or output is fixed at “L” or “H”.
The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writing to the
TRFMi register causes the values to be stored in the compare i register in the following timing:
• If the TSTART bit is set to 0 (count stops)
Values are stored simultaneously with the write to the TRFMi register.
• If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running)
Values are stored when the TRF register (counter) overflows.
• If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at compare 1 match)
Values are stored when the compare 1 and TRF register (counter) values match.
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17.Timers
17.4.3 Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0
; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
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18. Serial Interface
18. Serial Interface
The serial interface in the R8C/2H Group consists of two channels (UART0 and UART2). The serial interface in the
R8C/2J Group consists of one channel (UART0). Each UARTi (i = 0 or 2) has an exclusive timer to generate the
transfer clock and operates independently.
Figure 18.1 shows a UARTi (i = 0 or 2 (for R8C/2H Group only)) Block Diagram. Figure 18.2 shows a UARTi
Transmit/Receive Unit.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 18.3 to 18.5 show the Registers Associated with UARTi.
UART2 is not implemented in the R8C/2J Group. The description about UART2 in this chapter applies to
the R8C/2H Group only.
UARTi
RXDi
TXDi
UART reception
Receive
clock
1/16
Reception control
circuit
CKDIR = 0
Internal
CLK1 to CLK0 = 00b
Clock
Transmit/
receive
unit
synchronous type
UART transmission
f1
f8
= 01b
= 10b
U0BRG register
1/(n0+1)
Transmit
clock
1/16
1/2
f32
Transmission
control circuit
Clock
External
synchronous type
CKDIR = 1
CKDIR = 0
CKDIR = 1
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
switch
circuit
CLKi
i = 0 or 2 (for the R8C/2H Group only)
CKDIR: Bit in UiMR register
CLK0 to CLK1: Bits in UiC0 register
Figure 18.1
UARTi (i = 0 or 2 (for R8C/2H Group only)) Block Diagram
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18. Serial Interface
Clock
synchronous
type
PRYE = 0
PAR
Clock
UART (7 bits)
UART (8 bits)
1SP
synchronous
type
disabled
UART (7 bits)
UARTi receive register
SP
PAR
RXDi
SP
PAR
Clock
UART
2SP
UART (9 bits)
enabled
synchronous
type
PRYE = 1
UART (8 bits)
UART (9 bits)
UiRB register
0
0
0
0
0
0
0
D8
D7 D6 D5 D4 D3 D2 D1 D0
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7 D6 D5 D4 D3 D2 D1 D0
UiTB register
D8
UART (8 bits)
UART (9 bits)
Clock
PRYE = 1
PAR
synchronous
type
UART (9 bits)
UART
2SP
1SP
enabled
SP
PAR
TXDi
SP
Clock
PAR
UART (7 bits)
UARTi transmit register
UART (7 bits)
synchronous
type
disabled
PRYE = 0
UART (8 bits)
i = 0 or 2 (for the R8C/2H Group only)
SP: Stop bit
PAR: Parity bit
Clock
0
synchronous
type
Figure 18.2
UARTi Transmit/Receive Unit
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18. Serial Interface
UARTi Transmit/Receive Mode Register (i = 0 or 2 (for R8C/2H Group only))
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0MR
Address
00A0h
After Reset
00h
U2MR
0160h
00h
Bit Symbol
Bit Name
Serial I/O mode select bits
Function
RW
RW
b2 b1 b0
SMD0
SMD1
SMD2
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
RW
RW
Internal/external clock select bit 0 : Internal clock
1 : External clock
CKDIR
STPS
RW
RW
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity select bit
Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
PRY
RW
Parity enable bit
Reserved bit
0 : Parity disabled
1 : Parity enabled
Set to 0.
PRY E
RW
RW
—
(b7)
UARTi Bit Rate Register (i = 0 or 2 (for R8C/2H Group only))(1, 2, 3)
b7
b0
Symbol
U0BRG
U2BRG
Address
00A1h
0161h
After Reset
Undefined
Undefined
Setting Range
00h to FFh
Function
Assuming the set value is n, UiBRG divides the count source by n+1
RW
WO
NOTES:
1. Write to this register w hile the serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to w rite to this register.
3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
Figure 18.3
Registers U0MR, U2MR and U0BRG, U2BRG
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18. Serial Interface
UARTi Transmit Buffer Register (i = 0 or 2 (for R8C/2H Group only))(1, 2)
(b15)
b7
(b8)
b0
b7
b0
Symbol
U0TB
U2TB
Address
00A3h-00A2h
0163h-0162h
After Reset
Undefined
Undefined
Function
RW
WO
—
(b8-b0)
Transmit data
—
(b15-b9)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
NOTES:
1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
2. Use the MOV instruction to w rite to this register.
UARTi Transmit/Receive Control Register 0 (i = 0 or 2 (for R8C/2H Group only))
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C0
U2C0
Address
00A4h
0164h
After Reset
00001000b
00001000b
Function
Bit Symbol
Bit Name
RW
RW
BRG count source select
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
bits(1)
CLK0
CLK1
RW
RW
RO
—
(b2)
Reserved bit
Set to 0.
Transmit register empty
flag
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
TXEPT
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Data output select bit
0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open-drain output
NCH
RW
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
CKPOL
UFORM
RW
RW
Transfer format select bit 0 : LSB first
1 : MSB first
NOTE:
1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 18.4
Registers U0TB, U2TB and U0C0, U2C0
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18. Serial Interface
UARTi Transmit/Receive Control Register 1 (i = 0 or 2 (for R8C/2H Group only))
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C1
U2C1
Address
00A5h
0165h
After Reset
00000010b
00000010b
Function
Bit Symbol
Bit Name
RW
RW
Transmit enable bit
0 : Disables transmission
TE
TI
1 : Enables transmission
Transmit buffer empty flag
Receive enable bit
0 : Data in UiTB register
1 : No data in UiTB register
0 : Disables reception
1 : Enables reception
0 : No data in UiRB register
1 : Data in UiRB register
RO
RW
RO
RE
Receive complete flag(1)
RI
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1)
0 : Disables continuous receive mode
1 : Enables continuous receive mode
UiIRS
RW
RW
RW
—
UARTi continuous receive mode
UiRRM
enable bit(2)
—
(b6)
—
(b7)
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UARTi Receive Buffer Register (i = 0 or 2 (for R8C/2H Group only))(1)
(b15)
b7
(b8)
b0
b7
b0
Symbol
U0RB
U2RB
Address
00A7h-00A6h
0167h-0166h
After Reset
Undefined
Undefined
Function
Bit Symbol
—
Bit Name
—
RW
RO
Receive data (D7 to D0)
Receive data (D8)
(b7-b0)
—
(b8)
—
(b11-b9)
—
RO
—
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Overrun error flag(2)
Framing error flag(2)
Parity error flag(2)
Error sum flag(2)
0 : No overrun error
OER
FER
PER
SUM
RO
RO
RO
RO
1 : Overrun error
0 : No framing error
1 : Framing error
0 : No parity error
1 : Parity error
0 : No error
1 : Error
NOTES:
1. Read out the UiRB register in 16-bit units.
2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the REbit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
Figure 18.5
Registers U0C1, U2C1 and U0RB, U2RB
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18. Serial Interface
18.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 18.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 18.2 lists the Registers Used and
(1)
Settings in Clock Synchronous Serial I/O Mode
.
Table 18.1
Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer data format
Transfer clocks
• Transfer data length: 8 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
(1)
Transmit start conditions
Receive start conditions
• Before transmission starts, the following requirements must be met
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
(1)
• Before reception starts, the following requirements must be met
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- The UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- The UiIRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
(2)
Error detection
Select functions
• Overrun error
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the UiRB register.
i = 0 or 2 (for the R8C/2H Group only)
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
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18. Serial Interface
(1)
Table 18.2
Registers Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB
UiRB
Bit Function
0 to 7
0 to 7
OER
Set data transmission
Data reception can be read
Overrun error flag
Set bit rate
UiBRG
UiMR
0 to 7
Set to 001b
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
Select the internal clock or external clock
Select the count source in the UiBRG register
Transmit register empty flag
UiC0
Select TXDi pin output mode
CKPOL
UFORM
TE
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to 1 to enable transmission/reception
Transmit buffer empty flag
UiC1
TI
RE
RI
Set this bit to 1 to enable reception
Reception complete flag
UiIRS
UiRRM
Select the UARTi transmit interrupt source
Set this bit to 1 to use continuous receive mode
i = 0 or 2 (for the R8C/2H Group only)
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 18.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level
between the operating mode selection of UARTi (i = 0 or 2 (for the R8C/2H Group only)) and transfer start. (If the
NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state.)
Table 18.3
Pin Name
TXD0 (P1_4)
RXD0 (P1_5)
I/O Pin Functions in Clock Synchronous Serial I/O Mode
Function
Output serial data
Input serial data
Selection Method
(Outputs dummy data when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6)
Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
(1)
Output serial data
Input serial data
(Outputs dummy data when performing reception only)
TXD2 (P6_3)
RXD2 (P6_4)
(1)
PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
(1)
Output transfer clock CKDIR bit in U2MR register = 0
CLK2 (P6_5)
Input transfer clock
CKDIR bit in U2MR register = 1
PD6_5 bit in PD6 register = 0
NOTE:
1. Applicable to the R8C/2H Group only.
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18. Serial Interface
• Example of transmit timing (when internal clock is selected)
TC
Transfer clock
1
0
TE bit in UiC1
register
Set data in UiTB register
TI bit in UiC1
register
1
0
Transfer from UiTB register to UARTi transmit register
TCLK
Stop pulsing because the TE bit is set to
0
CLKi
TXDi
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPT bit in
UiC0 register
1
0
IR bit in SiTIC
register
1
0
Set to 0 when interrupt request is acknowledged, or set by a program
TC=TCLK=2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
n: Setting value to UiBRG register
The above applies under the following settings:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
• Example of receive timing (when external clock is selected)
RE bit in UiC1
register
1
0
TE bit in UiC1
register
1
0
Write dummy data to UiTB register
TI bit in UiC1
register
1
0
Transfer from UiTB register to UARTi transmit register
1/fEXT
CLKi
RXDi
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Read out from UiRB register
Transfer from UARTi receive register to
UiRB register
RI bit in UiC1
register
1
0
1
0
IR bit in SiRIC
register
Set to 0 when interrupt request is acknowledged, or set by a program
The above applies under the following settings:
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
fEXT: Frequency of external clock
i = 0 or 2 (for the R8C/2H Group only)
Figure 18.6
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
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18. Serial Interface
18.1.1 Polarity Select Function
Figure 18.7 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 2 (for the R8C/2H
Group only)) register to select the transfer clock polarity.
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
CLKi(1)
TXDi
RXDi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
CLKi(2)
TXDi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
RXDi
NOTES:
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
i = 0 or 2 (for the R8C/2H Group only)
Figure 18.7
Transfer Clock Polarity
18.1.2 LSB First/MSB First Select Function
Figure 18.8 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 2 (for the R8C/2H Group
only)) register to select the transfer format.
• When UFORM bit in UiC0 register = 0 (LSB first)(1)
CLKi
TXDi
RXDi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
• When UFORM bit in UiC0 register = 1 (MSB first)(1)
CLKi
TXDi
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
RXDi
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
i = 0 or 2 (for the R8C/2H Group only)
Figure 18.8
Transfer Format
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18. Serial Interface
18.1.3 Continuous Receive Mode
Continuous receive mode is selected by setting the UiRRM (i = 0 or 2 (for the R8C/2H Group only)) bit in the
UiC1 register to 1 (enables continuous receive mode). In this mode, reading the UiRB register sets the TI bit in
the UiC1 register to 0 (data in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to
the UiTB register by a program.
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18. Serial Interface
18.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 18.4 lists the UART Mode Specifications. Table 18.5 lists the Registers Used and Settings for UART Mode.
Table 18.4
UART Mode Specifications
Item
Specification
Transfer data formats
• Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
Transfer clocks
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
Transmit start conditions
Receive start conditions
• Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
• Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
(1)
Error detection
• Overrun error
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
i = 0 or 2 (for the R8C/2H Group only)
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
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18. Serial Interface
Table 18.5
Registers Used and Settings for UART Mode
Bit
Register
UiTB
UiRB
Function
(1)
0 to 8
0 to 8
Set transmit data
Receive data can be read
(1, 2)
OER,FER,PER,SUM Error flag
UiBRG
UiMR
0 to 7
Set a bit rate
SMD2 to SMD0
Set to 100b when transfer data is 7 bits long
Set to 101b when transfer data is 8 bits long
Set to 110b when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
CKDIR
STPS
PRY, PRYE
CLK0, CLK1
TXEPT
NCH
CKPOL
UFORM
Select whether parity is included and whether odd or even
Select the count source for the UiBRG register
Transmit register empty flag
Select TXDi pin output mode
Set to 0
LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
Set to 1 to enable transmit
UiC0
UiC1
TE
TI
RE
Transmit buffer empty flag
Set to 1 to enable receive
RI
UiIRS
UiRRM
Receive complete flag
Select the source of UARTi transmit interrupt
Set to 0
i = 0 or 2 (for the R8C/2H Group only)
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Table 18.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 2 (for the R8C/2H Group only))
operating mode is selected, the TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain
output), this pin is in a high-impedance state) until transfer starts.)
Table 18.6
I/O Pin Functions in UART Mode
Pin name
TXD0 (P1_4)
RXD0 (P1_5)
Function
Output serial data
Input serial data
Selection Method
(Cannot be used as a port when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing transmission only)
CLK0 (P1_6)
Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD2 (P6_3)(1)
RXD2 (P6_4)(1)
Output serial data
Input serial data
(Cannot be used as a port when performing reception only)
PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing transmission only)
CLK2 (P6_5)(1)
Programmable I/O Port CKDIR bit in U2MR register = 0
Input transfer clock
CKDIR bit in U2MR register = 1
PD6_5 bit in PD6 register = 0
NOTE:
1. Applicable to the R8C/2H Group only.
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18. Serial Interface
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1
register
1
0
Write data to UiTB register
TI bit in UiC1
register
1
0
Stop pulsing
because the TE bit is set to 0
Transfer from UiTB register to UARTi transmit register
Start
bit
Stop
bit
Parity
bit
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
SP
1
0
TXEPT bit in
UiC0 register
IR bit SiTIC
register
1
0
Set to 0 when interrupt request is acknowledged, or set by a program
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
n: Setting value to UiBRG register
i = 0 or 2 (for the R8C/2H Group only)
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1
register
1
0
Write data to UiTB register
1
0
TI bit in UiC1
register
Transfer from UiTB register to UARTi transmit register
Stop Stop
bit bit
Start
bit
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
SP SP
TXEPT bit in
UiC0 register
1
0
IR bit in SiTIC
register
1
0
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
• STPS bit in UiMR register = 1 (2 stop bits)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 2 (for the R8C/2H Group only)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
Figure 18.9
Transmit Timing in UART Mode
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18. Serial Interface
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
1
0
UiC1 register
RE bit
Stop bit
Start bit
RXDi
D0
D1
D7
Determined to be “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock
is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
UiC1 register
RI bit
1
0
SiRIC register
IR bit
1
0
Set to 0 when interrupt request is accepted, or set by a program
The above timing diagram applies when the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
i = 0 or 2 (for the R8C/2H Group only)
Figure 18.10 Receive Timing Example in UART Mode
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18. Serial Interface
18.2.1 Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 2 (for the R8C/2H Group only))
register.
UART mode
• Internal clock selected
fj
UiBRG register setting value =
- 1
Bit Rate × 16
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
• External clock selected
UiBRG register setting value =
fEXT
- 1
Bit Rate × 16
fEXT: Count source frequency of the UiBRG register (external clock)
i = 0 or 2 (for the R8C/2H Group only)
Figure 18.11 Calculation Formula of UiBRG (i = 0 or 2 (for R8C/2H Group only)) Register Setting
Value
Table 18.7
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
System Clock = 8 MHz
Bit Rate (bps)
BRG Count Source
UiBRG Setting Value
51 (33h)
Actual Time (bps)
1201.92
Error (%)
1200
2400
4800
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
0.16
0.16
0.16
0.16
-0.79
0.16
2.12
0.00
0.16
-2.34
25 (19h)
12 (0Ch)
51 (33h)
34 (22h)
25 (19h)
16 (10h)
15 (0Fh)
12 (0Ch)
9 (09h)
2403.85
4807.69
9615.38
9600
14400
19200
28800
31250
38400
51200
14285.71
19230.77
29411.76
31250.00
38461.54
50000.00
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18. Serial Interface
18.3 Notes on Serial Interface
•
When reading data from the UiRB (i = 0 or 2 (for the R8C/2H Group only)) register either in the clock
synchronous serial I/O mode or in the clock asynchronous serial I/O mode. Ensure the data is read in 16-bit
units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI
bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
#XXH,00A2H ; Write the low-order byte of U0TB register
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19. Hardware LIN
19. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
19.1 Features
The hardware LIN has the features listed below.
Figure 19.1 shows a Block Diagram of Hardware LIN.
Master mode
• Generates Synch Break
• Detects bus collision
Slave mode
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision
NOTE:
1. The WakeUp function is detected by INT1.
Hardware LIN
Synch Field
RXD0 pin
control
circuit
Timer RA
TIOSEL = 0
TIOSEL = 1
RXD data
Timer RA
RXD0 input
control
LSTART bit
SBE bit
underflow signal
Timer RA
interrupt
circuit
LINE bit
Interrupt
control
circuit
Bus collision
detection
circuit
UART0
BCIE, SBIE,
and SFIE bits
UART0 transfer clock
UART0 TE bit
Timer RA output pulse
MST bit
UART0 TXD data
TXD0 pin
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
Figure 19.1
Block Diagram of Hardware LIN
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19. Hardware LIN
19.2 Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 19.1.
Table 19.1
Pin Configuration
Abbreviation Input/Output
Name
Function
Receive data input
RXD0
TXD0
Input
Receive data input pin of the hardware LIN
Transmit data output pin of the hardware LIN
Transmit data output
Output
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19. Hardware LIN
19.3 Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 19.2 and 19.3.
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
LIN Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINCR
Address
0106h
Bit Name
After Reset
00h
Function
Bit Symbol
RW
RW
Synch Field measurement-
completed interrupt enable bit
0 : Disables Synch Field measurement-
completed interrupt
SFIE
1 : Enables Synch Field measurement-
completed interrupt
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt
enable bit 1 : Enables Synch Break detection interrupt
SBIE
BCIE
RW
RW
RO
Bus collision detection interrupt 0 : Disables bus collision detection interrupt
enable bit
1 : Enables bus collision detection interrupt
RXD0 input status flag
0 : RXD0 input enabled
1 : RXD0 input disabled
RXDSF
Synch Break detection start bit(1) When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
LSTART
SBE
RW
RW
When read, the content is 0.
RXD0 input unmasking timing
select bit (effective only in slave 1 : Unmasked after Synch Field measurement
mode) is completed
0 : Unmasked after Synch Break is detected
LIN operation mode setting bit(2) 0 : Slave mode
(Synch Break detection circuit actuated)
MST
LINE
RW
RW
1 : Master mode
(timer RA output OR’ed w ith TXD0)
LIN operation start bit
0 : Causes LIN to stop
1 : Causes LIN to start operating(3)
NOTES:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before changing LIN operation modes, temporarily stop the LIN operation (LINEbit = 0).
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to
Figure 19.5 Example of
and
Header Field Transmission Flowchart (1)
.)
Figure 19.9 Example of Header Field Reception Flowchart
(2)
Figure 19.2
LINCR Register
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19. Hardware LIN
LIN Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINST
Bit Symbol
Address
0107h
Bit Name
Synch Field measurement-
completed flag
Synch Break detection flag 1 show s Synch Break detected or Synch Break
generation completed.
Bus collision detection flag
After Reset
00h
Function
RW
1 show s Synch Field measurement completed.
SFDCT
SBDCT
BCDCT
B0CLR
B1CLR
B2CLR
RO
RO
RO
RW
RW
RW
—
1 show s Bus collision detected.
SFDCT bit clear bit
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
SBDCT bit clear bit
BCDCT bit clear bit
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 19.3
LINST Register
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19. Hardware LIN
19.4 Functional Description
19.4.1 Master Mode
Figure 19.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 19.5 and 19.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Synch Break
Synch Field
IDENTIFIER
1
0
TXD0 pin
Set by writing 1 to the
B1CLR bit in the LINST
register
SBDCT flag in the
LINST register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
IR bit in the TRAIC
register
1
0
(1)
(2) (3)
(4)
(5)
Shown above is the case where
LINE = 1, MST = 1, SBIE = 1
Figure 19.4
Typical Operation when Sending a Header Field
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Timer RA Set to timer mode
19. Hardware LIN
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
For the hardware LIN
Timer RA Set the INT1/TRAIO pin to P1_5
function, set the TIOSEL bit
in the TRAIOC register to 1.
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
Timer RA Set the Synch Break width
TRAPRE register
TRA register
UART0 Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)
Bits CLK0 to CLK2 in U0C0 register
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
UART0 Set the bit rate
U0BRG register
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
Figure 19.5
Example of Header Field Transmission Flowchart (1)
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19. Hardware LIN
A
Timer RA generates Synch Break.
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
Timer RA Read the count status flag
TCSTF flag in TRACR register
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
NO
TCSTF = 1 ?
YES
The timer RA interrupt may be used
to terminate generation of Synch
Break.
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
One to two cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
NO
SBDCT = 1 ?
YES
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Timer RA Read the count status flag
TCSTF flag in TRACR register
NO
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
TCSTF = 0 ?
YES
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
Transmit the Synch Field.
UART0 Communication via UART0
Transmit the ID field.
U0TB register ← ID field
Figure 19.6
Example of Header Field Transmission Flowchart (2)
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19. Hardware LIN
19.4.2 Slave Mode
Figure 19.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
19.8 through Figure 19.10 show an Example of Header Field Reception Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via
UART0.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Synch Break
Synch Field
IDENTIFIER
1
0
RXD0 pin
RXD0 input for
UART0
1
0
Set by writing 1 to
the LSTART bit in
the LINCR register
Cleared to 0 when Synch
Field measurement
finishes
RXDSF flag in the
LINCR register
1
0
Set by writing 1 to
the B1CLR bit in
the LINST register
SBDCT flag in the
LINST register
1
0
Set by writing 1 to the
B0CLR bit in the LINST
register
Measure this period
SFDCT flag in the
LINST register
1
0
Cleared to 0 upon
acceptance of
interrupt request or
by a program
IR bit in the TRAIC
register
1
0
(1)
(2) (3)
(4)
(5)
(6)
Shown above is the case where
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 19.7
Typical Operation when Receiving a Header Field
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19. Hardware LIN
Timer RA Set to pulse width measurement mode
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
For the hardware LIN
Timer RA Set the INT1/TRAIO pin to P1_5
function, set the TIOSEL bit
in the TRAIOC register to 1.
TIOSEL bit in the TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
A
Figure 19.8
Example of Header Field Reception Flowchart (1)
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19. Hardware LIN
A
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Timer RA waits until the timer starts
Timer RA Set to start a pulse width measurement
counting.
TSTART bit in the TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in the TRACR register
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set to
1.
NO
TCSTF = 1 ?
YES
Hardware LIN waits until the RXD0
input for UART0 is masked.
Hardware LIN Set to start Synch Break detection
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
One to two cycles of the CPU clock and
zero to one cycle of the timer RA count
source are required after the LSTART
bit is set to 1 before the RXDSF flag is
set to 1. After this, input to timer RA and
UART0 is enabled.
NO
RXDSF = 1 ?
YES
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
When Synch Break is detected, timer
RA is reloaded with the initially set count
value.
NO
SBDCT = 1 ?
Even if the duration of the input “L” level
is shorter than the set period, timer RA
is reloaded with the initially set count
value and waits until the next “L” level is
input.
YES
B
One to two cycles of the CPU clock are
required after Synch Break detection
before the SBDCT flag is set to 1.
When the SBE bit in the LINCR register
is set to 0 (unmasked after Synch Break
is detected), timer RA can be used in
timer mode after the SBDCT flag in the
LINST register is set to 1 and the
RXDSF flag is set to 0.
Figure 19.9
Example of Header Field Reception Flowchart (2)
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19. Hardware LIN
Hardware LIN measures the Synch
B
Field.
YES
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit
in the LINST register is set to 1.
Hardware LIN Read the Synch Field measurement-
completed flag
SFDCT flag in the LINST register
NO
SFDCT = 1 ?
YES
UART0 Set the UART0 communication rate
U0BRG register
Set a communication rate based on
the Synch Field measurement
result.
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
Communication via UART0
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
Figure 19.10 Example of Header Field Reception Flowchart (3)
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19. Hardware LIN
19.4.3 Bus Collision Detection Function
The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1
register = 1).
Figure 19.11 shows the Typical Operation when a Bus Collision is Detected.
1
TXD0 pin
0
1
RXD0 pin
0
1
Transfer clock
0
Set to 1 by a program
LINE bit in the
LINCR register
1
0
Set to 1 by a program
TE bit in the U0C1
register
1
0
Set by writing 1 to
the B2CLR bit in the
LINST register
BCDCT flag in the
LINST register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
IR bit in the TRAIC
register
1
0
Figure 19.11 Typical Operation when a Bus Collision is Detected
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19. Hardware LIN
19.4.4 Hardware LIN End Processing
Figure 19.12 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
• If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Set the timer to stop counting.
Timer RA Read the count status flag
TCSTF flag in TRACR register
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
NO
TCSTF = 0 ?
YES
When the bus collision detection
function is not used, end
UART0 Complete transmission via UART0
processing for the UART0
transmission is not required.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field measurement)
After clearing hardware LIN
s t at u s f l a g, s t o p t h e
hardware LIN operation.
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Figure 19.12 Example of Hardware LIN Communication Completion Flowchart
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19. Hardware LIN
19.5 Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 19.2 lists the Interrupt Requests of Hardware LIN.
Table 19.2
Interrupt Requests of Hardware LIN
Interrupt Request
Status Flag
SBDCT
Cause of Interrupt
Synch Break detection
Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Synch Break generation
completed
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field
SFDCT
BCDCT
Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
measurement completed
Bus collision detection
Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
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19. Hardware LIN
19.6 Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
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20. Flash Memory
20. Flash Memory
20.1 Overview
Rewrite operations to the flash memory can be performed in three modes: CPU rewrite, standard serial I/O, and
parallel I/O.
Table 20.1 lists the Flash Memory Performance (refer to Table 1.1 Specifications for R8C/2H Group and Table
1.2 Specifications for R8C/2J Group for items not listed in Table 20.1). Table 20.2 lists the Flash Memory
Rewrite Modes.
Table 20.1
Flash Memory Performance
Item
Specification
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Refer to Figure 20.1
Flash memory operating mode
Division of erase block
Programming method
Byte unit
Erase method
Programming and erasure control method
Protection method
Block erase
Program and erase control by software command
Program ROM protection by FMR0 register
5 commands
Number of commands
Programming and
Block 0 (program ROM) 100 times
erasure endurance(1)
Programming and erasure voltage
ID code check function
ROM code protect
VCC = 2.7 to 5.5 V
Standard serial I/O mode supported
Parallel I/O mode supported
NOTE:
1. Definition of programming and erasure endurance.
The programming and erasure endurance is defined on a per-block basis.
Table 20.2
Flash Memory Rewrite Modes
Flash Memory
Rewrite Mode
Function
CPU Rewrite Mode
Standard Serial I/O Mode
Parallel I/O Mode
User ROM area is rewritten User ROM area is rewritten User ROM area is rewritten
by executing software
commands from the CPU. programmer.
by a dedicated serial
by a dedicated parallel
programmer.
Areas which can User ROM area
be rewritten
Rewrite Program User program
User ROM area
User ROM area
Standard boot program
–
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20. Flash Memory
20.2 Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area).
Figure 20.1 shows the Flash Memory Block Diagram.
The user ROM area contains program ROM.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
The rewrite control program (standard boot program) for standard serial I/O mode is stored in the boot ROM area
before shipment. The boot ROM area and the user ROM area share the same address, but have separate memory
areas.
2 Kbytes ROM product(3)
0F800h
Block 0: 2 Kbytes
User ROM area
Program ROM
0FFFFh
8 Kbytes ROM product(2)
0E000h
0FFFFh
0E000h
0FFFFh
4 Kbytes ROM product
Block 0: 4 Kbytes
User ROM area
Block 0: 8 Kbytes
User ROM area
Program ROM
8 Kbytes
0F000h
0FFFFh
Boot ROM area
(reserved area)(1)
NOTES:
1. This area is for storing the standard boot program provided by Renesas Technology.
2. Applicable to the R8C/2H Group only.
3. Applicable to the R8C/2J Group only.
Figure 20.1
Flash Memory Block Diagram
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20. Flash Memory
20.3 Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten or erasure easily.
20.3.1 ID Code Check Function
The ID code check function is used in standard serial I/O mode. Unless 3 bytes (addresses from 0FFFCh to
0FFFEh) of the reset vector are set to FFFFFFh, the ID codes sent from the serial programmer or the on-chip
debugging emulator and the 7-byte ID codes written in the flash memory are checked to see if they match. If the
ID codes do not match, the commands sent from the serial programmer or the on-chip debugging emulator are
not acknowledged. For details of the ID code check function, refer to 14. ID Code Areas.
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20. Flash Memory
20.3.2 ROM Code Protect Function
The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased by
means of the OFS register when parallel I/O mode is used.
Figure 20.2 shows the OFS Register. Refer to 15. Option Function Select Area for details of the OFS register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
Address
0FFFFh
Bit Name
When Shipping
FFh(3)
Function
RW
RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
WDTON
—
Reserved bit
Set to 1.
RW
RW
RW
RW
(b1)
ROM code protect
disabled bit
ROM code protect bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
ROMCR
ROMCP1
—
(b4)
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
LVD0ON
RW
1 : Voltage monitor 0 reset disabled after hardw are
reset
—
Reserved bit
Set to 1.
RW
RW
(b6)
Count source protect
mode after reset select 1 : Count source protect mode disabled after reset
bit
0 : Count source protect mode enabled after reset
CSPROINI
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 20.2
OFS Register
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20. Flash Memory
20.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
Table 20.3 lists the EW0 Mode.
Table 20.3
EW0 Mode
Item
EW0 Mode
Operating mode
Single-chip mode
Areas in which a rewrite control program can RAM (Rewrite control program is executed after
be executed
being transferred)
User ROM
None
Read status register mode
Read status register mode
Areas which can be rewritten
Software command restrictions
Modes after program or erase
Modes after read status register
CPU status during auto- write and auto-erase Operating
Flash memory status detection
• Read bits FMR00, FMR06, and FMR07 in the
FMR0 register by a program
• Execute the read status register command and
read bits SR7, SR5, and SR4 in the status register.
CPU clock
5 MHz or below
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20. Flash Memory
20.4.1 Register Description
The registers used in CPU rewrite mode are described.
20.4.1.1 FMR0 Register (FMR0)
Figure 20.3 shows the FMR0 Register.
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
FMR0
Address
01B7h
After Reset
00000001b
Bit Symbol
Bit Name
RY/BY status flag
Function
RW
___
0 : Busy (w riting or erasing in progress)
FMR00
FMR01
FMR02
RO
RW
RW
1 : Ready
CPU rew rite mode select bit(1)
Block 0 rew rite enable bit(2, 6)
Flash memory stop bit(3, 5)
0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
0 : Disables rew rite
1 : Enables rew rite
0 : Enables flash memory operation
1 : Stops flash memory
FMSTP
RW
(enters low -pow er consumption state
and flash memory is reset)
—
Reserved bits
Set to 0.
RW
RO
RO
(b5-b4)
Program status flag(4)
Erase status flag(4)
0 : Completed successfully
1 : Terminated by error
0 : Completed successfully
1 : Terminated by error
FMR06
FMR07
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
3. Set this bit by a program located in a space other than the flash memory.
4. This bit is set to 0 by executing the clear status command.
5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode). When the FMR01 bit is set to 0, w riting 1 to the
FMSTPbit causes the FMSTPbit to be set to 1. The flash memory does not enter low -pow er consumption state nor is
it reset.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
Figure 20.3
FMR0 Register
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20. Flash Memory
• FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during programming,
erasure, or erase-suspend mode; otherwise, it is 1.
• FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
• FMR02 Bit
Rewriting of block 0 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of block 0 is controlled by FMR15 bit if the FMR02 bit is set to 1 (rewrite enabled).
• FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
- When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
- To provide lower consumption in low-speed on-chip oscillator mode and low-speed clock mode.
Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register
does not need to be set because the power for the flash memory is automatically turned off and is turned
back on again after returning from stop or wait mode.
• FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a
program error occurs; otherwise, it is set to 0. For details, refer to the description in Table 20.4 Errors and
FMR0 Register Status.
• FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase
error occurs; otherwise, it is set to 0. Refer to Table 20.4 Errors and FMR0 Register Status for details.
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20. Flash Memory
Table 20.4
Errors and FMR0 Register Status
FMR0 Register (Status
Register) Status
Error
Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1
1
Command sequence
error
• When a command is not written correctly.
• When D0h or FFh is not written in the 2nd byte
(1)
of the block erase command.
• When the program command or block erase
command is executed while rewriting is
disabled by the FMR02 bit in the FMR0 register,
or the FMR15 bit in the FMR1 register.
• When an address not allocated in flash memory
is input during erase command input
• When attempting to erase the block for which
rewriting is disabled during erase command
input.
• When an address not allocated in flash memory
is input during write command input.
• When attempting to write to a block for which
rewriting is disabled during write command
input.
1
0
0
1
0
Erase error
• When the block erase command is executed
but auto-erasure does not complete correctly
Program error
• When the program command is executed but
not auto-programming does not complete.
Completed successfully –
0
NOTE:
1. When FFh is written in the 2nd byte of the block erase command, the MCU enters read array mode,
and the command code written in the 1st byte is disabled.
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20. Flash Memory
20.4.1.2 FMR1 Register (FMR1)
Figure 20.4 shows the FMR1 Register.
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1 0
0 0 0 0
Symbol
FMR1
Bit Symbol
Address
01B5h
Bit Name
After Reset
1000000Xb
Function
RW
—
Reserved bit
Reserved bits
When read, the content is undefined.
RO
RW
RW
RW
RW
(b0)
—
(b4-b1)
Set to 0.
Block 0 rew rite disable bit(1,2)
Reserved bit
0 : Enables rew rite
1 : Disables rew rite
Set to 0.
FMR15
—
(b6)
—
(b7)
Reserved bit
Set to 1.
NOTES:
1. This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled).
2. While the FMR01 bit is set to 1 (CPU rew rite mode enabled), FMR15 bit can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
Figure 20.4
FMR1 Register
• FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
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20. Flash Memory
20.4.1.3 FMR4 Register (FMR4)
Figure 20.5 shows the FMR4 Register.
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
FMR4
Bit Symbol
Address
01B3h
Bit Name
After Reset
01000000b
Function
RW
RW
—
(b2-b0)
Reserved bits
Set to 0.
Erase command flag
0 : Erase not executed
FMR43
RO
RO
—
1 : Erase execution in progress
Program command flag
0 : Program not executed
1 : Program execution in progress
FMR44
—
(b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Read status flag
0 : Disables reading
FMR46
FMR47
RO
RW
1 : Enables reading
Low -current-consumption
read mode enable bit (1, 2, 3)
0 : Disable
1 : Enable
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
2. In high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
3. Set the FMR01 bit to 0 (CPU rew rite mode disabled) in low -current-consumption read mode.
Figure 20.5
FMR4 Register
• FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress).
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
• FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress).
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
• FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution. Do not access
the flash memory while this bit is set to 0.
• FMR47 Bit
Current consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1
(enabled) in low-speed clock mode and low-speed on-chip oscillator mode.
Refer to 21.2.10 Low-Current-Consumption Read Mode for details of the handling procedure.
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20. Flash Memory
20.4.2 Status Check Procedure
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Figure 20.6 shows the Full Status Check and Handling Procedure for Individual Errors.
Command sequence error
Full status check
Execute the clear status register command
(set these status flags to 0)
FMR06 = 1
and
Yes
Command sequence error
FMR07 = 1?
Check if command is properly input
Re-execute the command
No
Yes
Erase error
FMR07 = 1?
No
Erase error
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
No
Block targeting for erasure
cannot be used
Yes
Yes
FMR06 = 1?
No
Program error
Re-execute block erase command
Program error
Execute the clear status register
command
(set these status flags to 0)
Full status check completed
Specify the other address besides the
write address where the error occurs for
the program address(1)
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Re-execute program command
Figure 20.6
Full Status Check and Handling Procedure for Individual Errors
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20. Flash Memory
20.4.3 EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
Figure 20.7 shows How to Set and Exit EW0 Mode.
EW0 Mode Operating Procedure
Rewrite control program
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Set registers(1) CM0 and CM1
Execute software commands
Transfer a rewrite control program which uses CPU
Execute the read array command(3)
rewrite mode to the RAM.
Jump to the rewrite control program which has been
transferred to the RAM.
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
(The subsequent process is executed by the rewrite
control program in the RAM.)
Jump to a specified address in the flash memory
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
Figure 20.7
How to Set and Exit EW0 Mode
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20. Flash Memory
20.4.3.1 Software Commands
There are five types of software commands:
• Read array
• Read status register
• Clear status register
• Program
• Block erase
Figure 20.8 shows Software Command Status Transition Diagram in EW0 Mode.
Read array mode
(FMR46 = 1 Reading enabled)
No command required
Reading only available
CPU rewrite disabled
Reset
Write 1 to the FMR01 bit immediately after writing 0.
FMR01 = 0
CPU rewrite mode (EW0 mode)
Read array mode
(FMR46 = 1 Reading enabled)
70h
40h
(Bcolom2ckm0eharnads)e
(Cle5ar0shtatus
(Read status
register
(Program command)
register command)
command)
(cRoemFamdFaahnrrda)y
(cRoemFamdFaahnrrda)y
Clear ends
Program
Read status
register mode
Clear status
register
Block erase
Non-D0h
and
(ProWgrarmitemidngatsatarts)
(Block eDras0uhre starts)
non-FFh
Auto-erase
Auto-program
(FMR46 = 0 Reading disabled)
(FMR46 = 0 Reading disabled)
Auto-programming completed
Auto-erasure completed
Figure 20.8
Software Command Status Transition Diagram in EW0 Mode
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20. Flash Memory
• Read Array Command
The read array command reads the flash memory.
When FFh is written to an address in the user ROM area, the MCU enters read array mode. In this mode,
the contents of the specified address can be read.
Read array mode continues until other commands are written. The MCU enters this mode after a reset is
deasserted.
• Read Status Register Command
The read status register command is used to read the status register. Figure 20.9 shows Status Register.
The status register indicates the operating status of the flash memory and whether an erase or program
operation has completed normally or in error (refer to Table 20.4 Errors and FMR0 Register Status).
When 70h is written to an address in the user ROM area, the MCU enters read status register mode. When
the address in the user ROM area is read subsequently, the status register can be read.
The MCU remains in read status register mode until the next read array command is written.
The status of the status register can be determined by reading bits FMR00, FMR06, and FMR07 in the
FMR0 register.
D7
D6
D5
D4
D3
D2
D1
D0
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Status register
FMR0 register
FMR06 bit
FMR07 bit
FMR00 bit
D0 to D7: These indicate the read data buses when the read status command is executed.
Figure 20.9
Status Register
• Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written to an address in the user ROM area, bits FMR07 and FMR06 in the FMR0 register and
bits SR5 and SR4 in the status register are set to 00b.
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20. Flash Memory
• Program Command
The program command writes data to the flash memory in 1-byte units.
When 40h is written and then data is written to the write address, an auto-program operation (data program
and verify) starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed.
The FMR00 bit is set to 0 during auto-programming and set to 1 when auto-programming completes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has
been finished (refer to 20.4.2 Status Check Procedure).
Do not write additions to the already programmed addresses.
Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), program
commands targeting block 0 are not acknowledged.
Figure 20.10 shows the Program Command in EW0 Mode.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. In this case, the MCU remains in read status register mode until the next read
array command is written.
Start
Write the command code 40h to
the write address
Write data to the write address
No
FMR00 = 1?
Yes
Full status check
Program completed
Figure 20.10 Program Command in EW0 Mode
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20. Flash Memory
• Block Erase
When 20h is first written and then D0h is written to a given block address, an auto-erase operation (erase
and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure
has completed (refer to 20.4.2 Status Check Procedure).
Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1
(rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), block erase
commands targeting block 0 are not acknowledged.
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. In this case, the MCU remains in read status register mode until the next read array
command is written.
Figure 20.11 shows the Block Erase Command in EW0 Mode.
If the programming and erasure endurance is n (n = 100, 1000, or 10,000), each block can be erased n
times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is
erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be
reduced by executing programming operations in such a way that all blank areas are used before
performing an erase operation. Avoid rewriting only particular blocks and try to average out the
programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of
each block and limit the number of erase operations to a certain number.
Start
Write the command code 20h
Write D0h to any block
address
No
FMR00 = 1?
Yes
Full status check
Block erase completed
Figure 20.11 Block Erase Command in EW0 Mode
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20. Flash Memory
20.4.3.2 EW0 Mode Interrupts
In EW0 mode, maskable interrupts can be used by allocating a vector in RAM. Table 20.5 lists the EW0 Mode
Interrupts. Refer to 20.7.1.3 Non-Maskable Interrupts for details of the non-maskable interrupt.
Table 20.5
EW0 Mode Interrupts
Status
When Maskable Interrupt Request is Acknowledged
Interrupt handling is executed.
During auto-erasure
Auto-programming
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20. Flash Memory
20.5 Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of standard serial I/O modes:
• Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 3.
Refer to Appendix 2. Connection Examples with On-Chip Debugging Emulator. Contact the manufacturer of
your serial programmer for details. Refer to the user’s manual of your serial programmer for instructions on how to
use it.
Table 20.6 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3), and Figure 20.12 shows an
Example of Pin Processing in Standard Serial I/O Mode 3.
After processing the pins shown in Table 20.6 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
20.5.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match.
Refer to 14. ID Code Areas for details of the ID code check.
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20. Flash Memory
Table 20.6
Pin
VCC,VSS
Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Name I/O Description
Power input
Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
Reset input pin.
Reset input
I
RESET
P4_3/XCIN
(1)
P4_3 input/clock input
I
Connect crystal oscillator between pins XCIN and
XCOUT when connecting external oscillator.
To use P4_3 as an input port, input a “H” or “L” level
signal or leave the pin open.
(1)
P4_4 output/clock output O
P4_4/XCOUT
To use P4_4 as an output port, leave the pin open.
Input a “H” or “L” level signal or leave the pin open.
P1_0 to P1_7
P3_3, P3_7
P4_5
P6_3 to P6_5
MODE
Input port P1
Input port P3
Input port P4
Input port P6
MODE
I
I
I
I
(1)
I/O Serial data I/O pin. Connect to the flash programmer.
NOTE:
1. Ports P4_3, P4_4, P6_3, and P6_4 are not available in the R8C/2J Group.
MCU
MODE
MODE I/O
Reset input
VCC
RESET
User reset signal
VSS
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
Figure 20.12 Example of Pin Processing in Standard Serial I/O Mode 3
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20. Flash Memory
20.6 Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figure 20.1 can be rewritten in parallel I/O mode.
20.6.1 ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 20.3.2 ROM
Code Protect Function.)
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20. Flash Memory
20.7 Notes on Flash Memory
20.7.1 CPU Rewrite Mode
20.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register.
20.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
20.7.1.3 Non-Maskable Interrupts
• EW0 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not stop during command operation, so that interrupt requests may be generated.
Initialize the watchdog timer regularly.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
20.7.1.4 How to Access
Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1
register to 1. Do not generate an interrupt between writing 0 and 1.
20.7.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
20.7.1.6 Program
Do not write additions to the already programmed address.
20.7.1.7 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
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21. Reducing Power Consumption
21. Reducing Power Consumption
21.1 Overview
This chapter describes key points and processing methods for reducing power consumption.
21.2 Key Points and Processing Methods for Reducing Power Consumption
Key points for reducing power consumption are shown below. They should be referred to when designing a system
or creating a program.
21.2.1 Voltage Detection Circuit
When voltage monitor 1 and comparator 1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage
detection 1 circuit disabled). When voltage monitor 2 and comparator 2 are not used, set the VCA27 bit in the
VCA2 register to 0 (voltage detection 2 circuit disabled).
If the power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0
(voltage detection 0 circuit disabled).
21.2.2 Ports
Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into
the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance
state. Unnecessary ports should be set to input and fixed to a stable electric potential before the MCU enters
wait mode or stop mode.
21.2.3 Clocks
Power consumption generally depends on the number of the operating clocks and their frequencies. The fewer
the number of operating clocks or the lower their frequencies, the more power consumption decreases.
Unnecessary clocks should be stopped accordingly.
Stopping low-speed on-chip oscillator oscillation: CM14 bit in CM1 register (for R8C/2H Group only)
Stopping high-speed on-chip oscillator oscillation: HRA00 bit in HRA0 register
21.2.4 Selecting Oscillation Drive Capacity (for R8C/2H Group only)
Set the drive capacity of the XCIN clock oscillation circuit to “LOW”. Confirm that the circuit oscillates stably
while it is in the “LOW” state.
Selecting XCIN-XCOUT drive capacity: CM03 bit in CM0 register
21.2.5 Wait Mode, Stop Mode
Power consumption can be reduced in wait mode and stop mode. Refer to 11.4 Power Control for details.
21.2.6 Stopping Peripheral Function Clocks
If the peripheral function f1, f2, f4, f8, and f32 clocks are not necessary in wait mode, set the CM02 bit in the
CM0 register to 1 (peripheral function clock stops in wait mode). This will stop the f1, f2, f4, f8, and f32 clocks
in wait mode.
21.2.7 Timers
If timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff).
If timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff).
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21. Reducing Power Consumption
21.2.8 Reducing Internal Power Consumption
When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal
power consumption can be reduced by using the VCA20 bit in the VCA2 register. Figure 21.1 shows the
Handling Procedure of Internal Power Low Consumption Using VCA20 Bit. To enable internal power low
consumption by the VCA20 bit, follow Figure 21.1 Handling Procedure of Internal Power Low Consumption
Using VCA20 Bit.
Exit wait mode by interrupt
(Note 1)
Handling procedure of internal power
In interrupt routine
low consumption enabled by VCA20 bit
Enter low-speed clock mode(4) or low-speed
on-chip oscillator mode
VCA20 ← 0 (internal power low consumption
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
disabled)(2)
If it is necessary to start
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (8) in the interrupt
routine.
Stop high-speed on-chip oscillator clock
Start high-speed on-chip oscillator clock
VCA20 ← 1 (internal power low consumption
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
enabled)(2)
Enter wait mode(3)
Enter high-speed on-chip oscillator mode
Interrupt handling
VCA20 ← 0 (internal power low consumption
Step (5)
Step (6)
Step (7)
Step (8)
disabled)(2)
Enter low-speed clock mode(4) or
low-speed on-chip oscillator mode
Step (1)
Step (2)
Step (3)
Start high-speed on-chip oscillator clock
If high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
Stop high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter high-speed on-chip oscillator mode
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When entering wait mode, follow 11.5.2 Wait Mode.
4. Applicable to the R8C/2H Group only.
VCA20: Bit in VCA2 register
Figure 21.1
Handling Procedure of Internal Power Low Consumption Using VCA20 Bit
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21. Reducing Power Consumption
21.2.9 Stopping Flash Memory
In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by
stopping the flash memory using the FMSTP bit in the FMR0 register.
Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memory stops). The FMSTP bit
must be written to by a program transferred to RAM.
When the MUC enters stop mode or wait mode while CPU rewrite mode is disabled, the power for the flash
memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This
eliminates the need to set the FMR0 register.
Figure 21.2 shows the Handling Procedure Example of Low Power Consumption Using FMSTP Bit.
FMSTP bit setting program
After writing 0 to FMR01 bit, write 1 (CPU
rewrite mode enabled)
Transfer FMSTP bit setting program to RAM
Write 1 to FMSTP bit (flash memory stops, low
power consumption state)(1)
Jump to FMSTP bit setting program
(The subsequent processing is executed by
the program in the RAM)
Enter low-speed clock mode or low-speed on-
chip oscillator mode
Stop high-speed on-chip oscillator
Process in low-speed clock mode, low-
speed on-chip oscillator mode
Switch clock source for CPU clock(2)
Write 0 to FMSTP bit (flash memory operates)
Write 0 to FMR01 bit (CPU rewrite mode
disabled)
Wait until flash memory circuit stabilizes
(30 µs)(3)
NOTES:
1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled),
set the FMSTP bit to 1 (flash memory stops).
2. Before switching the CPU clock source, make sure the designated
clock is stable.
Jump to specified address in flash memory
3. Insert a 30 µs wait time by a program.
Do not access to the flash memory during this wait time.
FMR01, FMSTP: Bits in FMR0 register
Figure 21.2
Handling Procedure Example of Low Power Consumption Using FMSTP Bit
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21. Reducing Power Consumption
21.2.10 Low-Current-Consumption Read Mode
In low-speed clock mode (for the R8C/2H Group only) and low-speed on-chip oscillator mode, the current
consumption when reading the flash memory can be reduced by setting the FMR47 bit in the FMR4 register to 1
(enabled).
Figure 21.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode.
Handling procedure of
low-current-consumption read mode
enabled by FMR47 bit
Enter low-speed clock mode(3) or
Step (1)
low-speed on-chip oscillator mode
Step (2)
Step (3)
Step (4)
Stop high-speed on-chip oscillator clock
FMR47 ← 1 (low-current-consumption read
mode enabled)(1)
Enter low-current-consumption read mode(2)
FMR47 ← 0 (low-current-consumption read
Step (5)
Step (6)
Step (7)
Step (8)
mode disabled)
Start high-speed on-chip oscillator clock
(Wait until high-speed on-chip oscillator clock
oscillation stabilizes)
Enter high-speed on-chip oscillator mode
NOTES:
1. To set the FMR47 bit to 1, first write 0 and then write 1 immediately.
After writing 0, do not generate an interrupt before writing 1.
2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled).
3. Applicable to the R8C/2H Group only.
FMR47: Bit in FMR4 register
Figure 21.3
Handling Procedure Example of Low-Current-Consumption Read Mode
Rev.1.00 Mar 28, 2008 Page 281 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
22. Electrical Characteristics
22.1 R8C/2H Group
Table 22.1
Absolute Maximum Ratings
Symbol
VCC
VI
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Condition
Rated Value
Unit
V
V
V
mW
°C
−0.3 to 6.5
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
500
−20 to 85 (N version) /
−40 to 85 (D version)
VO
Pd
Topr = 25°C
Topr
Operating ambient temperature
Tstg
Storage temperature
−65 to 150
°C
Table 22.2
Recommended Operating Conditions
Standard
Typ.
−
Symbol
Parameter
Conditions
Unit
Min.
Max.
5.5
VCC
VSS
VIH
VIL
Supply voltage
2.2
V
V
V
V
Supply voltage
Input “H” voltage
Input “L” voltage
Peak sum output “H”
current
−
0
−
−
0.8 VCC
VCC
0.2 VCC
−160
0
−
−
IOH(sum)
Sum of all pins IOH(peak)
Sum of all pins IOH(avg)
−
mA
IOH(sum)
Average sum output “H”
−
−
−80
mA
current
IOH(peak)
IOH(avg)
Peak output “H” current
Average output “H”
current
All pins
All pins
−
−
−
−
−10
−5
mA
mA
IOL(sum)
IOL(sum)
Peak sum output “L”
Sum of all pins IOL(peak)
Sum of all pins IOL(avg)
All pins
−
−
−
−
160
80
mA
mA
currents
Average sum output “L”
currents
IOL(peak)
IOL(avg)
f(XCIN)
−
Peak output “L” currents
−
−
0
0
−
−
−
−
10
5
70
70
mA
mA
kHz
kHz
Average output “L” current All pins
XCIN clock input oscillation frequency
2.2 V ≤ VCC ≤ 5.5 V
2.2 V ≤ VCC ≤ 5.5 V
System clock
OCD2 = 0
XClN clock selected
OCD2 = 1
HRA01 = 0
−
125
−
kHz
Low-speed on-chip
On-chip oscillator clock
selected
oscillator selected
HRA01 = 1
−
−
8
MHz
High-speed on-chip
oscillator selected
2.7 V ≤ VCC ≤ 5.5 V
HRA01 = 1
−
−
4
MHz
High-speed on-chip
oscillator selected
2.2 V ≤ VCC ≤ 5.5 V
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
P1
P3
P4
30pF
P6
Figure 22.1
Ports P1, P3, P4, and P6 Timing Measurement Circuit
Rev.1.00 Mar 28, 2008 Page 282 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.3
Flash Memory (Program ROM) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
100
−
Typ.
−
Max.
−
(2)
(3)
−
−
−
−
−
−
−
times
µs
s
Program/erase endurance
Byte program time
Block erase time
Program, erase voltage
Read voltage
50
0.4
−
400
9
5.5
5.5
60
−
−
2.7
2.2
0
V
−
V
Program, erase temperature
−
°C
year
(7)
Ambient temperature = 55°C
20
−
Data hold time
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.00 Mar 28, 2008 Page 283 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.4
Voltage Detection 0 Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Voltage detection level
Condition
Min.
2.2
−
Typ.
2.3
0.9
−
Max.
2.4
−
Vdet0
−
V
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
VCA25 = 1, VCC = 5.0 V
µA
µs
td(E-A)
−
300
(2)
starts
Vccmin
MCU operating voltage minimum value
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 22.5
Voltage Detection 1 Circuit Electrical Characteristics
Standard
Typ.
2.85
40
Symbol
Parameter
Condition
Unit
Min.
2.70
−
Max.
3.00
−
(4)
Vdet1
V
Voltage detection level
(2)
−
µs
µA
µs
Voltage monitor 1 interrupt request generation time
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
−
VCA26 = 1, VCC = 5.0 V
−
0.6
−
−
td(E-A)
−
100
(3)
starts
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
Table 22.6
Voltage Detection 2 Circuit Electrical Characteristics
Standard
Typ.
3.6
Symbol
Parameter
Voltage detection level
Voltage monitor 2 interrupt request generation time
Voltage detection circuit self power consumption
Condition
Unit
Min.
3.3
−
Max.
3.9
−
Vdet2
V
(2)
−
40
0.6
µs
µA
µs
−
VCA27 = 1, VCC = 5.0 V
−
−
td(E-A)
Waiting time until voltage detection circuit operation
−
−
100
(3)
starts
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.1.00 Mar 28, 2008 Page 284 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
(3)
Table 22.7
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics
Standard
Unit
Symbol
Parameter
Condition
Min.
−
Typ.
−
Max.
0.1
(4)
Vpor1
Vpor2
V
V
Power-on reset valid voltage
Power-on reset or voltage monitor 0 reset valid
0
−
Vdet0
voltage
(2)
trth
20
−
−
mV/msec
External power VCC rise gradient
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
(3)
Vdet0
(3)
Vdet0
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
1
× 32
× 32
fOCO-S
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
Figure 22.2
Reset Circuit Electrical Characteristics
Rev.1.00 Mar 28, 2008 Page 285 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.8
Comparator Electrical Characteristics
Standard
Unit
Symbol
Vref
Parameter
Condition
Min.
1.15
−
Typ.
1.25
1.25
Max.
1.35
−
Internal reference voltage
VCC = 2.2 V to 5.5 V, Topr = 25°C
VCC = 2.2 V to 5.5 V,
Topr = −40 to 85°C
V
V
Vcref
Vcin
External input reference voltage
VCC = 2.2 V to 4.0 V
VCC = 4.0 V to 5.5 V
0.5
0.5
−0.3
−
−
−
VCC − 1.1
VCC − 1.5
VCC + 0.3
V
V
V
External comparison voltage input
range
Vofs
Tcrsp
Input offset voltage
Response time
−
−
20
4
120
−
mV
µs
NOTE:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.9
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Symbol
fOCO-F
Parameter
Condition
Unit
Min.
7.76
Typ.
8
Max.
8.24
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
VCC = 4.75 V to 5.25 V
MHz
(2)
Topr = 0 to 60°C
VCC = 2.7 V to 5.5 V
7.68
7.44
7.04
6.8
8
8
8
8
8.32
8.32
8.96
9.2
MHz
MHz
MHz
MHz
(2)
Topr = −20 to 85°C
VCC = 2.7 V to 5.5 V
(2)
Topr = −40 to 85°C
VCC = 2.2 V to 5.5 V
(3)
Topr = −20 to 85°C
VCC = 2.2 V to 5.5 V
(3)
Topr = −40 to 85°C
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h.
3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register.
Table 22.10 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Symbol
fOCO-S
Parameter
Condition
Unit
Min.
30
−
Typ.
125
10
Max.
250
100
−
Low-speed on-chip oscillator frequency
Oscillation stability time
Self power consumption at oscillation
kHz
µs
µA
−
−
VCC = 5.0 V, Topr = 25°C
−
15
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.11 Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Parameter
Condition
Unit
Min.
1
Max.
2000
td(P-R)
Time for internal power supply stabilization during
−
µs
(2)
power-on
(3)
td(R-S)
−
−
150
µs
STOP exit time
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.00 Mar 28, 2008 Page 286 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.12 Electrical Characteristics (1) [VCC = 5 V]
Standard
Unit
Symbol
VOH
Parameter
Output “H” voltage
Condition
IOH = −5 mA
IOH = −200 µA
IOL = 5 mA
Min.
VCC − 2.0
VCC − 0.5
Typ.
−
Max.
VCC
VCC
2.0
V
V
V
V
V
−
VOL
Output “L” voltage
Hysteresis
−
−
IOL = 200 µA
−
−
0.45
−
VT+-VT-
0.1
0.5
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.1
1.0
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 5 V, VCC = 5 V
VI = 0 V, VCC = 5 V
VI = 0 V, VCC = 5 V
−
−
−
−
5.0
−5.0
167
−
µA
µA
kΩ
MΩ
V
RPULLUP Pull-up resistance
RfXCIN
VRAM
30
−
50
18
−
Feedback resistance XCIN
RAM hold voltage
During stop mode
2.0
−
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 287 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.13 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
on-chip oscillator mode
No division
Power supply current High-speed
−
−
−
−
5
8
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
2
−
mA
µA
µA
Low-speed
130
130
300
300
on-chip oscillator mode
Low-speed clock mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
−
−
30
25
−
µA
µA
Flash memory off, FMSTP = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
Wait mode
75
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
23
4
60
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
−
−
−
2.2
8
−
−
−
3
−
8
−
µA
µA
µA
µA
µA
µA
µA
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
6
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Stop mode
0.8
1.2
5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
5.5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 288 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 22.14 XCIN Input
Standard
Unit
Symbol
Parameter
Min.
14
7
Max.
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
−
−
−
µs
µs
µs
7
VCC = 5 V
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 22.3
XCIN Input Timing Diagram when VCC = 5 V
Table 22.15 TRAIO Input
Standard
Max.
Symbol
Parameter
Unit
Min.
100
40
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
40
tC(TRAIO)
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.4
TRAIO Input Timing Diagram when VCC = 5 V
Rev.1.00 Mar 28, 2008 Page 289 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.16 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
200
100
100
−
Max.
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
50
−
0
50
90
RXDi input setup time
RXDi input hold time
−
−
i = 0 or 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 or 2
Figure 22.5
Serial Interface Timing Diagram when VCC = 5 V
Table 22.17 External Interrupt INTi (i = 0 or 1) Input
Standard
Symbol
Parameter
Unit
Min.
Max.
(1)
tW(INH)
−
ns
ns
250
250
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.6
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.1.00 Mar 28, 2008 Page 290 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.18 Electrical Characteristics (3) [VCC = 3 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage
Condition
IOH = −1 mA
Min.
VCC − 0.5
−
Typ.
−
Max.
VCC
0.5
−
VOH
VOL
VT+-VT-
V
V
V
Output “L” voltage
Hysteresis
IOL = 1 mA
−
0.1
0.3
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.1
0.4
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 3 V, VCC = 3 V
VI = 0 V, VCC = 3 V
VI = 0 V, VCC = 3 V
−
−
−
−
4.0
−4.0
500
−
µA
µA
kΩ
MΩ
V
RPULLUP Pull-up resistance
RfXCIN
VRAM
66
−
160
18
−
Feedback resistance XCIN
RAM hold voltage
During stop mode
1.8
−
NOTE:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 291 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.19 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
on-chip oscillator mode
No division
Power supply current High-speed
−
−
−
−
5
−
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
2
−
mA
µA
µA
Low-speed
130
130
300
300
on-chip oscillator mode
Low-speed clock mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
−
−
30
25
−
µA
µA
Flash memory off, FMSTP = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
Wait mode
70
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
23
55
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
3.8
−
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
−
−
−
2
8
−
−
−
3
−
7
−
µA
µA
µA
µA
µA
µA
µA
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
6
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Stop mode
0.7
1.1
5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
5.5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 292 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Table 22.20 XCIN Input
Standard
Unit
Symbol
Parameter
Min.
14
7
Max.
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
−
−
−
µs
µs
µs
7
tC(XCIN)
VCC = 3 V
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 22.7
XCIN Input Timing Diagram when VCC = 3 V
Table 22.21 TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
300
120
120
Max.
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
VCC = 3 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.8
TRAIO Input Timing Diagram when VCC = 3 V
Rev.1.00 Mar 28, 2008 Page 293 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.22 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
300
150
150
−
Max.
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
80
−
0
70
90
RXDi input setup time
RXDi input hold time
−
−
i = 0 or 2
tC(CK)
VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 or 2
Figure 22.9
Serial Interface Timing Diagram when VCC = 3 V
Table 22.23 External Interrupt INTi (i = 0 or 1) Input
Standard
Min. Max.
Symbol
Parameter
Unit
(1)
tW(INH)
−
ns
ns
380
380
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.10 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.1.00 Mar 28, 2008 Page 294 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.24 Electrical Characteristics (5) [VCC = 2.2 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage
Condition
IOH = −1 mA
Min.
VCC − 0.5
−
Typ.
−
Max.
VCC
0.5
−
VOH
VOL
VT+-VT-
V
V
V
Output “L” voltage
Hysteresis
IOL = 1 mA
−
0.05
0.3
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, RXD2,
CLK0, CLK2
0.05
0.15
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 2.2 V
VI = 0 V
VI = 0 V
−
−
−
−
4.0
−4.0
600
−
µA
µA
kΩ
MΩ
V
RPULLUP Pull-up resistance
RfXCIN
VRAM
100
−
200
35
−
Feedback resistance XCIN
RAM hold voltage
During stop mode
1.8
−
NOTE:
1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 295 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.25 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
on-chip oscillator mode
No division
Power supply current High-speed
−
−
−
−
3.5
−
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
FMR47 = 1
1.5
−
mA
µA
µA
Low-speed
100
100
230
230
on-chip oscillator mode
Low-speed clock mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
Program operation on RAM
−
−
25
22
−
µA
µA
Flash memory off, FMSTP = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
Wait mode
60
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
20
3
55
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
−
−
−
1.8
7
−
−
−
3
−
7
−
µA
µA
µA
µA
µA
µA
µA
BGR trimming circuit disabled (BGRCR0 = 1)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
BGR trimming circuit enabled (BGRCR0 = 0)
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
6
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Stop mode
0.7
1.1
5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
XCIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
XCIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
5.5
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 296 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Table 22.26 XCIN Input
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
14
7
7
−
−
−
µs
µs
µs
tC(XCIN)
VCC = 2.2 V
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 22.11 XCIN Input Timing Diagram when VCC = 2.2 V
Table 22.27 TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
500
200
200
Max.
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
tC(TRAIO)
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.12 TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.1.00 Mar 28, 2008 Page 297 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.28 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
800
400
400
−
Max.
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
200
−
0
RXDi input setup time
RXDi input hold time
150
90
−
−
i = 0 or 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 or 2
Figure 22.13 Serial Interface Timing Diagram when VCC = 2.2 V
Table 22.29 External Interrupt INTi (i = 0 or 1) Input
Standard
Min. Max.
Symbol
Parameter
Unit
(1)
tW(INH)
−
ns
ns
1000
1000
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.14 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.1.00 Mar 28, 2008 Page 298 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
22.2 R8C/2J Group
Table 22.30 Absolute Maximum Ratings
Symbol
VCC
Parameter
Condition
Rated Value
Unit
V
V
V
mW
°C
Supply voltage
Input voltage
Output voltage
−0.3 to 6.5
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
500
−20 to 85 (N version) /
−40 to 85 (D version)
VI
VO
Pd
Power dissipation
Operating ambient temperature
Topr = 25°C
Topr
Tstg
Storage temperature
−65 to 150
°C
Table 22.31 Recommended Operating Conditions
Standard
Typ.
−
Symbol
Parameter
Conditions
Unit
Min.
2.2
−
Max.
5.5
VCC
VSS
VIH
VIL
IOH(sum)
Supply voltage
Supply voltage
Input “H” voltage
Input “L” voltage
Peak sum output “H”
current
V
V
V
V
mA
0
−
−
0.8 VCC
VCC
0.2 VCC
−160
0
−
−
Sum of all pins IOH(peak)
Sum of all pins IOH(avg)
−
IOH(sum)
Average sum output “H”
−
−
−80
mA
current
IOH(peak)
IOH(avg)
Peak output “H” current
Average output “H”
current
All pins
All pins
−
−
−
−
−10
−5
mA
mA
IOL(sum)
IOL(sum)
Peak sum output “L”
Sum of all pins IOL(peak)
Sum of all pins IOL(avg)
All pins
−
−
−
−
160
80
mA
mA
currents
Average sum output “L”
currents
Peak output “L” currents
Average output “L” current All pins
System clock
IOL(peak)
IOL(avg)
−
−
−
−
−
−
10
5
mA
mA
kHz
HRA01 = 0
125
−
Low-speed on-chip
oscillator selected
HRA01 = 1
−
−
−
−
8
4
MHz
MHz
High-speed on-chip
oscillator selected
2.7 V ≤ VCC ≤ 5.5 V
HRA01 = 1
High-speed on-chip
oscillator selected
2.2 V ≤ VCC ≤ 5.5 V
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
P1
P3
30pF
P4
P6
Figure 22.15 Ports P1, P3, P4, and P6 Timing Measurement Circuit
Rev.1.00 Mar 28, 2008 Page 299 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.32 Flash Memory (Program ROM) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
100
−
Typ.
−
Max.
−
(2)
(3)
−
−
−
−
−
−
−
times
µs
s
Program/erase endurance
Byte program time
Block erase time
Program, erase voltage
Read voltage
50
0.4
−
400
9
5.5
5.5
60
−
−
2.7
2.2
0
V
−
V
Program, erase temperature
−
°C
year
(7)
Ambient temperature = 55°C
20
−
Data hold time
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.00 Mar 28, 2008 Page 300 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.33 Voltage Detection 0 Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Voltage detection level
Condition
Min.
2.2
−
Typ.
2.3
0.9
−
Max.
2.4
−
Vdet0
V
−
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
VCA25 = 1, VCC = 5.0 V
µA
µs
td(E-A)
−
300
(2)
starts
Vccmin
MCU operating voltage minimum value
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 22.34 Voltage Detection 1 Circuit Electrical Characteristics
Standard
Symbol
Parameter
Condition
Unit
Min.
2.70
−
Typ.
2.85
40
0.6
−
Max.
3.00
−
(4)
Vdet1
V
Voltage detection level
(2)
−
µs
µA
µs
Voltage monitor 1 interrupt request generation time
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
−
VCA26 = 1, VCC = 5.0 V
−
−
td(E-A)
−
100
(3)
starts
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
Table 22.35 Voltage Detection 2 Circuit Electrical Characteristics
Standard
Symbol
Parameter
Voltage detection level
Voltage monitor 2 interrupt request generation time
Voltage detection circuit self power consumption
Condition
Unit
Min.
3.3
−
Typ.
3.6
40
0.6
−
Max.
3.9
−
Vdet2
V
(2)
−
µs
µA
µs
−
VCA27 = 1, VCC = 5.0 V
−
−
td(E-A)
Waiting time until voltage detection circuit operation
−
100
(3)
starts
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.1.00 Mar 28, 2008 Page 301 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
(3)
Table 22.36 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics
Standard
Typ.
−
Symbol
Parameter
Condition
Unit
Min.
−
Max.
0.1
Vdet0
(4)
Vpor1
Vpor2
V
V
Power-on reset valid voltage
Power-on reset or voltage monitor 0 reset valid
0
−
voltage
(2)
trth
20
−
−
mV/msec
External power VCC rise gradient
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
(3)
Vdet0
(3)
Vdet0
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
1
× 32
× 32
fOCO-S
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
Figure 22.16 Reset Circuit Electrical Characteristics
Rev.1.00 Mar 28, 2008 Page 302 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.37 Comparator Electrical Characteristics
Standard
Unit
Symbol
Vref
Parameter
Condition
Min.
1.15
−
Typ.
1.25
1.25
Max.
1.35
−
Internal reference voltage
VCC = 2.2 V to 5.5 V, Topr = 25°C
VCC = 2.2 V to 5.5 V,
Topr = −40 to 85°C
V
V
Vcref
Vcin
External input reference voltage
VCC = 2.2 V to 4.0 V
VCC = 4.0 V to 5.5 V
0.5
0.5
−0.3
−
−
−
VCC − 1.1
VCC − 1.5
VCC + 0.3
V
V
V
External comparison voltage input
range
Vofs
Tcrsp
Input offset voltage
Response time
−
−
20
4
120
−
mV
µs
NOTE:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.38 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Symbol
fOCO-F
Parameter
Condition
Unit
Min.
7.76
Typ.
8
Max.
8.24
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
VCC = 4.75 V to 5.25 V
MHz
(2)
Topr = 0 to 60°C
VCC = 2.7 V to 5.5 V
7.68
7.44
7.04
6.8
8
8
8
8
8.32
8.32
8.96
9.2
MHz
MHz
MHz
MHz
(2)
Topr = −20 to 85°C
VCC = 2.7 V to 5.5 V
(2)
Topr = −40 to 85°C
VCC = 2.2 V to 5.5 V
(3)
Topr = −20 to 85°C
VCC = 2.2 V to 5.5 V
(3)
Topr = −40 to 85°C
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h.
3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register.
Table 22.39 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Symbol
fOCO-S
Parameter
Condition
Unit
Min.
30
−
Typ.
125
10
Max.
250
100
−
Low-speed on-chip oscillator frequency
Oscillation stability time
Self power consumption at oscillation
kHz
µs
µA
−
−
VCC = 5.0 V, Topr = 25°C
−
15
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 22.40 Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Parameter
Condition
Unit
Min.
1
Max.
2000
td(P-R)
Time for internal power supply stabilization during
−
µs
(2)
power-on
(3)
td(R-S)
−
−
150
µs
STOP exit time
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.00 Mar 28, 2008 Page 303 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.41 Electrical Characteristics (1) [VCC = 5 V]
Standard
Unit
Symbol
VOH
Parameter
Output “H” voltage
Condition
IOH = −5 mA
IOH = −200 µA
IOL = 5 mA
Min.
VCC − 2.0
VCC − 0.5
Typ.
−
Max.
VCC
VCC
2.0
V
V
V
V
V
−
VOL
Output “L” voltage
Hysteresis
−
−
IOL = 200 µA
−
−
0.45
−
VT+-VT-
0.1
0.5
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, CLK0
0.1
1.0
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 5 V, VCC = 5 V
VI = 0 V, VCC = 5 V
VI = 0 V, VCC = 5 V
During stop mode
−
−
−
−
5.0
−5.0
167
−
µA
µA
kΩ
V
RPULLUP Pull-up resistance
VRAM
30
2.0
50
−
RAM hold voltage
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 304 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.42 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
Power supply current High-speed
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
5
8
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
on-chip oscillator
mode
2
−
mA
µA
µA
Low-speed
on-chip oscillator
mode
130
25
300
75
Wait mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
23
60
3
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Topr = 25°C
Stop mode
0.8
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 85°C
−
−
−
1.2
−
8
−
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 25°C
5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Topr = 85°C
5.5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 305 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 22.43 TRAIO Input
Standard
Unit
Symbol
Parameter
Min.
100
40
Max.
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
40
tC(TRAIO)
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.17 TRAIO Input Timing Diagram when VCC = 5 V
Rev.1.00 Mar 28, 2008 Page 306 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.44 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
200
100
100
−
Max.
tc(CK)
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXD0 output delay time
TXD0 hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
50
−
0
50
90
RXD0 input setup time
RXD0 input hold time
−
−
VCC = 5 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
RXD0
td(C-Q)
tsu(D-C)
th(C-D)
Figure 22.18 Serial Interface Timing Diagram when VCC = 5 V
Table 22.45 External Interrupt INTi (i = 0 or 1) Input
Standard
Symbol
Parameter
Unit
Min.
Max.
(1)
tW(INH)
−
ns
ns
250
250
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.19 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.1.00 Mar 28, 2008 Page 307 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.46 Electrical Characteristics (3) [VCC = 3 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage
Condition
IOH = −1 mA
Min.
VCC − 0.5
−
Typ.
−
Max.
VCC
0.5
−
VOH
VOL
VT+-VT-
V
V
V
Output “L” voltage
Hysteresis
IOL = 1 mA
−
0.1
0.3
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, CLK0
0.1
0.4
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 3 V, VCC = 3 V
VI = 0 V, VCC = 3 V
VI = 0 V, VCC = 3 V
During stop mode
−
−
−
−
4.0
−4.0
500
−
µA
µA
kΩ
V
RPULLUP Pull-up resistance
VRAM
66
1.8
160
−
RAM hold voltage
NOTE:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 308 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.47 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
Power supply current High-speed
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
5
−
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
on-chip oscillator
mode
2
−
mA
µA
µA
Low-speed
on-chip oscillator
mode
130
25
300
70
Wait mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
23
55
3
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Topr = 25°C
Stop mode
0.7
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 85°C
−
−
−
1.1
−
7
−
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 25°C
5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Topr = 85°C
5.5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 309 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Table 22.48 TRAIO Input
Standard
Unit
Symbol
Parameter
Min.
300
120
120
Max.
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
−
−
−
ns
ns
ns
VCC = 3 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.20 TRAIO Input Timing Diagram when VCC = 3 V
Rev.1.00 Mar 28, 2008 Page 310 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.49 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
300
150
150
−
Max.
tc(CK)
CLK0 input cycle time
CLK0 input “H” width
CLK0 Input “L” width
TXD0 output delay time
TXD0 hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
80
−
0
70
90
RXD0 input setup time
RXD0 input hold time
−
−
tC(CK)
VCC = 3 V
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
RXD0
td(C-Q)
tsu(D-C)
th(C-D)
Figure 22.21 Serial Interface Timing Diagram when VCC = 3 V
Table 22.50 External Interrupt INTi (i = 0 or 1) Input
Standard
Min. Max.
Symbol
Parameter
Unit
(1)
tW(INH)
−
ns
ns
380
380
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.22 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.1.00 Mar 28, 2008 Page 311 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.51 Electrical Characteristics (5) [VCC = 2.2 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage
Condition
IOH = −1 mA
Min.
VCC − 0.5
−
Typ.
−
Max.
VCC
0.5
−
VOH
VOL
VT+-VT-
V
V
V
Output “L” voltage
Hysteresis
IOL = 1 mA
−
0.05
0.3
INT0, INT1,
KI0, KI1, KI2, KI3,
RXD0, CLK0
0.05
0.15
−
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 2.2 V
VI = 0 V
VI = 0 V
−
−
−
−
4.0
−4.0
600
−
µA
µA
kΩ
MΩ
V
RPULLUP Pull-up resistance
RfXCIN
VRAM
100
−
200
35
−
Feedback resistance XCIN
RAM hold voltage
During stop mode
1.8
−
NOTE:
1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Rev.1.00 Mar 28, 2008 Page 312 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.52 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
Symbol
ICC
Parameter
Condition
Unit
mA
Power supply current High-speed
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
High-speed on-chip oscillator on = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
−
−
−
3.5
1.5
100
22
−
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
on-chip oscillator
mode
−
mA
µA
µA
Low-speed
on-chip oscillator
mode
230
60
Wait mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
−
−
20
55
3
µA
µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Topr = 25°C
Stop mode
0.7
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 85°C
−
−
−
1.1
−
7
−
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit disabled (BGRCR0 = 1)
Topr = 25°C
5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Topr = 85°C
5.5
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
BGR trimming circuit enabled (BGRCR0 = 0)
Rev.1.00 Mar 28, 2008 Page 313 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Table 22.53 TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
500
200
200
−
−
−
ns
ns
ns
tC(TRAIO)
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 22.23 TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.1.00 Mar 28, 2008 Page 314 of 341
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R8C/2H Group, R8C/2J Group
22. Electrical Characteristics
Table 22.54 Serial Interface
Standard
Unit
Symbol
Parameter
Min.
800
400
400
−
Max.
tc(CK)
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXD0 output delay time
TXD0 hold time
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
−
200
−
0
RXD0 input setup time
RXD0 input hold time
150
90
−
−
VCC = 2.2 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
RXD0
td(C-Q)
tsu(D-C)
th(C-D)
Figure 22.24 Serial Interface Timing Diagram when VCC = 2.2 V
Table 22.55 External Interrupt INTi (i = 0 or 1) Input
Standard
Min. Max.
Symbol
Parameter
Unit
(1)
tW(INH)
−
ns
ns
1000
1000
INTi input “H” width
INTi input “L” width
(2)
tW(INL)
−
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 or 1
Figure 22.25 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.1.00 Mar 28, 2008 Page 315 of 341
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R8C/2H Group, R8C/2J Group
23. Usage Notes
23. Usage Notes
23.1 Notes on I/O Ports
23.1.1 Port P4_3, P4_4 (for R8C/2H Group only)
Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset
period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can
be switched to the port functions by setting the CM04 bit in the CM0 register to 0 (ports P4_3 and P4_4) by a
program.
To use ports P4_3 and P4_4 as ports, note the following:
• Port P4_3
After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, a typical 10 MΩ impedance is
connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level
input or left floating, a shoot-through current flows into the oscillation driver.
• Port P4_4
Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset
until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate
potential of about 2.0 V.
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23. Usage Notes
23.2 Notes on Clock Generation Circuit
23.2.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
LABEL_001 :
NOP
NOP
NOP
NOP
23.2.2 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
FSET
WAIT
NOP
1,FMR0
I
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
NOP
NOP
NOP
23.2.3 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
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23. Usage Notes
23.3 Notes on Interrupts
23.3.1 Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
23.3.2 SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
23.3.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0, INT1 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), Table 22.29 (VCC = 2.2V), Table
22.45 (VCC = 5V), Table 22.50 (VCC = 3V), and Table 22.55 (VCC = 2.2V) External Interrupt INTi (i = 0
or 1) Input.
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23. Usage Notes
23.3.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 23.1 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts(2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 13.5.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 23.1
Example of Procedure for Changing Interrupt Sources
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23. Usage Notes
23.3.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
NOP
NOP
; Set TRAIC register to 00h
;
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
AND.B #00H,0056H
MOV.W MEM,R0
I
; Disable interrupts
; Set TRAIC register to 00h
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B #00H,0056H
POPC FLG
I
; Disable interrupts
; Set TRAIC register to 00h
; Enable interrupts
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23. Usage Notes
23.4 Notes on ID Code Areas
23.4.1 Setting Example of ID Code Areas
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing
an instruction. Write appropriate values when creating a program. The following shows a setting example.
• To set 55h in all of the ID code areas
.org 00FFDCH
.lword dummy | (55000000h) ; UND
.lword dummy | (55000000h) ; INTO
.lword dummy ; BREAK
.lword dummy | (55000000h) ; ADDRESS MATCH
.lword dummy | (55000000h) ; SET SINGLE STEP
.lword dummy | (55000000h) ; WDT
.lword dummy | (55000000h) ; ADDRESS BREAK
.lword dummy | (55000000h) ; RESERVE
(Programming formats vary depending on the compiler. Check the compiler manual.)
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23. Usage Notes
23.5 Notes on Option Function Select Area
23.5.1 Setting Example of Option Function Select Area
As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by
executing an instruction. Write appropriate values when creating a program. The following shows a setting
example.
• To set FFh in the OFS register
.org 00FFFCH
.lword reset | (0FF000000h)
; RESET
(Programming formats vary depending on the compiler. Check the compiler manual.)
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23. Usage Notes
23.6 Notes on Timers
23.6.1 Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
(1)
During this time, do not access registers associated with timer RA other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
(1)
During this time, do not access registers associated with timer RA other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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23. Usage Notes
23.6.2 Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
(1)
During this time, do not access registers associated with timer RB other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
(1)
During this time, do not access registers associated with timer RB other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
23.6.2.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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23. Usage Notes
23.6.2.2 Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 23.2 and 23.3.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 23.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
Primary period
Secondary period
TRBO pin output
IR bit in
TRBIC register
Interrupt request is
acknowledged
(a)
Ensure sufficient time
(b)
Interrupt
Instruction in
Set the secondary and then
the primary register immediately
Interrupt request
is generated
sequence interrupt routine
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 23.2
Workaround Example (a) When Timer RB interrupt is Used
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• Workaround example (b):
23. Usage Notes
As shown in Figure 23.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
Primary period
Secondary period
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
Upon detecting (i), set the secondary and
then the primary register immediately.
is detected at the end of the
secondary period.
Figure 23.3
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
23.6.2.3 Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
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23. Usage Notes
23.6.2.4 Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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23. Usage Notes
23.6.3 Notes on Timer RE (for R8C/2H Group only)
23.6.3.1 Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
(1)
1. During this time, do not access registers associated with timer RE other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, TRECSR,
and TREOPR.
23.6.3.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 23.4 shows a Setting Example in Real-Time Clock Mode.
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23. Usage Notes
TRERST in TRECR1 register = 1
Timer RE register
and control circuit reset
TRERST in TRECR1 register = 0
TSTART in TRECR1 register = 0
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
Disable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 0
TREIC register ← 00h
(disable timer RE interrupt)
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR, TREWK,
and bits H12_H24, PM, and INT
in TRECR1 register
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Setting of TRECR2 register
Select interrupt source
Setting of TREIC register (IR bit ← 0,
select interrupt priority level)
Enable timer RE clock output
(When it is necessary)
TOENA in TRECR1 register = 1
TSTART in TRECR1 register = 1
Start timer RE operation
TCSTF in
TRECR1 register = 1?
Figure 23.4
Setting Example in Real-Time Clock Mode
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23. Usage Notes
23.6.3.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
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23. Usage Notes
23.6.4 Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0
; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
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23. Usage Notes
23.7 Notes on Serial Interface
•
When reading data from the UiRB (i = 0 or 2 (for the R8C/2H Group only)) register either in the clock
synchronous serial I/O mode or in the clock asynchronous serial I/O mode. Ensure the data is read in 16-bit
units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI
bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
#XXH,00A2H ; Write the low-order byte of U0TB register
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23. Usage Notes
23.8 Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
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23. Usage Notes
23.9 Notes on Flash Memory
23.9.1 CPU Rewrite Mode
23.9.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register.
23.9.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
23.9.1.3 Non-Maskable Interrupts
• EW0 Mode
Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt
request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts.
As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal
value may not be readable. Execute auto-erasure again and ensure it completes normally.
The watchdog timer does not stop during command operation, so that interrupt requests may be generated.
Initialize the watchdog timer regularly.
Do not use the address match interrupt while a command is being executed because the vector of the
address match interrupt is allocated in ROM.
Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is
allocated in block 0.
23.9.1.4 How to Access
Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1
register to 1. Do not generate an interrupt between writing 0 and 1.
23.9.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
23.9.1.6 Program
Do not write additions to the already programmed address.
23.9.1.7 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Rev.1.00 Mar 28, 2008 Page 334 of 341
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23. Usage Notes
23.10 Notes on Noise
23.10.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
23.10.2 Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
Rev.1.00 Mar 28, 2008 Page 335 of 341
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R8C/2H Group, R8C/2J Group
24. Notes for On-Chip Debugger
24. Notes for On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/2H Group and R/2J Group, take note of
the following:
(1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
(2) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
(3) Do not use the BRK instruction in a user system.
(4) Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for
details.
Rev.1.00 Mar 28, 2008 Page 336 of 341
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R8C/2H Group, R8C/2J Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
RENESAS Code
PLSP0020JB-A
Previous Code
20P2F-A
MASS[Typ.]
0.1g
P-LSSOP20-4.4x6.5-0.65
11
20
NOTE)
F
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
10
Index mark
c
A2
A1
Dimension in Millimeters
Reference
Symbol
*2
D
Min Nom Max
D
E
6.4 6.5 6.6
4.3 4.4 4.5
1.15
A2
A
1.45
0.1 0.2
0
A1
bp
c
*3
bp
e
0.17 0.22 0.32
Detail F
y
0.2
10°
0.13 0.15
0°
HE
e
6.2 6.4 6.6
0.53 0.65 0.77
0.10
y
L
0.3 0.5 0.7
Rev.1.00 Mar 28, 2008 Page 337 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
Appendix 2. Connection Examples with On-Chip Debugging Emulator
Appendix 2. Connection Examples with On-Chip Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with E8 Emulator (R0E000080KCE00).
VCC
Open collector buffer
20
19
18
17
16
15
14
13
12
11
1
User logic
4.7kΩ or more
2
3
Connect oscillation circuit(1)
VSS
4
5
6
7
4.7kΩ ±10%
8
13
RESET
14
12
10
8
9
MODE
10
7
MODE
VCC
6
4
2
VSS
NOTE:
E8 emulator
(R0E000080KCE00)
1. It is not necessary to connect an oscillation circuit when
operating the R8C/2H Group with the on-chip oscillator clock.
Appendix Figure 2.1
Connection Example with E8 Emulator (R0E000080KCE00)
Rev.1.00 Mar 28, 2008 Page 338 of 341
REJ09B0388-0100
R8C/2H Group, R8C/2J Group
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
VCC
20
19
18
17
16
15
14
13
12
11
1
2
3
RESET
4
Connect
5
VSS
oscillation
circuit
6
7
8
9
10
NOTE:
1. After reset, the XCIN clock stop.
Write a program to oscillate the XCIN clock.
Appendix Figure 3.1
Example of Oscillation Evaluation Circuit
Rev.1.00 Mar 28, 2008 Page 339 of 341
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R8C/2H Group, R8C/2J Group
Index
Index
PUR1 ..................................................................................... 82
[ A ]
AIER .................................................................................... 137
ALCMR .................................................................................. 59
[ R ]
RMAD0 ................................................................................ 137
RMAD1 ................................................................................ 137
[ B ]
BGRCR ................................................................................. 60
BGRTRM ............................................................................... 61
BGRTRMA ............................................................................ 55
BGRTRMB ............................................................................ 55
[ S ]
S0RIC .................................................................................. 123
S0TIC .................................................................................. 123
S2RIC .................................................................................. 123
S2TIC .................................................................................. 123
[ C ]
CAPIC ................................................................................. 123
CM0 ................................................................................. 96, 97
CM1 ................................................................................. 98, 99
CMP0IC ............................................................................... 123
CMP1IC ............................................................................... 123
CPSRF ................................................................................ 102
CSPR .................................................................................. 151
[ T ]
TRA ..................................................................................... 160
TRACR ................................................................................ 159
TRAIC .................................................................................. 123
TRAIOC ....................................... 159, 161, 164, 166, 168, 171
TRAMR ................................................................................ 160
TRAPRE .............................................................................. 160
TRBCR ................................................................................ 175
TRBIC .................................................................................. 123
TRBIOC ............................................... 176, 178, 182, 185, 189
TRBMR ................................................................................ 176
TRBOCR ............................................................................. 175
TRBPR ................................................................................ 177
TRBPRE .............................................................................. 177
TRBSC ................................................................................ 177
TRECR1 ...................................................................... 200, 207
TRECR2 ...................................................................... 201, 207
TRECSR ...................................................................... 202, 208
TREHR ................................................................................ 199
TREIC .................................................................................. 123
TREMIN ....................................................................... 198, 206
TREOPR .............................................................................. 202
TRESEC ...................................................................... 198, 206
TREWK ................................................................................ 199
TRF ...................................................................................... 215
TRFCR0 .............................................................................. 216
TRFCR1 .............................................................................. 217
TRFCR2 .............................................................................. 216
TRFIC .................................................................................. 123
TRFM0 ................................................................................. 215
TRFM1 ................................................................................. 215
TRFOUT .............................................................................. 217
[ F ]
FMR0 .................................................................................. 262
FMR1 .................................................................................. 265
FMR4 .................................................................................. 266
FRA4 ................................................................................... 102
FRA6 ................................................................................... 102
[ H ]
HRA0 ................................................................................... 101
HRA1 ................................................................................... 101
HRA2 ................................................................................... 101
[ I ]
INT0IC ................................................................................. 124
INT1IC ................................................................................. 124
INTEN ................................................................................. 131
INTF .................................................................................... 132
[ K ]
KIEN .................................................................................... 135
KUPIC ................................................................................. 123
[ L ]
LINCR ................................................................................. 244
LINST .................................................................................. 245
[ U ]
U0BRG ................................................................................ 228
U0C0 ................................................................................... 229
U0C1 ................................................................................... 230
U0MR .................................................................................. 228
U0RB ................................................................................... 230
U0TB ................................................................................... 229
U2BRG ................................................................................ 228
U2C0 ................................................................................... 229
U2C1 ................................................................................... 230
U2MR .................................................................................. 228
U2RB ................................................................................... 230
U2TB ................................................................................... 229
[ O ]
OCD .................................................................................... 100
OFS ............................................................... 33, 144, 152, 260
[ P ]
PDi (i = 1, 3, 4, or 6) ........................................................ 78, 79
Pi (i = 1, 3, 4, or 6) ........................................................... 78, 79
PINSR2 ................................................................................. 80
PINSR4 ..................................................................... 46, 61, 80
PM0 ....................................................................................... 91
PM1 ....................................................................................... 91
PMR ...................................................................................... 81
PRCR .................................................................................. 117
PUR0 ..................................................................................... 82
[ V ]
VCA1 ............................................................................... 42, 56
VCA2 ....................................................................... 42, 56, 103
VCAB ..................................................................................... 59
Rev.1.00 Mar 28, 2008 Page 340 of 341
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Index
VCAC .............................................................................. 46, 60
VCMP1IC ............................................................................ 123
VCMP2IC ............................................................................ 123
VW0C .................................................................................... 43
VW1C .............................................................................. 44, 57
VW2C .............................................................................. 45, 58
[ W ]
WDC .................................................................................... 150
WDTR ................................................................................. 149
WDTS .................................................................................. 149
Rev.1.00 Mar 28, 2008 Page 341 of 341
REJ09B0388-0100
REVISION HISTORY
R8C/2H Group, R8C/2J Group Hardware Manual
Description
Summary
Rev.
Date
Page
0.01
0.10
Apr 06, 2007
Jul 20, 2007
−
−
−
First Edition issued
Descriptions about “R8C/2J” added
“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A164A/E, TN-16C-A167A/E
−
Register/bit symbols revised:
“CM1POR” → “LCM1POR”, “CM2POR” → “LCM2POR”,
“ACMR” → “ALCMR”
2
Table 1.1: Clock; “Real-time clock (timer RE)” added
Table 4.2, Figure 6.6: 0038h After reset;
“0000X010b” → “1000X010b”, “0100X011b” → “1100X011b”
20, 43
32
Figure 5.3 revised
33, 139, Figure 5.4, Figure 15.2, Figure 16.6, Figure 20.2:
147, 252
69
OFS Register; NOTE1 revised
Table 8.3, Table 8.4: NOTE1 revised
Figure 8.5, Figure 8.6: revised
Figure 8.11 revised
74
78
157
Figure 17.5 “Both bits .... register are set to 0 (During count).”
→ “Both bits .... register are set to 1 (During count).”
175
Figure 17.17 “Both bits .... register are set to 0 (During count).”
→ “Both bits .... register are set to 1 (During count).”
186
240
241
NOTE: “TRBIOC” added
Figure 19.6 revised
Figure 19.7: SFDCT flag in the LINST register;
“Set by ....the B1CLR bit in the LINST register” →
“Set by ....the B0CLR bit in the LINST register”
243
250
286
2
Figure 19.9 revised
Figure 20.1 revised
Figure 21.2 NOTE4 deleted
Table 1.1 I/O Ports: “• Output-only: 1” added
“• CMOS I/O ports: 16” → “• CMOS I/O ports: 15”
0.20
Nov 12, 2007
6
8
Figure 1.3 revised
Figure 1.5 revised
9
Table 1.5 Pin Number: 4, 6, 16 revised
12
Table 1.7 I/O port: “P4_3 to P4_5” → “P4_3, P4_5”
Timer RE, Output port added
19
23
Table 4.1 0006h “01001000b” → “01011000b”
Table 4.5 0118h to 011Dh: After reset revised
011Fh “Timer RE Real-Time Clock Precision Adjust Register”
added
52
Figure 6.13 revised
C - 1
REVISION HISTORY
R8C/2H Group, R8C/2J Group Hardware Manual
Description
Summary
Rev.
0.20
Date
Page
68
Nov 12, 2007
8. “There are 16 input/output .... oscillation circuit is not used.” →
“There are 15 input/output .... used as an output port.
Table 8.1 revised, NOTE3 added
72
74
78
83
Figure 8.3 revised
Figure 8.5 NOTE2 “To use port P4_4 as ... an input port.” added
Figure 8.11 Pull-Up Control Register 1 (R8C/2H Group): b1 revised
Table 8.16 NOTE2 added
Table 8.17 revised
84
86
89
Table 8.21 revised
8.6 added
Table 11.1 Oscillator status after reset: XCIN Clock Oscillation Circuit
“Stop” → “Oscillate”
92
Figure 11.3 revised
102
11.2 “During and after reset, the XCIN clock stops.” → “During and after
reset, the XCIN clock oscillates.”
154
192
193
194
195
Figure 17.1 “TSTART” → “TCSTF”
Figure 17.26 revised
Table 17.11 revised
Figure 17.27, Figure 17.28 After Reset “00h” → “Undefined”
Figure 17.29 After Reset “00h” → “X0XXXXXXb”
Figure 17.30 After Reset “00h” → “X0000XXXb”
196
197
198
Figure 17.31 After Reset “00h” → “XXX0X0X0b”
Figure 17.33 After Reset “00h” → “00XXXXXXb”
Figure 17.34 revised
Figure 17.35 added
200
201
202
203
Figure 17.37 revised
Table 17.13 revised
Figure 17.38, Figure 17.39 After Reset “00h” → “Undefined”
Figure 17.40 revised
Figure 17.41 After Reset “00h” → “00XXXXXXb”
204
205
206
207
213
247
283
300
Figure 17.42 revised
Figure 17.43 revised
17.3.3.1 NOTE1 “TREOPR” added
Figure 17.44 revised
Figure 17.50 NOTE4 added
Figure 19.9 revised
Table 22.2 NOTE2 revised
Table 22.31 NOTE2 revised
306, 310, Table 22.42, Table 22.47, Table 22.52 revised
314
C - 2
REVISION HISTORY
R8C/2H Group, R8C/2J Group Hardware Manual
Description
Summary
Rev.
Date
Page
330
0.20
1.00
Nov 12, 2007
Figure 23.4 revised
Mar 28, 2008 All pages “Under development” deleted
2, 3
4, 5
Table 1.1, Table 1.2 revised
Table 1.3, Table 1.4; “(D): Under development” deleted
17, 18 Figure 3.1, Figure 3.2; “Expanded area” deleted
19
20
31
32
Table 4.1 “002Eh” “002Fh” revised
Table 4.2 “003Eh” “003Fh” revised
Figure 5.1 NOTE1 added
Table 5.2 revised
45, 58 Figure 6.8, Figure 7.5; “7. The VW2C7 ... 1.” → “7. The VW2C7 ... 0.”
55 Figure 7.2 added
60, 61 Figure 7.9, Figure 7.10 added
70, 71 7.6, Figure 7.16, Figure 7.17 added
89
Table 8.23 NOTE4 revised
Figure 8.12 NOTE2 revised
93
97
99
Table 11.2 revised
Figure 11.4; “01001000b” → “01011000b”, b4 revised, NOTE3 added
Figure 11.6 b4 revised
107, 109 11.3.1, 11.4.1.1, 11.4.1.2; “(for R8C/2H Group only)” added
110
11.4.2 “(for R8C/2H Group only)” added
Table 11.5; Timer RA interrupt: CM02 = 1 “NOTE1” added
117
157
174
181
184
248
251
257
261
12, Figure 12.1; “BGRCR, and BGRTRM” added
Table 17.1 Timer RF “Capture interrupt” added
Figure 17.12 “TSTRAT” → “TSTART”
Table 17.8 “... P3_1 (P1_3) ...” → “... P1_3 ...”
Table 17.9 “TRBP pin function” → “TRBO pin function”
Figure 19.6 “Three to five ...” → “One to two ...”
Figure 19.9 revised
Table 20.1 “Suspend ...” deleted, “Blocks 0 and 1 ...” → “Block 0 ...”
20.4 “The flash module ... (EW0 mode).” deleted
Table 20.3 “... to erase-suspend” “... to program-suspend” deleted
263
264
266
• FMR00 Bit “(including suspend periods)” deleted
Table 20.4 “FRM0 Register ...” → “FMR0 Register ...”
Figure 20.5 revised
• FMR40 Bit, • FMR41 Bit, • FMR42 Bit; deleted
• FMR43 Bit, • FMR44 Bit, • FMR46 Bit; revised
269
271
Figure 20.8 revised
• Program Command; revised
Old Figure 20.11 deleted
C - 3
REVISION HISTORY
R8C/2H Group, R8C/2J Group Hardware Manual
Description
Summary
Rev.
1.00
Date
Page
272
Mar 28, 2008
• Block Erase; revised
Old Figure 20.13, Old 20.4.3.2, Old Figure 20.14, Old Figure 20.15;
deleted
275
277
278
283
Table 20.6 revised
Old 20.7.1.7, Old 20.7.1.8 deleted
21.2.3 “(for R8C/2H Group only)” added
Table 22.3 revised
Old Figure 22.2 deleted
286
Table 22.8, Table 22.11 revised
Table 22.9 revised, NOTE3 added
288
292
296
300
Table 22.13 revised
Table 22.19 revised
Table 22.25 revised
Table 22.32 revised
Old Figure 22.17 deleted
303
Table 22.37, Table 22.40 revised
Table 22.38 revised, NOTE3 added
305
309
313
334
Table 22.42 revised
Table 22.47 revised
Table 22.52 revised
Old 23.9.1.7, Old 23.9.1.8 deleted
C - 4
R8C/2H Group, R8C/2J Group Hardware Manual
Publication Date: Rev.0.01 Apr 06, 2007
Rev.1.00 Mar 28, 2008
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
R8C/2H Group, R8C/2J Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
相关型号：
R8C32M
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