RD151TS502USE [RENESAS]
PLL clock generator series; PLL时钟发生器系列
| 型号： | RD151TS502USE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | PLL clock generator series |
| 文件： | 总7页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RD151TS502US
PLL clock generator series
REJ03D0898-0100
Rev.1.00
Apr 25, 2007
Description
RD151TS502US is phase-locked loop clock generator with high-performance. And RD151TS502US is low-jitters and
will enable high density mounting by shrink small-size package (SSOP-8).
Features
•
•
Input frequency:
27.0 MHz
Output frequency:
27.0 MHz (1 : 1), 33.75 MHz (1 : 1.25)
13.5 MHz (1 : 0.5), 16.875MHz (1 : 0.625) (Selectable)
Key Specifications
•
•
•
•
•
•
•
Supply voltages: VDD = 2.7 to 3.6 V
Operating temperature = -10 to 75 °C
Cycle to cycle jitter = ±75 ps typ.
Clock output duty cycle = 50±5%
Stabilization time: 2ms max
Power-down mode is supported
Ordering Information
Package Code
(Previous Package Code)
Package
Abbreviation
Taping
Abbreviation (Quantity)
Part Name
Package Type
PVSP0008KA–A
(TTP-8DBV)
RD151TS502USE
SSOP-8 pin
US
E (3,000 pcs / Reel)
Pin Arrangement
1
2
3
4
VDD
VDD
VSS
OUT
8
7
6
5
DIV2
IN
SEL
PDWN
(Top view)
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 1 of 6
RD151TS502US
Block Diagram
VDD
VSS
1/M
IN
DIV
Synthesizer
OUT
Rpd = 100 kΩ
1/N
PDWN
Rpd = 100 kΩ
SEL
Rpd = 100 kΩ
Rpd = 100 kΩ
DIV2
Pin Descriptions
Pin name
VDD
No.
1,2
3
Type
Description
Power
Power supply
GND
VSS
Ground
Output
Input
OUT
4
Clock signal output
Power-down control *1
Frequency select *1
Clock signal input *1
Frequency select *1
PDWN
SEL
5
6
Input
IN
7
Input
DIV2
8
Input
Note: 1. LVCMOS level input. Pull-down by internal resistor (100 kΩ).
Power-down Function Table
PDWN
IC Operating
Power-down
Active
OUTPUT
Low level
Remark
Default *1
L
H
Clock signal output
Note: 1. All Circuits are set stand-by condition.
Clock Frequency Table
Output Frequency
(IN:OUT Ratio)
SEL
DIV2
Remark
L
H
L
L
L
27.0 MHz (1:1)
Default
33.75 MHz (1:1.25)
13.5 MHz (1:0.5)
H
H
H
16.875 MHz (1:0.625)
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 2 of 6
RD151TS502US
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VDD+0.5
–50
Unit
V
Conditions
VDD
VI
Input voltage
V
Output voltage
VO
IIK
V
Input clamp current *1
Output clamp current *1
Continuous output current
Maximum power dissipation
Storage temperature
mA
mA
mA
W
VI < 0
IOK
IO
–50
VO < 0
±50
VO = 0 to VDD
PW
Tstg
0.2
Ta = 25°C (in still air)
–65 to +150
°C
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
Symbol
Min
2.7
Typ
3.3
—
Max
3.6
Unit
V
Conditions
VDD
DC input signal voltage
Operating temperature
–0.3
–10
VDD+0.3
75
V
Ta
—
°C
DC Electrical Characteristics
Ta = –10 to 75 °C, VDD = 2.7 to 3.6 V
Unit Test Conditions
Item
Input voltage
Symbol
VIL
Min
—
Typ
Max
—
—
0.8
—
V
V
IN, PDWN, SEL, DIV2 pins
IN, PDWN, SEL, DIV2 pins
VIH
2.0
VI = 0V or 3.6V,
IN, PDWN, SEL, DIV2 pins
Input current
II
—
—
±100
µA
pF
V
Input capacitance
Output voltage
CI
VOL
VOH
IOL
—
—
3
—
—
0.5
VDD
—
IN, PDWN, SEL, DIV2 pins
VOL = 1 mA, VDD = 3.3 V, OUT pin
VOH = –1 mA, VDD = 3.3 V, OUT pin
VOL = 1.65 V, VDD = 3.3 V, OUT pin
VOH = 1.65 V, VDD = 3.3 V, OUT pin
OUT pin
VDD–0.2
—
—
15
mA
mA
Ω
Output current
IOH
—
–15
30
—
Output impedance
Pull-down resister
—
—
Rpd
80 k
100 k
120 k
Ω
Note: The condition of the minimum and maximum value must use the value specified under “Recommended
Operating Conditions”.
Parameters are target of design. Not 100% tested in production.
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 3 of 6
RD151TS502US
AC Electrical Characteristics
Ta = –10 to 75 °C, VDD = 2.7 to 3.3 V, CL = 15 pF
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Notes
VDD = 3.3 V, PDWN = 1, CL = 0 pF
Operating current
IDD
—
6
—
mA
Stand-by current
IDDPD
tCCJ
—
—
—
—
—
10
|75|
—
—
—
—
—
µA
ps
VDD = 3.3 V, PDWN = 0, IN = 0 V
CL=0pF
Cycle to cycle jitter
Figure 1
1
MHz
*
13.5
16.875
27.0
SEL = 0, DIV2 = 1
SEL = 1, DIV2 = 1
SEL = 0, DIV2 = 0
Output Frequency
Figure 2
—
33.75
—
SEL = 1, DIV2 = 0
2
*
Frequency accuracy
Slew Rate
–50
—
—
1.5
50
—
50
—
55
2
ppm
ns
tSR
tDT
tSB
VDD = 3.3 V, 0.2VDD to 0.8VDD
Clock duty cycle
Stabilization time
45
—
%
3
ms
*
Notes: Parameters are target of design. Not 100% tested in production.
1. Output Frequency means average value.
2. The accuracy of the output frequency to a set value.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal
power up.
after
OUT
tcycle n
tcycle n+1
tCC = (tcycle n) – (tcycle n+1)
Figure 1 Cycle to cycle jitter
DIV2
fout
fout/2
OUT
...
f
f
f
f
f/2
f/2
f/2
f
f
Figure 2 Timing chart
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 4 of 6
RD151TS502US
Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 3.
V
DD decoupling is important to reduce Jitter performance.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
DIV2
1
2
3
4
VDD
8
7
6
5
C2 C1
IN
GND GND
SEL
VDD
GND
R2
R1
OUT
PDWN
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF recommended)
R1 = Match value to line impedance.
(Please use R1 if necessary)
R2 = Pull-up resistance.
(51kΩ recommended)
Figure 3 Recommended circuit configuration
Remark for use
•
•
Please do not use the pull-up resistance for the OUT terminal to prevent wrong operation of IC.
Please set the voltage of the PDWN terminal according to the following procedures when it is necessary to set IC
to power-down (standby) operation immediately after the start-up this IC.
1. Set the Hi level voltage when IC starts.
2. Set the Low level voltage after IC starts.
As this counter measures, we recommend the pull-up register that has been described to the above recommended
circuit to be added beforehand.
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 5 of 6
RD151TS502US
Package Dimensions
JEITA Package Code
P-VSSOP8-2.3x2-0.50
RENESAS Code
Previous Code
MASS[Typ.]
0.010g
PVSP0008KA-A
TTP-8DB/TTP-8DBV
D
0.2
F
1.5
8
5
bp
b1
Terminal cross section
Dimension in Millimeters
Reference
Symbol
L1
Min Nom Max
1.8 2.0 2.2
2.2 2.3 2.4
0.6 0.7 0.8
1
4
D
E
A2
A1
A
e
bp
0.1
0
bp
b1
c
0.3
0.15 0.22
0.20
0.08 0.13 0.23
0.11
c1
Detail F
θ
HE
e
2.8 3.1 3.4
(0.5)
x
y
Z
L
L1
(0.4)
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 6 of 6
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