RD15LD74ANP [RENESAS]
8-bit D-type Flip-Flop Driver (with Clear); 8位D型触发器驱动器（带清除）
| 型号： | RD15LD74ANP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-bit D-type Flip-Flop Driver (with Clear) |
| 文件： | 总10页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RD15LD74AP, RD15LD74ANP, RD15LD74AT
8-bit D-type Flip-Flop Driver (with Clear)
REJ03D0894-0300
Rev.3.00
Feb 29, 2008
Description
RD15LD74AP, RD15LD74ANP, RD15LD74AT have eight D-type flip-flop drivers and high voltage NMOS output
(open drain output) in a 20 pin package. Each bit, there are a common clear and clock input. The input signal is output
with the rising edge of clock signals. The voltage of maximum 15 V can be impressed to the drain-source voltage.
Features
•
•
•
•
•
•
•
•
Application of amusement equipment.
Output voltage : VDS (max) = 15 V
Output current : IDS (max) = 200 mA (par pin)
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –20 to +85 °C
Quiescent supply current : 5 µA max.
Low input current : 1 µA max.
Ordering Information
Package Code
(Previous Code)
PRDP0020BA-A
(20P4B)
Package
Packing Abbreviation
(Quantity)
Surface
Part Name
Package Type
SDIP-20 pin
Abbreviation
Treatment
RD15LD74APT0
RD15LD74ANPT0
RD15LD74ATH0
P
P
T
T (1,125 pcs/box)
T (1,000 pcs/box)
H (2,000 pcs/reel)
0 (Sn-Cu)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
PRDP0020AC-B
(DP-20NEV)
DILP-20 pin
PTSP0020JB-A
(TTP-20DAV)
TSSOP-20 pin
Note: Please consult the sales office for the above package availability.
Pin Arrangement
1
2
20 VCC
CLR
D0
19
18
17
Y0
Y1
Y2
3
D1
4
D2
5
16 Y3
15 Y4
D3
6
D4
7
D5
14
Y5
8
13 Y6
12 Y7
D6
9
D7
10
CLK
11
GND
(Top view)
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 1 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Logic Diagram
Y0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y7
19
18
17
16
15
14
13
12
20
VCC
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
10
CK
CK
CK
CK
CK
CK
CK
CLK
CK
R
R
R
R
R
R
R
R
CLR
GND
1
11
2
3
4
5
6
7
8
9
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
Note: Schmitt trigger circuit is added to all input. VH = 1.5 V (TYP)
Function Table
Inputs
Output
CLR
L
CLK
D
X
L
Y
Z
X
↑
↑
L
↓
H
Z
H
H
H
X
X
L
Y0
Y0
H
H : High level
L : Low level
X : Immaterial
Z : High Impedance
↑ : Low to High transition
↓ : High to Low transition
Y0 : Level of Y before the indicated steady input conditions were established.
Timing Figure
VCC
CLK
D
GND
VCC
GND
VCC
CLR
Y
GND
VOH
VOL
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 2 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Output current
Symbol
VCC
VI
Ratings
6.5
Unit
V
Conditions
–0.5 to VCC
–0.5 to 15
200
V
VDS
V
Output : “Z” (off)
IDS
mA
Output : “on” , Current of one circuit
1.47
SDIP
Ta = 25°C
DILP
Maximum power
dissipation *1
PT
W
1.38
Base implementation
TSSOP
0.76
Storage temperature
Tstg
–55 to +125
°C
Note: The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of
which may be realized at the same time.
1. The maximum package power dissipation was calculated using a junction temperature of 150°C
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Symbol
VCC
Ratings
Unit
V
Conditions
3.0
0
5.5
VCC
15
VI
V
Output voltage
VDS
0
V
Output “Z” (off)
0
200
150
200
140
200
105
500
85
Duty cycle ≤ 60%
Duty cycle ≤ 100%
Duty cycle ≤ 55%
Duty cycle ≤ 100%
Duty cycle ≤ 25%
Duty cycle ≤ 100%
mA
mA
mA
SDIP
0
Output current
0
(Current of an one circuit,
when eight circuit
operation)
IDS
DILP
0
0
TSSOP
0
Input rise / fall time
tr, tf
Ta
0
ns
VCC = 3.0 V, 4.5 V
Operating temperature
–20
°C
Note: Unused or floating inputs must be held high or low.
Electrical Characteristics
(Ta = –20 to +85°C)
Ratings
Typ
—
Item
Symbol
VIH
VCC (V)
Unit
V
Conditions
Min
CC×0.84
CC×0.76
—
Max
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
V
V
—
—
—
Input voltage
—
V
CC×0.16
CC×0.24
0.45
0.38
0.90
0.77
1.0
VIL
V
—
—
V
—
0.30
0.25
0.60
0.51
0.005
0.005
I
DS = 100 mA
—
Output voltage
VDS
V
—
IDS = 200 mA
—
“H” input current
“L” input current
IIH
IIL
—
µA
µA
VI = VCC
—
–1.0
VI = 0 V
All output “Z” (off)
VI = VCC or GND
All output “on”, VI = VCC or GND
5.5
5.5
5.0
4.5
—
—
—
—
0.005
0.005
0.002
2.5
5.0
5.0
5.0
3.8
Quiescent supply
current
ICC
µA
Output off state
leak current
IDS
µA
VDS = 12 V
Output on resister
RDS
Ω
IDS = 100 mA
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 3 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Switching Characteristics
(Ta = –20 to +85°C, CL = 30 pF, tr = tf =6 ns )
Ratings
Item
Symbol
fmax
tPLH
tPHL
tsu
VCC (V)
Unit
MHz
ns
Conditions
Min
—
Max
15
20
65
50
60
45
—
—
—
—
—
—
30
20
10
5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Maximum clock
frequency
—
1.0
1.0
1.0
1.0
25
20
3
Propagation delay
time
CLK, CLR to Y
Propagation delay
time
ns
CLK to Y
D to CLK
CLK to D
CLK, CLR
Y
Setup time
ns
Hold time
th
ns
3
50
40
—
Pulse width
Output rise time
Output fall time
tW
ns
tTLH
tTHL
ns
—
—
ns
Y
—
Test Circuit
VT = 12V
VCC
Input
Input
VCC
RL = 120Ω
Palse generator
Ω
CLK
D
Zout
= 50
Output
Y
CLR
Palse generator
Zout
CL = 30 pF
Ω
= 50
GND
Note: 1. Input waveform : PRR = 1MHz, Duty Cycle = 50%, tr = 6ns, tf = 6ns
2. CL includes probe and jig capacitance.
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 4 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Waveforms
•
Waveforms – 1
tr
tf
VCC
90 %
50 %
90 %
50 %
Data Input (D0 to D7)
50 %
10 %
10 %
tsu
GND
tsu
tr
th
th
tf
VCC
90 %
50 %
Clock Input (CLK)
50 %
10 %
10 %
GND
tPHL
tPLH
VOH
90 %
90 %
Output (Y0 to Y7)
50 %
50 %
10 %
10 %
VOL
tTHL
tTLH
•
Waveforms – 2
tf
VCC
90 %
Clear Input (CLR)
50 %
10 %
GND
tPLH
VOH
90 %
Output (Y0 to Y7)
50 %
10 %
VOL
tTLH
•
Waveforms – 3
tr
tf
VCC
90 %
50 %
90 %
50 %
High Level Pulse
10 %
90 %
10 %
GND
tw
tw
All Input
VCC
90 %
Low Level Pulse
50 %
10 %
50 %
10 %
GND
tf
tr
Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. The input and output is measured one at a time with one transition per measurement.
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 5 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Application Data
Duty Cycle − Output Current Characteristics
Duty Cycle − Output Current Characteristics
• RD15LD74AP
• RD15LD74AP
Ta=85°C
Ta=25°C
200
200
180
160
140
120
100
80
1
6
5
~
1
8
~
180
160
140
120
100
80
7
8
60
60
• Output current values represent
the current per circuit.
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
40
20
0
40
• Repeated frequency ≥ 10Hz
• The value the circle represents the value
of the simultaneously - operated circuit.
20
• The value the circle represents the value
of the simultaneously - operated circuit.
0
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
Duty Cycle − Output Current Characteristics
Duty Cycle − Output Current Characteristics
• RD15LD74ANP
• RD15LD74ANP
Ta=85°C
Ta=25°C
1
5
4
~
200
180
160
140
120
100
80
200
180
160
140
120
100
80
1
8
~
6
7
8
60
60
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
40
40
20
20
• The value the circle represents the value
of the simultaneously - operated circuit.
• The value the circle represents the value
of the simultaneously - operated circuit.
0
0
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 6 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Application Data
Duty Cycle − Output Current Characteristics
• RD15LD74AT
Ta=25°C
Duty Cycle − Output Current Characteristics
• RD15LD74AT
Ta=85°C
200
1
5
200
180
160
140
120
100
80
1
3
2
~
~
6
7
8
180
160
140
120
100
80
4
5
6
7
8
60
60
• Output current values represent
the current per circuit.
• Output current values represent
the current per circuit.
• Repeated frequency ≥ 10Hz
40
40
20
0
• Repeated frequency ≥ 10Hz
• The value the circle represents the value
of the simultaneously - operated circuit.
20
• The value the circle represents the value
of the simultaneously - operated circuit.
0
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle (%)
Switching Time − Ambient Temperature Characteristics
Switching Time − Output Current Characteristics
V
CC
=5.0V, V =12V, C =30pF, R =120Ω
L
V
=5.0V, V =12V, Ta=25°C
T
T
L
CC
50.0
40.0
30.0
20.0
10.0
0.0
1000.0
100.0
10.0
tPLH(CLR to Y)
tPLH(CLK to Y)
tPHL(CLK to Y)
tPLH(CLR to Y)
tPLH(CLK to Y)
tPHL(CLK to Y)
tTLH
tTLH
tTHL
tTHL
1.0
-40
-20
0
20
40
60
80
100
10
100
Output Current I (mA)
1000
Ambient Temperature Ta (°C)
DS
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 7 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
Package Dimensions
JEITA Package Code
P-SDIP20-6.3x19-1.78
RENESAS Code
PRDP0020BA-A
Previous Code
20P4B
MASS[Typ.]
1.0g
20
11
1
10
c
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
E
A
A1
A2
bp
b3
c
0.51
*3
b3
bp
e
3.3
SEATING PLANE
0.38 0.48 0.58
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
e
L
1.528 1.778 2.028
3.0
JEITA Package Code
P-DIP20-6.3x24.5-2.54
RENESAS Code
PRDP0020AC-B
Previous Code
DP-20NEV
MASS[Typ.]
1.26g
D
20
11
1
10
b 3
0.89
Z
Dimension in Millimeters
Min Nom Max
7.62
Reference
Symbol
e1
D
E
A
A1
bp
b3
c
24.50 25.40
6.30 7.00
5.08
bp
e
c
0.51
e1
0.40 0.48 0.56
1.30
0.19 0.25 0.31
( Ni/Pd/Au plating )
θ
0° 15°
2.29 2.54 2.79
e
Z
1.27
2.54
L
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 8 of 9
RD15LD74AP, RD15LD74ANP, RD15LD74AT
JEITA Package Code
RENESAS Code
PTSP0020JB-A
Previous Code
TTP-20DAV
MASS[Typ.]
0.07g
P-TSSOP20-4.4x6.5-0.65
*1
D
F
NOTE)
20
11
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
b p
Terminal cross section
( Ni/Pd/Au plating )
Index mark
Dimension in Millimeters
Reference
Symbol
Min Nom Max
1
10
D
E
6.50 6.80
4.40
*3
L 1
e
bp
Z
x
M
A2
A1
A
bp
b1
c
0.03 0.07 0.10
1.10
0.15 0.20 0.25
0.10 0.15 0.20
L
c1
θ
y
0° 8°
6.20 6.40 6.60
Detail F
HE
e
x
0.65
0.13
0.10
y
Z
L
L1
0.65
0.4 0.5 0.6
1.0
REJ03D0894-0300 Rev.3.00 Feb 29, 2008
Page 9 of 9
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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