RD74LVC74BTELL [RENESAS]
Dual D-type Flip Flops with Preset and Clear; 双D-型触发器与预置和清除
| 型号： | RD74LVC74BTELL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual D-type Flip Flops with Preset and Clear |
| 文件： | 总9页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RD74LVC74B
Dual D-type Flip Flops with Preset and Clear
REJ03D0324–0100Z
Rev.1.00
Jun. 22, 2004
Description
The RD74LVC74B has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The
logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage
and high-speed operation is suitable at the battery drive product (note type personal computer) and low power
consumption extends the life of a battery for long time operation.
Features
•
•
•
•
•
VCC = 1.65 V to 5.5 V
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±12 mA (@VCC = 2.7 V)
±24 mA (@VCC = 3.0 V to 5.5 V)
•
Ordering Information
Part Name
Package Type
Package Code
Package
Taping Abbreviation
(Quantity)
Abbreviation
RD74LVC74BFPEL
RD74LVC74BTELL
SOP–14 pin (JEITA)
TSSOP–14 pin
FP–14DAV
TTP–14DV
FP
T
EL (2,000 pcs / reel)
ELL (2,000 pcs / reel)
Function Table
Inputs
Outputs
PR
CLR
CK
D
Q
Q
L
H
L
X
X
X
X
H
L
H
L
H
X
L
H
L
L
X
H*1
H
H*1
L
H
H
H
H
H
H
↑
H
↑
L
H
H
L
X
X
X
Q0
Q0
Q0
Q0
Q0
Q0
H
H
↓
H
H :
L :
X :
↓ :
↑ :
Q0:
High level
Low level
Immaterial
High to Low transition
Low to high transition
Level to Q before the indicated steady input conditions were established.
Note: 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and
clear go high simultaneously.
Rev.1.00 Jun. 22, 2004 page 1 of 8
RD74LVC74B
Pin Arrangement
VCC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
10
9
1CLR
1D
D
CK
PR CLR
1CK
1PR
1Q
Q
Q
2CK
2PR
2Q
D
CK
CLR PR
1Q
Q
Q
GND
8 2Q
(Top view)
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
Unit
Conditions
VCC
IIK
–0.5 to 7.0
V
Input diode current
Input voltage
–50
mA
V
VI = –0.5 V
VI
–0.5 to 7.0
Output diode current
IOK
–50
mA
VO = –0.5 V
50
VO = VCC +0.5 V
Output voltage
VO
IO
–0.5 to VCC +0.5
±50
V
Output current
mA
mA
°C
VCC, GND current / pin
Storage temperature
ICC or IGND 100
Tstg –65 to +150
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.1.00 Jun. 22, 2004 page 2 of 8
RD74LVC74B
Recommended Operating Conditions
Item
Symbol
VCC
Ratings
1.5 to 5.5
Unit
Conditions
Data retention
Supply voltage
V
V
1.65 to 5.5
At operation
PR, CLR, CK, D
Q, Q
Input / output voltage
VI
0 to 5.5
VO
Ta
IOH
0 to VCC
Operating temperature
Output current
–40 to 85
°C
–4
–8
–12
–24
4
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
VCC = 1.65 V
IOL
mA
8
VCC = 2.3 V
12
24
20
10
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
VCC = 1.65 V to 2.7 V
VCC = 3.0 V to 5.5 V
Input rise / fall time *1
tr, tf
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.1.00 Jun. 22, 2004 page 3 of 8
RD74LVC74B
Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
VIH
VCC (V)
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 5.5
1.65
Unit
Test Conditions
Min
Max
V
CC×0.65
—
—
—
—
V
V
V
1.7
2.0
V
CC×0.7
VIL
—
VCC×0.35
—
0.7
0.8
—
—
V
CC×0.3
Output voltage
VOH
VCC –0.2
1.2
1.7
2.2
2.4
2.2
3.8
—
—
IOH = –100 µA
—
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
2.3
—
2.7
—
3.0
—
3.0
—
IOH = –24 mA
4.5
—
VOL
1.65 to 5.5
1.65
0.2
0.45
0.7
0.4
0.55
0.55
±5.0
±5.0
5.0
500
V
IOL = 100 µA
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 24 mA
—
2.3
—
2.7
—
3.0
—
4.5
—
Input current
IIN
0 to 5.5
2.7 to 3.6
2.7 to 5.5
2.7 to 3.6
—
µA
µA
VIN = 5.5 V or GND
VIN = 3.6 V to 5.5 V
VIN = VCC or GND
Quiescent supply current ICC
—
—
∆ICC
—
µA
VIN = one input at (VCC –0.6)V,
other inputs at VCC or GND
Rev.1.00 Jun. 22, 2004 page 4 of 8
RD74LVC74B
Switching Characteristics
Ta = –40 to 85°C
Min Typ Max
Item
Symbol
VCC (V)
1.8±0.15
2.5±0.2
2.7
Unit From (Input) To (Output)
MHz
Maximum clock frequency fmax
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
83
—
83
—
150
150
150
13.4
7.1
6.0
5.2
4.1
14.4
7.7
6.0
5.2
4.4
12.9
7.0
6.0
5.4
4.1
—
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
—
—
Propagation delay time
tPLH
tPHL
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
3.6
2.3
3.4
3.0
3.0
2.7
1.9
2.2
2.0
2.0
1.0
1.0
1.0
0.0
0.0
4.1
3.3
3.3
3.3
3.3
—
ns
ns
ns
ns
ns
ns
ns
ns
pF
CK
CK
Q
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
tPLH
tPHL
Q
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
tPLH
tPHL
PR or CLR Q, Q
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
Setup time
tsu
tsu
th
Data
—
—
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
—
—
—
PR or CLR
—
—
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
—
—
Hold time
—
—
—
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
—
—
Pulse width
tw
—
CK, PR, CLR
—
—
3.3±0.3
5.0±0.5
1.8±0.15
2.5±0.2
2.7
—
—
Output skew between
pins*1
tOSLH
tOSHL
—
—
—
—
—
3.3±0.3
5.0±0.5
3.3
—
1.0
1.0
—
—
Input capacitance
CIN
—
4.0
Note: 1. This parameter is characterized but not tested.
tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn
|
Rev.1.00 Jun. 22, 2004 page 5 of 8
RD74LVC74B
Operating Characteristics
Ta = 25°C
Item
Symbol
VCC = (V)
1.8
Unit
pF
Test Conditions
Min
Typ
34
Max
Power dissipation capacitance CPD
—
—
f = 10 MHz
2.5
—
—
—
34
—
—
—
3.3
36
5.0
40
Test Circuit
VCC
Input
Pulse Generator
PR
Zout = 50 Ω
Output Q
D
Q
Q
Input
CL
CL
RL
RL
Output Q
CK
CLR
Pulse Generator
Zout = 50 Ω
Notes:
1. CL includes probe and jig capacitance.
2. Test is put into the each flip flops.
Rev.1.00 Jun. 22, 2004 page 6 of 8
RD74LVC74B
Waveforms
tf
tr
VIH
90 %
Vref
90 %
Vref
Input CLR
10 % 10 %
GND
tw
tf
tr
VIH
90 %
10 %
90 %
Vref
10 %
Vref
Input PR
Input CK
tsu
GND
VIH
tr
tf
tw (H) tw (L)
Vref Vref
tw
tSU
90 % 90 %
Vref
Vref
Vref
10 %
Vref
10 %
GND
ts (H)
90 %
th (H) ts (L)
th (L)
VIH
90 %
Vref
Vref
Vref
Vref
Input D
10 %
10 %
GND
tr
tPHL
tf
tPLH
tPHL
tPLH
VOH
Vref
Vref
Vref
Vref
Output Q
Output Q
VOL
tPLH
Vref
tPHL
Vref
tPLH
tPHL
VOH
Vref
Vref
VOL
INPUTS
VIH
tr / tf
CL
RL
Vcc (V)
Vref
Vcc ≤ 2 ns
Vcc ≤ 2 ns
30 pF 1.0 kΩ
Vcc = 1.8 0.15 V
Vcc = 2.5 0.2 V
Vcc = 2.7 V
1/2 Vcc
1/2 Vcc
1.5 V
30 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
≤ 2.5 ns
Vcc = 3.3 0.3 V 2.7 V ≤ 2.5 ns 1.5 V
Vcc = 5.0 0.5 V
1/2 Vcc 50 pF
Vcc ≤ 2.5 ns
Notes: 1. Clock pulse Input waveform: PRR = 10 MHz, duty cycle 50%.
2. Data input waveform: PRR = 5 MHz, duty cycle 50%.
Rev.1.00 Jun. 22, 2004 page 7 of 8
RD74LVC74B
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-14DAV
—
JEITA
Mass (reference value)
Conforms
0.23 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
0.83 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-14DV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.1.00 Jun. 22, 2004 page 8 of 8
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