RMHE41A184AGBG [RENESAS]
1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 4;
| 型号： | RMHE41A184AGBG |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 4 动态存储器 |
| 文件： | 总52页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
RMHE41A184AGBG
RMHE41A364AGBG
R10DS0250EJ0100
Rev. 1.00
1.1G-BIT Low Latency DRAM-III
Common I/O Burst Length of 4
Jun. 19, 2015
Description
The RMHE41A184AGBG is a 67,108,864-word by 18-bit and the RMHE41A364AGBG is a 33,554,432-word by 36-bit
synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using DRAM memory cell.
The Low Latency DRAM-III chip is a 1.1Gb DRAM capable of a sustained throughput of approximately 57.6 Gbps for
burst length of 4 (approximately 51.2 Gbps for applications implementing error correction), excluding refresh overhead
and data bus turn-around
With a bus speed of 800 MHz, a burst length of 4, and a tRC of 13.75 ns, the Low Latency DRAM-III chip is capable of
achieving this rate when accesses to at least 6 banks of memory are overlapped.
These products are packaged in 180-pin FCBGA.
Specification
• Package
• Density: 1.1Gbit
180-pin FCBGA (Ball Array: 1 mm x 1 mm Pitch)
• Organization: 8M words x 18 bits x 8 banks
Package size: 18.5 mm x 14 mm
4M words x 36 bits x 8 banks
ROHS 6/6 compliance
• Operating frequency
• Power supply
800 MHz (MAX.) @ tRC=13.75 ns
• tRC
13.75 ns tRC (and 13.75 ns tRFC
- 2.5 V VEXT
- 1.5 V VDD
- 1.0 V or 1.2 V VDDQ
)
• Refresh command
• Burst length: 4
• Address bus
- Auto Refresh : 16384 cycles / 2 ms for each bank
- Overlapped Refresh with REF# pin
• Operating case temperature: 0 to 95 °C
2 cycle DDR address
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RMHE41A184AGBG, RMHE41A364AGBG
Features
Datasheet
• 2 cycle 800MHz DDR Muxed Address
• Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
• Training sequence for per-bit deskew
• Selectable Refresh Mode: Auto or Overlapped Refresh
• Programmable PVT-compensated output impedance
• Programmable PVT-compensated on-die input termination
• PLL for improved input jitter tolerance and wide output data valid window
Ordering Information
Orderable Part Name
Cycle
Clock
Random Output Supply Burst
Address Organization
Package
Time Frequency
Cycle
Voltage
Length
Type
(word x bit)
(VDDQ
V
)
ns
MHz
800
667
800
667
ns
RMHE41A184AGBG-120#AC0 1.25
RMHE41A184AGBG-150#AC0 1.50
RMHE41A364AGBG-120#AC0 1.25
RMHE41A364AGBG-150#AC0 1.50
13.75
1.0 / 1.2
4
DDR
64 M x 18
32 M x 36
180-pin
FCBGA
(18.5 x14)
Pb-Free
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Jun. 19, 2015
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RMHE41A184AGBG, RMHE41A364AGBG
Pin Configurations
Datasheet
180-pin FCBGA (18.5 x 14) (Top View)
[RMHE41A184AGBG] ( x18 )
1
2
3
4
5
6
7
8
9
10
11
12
13
TMS
VDD
TCK
VDDQ
VSS
VSS
VDDQ
VEXT
VDD
QK0
A
B
C
D
E
F
DNU,
VSS
DNU,
VSS
VSS
QVLD
VSS
VSS
DQ6
VDDQ
DQ2
VDDQ
VDD
DQ4
VSS
x18
VDD
VSS
DQ7
VSS
DQ8
VDDQ
DQ5
VDDQ
VSS
QK0#
VSS
DNU,
VSS
DNU,
VSS
VDDQ
Burst of 4
259 sq. mm
VDDQ
DNU,
VSS
DNU,
VSS
VSS
VSS
DNU,
VSS
DNU,
VSS
DNU,
VSS
VDDQ
DINV0
VDDQ
DQ0
VSS
VDDQ
DQ1
VSS
DQ3
VSS
DNU,
VDDQ
DNU,
VDDQ
DNU,
VSS
VSS
VDD
VSS
VSS
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
VDDQ
A6
VDDQ
A5
VDDQ
DM
VDD
G
H
J
Top
View
Note
VSS
RST#
VDDQ
VSS
DK0
DK0#
VSS
VSS
VSS
CK
VSS
VSS
DNU,
VSS
MF
VSS
VDD
VDD
VSS
VSS
VDDQ
VSS
LBK#
VREF
VSS
DNU,
VSS
VREF
TRST#
VDD
VSS
VDDQ
A4
CK#
VSS
VDDQ
A3
K
L
CS#
VSS
WE#
VDDQ
DNU,
VDDQ
DNU,
VDDQ
VDDQ
VDDQ
A0
A2
REF#
VSS
VDDQ
A1
VDD
M
N
P
R
T
DNU,
VSS
VSS
DINV1
VDDQ
VSS
VSS
VSS
DQ10
VSS
VSS
DNU,
VSS
DNU,
VSS
DNU,
VSS
VDDQ
DQ11
VDDQ
DQ15
VDDQ
DQ9
VSS
VDDQ
VDDQ
DQ14
VDDQ
DQ17
VDD
DQ12
VSS
DNU,
VSS
DNU,
VSS
VSS
QK1#
VSS
VSS
VSS
DNU,
VSS
DNU,
VSS
VDDQ
DQ13
VDD
VSS
VDDQ
DQ16
VSS
TDO
VSS
DNU,
VSS
DNU,
VSS
VSS
ZQ
VDD
VSS
U
V
QK1
VDD
VDDQ
VEXT
TDI
Note When VDDQ is set to a nominal 1.0 V supply, H5 pin must be connected to VSS
.
When VDDQ is set to a nominal 1.2 V supply, H5 pin must be connected to VDDQ
.
DQ0–DQ17
: Data inputs / output
REF#
LBK#
MF
: Refresh enable
DINV0–DINV1 : Data inversion
: Loopback mode
: Mirror function
DM
: Write data mask
: Address
A0–A6
TMS
: IEEE 1149.1 test input
CK, CK#
DK0, DK0#
QVLD
: Input clock
TDI
: IEEE 1149.1 test input
: Input data clock
: Read data valid
: Output data clock
TCK
: IEEE 1149.1 clock input
: IEEE 1149.1 test output
: IEEE 1149.1 test reset input
: HSTL input reference input
: Power supply, 1.5 V nominal
TDO
QK0–QK1,
QK0#–QK1#
ZQ
TRST#
VREF
: Output impedance & input
termination control
: Master reset
VDD
VDDQ
: DQ power supply, 1.0 V or 1.2 V nominal
: Power supply, 2.5 V nominal
RST#
CS#
VEXT
: Chip select
VSS
: Ground
WE#
: Write enable
DNU, VSS
DNU, VDDQ
: Must not be used, or must be connected to VSS
: Must not be used, or must be connected to VDDQ
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RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
180-pin FCBGA (18.5 x 14) (Top View)
[RMHE41A364AGBG] ( x36 )
1
2
3
4
5
6
7
8
9
10
11
12
13
TMS
VDD
TCK
VDDQ
VSS
VSS
VDDQ
VEXT
VDD
QK0
A
B
C
D
E
F
VSS
QVLD
VSS
DQ9
VDDQ
DQ12
VDDQ
DINV0
VDDQ
RST#
VDDQ
VSS
VSS
DQ10
VSS
DQ6
VDDQ
DQ2
VDDQ
VDD
DQ4
VSS
VDD
DQ13
VSS
DQ11
VDDQ
VSS
DQ7
VSS
DQ8
VDDQ
DQ5
VDDQ
DINV1
VDDQ
DM
VSS
QK0#
VSS
x36
Burst of 4
259 sq. mm
DQ15
VDDQ
DQ16
VSS
DQ14
VSS
DQ0
VSS
DQ17
VSS
DQ1
VSS
DQ3
VSS
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
DNU,
VDDQ
VDD
VDDQ
A6
VDDQ
A5
VDD
G
H
J
Top
View
Note
VSS
VSS
DK0
DK0#
VSS
VSS
VSS
CK
VSS
DK1
DK1#
VSS
VSS
MF
VSS
VDD
VDD
VSS
VDDQ
VSS
LBK#
VREF
VSS
VREF
VDDQ
A4
CK#
VSS
VDDQ
A3
K
L
TRST# CS#
VSS
WE#
VDDQ
DINV3
VDDQ
DQ23
VDDQ
DQ26
VDD
DNU,
VDDQ
DNU,
VDDQ
VDD
VSS
VDDQ
DINV2
VDDQ
VDDQ
A0
A2
REF#
VSS
VDDQ
A1
VDD
M
N
P
R
T
VSS
DQ34
VSS
VSS
VSS
DQ19
VSS
VSS
DQ35
VSS
VDDQ
DQ20
VDDQ
DQ24
VDDQ
DQ18
VSS
DQ33
VSS
VDDQ
DQ31
VDDQ
DQ27
VDDQ
DQ21
VSS
DQ32
VDDQ
QK1#
VSS
DQ30
VSS
DQ22
VDD
DQ29
VDD
DQ25
VSS
TDO
VSS
DQ28
VDD
U
V
QK1
ZQ
VSS
VSS
VEXT
TDI
Note When VDDQ is set to a nominal 1.0 V supply, H5 pin must be connected to VSS
.
When VDDQ is set to a nominal 1.2 V supply, H5 pin must be connected to VDDQ
.
DQ0–DQ35
: Data inputs / output
REF#
LBK#
MF
: Refresh enable
DINV0–DINV3 : Data inversion
: Loopback mode
: Mirror function
DM
: Write data mask
: Address
A0–A6
TMS
: IEEE 1149.1 test input
CK, CK#
DK0–DK1,
DK0#–DK1#
QVLD
: Input clock
TDI
: IEEE 1149.1 test input
: Input data clock
TCK
: IEEE 1149.1 clock input
: IEEE 1149.1 test output
: IEEE 1149.1 test reset input
: HSTL input reference input
: Power supply, 1.5 V nominal
TDO
: Read data Valid
: Output data clock
TRST#
VREF
VDD
QK0–QK1,
QK0#–QK1#
ZQ
: Output impedance & Input
termination control
: Master reset
VDDQ
: DQ power supply, 1.0 V or 1.2 V nominal
: Power supply, 2.5 V nominal
VEXT
RST#
CS#
VSS
: Ground
: Chip select
DNU, VSS
DNU, VDDQ
: Must not be used, or must be connected to VSS
: Must not be used, or must be connected to VDDQ
WE#
: Write enable
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RMHE41A184AGBG, RMHE41A364AGBG
Pin Identification
Datasheet
(1/2)
Freq
Symbol
CK, CK#
Direction
I/O Type
Description
[MHz]
Input
1.0 / 1.2 V 800 / 667
HSIO
Clock inputs:
CK and CK# are differential clock inputs. This input clock pair registers
address and control inputs on the rising edge of CK. CK# is ideally 180
degrees out of phase with CK.
DK0-DK1,
Input
Input
1.0 / 1.2 V 800 / 667
HSIO
Differential clocks for DQ inputs:
DK0#-DK1#
DK0, DK0# => DQ0-DQ17, DM
DK1, DK1# => DQ18-DQ35
Note that DK1,DK1# are only active on x36 parts.
Chip select:
CS#
1.0 / 1.2 V 800 / 667
HSIO
CS# enables the commands when CS# is LOW and disables them
when CS# is HIGH. When the command is disabled, new commands
are ignored, but internal operations continue.
Write enable, Refresh enable:
WE#, REF#
RST#
Input
Input
Input
Input
Input
1.0 / 1.2 V 800 / 667
HSIO
WE#, REF# are sampled at the positive edge of CK, WE#, and REF#
define (together with CS#) the command to be executed.
Master reset:
1.0 / 1.2 V
HSIO
-
-
Note that this pin has no on-die termination.
(no ODT)
1.0 / 1.2 V
HSIO
LBK#
Loopback mode for control pin de-skew training
Note that this pin has no on-die termination.
(no ODT)
MF
1.0 / 1.2 V DC
HSIO
Causes “mirroring” of certain pins as described in
2.14 Clam-shell support.
(no ODT)
Note that this pin has no on-die termination.
Address inputs for DDR Address:
A0-A6
1.0 / 1.2 V 800 / 667
HSIO
Address bus, including bank select bits.
A６ is reserved for future use.
DQ0-DQ35
Input
1.0 / 1.2 V 800 / 667
HSIO
Data input/output:
/Output
The DQ signals form the 36 bit data bus. During READ commands, the
data is referenced to both edges of QKx. During WRITE commands,
the data is sampled at both edges of DKx.
Note that DQ18-DQ35 are only active on x36 parts.
Data inversion state for DQ inputs:
DINV0-DINV3
Input
1.0 / 1.2 V 800 / 667
HSIO
/Output
DINV0 => DQ0-DQ8
DINV1 => DQ9-DQ17
DINV2 => DQ18-DQ26
DINV3 => DQ27-DQ35
Note that DINV2-DINV3 are only active on x36 parts
Write data mask: disables writing of the corresponding data value.
Clocked by DK0.
DM
Input
1.0 / 1.2 V 800 / 667
HSIO
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RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
(2/2)
Freq
Symbol
Direction
I/O Type
Description
[MHz]
QK0-QK1,
Output
1.0 / 1.2 V
HSIO
800 / 667
Output data clocks:
QK0#-QK1#
Differential clocks for DQ, QVLD outputs:
QK0/QK0# => x36: DQ0-DQ17, x18: DQ0-DQ8, QVLD
QK1/QK1# => x36: DQ18-DQ35, x18: DQ9-DQ17
Data valid:
QVLD
TMS, TDI
TCK
Output
Input
1.0 / 1.2 V
HSIO
800 / 667
The QVLD indicates valid output data. QVLD is edge-aligned with QKx and
QKx#.
1.0 / 1.2 V
HSIO
JTAG function pins:
IEEE 1149.1 test inputs: These balls may be left as no connects if the
JTAG function is not used in the circuit
JTAG function pin:
Input
1.0 / 1.2 V
HSIO
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function
is not used in the circuit.
TDO
Output
Input
1.0 / 1.2 V
HSIO
JTAG function pin:
IEEE 1149.1 test output: JTAG output.
This ball may be left as no connect if JTAG function is not used.
JTAG reset:
TRST#
1.0 / 1.2 V
HSIO
IEEE 1149.1 test rest: This ball must be tied to VSS if the JTAG function is
not used in the circuit.
ZQ
Analog
Ref
Output impedance and input termination control
VREF
VEXT
VDDQ*0.7 V I/O reference voltage.
Supply
Power supply: 2.5 V nominal. See Recommended DC Operating
Conditions for range.
VDD
Supply
Supply
Power supply: 1.5 V nominal. See Recommended DC Operating
Conditions for range.
VDDQ
DQ power supply:
Nominally, 1.0 V or 1.2 V. Isolated on the device for improved noise
immunity.
See Recommended DC Operating Conditions for range.
VSS
Supply
Ground
DNU, VSS
DNU, VDDQ
Do Not Use, Or must not be used, or must be connected to VSS
.
Do Not Use, Or must not be used, or must be connected to VDDQ
HSIO is a single-ended 1.0 V or 1.2 V high-side terminated I/O described in 1. Electrical Specifications.
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RMHE41A184AGBG, RMHE41A364AGBG
Block Diagram
Datasheet
A0-A5
De-muitiplexer
Column Address
Row Address
Buffer
Refresh
Counter
Buffer
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Memory Array
Bank 0
Memory Array
Bank 1
Memory Array
Bank 2
Memory Array
Bank 3
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Memory Array
Bank 4
Memory Array
Bank 5
Memory Array
Bank 6
Memory Array
Bank 7
Output Data Valid
Output Data Clock
Input Buffers
Output Buffers
Control Logic and Timing Generator
QVLD
DQxx
QK0-QK1, QK0#-QK1#
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RMHE41A184AGBG, RMHE41A364AGBG
Contents
Datasheet
1. Electrical Specifications ...........................................................................................................................9
2. Operation..................................................................................................................................................17
2.1 Interface Overview............................................................................................................................................. 17
2.2 Clocking ............................................................................................................................................................. 17
2.3 Address bus....................................................................................................................................................... 18
2.4 Command encoding.......................................................................................................................................... 19
2.5 Data mask........................................................................................................................................................... 21
2.6 Data inversion.................................................................................................................................................... 21
2.7 Data bus turn-around........................................................................................................................................ 21
2.8 Command cycles............................................................................................................................................... 21
2.9 Write data cycles ............................................................................................................................................... 22
2.10 Read data cycles ............................................................................................................................................. 22
2.11 READ and WRITE command protocol ........................................................................................................... 22
2.12 Automatic Refresh........................................................................................................................................... 25
2.13 Overlapped refresh commands...................................................................................................................... 25
2.14 Clam-shell support.......................................................................................................................................... 27
3. Initialization ..............................................................................................................................................28
3.1 Power-on ............................................................................................................................................................ 29
3.2 Reset................................................................................................................................................................... 30
3.3 Initial impedance settings................................................................................................................................. 31
3.4 Per-bit de-skew training sequence................................................................................................................... 32
3.5 Configuration..................................................................................................................................................... 34
4. JTAG Specification..................................................................................................................................39
4.1 Test Pins............................................................................................................................................................. 39
4.2 JTAG AC Test Conditions................................................................................................................................. 40
4.3 Boundary Scan .................................................................................................................................................. 43
4.4 JTAG Instructions.............................................................................................................................................. 48
4.5 TAP Controller State Diagram .......................................................................................................................... 49
5. Package Drawing .....................................................................................................................................50
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RMHE41A184AGBG, RMHE41A364AGBG
1. Electrical Specifications
Datasheet
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VEXT
Conditions
2.5 V nominal
Rating
Unit
V
–0.3 to +2.8
–0.3 to +1.95
–0.3 to +1.56
Supply voltage
VDD
1.5 V nominal
V
Output supply voltage,
Input voltage, Input / Output voltage
Input / Output voltage
Junction temperature
Storage temperature
VDDQ
1.0 / 1.2 V nominal
V
VIH / VIL 1.0 / 1.2 V nominal
–0.3 to +1.56
105
V
TJ MAX.
TSTG
°C
°C
–55 to +125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Recommended DC Operating Conditions
0°C ≤ TC ≤ 95°C
Parameter
Supply voltage
Symbol
VEXT
MIN.
2.3
TYP.
2.5
MAX.
2.7
Unit
V
Comments
Note
1
1
Supply voltage
VDD
1.395
1.5
1.605
V
Output supply voltage
(1.0 V nominal)
VDDQ
0.95
1.14
1.0
1.05
V
V
1
1
Output supply voltage
(1.2 V nominal)
VDDQ
1.2
1.26
Reference voltage
VREF
VDDQ*0.69
VDDQ*0.7
VDDQ*0.71
V
V
V
1,2,4
High level output voltage
Low level output voltage
VOH (DC)
VOL (DC)
VDDQ–0.025
1
1
VDDQ*0.4
ZOL=40 Ω,
RL=60 Ω
High level input voltage
Low level input voltage
Clock input voltage
VIH (DC)
VIL (DC)
VIN
VREF+0.07
–0.3
VDDQ+0.3
VREF–0.07
VDDQ+0.3
VDDQ+0.6
V
V
V
V
Ω
Ω
Ω
1,4
1,4
–0.3
Clock differential voltage
Output Impedance HIGH
Output Impedance LOW
Input Impedance LOW
VID
0.2
ZOH
ZOL
60
40
60
3
3
4
ZI
Notes 1. All voltage referenced to VSS (GND)
2. Peak - to - Peak AC noise on VREF must not exceed +/- 2 % VDDQ (DC)
3. Programmable via ZQ and Reset Impedance Control
4. High-side termination (programmable via ZQ and Reset/MRS)
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Page 9 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
DC Characteristics
0°C ≤ TC ≤ 95°C; 1.395 V ≤ VDD ≤ 1.605 V, unless otherwise noted
Parameter
Input leakage current
Symbol
Test condition
MIN.
MAX.
50
Unit Note
ILI
0
0
0
µA
µA
µA
1
1
1
Output leakage current
3 state leakage current
ILO
IOZ
50
50
Note 1. Outputs Driver High-Z and ODT Disabled.
Capacitance (TA
=
25 °C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
MAX.
Unit
Input capacitance
CIN
VIN = 0 V
1.5
pF
(CK,DK, CS#, WE#, REF#, A)
I/O, Output, Other capacitance
(DQ, DINV, QVLD, DM)
CI/O
CDCK
CDDQ
CDCTL
VI/O = 0 V
VIN = 0 V
VI/O = 0 V
VIN = 0 V
1.8
0.15
0.2
pF
pF
pF
pF
Input capacitance delta between
differential clock pins
Input capacitance delta between DQ pins
Input capacitance delta between CS#,
WE#, REF#, A pins
0.2
Remark These parameters are periodically sampled and not 100% tested.
Capacitance is not tested on ZQ pin.
Recommended AC Operating Conditions
0°C ≤ TC ≤ 95°C; 1.395 V ≤ VDD ≤ 1.605 V, unless otherwise noted
Parameter
Symbol
VIH (AC)
Conditions
MIN.
VREF+0.13
–0.3
MAX.
Unit
V
Note
Input HIGH voltage
Input LOW voltage
VDDQ+0.3
VREF–0.13
1
1
VIL (AC)
V
Note 1. Overshoot: VIH (AC) ≤ VDDQ+0.3 V for t ≤ tCK/5
Undershoot: VIL (AC) ≥ –0.3 V for t ≤ tCK/5
Control input signals may not have pulse widths less than tCKH (MIN.) or operate at cycle rates less than tCK
(MIN.).
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RMHE41A184AGBG, RMHE41A364AGBG
Power Consumption
Datasheet
Parameter
Symbol
Test condition
Nominal supply voltage
Max
Unit
Note
Sequential bank access
Overlapped refresh mode
Data inversion enabled
x18
x36
Total power
consumption
PD
2.0
W
1
Half address and data transitions
30% Write and 70% Read operation
ODT=60Ω, ZOH/ZOL = 60Ω/40Ω
TC=95°C
Note 1. Including all the power supply (VDD=1.5 V, VDDQ=1.0 V and VEXT=2.5 V)
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RMHE41A184AGBG, RMHE41A364AGBG
AC Characteristics
Datasheet
Normal bus timing
Standard bus timing waveforms and values for command and data are shown in Figure 1-1 through Figure 1-5 and
Interface AC Parameters. All timing is measured to/from the crossing point on differential clocks and to/from the VREF
crossing point on single-ended signals.
Figure 1-1 Command and DDR Address Input Timing Waveforms
tCK
tCKH
tCKL
CK#
CK
tAS
tAH
tAS
tAH
A
tASH
tASH
tCS
tCH
CS#,
WE#,
REF#
tCSH
Figure 1-2 Data Input Timing Waveforms
CK#
CK
tCKDK
tCK
tCKH
tCKL
DK#
DK
tIS
tIH
tIS
tIH
DQ,
DINV,
DM
tISH
tIPW
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RMHE41A184AGBG, RMHE41A364AGBG
Figure 1-3 Data Output Timing Waveforms
Datasheet
CK#
CK
tCKQK
tCK
tQKH
tQKL
QK#
QK
t
t
t
QKQ0
QKQ1
QKQ
,
,
t
t
t
QKQ0
QKQ1
QKQ
,
,
DQ,
DINV
t
t
t
QH0
QH1
QH
,
,
t
t
t
QH0
QH1
QH
,
,
tQKQV
QVLD
tQVH
Figure 1-4 Output Driver Enable/Disable Timing
QK#
QK
tQON
tQOFF
DQ,
DINV
Figure 1-5 Reset Timing Waveforms
CK
tRSS
tRSH
RST #
tRDS
tRDH
DQ
CS#,
LBK#
Note The clock must be within specification and all other chip inputs must be driven to legal values
throughout the tRSS period.
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RMHE41A184AGBG, RMHE41A364AGBG
Interface AC Parameters
Datasheet
(1/2)
–120
–150
Parameter
Symbol
Unit
Note
( 800 MHz )
( 667 MHz )
MIN.
MAX.
MIN.
MAX.
CK, DK, QK clock period (maximum 800 MHz
clock frequency, minimum 400 MHz)
CK, DK LOW time (assumes 5% duty cycle
distortion at 800 MHz)
tCK
tCKL
tCKH
1.250
2.500
1.500
2.500
ns
0.45*
0.45*
tCK(avg)
tCK(avg)
5
5
CK, DK HIGH time (assumed 5% duty cycle
distortion at 800 MHz)
0.45*
0.45*
Clock period jitter
tJIT(per)
tJIT(cc)
–0.070
0.070
0.140
–0.070
0.070
0.140
ns
ns
ns
6,7
8
Cycle-to-cycle clock jitter
Cumulative jitter error
tERR(nper)
tERR(nper),min = [1+0.08LN(n)] * tJIT(per),min
tERR(nper),max = [1+0.08LN(n)] * tJIT(per),max
A to CK setup
tAS
tAH
0.160
0.192
0.192
0.192
0.240
0.215
0.215
0.358
ns
ns
ns
ns
ns
2
1
4
CK to A hold
0.160
0.160
0.200
0.180
0.180
0.300
CK to A setup/hold window
A input pulse width
tASH
tAPW
tCS
CS#, WE#, REF# to CK setup
CK to CS#, WE#, REF # hold
CK to CS#, WE#, REF# setup/hold
window
2
1
4
tCH
tCSH
ns
CS#, WE#, REF# input pulse width
CK to DK skew
tCPW
tCKDK
tIS
0.400
–0.200
0.160
0.160
0.160
0.200
2
0.480
–0.240
0.192
0.192
0.192
0.240
2
ns
ns
0.200
0.240
DQ, DINV, DM to DK setup
DK to DQ, DINV, DM hold
DK to DQ, DINV, DM setup/hold window
DQ, DINV, DM input pulse width
Output signal rise time [See Note]
Output signal fall time [See Note]
QK LOW time
ns
2
1
4
tIH
ns
tISH
ns
tIPW
tRISE
tFALL
tQKL
ns
5
5
5
5
V/ns
V/ns
tCK(avg)
3
3
5
2
2
0.45*
0.45*
(assumed 5% duty cycle distortion at 800 MHz)
QK HIGH time
tQKH
0.45*
0.45*
tCK(avg)
5
(assumed 5% duty cycle distortion at 800 MHz)
CK to QK skew
tCKQK
tCD
–0.300
0.300
5
–0.358
0.358
5
ns
ns
ns
Additional tRL delay in loopback
QK0 to DQ[17:0], DINV[1:0] (x36) or DQ[8:0],
DINV[0] (x18)
tQKQ0
0.100
0.120
9
5
9
5
QK0 to DQ[17:0], DINV[1:0] (x36) or DQ[8:0],
DINV[0] (x18)
tQH0
tQKQ1
tQH1
0.4*
0.4*
0.4*
0.4*
tCK(avg)
ns
QK1 to DQ[35:18], DINV[3:2] (x36) or
DQ[17:9],DINV[1] (x18)
0.100
0.120
QK1 to DQ[35:18], DINV[3:2] (x36) or
DQ[17:9],DINV[1] (x18)
tCK(avg)
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RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
(2/2)
–120
–150
Parameter
Symbol
Unit
Note
( 800 MHz )
( 667 MHz )
MIN.
0.35*
0.85*
MAX.
MIN.
0.35*
0.85*
MAX.
Any QK to any DQ, DINV
Any QK to any DQ, DINV
Any QK to QVLD
tQKQ
tQH
0. 150
0. 150
0.100
0.100
0.180
0.180
0.120
0.120
ns
tCK(avg)
ns
9
5
tQKQV
tQVH
tQON
Any QK to QVLD
tCK(avg)
ns
5
5
QK to DQ output driver turn-on time
and ODT turn-on time
QK to DQ output driver turn-off time
and ODT turn-on time
tQOFF
–0.1*
tCK(avg)
1000 *
5 *
–0.1*
tCK(avg)
1000 *
5 *
ns
DQ to RST# setup
tRDS
tRDH
tRSS
tRSH
tPLL
tCK
tCK
2
1
DQ to RST# hold
RST# pulse length
200
200
µs
RST# deasserted to CS# or LBK# asserted
Time for PLL to stabilize after being
enabled
400000 *
400000 *
tCK
20
20
µs
MRS command start to next CS#, or LBK#
assertion; also from previous command
to MRS command
tMRD
24 *
24 *
tCK
Notes 1. All input hold timing assumes rising edge slew rate of 2 V/ns measured from VIL/VIH (DC) to VREF
.
2. All input setup timing assumes falling edge slew rate of 2 V/ns measured from VREF to VIL/VIH (AC)
3. All output timing assumes the load shown in Figure 1-6.
4. Setup/hold windows, tASH, tCSH, tISH are used for de-skew timing budgeting and are based on electrical
simulations. These cannot be directly measured without performing de-skew training.
5. tCK (avg) is the value of tCK averaged over 200 clock cycles.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. Frequency drift is not allowed.
8. The cumulative jitter error, tERR(nper), where n is the number of clocks between 2 and 50, is the amount of clock
time allowed to accumulate consecutively away from the average clock over n number of clock cycles.
9. tQKQ, tQKQ0 and tQKQ1 are guaranteed by design.
Figure 1-6 Output Load
VDDQ
60Ω
50Ω
Output
2 pF
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RMHE41A184AGBG, RMHE41A364AGBG
Temperature and Thermal Impedance
Datasheet
Temperature Limits
Parameter
Symbol
MIN.
MAX.
+105
+100
+95
Unit
°C
Note
Reliability junction temperature
Operating junction temperature
Operating case temperature
TJ
TJ
TC
0
0
0
1
2
3
°C
°C
Notes 1. Temperatures greater than 105°C may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at or above this is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability of the part.
2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow.
3. MAX operating case temperature; TC is measured in the center of the package. Device functionality is not
guaranteed if the device exceeds maximum TC during operation.
Thermal Impedance
Substrate
θja (°C/W)
θjb
(°C/W)
5.7
θjc
(°C/W)
2.1
Air Flow = 0 m/s Air Flow = 1 m/s Air Flow = 2 m/s
4 - Layers
14.9
11.7
10.7
Impedance Controls
The Low Latency DRAM-III includes programmable impedance control that affects the output impedance of all output and
bidirectional pins, as well as the termination of all input and bidirectional pins. The output impedance control affects all
output pins and the input termination control affects those pins grouped together as shown in Table 3-5 and Table 3-6.
The impedance control affects the drive strengths of both high and low values, as well as the high-side termination
impedance. The impedance is controlled via a precision resistor connected between the ZQ and VSS pins. The nominal
value of the precision (1%) resistor is 240 Ω, with a supported range of 200 to 240 Ω.
The output impedance accuracy is within 15% of the programmed nominal value, with the linearity measured at the
points described in Impedance Test Parameters. The actual impedance must remain within the range specified by the
linear interpolation of the values at those points.
Normally, the input termination and output impedance are continuously adjusted, such that only minor instantaneous
variations in the impedance occur. However, when the FZ bit in the configuration register is set, then the input termination
and output impedance will be “frozen” at their current values. If the IM bit in the configuration register is set, then the output
impedance will have a nominal value that is not dependent on the value of the resistor connected to the ZQ pin. In this
mode, the ZQ pin is ignored by the Low Latency DRAM-III, and the output impedances will not be PVT compensated.
Impedance Test Parameters
Parameter
Symbol
MIN.
NORM.
MAX.
Unit
Output HIGH voltage with forced IOH = -(VDDQ -0.85 VDDQ) /
ZOH
VOH
0.723*
0.85*
0.978*
VDDQ
Output HIGH voltage with forced IOH = -(VDDQ -0.7 VDDQ) /
ZOH
VOH
0.595*
0.7*
0.805*
VDDQ
Output LOW voltage with forced IOL = 0.7 VDDQ / ZOL
Output LOW voltage with forced IOL = 0.55 VDDQ / ZOL
VOL
VOL
0.595*
0.468*
0.7*
0.805*
0.633*
VDDQ
VDDQ
0.55*
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RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
2.Operation
2.1 Interface Overview
The primary Low Latency DRAM-III interface consists of a unidirectional command and address bus and a bidirectional
data bus. This type of data bus is often referred to as common I/O or CIO. Pin Identification contains the list of pins on
the Low Latency DRAM-III.
The command bus is a single data rate (SDR) bus consisting of CS#, WE#, and REF#. The RMHE41A184AGBG,
RMHE41A364AGBG have a double data rate (DDR) address bus consisting of multiplexed A0-A6 in burst length 4 mode.
Both the command bus and address bus are clocked by the differential clock pair CK and CK#. READ and WRITE
commands can be issued at a rate of one every 2 cycles of CK in burst length 4 mode.
The data interface is a double-rate (DDR) interface that transfers 36 bits of data Note on each clock edge for 36-bit parts
and 18 bits of data on each clock edge for 18-bit parts. The data interface also includes 4 data inversion pins. In addition
to 36 data bits, the inputs to the Low Latency DRAM-III include a DDR data mask, DM, and two differential clock pairs,
DK0-DK1 and DK0#-DK1#. The Low Latency DRAM-III outputs two differential clock pairs, QK0-QK1 and QK0#-QK1#
that are associated with read data, and a data valid signal, QVLD. Because the data bus is bidirectional, idle cycles are
required to implement data bus turn-around as described in 2.7 Data bus turn-around.
Note For parts with 18-bit data bus, all references in this section should refer to DQ0-DQ17 and DINV0- DINV1 unless
otherwise noted. DQ0-DQn is used to represent DQ0-DQ35 or DQ0-DQ17 for 36-bit and 18-bit parts, respectively,
and DINV0-DINVm is used to represent either DINV0-DINV3 or DINV0-DINV1 for 36-bit and 18-bit parts.
2.2 Clocking
There are three groups of clock signals: CK/CK#, DK0-DK1/DK0#-DK1#, and QK0-QK1/QK0#-QK1#.
The CK/CK# clock is associated with the address and command pins: A0-A6, CS#, WE#, and REF#. At the Low Latency
DRAM-III pins, the CK/CK# transitions are nominally centered with respect to address and command signal transitions.
The DK0-DK1/DK0#-DK1# clocks are associated with write data. DK0/DK0# is used as a source-centered clock for the
double data rate DQ0-DQ17, DINV0-DINV1, and DM pins. DK1/DK1# is used as a source-centered clock for the double
data rate DQ18-DQ35 and DINV2-DINV3 pins.
The DK0-DK1/DK0#-DK1# clocks must meet the specified tCKDK skew with respect to the CK/CK# clock in order to ensure
proper timing relationship between command and data cycles and to enable proper data bus turn-around.
The QK0-QK1/QK0#-QK1# clocks are associated with read data. At the Low Latency DRAM-III pins, and for x36 devices,
QK0/QK0# must be source-synchronous with the read data DQ0-DQ17, DINV0-DINV1, and QVLD pins. Similarly, for x36
devices, QK1/QK1# is used as a source-synchronous clock for the read data DQ18-DQ35 and DINV2-DINV3 pins.
For x18 devices, QK0/QK0# must be source-synchronous with DQ0-DQ8, DINV0, and QVLD. Similarly, for x18 devices,
QK1/QK1# must be source-synchronous with DQ9-DQ17 and DINV1.
The QK0-QK1/QK0#-QK1# clocks must meet the specified tCKQK skew with respect to the CK/CK# clock in order to ensure
proper timing relationship between command and data cycles and to enable proper data bus turn-around.
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RMHE41A184AGBG, RMHE41A364AGBG
2.3 Address bus
Datasheet
In Burst of 4 mode two clock cycles are required to load the multiplexed address. In DDR Address mode address inputs
are captured by the RAM in two beats per cycle. Three of the bits in the address field select which of the 8 banks in the
RAM will be accessed. Note that a 4th bank address bit has been identified anticipating that a 16 bank version of the RAM
might someday reach the market. The bit functions as an ordinary address bit in the devices described in this data sheet.
Table 2-1 Address Bit Encoding
Device
Command
Beat
A6 Note1
A5
A4
A3
A2
A1
A0
Width
READ or WRITE
x36
0
1
2
3
0
1
2
3
0
X
X
X
X
X
X
X
X
X
Address
Address Note2
Address
Bank
Address
X Note1
Address
Address
READ or WRITE
AUTO REFRESH
x18
Address Note2
Address
Address
Address
X
Bank
Bank
ANY
X
X
Notes 1. A6 is reserved for future expansion. For smaller capacity devices, the value is a don’t care, but for devices
of the designated capacity or larger, the value will be used.
2. Address bit A3 in beat zero is used as an address bit in the current devices, but may be used as a bank
address bit in future generations of the part.
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RMHE41A184AGBG, RMHE41A364AGBG
2.4 Command encoding
Datasheet
The Low Latency DRAM-III supports five types of command cycles as shown in Table 2-3.
The NOP command must be used on any cycle where no other commands are requested.
The READ command is used to initiate a burst read from the Low Latency DRAM-III.
The WRITE command is used to initiate a burst write from the Low Latency DRAM-III.
The AUTO REFRESH command is used to initiate a refresh operation on a particular bank of the memory.
The OVERLAPPED REFRESH command is used to initiate a refresh operation, but may be overlapped with other
commands.
The MRS command is used to configure the Low Latency DRAM-III following a reset.
Because the overlapped refresh feature can be enabled or disabled, the command decoding and it’s associated state
diagram have two different forms. Table 2-2 and Figure 2-1 show the command encoding for the case when the
overlapped refresh feature is disabled. Figure 2-1 only shows the state diagram for the command decoder; there may be
many other states internal to the device.
Because READ and WRITE commands require two cycles to fully transfer their associated address in burst length 4 mode
and because the OVERLAPPED REFRESH command may be specified simultaneously with other commands, the
command decoder and its state diagram are more complex when the overlapped refresh feature is enabled. The states
associated with the command decoder and how command cycles are interpreted is described in Table 2-3 and Figure 2-2
(again, the state diagram only shows the states for the command decoder, not other internal states of the device).
Table 2-2 Command Encoding (Overlapped Refresh Disabled)
Length
State
IDLE
Command
CS#
WE#
REF#
LBK#
RST#
Description
(cycles)
NOP
1
0
0
0
0
1
1
-
-
1
0
1
0
-
-
1
1
0
0
-
1
1
1
1
1
1
1
0
-
1
1
1
1
1
1
1
1
0
1
2
2
1
2
-
No operation
READ
Read
WRITE
Write
AUTO REFRESH
MRS
Auto refresh
Mode register set
No operation
No operation
Address/control loopback
Reset
RD, WR
MRS
NOP
NOP
-
-
-
LOOPBACK
RESET
-
-
-
-
-
-
-
Figure 2-1 Command Decode State Diagram (Overlapped Refresh Disabled)
RD
NOP
READ
NOP
REF
IDLE
WRITE
MRS
NOP
WR
NOP
MRS
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RMHE41A184AGBG, RMHE41A364AGBG
Table 2-3 Command Encoding (Overlapped Refresh Enabled)
Datasheet
Length
(cycles)
State
IDLE
Command
NOP
CS#
WE#
REF#
LBK#
RST#
Description
No operation
1
0
0
0
-
-
1
1
1
1
1
1
1
1
1
2
2
4
READ
1
0
1
1
1
0
Read
Write
WRITE
OVERLAPPED
REFRESH
MRS
Overlapped refresh
0
1
0
0
-
0
-
1
1
1
1
1
1
2
-
Mode register set
No operation
RD,
WR
NOP
OVERLAPPED
REFRESH
NOP
READ Note
WRITE Note
NOP
1
0
4
Overlapped refresh
Note
OR1,
1
0
0
1
-
1
0
-
-
1
1
1
1
1
1
1
1
-
2
2
-
No operation
Note
OR2,
-
Read (overlapped)
Write (overlapped)
No operation
Note
OR3
-
Note
OR2RD,
OR3RD,
OR2WR,
OR3WR
MRS
-
NOP
1
-
-
-
-
-
-
-
1
0
-
1
1
0
-
-
-
No operation
LOOPBACK
RESET
Address/control loopback
Reset
-
Note These indicate that the value of the REF# pin is ignored for the purpose of command decoding (the pin is used
for conveying bank number during this cycle).
Figure 2-2 Command Decode State Diagram (Overlapped Refresh Enabled)
IDLE
NOP*
OR2RD*
OR3RD*
RD
NOP
NOP*
REF
READ *
NOP*
NOP
READ *
NOP*
READ
READ *
REF
NOP*
IDLE
IDLE
OR1*
OR2*
OR3*
WRITE*
WRITE
WRITE*
WRITE*
MRS
REF
NOP*
MRS
WR
OR2WR*
NOP
OR3WR*
NOP
NOP*
IDLE
Note States and transitions marked with an asterisk (*) indicate
that the value of the REF# pin should be ignored, so that neither a
REFRESH, nor MRS command will be recognized in that state.
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RMHE41A184AGBG, RMHE41A364AGBG
2.5 Data mask
Datasheet
The DM pin is used during write cycles to indicate that the corresponding data are to be masked off from writing to the
memory. The value of the DM pin is sampled on both edges of DK0/DK0#, and corresponds to the data sampled on that
same edge of either DK0/DK0# or DK1/DK1#.
When the DM pin has a logic 0 value, the data will be written to the memory. When the DM pin has a logic 1 value, the
data will be ignored and no update to the corresponding memory data will be made.
The value of the DM pin is ignored in all other circumstances. Thus, driving a constant logic 0 to the DM pin can be used
in systems where all data cycles in a burst result in writes to the memory.
When the Auto-DM Function (ADM) bit is set via an MRS command, the value of the DM pin is ignored and the device will
behave as if it were a logic 0 on only the clock edge specified by the value of the DM pattern (DMP) field.
2.6 Data inversion
In order to reduce simultaneous switch noise, I/O current and average I/O power, the Low Latency DRAM-III provides the
ability to invert all data pins. Because the nominal design for Low Latency DRAM-III I/O signals is high-side termination to
VDDQ, signals driven to a logic high state will consume less power than those in a logic low state.
The DINVm-DINV0 pins indicate whether corresponding DQn-DQ0 pins, in groups of nine, represent the true logic value or
an inverted logic value. With the ability to invert DQn-DQ0 pins in groups of nine, each group is guaranteed to be driving
no more than five pins low on any given cycle. As a result, no more than five pins in each group can switch in the same
direction during each bit time, reducing simultaneous switching noise effects.
When data inversion is enabled (DI=1) and a DINV pin is a logic 1, the corresponding DQ pins have been inverted.
When data inversion is disabled (DI=0) then the device will ignore the value of the DINV pins for write data and will drive
DINV pins to logic 1 for read data; however, in such a case, the DQ pins are not inverted, regardless of the values of the
DINV pins.
2.7 Data bus turn-around
Because the DQn-DQ0 and DINVm-DINV0 pins are bidirectional, care must be taken to ensure that the Low Latency
DRAM-III and the system chip connected to it do not drive these pins simultaneously. In order to guarantee this, a rapid
DQ and DINV turn-off time is required. The actual bus turn-around time is dependent on many system parameters,
including BL, RL, WL, pre-amble, post-amble, controller I/O timing, DRAM I/O timing, PCB delays; and the system must
ensure that neither the Low Latency DRAM-III, nor the system chip is driving the bus during that time. This is
accomplished by inserting a sufficient number of NOP commands between each READ-to-WRITE command transition and
between each WRITE-to-READ transition. Additional NOP commands may be required to allow settling of the bus in order
to insure no adverse effect on I/O timing.
Note that a REFRESH command can be used in place of a NOP command to effect the insertion of an idle cycle on the
data bus.
2.8 Command cycles
A command to the Low Latency DRAM-III is initiated by driving the CS# pin low at the rising edge of CK and
simultaneously driving the WE#, REF#, and A0-A6 pins to the appropriate state corresponding to the command.
READ and WRITE commands each require 2 clocks to send the full command in burst length 4 mode, due to the
multiplexed nature of Address loading. The NOP and AUTO REFRESH commands are each a single cycle in length. The
OVERLAPPED REFRESH command is four cycles in length.
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RMHE41A184AGBG, RMHE41A364AGBG
2.9 Write data cycles
Datasheet
DQ0-DQn, DINV0-DINVm, and DM associated with a WRITE command are received by the Low Latency DRAM-III in a
DDR burst, starting on a rising edge of DK that is offset WL clock cycles from rising edge of the CK signal corresponding to
the first cycle that the WRITE command was initiated. This delay of WL cycles is intended to ensure that the write data are
not driven at the same time that data from a previous READ command are being driven from the Low Latency DRAM-III.
2.10 Read data cycles
DQ0-DQn and DINV0-DINVm associated with a READ command are driven by the Low Latency DRAM-III in a DDR burst
by the Low Latency DRAM-III RL clock cycles from the rising edge of the CK signal corresponding to the first cycle that the
READ command was initiated. This delay of RL cycles is equal to the delay required for the internal logic and memory
within the Low Latency DRAM-III to read data and make it available on the bus.
2.11 READ and WRITE command protocol
Figure 2-3 through Figure 2-4 show the READ and WRITE command sequences.
Figure 2-3 READ Command Sequence
tRC
tRL+2
tRL-1
tRL
tRL+1
0
1
2
3
CK#
CK
A0 A1 A2 A3
A
WE#,
REF#
CS#
QK#
QK
DQ,
DINV
R0 R1 R2 R3
QVLD
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Figure 2-4 WRITE Command Sequence
Datasheet
tRC
0
1
2
3
tWL
tWL+1
tWL+2
CK#
CK
A0 A1 A2 A3
A
REF#
CS#,
WE#
DK#
DK
DQ,
DINV,
DM
W3
W0 W1 W2
Figure 2-5 shows DDR Address examples of a sequence of 2 READ, 2 WRITE, and 2 READ commands, with the
following configuration:
Burst length 4
Speed Config 5: tRC=11, tRL=16, tWL=17
Data inversion is enabled
Some observations of this sequence are:
A NOP is inserted between READ2 and WRITE1 to allow for read-to-write bus turn-around
3 NOPs are inserted between WRITE2 and READ3 to allow for write-to-read bus turn-around
Because tRC is 11, READ3 may access the same bank as READ1; however, none of READ2, WRITE1, or WRITE2
may access the same bank as READ1
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Datasheet
Figure 2-5 READ/WRITE/READ Command Sequence (Speed Config 5, tRC=11, tRL=16, tWL=17, DI=1)
Command
Clock#
READ 1
0
READ 2
2
WRITE 1 WRITE 2
5 7
3 NOPs
READ 4
READ 3
12
NOP
t
RL
tWL
tRC
11
16
18
22
24
27
CK
CS#
WE#
A
READ
DATA1
16
READ
DATA2
18
WRITE
DATA1
22
WRITE
DATA2
READ
DATA3
READ
DATA4
0
2
5
7
12
24
DK
QK
DQ,
DINV
QVLD
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2.12 Automatic Refresh
Datasheet
Refresh cycles of the internal memory are initiated via the AUTO REFRESH command. Each refresh command causes a
single refresh cycle to occur on the bank specified in the command.
The minimum data retention time is 2 ms over the temperature range specified in 1. Electrical Specifications, and there
are 16384 words in each bank. Therefore, each bank must receive 16384 refresh commands every 2 ms in order to
ensure proper data retention.
This means that a refresh command must be received at an average rate of one every 15.3 ns. At a frequency of 800
MHz, this represents 8.2% of the usable bandwidth to the Low Latency DRAM-III.
The refresh command waveforms are shown in Figure 2-6. This refresh command is only supported if overlapped refresh
is not configured (see 2.13 Overlapped refresh commands).
Figure 2-6 Automatic Refresh Command Sequence
tRC
0
1
CK#
CK
BANK
A
WE#
CS#,
REF #
2.13 Overlapped refresh commands
Refresh commands may be overlapped with READ, WRITE, or NOP commands so that it is possible to design a system
that does not require any bus bandwidth to be consumed due to refresh. During the MRS command, overlapped refresh
may be enabled.
Once configured for overlapped refresh via an MRS command, the REF# pin is used to both initiate the refresh command
as well as to communicate the bank to be refreshed. This is accomplished by indicating one bit of bank address on each
rising edge of the CK clock, following the initial assertion of the REF# pin. The AUTO REFRESH command is not
supported when the Low Latency DRAM-III is configured for overlapped refresh mode.
The overlapped refresh command cannot be initiated on the same cycle as a READ or WRITE command; this avoids the
potential ambiguity of an overlapped refresh and WRITE command being interpreted as an MRS command. In general,
overlapped refresh commands are expected to be initiated one cycle out of phase with READ and WRITE commands.
In addition, once the overlapped refresh command has begun, the state of the REF# pin is ignored for the purposes of
command decoding, in order to allow subsequent READ or WRITE commands to begin while the refresh bank address is
being specified on the REF# pin.
Figure 2-7 shows the OVERLAPPED REFRESH command sequence.
An example of refresh being overlapped with READ commands is shown in Figure 2-8.
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Datasheet
Figure 2-7 Overlapped Refresh Command Sequence
tRC
0
1
2
3
4
CK#
CK
B0
B1
B2
REF #
WE#
CS#
See Note
Note tRC for overlapped refresh begins 3 cycles after the start of the command.
Figure 2-8 Overlapped Refresh with READ Commands
0
1
2
3
4
5
6
7
8
CK#
CK
A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3
A
B0
B1
B2
REF#
WE#
CS#
READ
READ
READ
OVERLAPPED
REFRESH
See Note
Note tRC for overlapped refresh begins 3 cycles after the start of the command.
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2.14 Clam-shell support
Datasheet
In order to support clam-shell mounting on the board, the pin-out of the Low Latency DRAM-III is designed so that most
pins that will be interchanged via mirroring are functionally interchangeable. A few pins require their function to be
swapped, however. The MF pin causes the pin assignment to be modified to effect those pin swaps. In order to support
proper signal integrity, package trace lengths for mirrored pins are matched to within +/- 0.1mm. Table 2-4 shows the pins
that are mirrored by the MF pin.
Due to the mirroring of A5 and A6, all devices are required to include an I/O cell on A6 in order to support the mirror
function. For lower capacity devices, the A6 pin would remain DNU, VDDQ from a memory controller standpoint, so the
system need not actively drive this functionally unused pin.
A3 and A4 are mirrored to support future devices that may use A3 as an additional bank select bit.
All of A0 through A5 must be mirrored in order for MRS commands to be interpreted correctly.
Table 2-4 Pins Affected by MF Pin
Pin
N4
MF=0
A0
MF=1
A1
N10
L4
A1
A0
A4
A3
L10
M5
M9
L2
A3
A4
A2
REF#
A2
REF#
CS#
WE#
A5
WE#
CS#
A6
L12
H10
H4
A6
A5
H2
RST#
DM
DM
RST#
H12
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3.Initialization
Datasheet
Prior to functional use, the Low Latency DRAM-III must be initialized and configured. The steps described in this chapter
will ensure that the internal logic of the Low Latency DRAM-III has been properly reset and that the functional timing
parameters of the chip have been configured.
Figure 3-1 shows the overall initialization sequence required by the Low Latency DRAM-III. An example of an initialization
sequence, showing each of the different phases, is shown in Figure 3-7.
Figure 3-1 Initialization Flow
Power on
Reset chip and
comfigure
impedances
No
Deskew
Required?
Yes
Control/address
Deskew
(loopback)
Enable PLL
and other modes
(MRS command)
Enable PLL
and other modes
(MRS command)
Read data
deskew
Write data
deskew
Set modes
(MRS commands)
Normal operation
New
No
Yes
deskew
Required?
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3.1 Power-on
Datasheet
1. There are no restrictions on the sequence of applying the VDD, VEXT, and VDDQ power supplies as long as maintaining
RST# = Low and fix MF input state before and during any of the power supplies ramp up.
2. In case when RST# can not be asserted Low and fixed MF input state before and during any of the power supplies
ramp up, make sure to ramp up following manners.
(1) Ramp up VDD and VEXT
(no ramp up sequence restriction on VDD and VEXT
(2) Ramp up VDDQ and VREF following to the VDD and VEXT
(no ramp up sequence restriction on VDDQ and VREF
)
)
(3) Make sure to assert RST# for tRSS specified period before initiating any operations
Figure 3-2 Power-on 1
VDD
VEXT
V
DDQ
VREF
tRSS
RST#
MF
CS# or LBK#
CK/CK#
tRSH
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Datasheet
Figure 3-3 Power-on 2
VDD
VEXT
VDDQ
VREF
tRSS
RST#
MF
CS# or LBK#
CK/CK#
tRSH
3.2 Reset
Before the Low Latency DRAM-III can be configured, it must be properly reset, to ensure that the Low Latency DRAM-III is
in a known and functional state, regardless of any power on anomalies and power supply ramp rates. Reset requires the
assertion of the RST# pin for at least 200 µs, during which time the device logic is reset to a known state, and the I/O
impedances are programmed as described in 3.3 Initial impedance settings.
The contents of memory are not guaranteed to be retained when the chip is reset.
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3.3 Initial impedance settings
Datasheet
When the RST# pin is deasserted, the value of specific DQ pins is used to configure the input termination and output
impedance as shown in Table 3-1. The meaning of the bits is the same as the corresponding bits described in 3.5
Configuration, although their positions in the DQ pins are unrelated to their positions in the corresponding MRS registers.
While RST# is asserted, the impedance values are continuously updated based on the values of the DQ pins and on the
sampled value of the ZQ impedance programming pin. On the rising edge of RST#, the values will be latched into the
device and stored in the appropriate positions in the MRS registers. Figure 3-4 shows the waveforms associated with this
function.
Note that the DINV pins are ignored during reset time and the values of the DQ pins are considered to never be inverted
during this time.
Table 3-1 Reset Impedance Control Assignments
Pins
U12 T11 U4 R12 T5 P13 R4 P11 P5 B12 C11 B4 D12 C5 E13 D4 E11 E5
DQ (x18)
DQ (x36)
Reset Reg
MSB → LSB
Cell ID
17
26
17
16
25
16
15
24
15
14
23
14
13
22
13
12
21
12
11
20
11
10
19
10
9
18
9
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
KD
KU
CD
CU
DD
DU
ODT QD QU
IM
Figure 3-4 Reset Sequence
0
1
CK#
CK
RST #
DQ
CS#,
WE#,
REF #
DK#
DK
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3.4 Per-bit de-skew training sequence
Datasheet
The Low Latency DRAM-III device provides support that allows a memory controller to de-skew signals for high-speed
operation. If per-bit de-skew is desired, the memory controller must provide the actual de-skew functionality. Per-pin de-
skew is normally performed after deassertion of the RST# pin, but may be performed at any time, without affecting the
contents of the memory within the device. Furthermore, resetting the device does not necessarily affect the skew
characteristics of the device pins; therefore, a reset of the device does not necessarily require repeating the de-skew
training sequence that was previously performed.
Per-pin de-skew training is anticipated to be implemented in three steps:
De-skew of the control, address, and clock pins: A0-A6, CS#, WE#, REF#, and DK0-DK1 with respect to CK
De-skew of the read path: DQ0-DQn, DINV0- DINVm and QVLD with respect to QK0-QK1
De-skew of the write path: DQ0-DQn, DINV0- DINVm and DM with respect to DK0-DK1
The first phase, de-skew of the control and related pins, requires support from the device by driving the LBK# pin to a logic
0. When the LBK# pin is a logic 0, the DK0-DK1, CS#, WE#, REF#, and A0-A6 pins are looped back to the various DQ
and DINV pins. All pins are sampled by the CK clock, including DK0-DK1. The specific mapping of input pins to output
pins during loopback mode is shown in Table 3-2.
Table 3-2 Control/Address Pin Mapping When LBK#=0
x36 part
Input
x18 part
Output
Input
Output
Input Pin
Output
Pin
MF=0
MF=1
MF=0
MF=1
A6
A6
H4
E5
A5
DQ0
A5
DQ0
(DNU, VDDQ
)
(DNU, VDDQ)
J1, K1
L4
E11
P5
R4
T5
DK0, DK0#
DK0, DK0#
A3
DQ1
DQ18
DQ20
DQ22
DQ24
DK0, DK0#
DK0, DK0#
A3
DQ1
DQ9
A4
CS#
A2
A4
CS#
A2
L2
WE#
REF#
A1
WE#
REF#
A1
DQ11
DQ13
DQ15
M5
N4
U4
A0
A0
A6
A6
H10
E13
A5
DQ3
A5
DQ3
(DNU, VDDQ
)
(DNU, VDDQ
DNU, VSS
A4
)
J11, K11
L10
E3
DK1, DK1#
A3
DK1, DK1#
DQ14
DQ19
DQ21
DQ25
DQ26
DNU, VSS
A3
DNU, VSS
DQ10
P11
P13
T11
U12
A4
CS#
A2
L12
WE#
WE#
REF#
A1
CS#
DQ12
M9
REF#
A1
A2
DQ16
N10
A0
A0
DQ17
Note
DK0, DK0# and DK1, DK1# have differential receivers, so the output of the receiver is used as signal being looped back.
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Datasheet
For each pin that is looped back, the input pin is sampled on both the rising edge and falling edges of the corresponding
input clock. The value output on the rising edge of the corresponding output clock will be the value that was sampled on
the rising edge of the input clock. The value output on the falling edge of the corresponding output clock will be the
inverted value that was sampled on the falling edge of the input clock. Data inversion is not used during loopback mode
and the value of the corresponding MRS bits are ignored.
The delay from input pins to DQ/DINV output pins, when loopback mode is enabled, is 5 cycles of CK.
In burst length 4 mode, while the LBK# pin is a logic 0 , the DQ/DINV output pins corresponding to unused input pins (See
Table 3-2) will still meet the AC timing specification (See Interface AC Parameters), but they may have arbitrary logic
state and may or may not have a constant logic value.
While the LBK# pin is a logic 0, the device will ignore any apparent commands being presented on the CS#, WE#, and
REF# pins and will perform self refresh operations to prevent loss of data during extended periods of de-skew training. In
order to ensure that commands are not inadvertently received during entry and exit from de-skew training, no commands
may be sent to the device for a period of 16 cycles of CK prior to the LBK# pin being driven to 0, nor for 16 cycles after the
LBK# pin is returned to a logic 1. Also, no valid input signals for looped back must be inserted for 16 cycles after LBK# pin
being driven to 0 when device just enters into loopback mode.
While LBK# is asserted, the on-chip PLL is ignored; therefore the phase of the QK output clock will be undefined with
respect to the CK input clock. However, the QK to DQ timing will still meet its specifications. Note that the PLL will remain
enabled or disabled, per its state prior to LBK# being asserted, and after LBK# is deasserted.
An example of a loopback sequence is show in Figure 3-5.
Figure 3-5 Loopback De-skew Training Sequence
tLBL
0
1
2
3
5
6
7
CK#
CK
CS#,
WE# ,
REF #,
A, DK
LBK#
tCD
QK#
QK
DQ
Parameter
Symbol
tLBL
-120
-150
Units
Cycle
ns
Loopback Latency
5
5
5
5
Maximum CK to QK/DQ Output Delay in Loopback Mode
tCD
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Datasheet
Following de-skew of the control, address, and DK pins, the memory controller drives the LBK# pin to a logic 1, then will
likely perform read data and write data de-skew training.
Prior to beginning read path de-skew, the memory controller should issue an MRS command to the Low Latency DRAM-III
device to enable the PLL. After the PLL is enabled, the timing of the QK, DQ outputs, and QVLD will be unspecified for a
period of tPLL. The MRS command is described in 3.5 Configuration. While the PLL is stabilizing, refresh commands must
continue to be issued to the device in order to ensure proper retention of data.
Read data de-skew requires that a training pattern be written to Low Latency DRAM-III memory. Complex data patterns
can be written to the Low Latency DRAM-III memory using the non-de-skewed DQ signals and the auto-DM functions.
Auto-DM functions are enabled through MRS, as described in 3.5 Configuration.
Read data de-skew can be performed by using the de-skewed control and related pins, including the DK pin, and non-
switching DQ and DINV pins to write 36-bit values to memory locations in the device. Because the data are held at
constant values, the auto-DM modes of the device are used to specify which 36-bit beat (or 18-bit beat for x18 devices) of
data on the bus is to be written to the memory. Once written to the memory, these data can then be read out using
standard BL4 READ commands to effect any desired pattern on the DQ bus. This permits the system to de-skew the DQ,
DINV, and QVLD signals with respect to the QK clocks.
Write data de-skew can be performed by issuing WRITE commands to the device, then using the de-skewed read bus to
determine whether or not data were correctly received by the device. This permits the system to de-skew the DQ, DINV,
and DM signals with respect to the DK clocks.
3.5 Configuration
The MRS command is used to configure the Low Latency DRAM-III. Configuration is used to specify the following
parameters:
Address Mode
The Address Mode of Low Latency DRAM-III devices from some vendors may be electrically configurable. The default
Address Mode may vary from vendor-to-vendor as well. Therefore, systems must configure the desired Address Mode
prior to issuing READ or WRITE commands
Mode select for READ latency, WRITE latency, and tRC
The version of the Low Latency DRAM-III covered by this specification only supports modes 4 and 5
Select driver pull-up impedance of 1/4 or 1/6 of reference resistor (default 1/4)
Select driver pull-down impedance of 1/4 or 1/6 reference resistor (default 1/6)
Select DQ, DINV, DM, DK, DKN, CK, CK#, RST# terminator pull-up impedance of OFF, 1x, 1/2, or 1/4 of reference resistor
(default 1/4)
Select DQ, DINV, DM, DK, DKN, CK, CK#, RST# terminator pull-down impedance of OFF, 1x, 1/2, or 1/4 of reference
resistor (default OFF)
Select CS#, WE#, REF#, A, LBK#, TCK, TDI, TMS terminator pull-up impedance of OFF, 1x, 1/2, or 1/4 of reference
resistor (default 1/4)
Select CS#, WE#, REF#, A, LBK#, TCK, TDI, TMS terminator pull-down impedance of OFF, 1x, 1/2, or 1/4 of reference
resistor (default OFF)
Enable/freeze dynamic PVT compensation (default enabled)
Enable/disable PLL (default disabled)
Enable/disable read/write data inversion (default disabled)
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Datasheet
Refresh Mode (default AUTO REFRESH)
Select Auto-DM Mode (default disabled)
The MRS command allows the configuration of one of eight different registers to be configured using SDR timing on the
address pins. The MRS command waveforms are shown in Figure 3-6 and the values of the MRS registers are described
in Table 3-3 through Table 3-6. Because an MRS command may change values that significantly affect the behavior of
the device, no other commands should be issued to the device for a period of tMRD clock cycles following the MRS
command.
MRS commands use the address pins specified in Table 3-3. The actual pins used depend on the value of the mirror
function (MF) pin.
Table 3-3 MRS Configuration Register Bit Assignments
Beat 0
L10
L4
Beat 2
L10
L4
Pins (MF=0)
Pins (MF=1)
Address
H4
H10
A6
H10
H4
L4
L10
A4
M5
M9
A2
N10
N4
N4
N10
A0
H4
H10
A6
H10
H4
L4
L10
A4
M5
M9
A2
N10
N4
N4
N10
A0
A5
A3
A1
A5
A3
A1
Mode Register
MSB→LSB
Mode Reg #
Active
Active
X
X
X
X
X
X
X
X
Configuration
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
0
0
DI
0
FZ
0
RM
0
BL
DMP
KU
QD
ADM
ODT
IM
0
0
PLL
Active
CD
DD
CU
DU
0
KD
Active
QU
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Table 3-4 MRS Configuration Bit Definitions
Datasheet
Speed Configuration
Config #
Clock Cycles
tRL
Configuration
DI
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
tRC
tWL
Not supported
Not supported
Not supported
Not supported
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10
11
12
13
15
14
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
10
11
14
15
17
16
Not supported
Not supported
Refresh Mode
PLL Control
RM
0
Operation
PLL
0
Operation
Auto Refresh Mode (Default)
Overlapped Refresh Mode
PLL Off / Reset (Default)
PLL On
1
1
Auto-DM Function
ADM
Burst Length
BL
Operation
Operation
4
0
1
Off / Normal Operation (Default)
On
0
0
1
1
0
1
0
1
Not supported
Reserved
Reserved
Note When ADM=0, DMP=Don't Care
Note Setting 01,10 & 11 not supported
Auto-DM Pattern
Burst of 4
Pattern #
DMP
00
1
01
0
10
0
11
0
Impedance Freeze
Write Beat 0
Write Beat 1
Write Beat 2
Write Beat 3
FZ
0
Operation
Update active (Default)
Update frozen
0
1
0
0
0
0
1
0
1
0
0
0
1
Note Data to be written =1, Data to be masked =0
Data Inversion
DI
Operation
0
1
Disable data inversion (Default)
Enable data inversion
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Datasheet
Table 3-5 MRS Input Termination Bit Definitions
Data Input On-Die Termination - Up Data Input On-Die Termination - Down
Pins
DQ, DINV,
DM,
ODT
DU
Div 200 240 RQ Ohms ODT
DD
Div
Off
Off
1
200 240
RQ Ohms
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
Off
Off
1
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
DK0, DK0#
DK1, DK1#
200 240
(Not Supported)
(Not Supported)
(Not Supported)
1/2 100 120
1/4 50 60
1/2
1/4
Pins
Address,
CS#, WE#,
REF#
Control Input On-Die Termination - Up
Control Input On-Die Termination - Down
ODT
CU
Div 200 240 RQ Ohms ODT
CD
Div
Off
Off
1
200 240
RQ Ohms
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
Off
Off
1
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
200 240
(Not Supported)
(Not Supported)
(Not Supported)
1/2 100 120
1/4 50 60
1/2
1/4
Pins
Clock Input On-Die Termination - Up
Clock Input On-Die Termination - Down
ODT
KU
Div 200 240 RQ Ohms ODT
KD
Div
Off
Off
1
200 240
RQ Ohms
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
Off
Off
1
1
X
0
0
0
X
1
1
0
0
X
1
0
1
0
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
CK, CK#
200 240
(Not Supported)
(Not Supported)
(Not Supported)
1/2 100 120
1/4 50 60
1/2
1/4
Note Internal RQ is set to 240Ω when IM=1.
Table 3-6 MRS Output Impedance Bit Definitions
Output Driver Impedance - Up Output Driver Impedance - Down
Pins
DQ, DINV,
QK0, QK0#
QK1, QK1#
QVLD
IM
0
QU
1
Div
1/4
X
200
50
240
60
RQ Ohms
IM
0
QD
1
Div
1/4
X
200
50
240
60
RQ Ohms
1
X
60*
NA
60*
40.0
1
X
40*
33.3
40*
0
0
1/6
0
0
1/6
40.0
Note 60* = 60 Ω +/- 20% no PVT compensation
Note 40* = 40 Ω +/- 20% no PVT compensation
Figure 3-6 MRS Sequence
0
1
2
3
CK#
CK
A0
A2
A
CS#,
WE#
REF #
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 37 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Figure 3-7 Initialization Sequence (DDR Address mode shown)
Datasheet
CK
RST #
LBK#
CS#
WE#
REF #
Note : refresh should be performed on a regular basis
A
DK
DQ,
DINV,
DM
Control/
Address
De-skew
PLL
Initial
and Config
Read path de-skew
Write path de-skew
Reset
Write data at
low speed
Read data at
full speed
Write data at
full speed
Read data at
full speed
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 38 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
4.JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
4.1 Test Pins
Table 4-1 Low Latency DRAM-III Test Pins
Functional
Pin Name
Test Use
Pull Up/Down in Chip
Pull Up/Down on Board
Mode Value
TDI
TDO
JTAG serial chain input
JTAG serial chain output
JTAG clock
1
1
0
1
0
1
1
TCK
0
1
0
TMS
JTAG mode
1
0
TRST#
JTAG reset
Table 4-2 Test Access Port (TAP) Pins
Description
Pin Name
Pin Assignment
TCK
3A
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
1A
Test Mode Select. This is the command input for the TAP controller state machine.
Test Data Input. This is the input side of the serial registers placed between TDI
and TDO. The register placed between TDI and TDO is determined by the state
of the TAP controller state machine and the instruction that is currently loaded in
the TAP instruction.
13V
TDO
13T
1L
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Test Reset Input. This is active-low input asynchronously reset the TAP controller.
This pin should be driven low or tied to GND when JTAG function is not in use.
TRST#
Table 4-3 JTAG DC Characteristics (0°C ≤ TC ≤ 95°C, 1.395 V ≤ VDD ≤ 1.605 V, unless otherwise noted)
Parameter
Symbol
Conditions
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDDQ
Outputs disabled
MIN.
MAX.
+100
+100
Unit
JTAG Input leakage current
JTAG I/O leakage current
ILI
−100
100
µ
A
A
−
ILO
,
µ
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
JTAG output LOW voltage
VIH (DC)
VIL (DC)
VOH (DC)
VOL (DC)
VREF + 0.15
SS − 0.3
VDDQ − 0.10
VDDQ + 0.3
V
V
V
REF − 0.15
V
V
V
| IOHC | = 100
IOLC = 100
µ
A
µ
A
0.10
Note All voltages referenced to VSS (GND).
Table 4-4 JTAG Capacitance
Teat Conditions
Parameter
Symbol
MIN.
MAX.
Unit
JTAG input capacitance
(TCK, TDI, TMS and TRST#)
JTAG output capacitance
(TDO)
CINJ
VIN = 0V
2.5
pF
COJ
VIO = 0V
2.5
pF
Note Including package.
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 39 of 51
RMHE41A184AGBG, RMHE41A364AGBG
4.2 JTAG AC Test Conditions
Datasheet
Input waveform (Rise / Fall time ≤ 0.3 ns)
VDDQ
VIH(AC) MIN.
VIL(AC) MAX.
VSS
Rise Time:
2 V/ns
Fall Time:
2 V/ns
Output waveform
VDDQ*0.7
VDDQ*0.7
Test Points
Output load condition
VDDQ
60Ω
50Ω
Output
2 pF
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 40 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Table 4-5 JTAG AC Characteristics (0°C ≤ TC ≤ 95°C)
Datasheet
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Note
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
tTHTL
tTLTH
20
ns
MHz
ns
50
10
10
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
ns
ns
10
Setup time
TMS setup time
tMVTH
tDVTH
tRVTH
5
5
ns
ns
ns
TDI valid to TCK HIGH
TRST High Level to
valid rising edge of TCK
Capture setup time
50
tCSJ
5
ns
1
1
Hold time
TMS hold time
tTHMX
tTHDX
tCHJ
5
5
5
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
Reset
TRST LOW pulse width
tTRSTW
100
ns
Note tCSJ and tCHJ refer to the setup and hold time requirements of latching data from the boundary scan register.
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
TDI
tTHMX
tDVTH
tTHDX
tTLOV
tTLOX
TDO
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 41 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Table 4-6 Scan Register Definition (1)
Description
Datasheet
Register name
Instruction register
The 8 bit instruction registers hold the instructions that are executed by the TAP controller. The register
can be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in
test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible. The bypass register is set LOW (VSS) when the bypass instruction is executed.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs
I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins
when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the
boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register location.
The first column defines the bit’s position in the boundary register. The second column is the name of
the input or I/O at the bump and the third column is the bump number.
Table 4-7 Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
8
1
bit
32
113
bit
Boundary register
bit
Table 4-8 ID Register Definition
ID [31:28]
ID [27:12]
part no.
Part number
Organization
ID [11:1] vendor ID no. ID [0] fix bit
vendor revision no.
RMHE41A184AGBG
RMHE41A364AGBG
64M x 18
32M x 36
0000
0000
1000 0010 1100 1101
1000 0010 1100 1100
01000100011
01000100011
1
1
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 42 of 51
RMHE41A184AGBG, RMHE41A364AGBG
4.3 Boundary Scan
Datasheet
IEEE 1149.1 compliant boundary scan will be implemented on all component I/O pins. High speed I/Os that are differential
or AC coupled will be fully compliant to the IEEE 1149.6 standard.
The actual boundary scan order is defined in an underscore (e.g. “CS#_WE#”).
Table 4-9 and Table 4-10.
Pins labeled DNU0 are DNU, VSS. Pins labeled DNU1 are DNU, VDDQ. Pins that are subject to the mirror function are
named with the obverse name and reverse name, separated by an underscore (e.g. “CS#_WE#”).
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 43 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Table 4-9 Boundary Scan Order, x18
Datasheet
Safe
Bit
X
X
X
X
X
X
0
Cntrl
Cell
Cntrl
Cntrl
x18
Cell #
Cell
Pin Name
TYPE
Value
State
J3
K3
L2
0
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
DK0
input
input
1
DK0#
2
CS#_WE#
input
L4
3
A4_A3
input
M5
M3
4
A2_REF#
input
5
DNU1(1)
internal
control
bidir
6
*
N2
N4
7
DINV1
X
X
0
6
9
0
0
Z
Z
8
A0_A1
input
9
*
control
bidir
P5
P3
P1
R2
R4
T5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
DQ9
X
0
*
internal
internal
internal
internal
internal
internal
control
bidir
DNU0(1)
X
0
*
DNU0(2)
X
0
*
DNU0(3)
X
0
*
DQ11
X
0
17
19
0
0
Z
Z
*
control
bidir
DQ13
X
0
*
internal
internal
output2
internal
internal
control
bidir
T3
T1
DNU0(4)
X
X
0
QK1#
*
U2
DNU0(5)
X
0
*
DQ15
QK1
U4
V1
X
X
0
26
29
0
0
Z
Z
output2
control
bidir
*
U12
U10
T9
DQ17
*
X
0
internal
internal
internal
internal
control
bidir
DNU0(6)
*
X
0
DNU0(7)
*
X
0
T11
R12
R10
P9
DQ16
*
X
0
35
37
0
0
Z
Z
control
bidir
DQ14
*
X
0
internal
internal
internal
internal
control
bidir
DNU0(8)
*
X
0
DNU0(9)
*
X
0
P11
P13
DQ10
*
X
0
43
45
0
0
Z
Z
control
bidir
DQ12
*
X
0
internal
internal
input
N12
N10
M9
DNU0(10)
A1_A0
REF#_A2
DNU1(2)
WE#_CS#
A3_A4
CK#
X
X
X
X
X
X
X
X
1
input
M11
L12
L10
K9
internal
input
input
input
K11
J13
J11
J9
DNU0(11)
LBK#
DNU0(12)
CK
internal
input
internal
input
X
X
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 44 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
Safe
Bit
X
X
X
X
X
0
Cntrl
Cell
Cntrl
Cntrl
x18
Cell #
Cell
Pin Name
TYPE
Value
State
H10
H12
G11
G9
59
60
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
A5_A6
input
input
DM_RST#
61
DNU1(3)
internal
internal
internal
internal
internal
control
bidir
62
DNU1(4)
F10
63
DNU1(5)
64
*
F12
E13
E11
E9
65
DNU0(13)
X
0
66
*
67
DQ3
X
0
66
68
0
0
Z
Z
68
*
control
bidir
69
DQ1
X
0
70
*
internal
internal
internal
internal
control
bidir
71
DNU0(14)
X
0
72
*
D10
73
DNU0(15)
X
0
74
*
D12
C13
75
DQ5
X
X
0
74
77
0
0
Z
Z
76
QK0#
output2
control
bidir
77
*
C11
C9
78
DQ7
X
0
79
*
internal
internal
internal
internal
control
bidir
80
DNU0(16)
X
0
81
*
B10
82
DNU0(17)
X
0
83
*
B12
A13
84
DQ8
X
X
0
83
86
0
0
Z
Z
85
QK0
output2
control
bidir
86
*
B4
87
DQ6
X
0
88
*
internal
internal
output2
internal
internal
control
bidir
B2
C1
89
DNU0(18)
X
X
0
90
QVLD
91
*
C3
C5
D4
D2
E1
E3
92
DNU0(19)
X
0
93
*
94
DQ4
X
0
93
95
0
0
Z
Z
95
*
DQ2
control
bidir
96
X
0
97
*
internal
internal
internal
internal
internal
internal
control
bidir
98
DNU0(20)
*
X
0
99
100
101
102
103
104
105
106
107
108
109
110
111
112
DNU0(21)
*
X
0
DNU0(22)
*
X
0
E5
F4
DQ0
X
X
0
103
106
0
0
Z
Z
DNU1(6)
*
internal
control
bidir
F2
G3
G5
H4
H2
J1
DINV0
DNU1(7)
DNU1(8)
A6_A5
RST#_DM
MF
X
X
X
X
X
X
internal
internal
input
input
input
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 45 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Table 4-10 Boundary Scan Order, x36
Datasheet
Safe
Bit
X
Cntrl
Cell
Cntrl
Cntrl
x36
Cell #
Cell
Pin Name
TYPE
Value
State
J3
K3
L2
L4
M5
0
1
2
3
4
BC_1
BC_1
BC_1
BC_1
BC_1
DK0
DK0#
input
input
input
input
input
X
CS#_WE#
A4_A3
X
X
A2_REF#
X
M3
5
BC_1
DNU1(1)
internal
X
6
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
*
DINV2
A0_A1
*
control
bidir
0
X
X
0
N2
N4
7
6
0
Z
8
input
9
control
bidir
P5
P3
P1
R2
R4
T5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
DQ18
*
X
0
9
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
control
bidir
DQ34
*
X
0
11
13
15
17
19
21
control
bidir
DQ35
*
X
0
control
bidir
DQ32
*
X
0
control
bidir
DQ20
*
X
0
control
bidir
DQ22
*
X
0
control
bidir
T3
T1
DQ30
QK1#
*
X
X
0
output2
control
bidir
U2
DQ28
*
X
0
24
26
0
0
Z
Z
control
bidir
U4
V1
DQ24
QK1
*
X
X
0
output2
control
bidir
U12
U10
T9
DQ26
*
X
0
29
31
33
35
37
39
41
43
45
47
0
0
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
control
bidir
DQ27
*
X
0
control
bidir
DQ29
*
X
0
control
bidir
T11
R12
R10
P9
DQ25
*
X
0
control
bidir
DQ23
*
X
0
control
bidir
DQ31
*
X
0
control
bidir
DQ33
*
X
0
control
bidir
P11
P13
DQ19
*
X
0
control
bidir
DQ21
*
X
0
control
bidir
N12
N10
M9
DINV3
A1_A0
REF#_A2
DNU1(2)
WE#_CS#
A3_A4
CK#
DK1#
LBK#
DK1
CK
X
X
X
X
X
X
X
X
1
input
input
M11
L12
L10
K9
internal
input
input
input
K11
J13
J11
J9
input
input
input
X
X
input
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 46 of 51
RMHE41A184AGBG, RMHE41A364AGBG
Datasheet
Safe
Bit
X
X
X
X
X
0
Cntrl
Cell
Cntrl
Cntrl
x36
Cell #
Cell
Pin Name
TYPE
Value
State
H10
H12
G11
G9
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
A5_A6
input
input
DM_RST#
DNU1(3)
internal
internal
internal
control
bidir
DNU1(4)
F10
DNU1(5)
*
F12
E13
E11
E9
DINV1
X
0
64
66
68
70
72
74
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
*
control
bidir
DQ3
X
0
*
control
bidir
DQ1
X
0
*
control
bidir
DQ17
X
0
*
control
bidir
D10
DQ15
X
0
*
control
bidir
D12
C13
DQ5
X
X
0
QK0#
output2
control
bidir
*
C11
C9
DQ7
X
0
77
79
81
83
0
0
0
0
Z
Z
Z
Z
*
control
bidir
DQ13
X
0
*
DQ11
*
control
bidir
B10
X
0
control
bidir
B12
A13
DQ8
QK0
*
X
X
0
output2
control
bidir
B4
DQ6
*
X
0
86
88
0
0
Z
Z
control
bidir
B2
C1
DQ9
QVLD
*
X
X
0
output2
control
bidir
C3
C5
D4
D2
DQ10
*
X
0
91
93
95
97
0
0
0
0
Z
Z
Z
Z
Z
control
bidir
DQ4
*
X
0
control
bidir
DQ2
*
X
0
control
bidir
DQ12
*
X
0
control
E1
E3
100
BC_7
DQ16
bidir
X
99
0
101
102
103
104
105
106
107
108
109
110
111
112
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
*
DQ14
*
control
bidir
0
X
0
101
103
0
0
Z
Z
control
bidir
E5
F4
DQ0
X
X
0
DNU1(6)
*
internal
control
bidir
F2
G3
G5
H4
H2
J1
DINV0
DNU1(7)
DNU1(8)
A6_A5
RST#_DM
MF
X
X
X
X
X
X
106
0
Z
internal
internal
input
input
input
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 47 of 51
RMHE41A184AGBG, RMHE41A364AGBG
4.4 JTAG Instructions
Datasheet
Many different instructions (28) are possible with the 8-bit instruction register. All used combinations are listed in Table
4-11, Instruction Codes. These six instructions are described in detail below. The remaining instructions are reserved and
should not be used.
The TAP controller used in this RAM is fully compliant to the 1149.1 convention. Instructions are loaded into the TAP
controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state,
instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is
shifted in, the TAP controller needs to be moved into the Update-IR state.
Table 4-11
Instructions
Instruction
Code [7:0]
Description
EXTEST
0000 0000
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those
at input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on
and the PRELOAD data is driven onto the output pins.
IDCODE
0010 0001
0000 0101
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO
pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at
power up and any time the controller is placed in the test-logic-reset state.
SAMPLE / PRELOAD
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and Q pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture
setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan
register. Moving the controller to shift-DR state then places the boundary scan register
between the TDI and TDO pins.
CLAMP
0000 0111
0000 0011
1111 1111
−
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary scan register.
Selects the bypass register to be connected between TDI and TDO. Data driven by
output balls are determined from values held in the boundary scan register.
High-Z
The High-Z instruction causes the boundary scan register to be connected between the
TDI and TDO. This places all RAMs outputs into a High-Z state.
Selects the bypass register to be connected between TDI and TDO. All outputs are
forced into high impedance state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register
is placed between TDI and TDO. This occurs when the TAP controller is moved to the
shift-DR state. This allows the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 48 of 51
RMHE41A184AGBG, RMHE41A364AGBG
4.5 TAP Controller State Diagram
Datasheet
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 49 of 51
RMHE41A184AGBG, RMHE41A364AGBG
5.Package Drawing
Datasheet
180-PIN FCBGA (18.5 x 14)
JEITA Package Code
RENESAS Code
PLBG0180FA-A
Previous Code
MASS (TYP.) [g]
P-LBGA180-14x18.5-1.00
T180F5-100-FE1
0.61
R10DS0250EJ0100 Rev. 1.00
Jun. 19, 2015
Page 50 of 51
Revision History
RMHE41A184AGBG, RMHE41A364AGBG
Description
Summary
Rev.
Date
Page
Rev. 0.01
Rev. 0.02
’14.10.01
’15.04.01
-
-
New Preliminary Datasheet
Fixed some typo
50
-
Added Package drawing
New Datasheet
Rev. 1.00
’15.06.19
All trademarks and registered trademarks are the property of their respective owners.
C - 51
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Colophon 5.0
相关型号：
RMIK0-55S
MIL Series Connector, 55 Contact(s), Polyethylene, Female, Crimp Terminal, Receptacle, ROHS COMPLIANT
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