RMLV1616AGBG-5S2 [RENESAS]
16Mb Advanced LPSRAM (1M word à 16bit / 2M word x 8bit);
| 型号： | RMLV1616AGBG-5S2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16Mb Advanced LPSRAM (1M word à 16bit / 2M word x 8bit) 静态存储器 |
| 文件： | 总16页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RMLV1616A Series
16Mb Advanced LPSRAM (1M word × 16bit / 2M word x 8bit)
R10DS0258EJ0100
Rev.1.00
2016.01.06
Description
The RMLV1616A Series is a family of 16-Mbit static RAMs organized 1,048,576-word × 16-bit, fabricated by
Renesas’s high-performance Advanced LPSRAM technologies. The RMLV1616A Series has realized higher density,
higher performance and low power consumption. The RMLV1616A Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 48pin TSOP (I), 52pin TSOP (II) or 48-ball fine
pitch ball grid array.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 55ns (max.)
Current consumption:
── Standby: 0.5µA (typ.)
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Temperature
Range
Part Name
Access time
Package
RMLV1616AGSA-5S2
12mm x 20mm 48pin plastic TSOP (I)
RMLV1616AGSD-5S2
RMLV1616AGBG-5S2
55 ns
-40 ~ +85°C
10.79mm × 10.49mm 52pin plastic µTSOP (II)
48-ball FBGA with 0.75mm ball pitch
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2016.01.06
Page 1 of 14
RMLV1616A Series
Pin Arrangement
A15
A14
A13
A12
A11
A10
A9
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
Vss
3
4
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
5
6
7
A8
8
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
CS2
NC
48pin TSOP (I)
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
UB#
LB#
A18
A17
A7
A6
A5
A4
A3
Vss
A2
CS1#
A0
A1
A15
A14
A13
A12
A11
A10
A9
1
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
A16
2
BYTE#
UB#
Vss
1
2
3
4
5
6
3
4
LB#
OE#
A0
A1
A2
A
B
C
D
CS2
DQ0
DQ2
Vcc
5
LB#
6
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
DQ15 UB#
A3
A4
A6
A7
CS1#
DQ1
DQ3
7
A8
8
DQ13 DQ14 A5
Vss DQ12 A17
Vcc DQ11 NC
DQ10 DQ9 A14
A19
CS1#
WE#
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A16 DQ4
A15 DQ6
A13 WE#
Vss
E
F
NC
52pin TSOP (II)
Vcc
CS2
NC
DQ5
DQ7
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
DQ8
A18
A19
A8
A12
A9
G
H
NC
A18
A17
A7
A10
A11
A6
A5
48-ball FBGA (TOP VIEW)
A4
A3
A2
NC
A1
A0
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2016.01.06
Page 2 of 14
RMLV1616A Series
Pin Description
Pin name
VCC
Function
Power supply
VSS
Ground
A0 to A19
A-1 to A19
DQ0 to DQ15
CS1#
Address input (word mode)
Address input (byte mode)
Data input/output
Chip select 1
CS2
Chip select 2
OE#
Output enable
WE#
Write enable
LB#
Lower byte select
Upper byte select
Byte control mode enable
No connection
UB#
BYTE#
NC
Block Diagram
DQ0
Memory Array
A0
1048576 Words
x 16BITS
DQ7
DQ8
OR
2097152 Words
x 8BITS
A19
DQ15
/ A-1
CS2
CS1#
LB#
CLOCK
GENERATOR
Vcc
Vss
x8/x16
SWITCHING
CIRCUIT
UB#
BYTE#
WE#
OE#
Note 1. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
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2016.01.06
Page 3 of 14
RMLV1616A Series
Operation Table
CS1#
CS2
X
BYTE#
UB#
X
X
H
H
H
H
L
LB#
X
X
H
L
WE#
X
OE#
X
DQ0~7
High-Z
High-Z
High-Z
Din
DQ8~14
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Operation
Stand-by
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
H
H
L
L
X
X
Stand-by
X
X
X
Stand-by
H
H
H
H
H
H
H
H
H
H
H
H
L
X
Write in lower byte
Read in lower byte
Output disable
Write in upper byte
Read in upper byte
Output disable
Word write
L
H
H
L
L
Dout
L
H
X
High-Z
High-Z
High-Z
High-Z
Din
H
H
H
L
L
H
H
L
L
Dout
Dout
L
H
X
High-Z
Din
High-Z
Din
L
L
L
H
H
L
L
Dout
Dout
Dout
Word read
L
L
H
X
High-Z
Din
High-Z
High-Z
High-Z
High-Z
High-Z
A-1
Output disable
Byte write
X
X
X
X
X
X
L
H
H
L
Dout
A-1
Byte read
L
H
High-Z
A-1
Output disable
Note 2. H: VIH L:VIL X: VIH or VIL
3. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
48-ball FBGA type equals BYTE#=H mode.
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Symbol
VCC
Value
unit
V
-0.5 to +4.6
-0.5*4 to VCC+0.3*5
0.7
VT
V
PT
W
°C
°C
°C
Operation temperature
Topr
Tstg
Tbias
-40 to +85
Storage temperature range
-65 to +150
-40 to +85
Storage temperature range under bias
Note 4. -2.0V for pulse ≤ 30ns (full width at half maximum)
5. Maximum voltage is +4.6V.
DC Operating Conditions
Parameter
Supply voltage
Symbol
VCC
Min.
2.7
Typ.
3.0
Max.
3.6
Unit
Note
V
V
VSS
VIH
VIL
Ta
0
0
─
─
─
0
VCC+0.3
0.6
Input high voltage
2.2
-0.3
-40
V
Input low voltage
V
6
Ambient temperature range
+85
°C
Note 6. -2.0V for pulse ≤ 30ns (full width at half maximum)
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RMLV1616A Series
DC Characteristics
Parameter
Symbol
| ILI |
Min.
Typ.
Max.
1
Unit
Test conditions*7
Vin = VSS to VCC
Input leakage current
Output leakage current
─
─
A
CS1# = VIH or CS2 = VIL or OE# = VIH
or WE# = VIL or LB# = UB# = VIH,
VI/O = VSS to VCC
| ILO
|
─
─
─
─
1
30
4
A
Average operating current
Cycle = 55ns, duty =100%, II/O = 0mA,
CS1# = VIL, CS2 = VIH, Others = VIH/VIL
ICC1
23*8
1.6*8
mA
Cycle = 1s, duty =100%, II/O = 0mA,
ICC2
ISB
mA CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
Standby current
Standby current
─
─
─
0.3
3
mA CS2 = VIL, Others = VSS to VCC
0.5*8
A
A
A
A
~+25°C
~+40°C
~+70°C
Vin = VSS to VCC,
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
─
─
─
0.8*9
2.5*10
5*11
5
ISB1
12
16
~+85°C
CS2 ≥ VCC-0.2V
Output high voltage
Output low voltage
VOH
VOH2
VOL
2.4
─
─
─
─
─
─
V
V
V
V
IOH = -1mA
Vcc - 0.2
IOH = -0.1mA
IOL = 2mA
─
─
0.4
0.2
VOL2
IOL = 0.1mA
Note 7. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
8. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
9. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
10. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested.
11. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested.
Capacitance
(Ta =25°C, f =1MHz)
Parameter
Input capacitance
Input / output capacitance
Symbol
C in
Min.
─
Typ.
─
Max.
8
Unit
pF
Test conditions
Vin =0V
Note
12
C I/O
─
─
10
pF
VI/O =0V
12
Note 12. This parameter is sampled and not 100% tested.
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RMLV1616A Series
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
1.4V
Input pulse levels:
VIL = 0.4V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
RL = 500 ohm
DQ
CL = 30 pF
Read Cycle
Parameter
Symbol
Min.
Max.
Unit
Note
Read cycle time
tRC
tAA
55
─
─
─
─
10
─
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
55
45
45
22
─
tACS1
tACS2
tOE
Chip select access time
Output enable to output valid
Output hold from address change
LB#, UB# access time
tOH
tBA
45
─
tCLZ1
tCLZ2
tBLZ
tOLZ
tCHZ1
tCHZ2
tBHZ
tOHZ
13,14
13,14
Chip select to output in low-Z
─
LB#, UB# enable to low-Z
─
13,14
Output enable to output in low-Z
5
─
13,14
0
18
18
18
18
13,14,15
13,14,15
13,14,15
13,14,15
Chip deselect to output in high-Z
0
LB#, UB# disable to high-Z
0
Output disable to output in high-Z
0
Note 13. This parameter is sampled and not 100% tested.
14 At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is
less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
15. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
R10DS0258EJ0100 Rev.1.00
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RMLV1616A Series
Write Cycle
Parameter
Symbol
Min.
Max.
Unit
Note
16
Write cycle time
tWC
tAW
tCW
tWP
tBW
tAS
55
35
35
35
35
0
─
─
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to write end
Chip select to write end
─
Write pulse width
─
LB#,UB# valid to write end
Address setup time to write start
Write recovery time from write end
Data to write time overlap
Data hold from write end
Output enable from write end
Output disable to output in high-Z
Write to output in high-Z
─
─
tWR
tDW
tDH
0
─
25
0
─
─
tOW
tOHZ
tWHZ
5
─
17
0
18
18
17,18
17,18
0
Note 16. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
17. This parameter is sampled and not 100% tested.
18. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
BYTE# Timing Conditions (BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types)
Parameter
Byte setup time
Symbol
Min.
Max.
Unit
Note
tBS
tBR
5
5
-
-
ms
ms
Byte recovery time
BYTE# Timing Waveforms
CS1#
CS2
tBS
tBR
BYTE#
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RMLV1616A Series
Timing Waveforms
Read Cycle*19
tRC
A0~19
(Word Mode)
Valid address
A -1~19
(Byte Mode)
tAA
tACS1
CS1#
*21,22
*20,21,22
tCLZ1
tCHZ1
CS2
tACS2
*20,21,22
*21,22
tCLZ2
tCHZ2
tBA
LB#,UB#
*20,21,22
*21,22
tBLZ
tBHZ
VIH
WE#
WE# = “H” level
*20,21,22
tOHZ
tOE
OE#
*21,22
tOLZ
tOH
DQ0~15
(Word Mode)
DQ0~7
High impedance
Valid Data
(Byte Mode)
Note 19. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
20. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
21. This parameter is sampled and not 100% tested.
22. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is
less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
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Page 8 of 14
RMLV1616A Series
Write Cycle (1)*23 (WE# CLOCK, OE#=”H” while writing)
tWC
A0~19
(Word Mode)
Valid address
A -1~19
(Byte Mode)
tCW
CS1#
CS2
tCW
tBW
LB#,UB#
tAW
tWR
*24
tWP
WE#
OE#
tAS
*25,26
tWHZ
*25,26
tOHZ
tDW
tDH
DQ0~15
(Word Mode)
DQ0~7
Valid Data
*27
(Byte Mode)
Note 23. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
24. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
25. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
26. This parameter is sampled and not 100% tested.
27. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
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RMLV1616A Series
Write Cycle (2)*28 (WE# CLOCK, OE# Low Fixed)
tWC
A0~19
(Word Mode)
Valid address
A -1~19
(Byte Mode)
tCW
CS1#
CS2
tCW
tBW
LB#,UB#
tAW
tWR
*29
tWP
WE#
tAS
OE#
VIL
OE# = “L” level
*30,31
tWHZ
tOW
DQ0~15
(Word Mode)
DQ0~7
*32
Valid Data
tDH
*32
(Byte Mode)
tDW
Note 28. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
29. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
30. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ
levels.
31. This parameter is sampled and not 100% tested.
32. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
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RMLV1616A Series
Write Cycle (3)*33 (CS1#, CS2 CLOCK)
tWC
A0~19
(Word Mode)
Valid address
A -1~19
(Byte Mode)
tAW
tAS
tWR
tCW
CS1#
tAS
tCW
CS2
tBW
LB#,UB#
WE#
*34
tWP
OE#
OE# = “H” level
VIH
tDW
tDH
DQ0~15
(Word Mode)
DQ0~7
Valid Data
(Byte Mode)
Note 33. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
34. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
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RMLV1616A Series
Write Cycle (4)*35 (LB#, UB# CLOCK, Word Mode)
tWC
A0~19
(Word Mode)
Valid address
tAW
tCW
CS1#
tCW
CS2
tWR
tBW
tAS
LB#,UB#
*36
tWP
WE#
OE#
OE# = “H” level
VIH
tDH
Valid Data
tDW
DQ0~15
(Word Mode)
Note 35. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode)
36. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
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RMLV1616A Series
Low VCC Data Retention Characteristics
Parameter
Symbol
Min.
1.5
Typ. Max.
Unit
V
Test conditions*37,38
Vin ≥ 0V
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
VCC for data retention
VDR
─
3.6
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V
─
─
─
─
0.5*39
0.8*40
2.5*41
5*42
3
5
A
A
A
A
~+25°C
VCC = 3.0V, Vin ≥ 0V
(1) CS2 ≤ 0.2V or
~+40°C
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
Data retention current
ICCDR
(3) LB# = UB# ≥ VCC-0.2V,
12
16
~+70°C
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
~+85°C
Chip deselect time to data retention
Operation recovery time
tCDR
tR
0
5
─
─
─
─
ns
See retention waveform.
ms
Note 37. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
38. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer.
If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, DQ) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V.
The other inputs levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high-impedance state.
39. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
40. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
41. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested.
42. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested.
R10DS0258EJ0100 Rev.1.00
2016.01.06
Page 13 of 14
RMLV1616A Series
Low Vcc Data Retention Timing Waveforms (CS1# controlled)*43
CS1# Controlled
VCC
2.7V
2.7V
tCDR
tR
VDR
2.4V
2.4V
CS1# ≥ VCC - 0.2V
CS1#
Low Vcc Data Retention Timing Waveforms (CS2 controlled)*43
CS2 Controlled
VCC
2.7V
2.7V
tCDR
tR
CS2
VDR
0.4V
0.4V
CS2 ≤ 0.2V
Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled, Word Mode)*44
LB#,UB# Controlled
VCC
2.7V
2.7V
tR
tCDR
VDR
2.4V
2.4V
LB#,UB# ≥ VCC - 0.2V
LB#,UB#
Note 43. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V
44. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode)
R10DS0258EJ0100 Rev.1.00
2016.01.06
Page 14 of 14
Revision History
RMLV1616A Series Data Sheet
Description
Summary
Rev.
1.00
Date
Page
2016.01.06
─
First Edition issued
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