RNA51A26FLP [RENESAS]
CMOS system.RESET IC; CMOS system.RESET IC
| 型号： | RNA51A26FLP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CMOS system.RESET IC |
| 文件： | 总12页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RNA51xx Series
CMOS system–RESET IC
REJ03D0505-0300
Rev.3.00
Oct 10, 2008
General Description
The RNA51xx series provide system reset signal for microprocessor and electrical systems.
Threshold voltage is 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V and accuracy is ±1.0%.
The reset output delay time can be set by external capacitor connected to CD pin.
Manual reset input is available and input resistance is 2 MΩ typ.
This series have two output types (active-low CMOS output and active-low open-drain output).
Features
•
•
•
•
•
•
•
•
•
•
Threshold voltage: 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V
Threshold voltage accuracy: ±1.0%
Threshold voltage hysteresis: 5% typ.
Low supply current: 0.7 µA typ.
Capacitor-adjustable output delay time
Manual reset
VOUT CMOS output, or open-drain output
5-pin SOT-23 package
Temperature range: –40°C to 85°C
Ordering Information
Taping Abbreviation
(Quantity)
Package
Abbreviation
Part Name
Package Type
Package Code
RNA51A26FLPEL
RNA51A27FLPEL
RNA51A28FLPEL
RNA51A29FLPEL
RNA51A30FLPEL
RNA51A31FLPEL
RNA51A44FLPEL
RNA51A45FLPEL
RNA51A46FLPEL
RNA51B14FLPEL
RNA51B27FLPEL
RNA51B50FLPEL
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
Applications
•
•
•
•
•
Power supply voltage monitoring for microprocessors
Battery-powered portable equipment
Computers and notebook computers
Wireless Communication Systems
Digital still camera, digital video camera, PDA
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 1 of 11
RNA51xx Series
Pin Arrangement
VOUT
VDD
1
2
3
5
4
CD
MR
GND
(Top view)
Product list
Open-Drain output
Type No. Marking
CMOS output
Type No.
Threshold Voltage –VTH
[V]
Marking
6P
—
1.4
2.6
2.7
2.8
2.9
3.0
3.1
4.4
4.5
4.6
5.0
—
—
5N
5P
5Q
5R
5S
5T
6G
6H
6J
RNA51B14FLP
RNA51A26FLP
RNA51A27FLP
RNA51A28FLP
RNA51A29FLP
RNA51A30FLP
RNA51A31FLP
RNA51A44FLP
RNA51A45FLP
RNA51A46FLP
—
—
RNA51B27FLP
7C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RNA51B50FLP
3R
Outline and Article Indication
• RNA51A26FLP (Example)
Marking
Control Code
5 N
MPAK-5
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 2 of 11
RNA51xx Series
Functional block diagram & typical application circuit
(1) RNA51Axx Products
Power
supply
MR
4
Power
supply
2
VDD
VOUT
delay
RESET
1
Microprocessor
Vref
GND
3
5
CD
(2) RNA51Bxx Products
Power
supply
MR
4
2
VDD
VOUT
delay
RESET
1
Microprocessor
Vref
GND
3
5
CD
Notes: 1. It is good for stable operation to use a decoupling capacitor with excellent high frequency characteristics
between VDD and GND pin.
2. Capacitor value is determined by system conditions.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 3 of 11
RNA51xx Series
Timing Diagram
VHYS
VTH
VDD
MR
tDLY
tDLY
tDLY
VOUT
Absolute Maximum Ratings
(1) RNA51Axx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Symbol
VDD
Pin
Ratings
6.0
Unit
V
VDD
Output voltage
VOUT
VIN
VOUT
MR, MD
VOUT
—
–0.3 to 6.0
–0.3 to VDD+0.3
±50
V
Input voltage
V
Output current
IOUT
mA
mW
°C
°C
Continuous power dissipation
Operating temperature range
Storage temperature range
PD
120
TOPR
TSTG
—
–40 to +85
–55 to +125
—
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Symbol
VDD
Pin
VDD
Ratings
Unit
V
6.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
±50
Output voltage
VOUT
VIN
VOUT
MR, MD
VOUT
—
V
Input voltage
V
Output current
IOUT
mA
mW
°C
°C
Continuous power dissipation
Operating temperature range
Storage temperature range
PD
120
TOPR
TSTG
—
–40 to +85
–55 to +125
—
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 4 of 11
RNA51xx Series
Electrical characteristics
(1) RNA51Axx Products
Temperature condition Ta = 25°C
Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
1.1
5.5
V
pull-up resistor = 470 kΩ
V
OUT ≤ 0.1×VDD
Supply current
IDD
0.7
4.2
µA
VDD = 5.5 V
Threshold voltage
–VTH
–VTH×0.99
–VTH×1.01
V
Temperature coefficiency of the
thereshold voltage
∆(–VTH
–VTH ∆Ta
)
±100
ppm/ Ta = –40 to 85°C
°C
(Reference value)
Threshold voltage hysteresis
VHYS
IOL
–VTH×3%
0.2
–VTH×5%
1.2
–VTH×8%
V
mA
VOUT = 0.5 V
VDD = 1.3 V
VOUT low-level output current
3.4
7.0
VDD = 2.4 V
(–VTH ≥ 2.7 V)
ILEAK
tDLY
0.1
35
µA
VDD = VOUT = 5.5 V
VOUT Output leakage current
(open drain output)
Delay time Note1
10
20
2
ms
VDD = 1.1 to 5.5V, tTLH = 1 µs
CD = 4.7 nF
MR Low-level input voltage Note2
MR High-level input voltage
MR internal pull-up resistance
VIL
VIH
V
DD×0.25
V
V
V
DD×0.75
RMR
1
7
MΩ
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
1.1
5.5
V
pull-up resistor = 470 kΩ
V
OUT ≤ 0.1×VDD
Supply current
IDD
0.7
4.2
µA
VDD = 5.5 V
Threshold voltage
–VTH
–VTH×0.99
–VTH×1.01
V
Threshold voltage
temperature dependency
(Reference value for design)
∆(–VTH
–VTH ∆Ta
)
±100
ppm/ Ta = –40 to 85°C
°C
Threshold voltage hysteresis
VHYS
IOL
–VTH×3%
0.2
–VTH×5%
1.2
–VTH×8%
V
mA
mA
ms
VOUT = 0.5 V
VDD = 1.3 V
VOUT low-level output current
3.4
7.0
VDD = 2.4 V
(–VTH ≥ 2.7 V)
IOH
–1.4
–2.7
VOUT
=
VDD = 4.5 V
VOUT High-level output current
V
DD–0.5 V
(–VTH ≤ 4.0 V)
(CMOS output)
–1.5
10
–3.0
20
VDD = 5.5 V
Delay time Note1
tDLY
35
VDD = 1.1 to 5.5 V, tTLH = 1 µs
CD = 4.7 nF
MR Low-level input voltage Note2
MR High-level input voltage
MR internal pull-up resistance
VIL
VIH
V
DD×0.25
V
V
V
DD×0.75
RMR
1
2
7
MΩ
Note:
1. Delay time is specified when charging starts in the condition that CD pin is completely discharged. When discharging of CD
pin is not complete because of immediate stop and other reasons, the delay time is not guaranteed. Therefore, when
passing of VDD pin input voltage immediately stops (the period of condition that VDD pin input voltage is lower than the
detected voltage is short), discharging of external capacitor CD is inadequate, and the delay time becomes much shorter
than the minimum guaranteed value. Be sure to fully check that there are no problems as the system.
2. Minimum value of low-pulse width to be input to MR pin depends on the value of external capacitor CD. Therefore, set the
low-pulse width to be input to MR pin to the minimum input low-pulse width shown in figure 1 or more.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 5 of 11
RNA51xx Series
1000
100
10
1
0.1
1
10
100
1000
External Capacitor CD (nF)
Figure 1 Dependence of MR pin minimum input low pulse width and external capacitor CD
Pin Description
PIN
NAME
FUNCTION
1
VOUT VOUT changes from high to low whenever VDD drops below –VTH
.
A pull-up resistor from 470 kΩ to 1 MΩ should be used on this pin for open-drain output.
2
VDD
Supply voltage and input for voltage detector.
A decoupling capacitor with excellent high frequency characteristics should be placed near VDD
pin and connected between VDD and GND pin.
3
4
GND
MR
Ground
Active-low Manual Reset Input. VOUT is low-level while MR is low.
Once MR is disabling, VOUT turn to high-level after delay time.
MR pin is internally pulled up to VDD through 2 MΩ.
5
CD
Connect capacitor between CD and GND pin to set programmable delay time.
Ceramic capacitor from 100 pF to 0.1 µF is recommended.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 6 of 11
RNA51xx Series
Test Circuit
(1) RNA51Axx Products
Minimum Supply voltage VDDmin
Threshold voltage and Hysteresis VTH & VHYS
1 VOUT CD
5
4
1 VOUT CD
2 VDD
5
4
470 k
0.0 V
5.5 V
4.7 nF
470 k
5.5 V
4.7 nF
2 VDD
0.0 V
5.5 V
3 GND MR
3 GND MR
–VTH x 3% ≤ VHYS ≤ –VTH x 8%
VOUT = VDD
VHYS
VOUT = VDD
VOUT = 0.1 x VDD
VDD
VDD
0
0
Minimum Supply voltage
–VTH : Reset asserted voltage
+VTH : Reset released voltage
Minimum Supply voltage: VOUT = 0.1 x VDD ≤ 1.1 V
Supply current IDD
Output leakage current ILEAK
ILEAK
1 VOUT CD
2 VDD
5
4
A
1 VOUT CD
5
4
IDD
A
470 k
5.5 V
4.7 nF
2 VDD
4.7 nF
5.5 V
3 GND MR
3 GND MR
Low-level output current IOL
MR internal pull-up resistance RMR
1 VOUT CD
2 VDD
5
4
IOL
A
1 VOUT CD
5
4
470 k
4.7 nF
2 VDD
4.7 nF
0.5 V
3 GND MR
1.3 V
or
2.4 V
–VTH +1
3 GND MR
A
IMR
–VTH +1
RMR
=
IMR
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 7 of 11
RNA51xx Series
Test Circuit (Cont.)
(1) RNA51Axx Products
Delay time tDLY
MR input voltage VIL & VIH
1 VOUT CD
2 VDD
5
4
1 VOUT CD
2 VDD
5
4
470 k
1.1 V
5.5 V
4.7 nF
470 k
4.7 nF
3 GND MR
3 GND MR
0 V
VDD
VDD
1 µs
5.5 V
5.5 V
0.25 x VDD < VLTH < 0.75 x VDD
+VTH
VDD
VDD
1.1 V
0 V
tDLY
VIL
VIH
VMR
0
2.75 V
VOUT
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 8 of 11
RNA51xx Series
Test Circuit (Cont.)
(2) RNA51Bxx Products
Minimum Supply voltage VDDmin
Threshold voltage and Hysteresis VTH & VHYS
1 VOUT CD
5
4
1 VOUT CD
2 VDD
5
4
470 k
0.0 V
5.5 V
4.7 nF
4.7 nF
5.5 V
0.0 V
5.5 V
2 VDD
3 GND MR
3 GND MR
–VTH x 3% ≤ VHYS ≤ –VTH x 8%
V
OUT=VDD
VHYS
VOUT = VDD
VOUT = 0.1 x VDD
VDD
VDD
0
0
Minimum Supply voltage
–VTH : Reset asserted voltage
+VTH : Reset released voltage
Minimum Supply voltage: VOUT = 0.1 x VDD ≤ 1.1 V
Supply current IDD
High-level output current IOH
IOH
1 VOUT CD
2 VDD
5
4
A
1 VOUT CD
2 VDD
5
4
0.5 V
IDD
A
4.7 nF
4.7 nF
4.5 V
or
5.5 V
5.5 V
3 GND MR
3 GND MR
Low-level output current IOL
MR internal pull-up resistance RMR
1 VOUT CD
2 VDD
5
4
IOL
A
1 VOUT CD
5
4
4.7 nF
2 VDD
4.7 nF
0.5 V
3 GND MR
1.3 V
or
2.4 V
–VTH +1
3 GND MR
A
IMR
–VTH +1
RMR
=
IMR
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 9 of 11
RNA51xx Series
Test Circuit (Cont.)
(2) RNA51Bxx Products
Delay time tDLY
MR input voltage VIL & VIH
1 VOUT CD
2 VDD
5
4
1 VOUT CD
2 VDD
5
4
4.7 nF
4.7 nF
1.1 V
5.5 V
3 GND MR
3 GND MR
0 V
VDD
VDD
1 µs
5.5 V
5.5 V
0.25 x VDD < VLTH < 0.75 x VDD
VDD
+VTH
VDD
1.1 V
0 V
tDLY
V
IL
VIH
VMR
0
2.75 V
VOUT
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 10 of 11
RNA51xx Series
Delay Time Graph
Delay Time vs. External Capacitor
1000
100
10
1
0.1
0.1
1
10
100
1000
External Capacitor CD (nF)
Note: This graph shows simulation results.
Package Dimensions
Package Name
MPAK-5
JEITA Package Code
SC-74A
RENESAS Code
PLSP0005ZB-A
Previous Code
MASS[Typ.]
0.015g
MPAK-5 / MPAK-5V
D
A
e
Q
c
E
HE
L
P
L
L
1
A
3
Dimension in Millimeters
Reference
Symbol
A
A
Min
1.0
0
Nom Max
b
x
S
A
M
A
A1
A2
A3
b
c
D
E
1.4
0.1
1.3
e
1.0
1.1
0.25
0.4
0.35
0.11
2.8
0.5
0.16 0.26
A
A
2
1
A
2.95
1.6
3.1
1.8
1.5
e
HE
L
L1
LP
x
0.95
2.8
e
1
y
S
2.5
0.3
0.1
0.2
3.0
0.7
0.5
0.6
S
b
0.05
0.05
0.55
I1
y
b2
e1
I1
c
b
2
2.15
0.3
0.85
A-A Section
Pattern of terminal position areas
Q
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 11 of 11
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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and regulations, and procedures required by such laws and regulations.
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