RNA52A10TH5 [RENESAS]
SPECIALTY ANALOG CIRCUIT;
| 型号： | RNA52A10TH5 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY ANALOG CIRCUIT 光电二极管 |
| 文件： | 总12页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
RNA52A10T
Descriptive Title
Description
R03DS0078EJ0100
Rev.1.00
Dec 06, 2013
The RNA52A10T incorporates two reset circuits, one with and one without a delay function, allowing the generation of
separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is
determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the
RNA52A10T means that the device draws only 1.1 μA (typ.). The reset cancellation delay time is set with a high
degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input
pin is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on
the MR input pin. The MR pin is pulled down by a 2-MΩ internal resistor. Output pins Vo1 and Vo2 are open drain.
Features
•
•
•
•
•
•
•
•
•
•
•
Two CMOS reset circuits, one with and one without the delay function
Reference voltage: 1.0 V
Reference voltage accuracy: ± 50 mV
Reference voltage hysteresis: 6% (typ.)
Low current consumption: 1.1 μA (typ.)
Delay time set by an external CR circuit
Manual reset input
Open-drain output
TSSOP-8 (8-pin) package
Operating temperature range: – 40 to 85°C
Ordering Information
Package
Abbreviation
Taping Abbreviation
(Quantity)
Surface
Treatment
Part Name
Package Type
Package Code
RNA52A10TH5
TSSOP-8 pin
PTSP0008JC-B
T
H (3,000 pcs / Reel)
5 (Ni/Pd/Au)
Application
•
•
•
•
•
•
•
Power-supply monitoring and resetting for microprocessors
Power supply sequence control for microprocessors
Desktop and laptop PCs
PC peripheral devices such as printers
Digital still cameras, digital video cameras, and PDAs
Battery-driven products
Wireless communications systems
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 1 of 11
RNA52A10T
Pin Arrangement
VDD 1
Vi1 2
Vi2 3
CD 4
8 MR
7
6
Vo1
Vo2
5 GND
(Top view)
Outline and Article Indication
• RNA52A10T
Marking
R52A
YMW
Index mark
Y : Year code
(the last digit of year)
M : Month code
W : Week code
TSSOP-8
Lot No.
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 2 of 11
RNA52A10T
Functional Block Diagram and Typical application Circuit
V
V
DD3
R
R
L1
V
DD1
Vo1
Vo2
R
R
S1
S2
Reset circuit 1
Vi1
7
6
2
DD4
L2
V
DD2
Reset circuit 2
RESET
R
R
S3
S4
Vi2
Micro-
computer
3
V
REF
1.0V
2M
VDD
MR
CD
GND
1
8
4
5
C
C
D
R
D
V
DD0
1
Notes: 1. Please refer to the following equations to set up reset-threshold voltages for power supplies VDD1 and VDD2
and to set up external voltage-dividing resistor pairs RS1 and RS2, and RS3 and RS4.
(1) VDD1 reset-threshold voltage = VREF × (RS1+RS2)/RS2
,
(2) VDD2 reset-threshold voltage = VREF × (RS3+RS4)/RS4
Note that values must be set up within the following range: RS1, RS2, RS3, RS4 ≤ 50 kΩ
See the following graph for the relationship between the reference voltage variation and the value selected for
RS1, RS2, RS3 and RS4.
2. For capacitor C1, select a type which has excellent frequency characteristics. For stable operation, place it
between the VDD pin and the GND pin and as close as is possible to the chip.
3. The value of capacitor C1 must suit the system environment in terms of the quality of the power supply and so
forth.
Reference Voltage Variation vs. Parallel Resistance
5
4
3
2
1
0
-1
0.1
1
10
100
1000
Parallel Resistance (RS1//RS2, RS3//RS4) [kΩ]
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 3 of 11
RNA52A10T
Timing Diagram
1. I/O Table
MR
L
Vi1, Vi2
VREF
Vo1
L
Vo2
L
H (after TDLY0
)
(VREF+VHYS
)
H
VREF
L
H
L
(VREF+VHYS
)
H
2. Timing Chart
(VREF+VHYS
)
(VREF+VHYS
)
VREF
Vi1, Vi2
MR
VDD0
VDD3
VDD4
Vo1
Vo2
TDLY0
TDLY0
TDLY0
Absolute Maximum Ratings
Item
Symbol
VDD
Ratings
6.0
Unit
V
Supply voltage (VDD)
Input voltage (Vi1, Vi2, MR, CD)
Output voltage (Vo1, Vo2)
Output current (Vo1, Vo2)
Continuous power dissipation
Operating temperature
Storage temperature
VIN
–0.3 to VDD
–0.3 to 6.0
30
V
VOUT
IOUT
V
mA
mW
°C
°C
PT
192
TOPR
TSTG
–40 to 85
–55 to 125
Note: Ta ≤ 25°C, If Ta > 25°C, derate by 1.92 mW/°C (see figure on page 6)
Recommended Operating Conditions
Item
Symbol
VDD
Min.
1.4
0
Max.
5.5
VDD
5.5
15
Unit
Supply voltage (VDD)
V
V
Input voltage (Vi1, Vi2, MR, CD)
Output voltage (Vo1, Vo2)
Output current (Vo1, Vo2)
Operating temperature
VIN
VOUT
IOUT
0
V
0
mA
°C
TOPR
–40
85
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 4 of 11
RNA52A10T
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
Test
Test Conditions
Circuit
Item
Supply voltage
Symbol
VDD
IDD
Min.
1.4
Typ.
—
Max.
5.5
Unit
V
—
V
DD = 5.5 V
Current consumption
—
1.1
19
μA
1
2
Vi1 = V i2 = 5.5 V
VDD = 3.3 V
Reference voltage
VREF
0.95
1.00
1.05
V
Reference voltage temperature
coefficient
ΔVREF
VREF ⋅ΔTa
ppm
°C
—
±100
—
Ta = –40 to 85°C
2
(Reference value for design)
Vi1, Vi2 input
28.5
60
94.5
VHYS
IIN
mV
μA
V
V
V
DD = 3.3 V
DD = 5.5 V
2
3
4
hysteresis voltage
(VREF×3%)
(VREF×6%)
(VREF×9%)
Vi1, Vi2 input current
—
0.6
2.2
Vi1 = V i2 = 5.5 V
DD = 3.3 V
Vi1 = V i2 = 1.2 V
DD = 1.4V
V
CD input threshold voltage
VDLY
VDD×0.43
VDD×0.63
VDD×0.83
V
—
0.05
0.15
V
Vi1 = V i2 = 0 V
IOL = 0.5 mA
5
Vo1, Vo2
low-level output voltage
VOL
V
DD = 3.3V
—
—
0.15
—
0.35
100
17
V
Vi1 = V i2 = 0 V
IOL = 5 mA
6
7
8
V
DD = VO1 = VO2 = 5.5 V
Vo1, Vo2
output leakage current
ILK
nA
ms
Vi1 = V i2 = 1.2 V
Incomplete
discharge of
TDLY
1.1
11
VDD = 3.3 V
capacity CD
Vo2
Vi2 = 0 V→1.2 V
CD = 0.3 μF, RD = 39 kΩ
Delay time Note1
complete
discharge of
capacity CD
TDLY0
7
11
30
17
ms
8
9
V
DD = 3.3 V
Vi1 = 0 V→1.2 V
DD = 3.3 V
Vo1
TPLH
—
300
μs
Rise response time
V
Vo1, Vo2
fall response time
TPHL
—
30
800
μs
Vi1 = Vi2 = 1.2 V→0 V
CD = 0.3 μF, RD = 39 kΩ
10
V
DD = 3.3 V
Vi1 = V i2 = 1.2 V
DD = 3.3 V
Vi1 = V i2 = 1.2 V
DD = 5.0 V
Vi1 = V i2 = 1.2 V
DD = 5.5 V
VMR = 5.5 V
MR low-level input voltage
VIL
—
—
—
—
2
VDD×0.2
V
V
11
11
12
13
V
V
DD < 4.5V
VDD×0.75
VDD×0.5
0.5
—
—
—
MR high-level
input voltage
VIH
V
VDD ≥ 4.5V
V
V
MR input
RMR
MΩ
pull-down resistance
Notes: 1. When capacitor CD is completely discharged and charging starts in the state that CD pin voltage is 0 V, the
minimum value of delay time TDLY0 is 7 ms. However, when the discharging time is short and charging starts
in the state that the voltage does not completely fall to 0 V, the minimum value of delay time TDLY is 1.1 ms.
Then, the minimum value of Low time (reset time) of Vo2 is 1.1 ms as the delay time TDLY. Refer to
Regulations for state of capacitor CD electrical discharge and delay time on page 10 for details.
2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.
3. Refer to pages 8 and 9 for the test circuits.
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 5 of 11
RNA52A10T
Characteristic curves
Current Dissipation IDD
200
150
100
50
20
15
10
5
VDD = 5.5 V, Vi1 = Vi2 = 5.5 V
0
0
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
Ambient Temperature Ta [°C]
Ambient Temperature Ta [°C]
Reference voltage VREF
Vi1, Vi2 Input Current I
IN
1.04
1.02
1.00
0.98
0.96
2.0
1.5
1.0
0.5
0.0
VDD = 3.3 V
VDD = 5.5 V, Vi1 = Vi2 = 5.5 V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Ambient Temperature Ta [°C]
Ambient Temperature Ta [°C]
Vo1, Vo2 Low-level output voltage VOL
Delay time TDLY0
0.4
0.3
0.2
0.1
0
20
15
10
5
VDD = 3.3 V, Vi2 = 0 to 1.2 V
CD = 0.3 μF, RD = 39 kΩ
VDD = 3.3 V, IOL = 5 mA
VDD = 1.4 V, IOL = 0.5 mA
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Ambient Temperature Ta [°C]
Ambient Temperature Ta [°C]
Rise Response Time TPLH
Fall Response Time TPHL
1000
100
10
1000
VDD = 3.3 V, Vi1 = Vi2 = 1.2 to 0 V
CD = 0.3 μF, RD = 39 KΩ
100
10
1
Vi2
Vi1
VDD = 3.3 V, Vi1 = 0 to 1.2 V
1
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Ambient Temperature Ta [°C]
Ambient Temperature Ta [°C]
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 6 of 11
RNA52A10T
Pin Descriptions
Pin No. Pin Name
Function
Power-supply pin for the chip. For stable operation, select a capacitor with superior frequency characteristics
and connect it between the VDD and GND pins and as close to the chip as possible. When selecting the value
of the capacitor, consider aspects of the system environment such as the quality of the power supply. Refer to
the block diagram and typical application circuit on page 3 for details.
1
2
VDD
Voltage input pin for reset circuit 1 (the circuit without the delay function). When the input voltage falls to or
below VREF, the signal output from the Vo1 pin is changed to the low level. Since the input characteristic
includes hysteresis, the signal output from the Vo1 pin is changed from the low to the high level after the
voltage input on pin Vi1 has risen to or above VREF+VHYS. The reset-threshold voltage is derived from the
power-supply voltage VDD1 according to the division ratio set up by resistors RS1 and RS2 as described under the
block diagram and typical application circuit on page 3. To avoid shifting of the reset detection voltage being
shifted by input current via the Vi1 pin, select a value no greater than 25 kΩ for parallel resistors RS1 and RS2.
Vi1
Refer to the graph on page 3 for details. Besides, to avoid errors due to noise in power-supply voltage VDD1
,
select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins.
Voltage input pin for reset circuit 2 (the circuit with the delay function). When the input voltage falls to or below
VREF, the signal output from the Vo2 pin is changed to the low level. Since the input characteristic includes
hysteresis, the signal output from the Vo2 pin is changed from the low to the high level after the voltage input
on pin Vi2 has risen to or above VREF+VHYS and delay time TDLY has elapsed. The reset-threshold voltage is
derived from the power-supply voltage VDD2 according to the division ratio set up by resistors RS3 and RS4 as
described under the block diagram and typical application circuit on page 3. To avoid shifting of the reset
detection voltage being shifted by input current via the Vi2 pin, select a value no greater than 25 kΩ for parallel
resistors RS3 and RS4. Refer to the graph on page 3 for details. Besides, to avoid errors due to noise in power-
supply voltage VDD2, select a capacitor with superior frequency characteristics and connect it between the Vi2
and GND pins.
3
Vi2
Pin for connection to the resistor (RD) and capacitor (CD) for setting of the delay time, TDLY0. Refer to the Block
Diagram and Typical Application Circuit on page 2 for an example of the connection. The relation by which the
resistance and capacitance set up the delay time can be expressed as TDLY0 = 0.94 × CD × RD. Refer to this
formula in determining the values of resistance and capacitance. Resistance RD must use the one within the
range of 1 k to 1 MΩ. Ensure that capacitor CD has a value no greater than 1.3 μF. The dependence of delay
time TDLY0 on the values of external capacitor CD and external resistor RD is illustrated on page 10. To avoid
errors due to noise input via the CD pin, this input includes a Schmitt-trigger inverter.
4
5
6
CD
GND
Vo2
GND pin
Reset signal output pin for reset circuit 2 (the circuit with the delay function). The output is open-drain.
The recommended value for the pull-up resistor (RL2 ) is 3 k to 100 kΩ. When the voltage input on pin Vi2 falls
to or below VREF, the signal output from the Vo2 pin is changed from the high to the low level. Since the input
characteristic includes hysteresis, the signal output from the Vo2 pin changes from the low to the high level
when the voltage input on pin Vi2 rises to or above VREF+VHYS and the set delay time TDLY0 has elapsed. Refer
to the timing diagram on page 4 and regulations for state of capacitor CD electrical discharge and delay time on
page 10 for details.
Reset signal output pin for reset circuit 1 (the circuit with no delay function). The output is open-drain.
The recommended value of the pull-up resistor (RL1) is 3 k to 100 kΩ. When the voltage input on pin Vi1 falls to
or below VREF, the signal output from the Vo1 pin is changed from the high to the low level. Since the
characteristic includes hysteresis, the signal output from the Vo1 pin changes from the low to the high level
when the voltage input on pin Vi1 rises to or above VREF+VHYS. Refer to the timing diagram on page 4 for
details.
7
8
Vo1
Manual reset input pin for reset circuit 2 (the circuit with the delay function).
The MR signal is active high, so applying a high level to MR sets the Vo2 pin to the low level.
If Vi2 > VREF when the signal on the MR pin is changed back from the high to the low level, the Vo2 pin is
returned from the low to the high level after a delay time TDLY0. This can be set as required. The MR pin is
pulled down to the GND level via an internal 2-MΩ resistor . However, we recommend connection of the pin to
the GND line when it is not in use.
MR
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 7 of 11
RNA52A10T
Test Circuits
1
2
4
6
A
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
Vi2
Vo2
Vi2
Vo2
CD
GND
V
CD
GND
3
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
A
A
Vi2
Vo2
Vi2
Vo2
CD
GND
CD
GND
V
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
V
V
Vi2
Vo2
Vi2
Vo2
CD
GND
CD
GND
V
V
7
A
A
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
Vi2
Vo2
CD
GND
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 8 of 11
RNA52A10T
Test Circuits (cont.)
8
9
1
2
3
4
VDD
MR
Vo1
8
7
6
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
Vi1
Vi2
CD
Vo2
Vi2
Vo2
GND
CD
GND
3.3 V
3.3 V
3.3 V
3.3 V
1.06 V
1.06 V
Vi2
Vi1
0 V
0 V
0 V
0 V
TDLY0
TPLH
Vo2
1.65 V
Vo1
1.65 V
10
11
1
2
3
4
VDD
MR
Vo1
8
7
6
5
Vi1
Vi2
CD
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
Vo2
GND
Vi2
Vo2
CD
GND
3.3 V
3.3 V
V
1.0 V
Vi1, Vi2
0 V
0 V
1.65V
,
Vo1 Vo2
TPHL
12
13
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
1
2
3
4
VDD
Vi1
MR
Vo1
8
7
6
5
Vi2
Vo2
Vi2
Vo2
A
CD
GND
CD
GND
V
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 9 of 11
RNA52A10T
Regulations for state of capacitor CD electrical discharge and delay time
(1) Operation to MR input signal
MR
Vth+
Vth+
Capacitor complete
electrical discharge
CD
Vth-
Vth-
Capacitor incomplete
electrical discharge
0V
TDLY
TDLY0
Vo2
(2) Operation to Vi2 input signal
VREF+VHYS
VREF+VHYS
Vi2 VREF
VREF
Vth+
Vth+
Capacitor complete
electrical discharge
CD
Vth-
Vth-
Capacitor incomplete
electrical discharge
0V
TDLY
TDLY0
Vo2
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 10 of 11
RNA52A10T
Relation between Delay Time TDLY and External Component Values CD, RD
1000
100
10
1
1
10
100
1000
Resistance RD [kΩ]
Package Dimensions
JEITA Package Code
P-TSSOP8-4.4x3-0.65
RENESAS Code
Previous Code
TTP-8DAV
MASS[Typ.]
0.034g
PTSP0008JC-B
*1 D
F
8
5
NOTE)
1. DIMENSIONS" *1 (Nom)"AND" *2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION" *3"DOES NOT
INCLUDE TRIM OFFSET.
bp
Terminal cross section
(Ni/Pd/Au plating)
Dimension in Millimeters
Min Nom Max
3.00 3.30
Reference
Symbol
Index mark
D
E
4.40
L1
A2
A1
A
0.03 0.07 0.10
1.10
0.15 0.20 0.25
1
4
*3
bp
bp
b1
c
e
Z
x
M
0.10 0.15 0.20
c1
θ
HE
e
0°
8°
L
6.20 6.40 6.60
S
0.65
0.13
Detail F
x
y
0.10
Z
L
L1
0.805
0.40 0.50 0.60
1.00
y
S
R03DS0078EJ0100 Rev.1.00
Dec 06, 2013
Page 11 of 11
Notice
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contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 LanGao Rd., Putuo District, Shanghai, China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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