UPD16F15GC-8BT [RENESAS]
MICROCONTROLLER, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80;
| 型号： | UPD16F15GC-8BT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | MICROCONTROLLER, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80 外围集成电路 |
| 文件： | 总389页 (文件大小：1969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary User’s Manual
µPD1615, µPD16F15,
µPD1616
8-bit Single-Chip Microcontroller
Hardware
Document No. U13635EE1V0UM00
Date Published March 1999
© NEC Corporation 1999
µPD1615, µPD16F15, µPD1616
FIP is a trademark of NEC Corporation
EEPROM and IEBus are trademarks of NEC Corporation.
MS-DOS and MS-Windows are either registered trademarks or trademarks of Microsoft
Corporation in the United States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corp.
IBM-DOS, PC/ATandPCDOSaretrademarksofInternationalBusinessMachinesCorporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of Xerox Corp.
NEWS and NEWS-OS are trademarks of Sony Corporation.
OSF/Motif is a trade mark of OpenSoftware Foundation, Inc..
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The related documents in this publication may include preliminary versions. However, prelimi-
nary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this
product may be prohibited without governmental license, the need for which must be judged by the
customer. The export or re-export of this product from a country other than Japan may also be
prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear
in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor
devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to
persons or property arising from a defect in an NEC semiconductor device, customer must incorporate
sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based
on a customer designated “quality assurance program“ for a specific application. The recommended
applications of a device depend on its quality grade, as indicated below. Customers must check the quality
grade of each device before using it in a particular application.
Standard:Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard“ unless otherwise specified in NEC's Data Sheets or Data
Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality
grade, they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
2
µPD71615,µPD16F15,µPD1616
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Developmentenvironmentspecifications(forexample,specificationsforthird-partytoolsandcomponents,
host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Fax: 02-66 75 42 99
Fax: 02-719-5951
Taeby, Sweden
Tel: 08-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 08-63 80 388
3
µPD1615, µPD16F15, µPD1616
Introduction
Readers
This manual has been prepared for user engineers who want to understand the functions of the
µPD1615 subseries and design and develop its application systems and programs.
µPD1615 Subseries: µPD1615, µPD16F15, µPD1616.
Purpose
This manual is intended for users to understand the functions described in the Organization below.
Organization
The µPD1615 subseries manual is separated into two parts: this manual and the instruction edition
(common to the 78K/0 series).
µPD1615
subseries
78K/0 series
User’s Manual
Instruction
This Manual
• Pin functions
• CPU functions
• Internal block functions
• Interrupt
• Instruction set
• Explanation of each instruction
• Other on-chip peripheral functions
How to Read This Manual
Before reading this manual, you should have general knowledge of electric and logic circuits and
microcontrollers.
• When you want to understand the function in general:
→ Read this manual in the order of the contents.
• How to interpret the register format:
→ For the bit number enclosed in square, the bit name is defined as a reserved word in the
assembler and the compiler.
• To make sure the details of the registers when you know the register name.
→ Refer to Appendix C.
4
µPD1615, µPD16F15, µPD1616
Chapter Organization
This manual devides the descriptions for the subseries into different chapters as shown below. Read
only the chapters related to the device you use.
µPD1615
¡
µPD16F15
µPD1616
Chapter
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Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Outline
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Pin Function
¡
CPU Architecture
Port Functions
¡
¡
Clock Generator
¡
16-Bit Timer/Counter
8-Bit Timer/Event Counters 50, 51
Watch Timer
¡
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Watchdog Timer
¡
Clock Output Control Circuit
A/D-Converter
¡
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Serial Interface Outline
Serial Interface Channel 30
Serial Interface UART
VAN Controller
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LCD Controller/Driver
Sound Generator
Interrupt Functions
Standby Function
Reset Function
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µPD16F15
¡
Instruction Set
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Appendix A Development Tools
Appendix B Embedded Software
Appendix C Register
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Appendix D Revision History
5
µPD1615, µPD16F15, µPD1616
RelatedDocuments
The related documents indicated in this publication may include preliminary versions. However,
preliminary versions are not marked as such.
• Related documents for µPD1615 subseries
Document No.
Document name
Japanese
—
English
U13723E
U13606E
This manual
IEU-1372
—
µPD1615 Preliminary Product Information
µPD16F15 Preliminary Product Information
µPD1615 Subseries User’s Manual
78K/0 Series User’s Manual-Instruction
78K/0 Series Instruction Table
—
—
IEU-849
U10903J
U10904J
—
78K/0 Series Instruction Set
U12326E
—
µPD1615 Subseries Special Function Register Table
• Related documents for development tool (User's Manuals)
Document No.
Document name
Japanese
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
U11517J
U11518J
EEA-618
EEU-777
U10057J
—
English
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
—
RA78K Series Assembler Package
Operation
Language
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
Operation
Language
CC78K/0 C Compiler
Operation
Language
—
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
IE-78001-R-A
Programming Note
EEA-1208
—
U10057E
U13359E
IE-78K0-NS-P04
IE-1615-NS-EM4
IE-78K0-R-EX1
SUD-3677
TEMPR-2093
U10181J
SUD-3677
U10181E
U10092E
—
EP-78230GC-12
—
Reference
SM78K0 System Simulator Windows™ Base
SM78K0 Series System Simulator
ID78K0 Integrated Debugger EWS Base
ID78K0 Integrated Debugger PC Base
ID78K0 Integrated Debugger Windows Base
External part user open Interface
Reference
U10092J
U11151J
U11539E
U11649E
Reference
U11539J
Guide
U11649J
6
µPD1615, µPD16F15, µPD1616
• Related documents for embedded software (User’s Manual)
Document No.
Document name
Basics
Japanese
English
—
78K/0 Series Real-Time OS
U11537J
U11536J
U11538J
EEU-5010
EEU-829
EEU-862
EEU-858
EEU-921
Installation
Technicals
Basics
—
—
78K/0 Series OS MX78K0
—
Fuzzy Knowledge Data Creation Tool
EEU1438
EEU-1444
EEU-1441
EEU-1458
78K/0, 78IK/II, 87AD Series Fuzzy Inference Development Suppport System-Translator
78K/0 Series Fuzzy Inference Development Suppport System- Fuzzy Inference Module
78K/0 Series Fuzzy Inference Development Suppport System- Fuzzy Inference Debugger
• Other Documents
Document No.
Document name
Japanese
C10943X
C10535J
C11531J
C10983J
MEM-539
MEI-603
U11416J
English
IC Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grade on NEC Semiconductor Devices
C10535E
C11531E
C10983E
—
Reliability Quality Control on NEC Semiconductor Devices
Electric Static Discharge (ESD) Test
Semiconductor Devices Quality Assurance Guide
Microcontroller Related Product Guide - Third Party Manufacturers
MEI-1202
—
Caution: The above documents are subject to change without prior notice. Be sure to use the
latest version document when starting design.
7
µPD1615, µPD16F15, µPD1616
Table of Contents
Chapter 1 Outline ........................................................................................................... 26
1.1 Features ................................................................................................................................................ 26
1.2 Application............................................................................................................................................ 26
1.3 Ordering Information ........................................................................................................................... 26
1.4 Pin Configuration (Top View) .............................................................................................................. 27
1.5 78K/0 Series Development .................................................................................................................. 30
1.6 Block Diagram ..................................................................................................................................... 31
1.7 Overview of Functions......................................................................................................................... 33
1.8 Mask Options........................................................................................................................................ 34
1.9 Differences between Flash and Mask ROM version .......................................................................... 34
Chapter 2 Pin Function .................................................................................................. 36
2.1 Pin Function List ................................................................................................................................... 36
2.2 Non-Port Pins ....................................................................................................................................... 38
2.3 Description of Pin Functions .............................................................................................................. 40
2.3.1 P00 to P02, P06 and P07 (Port 0)...................................................................................................... 40
2.3.2 P10 to P13 (Port 1) ............................................................................................................................ 40
2.3.3 P40 to P47 (Port 4) ............................................................................................................................ 40
2.3.4 P80 to P87 (Port 8) ............................................................................................................................ 41
2.3.5 P90 to P97 (Port 9) ............................................................................................................................ 41
2.3.6 P100 to P107 (Port 10)....................................................................................................................... 41
2.3.7 P110 to P117 (Port 11)....................................................................................................................... 41
2.3.8 P120 to P127 (Port 12)....................................................................................................................... 42
2.3.9 COM0 to COM3 .................................................................................................................................. 42
2.3.10 VLC0 to VLC2 ................................................................................................................................... 42
2.3.11 AVDD/AVREF ................................................................................................................................... 43
2.3.12 AVSS................................................................................................................................................. 43
2.3.13 RESET .............................................................................................................................................. 43
2.3.14 X1 and X2 ......................................................................................................................................... 43
2.3.15 CL1 and CL2 .................................................................................................................................... 43
2.3.16 VDD0/VDD1 ...................................................................................................................................... 43
2.3.17 VSS0/VSS1 ....................................................................................................................................... 43
2.3.18 VPP (µPD16F15 only) ...................................................................................................................... 43
2.4 Pin I/O Circuits and Recommended Connection of Unused Pins.................................................... 44
8
µPD1615, µPD16F15, µPD1616
Chapter 3 CPU Architecture .......................................................................................... 51
3.1 Memory Space ...................................................................................................................................... 51
3.1.1 Internal program memory space ..................................................................................................... 53
3.1.2 Internal data memory space............................................................................................................. 55
3.1.3 Special function register (SFR) area ............................................................................................... 55
3.1.4 Data memory addressing ................................................................................................................. 56
3.2 Processor Registers ............................................................................................................................ 58
3.2.1 Control registers ............................................................................................................................... 58
3.2.2 General registers .............................................................................................................................. 61
3.2.3 Special function register (SFR) ....................................................................................................... 62
3.3 Instruction Address Addressing......................................................................................................... 65
3.3.1 Relative addressing .......................................................................................................................... 65
3.3.2 Immediate addressing ...................................................................................................................... 66
3.3.3 Table indirect addressing ................................................................................................................. 67
3.3.4 Register addressing .......................................................................................................................... 68
3.4 Operand Address Addressing............................................................................................................. 69
3.4.1 Implied addressing ........................................................................................................................... 69
3.4.2 Register addressing .......................................................................................................................... 70
3.4.3 Direct addressing .............................................................................................................................. 71
3.4.4 Short direct addressing .................................................................................................................... 72
3.4.5 Special function register (SFR) addressing ................................................................................... 73
3.4.6 Register indirect addressing............................................................................................................ 74
3.4.7 Based addressing.............................................................................................................................. 75
3.4.8 Based indexed addressing ............................................................................................................... 76
3.4.9 Stack addressing............................................................................................................................... 76
Chapter 4 Port Functions .............................................................................................. 78
4.1 Port Functions ...................................................................................................................................... 78
4.2 Port Configuration ............................................................................................................................... 81
4.2.1 Port 0 .................................................................................................................................................. 81
4.2.2 Port 1 .................................................................................................................................................. 83
4.2.3 Port 4 .................................................................................................................................................. 84
4.2.4 Port 8 .................................................................................................................................................. 85
4.2.5 Port 9 .................................................................................................................................................. 86
4.2.6 Port 10 ................................................................................................................................................ 87
4.2.7 Port 11 ................................................................................................................................................ 88
4.2.8 Port 12 ................................................................................................................................................ 89
4.3 Port Function Control Registers......................................................................................................... 90
4.4 Port Function Operations .................................................................................................................... 93
4.4.1 Writing to input/output port ............................................................................................................. 93
4.4.2 Reading from input/output port....................................................................................................... 93
4.4.3 Operations on input/output port...................................................................................................... 93
9
µPD1615, µPD16F15, µPD1616
Chapter 5 Clock Generator............................................................................................ 95
5.1 Clock Generator Functions ................................................................................................................. 95
5.2 Clock Generator Configuration........................................................................................................... 96
5.3 Clock Generator Control Register ...................................................................................................... 97
5.4 System Clock Oscillator ...................................................................................................................... 98
5.4.1 Main system clock oscillator ........................................................................................................... 98
5.4.2 Subsystem clock oscillator .............................................................................................................. 99
5.4.3 When no subsystem clocks are used ............................................................................................ 101
5.5 Clock Generator Operations ............................................................................................................. 102
5.5.1 Main system clock operations ....................................................................................................... 103
5.5.2 Subsystem clock operations .......................................................................................................... 104
5.6 Changing System Clock and CPU Clock Settings............................................................................ 105
5.6.1 Time required for switchover between system clock and CPU clock.......................................... 105
5.6.2 System clock and CPU clock switching procedure ..................................................................... 106
Chapter 6 16-Bit Timer/ Event Counter ...................................................................... 108
6.1 16-bit Timer/Event Counter Function ............................................................................................... 108
6.2 16-bit Timer/Event Counter Configuration ....................................................................................... 109
6.3 16-Bit Timer/Event Counter Control Register.................................................................................. 113
6.4 16-Bit Timer/Event Counter Operations ........................................................................................... 120
6.4.1 Operation as interval timer (16 bits) .............................................................................................. 120
6.4.2 PPG output operation ..................................................................................................................... 122
6.4.3 Pulse width measurement .............................................................................................................. 123
6.4.4 Operation as external event counter ............................................................................................. 130
6.4.5 Operation to output square wave .................................................................................................. 132
6.4.6 Operation to output one-shot pulse .............................................................................................. 134
6.5 16-Bit Timer/Event Counter Operating Precautions........................................................................ 139
Chapter 7 8-Bit Timer/Event Counters 50 and 51 ...................................................... 143
7.1 8-Bit Timer/Event Counters 50 and 51 Functions ............................................................................ 143
7.2 8-Bit Timer/Event Counters 50 and 51 Configurations ................................................................... 146
7.3 8-Bit Timer/Event Counters 50 and 51 Control Registers............................................................... 149
7.4 8-Bit Timer/Event Counters 50 and 51 Operations .......................................................................... 154
7.4.1 Interval timer operations ................................................................................................................. 154
7.4.2 External event counter operation .................................................................................................. 158
7.4.3 Square-wave output ........................................................................................................................ 159
7.4.4 PWM output operations .................................................................................................................. 161
7.5 Cautions on 8-Bit Timer/Event Counters 50 and 51 ........................................................................ 164
10
µPD1615, µPD16F15, µPD1616
Chapter 8 Watch Timer ................................................................................................. 167
8.1 Watch Timer Functions ...................................................................................................................... 167
8.2 Watch Timer Configuration................................................................................................................ 168
8.3 Watch Timer Mode Register (WTM) .................................................................................................. 169
8.4 Watch Timer Operations ..................................................................................................................... 170
8.4.1 Watch timer operation ..................................................................................................................... 170
8.4.2 Interval timer operation ................................................................................................................... 170
Chapter 9 Watchdog Timer .......................................................................................... 173
9.1 Watchdog Timer Functions ................................................................................................................ 173
9.2 Watchdog Timer Configuration ......................................................................................................... 174
9.3 Watchdog Timer Control Registers................................................................................................... 175
9.4 Watchdog Timer Operations ............................................................................................................... 177
9.4.1 Watchdog timer operation ............................................................................................................... 177
9.4.2 Interval timer operation .................................................................................................................. 178
Chapter 10 Clock Output Control Circuit................................................................... 180
10.1 Clock Output Control Circuit Functions ........................................................................................ 180
10.2 Clock Output Control Circuit Configuration ................................................................................. 181
10.3 Clock Output Function Control Registers ..................................................................................... 182
Chapter 11 A/D Converter............................................................................................ 185
11.1 A/D Converter Functions ................................................................................................................. 185
11.2 A/D Converter Configuration .......................................................................................................... 186
11.3 A/D Converter Control Registers .................................................................................................... 188
11.4 A/D Converter Operations ............................................................................................................... 191
11.4.1 Basic operations of A/D converter .............................................................................................. 191
11.4.2 Input voltage and conversion results .......................................................................................... 193
11.4.3 A/D converter operation mode ..................................................................................................... 194
11.5 A/D Converter Precautions.............................................................................................................. 196
11.6 Cautions on Emulation ................................................................................................................... 199
11.6.1 D/A converter mode register (DAM0) .......................................................................................... 199
Chapter 12 Serial Interface Outline ............................................................................ 201
12.1 Serial Interface Outline.................................................................................................................... 201
11
µPD1615, µPD16F15, µPD1616
Chapter 13 Serial Interface Channel 30...................................................................... 203
13.1 Serial Interface Channel 30 Functions .......................................................................................... 203
13.2 Serial Interface Channel 30 Configuration.................................................................................... 204
13.3 List of SFRs (Special Function Registers).................................................................................... 204
13.4 Serial Interface Control Registers ................................................................................................ 205
13.5 Serial Interface Operations ........................................................................................................... 206
13.5.1 Operation stop mode ..................................................................................................................... 206
13.5.2 Three-wire serial I/O mode ........................................................................................................... 207
Chapter 14 Serial Interface UART ............................................................................... 210
14.1 Serial Interface UART Functions ................................................................................................... 210
14.2 Serial Interface UART Configuration ............................................................................................. 211
14.3 List of SFRS (Special Function Registers) .............................................................................. 212
14.4 Serial Interface Control Registers ................................................................................................. 212
14.5 Serial Interface Operations ........................................................................................................... 216
14.5.1 Operation stop mode .................................................................................................................... 216
14.5.2 Asynchronous serial interface (UART) mode ............................................................................. 216
14.6 Standby Function ............................................................................................................................ 228
Chapter 15 VAN Controller........................................................................................... 230
15.1 Features .......................................................................................................................................... 230
15.2 Overview of the VAN Bus .............................................................................................................. 231
15.2.1 VAN UART Description ............................................................................................................... 231
15.2.2 VAN UART Interface .................................................................................................................... 231
15.3 Functional description................................................................................................................... 235
15.3.1 Overview of the VAN UART Registers ....................................................................................... 235
15.3.2 Autonomous mode functions..................................................................................................... 236
15.3.2.1 Autonomous mode features ...................................................................................................... 236
15.3.2.2 Programming of the prescaler in Rank 0 transmission (SOF included) ................................ 236
15.3.2.3 Transmission features in autonomous mode........................................................................... 237
15.3.3 Synchronous mode functions .................................................................................................... 238
15.3.3.1 Synchronous mode features .................................................................................................... 238
15.3.3.2 Transmission features in synchronous mode.......................................................................... 238
15.3.4 Handling of a collision .................................................................................................................. 238
15.3.5 Executing the CRC ........................................................................................................................ 238
15.3.5.1 CRC transmission ...................................................................................................................... 238
15.3.5.2 Reception of the CRC ................................................................................................................ 239
15.3.6 Control of the acknowledge bit.................................................................................................... 239
15.3.7 Error control and Interrupt control ............................................................................................. 239
15.3.7.1 Error control ............................................................................................................................... 239
15.3.7.2 Interrupt control ......................................................................................................................... 240
12
µPD1615, µPD16F15, µPD1616
15.4 VAN UART Registers ..................................................................................................................... 243
15.4.1 Rank0 Transmission Register (RK0_REG) .................................................................................. 244
15.4.2 In Frame Response Register (IFR_REG) ..................................................................................... 245
15.4.3 Control Register (CTRL_REG) ..................................................................................................... 247
15.4.4 Configuration Register (CONF_REG) .......................................................................................... 250
15.4.5 Diagnosis Control Register (DIAG_CTRL_REG) ........................................................................ 253
15.4.6 Mask1 registers (MSK1_MSB_REG, MSK1_LSB_REG).............................................................. 256
15.4.7 Acceptance Code 1 registers (AC1_MSB_REG, AC1_LSB_REG) .............................................. 257
15.4.8 Mask2 registers (MSK2_MSB_REG, MSK2_LSB_REG)............................................................. 258
15.4.9 Acceptance Code 2, 3 and 4 Registers (AC2_MSB_REG, AC2_LSB_REG, ............................... 259
15.4.10 Status Register (STAT_REG) ...................................................................................................... 260
15.4.11 Receive register (REC_REG) ...................................................................................................... 262
15.4.12 Diagnosis Status Register (DIAG_STAT_REG) ......................................................................... 263
15.4.13 Interrupt enable register (INT_ENABLE_REG) ......................................................................... 264
15.4.14 VAN clock selection register (UDLCCL) .................................................................................... 266
15.5 VAN UART initialisation .................................................................................................................. 267
Chapter 16 LCD Controller/Driver............................................................................... 269
16.1 LCD Controller/Driver Functions ................................................................................................... 269
16.2 LCD Controller/Driver Configuration ............................................................................................ 270
16.3 LCD Controller/Driver Control Registers ..................................................................................... 272
16.4 LCD Controller/Driver Settings...................................................................................................... 275
16.5 LCD Display Data Memory ............................................................................................................. 276
16.6 Common Signals and Segment Signals ........................................................................................ 277
16.7 Supply of LCD Drive Voltages VLC0, VLC1, VLC2 ......................................................................... 281
16.8 Display Modes .................................................................................................................................. 284
16.8.1 Static display example .................................................................................................................. 284
16.8.2 2-time-division display example ................................................................................................. 287
16.8.3 3-time-division display example ................................................................................................. 290
16.8.4 4-time-division display example ................................................................................................. 294
Chapter 17 Sound Generator ...................................................................................... 298
17.1 Sound Generator Function .............................................................................................................. 298
17.2 Sound Generator Configuration ..................................................................................................... 299
17.3 Sound Generator Control Registers............................................................................................... 300
17.4 Sound Generator Operations ........................................................................................................... 305
17.4.1 To output basic cycle signal SGOF (without amplitude) ............................................................ 305
17.4.2 To output basic cycle signal SGO (with amplitude) .................................................................... 305
13
µPD1615, µPD16F15, µPD1616
Chapter 18 Interrupt Functions................................................................................... 307
18.1 Interrupt Function Types.................................................................................................................. 307
18.2 Interrupt Sources and Configuration ............................................................................................. 308
18.3 Interrupt Function Control Registers ............................................................................................. 311
18.4 Interrupt Servicing Operations ....................................................................................................... 317
18.4.1 Non-maskable interrupt request acknowledge operation ......................................................... 317
18.4.2 Maskable interrupt request acknowledge operation .................................................................. 320
18.4.3 Software interrupt request acknowledge operation .................................................................. 322
18.4.4 Multiple interrupt servicing.......................................................................................................... 323
18.4.5 Interrupt request reserve ............................................................................................................. 326
Chapter 19 Standby Function...................................................................................... 328
19.1 Standby Function and Configuration ............................................................................................. 328
19.1.1 Standby function ........................................................................................................................... 328
19.1.2 Standby function control register ............................................................................................... 329
19.2 Standby Function Operations ......................................................................................................... 330
19.2.1 HALT mode..................................................................................................................................... 330
19.2.2 STOP mode .................................................................................................................................... 333
Chapter 20 Reset Function .......................................................................................... 337
20.1 Reset Function ................................................................................................................................. 337
Chapter 21 µPD16F15................................................................................................... 342
21.1 Memory Size Switching Register (IMS).......................................................................................... 343
21.2 Internal Extension RAM Size Switching Register ........................................................................ 344
21.3 Flash memory programming........................................................................................................... 345
21.3.1 Selection of transmission method .............................................................................................. 345
21.3.2 Initialization of the programming mode ..................................................................................... 345
21.3.3 Flash memory programming function ........................................................................................ 346
21.3.4 Flashpro connection ................................................................................................................... 346
21.3.5 Flash programming precautions ................................................................................................. 347
14
µPD1615, µPD16F15, µPD1616
Chapter 22 Instruction Set .......................................................................................... 349
22.1 Legends Used in Operation List ..................................................................................................... 350
22.1.1 Operand identifiers and description methods............................................................................ 350
22.1.2 Description of “operation” column ............................................................................................. 351
22.1.3 Description of “flag operation” column ...................................................................................... 351
22.2 Operation List................................................................................................................................... 352
22.3 Instructions Listed by Addressing Type......................................................................................... 360
Appendix A Development Tools .................................................................................. 365
A.1 Language Processing Software ....................................................................................................... 366
A.2 Flash Memory Writing Tools ............................................................................................................. 367
A.3 Debugging Tools ................................................................................................................................ 367
A.3.1 Hardware ......................................................................................................................................... 367
A.3.2 Software (1/2).................................................................................................................................. 368
A.3.2 Software (2/2).................................................................................................................................. 369
A.4 OS for IBM PC.................................................................................................................................... 370
A.5 Development Environment when Using IE-78001-R-A ................................................................... 371
Appendix B Embedded Software ................................................................................ 373
B.1 Real-Time OS (1/2).............................................................................................................................. 374
B.1 Real-Time OS (2/2) ............................................................................................................................ 375
B.2 Fuzzy Inference Development Support System.............................................................................. 376
Appendix C Register Index.......................................................................................... 378
C.1 Register Index (In Alphabetical Order with Respect to Register Names) .................................... 378
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)................................... 381
Appendix D Revision History ...................................................................................... 385
15
µPD1615, µPD16F15, µPD1616
Contents of Figures
Figure No.
Title
Page
1-1
1-2
1-3
1-4
Pin Configuration µPD1615, µPD16F15 ....................................................................... 27
Pin Configuration µPD1616 ......................................................................................... 28
Block Diagram µPD1615, µPD16F15 ............................................................................ 31
Block Diagram µPD1616 .............................................................................................. 32
2-1
2-2
Connection of IC Pins.................................................................................................. 43
Pin Input/Output Circuits ............................................................................................ 48
3-1
Memory Map (µPD1615, µPD1616) ............................................................................. 51
Memory Map (µPD16F15) ............................................................................................ 52
Data Memory Addressing (µPD1615, µPD1616)........................................................ 56
Data Memory Addressing (µPD16F15) ....................................................................... 57
Program Counter Configuration................................................................................. 58
Program Status Word Configuration.......................................................................... 58
Stack Pointer Configuration........................................................................................ 60
Data to be Saved to Stack Memory ............................................................................ 60
Data to be Reset to Stack Memory ............................................................................. 60
General Register Configuration.................................................................................. 61
Relative Addressing..................................................................................................... 65
Immediate Addressing................................................................................................. 66
Table Indirect Addressing ........................................................................................... 67
Register Addressing .................................................................................................... 68
Register Addressing .................................................................................................... 70
Short Direct Addressing.............................................................................................. 72
Special-Function Register (SFR) Addressing ........................................................... 73
Special-Function Register (SFR) Addressing ........................................................... 74
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
PortTypes ..................................................................................................................... 78
P00 to P02 and P06, P07 Configurations.................................................................... 82
P10 to P13 Configurations .......................................................................................... 83
P40 to P47 Configurations .......................................................................................... 84
P80 to P87 Configurations .......................................................................................... 85
P90 to P97 Configurations .......................................................................................... 86
P100 to P107 Configurations ...................................................................................... 87
P110 to P117 Configurations ...................................................................................... 88
P120 to P127 Configurations ...................................................................................... 89
Port Mode Register Format ......................................................................................... 91
Port Function Register (PF8 to PF12) Format ........................................................... 92
16
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Block Diagram of Clock Generator ............................................................................ 96
Processor Clock Control Register Format ................................................................ 97
External Circuit of Main System Clock Oscillator .................................................... 98
External Circuit of Subsystem Clock Oscillator ....................................................... 99
Examples of Oscillator with Bad Connection (3/3) ................................................... 100
Main System Clock Stop Function (2/2)..................................................................... 103
System Clock and CPU Clock Switching ................................................................... 106
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
Block Diagram of 16-Bit Timer/Event Counter (TM0) ............................................... 109
Format of 16-Bit Timer Mode Control Register (TMC0)............................................ 114
Format of Capture/Compare Control Register 0 (CRC0) ......................................... 116
Format of 16-Bit Timer Output Control Register (TOC0) ......................................... 117
Format of Prescaler Mode Register 0 (PRM0) ........................................................... 118
Port Mode Register 12 (PM12) Format ....................................................................... 119
Port Function Register 12 (PF12) Format .................................................................. 119
Control Register Settings When Timer 0 Operates as Interval Timer...................... 120
Configuration of Interval Timer .................................................................................. 121
Timing of Interval Timer Operation ............................................................................ 121
Control Register Settings in PPG Output Operation................................................ 122
Control Register Settings for Pulse Width Measurement with Free Running Counter
and One Capture Register ........................................................................................... 123
Configuration for Pulse Width Measurement with Free Running Counter ............. 124
Timing of Pulse Width Measurement with Free Running Counter and One Capture
Register (with both edges specified) ......................................................................... 124
Control Register Settings for Measurement of Two Pulse Widths with Free Running
Counter ......................................................................................................................... 125
CR01 Capture Operation with Rising Edge Specified .............................................. 126
Timing of Pulse Width Measurement with Free Running Counter (with both edges
specified) ...................................................................................................................... 126
Control Register Settings for Pulse Width Measurement with Free Running Counter
and Two Capture Registers ......................................................................................... 127
Timing of Pulse Width Measurement with Free Running Counter and Two Capture
Registers (with rising edge specified) ....................................................................... 128
Control Register Settings for Pulse Width Measurement by Restarting ................ 129
Timing of Pulse Width Measurement by Restarting (with rising edge specified).. 130
Control Register Settings in External Event Counter Mode .................................... 131
Configuration of External Event Counter .................................................................. 131
Timing of External Event Counter Operation (with rising edge specified) ............ 132
Set Contents of Control Registers in Square Wave Output Mode........................... 133
Timing of Square Wave Output Operation ................................................................. 133
Control Register Settings for One-Shot Pulse Output with Software Trigger ....... 135
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
17
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
6-28
6-29
6-30
Timing of One-Shot Pulse Output Operation with Software Trigger....................... 136
Control Register Settings for One-Shot Pulse Output with External Trigger ........ 137
Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge
specified) ...................................................................................................................... 138
Start Timing of 16-Bit Timer Register......................................................................... 139
Timing after Changing Compare Register during Timer Count Operation ............. 139
Data Hold Timing of Capture Register ....................................................................... 140
Operation Timing of OVF0 Flag................................................................................... 141
6-31
6-32
6-33
6-34
7-1
8-Bit Timer/Event Counter 50 Block Diagram............................................................ 146
8-Bit Timer/Event Counter 51 Block Diagram............................................................ 147
Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit.. 148
Timer Clock Select Register 50 Format ..................................................................... 149
Timer Clock Select Register 51 Format ..................................................................... 150
8-Bit Timer Output Control Register 50 Format ........................................................ 151
8-Bit Timer Output Control Register 51 Format ........................................................ 152
Port Mode Register 0 Format ...................................................................................... 153
8-Bit Timer Mode Control Register Settings for Interval Timer Operation ............. 154
Interval Timer Operation Timings (3/3)....................................................................... 154
8-Bit Timer Mode Control Register Setting for External Event Counter Operation 158
External Event Counter Operation Timings (with Rising Edge Specified) ............. 158
8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation . 159
Square-wave Output Operation Timing ...................................................................... 159
8-Bit Timer Control Register Settings for PWM Output Operation ......................... 161
PWM Output Operation Timing (Active high setting) ............................................... 162
PWM Output Operation Timings (CRn0 = 00H, active high setting) ........................ 162
PWM Output Operation Timings (CRn = FFH, active high setting) ......................... 163
PWM Output Operation Timings (CRn changing, active high setting) .................... 163
8-bit Timer Registers 50 and 51 Start Timings .......................................................... 164
External Event Counter Operation Timings ............................................................... 164
Timings after Compare Register Change during Timer Count Operation .............. 165
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
8-1
8-2
8-3
Block Diagram of Watch Timer ................................................................................... 167
Watch Timer Mode Control Register (WTM) Format ................................................. 169
Operation Timing of Watch Timer/Interval Timer ....................................................... 171
9-1
9-2
9-3
Watchdog Timer Block Diagram ................................................................................. 174
Watchdog Timer Clock Select Register Format ........................................................ 175
Watchdog Timer Mode Register Format .................................................................... 176
18
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
10-1
10-2
10-3
10-4
10-5
Remote Controlled Output Application Example...................................................... 180
Clock Output Control Circuit Block Diagram............................................................ 181
Clock Output Selection Register Format ................................................................... 182
Port Mode Register 12 Format .................................................................................... 183
Port Function Register 12 (PF12) Format .................................................................. 183
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
A/D Converter Block Diagram ..................................................................................... 185
Power-Fail Detection Function Block Diagram ......................................................... 186
A/D Converter Mode Register (ADM1) Format .......................................................... 188
Analog Input Channel Specification Register (ADS1) Format ................................. 189
Power-Fail Compare Mode Register (PFM) Format .................................................. 190
Power-fail compare threshold value register (PFT) .................................................. 190
Basic Operation of 8-Bit A/D Converter..................................................................... 192
Relation between Analog Input Voltage and A/D Conversion Result ...................... 193
A/D Conversion ............................................................................................................ 195
11-10 Example Method of Reducing Current Consumption in Standby Mode ................. 196
11-11 Analog Input Pin Handling .......................................................................................... 197
11-12 A/D Conversion End Interrupt Request Generation Timing ..................................... 198
11-13 D/A Converter Mode Register (DAM0) Format .......................................................... 199
13-1
13-2
13-3
13-4
13-5
Block Diagram of SIO30 .............................................................................................. 203
Format of Serial Operation Mode Register 30 (CSIM30) .......................................... 205
Format of Serial Operation Mode Register 30 (CSIM30) .......................................... 206
Format of Serial Operation Mode Register 30 (CSIM30) .......................................... 207
Timing of Three-wire Serial I/O Mode......................................................................... 208
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
Block Diagram of UART............................................................................................... 210
Format of Asynchronous Serial Interface Mode Register (ASIM0) ......................... 213
Format of Asynchronous Serial Interface Status Register (ASIS0) ........................ 214
Format of Baud Rate Generator Control Register (BRGC0) .................................... 215
Register Settings ......................................................................................................... 216
Asynchronous serial interface mode register (ASIM0) ............................................ 217
Asynchronous serial interface status register (ASIS0) ............................................ 218
Baud rate generator control register (BRGC0) ......................................................... 219
Error Tolerance (when k = 0), including Sampling Errors ........................................ 222
14-10 Format of Transmit/Receive Data in Asynchronous Serial Interface ...................... 223
14-11 Timing of Asynchronous Serial Interface Transmit Completion Interrupt ............. 225
14-12 Timing of Asynchronous Serial Interface Receive Completion Interrupt............... 226
14-13 Receive Error Timing ................................................................................................... 227
19
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
VAN UART Interface................................................................................................... 231
VAN UART Block Diagram ........................................................................................... 232
Generation of the VAN Clock ...................................................................................... 233
Overview of the VAN UART Registers ...................................................................... 235
Prescaler in Rank 0 transmission............................................................................... 236
Rank0 Transmission Register Format ........................................................................ 244
Frame Responce Register Format.............................................................................. 245
Frame Responce Register Function ........................................................................... 246
Control Register Format ............................................................................................. 247
15-10 Control Register Block Diagram ................................................................................ 248
15-11 Control Register Function........................................................................................... 248
15-12 Last-Byte....................................................................................................................... 248
15-13 Configuration Register (CONF_REG) Format ........................................................... 250
15-14 Case where IT12 = 0 ..................................................................................................... 250
15-15 Case where IT12 = 1 ..................................................................................................... 251
15-16 Diagnosis Control Register (DIAG_CTRL_REG) Format .......................................... 253
15-17 Prescaler Block Diagram............................................................................................. 253
15-18-1 Mask1 register MSK1_MSB_REG Format ................................................................. 256
15-18-2 Mask1 register MSK1_LSB_REG Format .................................................................. 256
15-19-1 Acceptance Code 1 register AC1_MSB_REG .......................................................... 257
15-19-2 Acceptance Code 1 register AC1_LSB_REG ........................................................... 257
15-20-1 Mask2 register MSK2_MSB_REG Format .............................................................. 258
15-20-2 Mask2 register MSK2_LSB_REG Format............................................................... 258
15-21 Acceptance Code 2, 3 and 4 Registers Format ........................................................ 259
15-22 Status Register (STAT_REG) Format......................................................................... 260
15-23 Receive register (REC_REG) Format ........................................................................ 262
15-24 Diagnosis Status Register (DIAG_STAT_REG) Format ............................................ 263
15-25 Interrupt enable register (INT_ENABLE_REG) Format .......................................... 264
15-26 VAN clock selection register (UDLCCL) Format ...................................................... 266
20
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
16-1
16-2
16-3
16-4
16-5
LCD Controller/Driver Block Diagram ....................................................................... 270
LCD Clock Select Circuit Block Diagram................................................................... 271
LCD Display Mode Register Format ........................................................................... 273
LCD Display Clock Control Register Format............................................................. 274
Relationship between LCD Display Data Memory Contents
and Segment/Common Outputs ................................................................................. 276
Common Signal Waveform ......................................................................................... 279
Common Signal and Static Signal Voltages and Phases .......................................... 280
LCD Drive Power Supply Connection Examples (with External Split Resistor) .... 282
Example of LCD Drive Voltage Supply from Off-Chip .............................................. 283
16-6
16-7
16-8
16-9
16-10 Static LCD Display Pattern and Electrode Connections.......................................... 284
16-11 Static LCD Panel Connection Example ...................................................................... 285
16-12 Static LCD Drive Waveform Examples ....................................................................... 286
16-13 2-Time-Division LCD Display Pattern and Electrode Connections......................... 287
16-14 2-Time-Division LCD Panel Connection Example ..................................................... 288
16-15 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) ...................... 289
16-16 3-Time-Division LCD Display Pattern and Electrode Connections......................... 290
16-17 3-Time-Division LCD Panel Connection Example ..................................................... 291
16-18 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) ...................... 292
16-19 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................... 293
16-20 4-Time-Division LCD Display Pattern and Electrode Connections......................... 294
16-21 4-Time-Division LCD Panel Connection Example ..................................................... 295
16-22 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................... 296
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
Sound Generator Block Diagram................................................................................ 298
Concept of Each Signal ............................................................................................... 299
Sound Generator Control Register (SGCR) Format ................................................. 301
Sound Generator Buzzer Control Register (SGBR) Format .................................... 302
Sound Generator Frequency Selection ...................................................................... 303
Sound Generator Amplitude Register (SGAM) Format ............................................ 304
Sound Generator Output Operation Timing without Amplitude ............................. 305
Sound Generator Output Operation Timing with Amplitude .................................. 305
21
µPD1615, µPD16F15, µPD1616
Figure No.
Title
Page
18-1
18-2
18-3
18-4
18-5
Basic Configuration of Interrupt Function (2/2)........................................................ 309
Interrupt Request Flag Register Format .................................................................... 312
Interrupt Mask Flag Register Format ......................................................................... 313
Priority Specify Flag Register Format ....................................................................... 314
Formats of External Interrupt Rising Edge Enable Register and External Interrupt
Falling Edge Enable Register...................................................................................... 315
Program Status Word Format ..................................................................................... 316
Flowchart from Non-Maskable Interrupt Generation to Acknowledge ................... 318
Non-Maskable Interrupt Request Acknowledge Timing............................................ 318
Non-Maskable Interrupt Request Acknowledge Operation ...................................... 319
18-6
18-7
18-8
18-9
18-10 Interrupt Request Acknowledge Processing Algorithm ........................................... 321
18-11 Interrupt Request Acknowledge Timing (Minimum Time) ........................................ 322
18-12 Interrupt Request Acknowledge Timing (Maximum Time)........................................ 322
18-13 Multiple Interrupt Example (2/2) ................................................................................. 324
18-14 Interrupt Request Hold ................................................................................................ 326
19-1
19-2
19-3
19-4
19-5
Oscillation Stabilization Time Select Register Format............................................. 329
HALT Mode Clear upon Interrupt Generation ............................................................ 331
HALT Mode Release by RESET Input ......................................................................... 332
STOP Mode Release by Interrupt Generation............................................................ 334
Release by STOP Mode RESET Input ......................................................................... 335
20-1
20-2
20-3
20-4
Block Diagram of Reset Function............................................................................... 337
Timing of Reset Input by RESET Input ...................................................................... 338
Timing of Reset due to Watchdog Timer Overflow ................................................... 338
Timing of Reset Input in STOP Mode by RESET Input ............................................. 338
21-1
21-2
21-3
21-4
21-5
21-6
Memory Size Switching Register Format .................................................................. 343
Internal Extension RAM Size Switching Register Format........................................ 344
Transmission Method Selection Format .................................................................... 345
Connection of Flashpro Using 3-Wire Serial I/O Method ......................................... 346
Flashpro Connection Using UART Method ................................................................ 347
Flashpro Connection Using Pseudo 3-wire Serial I/O .............................................. 347
A-1
Development Tool Configuration ................................................................................ 365
22
µPD1615, µPD16F15, µPD1616
Contents ofTables
Table No.
Title
Page
1-1 Internal high capacity ROM and RAM ............................................................................................... 26
1-2 Differences between Flash and Mask ROM version ........................................................................ 34
2-1-1 Pin Input/OutputTypes µPD1615, µPD16F15 .................................................................................. 36
2-1-2 Pin Input/Output Types µPD1616 .................................................................................................... 37
2-2-1 Non-Port Pins µPD1615, µPD16F15 .................................................................................................. 38
2-2-2 Non-Port Pins µPD1616 .................................................................................................................... 39
2-3-1 Types of Pin Input/Output Circuits µPD1615, µPD16F15 (2/2) ...................................................... 44
2-3-2 Types of Pin Input/Output Circuits µPD1616 (2/2)......................................................................... 46
3-1 Internal ROM Capacities ..................................................................................................................... 53
3-2 Vectored Interrupts .............................................................................................................................. 54
3-3 Special Function Register List (2/2 .................................................................................................... 63
3-4 Implied Addressing.............................................................................................................................. 69
3-5 Register Addressing ............................................................................................................................ 70
3-6 Direct Addressing ................................................................................................................................ 71
3-7 Short Direct Addressing ..................................................................................................................... 72
3-8 Special-Function Register (SFR) Addressing ................................................................................... 73
3-9 Register Indirect Addressing .............................................................................................................. 74
3-10 Based Addressing .............................................................................................................................. 75
3-11 Based Indexed Addressing ............................................................................................................... 76
4-1 Pin Input/Output Types µPD1615, µPD16F15 ..................................................................................... 79
4-2 Pin Input/Output Types µPD1616 ........................................................................................................ 80
4-3 Port Configuration ............................................................................................................................... 81
5-1 Clock Generator Configuration .......................................................................................................... 96
5-2 Maximum Time Required for CPU Clock Switchover ..................................................................... 105
6-1 Configuration of 16-bit Timer/Event Counter (TM0) ....................................................................... 109
6-2 Valid Edge of TI00 Pin and Valid Edge of Capture Trigger of Capture/Compare Register ........... 111
6-3 Valid Edge of TI01 Pin and Valid Edge of Capture Trigger of Capture/Compare Register ........... 111
7-1 8-Bit Timer/Event Counter 50 Interval Times ................................................................................... 144
7-2 8-Bit Timer/Event Counter 51 Interval Times ................................................................................... 144
7-3 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges .......................................................... 145
7-4 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges .......................................................... 145
7-5 8-Bit Timer/Event Counters 50 and 51 Configurations ................................................................... 146
7-6 8-Bit Timer/Event Counters 50 Interval Times ................................................................................. 157
7-7 8-Bit Timer/Event Counters 51 Interval Times ................................................................................. 157
7-8 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges ........................................................ 160
7-9 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges ........................................................ 160
23
µPD1615, µPD16F15, µPD1616
Table No.
Title
Page
8-1 Interval Timer Interval Time............................................................................................................... 168
8-2 Watch Timer Configuration ............................................................................................................... 168
8-3 Interval Timer Operation ................................................................................................................... 170
9-1 Watchdog Timer Inadvertent Program Overrun Detection Times .................................................. 173
9-2 Interval Times ..................................................................................................................................... 173
9-3 Watchdog Timer Configuration ......................................................................................................... 174
9-4 Watchdog Timer Overrun Detection Time ........................................................................................ 177
9-5 Interval Timer Interval Time............................................................................................................... 178
10-1 Clock Output Control Circuit Configuration ................................................................................. 181
11-1 A/D Converter Configuration .......................................................................................................... 186
12-1 Differences between the Serial Interface Channels ...................................................................... 201
13-1 Composition of SIO30 ..................................................................................................................... 204
13-2 List of SFRs (Special Function Registers) .................................................................................... 204
14-1 Configuration of UART .................................................................................................................... 211
14-2 List of SFRs (Special Function Registers) .................................................................................... 212
14-3 Relation between 5-bit Counter’s Source Clock and “n”Value ................................................... 220
14-4 Relation between Main System Clock and Baud Rate .................................................................. 221
14-5 Causes of Receive Errors................................................................................................................ 227
15-1 Network Speeds as a Function of the Quartz Clock and the Chosen Division Ratio ................ 237
15-2 Error Table ........................................................................................................................................ 239
15-3 Frame Responce .............................................................................................................................. 241
15-4 VAN UART Registers...................................................................................................................... 243
15-5 Stop Transmit ................................................................................................................................... 247
15-6 Acknowledge Request ..................................................................................................................... 247
15-7 Last-Byte........................................................................................................................................... 248
15-8 Software Reset ................................................................................................................................. 249
15-9 Enable / Disable interrupt on the 12th bit of the identifier field.................................................. 250
15-10 Rank 0 / Rank 1 mode .................................................................................................................... 251
15-11 Enable / Disable In Frame Response............................................................................................ 251
15-12 Mask Enable / Disable.................................................................................................................... 252
15-13 Prescaler - Network Speeds as a Function of the Quartz Clock and the Chosen
Division Ratio ................................................................................................................................ 254
15-14 Synchronous Diagnosis Clock..................................................................................................... 254
15-15 Enable the Transmit Diagnosis .................................................................................................... 254
15-16 Choice of Communication Mode .................................................................................................. 255
24
µPD1615, µPD16F15, µPD1616
Table No.
Title
Page
15-17 LA_RESP, LA .................................................................................................................................. 260
15-18 EOM ................................................................................................................................................. 260
15-19 The bits SA and SB ........................................................................................................................ 263
15-20 The bit SC........................................................................................................................................ 263
15-21 Interrupt enable register (INT_ENABLE_REG) (2/2) ................................................................... 264
15-22 VAN clock selection register (UDLCCL) ....................................................................................... 266
16-1 Maximum Number of Display Pixels .............................................................................................. 269
16-2 LCD Controller/Driver Configuration ............................................................................................. 270
16-3 Frame Frequencies (Hz) .................................................................................................................. 273
16-4 COM Signals ..................................................................................................................................... 277
16-5 LCD Drive Voltages .......................................................................................................................... 278
16-6 LCD Drive Voltages (with On-Chip Split Resistor)connected externally) .................................. 281
16-7 Selection and Non-Selection Voltages (COM0)............................................................................. 284
16-8 Selection and Non-Selection Voltages (COM0, COM1) ................................................................ 287
16-9 Selection and Non-Selection Voltages (COM0 to COM2) ............................................................. 290
16-10 Selection and Non-Selection Voltages (COM0 to COM3) ........................................................... 294
17-1 Sound Generator Configuration ..................................................................................................... 299
17-2 Maximum and Minimum Values of the Buzzer Output Frequency .............................................. 352
18-1 Interrupt Source List ....................................................................................................................... 308
18-2 Various Flags Corresponding to Interrupt Request Sources ....................................................... 311
18-3 Times from Maskable Interrupt Request Generation to Interrupt Service.................................. 320
18-4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ............................ 323
19-1 HALT Mode Operating Status.......................................................................................................... 330
19-2 Operation after HALT Mode Release .............................................................................................. 332
19-3 STOP Mode Operating Status ......................................................................................................... 333
19-4 Operation after STOP Mode Release .............................................................................................. 335
20-1 Hardware Status after Reset (2/2) .................................................................................................. 339
21-1 Differences among µPD16F15 and Mask ROM Versions............................................................... 342
21-2 Values when the Memory Size Switching Register is Reset ........................................................ 343
21-3 Examples of internal Extension RAM Size Switching Register Settings.................................... 344
21-4 Transmission Method List ............................................................................................................... 345
21-5 Main Functions of Flash Memory Programming ........................................................................... 346
22-1 Operand Identifiers and Description Methods .............................................................................. 350
25
µPD1615, µPD16F15, µPD1616
Chapter 1 Outline (µPD1615 Subseries)
1.1 Features
• Internal high capacity ROM and RAM
Table 1-1: Internal high capacity ROM and RAM
Item
Program
Data Memory
LCD Display
Part
Number
Memory
(ROM)
Internal High-
Speed RAM
Internal
VAN
Package
RAM
Expansion RAM
µPD1615
µPD16F15
µPD1616
32 K bytes
60 K bytes
32 K bytes
1024 bytes
1024 bytes
1024 bytes
40 bytes
512 bytes
1024 bytes
512 bytes
256 bytes
256 bytes
256 bytes
80-pin plastic QFP (fine pitch)
80-pin plastic QFP (fine pitch)
80-pin plastic QFP (fine pitch)
40 bytes
—
• Instruction execution time can be changed from
high speed (0.25 µs) to ultra low speed
• I/O ports: 57
• VAN-Interface
• Serial interface : 2 channels
• 3-wire mode : 1 channel
• UART mode : 1 channel
• 8-bit resolution A/D converter : 4 channels
• Sound generator
•
Timer
: 5 channels
• LCD-controller / driver
• Supply voltage : VDD = 4.0 to 5.5 V
1.2 Application
Multifunction display, steering controller, climate controller etc.
1.3 Ordering Information
PartNumber
Package
µPD1615GC(A) - xxx - 8BT 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)
µPD1616GC(A) - xxx - 8BT 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)
µPD16F15GC - 8BT
80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)
26
µPD1615, µPD16F15, µPD1616
1.4 Pin Configuration (Top View)
80-pin plastic QFP (14 x 14 mm)
µPD1615GC(A) - xxx - 8BT
µPD1616GC(A) - xxx - 8BT
µPD16F15GC - 8BT
Figure 1-1: Pin Configuration µPD1615, µPD16F15
60
59
58
57
56
P105/S18
P104/S19
P12/ANI2
P11/ANI1
P10/ANI0
AVDD/AVREF
RESET
X1
1
2
3
4
5
P103/S20
P102/S21
P101/S22
P100/S23
P97/S24
55
54
53
52
51
50
49
48
6
X2
7
8
P96/S25
V
PP/IC
CL1
CL2
P95/S26
P94/S27
P93/S28
P92/S29
P91/S30
9
10
11
12
13
V
SS
0
0
V
DD
P00/INTP0
47
46
45
44
43
42
41
P90/S31
P87/S32
P01/INTP1
P02/INTP2
P06/TI50/TO50
P07/TI51/TO51
Rx1VAN
14
15
16
17
18
19
20
P86/S33
P85/S34
P84/S35
Rx2VAN
P83/S36
P82/S37
Rx0VAN
Cautions: 1. Connect IC (internally connected) pin directly to VSS.
2. AVDD pin should be connected to VDD.
3. AVSS pin should be connected to VSS.
27
µPD1615, µPD16F15, µPD1616
Figure 1-2: Pin Configuration µPD1616
60
59
58
57
56
P105
P104
P12/ANI2
P11/ANI1
P10/ANI0
AVDD/AVREF
RESET
1
2
3
4
5
P103
P102
P101
P100
P97
55
54
53
52
51
50
49
48
X1
X2
IC1
CL1
CL2
6
7
8
P96
P95
P94
P93
P92
P91
9
10
11
12
13
V
SS
0
0
V
DD
P00/INTP0
47
46
45
44
43
42
41
P90
P87
P01/INTP1
P02/INTP2
P06/TI50/TO50
P07/TI51/TO51
Rx1VAN
14
15
16
17
18
19
20
P86
P85
P84
Rx2VAN
P83
P82
Rx0VAN
Cautions: 1. Connect IC1 (internally connected) pin directly to VSS.
2. Connect IC2 (internally connected) pin directly to VDD.
3. AVDD pin should be connected to VDD.
4. AVSS pin should be connected to VSS.
5. NC pins are not connected.
28
µPD1615, µPD16F15, µPD1616
Pin Identifications
P00 to P02, P06, P07 : Port0
RxD0
TxD0
SGO
SGOA
SGOF
PCL
: Receive Data
: Transmit Data
: Sound Generator Output
: Sound Generator Amplitude
: Sound Generator Frequency
: Programmable Clock Output
P10 to P13
: Port1
P40 to P47
: Port4
P80 to P87
: Port8
P90 to P97
: Port9
P100 to P107
P110 to P117
P120 to P127
INTP0 to INTP2
: Port10
: Port11
: Port12
: Interrupt External
S0 to S39
COM0 to COM3: Common Output
X1, X2
: Segment Output
: Crystal (Main System Clock)
TI00, TI01, TI50, TI51 : Timer Input
CL1, CL2
RESET
ANI0 to ANI3 : Analog Input
: RC (Subsystem Clock)
: Reset
TO0 , TO51, TO52
Rx0VAN
Rx1VAN
Rx2VAN
TxVAN
: Timer Output
: VAN Receive Data
: VAN Receive Data
: VAN Receive Data
: VAN Transmit Data
: Serial Input
AVSS
: Analog Ground
AVDD/AVREF
: Analog Power Supply and
Reference Voltage
: Programming Power supply
: Ground
SI3
VPP
SO3
: Serial Output
VSS
SCK3
: Serial Clock
IC, IC1, IC2 : Internally Connected
NC : Not Connected
29
µPD1615, µPD16F15, µPD1616
1.5 78K/0 Series Development
These products are a further development in the 78K/0 Series. The designations appearing inside the
boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
For control
µ
100-pin
100-pin
80-pin
µPD78078
µPD78070A
µPD78054
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD78078Y
µPD78070AY ROM-less product for the µPD78078
PD78054Y
µPD78018FY Low-voltage (1.8 V) operation version of the PD78014, ROM and RAM variations enhanced
Timer added to the PD78054, external interface functions enhanced
µ
UART and D/A added to the µPD78014, I/O enhanced
64-pin
µ
µPD78014Y
A/D and 16-bit timer added to the PD78002
A/D added to the µPD78002
Basic subseries for control
Internal UART, low-voltage (1.8 V) operation possible
µ
64-pin
64-pin
64-pin
42/44-pin
µPD78002Y
For FIPdriving
100-pin
µPD780208
µPD78044A
µPD78024
I/O, FIP C/D of the PD78044A enhanecd, display output total: 53
µ
78K/0
Series
80-pin
64-pin
6-bit U/D counter added to the PD78024, display output total: 34
µ
Basic subseries for FIP driving, display output total: 26
For LCD driving
µPD78064
100-pin
µPD78064Y Subseries for LCD driving, internal UART
µPD780308Y
µ
PD780308
For IEBusTM
80-pin
µPD78098
IEBus controller added to the PD78054
µ
100-pin
µ
µ
µ
PD780949
PD780826
PD780814
CANBus controller
80-pin
64-pin
30
µPD1615, µPD16F15, µPD1616
1.6 Block Diagram
Figure 1-3: Block Diagram µPD1615, µPD16F15
P00-P02,
P06, P07
Port 0
Port 1
5
4
16-bitCounter
TI00/TO0/P121
P122/TI01
(TM0)
P10-P13
8-bit Timer
(TM50)
TI50/TO50/P06
TI51/TO51/P07
8
8
8
8
8
8
3
Port 4
Port 8
P40-P47
8-bit Timer
(TM51)
P80-P87
SGO/SGOF/P47
SGOA/P46
Sound Generator
Port 9
P90-P97
Watchdog Timer
Port 10
Port 11
Port 12
P100-P107
P110-P117
P120-P127
Watch Timer
UART
78K/0
CPU CORE
RxD0/P123
TxD0/P124
SCK3/P125
SO3/P126
SI3/P127
SIO30
INTP0/P00-
INTP2/P02
Interrupt
Control
ROM
RAM
Standby
Control
32 K bytes/
Flash
ANI0 to ANI3
AVDD/AVREF
AVSS
1536 bytes/
A/D Converter
2048 bytes
60 K bytes
COM0-COM3
LCD
Controller/
Driver
P127/S0-
P80/S39
Clock Output
Control
PCL/P120
System
Control
8.0 M Hz /
5 V
RESET
X1
VLC0-VLC2
TxVAN
Rx0VAN
Rx1VAN
Rx2VAN
X2
VAN-
UDL
UART
I/F
CL1
CL2
RC Oscillator
UDL
Remark:
The internal ROM and RAM capacity depends on the product.
31
µPD1615, µPD16F15, µPD1616
Figure 1-4: Block Diagram µPD1616
P00-P02,
P06, P07
Port 0
Port 1
5
4
16-bitCounter
(TM0)
TI00/TO0/P121
P122/TI01
P10-P13
8-bit Timer
(TM50)
TI50/TO50/P06
TI51/TO51/P07
8
8
8
8
8
8
3
Port 4
Port 8
P40-P47
8-bit Timer
(TM51)
P80-P87
SGO/SGOF/P47
SGOA/P46
Sound Generator
Port 9
P90-P97
Watchdog Timer
Port 10
Port 11
Port 12
P100-P107
P110-P117
P120-P127
Watch Timer
UART
78K/0
CPU CORE
RxD0/P123
TxD0/P124
SCK3/P125
SO3/P126
SI3/P127
SIO30
INTP0/P00-
INTP2/P02
Interrupt
Control
Standby
Control
ROM
RAM
ANI0 to ANI3
AVDD/AVREF
AVSS
32 K bytes
1536 Bytes
A/D Converter
Clock Output
Control
PCL/P120
System
Control
8.0 M Hz /
5 V
RESET
X1
TxVAN
Rx0VAN
Rx1VAN
Rx2VAN
X2
VAN-
UDL
UART
I/F
CL1
CL2
RC Oscillator
UDL
32
µPD1615, µPD16F15, µPD1616
1.7 Overview of Functions
Part Number
µPD1615
40 bytes
µPD1616
µPD16F15
60 Kbytes
Item
ROM
32 Kbytes
512 bytes
Internal high-speed RAM
LCD Display RAM
Internal Expansion RAM
1024 bytes
Internal
memory
40 bytes
—
1024 bytes
Memory space
General registers
Instruction cycle
64 Kbytes
8 bits x 32 registers ( 8 bits x 8 registers x 4 banks)
On-chip instruction execution time selective function
When main system clock
selected
When subsystem clock
selected
0,25 µs/0,5 µs/1 µs/2 µs/4 µs (at 8 MHz)
122 µs (at 32.768 kHz)
•
•
•
•
16-bit operation
Multiplication/division ( 8 bits x 8 bits, 16 bits – 8 bits )
Bit manipulation ( set, reset, test, boolean operation )
BCD adjustment, etc.
Instruction set
Total
: 57
I/O ports
•
•
CMOS input
CMOS I/O
: 4
: 53
A/D converter
•
8 bit resolution x 4 channels
•
•
•
•
•
•
3-wire mode : 1 channel
UART mode : 1 channel
16 bit timer / event counter : 1 channel
8 bit timer / event counter : 2 channels
Watch timer
Serial Interface
Timer
: 1 channel
: 1 channel
Watchdog timer
Timer output
Clock output
2 (8-bit PWM output x 2 )
62,5 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz,
4 MHz, 8 MHz (at main system clock of 8.0 MHz)
Sound Generator
LCD Controller/Driver
VAN
1 channel (as separate or composed output)
40 seg x 4 COM
1 channel
Internal : 15
External : 3
Maskable interrupts
Vectored
interrupts
Non-maskable interrupts Internal : 1
Software interrupts
Internal : 1
Supply voltage
Package
VDD = 4,0 V to 5,5 V
80-pin plastic QFP ( 14 mm x 14 mm )
33
µPD1615, µPD16F15, µPD1616
1.8 Mask Options
There are no mask options provided.
1.9 Differences between Flash and Mask ROM version
The differences between the two versions are shown in the table below. Differences of the electrical
specification are given in the data sheet.
Table 1-2: Differences between Flash and Mask ROM version
Flash Version
Flash EEPROM
Yes
Mask ROM Version
Mask ROM
ROM
VPP Pin
None (IC pin)
34
µPD1615, µPD16F15, µPD1616
[Memo]
35
µPD1615, µPD16F15, µPD1616
Chapter 2 Pin Function (µPD1615 Subseries)
2.1 Pin Function List
Normal Operating Mode Pins / Pin Input/Output Types
Table 2-1-1: Pin Input/Output Types µPD1615, µPD16F15
Input /
Output
Pin
Name
P00
Alternate
Function
INTP0
After
Reset
Function
Input
Input
Input
Input
Input
P01
P02
P06
P07
INTP1
Port 0
Input /
Output
5 bit input / output port
Input / output mode can be specified bit-wise
INTP2
TI50/TO50
TI51/TO51
Port 1
Input
P10-P13
4 bit input port
ANI0-ANI3
Input
Input mode can be specified bit-wise
P40
P41
P42
P43
P44
P45
P46
P47
-
Input
Input
Input
Input
Input
Input
Input
Input
-
-
Port 4
8 bit input/output port
Input / output mode can be specified bit-wise
-
Input /
Output
-
-
SG0A
SG0/SG0F
Port 8
8 bit input / output port
Input/
Output
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 9
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 10
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 11
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
P80-P87
P90-P97
S39 - S32
S31 - S24
S23 - S16
S15 - S8
Input
Input
Input
Input
Input/
Output
Input/
Output
P100-
P107
Input/
Output
P110-
P117
P120
P121
P122
P123
P124
P125
P126
P127
PCL/S7
TI00/TO0/S6
TI01/S5
Port 12
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
RxD0/S4
TxD0/S3
SCK3/S2
SO3/S1
Input/
Output
Input
SI3/S0
36
µPD1615, µPD16F15, µPD1616
Table 2-1-2: Pin Input/Output Types µPD1616
Input /
Output
Pin
Name
Alternate
Function
After
Reset
Function
P00
INTP0
Input
Input
Input
Input
Input
P01
P02
P06
P07
INTP1
Port 0
Input /
Output
5 bit input / output port
Input / output mode can be specified bit-wise
INTP2
TI50/TO50
TI51/TO51
Port 1
Input
P10-P13
4 bit input port
ANI0-ANI3
Input
Input mode can be specified bit-wise
P40
P41
P42
P43
P44
P45
P46
P47
-
Input
Input
Input
Input
Input
Input
Input
Input
-
-
Port 4
8 bit input/output port
Input / output mode can be specified bit-wise
-
Input /
Output
-
-
SG0A
SG0/SG0F
Port 8
8 bit input / output port
Input/
Output
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 9
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 10
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 11
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
P80-P87
P90-P97
-
-
-
-
Input
Input
Input
Input
Input/
Output
Input/
Output
P100-
P107
Input/
Output
P110-
P117
P120
P121
P122
P123
P124
P125
P126
P127
PCL
TI00/TO0
TI01
Port 12
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
RxD0
TxD0
SCK3
SO3
Input/
Output
Input
SI3
37
µPD1615, µPD16F15, µPD1616
2.2 Non-Port Pins
Table 2-2-1: Non-Port Pins µPD1615, µPD16F15
After
Reset
Alternate
Function Pin
Pin Name
INTP0
I/O
Function
P00
External interrupts with specifiable valid edges
(rising edge, falling edge, both rising and falling
edges)
INTP1
INTP2
SI3
Input
Input
P01
P02
Input
Serial interface serial data input
Serial interface serial data output
Input
Input
P127/S0
P126/S1
SO3
Output
Input/
Output
SCK3
Serial interface serial clock input / output
Input
P125/S2
RxD0
TxD0
Input
Asynchronous serial interface data input
Asynchronous serial interface data output
Input
Input
P123/S4
P124/S3
Output
Rx0VAN,
Rx1VAN,
Rx2VAN
Input
VAN serial data input
Input
-
TxVAN
TI00
Output
VAN serial data output
Output
-
P121/TO0/S6
P122/S5
P06/TO50
P07/TO51
P121/TI00/S6
P06/TI50
P07/TI51
P120/S7
P127 to P120
P117 to P110
P107 to P100
P97 to P90
P87 to P80
-
External count clock input to 16-bit timer (TM0)
TI01
Input
Input
TI50
External count clock input to 8-bit timer (TM50)
External count clock input to 8-bit timer (TM51)
16-bit timer output
TI51
TO0
TO50
Output
Output
8-bit timer output (also used for PWM output)
8-bit timer output (also used for PWM output)
Clock output
Input
Input
TO51
PCL
S0 to S7
S8 to S15
S16 to S23
S24 to S31
S32 to S39
COM0-COM3
VLC0 to V LC2
SGO
Output
Segment signal output of LCD controller / driver
Input
Output
-
Common signal output of LCD controller/driver
LCD drive voltage
Output
-
-
Output
Output
Output
Input
Sound generator output
Input
Input
Input
Input
P47/SGOF
P46
SGOA
Sound generator amplitude output
Sound generator frequency output
A/D Converter analog input
SGOF
P47/SGO
P10 – P13
ANI0 to ANI3
A/D Converter reference voltage input and power
supply
AVDD/ AVREF
-
-
-
AVSS
-
A/D Converter ground potential. Connect to VSS.
System reset input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESET
X1
Input
-
Connection for main system clock
Connection for main system clock
RC connection for subsystem clock
RC connection for subsystem clock
Positive power supply
X2
-
CL1
Input
CL2
-
-
-
-
VDD1, VDD2
VSS1, VSS2
IC
Ground potential
Internal connection. Connect directly to VSS
Programming voltage. Connect directly to VSS
except flash programming.
VPP
-
-
-
38
µPD1615, µPD16F15, µPD1616
Table 2-2-2: Non-Port Pins µPD1616
After
Reset
Alternate
Function Pin
Pin Name
INTP0
I/O
Function
P00
External interrupts with specifiable valid edges
(rising edge, falling edge, both rising and falling
edges)
INTP1
INTP2
SI3
Input
Input
P01
P02
Input
Serial interface serial data input
Serial interface serial data output
Input
Input
P127
P126
SO3
Output
Input/
Output
SCK3
Serial interface serial clock input / output
Input
P125
RxD0
TxD0
Input
Asynchronous serial interface data input
Asynchronous serial interface data output
Input
Input
P123
P124
Output
Rx0VAN,
Rx1VAN,
Rx2VAN
Input
VAN serial data input
Input
-
TxVAN
TI00
Output
VAN serial data output
Output
-
P121/TO0
P122
External count clock input to 16-bit timer (TM0)
TI01
Input
Input
TI50
External count clock input to 8-bit timer (TM50)
External count clock input to 8-bit timer (TM51)
16-bit timer output
P06/TO50
P07/TO51
P121/TI00
P06/TI50
P07/TI51
P120
TI51
TO0
TO50
TO51
PCL
Output
8-bit timer output (also used for PWM output)
8-bit timer output (also used for PWM output)
Clock output
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
SGO
Sound generator output
P47/SGOF
P46
SGOA
SGOF
ANI0 to ANI3
Sound generator amplitude output
Sound generator frequency output
A/D Converter analog input
P47/SGO
P10 – P13
A/D Converter reference voltage input and power
supply
AVDD/ AVREF
-
-
-
AVSS
RESET
X1
-
A/D Converter ground potential. Connect to VSS.
System reset input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input
-
Connection for main system clock
Connection for main system clock
RC connection for subsystem clock
RC connection for subsystem clock
Positive power supply
X2
-
CL1
Input
CL2
-
-
-
-
-
-
VDD1, VDD2
VSS1, VSS2
IC1
Ground potential
Internal connection. Connect directly to VSS
Internal connection. Connect directly to VDD
Not connected
IC2
NC
39
µPD1615, µPD16F15, µPD1616
2.3 Description of Pin Functions
2.3.1 P00 to P02, P06 and P07 (Port 0)
This is a 5-bit input/output port. Beside serving as input/output port, it supports functions as an
external interrupt input, an external count clock input to the timer and a timer signal output.
The following operating modes can be specified bit-wise.
(1) Port mode
P00 to P02, P06 and P07 function as input/output ports. P00 to P02, P06 and P07 can be specified
for input or output ports bitwise with a port mode register 0.
(2) Control mode
In this mode, this port supports the function like external interrupt input, an external count
clock input to the timer and a timer signal output.
(a) INTP0 to INTP2
INTP0 to INTP2 are external interrupt input pins which can specify valid edges (rising edge,
falling edge, and both rising and falling edges).
(b) TI50
Pin for external count clock input to 8-bit timer/event counter.
(c) TI51
Pin for external count clock input to 8-bit timer/event counter.
(d) TO50
Pin for output of the 8-bit timer/event counter.
(e) TO51
Pin for output of the 8-bit timer/event counter.
2.3.2 P10 to P13 (Port 1)
This is a 4-bit input port. Beside serving as input port, it functions as an A/D converter analog input.
The following operating modes can be specified bit-wise.
(1) Port mode
Thisport functions as 4-bit input ports.
(2) Control mode
This port functions as A/D converter analog input pins (ANI0 to ANI3).
2.3.3 P40 to P47 (Port 4)
This is an 8-bit input/output port. Beside serving as input/output port, this port functions as sound
generator output.
The following operating modes can be specified bit-wise.
(1) Port mode
This port functions as an 8-bit input/output port. It can be specified bit-wise as input or output
ports with the port mode register 4.
40
µPD1615, µPD16F15, µPD1616
(2) Control mode
This port functions as timer input, clock output, and sound generator output.
(a) SGO, SGOA and SGOF
Pins for separate or composed signal ouput of the sound generator.
2.3.4 P80 to P87 (Port 8)
This is an 8-bit input/output port. Beside serving as input/output port, this port supports an LCD
controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
This port functions as an 8-bit input/output port. It can be specified bit-wise as input/ output ports
with the port mode register 8.
(2) Control mode
In this mode it functions as segment signal output pins (S32 to S39) of the LCD controller/
driver.
2.3.5 P90 to P97 (Port 9)
This is an 8-bit input/output port. In addition to its use as an input/output port, it supports also segment
signal output function of the LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
Port 9 functions as an 8-bit input/output port. Bit-wise specification as an input port or output port
is possible by meaning of port mode register 9.
(2) Control mode
Port 9 supports the segment signal output pins (S24 to S31) of the LCD controller/driver.
2.3.6 P100 to P107 (Port 10)
This is an 8-bit input/output port. In addition to its use as an input/output port, it supports also segment
signal output functions of the LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
Port 10 functions as an 8-bit input/output port. Bit-wise specification as an input port or output
port is possible by meaning of port mode register 10.
(2) Control mode
Port 10 supports the segment signal output pins (S16 to S23) of the LCD controller/driver.
2.3.7 P110 to P117 (Port 11)
This is an 8-bit input/output port. In addition to its use as an input/output port, it supports also segment
signal output functions of the LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
Port 11 functions as an 8-bit input/output port. Bit-wise specification as an input port or output
port is possible by meaning of port mode register 11.
41
µPD1615, µPD16F15, µPD1616
(2) Control mode
Port 11 supports the segment signal output pins (S15 to S8) of the LCD controller/driver.
2.3.8 P120 to P127 (Port 12)
These are 8-bit input/output ports. Besides serving as input/output ports, they function as data
input/output to/from the serial interface, serial interface clock input/output, as segment signal output
pins of LCD controller/driver and as processor clock output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output
ports with port mode register 12.
(2) Control mode
These ports function as serial interface data input/output, clock input/output.
(a) SI3, SO3
Serial interface serial data input/output pins
(b) SCK3
Serial interface serial clock input/output pins
(c) RxD0, TxD0
Asynchronous serial interface data input/output pins
(d) PCL
Clock output pin.
(e) LCD controller/driver
These ports function as segment output signal pins (S0 to S7) of LCD controller/driver.
Caution: When this port is used as a serial interface, the I/O and output latches must
be set according to the function the user requires.
2.3.9 COM0 to COM3
These are LCD controller/driver common signal output pins. They output common signals under the
following condition:
- static mode
- 1/2 duty cycle is performed in 1/2 bias mode
- 1/3 duty cycle is performed in 1/2 bias mode
- 1/3 duty cycle is performed in 1/3 bias mode
- 1/4 duty cycle is performed in 1/3 bias mode
2.3.10 VLC0 to VLC2
These are LCD drive voltage pins. In the Flash EEPROM and the MaskROM product an external split
resistors are necessary.
42
µPD1615, µPD16F15, µPD1616
2.3.11 AVDD/AVREF
A/D converter reference voltage input pin and the power supply for the A/D-converter. When A/D
converter is not used, connect this pin to VDD.
2.3.12 AVSS
This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin
even when A/D converter is not used.
2.3.13 RESET
This is a low-level active system reset input pin.
2.3.14 X1 and X2
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it
to X1.
2.3.15 CL1 and CL2
Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input it to
CL1 and let CL2 open.
2.3.16 VDD0/VDD1
Positive power supply pins.
2.3.17 VSS0/VSS1
Ground potential pins.
2.3.18 VPP (µPD16F15 only)
High-voltage apply pin for FLASH programming mode setting. Connect it directly to VSS with the
shortest possible wire in the normal operating mode. When a voltage difference is produced between
the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is
input to the IC pin, the user’s program may not run normally.
Figure 2-1: Connection of IC Pins
• Connect IC pins to Vss pins directly.
Vss IC
As short as possible
43
µPD1615, µPD16F15, µPD1616
2.4 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in the
following table.
For the input/output circuit configuration of each type, see table.
Table 2-3-1: Types of Pin Input/Output Circuits µPD1615, µPD16F15 (1/2)
Input/Output
Circuit Type
Pin Name
P00/INTP0
I/O
Recommended Connection for Unused Pins
P01/INTP1
P02/INTP2
P06/TI50/TO50
P07/TI51/TO51
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P40
8
I/O Connect to VSS via a resistor individually
9
5
I
Connect to VDD or VSS via a resistor individually
P41
P42
P43
I/O
Connect to VDD or VSS via a resistor individually
P44
P45
P46/SGOA
P47/SGO/SGOF
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
17
I/O
Connect to VDD or VSS via a resistor individually
17
I/O
Connect to VDD or VSS via a resistor individually
44
µPD1615, µPD16F15, µPD1616
Table 2-3-1: Types of Pin Input/Output Circuits µPD1615, µPD16F15 (2/2)
Input/Output
Circuit Type
Pin Name
P100/S23
I/O
Recommended Connection for Unused Pins
Connect to VDD or VSS via a resistor individually
P101/S22
P102/S21
P103/S20
17
I/O
P104/S19
P105/S18
P106/S17
P107/S16
P110/S15
P111/S14
P112/S13
P113/S12
17
I/O
Connect to VDD or VSS via a resistor individually
P114/S11
P115/S10
P116/S9
P117/S8
P120/S7/PCL
P121/S6/TI00/TO0
P122/S5/TI01
P123/S4/RxD0
P124/S3/TxD0
P125/S2/SCK3
P126/S1/SO3
P127/S0/SI3
COM0 – COM3
VLC0 – VLC2
17
17-C
17-C
17-C
17
I/O
Connect to VDD or VSS via a resistor individually
17-C
17
17-C
18
O
-
Leave open
-
Connect to VDD
Rx0VAN, Rx1VAN,
Rx2VAN
2
I
-
TxVAN
CL1
19
-
O
I
-
Connect to VDD or VSS
Leave open
CL2
-
-
RESET
AVDD
AVSS
IC
2
-
I
-
I
Connect to VDD
Connect to VSS
Connect directly to VSS
-
-
-
-
Connect directly to VSS
(except for flash programming)
VPP
1
-
45
µPD1615, µPD16F15, µPD1616
Table 2-3-2: Types of Pin Input/Output Circuits µPD1616 (1/2)
Input/Output
Circuit Type
Pin Name
P00/INTP0
I/O
Recommended Connection for Unused Pins
P01/INTP1
P02/INTP2
P06/TI50/TO50
P07/TI51/TO51
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P40
8
9
I/O Connect to VDD or VSS via a resistor individually
I
Connect to VDD or VSS via a resistor individually
P41
P42
P43
5
5
5
I/O
Connect to VDD or VSS via a resistor individually
P44
P45
P46/SGOA
P47/SGO/SGOF
P80
P81
P82
P83
I/O
Connect to VDD or VSS via a resistor individually
P84
P85
P86
P87
P90
P91
P92
P93
I/O
Connect to VDD or VSS via a resistor individually
P94
P95
P96
P97
46
µPD1615, µPD16F15, µPD1616
Table 2-3-2: Types of Pin Input/Output Circuits µPD1616 (2/2)
Input/Output
Circuit Type
Pin Name
P100
I/O
I/O
Recommended Connection for Unused Pins
Connect to VDD or VSS via a resistor individually
P101
P102
P103
8
P104
P105
P106
P107
P110
P111
P112
P113
5
I/O
Connect to VDD or VSS via a resistor individually
P114
P115
P116
P117
P120/ PCL
P121/TI00/TO0
P122/TI01
P123/RxD0
P124/ TxD0
P125/ SCK3
P126/SO3
P127/SI3
5
8
8
8
5
8
5
8
I/O
Connect to VDD or VSS via a resistor individually
Rx0VAN, Rx1VAN,
Rx2VAN
2
I
-
TxVAN
CL1
19
-
O
I
-
Connect to VDD or VSS
Leave open
CL2
-
-
I
RESET
AVDD
AVSS
IC1
2
-
-
I
Connect to VDD
Connect to VSS
Connect directly to VSS
Connect directly to VDD
Leave open
-
-
-
-
-
-
IC2
-
NC
-
47
µPD1615, µPD16F15, µPD1616
Figure 2-2: Pin Input/Output Circuits (1/2)
Type 1
Type 2
Input data
IN
Input data
IN
Type 5
Type 8
VDD
P-ch
VDD
Data
Data
P-ch
IN/OUT
IN/OUT
Output
disable
N-ch
Output
disable
N-ch
Input
enable
Type 9
P-ch
N-ch
Comparator
V
+
-
IN
REF (Threshold Voltage)
Input
enable
48
µPD1615, µPD16F15, µPD1616
Figure 2-2: Pin Input/Output Circuits (2/2)
Type 17-C
Data
Type 17
Data
V
DD
V
DD
P-ch
P-ch
IN/OUT
IN/OUT
Output
disable
Output
disable
N-ch
N-ch
Input
enable
VLC0
VLC0
P-ch
N-ch
P-ch
N-ch
V
LC1
V
LC1
P-ch
N-ch
P-ch
N-ch
SEG
Data
SEG
Data
P-ch
N-ch
P-ch
N-ch
VLC2
VLC2
Type 18
Type 19
LC0
V
P-ch
OUT
LC1
V
Data
N-ch
N-ch
N-ch
P-ch
OUT
N-ch
P-ch
COM
P-ch
N-ch
VLC2
N-ch
49
µPD1615, µPD16F15, µPD1616
[Memo]
50
µPD1615, µPD16F15, µPD1616
Chapter 3 CPU Architecture
3.1 Memory Space
The memory map of the µPD1615, µPD1616 is shown in Figure 3-1.
Figure 3-1: Memory Map (µPD1615, µPD1616)
FFFFH
Special Function Registers
(SFRs) 256 x 8 bits
FF20H
FF1FH
FF00H
FEFFH
General Registers
32 x 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1024 x 8 bits
FE20H
FB00H
FAFFH
Not usable
FA28H
FA27H
LCD Display RAM
40 x 4 bits
FA00H
F9FFH
7FFFH
Not usable
F900H
F8FFH
Program Area
CALLF Entry Area
Program Area
VAN UDL RAM
256 x 8 bits
1000H
0FFFH
F800H
F7FFH
Internal Expansion RAM
512 x 8 bits
0800H
07FFH
F600H
F5FFH
0080H
007FH
Not usable
8000H
7FFFH
CALLT Table Area
Vector Table Area
0040H
003FH
Internal ROM
32768 x 8 bits
0000H
0000H
Note: The LCD Display RAM is not available in the µPD1616.
51
µPD1615, µPD16F15, µPD1616
The memory map of the µPD16F15 is shown in Figure 3-2.
Figure 3-2: Memory Map (µPD16F15)
FFFFH
Special Function Registers
(SFRs) 256 x 8 bits
FF20H
FF1FH
FF00H
FEFFH
General Registers
32 x 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1024 x 8 bits
FE20H
FB00H
FAFFH
Not usable
FA28H
FA27H
LCD Display RAM
40 x 4 bits
FA00H
F9FFH
Not usable
EFFFH
F900H
F8FFH
Program Area
CALLF Entry Area
Program Area
1000H
0FFFH
VAN UDL RAM
256 x 8 bits
F800H
F7FFH
0800H
07FFH
Internal Expansion RAM
1024 x 8 bits
F400H
F3FFH
0080H
007FH
Not usable
F000H
EFFFH
CALLT Table Area
Vector Table Area
0040H
003FH
Internal Flash EEPROM
61440 x 8 bits
0000H
0000H
52
µPD1615, µPD16F15, µPD1616
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This is generally accessed by the
program counter (PC). The µPD1615 subseries have various size of internal ROMs or Flash EPROM
as shown below.
Table 3-1: Internal ROM Capacities
Part Number
Internal ROM
Capacity
Type
Mask ROM
Mask ROM
Flash
µPD1615
32768 x 8-bits
32768 x 8-bits
61440 x 8-bits
µPD1616
µPD16F15
The internal program memory is divided into three areas: vector table area, CALLT instruction table area,
and CALLF instruction table area. These areas are described on the next page.
53
µPD1615, µPD16F15, µPD1616
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program
start addresses for branch upon generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored
at odd addresses.
Table 3-2: Vectored Interrupts
Vector Table Address
0004H
Interrupt Request
INWDT
0006H
INTVE
0008H
INTVT
000AH
000CH
000EH
0010H
INTTVR
INTP0
INTP1
INTP2
0012H
INTTM00
INTTM01
INTTM50
INTTM51
INTWTI
INTWT
0014H
0016H
0018H
001AH
001CH
001EH
0020H
INTCSI3
INTSER
INTSR
0022H
0024H
INTST
0026H
INTAD
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction
(CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
54
µPD1615, µPD16F15, µPD1616
3.1.2 Internal data memory space
The µPD1615 subseries units incorporate the following RAMs.
(1) Internal high-speed RAM
This is a 1024 x 8-bit configuration in the area FB00H to FEFFH 4 banks of general registers,
each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.
(2) LCD-DisplayRAM
Buffer RAM is allocated to the 40 x 4 bits area from FA00H to FA27H. LCD-Display RAM can
also be used as normal RAM. The LCD Display RAM is not available in the µPD1616.
(3) Internal expansion RAM
Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH for the
µPD16F15. For the µPD1615, µPD1616 is the 512-byte area located between F600H and F7FFH.
(4) VAN UDL RAM
The VAN UDL RAM is located in a 256-byte area from F800H to F8FFH.
3.1.3 Special function register (SFR) area
An on-chip peripheral hardware special function register (SFR) is allocated in the area FF00H to
FFFFH. (Refer to Table 3-3).
Caution: Do not access addresses where the SFR is not assigned.
55
µPD1615, µPD16F15, µPD1616
3.1.4 Data memory addressing
The µPD1615 subseries is provided with a varity of addressing modes which take account of memory
manipulability, etc. Special addressing methods are possible to meet the functions of the special function
registers (SFRs) and general registers. The data memory space is the entire 64K-byte space (0000H to
FFFFH). Figures 3-3 and 3-4 show the data memory addressing modes.
For details of addressing, refer to 3.4 Operand Address Addressing.
Figure 3-3: Data Memory Addressing (µPD1615, µPD1616)
FFFFH
Special Function Registers
SFR Addressing
(SFRs) 256 x 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short Direct
Addressing
General Registers
32 x 8 bits
Register Addressing
FEE0H
FEDFH
Internal High-speed RAM
1024 x 8 bits
FE20H
FB1FH
FB00H
FAFFH
Not usable
FA28H
FA27H
Direct
LCD Display RAM
40 x 4 bits
Addressing
FAD0H
F9FFH
Register
Indirect
Addressing
Not usable
F900H
F8FFH
Based
Addressing
VAN UDL RAM
256 x 8 bits
F800H
F7FFH
Based
Indexed
Addressing
Internal Expansion RAM
512 x 8 bits
F600H
F5FFH
Not usable
8000H
7FFFH
Internal ROM
32768 x 8 bits
0000H
56
µPD1615, µPD16F15, µPD1616
Figure 3-4: Data Memory Addressing (µPD16F15)
FFFFH
Special Function Registers
(SFRs) 256 x 8 bits
SFR Addressing
FF20H
FF1FH
FF00H
FEFFH
Short Direct
Addressing
General Registers
32 x 8 bits
Register Addressing
FEE0H
FEDFH
Internal High-speed RAM
1024 x 8 bits
FE20H
FB1FH
FB00H
FAFFH
Not usable
FA28H
FA27H
Direct
LCD Display RAM
40 x 4 bits
Addressing
FA00H
F9FFH
Register
Indirect
Addressing
Not usable
F900H
F8FFH
Based
Addressing
VAN UDL RAM
256 x 8 bits
F800H
F7FFH
Based
Indexed
Addressing
Internal Expansion RAM
1024 x 8 bits
F400H
F3FFH
Not usable
F000H
EFFFH
Internal Flash EEPROM
61440 x 8 bits
0000H
57
µPD1615, µPD16F15, µPD1616
3.2 Processor Registers
The µPD1615 subseries units incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses, and stack memory. The control registers
consist of a program counter, a program status word and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program
to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the
instruction to be fetched. When a branch instruction is executed, immediate data and register
contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program
counter.
Figure 3-5: Program Counter Configuration
15
0
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by
instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or
PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI
and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-6: Program Status Word Configuration
7
0
IE
Z
RBS1
AC
RBS0
0
ISP
CY
58
µPD1615, µPD16F15, µPD1616
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt
are disabled.
When 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is controlled
with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE is reset to (0) upon DI instruction execution or interrupt request acknowledgement and is set
to (1) upon EI instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0)
in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When 0, acknowl-
edgment of the vectored interrupt request specified to low-order priority with the priority specify flag
registers (PR0L, PR0H, and PR1L) is disabled. Whether an actual interrupt request is acknowledged
or not is controlled with the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-
out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
59
µPD1615, µPD16F15, µPD1616
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal
high-speed RAM area can be set as the stack area.
Figure 3-7: Stack Pointer Configuration
15
0
SP
The SP is decremented ahead of write (save) to the stack memory and is incremented after read
(reset) from the stack memory.
Each stack operation saves/resets data as shown in Figures 3-8 and 3-9.
Caution: Since RESET input makes SP contents indeterminate, be sure to initialize the SP
before instruction execution.
Figure 3-8: Data to be Saved to Stack Memory
Interrupt and
BRK Instruction
PUSH rp Instruction
CALL, CALLF, and
CALLT Instruction
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Register Pair Lower
Register Pair Upper
SP
PC7 to PC0
SP
SP
SP
PC15 to PC8
SP
SP
SP
Figure 3-9: Data to be Reset to Stack Memory
RETI and RETB
Instruction
POP rp Instruction
RET Instruction
SP
SP + 1
Register Pair Lower
Register Pair Upper
SP
SP + 1
SP
PC7 to PC0
PC7 to PC0
PC15 to PC8
PSW
SP + 1
SP + 2
PC15 to PC8
SP SP + 2
SP SP + 2
SP SP + 3
60
µPD1615, µPD16F15, µPD1616
3.2.2 General registers
A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It
consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a
16-bit register (AX, BC, DE, and HL).
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL
RBn). Because of the 4-register bank configuration, an efficient program can be created by switching
between a register for normal processing and a register for interruption for each bank.
Figure 3-10: General Register Configuration
(a) Absolute Name
16-Bit Processing
RP3
8-Bit Processing
R7
FEFFH
FEF8H
BANK0
BANK1
BANK2
BANK3
R6
R5
R4
R3
R2
R1
R0
RP2
RP1
RP0
FEE0H
FEE8H
FEE0H
15
0
7
0
(b) Function Name
16-Bit Processing
8-Bit Processing
H
FEFFH
FEF8H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
L
D
E
B
C
A
X
FEF0H
FEE8H
AX
FEE0H
15
0
7
0
61
µPD1615, µPD16F15, µPD1616
3.2.3 Special function register (SFR)
Unlike a general register, each special function register has special functions.
It is allocated in the FF00H to FFFFH area.
The special function registers can be manipulated in a similar way as the general registers, by using
operation, transfer, or bit-manipulate instructions. The special function registers are read from and
written to in specified manipulation bit units (1, 8, and/or 16) depending on the register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand
(sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand
(sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand
(sfrp).
When addressing an address, describe an even address.
Table 3-3 gives a list of special function registers. The meaning of items in the table is as follows.
• Symbol
The assembler software translates these symbols into corresponding addresses where the special
function registers are allocated. These symbols should be used as instruction operands in the case
of programming.
• R/W
This column shows whether the corresponding special function register can be read or written.
R/W : Both reading and writing are enabled.
R
: The value in the register can read out. A write to this register is ignored.
W
: A value can be written to the register. Reading values from the register is impossible.
• Manipulation
The register can be manipulated in bit units.
• After reset
The register is set to the value immediately after the RESET signal is input.
62
µPD1615, µPD16F15, µPD1616
Table 3-3: Special Function Register List (1/2)
Address
SFR Name
Symbol
R/W
Manipulatable Bit Unit
After
Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
1 bit
¡
¡
¡
¡
¡
¡
¡
¡
—
8 bits
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
16 bits
—
FF00H
FF01H
FF04H
FF08H
FF09H
FF0AH
FF0BH
FF0CH
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H
FF17H
FF18H
Port 0
Port 1
Port 4
Port 8
Port 9
Port 10
Port 11
Port 12
P0
P1
R/W
R
—
P4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
—
P8
—
P9
—
P10
P11
P12
CR50
CR51
TM50
TM51
—
—
—
8 bit compare register 50
8 bit compare register 51
8 bit timer/counter 50
8 bit timer/counter 51
—
—
—
—
—
R
—
—
16bit capture/compare register 00
16bit capture/compare register 01
CR00
CR01
R/W
R/W
—
—
—
—
0000H
0000H
¡
¡
Serial shift register
SIO3
TXS0
RXB0
ADCR1
PM0
R/W
W
—
—
—
—
¡
¡
¡
¡
¡
¡
¡
¡
—
—
—
—
—
—
—
—
—
—
—
—
00H
FFH
FFH
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
Transmission shift register
Reception shift register
A/D conversion result register
Port mode register 0
FF1AH
R
FF1BH
FF20H
FF24H
FF28H
FF29H
FF2AH
FF2BH
FF2CH
FF40H
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port mode register 4
PM4
Port mode register 8
PM8
Port mode register 9
PM9
Port mode register 10
Port mode register 11
Port mode register 12
Clock output select register
PM10
PM11
PM12
CKS
Watch timer operation mode
register
Watchdog timer clock select
register
External interrupt rising edge
enable register
External interrupt falling edge
enable register
FF41H
FF42H
FF48H
FF49H
WTM
WDCS
EGP
R/W
R/W
R/W
R/W
—
—
—
—
00H
00H
00H
00H
¡
—
¡
¡
¡
¡
¡
¡
EGN
FF58H
FF59H
FF5AH
FF5BH
FF5CH
Port function register 8
Port function register 9
Port function register 10
Port function register 11
Port function register 12
PF8
PF9
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
00H
00H
00H
00H
00H
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
PF10
PF11
PF12
63
µPD1615, µPD16F15, µPD1616
Table 3-3: Special Function Register List (2/2)
Manipulatable Bit Unit
After
Reset
Address
SFR Name
Symbol
R/W
1 bit
¡
8 bits 16 bits
FF60H
FF61H
FF62H
FF63H
FF64H
FF65H
FF66H
16-bit timer mode control register 0
Prescaler mode register 0
TMC0
PRM0
CRC0
TOC0
R/W
R/W
R/W
R/W
—
—
—
—
00H
00H
00H
00H
¡
¡
¡
¡
—
Capture compare control register 0
Timer output control register 0
¡
¡
16-bit timer/counter 0
TM0
R
—
—
00H
¡
Sound generator control register
SGCR
SGAM
R/W
R/W
—
—
00H
00H
¡
¡
¡
¡
Sound generator 7-bit amplitude
register
Sound generator buzzer control
register
FF67H
FF68H
SGBR
R/W
—
00H
¡
¡
FF6FH
FF70H
FF71H
FF74H
FF75H
FF78H
FF80H
Serial I/F mode register
CSIM3
TMC50
TCL50
TMC51
TCL51
UDLCCL
ADM1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
00H
04H
00H
04H
00H
00H
00H
¡
¡
—
¡
—
¡
¡
¡
¡
¡
¡
¡
—
¡
8-bit timer mode control register 50
Timer clock select register 50
8-bit timer mode control register 51
Timer clock select register 51
VAN-UDL clock control register
A/D converter mode register 1
Analog input channel specification
register 1
Power fail detector value comparison
mode register
FF81H
FF82H
ADS1
PFM
R/W
R/W
—
—
—
—
00H
00H
¡
¡
Power fail detector threshold value
setting register
FF83H
FF84H
FFA0H
PFT
R/W
R/W
R/W
—
¡
¡
—
—
—
00H
00H
00H
¡
¡
¡
On Emulator for power-fail detection
DAM0
ASIM0
Asynchronous serial interface mode
register
Asynchronous serial interface status
register
FFA1H
ASIS0
R/W
—
—
00H
¡
FFA2H
FFB0H
FFB2H
FFE0H
FFE1H
FFE2H
FFE4H
FFE5H
FFE6H
FFE8H
FFE9H
Baud rate generator control register
LCD display mode register
LCD clock control register
BRGC0
LCDM
LCDC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
—
—
—
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
00H
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
¡
Interrupt request flag register
Interrupt request flag register
Interrupt request flag register
Interrupt mask flag register
Interrupt mask flag register
Interrupt mask flag register
Priority flag specification register
Priority flag specification register
IF0L
IF0H
IF1L
IF0
MK0
PR0
¡
¡
¡
—
¡
MK0L
MK0H
MK1L
PR0L
PR0H
FFEAH Priority flag specification register
PR1L
—
—
Internal memory size switching
FFF0H
register
IMS
R/W
—
CFH
¡
Internal extended RAM size
switching register
FFF4H
IXS
WDTM
OSTS
PCC
R/W
R/W
R/W
R/W
—
¡
—
¡
—
—
—
—
0CH
00H
04H
04H
¡
¡
¡
¡
FFF9H
FFFAH
FFFBH
Watchdog timer mode register
Oscillation stabilisation time select
register
Processor clock control register
64
µPD1615, µPD16F15, µPD1616
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. The PC contents are normally
incremented(+1foreachbyte)automaticallyaccordingtothenumberofbytesofaninstructiontobefetched
each time another instruction is executed. However, when a branch instruction is executed, the branch
destinationinformationissettothePCandbranchedbythefollowingaddressing. (Fordetailsofinstructions,
refer to 78K/0 User's Manual - Instructions (U12326E).
3.3.1 Relative addressing
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code
to the start address of the following instruction is transferred to the program counter (PC) and branched.
The displacement value is treated as signed two’s complement data (-128 to +127) and bit 7 becomes
a sign bit.
In other words, the range of branch in relative addressing is between -128 and +127 of the start address
of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional
branch instruction is executed.
Figure 3-11: Relative Addressing
15
15
0
PC indicates the start address
of the instruction
after the BR instruction.
...
PC
+
8
7
6
0
S
a
jdisp8
15
0
PC
When S = 0, all bits of a are 0.
When S = 1, all bits of a are 1.
65
µPD1615, µPD16F15, µPD1616
3.3.2 Immediate addressing
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is
executed.
CALL !addr16 and BR !addr16 instructions can branch to all the memory space.
CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.
Figure 3-12: Immediate Addressing
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALL !addr16 and BR !addr16 instructions
7
6
4
3
0
fa10–8
CALLF
fa7–0
15
11 10
1
8 7
0
PC
0
0
0
0
In the case of CALLF !addr11 instruction
66
µPD1615, µPD16F15, µPD1616
3.3.3 Table indirect addressing
Table contents (branch destination address) of the particular location to be addressed by bits 1 to
5 of the immediate data of an operation code are transferred to the program counter (PC) and branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This
instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory
space.
Figure 3-13: Table Indirect Addressing
7
6
1
5
1
0
1
Operation Code
1
ta4–0
15
8
0
7
0
6
1
5
1
0
0
Effective Address
0
0
0
0
0
0
0
7
Memory (Table)
Low Addr.
0
High Addr.
Effective Address+1
15
8
7
0
PC
67
µPD1615, µPD16F15, µPD1616
3.3.4 Register addressing
Register pair (AX) contents to be specified with an instruction word are transferred to the program
counter (PC) and branched.
This function is carried out when the BR AX instruction is executed.
Figure 3-14: Register Addressing
7
0
8
7
7
0
0
rp
A
X
15
PC
68
µPD1615, µPD16F15, µPD1616
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
3.4.1 Implied addressing
The register which functions as an accumulator (A and AX) in the general register is automatically
(implicitly) addressed.
Table 3-4: Implied Addressing
Instruction
MULU
Register to be Specified by Implied Addressing
A register for multiplicant and AX register for product storage
AX register for dividend and quotient storage
DIVUW
ADJBA/ADJBS
ROR4/ROL4
A register for storage of numeric values which become decimal correction targets
A register for storage of digit data which undergoes digit rotation
Operand format
Because implied addressing can be automatically employed with an instruction, no particular operand
format is necessary.
Description example
In the case of MULU X
With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In
this example, the A and AX registers are specified by implied addressing.
69
µPD1615, µPD16F15, µPD1616
3.4.2 Register addressing
The general register is accessed as an operand. The general register to be accessed is specified
with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction
code.
Register addressing is carried out when an instruction with the following operand format is executed.
When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation
code.
Table 3-5: Register Addressing
Operand format
Identifier
Description
X, A, C, B, E, D, L, H
AX, BC, DE, HL
r
rp
‘r’ and ‘rp’ can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well
as absolute names (R0 to R7 and RP0 to RP3).
Description example
Figure 3-15: Register Addressing
Operation code
0
1 1 0 0 0 1 0
Register specify code
MOV A, C; when selecting C register as r
Operation code
1
0 0 0 0 1 0 0
Register specify code
INCW DE; when selecting DE register pair as rp
70
µPD1615, µPD16F15, µPD1616
3.4.3 Direct addressing
The memory indicated by immediate data in an instruction word is directly addressed.
Operand format
Table 3-6: Direct Addressing
Identifier
addr16
Description
Label or 16-bit immediate data
Description example
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1 0 0 0 1 1 1 0
OP code
00H
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0
FEH
71
µPD1615, µPD16F15, µPD1616
3.4.4 Short direct addressing
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction
word.
The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH.
An internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and
FF00H to FF1FH, respectively.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the SFR area.
In this area, ports which are frequently accessed in a program, a compare register of the timer/event
counter, and a capture register of the timer/event counter are mapped and these SFRs can be
manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at
00H to 1FH, bit 8 is set to 1. Refer to Figure 3-16 below.
Operand format
Table 3-7: Short Direct Addressing
Identifier
saddr
Description
Label of FE20H to FF1FH immediate data
saddrp
Label of FE20H to FF1FH immediate data (even address only)
Description example
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H.
Operation code
0 0 0 1 0 0 0 1
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
OP code
30H (saddr-offset)
50H (immediate data)
Illustration
Figure 3-16: Short Direct Addressing
7
0
OP code
saddr-offset
Short Direct Memory
15
1
8
7
0
Effective Address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
72
µPD1615, µPD16F15, µPD1616
3.4.5 Special function register (SFR) addressing
The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However,
the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Operand format
Table 3-8: Special-Function Register (SFR) Addressing
Identifier
sfr
Description
Special-function register name
16-bit manipulatable special-function register name (even address only)
sfrp
Description example
MOV PM0, A; when selecting PM0 (FE20H) as sfr
Operation code 1 1 1 1 0 1 1 0
0 0 1 0 0 0 0 0
OP code
20H (sfr-offset)
Illustration
Figure 3-17: Special-Function Register (SFR) Addressing
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective Address
1
1
1
1
1
1
1
73
µPD1615, µPD16F15, µPD1616
3.4.6 Register indirect addressing
The memory is addressed with the contents of the register pair specified as an operand. The register
pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register
pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Operand format
Table 3-9: Register Indirect Addressing
Identifier
—
Description
[DE], [HL]
Description example
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1 0 0 0 0 1 0 1
Illustration
Figure 3-18: Special-Function Register (SFR) Addressing
16
8
7
0
DE
D
E
Memory address specified
by register pair DE
7
0
The contents of addressed
memory are transferred
Memory
7
0
A
74
µPD1615, µPD16F15, µPD1616
3.4.7 Based addressing
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and
the sum is used to address the memory. The HL register pair to be accessed is in the register bank
specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the
offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can
be carried out for all the memory spaces.
Operand format
Table 3-10: Based Addressing
Identifier
—
Description
[HL + byte]
Description example
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1 0 1 0 1 1 1 0
0 0 0 1 0 0 0 0
75
µPD1615, µPD16F15, µPD1616
3.4.8 Based indexed addressing
The B or C register contents specified in an instruction are added to the contents of the base register,
that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers
to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and
RBS1).
Addition is performed by expanding the contents of the B or C register as a positive number to 16
bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory
spaces.
Table 3-11: Based Indexed Addressing
Operand format
Identifier
—
Description
[HL + B], [HL + C]
Description example
In the case of MOV A, [HL + B]
Operation code
1 0 1 0 1 0 1 1
3.4.9 Stack addressing
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and
RETURN instructions are executed or the register is saved/reset upon generation of an interrupt
request.
Stack addressing enables to address the internal high-speed RAM area only.
Description example
In the case of PUSH DE
Operation code
1 0 1 1 0 1 0 1
76
µPD1615, µPD16F15, µPD1616
[Memo]
77
µPD1615, µPD16F15, µPD1616
Chapter 4 Port Functions
4.1 Port Functions
The µPD1615 subseries units incorporate four input ports and fifty-three input/output ports. Figure
4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry
out considerably varied control operations. Besides port functions, the ports can also serve as on-chip
hardware input/output pins.
Figure 4-1: Port Types
P00
P01
P02
P06
P07
Port0
P90
Port9
P10
P13
Port1
P97
P100
Port10
Port11
Port12
P40
P107
P110
Port4
P47
P80
P117
P120
Port8
P127
P87
78
µPD1615, µPD16F15, µPD1616
Table 4-1: Pin Input/Output Types µPD1615, µPD16F15
Input /
Output
Pin
Name
Alternate
Function
INTP0
After
Reset
Function
P00
Input
Input
Input
Input
Input
P01
P02
P06
P07
INTP1
Port 0
Input /
Output
5 bit input / output port
Input / output mode can be specified bit-wise
INTP2
TI50/TO50
TI51/TO51
Port 1
Input
P10-P13
4 bit input port
ANI0-ANI3
Input
Input mode can be specified bit-wise
P40
P41
P42
P43
P44
P45
P46
P47
-
Input
Input
Input
Input
Input
Input
Input
Input
-
-
Port 4
8 bit input/output port
Input / output mode can be specified bit-wise
-
Input /
Output
-
-
SG0A
SG0/SG0F
Port 8
8 bit input / output port
Input/
Output
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 9
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 10
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 11
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
P80-P87
P90-P97
S39 - S32
S31 - S24
S23 - S16
S15 - S8
Input
Input
Input
Input
Input/
Output
Input/
Output
P100-
P107
Input/
Output
P110-
P117
P120
P121
P122
P123
P124
P125
P126
P127
PCL/S7
TI00/TO0/S6
TI01/S5
Port 12
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
RxD0/S4
TxD0/S3
SCK3/S2
SO3/S1
Input/
Output
Input
SI3/S0
79
µPD1615, µPD16F15, µPD1616
Table 4-2: Pin Input/Output Types µPD1616
Input /
Output
Pin
Name
Alternate
Function
After
Reset
Function
P00
INTP0
Input
Input
Input
Input
Input
P01
P02
P06
P07
INTP1
Port 0
Input /
Output
5 bit input / output port
Input / output mode can be specified bit-wise
INTP2
TI50/TO50
TI51/TO51
Port 1
Input
P10-P13
4 bit input port
ANI0-ANI3
Input
Input mode can be specified bit-wise
P40
P41
P42
P43
P44
P45
P46
P47
-
Input
Input
Input
Input
Input
Input
Input
Input
-
-
Port 4
8 bit input/output port
Input / output mode can be specified bit-wise
-
Input /
Output
-
-
SG0A
SG0/SG0F
Port 8
8 bit input / output port
Input/
Output
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 9
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 10
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
Port 11
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
P80-P87
P90-P97
-
-
-
-
Input
Input
Input
Input
Input/
Output
Input/
Output
P100-
P107
Input/
Output
P110-
P117
P120
P121
P122
P123
P124
P125
P126
P127
PCL
TI00/TO0
TI01
Port 12
8 bit input / output port
Input / output mode can be specified bit-wise
This port can be used as segment signal output port
or an I/O port in 1-bit units by setting port function
register
RxD0
TxD0
SCK3
SO3
Input/
Output
Input
SI3
80
µPD1615, µPD16F15, µPD1616
4.2 Port Configuration
A port consists of the following hardware:
Table 4-3: Port Configuration
Item
Control register
Port
Configuration
Port mode register (PMm: m = 0, 4, 8 to 12)
Port function register (PFm: m = 8 to 12)
Total: 57 ports
4.2.1 Port 0
Port 0 is an 5-bit input/output port with output latch. P00 to P02 and P06, P07 pins can be specified
as input mode/output mode in 1-bit units with the port mode register 0 (PM0).
Dual-functions include external interrupt request input.
RESET input sets port 0 to input mode.
Figure 4-2 shows block diagram of port 0.
Caution: Because port 0 also supports the external interrupt request input, when the port
function output mode is specified and the output level is changed, the interrupt
request flag is set. Thus, when the output mode is used, set the interrupt mask flag
to 1.
81
µPD1615, µPD16F15, µPD1616
Figure 4-2: P00 to P02 and P06, P07 Configurations
RD
Selector
WRPORT
P00/INTP0,
P01/INTP1,
P02/INTP02,
P06/TI50/TO50,
Output Latch
(P00 to P02,
P06, P07)
P07/TI51/TO51
WRPM
PM00 to PM02,
P06, P07
PM : Port mode register
RD : Port 0 read signal
WR : Port 0 write signal
82
µPD1615, µPD16F15, µPD1616
4.2.2 Port 1
Port 1 is a 4-bit input only port.
Dual-functions include an A/D converter analog input.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3: P10 to P13 Configurations
RD
P10/ANI0
to
P13/ANI13
RD : Port 1 read signal
83
µPD1615, µPD16F15, µPD1616
4.2.3 Port 4
Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output
mode in 1-bit units.
Dual-function includes the sound generator output.
RESET input sets port 4 to input mode.
Figure 4- 4 shows a block diagram of port 4.
Figure 4-4: P40 to P47 Configurations
RD
Selector
WRPORT
P40 to P45,
P46/SGOA,
P47/SGO/SGOA
Output Latch
(P40 to P47)
WRPM
PM40 to PM47
PM : Port mode register
RD : Port 4 read signal
WR : Port 4 write signal
84
µPD1615, µPD16F15, µPD1616
4.2.4 Port 8
Port 8 is an 8-bit input/output port with output latch. P80 to P87 pins can be specified as input mode/
output mode in 1-bit units with the port mode register 8 (PM8).
Dual-function includes the segment signal outputs of LCD controller driver. The dual-function can be
selected with the port function register 8 (PF8).
RESET input sets port 8 to input mode.
Figure 4-5 shows a block diagram of port 8.
Figure 4-5: P80 to P87 Configurations
RD
Selector
WRPORT
P80/S39
to
P87/S32
Output Latch
(P80 to P87)
WRPM
PM80 to PM87
Dual Function
PM : Port mode register
RD : Port 8 read signal
WR : Port 8 write signal
Note:
The LCD controller/driver segment signal output is only valid on the µPD1615 and the
µPD16F15.
85
µPD1615, µPD16F15, µPD1616
4.2.5 Port 9
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in
1-bit units with a port mode register 9.
Dual-function includes the segment signal outputs of LCD controller driver. The dual-function can
be specified with the port function register 9 (PF9).
RESET input sets port 9 to input mode.
Figure 4-6 shows a block diagram of port 9.
Caution: When used as segment lines, set the port function PF9 according to its functions.
Figure 4-6: P90 to P97 Configurations
RD
Selector
WRPORT
P90/S31
to
P97/S24
Output Latch
(P90 to P97)
WRPM
PM90 to PM97
Dual Function
PM : Port mode register
RD : Port 9 read signal
WR : Port 9 write signal
Note:
The LCD controller/driver segment signal output is only valid on the µPD1615 and the
µPD16F15.
86
µPD1615, µPD16F15, µPD1616
4.2.6 Port 10
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in
1-bit units with a port mode register 10.
These pins are dual function pins and serve as segment signal output of LCD controller driver. The
dual-function can be specified with the port function register 10 (PF10).
RESET input sets port 10 to input mode.
Figure 4-7 shows a block diagram of port 10.
Caution: When used as segment lines, set the port function PF9 according to its functions.
Figure 4-7: P100 to P107 Configurations
RD
Selector
WRPORT
P100/S23
to
Output Latch
(P100 to P107)
P107/S16
WRPM
PM100 to PM107
Dual Function
PM : Port mode register
RD : Port 10 read signal
WR : Port 10 write signal
Note:
The LCD controller/driver segment signal output is only valid on the µPD1615 and the
µPD16F15.
87
µPD1615, µPD16F15, µPD1616
4.2.7 Port 11
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in
1-bit units with a port mode register 11.
These pins are dual function pins and serve as segment signal output of LCD controller driver. The
dual-function can be specified with the port function register 11 (PF11).
RESET input sets port 11 to input mode.
Figure 4-8 shows a block diagram of port 11.
Figure 4-8: P110 to P117 Configurations
RD
Selector
WRPORT
P110/S15
to
Output Latch
(P110 to P117)
P117/S8
WRPM
PM110 to PM117
Dual Function
PM : Port mode register
RD : Port 11 read signal
WR : Port 11 write signal
Note:
The LCD controller/driver segment signal output is only valid on the µPD1615 and the
µPD16F15.
88
µPD1615, µPD16F15, µPD1616
4.2.8 Port 12
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in
1-bit units with a port mode register 12.
These pins are dual function pins and serve as segment signal output of LCD controller driver. The
dual-function can be specified with the port function register 12 (PF12).
RESET input sets port 12 to input mode.
Figure 4-9 shows a block diagram of port 12.
Figure 4-9: P120 to P127 Configurations
RD
Selector
P120/PCL//S7,
P121/TI00/TO0/S6,
WRPORT
P122/TI01/S5,
Output Latch
P123/RxD0/S4,
(P120 to P127)
P124/TxD0/S3,
P125/SCK3/S2,
P126/SO3/S1,
P127/SI3/S0
WRPM
PM120 to PM127
Dual Function
PM : Port mode register
RD : Port 12 read signal
WR : Port 12 write signal
Note:
The LCD controller/driver segment signal output is only valid on the µPD1615 and the
µPD16F15.
89
µPD1615, µPD16F15, µPD1616
4.3 Port Function Control Registers
The following four types of registers control the ports.
• Port mode registers (PM0, PM4, PM8 to PM12)
• Port function registers (PFm : m = 8 to 12)
(1) Port mode registers (PM0, PM4, PM8 to PM12)
These registers are used to set port input/output in 1-bit units.
PM0, PM4, PM7, PM10 and PM12 are independently set with a 1-bit or 8-bit memory manipulation
instruction.
RESET input sets registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch
according to the function.
Cautions: 1. Pins P10 to P13 are input-only pins.
2. As port 0 has an alternate function as external interrupt request input, when the
port function output mode is specified and the output level is changed, the interrupt
request flag is set. When the output mode is used, therefore, the interrupt mask
flag should be set to 1 beforehand.
90
µPD1615, µPD16F15, µPD1616
Figure 4-10: Port Mode Register Format
Symbol
PM0
7
6
5
1
4
1
3
1
2
1
0
Address After Reset R/W
FF20H
FF24H
FF28H
FF29H
FF2AH
FF2BH
FF2CH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PM07
PM06
PM02
PM01
PM00
PM4
PM8
PM47
PM87
PM97
PM46
PM86
PM96
PM45
PM85
PM95
PM44
PM84
PM94
PM43
PM83
PM93
PM42
PM82
PM92
PM41
PM81
PM91
PM40
PM80
PM90
PM9
PM10
PM11
PM12
PM107 PM106 PM105 PM104 PM103 PM102 PM101 PM100
PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110
PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PMmn
PMmn Pin Input/Output Mode
Selection (m = 0 - 4, 8, 12; n = 0 – 7)
Output mode (output buffer ON)
Input mode (output buffer OFF)
0
1
91
µPD1615, µPD16F15, µPD1616
3) Port function register (PF8 to PF12)
This register is used to set LCD segment function of ports 8 to 12.
PF8 to PF12 are set with an 1-bit or 8-bit manipulation instruction.
RESET input set this registors to 00H.
Figure 4-11: Port Function Register (PF8 to PF12) Format
PF8
PF9
PF87
PF97
PF86
PF96
PF85
PF95
PF84
PF94
PF83
PF93
PF82
PF92
PF81
PF91
PF80
PF90
FF58H
FF59H
FF5AH
FF5BH
FF5CH
00H
00H
00H
00H
00H
R/W
R/W
R/W
R/W
R/W
PF10
PF11
PF12
PF107
PF117
PF127
PF106
PF116
PF126
PF105
PF115
PF125
PF104
PF114
PF124
PF103
PF113
PF123
PF102
PF112
PF122
PF101
PF111
PF121
PF100
PF110
PF120
PMmn
PFmn Port Function Selection
(m = 8 to 12; n = 0 to 7)
Port function
0
1
LCD segment function
Caution: For µPD1616 it is only allowed to set 00h to the port function register.
92
µPD1615, µPD16F15, µPD1616
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to input/output port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output
from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the
pin status does not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
Caution: In the case of 1-bit memory manipulation instruction, although a single bit is
manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture
of input and output pins, the output latch contents for pins specified as input are
undefined except for the manipulated bit.
4.4.2 Reading from input/output port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
T he pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on input/output port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch.
The output latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is OFF, the pin status does not
change.
Caution: In the case of 1-bit memory manipulation instruction, although a single bit is
manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture
of input and output pins, the output latch contents for pins specified as input are
undefined, even for bits other than the manipulated bit.
93
µPD1615, µPD16F15, µPD1616
[Memo]
94
µPD1615, µPD16F15, µPD1616
Chapter 5 Clock Generator
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The
following two types of system clock oscillators are available.
(1) Main system clock oscillator
This circuit oscillates at frequencies of 3.9 to 8.1 MHz. Oscillation can be stopped by executing the
STOP instruction or setting the processor clock control register.
(2) Subsystem clock oscillator
The circuit oscillates at a typical frequency of 40 kHz. Oscillation cannot be stopped.
95
µPD1615, µPD16F15, µPD1616
5.2 Clock Generator Configuration
The clock generator consists of the following hardware.
Table 5-1: Clock Generator Configuration
Item
Configuration
Processor clock control register (PCC)
Main system clock oscillator
Subsystem clock oscillator
Control register
Oscillator
Figure 5-1: Block Diagram of Clock Generator
CL1
CL2
f
XT
Subsystem
Clock
Oscillator
Watch Timer
Prescaler
Clock to
Peripheral
Hardware
1/2
f
X1
X2
Main
System
Clock
f
X
Prescaler
XT
f
X
2
Oscillator
f
X
f
X
f
X
f
X
24
22 23
Standby
Control
Circuit
2
CPU Clock
(fCPU
)
3
STOP
MCC
CLS CSS
PCC2
PCC0
PCC1
ProcessorClock
ControlRegister
Internal Bus
96
µPD1615, µPD16F15, µPD1616
5.3 Clock Generator Control Register
The clock generator is controlled by the processor clock control register (PCC).
(1) Processor clock control register (PCC)
The PCC selects a CPU clock and the division ratio, determines whether to make the main system
clock oscillator operate or stop.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Figure 5-2: Processor Clock Control Register Format
Symbol
PCC
7
6
0
5
4
3
0
2
1
0
Address After Reset R/W
FFFBH 04H
R/W Note 1
MCC
CLS
CSS
PCC2
PCC1
PCC0
R/W
CSS
0
PCC2
PCC1
PCC0
CPU Clock Selection (fCPU)
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
fX (0.25 µs)
fX/2 (0.5 µs)
fX/22 (1 µs)
fX/23 (2 µs)
fX/24 (4 µs)
1
fXT/2 (122 µs)
Other than above
Setting prohibited
CPU Clock Status
R
CLS
0
Main system clock
Subsystem clock
1
R/W
MCC
Main System Clock Oscillation Control
Oscillation enable
Oscillation stopped
0
1
Notes:
1. Bit 5 is a read-only bit.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Cautions: 1. Bit 3 must be set to 0.
2. When external clock input is used MCC should not be set, because the X2 pin is
connected to VDD via a resistor.
Remarks: 1. fX
: Main system clock oscillation frequency
2. fXT : Subsystem clock oscillation frequency
3. Figures in parentheses indicate minimum instruction execution time: 2fCPU when oper-
ating at fX = 8.0 MHz or fXT = 32.768 kHz.
97
µPD1615, µPD16F15, µPD1616
5.4 System Clock Oscillator
5.4.1 Main system clock oscillator
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard:
8.0 MHz) connected to the X1 and X2 pins.
External clocks can be input to the main system clock oscillator. In this case, the clock signal to
the X1 pin and an inversed phase clock signal to the X2 pin.
Figure 6-3 shows an external circuit of the main system clock oscillator.
Figure 5-3: External Circuit of Main System Clock Oscillator
(a) Crystal and ceramic oscillation
(b) External clock
IC
X2
X2
X1
External
Clock
X1
PD74HCU04
µ
Crystal or
Ceramic
Resonator
Caution: Do not execute the STOP instruction and do not set MCC [bit 7 of processor clock
control register (PCC)] to 1 if an external clock is input. This is because when the
STOP instruction or MCC is set to 1, the main system clock operation stops and the
X2 pin is connected to VDD1 via a pull-up resistor.
98
µPD1615, µPD16F15, µPD1616
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a RC-resonator (standard: 40kHz) connected to the CL1
and CL2 pins.
External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to
the CL1 pin and open the CL2 pin.
Figure 5-4 shows an external circuit of the subsystem clock oscillator.
Figure 5-4: External Circuit of Subsystem Clock Oscillator
(a) RC oscillation
(b) External clock
CL2
CL2
R
CL1
C
External
Clock
CL1
Caution:
When using a main system clock oscillator and a subsystem clock oscillator, carry
out wiring in the broken-line area in Figures 6-3 and 6-4 as follows to prevent any
effects from wiring capacities.
• Minimize the wiring length.
• Do not allow wiring to intersect with other signal conductors. Do not allow wiring
to come near abruptly changing high current.
• Set the potential of the grounding position of the oscillator capacitor to that of
VSS. Do not ground to any ground pattern where high current is present.
• Do not fetch signals from the oscillator.
Take special note of the fact that the subsystem clock oscillator is a circuit with
low-level amplification so that current consumption is maintained at low levels.
Figure 5-5 shows examples of oscillator having bad connection.
99
µPD1615, µPD16F15, µPD1616
Figure 5-5: Examples of Oscillator with Bad Connection (1/3)
(a) Wiring of connection
circuits is too long
(b) A signal line crosses over
oscillation circuit lines
PORTn
(n = 0, 4, 8 to 12)
IC
X2
X1
IC
X2
X1
Figure 5-5: Examples of Oscillator with Bad Connection (2/3)
(c) Changing high current is too near a
signal conductor
(d) Current flows through the grounding line
of the oscillator (potential at points A, B,
and C fluctuate)
V
DD
Pnm
IC
X2
X1
IC
X2
X1
High
Current
A
B
C
High
Current
100
µPD1615, µPD16F15, µPD1616
Figure 5-5: Examples of Oscillator with Bad Connection (3/3)
(e) Signals are fetched
(f) Signal conductors of the main and sub-
system clock are parallel and near
each other
IC
X2
X1
IC
X2
X1
CL2
CL1
CL1 and CL2 are wiring in parallel
Caution: In Figure 6-5 (f), CL1 and X1 are wired in parallel. Thus, the cross-talk noise of X1
may increase with CL1, resulting in malfunctioning. To prevent that from occurring,
it is recommended to wire CL1 and X1 so that they are not in parallel, and to connect
the IC pin between CL1 and X1 directly to VSS
.
5.4.3 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock
operations, connect the CL1 and CL2 pins as follows.
CL1: Connect to VDD or GND
CL2: Open
101
µPD1615, µPD16F15, µPD1616
5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating
mode including the standby mode.
• Main system clock fX
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock
control register (PCC).
(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (4 µs when
operated at 8.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while low
level is applied to RESET pin.
2
3
(b) With the main system clock selected, one of the five CPU clock stages (fX, fX/2, fX/2 , fX/2 or
4
fX/2 ) can be selected by setting the PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are
available.
(d) The PCC can be used to select the subsystem clock and to operate the system with low current
consumption (122 µs when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC.
The HALT mode can be used. However, the STOP mode cannot be used. (Subsystem clock
oscillation cannot be stopped.)
102
µPD1615, µPD16F15, µPD1616
5.5.1 Main system clock operations
When operated with the main system clock (with bit 5 (CLS) of the processor clock control register
(PCC) set to 0), the following operations are carried out by PCC setting.
(a) Because the operation guarantee instruction execution speed depends on the power supply
voltage, the instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
(b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system
clock oscillation does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation
is switched to subsystem clock operation (CLS = 1) after that, the main system clock
oscillation stops (see Figure 6-6).
Figure 5-6: Main System Clock Stop Function (1/2)
(a) Operation when MCC is set after setting CSS with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
(b) Operation when MCC is set in case of main system clock operation
MCC
L
CSS
L
CLS
Oscillation does not stop.
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
103
µPD1615, µPD16F15, µPD1616
Figure 5-6: Main System Clock Stop Function (2/2)
(c) Operation when CSS is set after setting MCC with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
5.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register
(PCC) set to 1), the following operations are carried out.
(a) The instruction execution time remains constant (122 µs when operated at 32.768 kHz)
irrespective of bits 0 to 2 (PCC0 to PCC2) of the PCC.
(b) Watchdog timer counting stops.
Caution: Do not execute the STOP instruction while the subsystem clock is in operation.
104
µPD1615, µPD16F15, µPD1616
5.6 Changing System Clock and CPU Clock Settings
5.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2)
and bit 4 (CSS) of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation
continues on the pre-switchover clock for several instructions (see Table 5-2).
Determination as to whether the system is operating on the main system clock or the subsystem clock
is performed by bit 5 (CLS) of the PCC register.
Table 5-2: Maximum Time Required for CPU Clock Switchover
Set Values after Switchover
Set Values before Switchover
MCS CSS PCC2 PCC1 PCC0 CSS PCC2PCC1PCC0 CSS PCC2PCC1PCC0 CSS PCC2PCC1 PCC0 CSS PCC2PCC1PCC0 CSS PCC2PCC1PCC0 CSS PCC2 PCC1PCC0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
X
X
X
X
0
0
0
0
0
1
X
0
0
1
1
0
X
0
1
0
1
0
X
8 instructions 4 instructions 2 instructions 1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
16 instructions
4 instructions 2 instructions 1 instruction
16 instructions 8 instructions
2 instructions 1 instruction
1 instruction
16 instructions 8 instructions 4 instructions
16 instructions 8 instructions 4 instructions 2 instructions
1
0
1
fX/2fXT instruction fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction
(77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions)
fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction fX/64fXT instruction
(39 instructions) (20 instructions) (10 instructions) (5 instructions)
(3 instructions)
Caution: Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from
the main system clock to the subsystem clock (changing CSS from 0 to 1) should not
be performed simultaneously. Simultaneous setting is possible, however, for selec-
tion of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the
subsystem clock to the main system clock (changing CSS from 1 to 0).
Remarks: 1. One instruction is the minimum instruction execution time with the pre-switchover CPU
clock.
105
µPD1615, µPD16F15, µPD1616
5.6.2 System clock and CPU clock switching procedure
This section describes switching procedure between system clock and CPU clock.
Figure 5-7: System Clock and CPU Clock Switching
VDD
RESET
Interrupt
Request
Signal
f
X
f
X
f
XT
f
X
SystemClock
CPUClock
Minimum Maximum Speed
Speed
Subsystem Clock
Operation
High-Speed
Operation
Operation
Operation
Wait (16.3 ms: 8.0 MHz)
Internal Reset Operation
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset
is released by setting the RESET signal to high level, main system clock starts oscillation. At this
17
time, oscillation stabilization time (2 /fX) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock
(4 µs when operated at 8.0 MHz).
(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum
speeds, the processor clock control register (PCC) is rewritten and the maximum-speed operation
is carried out.
(3) Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system
clock is switched to the subsystem clock (which must be in an oscillation stable state).
(4) Upon detection of VDD voltage reset due to an interrupt request signal, 0 is set to bit 7 (MCC) of
PCC and oscillation of the main system clock is started. After the lapse of time required for
stabilization of oscillation, the PCC is rewritten and the maximum-speed operation is resumed.
Caution:
When subsystem clock is being operated while main system clock was stopped, if
switching to the main system clock is made again, be sure to switch after securing
oscillation stable time by software.
106
µPD1615, µPD16F15, µPD1616
[Memo]
107
µPD1615, µPD16F15, µPD1616
Chapter 6 16-Bit Timer/ Event Counter
6.1 16-bit Timer/Event Counter Function
16-bit timer/event counter (TM0) has the following functions:
• Interval timer
• PPG output
• Pulse width measurement
• External event counter
• Square wave output
• One-shot pulse output
(1) Interval timer
When 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at
predetermined time intervals.
(2) PPG output
16-bit timer/event counter can output a square wave whose frequency and output pulse width can be
freely set.
(3) Pulse width measurement
16-bit timer/event counter can be used to measure the pulse width of a signal input from an external
source.
(4) External event counter
16-bit timer/event counter can be used to measure the number of pulses of a signal input from an
external source.
(5) Square wave output
16-bit timer/event counter can output a square wave any frequency.
(6) One-shot pulse output
16-bit timer/event counter can output a one-shot pulse with any output pulse width.
108
µPD1615, µPD16F15, µPD1616
6.2 16-bit Timer/Event Counter Configuration
16-bit timer/event counter (TM0) consists of the following hardware:
Table 6-1: Configuration of 16-bit Timer/Event Counter (TM0)
Item
Timer register
Register
Configuration
16 bits x 1 (TM0)
Capture/compare register: 16 bits x 2 (CR00, CR01)
1 (TO0)
Timer output
16-bit timer mode control register (TMC0)
Capture/compare register 0 (CRC0)
16-bit timer output control register (TOC0)
Prescaler mode register 0 (PRM0)
Port mode register 12 (PM12)
Control register
Figure 6-1: Block Diagram of 16-Bit Timer/Event Counter (TM0)
Internal bus
Capture/compare
control register 0
(CRC0)
CRC02 CRC01CRC00
INTTM00
Noise
rejection
circuit
16-bit capture/compare
register 00 (CR00)
P122/
TI01/
S5
Coincidence
fx/21
fx/23
fx/26
16-bit timer register (TM0)
Clear
Output
control
circuit
TO0/P121/TI00/S6
Coincidence
Noise
rejection
circuit
fx/2
2
Noise
rejection
circuit
16-bit capture/compare
register 01 (CR01)
P121/
TI00/
TO0/
S6
INTTM01
CRC02
OSPE TOC04
TOC01 TOE0
LVS0 LVR0
OSPT
PRM01PRM00
TMC03TMC02TMC01 OVF0
Internal bus
Timermode
control register (TMC0)
Prescaler mode
register 0 (PRM0)
Timer output control
register (TOC0)
109
µPD1615, µPD16F15, µPD1616
1) 16-bit timer register (TM0)
TM0 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of an input clock. If the count value
is read during operation, input of the count clock is temporarily stopped, and the count value at that point
is read. The count value is reset to 0000H in the following cases:
<1> RESET is input.
<2> TMC03 and TMC02 are cleared.
<3> Valid edge of TI00 is input in the clear & start mode by inputting valid edge of TI00.
<4> TM0 and CR00 coincide with each other in the clear & start mode on coincidence between TM0
and CR00.
<5> Bit 6 of TOC0 (OSPT) is set or if the valid edge of TI00 is input in the one-shot pulse output mode.
110
µPD1615, µPD16F15, µPD1616
2) Capture/compare register 00 (CR00)
CR00 is a 16-bit register that functions as a capture register and as a compare register. Whether
this register functions as a capture or compare register is specified by using bit 0 (CRC00) of the
capture/compare control register 0.
• When using CR00 as compare register
The value set to CR00 is always compared with the count value of the 16-bit timer register (TM0).
When the values of the two coincide, an interrupt request (INTTM00) is generated. When TM00
is used as an interval timer, CR00 can also be used as a register that includes the interval time.
• When using CR00 as capture register
The valid edge of the TI00 or TI01 pin can be selected as a capture trigger. The valid edge of TI00
and TI01 is performed via the prescaler mode register 0 (PRM0).
Tables 6-2 and 6-3 show the conditions that apply when the capture trigger is specified as the valid
edge of the TI00 pin and the valid edge of the TI01 pin respectively.
Table 6-2: Valid Edge of TI00 Pin and Valid Edge of Capture Trigger of Capture/Compare Register
ES01
ES00
Valid Edge of TI00 Pin
Falling edge
Capture Trigger of CR00
Rising edge
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Setting prohibited
Both rising and falling edges
Setting prohibited
No capture operation
Table 6-3: Valid Edge of TI01 Pin and Valid Edge of Capture Trigger of Capture/Compare Register
ES01
ES00
Valid Edge of TI01 Pin
Falling edge
Capture Trigger of CR00
Rising edge
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Setting prohibited
Both rising and falling edges
Setting prohibited
Both rising and falling edges
CR00 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Caution: Set a value other than 0000H in CR00. This means, that an 1-pulse count operation
cannot be performed when CR00 is used as an event counter.
111
µPD1615, µPD16F15, µPD1616
(3) Capture/compare register 01 (CR01)
This is a 16-bit register that can be used as a capture register and a compare register. Whether it
is used as a capture register or compare register is specified by bit 2 of the capture/compare control
register 0 (CRC0).
• When using CR01 as compare register
The value set to CR01 is always compared with the count value of the 16-bit timer register (TM0).
When the values of the two coincide, an interrupt request (INTTM01) is generated.
• When using CR01 as capture register
The valid edge of the TI00 pin can be selected as a capture trigger. The valid edge of TI00 is
specified by using the prescaler mode register 0 (PRM0).
CR01 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Caution: Set a value other than 0000H in CR01. This means, that an 1-pulse count operation
cannot be performed when CR01 is used as an event counter.
112
µPD1615, µPD16F15, µPD1616
6.3 16-Bit Timer/Event Counter Control Register
The following four types of registers control 16-bit timer/event counter (TM0).
• 16-bit timer mode control register (TMC0)
• Capture/compare control register (CRC0)
• 16-bit timer output control register (TOC0)
• Prescaler mode register 0 (PRM0)
• Port mode register 12 (PM12)
(1) 16-bit timer mode control register (TMC0)
This register specifies the operation mode of the 16-bit timer and the clear mode, output timing, and
overflow detection of the 16-bit timer register.
TMC0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC0 to 00H.
Caution: The 16-bit timer register starts operating when a value other than 0, 0 (operation stop
mode) is set to TMC02 and TMC03. To stop the operation, set 0, 0 to TMC02 and
TMC03.
113
µPD1615, µPD16F15, µPD1616
Figure 6-2: Format of 16-Bit Timer Mode Control Register (TMC0)
Address: FF60H After Reset: 00H R/W
Symbol
TMC0
7
0
6
0
5
0
4
0
3
2
1
0
TMC03
TMC02
TMC01
OVF0
Operating Mode
Clear mode and
clear mode
Selection of TO0 Generation of
TMC03
TMC02
TMC01
output timing
interrupt
Operation stop
(TM0 is cleared
to 0).
Not affected
Does not
generate.
0
0
0
0
0
1
0
1
0
Coincidence
between TM0
and CR00 or
coincidence
between TM0
andCR01
Free running
mode
Generates on
coincidence
between TM0
and CR00 and
coincidence
between TM0
and CR01.
Coincidence
between TM0
and CR00,
coincidence
between TM0
and CR01, or
valid edge of
TI00
0
1
1
Coincidence
between TM0
and CR00 or
coincidence
between TM0
andCR01
1
1
0
0
0
1
Clears and
starts at valid
edge of TI00.
Coincidence
between TM0
and CR00,
coincidence
between TM0
and CR01, or
valid edge of
TI00
Coincidence
between TM0
and CR00 or
coincidence
between TM0
andCR01
1
1
1
1
0
1
Clears and
starts on
coincidence
between TM0
and CR00.
Coincidence
between TM0
and CR00,
coincidence
between TM0
and CR01, or
valid edge of
TI00
0VF0
Detection of overflow of 16-bit timer register
0
1
Overflows.
Does not overflow.
114
µPD1615, µPD16F15, µPD1616
Cautions 1. Before changing the clear mode and TO0 output timing, be sure to stop the timer
operation (reset TMC02 and TMC03 to 0, 0).
2. The valid edge of the TI00 pin is selected by using the prescaler mode register 0
(PRM0).
3. When a mode in which the timer is cleared and started on coincidence between TM0
and CR00, the OVF0 flag is set to 1 when the count value of TM0 changes from FFFFH
to 0000H with CR00 set to FFFFH.
Remark:
T00 : output pin of 16-bit timer/counter (TM0)
TI00 : input pin of 16-bit timer/counter (TM0)
TM0 : 16-bit timer register
CR00: compare register 00
CR01: compare register 01
115
µPD1615, µPD16F15, µPD1616
(2) Capture/compare control register 0 (CRC0)
This register controls the operation of the capture/compare registers (CR00 and CR01).
CRC0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CRC0 to 00H.
Figure 6-3: Format of Capture/Compare Control Register 0 (CRC0)
Address: FF62H After Reset: 00H R/W
Symbol
CRC0
7
0
6
0
5
0
4
0
3
0
2
1
0
CRC02
CRC01
CRC00
CRC02
Selection of operation mode of CR01
0
1
Operates as compare register
Operates as capture register
CRC01
Selection of capture trigger of CR00
0
1
Captured at valid edge of TI01
Captured in reverse phase of valid edge of TI00
CRC00
Selection of operation mode of CR00
Operates as compare register
0
1
Operates as capture register
Cautions: 1. Before setting CRC0, be sure to stop the timer operation.
2. When the mode in which the timer is cleared and started on coincidence between
TM0 and CR00 is selected by the 16-bit timer mode control register (TMC0), do not
specify CR00 as a capture register.
3. If valid edge of TI00 is both falling and rising, the capture operation is not available
when CRC01 = 1.
116
µPD1615, µPD16F15, µPD1616
(3) 16-bit timer output control register (TOC0)
This register controls the operation of the 16-bit timer/event counter (TM0) output control circuit by
setting or resetting the R-S flip-flop, enabling or disabling reverse output, enabling or disabling output
of 16-bit timer/counter (TM0), enabling or disabling one-shot pulse output operation, and selecting an
output trigger for a one-shot pulse by software.
TOC0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TOC0 to 00H.
Figure 6-4 shows the format of TOC0.
Figure 6-4: Format of 16-Bit Timer Output Control Register (TOC0)
Address: FF63H After Reset: 00H R/W
Symbol
TOC0
7
0
6
5
4
3
2
1
0
OSPT
OSPE
TOC04
LVS0
LVR0
TOC01
TOE0
OSPT
Output trigger control of one-shot pulse by software
0
1
No one-shot pulse trigger
Uses one-shot pulse trigger
OSPE
Controls of one-shot pulse output operation
0
1
Continuous pulse output
One-shot pulse output
TOC04
Timer output F/F control on coincidence between CR01 and TM0
0
1
Disables inversion timer output
Enables inversion timer output
LVS0
LVR0
Set status of timer output F/F of 16-bit timer/counter (TM0)
Not affected
0
0
1
1
0
1
0
1
Resets timer output F/F (0)
Sets timer output F/F (1)
Setting prohibited
TOC01
Timer output F/F control on coincidence between CR00 and TM0
Disables inversion timer output F/F
0
1
Enables inversion timer output F/F
TOE0
Output control of 16-bit timer/counter (TM0)
Disables output (port mode)
0
1
Enables output
Cautions: 1. Before setting TOC0, be sure to stop the timer operation.
2. LVS0 and LVR0 are 0 when read after data have been set to them.
3. OSPT is 0 when read because it is automatically cleared after data has been set.
117
µPD1615, µPD16F15, µPD1616
(4) Prescaler mode register 0 (PRM0)
This register selects a count clock of the 16-bit timer/event counter (TM0) and the valid edge of TI00,
TI01 input. PRM0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PRM0 to 00H.
Figure 6-5: Format of Prescaler Mode Register 0 (PRM0)
Address: FF61H
Symbol
After Reset : 00H
R/W
5
7
6
4
3
0
2
0
1
0
PRM0
ES11
ES10
ES01
ES00
PRM01
PRM00
ES11
ES10
Selection of valid edge of TI01
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES01
ES00
Selection of valid edge of TI00
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
PRM01
PRM00
Selection of count clock
1
0
0
1
1
0
1
0
1
fX/2 (4.00 MHz)
3
fX/2 (1.00 MHz)
6
fX/2 (125 KHz)
Valid edge of TI00
Caution: When selecting the valid edge of TI00 as the count clock, do not specify the valid
edge of TI00 to clear and start the timer and as a capture trigger.
Remark:
Figures in parentheses apply to operation with fX = 8.00 MHz.
118
µPD1615, µPD16F15, µPD1616
(5) Port mode register 12 (PM12)
This register sets port 12 input/output in 1-bit units.
When using the P121/TO0/TI00/S6 pin for timer output, set PM121 and the output latch of P121
to 0.
PM12 is set with an 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM12 value to FFH.
Figure 6-6: Port Mode Register 12 (PM12) Format
Symbol
PM12
7
6
5
4
3
2
1
0
Address After Reset R/W
FF2CH FFH R/W
PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PM12n
P12n pin input/output mode selection (n = 0 to 7)
Output mode (output buffer ON)
Input mode (output buffer OFF)
0
1
(6) Port function register 12 (PM12)
This register sets the port function of port 12 in 1-bit units.
When using the timer for timer output or timer input, the register PF12 has to be set to port function.
PM12 is set with an 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM12 value to 00H.
Figure 6-7: Port Function Register 12 (PM12) Format
Symbol
PF12
7
6
5
4
3
2
1
0
Address After Reset R/W
FF5CH 00H R/W
PF127
PF126
PF125
PF124
PF123
PF122
PF121
PF120
PF12n
P12n function selection (n = 0 to 7)
Port mode
LCD mode
0
1
Note:
For the µPD1616 set always 00H to PF12.
119
µPD1615, µPD16F15, µPD1616
6.4 16-Bit Timer/Event Counter Operations
6.4.1 Operation as interval timer (16 bits)
The 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control
register (TMC0) and capture/compare control register 0 (CRC0) are set as shown in Figure 6-8.
In this case, 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified
by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
When the count value of the 16-bit timer register (TM0) coincides with the set value of CR00, the value
of TM0 is cleared to 0, and the timer continues counting. At the same time, an interrupt request signal
(INTTM00) is generated.
The count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (PRM00 and PRM01)
of the prescaler mode register 0 (PRM0).
Figure 6-8: Control Register Settings When Timer 0 Operates as Interval Timer
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clears and starts on
coincidence between
TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 as compare
register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the interval timer function. For details, refer to Figures 6-2 and 6-3.
120
µPD1615, µPD16F15, µPD1616
Figure 6-9: Configuration of Interval Timer
16-bit capture/compare
register 00 (CR00)
fx/21
fx/23
fx/26
TI01
INTTM00
OVF0
16-bit timer register (TM0)
Clear circuit
Figure 6-10: Timing of Interval Timer Operation
t
Count clock
TM0 count value
CR00
0001H
0000H 0001H
Count starts
N
0001H
N
N
0000H
Clear
0000H
Clear
N
N
N
N
INTTM00
Interrupt accepted
Interrupt accepted
Interval time
Interval time
Interval time
Remark:
Interval time = (N+1) x t: N = 0000H to FFFFH
121
µPD1615, µPD16F15, µPD1616
6.4.2 PPG output operation
The 16-bit timer/counter can be used for PPG (Programmable Pulse Generator) output by setting the
16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown
in Figure 6-11.
The PPG output function outputs a rectangular wave with a cycle specified by the count value set
in advance to the 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count
value set in advance to the 16-bit capture/compare register 01 (CR01).
Figure 6-11: Control Register Settings in PPG Output Operation
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0
0
Clears and starts on
coincidence between
TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
X
0
CR00 as compare register
CR01 as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOC0
0
0
0
1
0/1
0/1
1
1
Enables TO0 output
Reverses output on coincidence
between TM0 and CR00
Specifies initial value of
TO0 output F/F
Reverses output on coincidence
between TM0 and CR01
Disables one-shot pulse output
Remark:
x
: don’t care
on : can be used for other functions
Caution: Make sure that 0000H ≤ CR01 < CR00 ≤ FFFFH is set to CR00 and CR01.
122
µPD1615, µPD16F15, µPD1616
6.4.3 Pulse width measurement
The 16-bit timer register (TM0) can be used to measure the pulse widths of the signals input to the
TI00 and TI01 pins.
Measurement can be carried out with TM0 used as a free running counter or by restarting the timer
in synchronization with the edge of the signal input to the TI00 pin.
(1) Pulse width measurement with free running counter and one capture register
If the edge specified by the prescaler mode register 0 (PRM0) is input to the TI00 pin when the 16-
bit timer register (TM0) is used as a free running counter (refer to Figure 6-12), the value of TM0 is
loaded to the 16-bit capture/compare register 01 (CR01), and an external interrupt request signal
(INTTM01) is set.
The edge is specified by using bits 6 and 7 (ES10 and ES11) of the prescaler mode register 0 (PRM0).
The rising edge, falling edge, or both the rising and falling edges can be selected.
The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode
register 0n (PRM0), and the capture operation is not performed until the valid level is detected two times.
Therefore, noise with a short pulse width can be rejected.
Figure 6-12: Control Register Settings for Pulse Width Measurement with Free Running Counter
and One Capture Register
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0/1
0
CR00 as compare register
CR01 as capture register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the pulse width measurement function. For details, refer to Figures 6-2 and 6-3.
123
µPD1615, µPD16F15, µPD1616
Figure 6-13: Configuration for Pulse Width Measurement with Free Running Counter
fx/21
fx/23
fx/26
OVF0
16-bit timer register (TM0)
16-bit capture/compare register 01
(CR01)
TI00
INTTM00
Internal bus
Figure 6-14: Timing of Pulse Width Measurement with Free Running Counter and One Capture
Register (with both edges specified)
t
Count clock
TM0 count value
TI00 pin input
0000H 0001H
D0
D1
FFFFH
D2
D3
0000H
Value loaded
to CR01
D0
D1
D2
D3
INTTM00
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
124
µPD1615, µPD16F15, µPD1616
(2) Measurement of two pulse widths with free running counter
The pulse widths of the two signals respectively input to the TI00 and TI01 pins can be measured when
the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 6-14).
When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0)
is input to the TI00 pin, the value of the TM0 is loaded to the 16-bit capture/compare register 01 (CR01)
and an external interrupt request signal (INTTM01) is set.
When the edge specified by bits 6 and 7 (ES10 and ES11) of the prescaler mode register 0 (PRM0)
is input to the TI01 pin, the value of TM0 is loaded to the 16-bit capture/compare register 00 (CR00),
and an external interrupt request signal (INTTM00) is set.
The edges of the TI00 and TI01 pins are specified by bits 4 and 5 (ES00 and ES01) and bits 6 and
7 (ES10 and ES11) of PRM0, respectively. The rising, falling, or both rising and falling edges can be
specified.
The valid edge of TI00 pin and TI01 pin is detected through sampling at a count clock cycle selected
by the prescaler mode register 0 (PRM0), and the capture operation is not performed until the valid level
is detected two times. Therefore, noise with a short pulse width can be rejected.
Figure 6-15: Control Register Settings for Measurement of Two Pulse Widths with Free Running
Counter
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0
1
CR00 as capture register
Captures valid edge of TI01 pin to CR00.
CR01 as capture register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the pulse width measurement function. For details, refer to Figures 6-2 and 6-3.
125
µPD1615, µPD16F15, µPD1616
• Capture operation (free running mode)
The following figure illustrates the operation of the capture register when the capture trigger is input.
Figure 6-16: CR01 Capture Operation with Rising Edge Specified
Count clock
TM0
n-3
n-2
n-1
n
n+1
TI00
Rising edge detection
n
CR01
INTTM01
Figure 6-17: Timing of Pulse Width Measurement with Free Running Counter (with both edges
specified)
t
Count clock
TM0 count value
TI00 pin input
0000H 0001H
D0
D1
FFFFH 0000H
D2
D3
Value loaded to
CR01
D0
D1
D2
D3
INTTM01
TI01 pin input
Value loaded to
CR00
Note
D1
INTTM00
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
(10000H - D1 + (D2+1)) x t
Note:
D2 + 1
126
µPD1615, µPD16F15, µPD1616
(3) Pulse width measurement with free running counter and two capture registers
When the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 6-17), the pulse
width of the signal input to the TI00 pin can be measured.
When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0)
is input to the TI00 pin, the value of TM0 is loaded to the 16-bit capture/compare register 01 (CR01),
and an external interrupt request signal (INTTM01) is set.
The value of TM0 is also loaded to the 16-bit capture/compare register 00 (CR00) when an edge
reverse to the one that triggers capturing to CR01 is input.
The edge of the TI00 pin is specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register
0 (PRM0). The rising or falling edge can be specified.
The valid edge of TI00 pin and TI01 pin is detected through sampling at a count clock cycle selected
by the prescaler mode register 0 (PRM0), and the capture operation is not performed until the valid level
is detected two times. Therefore, noise with a short pulse width can be rejected.
Caution: If the valid edge of the TI00 pin is specified to be both the rising and falling edges,
the capture/compare register 00 (CR00) cannot perform its capture operation.
Figure 6-18: Control Register Settings for Pulse Width Measurement with Free Running Counter
and Two Capture Registers
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
CR00 as capture register
Captures to CR00 at edge reverse to valid
edge o f TI00 pin.
CR01 as capture register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the pulse width measurement function. For details, refer to Figures 6-2 and 6-3.
127
µPD1615, µPD16F15, µPD1616
Figure 6-19: Timing of Pulse Width Measurement with Free Running Counter and Two Capture
Registers (with rising edge specified)
t
Count clock
TM0 count value
TI00 pin input
0001H
D0
D1
FFFFH 0000H
D2
D3
0000H
Value loaded to
CR01
D0
D2
Value loaded to
CR00
D1
D3
INTTM01
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
128
µPD1615, µPD16F15, µPD1616
(4) Pulse width measurement by restarting
When the valid edge of the TI00 pin is detected, the pulse width of the signal input to the TI00n pin
can be measured by clearing the 16-bit timer register (TM0) once and then resuming counting after
loading the count value of TM0 to the 16-bit capture/compare register 01 (CR01).
The edge of the TI00 pin is specified by bits 4 and 5 (ES00 and ES01) of PRM0. The rising or falling
edge can be specified.
The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode
register 0 (PRM0), and the capture operation is not performed until the valid level is detected two times.
Therefore, noise with a short pulse width can be rejected.
Caution: If the valid edge of the TI00 pin is specified to be both the rising and falling edges,
the capture/compare register 00 (CR00) cannot perform its capture operation.
Figure 6-20: Control Register Settings for Pulse Width Measurement by Restarting
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0/1
0
Clears and starts at valid edge of TI00 pin.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
NCR00 as capture register
Captures to CR00 at edge reverse to
valid edge of TI00.
CR01 as capture register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the pulse width measurement function. For details, refer to Figures 6-2 and 6-3.
129
µPD1615, µPD16F15, µPD1616
Figure 6-21: Timing of Pulse Width Measurement by Restarting (with rising edge specified)
t
Count clock
TM0 count value
TI00 pin input
0000H 0001H
D0 0000H 0001H D1
D2
0001H
0000H
Value loaded to
CR01
D0
D2
Value loaded to
CR00
D1
INTTM01
D1 x 1
D2 x 1
6.4.4 Operation as external event counter
16-bit timer/event counter can be used as an external event counter which counts the number of clock
pulses input to the TI00 pin from an external source by using the 16-bit timer register (TM0).
Each time the valid edge specified by the prescaler mode register 0 (PRM0) has been input to the
TI00 pin, TM0 is incremented.
When the count value of TM0 coincides with the value of the 16-bit capture/compare register 00
(CR00), TM0 is cleared to 0, and an interrupt request signal (INTTM00) is generated.
The edge of the TI00 pin is specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode
register 0 (PRM0). The rising, falling, or both the rising and falling edges can be specified.
The valid edge is detected through sampling at a count clock cycle, selected by the prescaler mode
register 0 (PRM0) and performed until the valid level is detected two times. Therefore, noise with a
short pulse width can be rejected.
130
µPD1615, µPD16F15, µPD1616
Figure 6-22: Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clears and starts on coincidence
between TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 as compare register
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the external event counter function. For details, refer to Figures 6-2 and 6-3.
Figure 6-23: Configuration of External Event Counter
16-bit capture/compare
register (CR00)
INTTM00
Clear
OVF0
Valid edge of TI00
fx/2
16-bit timer register (TM0)
Noise elimination
circuit
16-bit capture/compare
register 01 (CR01)
fx/21
fx/23
fx/26
Internal bus
131
µPD1615, µPD16F15, µPD1616
Figure 6-24: Timing of External Event Counter Operation (with rising edge specified)
TI00 pin input
TM0 count value
CR00
0000H 0001H
0003H
0004H
0005H
N
N - 1
N
0000H
0002H
0001H
0003H
0002H
INTTM00
Caution: Read TM0 when reading the count value of the external event counter.
6.4.5 Operation to output square wave
The 16-bit timer/event counter can be used to output a square wave with any frequency at an interval
specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
By setting bits 0 (TOE0) and 1 (TOC01) of the 16-bit timer output control register to 1, the output status
of the TO0 pin is reversed at an interval specified by the count value set in advance to CR00. In this
way, a square wave of any frequency can be output.
132
µPD1615, µPD16F15, µPD1616
Figure 6-25: Set Contents of Control Registers in Square Wave Output Mode
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clears and starts on coincidence
between TM0 and CR00.
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOC0
0
0
0
0
0/1
0/1
1
1
Enables TO0 output
Reverses output on coincidence
between TM0 and CR00
Specifies initial value of TO0
output F/F
Does not reverse output on coincidence
between TM0 and CR01
Disables one-shot pulse output
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the square wave output function. For details, refer to Figures 6-2, 6-3, and 6-4.
Figure 6-26: Timing of Square Wave Output Operation
Count clock
TM0 count value
0001H
0002H
N - 1
N
0001H 0002H
0000H
N - 1
N
0000H
0000H
CR00
N
INTTM00
TO0 pin output
133
µPD1615, µPD16F15, µPD1616
6.4.6 Operation to output one-shot pulse
16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and
an external trigger (TI00/TO0 pin input).
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO0 pin by setting the 16-bit timer mode control register
(TMC0) and by setting bit 6 (OSPT) of TOC0 by software.
By setting OSPT to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted
active at the count value set in advance to the 16-bit capture/compare register 01 (CR01). After that,
the output is deasserted inactive at the count value set in advance to the 16-bit capture/compare register
00 (CR00).
Even after the one-shot pulse has been output, TM0 continues its operation. To stop TM0, TMC0 must
be reset to 00H.
Caution: Do not set OSPT to 1 while the one-shot pulse is being output. To output the one-
shot pulse again, wait until INTTM00, which occurs on coincidence between TM0 and
CR00, occurs.
134
µPD1615, µPD16F15, µPD1616
Figure 6-27: Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
CRC0
TOC0
0
0
0
0
0
0
1
1
0
0
Clears and starts on coincidence
between TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
0
0
0
0
0
0/1
0
CR00 as compare register
CR01 as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
0
1
1
0/1
0/1
1
1
Enables TO0 output
Reverses output on coincidence
between TM0 and CR00
Specifies initial value of TO0 output F/F
Reverses output on coincidence
between TM0 and CR01
Sets one-shot pulse output mode
Set to 1 for output
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the one-shot pulse output function. For details, refer to Figures 6-2, 6-3, and 6-4.
Caution: Set a value in the following range to CR00 and CR01.
0000H - CR01 < CR00 - FFFFH
135
µPD1615, µPD16F15, µPD1616
Figure 6-28: Timing of One-Shot Pulse Output Operation with Software Trigger
Sets 0CH to TMC0
(TM0 count starts)
Count clock
TM0 count value
CR01 set value
CR00 set value
OSPT
0000H 0001H
N
N + 1
N
N - 1
N
M - 1
M
0000H 0001H 0002H
0000H
N
N
N
M
M
M
M
INTTM01
INTTM00
TO0 pin output
Caution:
The 16-bit timer register starts operating as soon as a value other than 0, 0 (operation
stop mode) has been set to TMC02 and TMC03.
(2) One-shot pulse output with external trigger
A one-shot pulse can be output from the TO0/TI00 pin by setting the 16-bit timer mode control register
(TMC0),capture/comparecontrolregister0(CRC0),and16-bittimeroutputcontrolregister(TOC0)asshown
in Figure 6-28, and by using the valid edge of the TO0/TI00 pin as an external trigger.
The valid edge of the TI00 pin is specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode
register 0 (PRM0). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of the TI00 pin is detected, the 16-bit timer/event counter is cleared and started,
and the output is asserted active at the count value set in advance to the 16-bit capture/compare register
01(CR01).
Afterthat, theoutputisdeassertedinactiveatthecountvaluesetinadvancetothe16-bitcapture/compare
register 00 (CR00).
Caution:
Even if the external trigger is generated again while the one-shot pulse is output, it
is ignored.
136
µPD1615, µPD16F15, µPD1616
Figure 6-29: Control Register Settings for One-Shot Pulse Output with External Trigger
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0
0
Clears and starts at valid edge of TI00/TO0 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
0/1
0
CR00 as compare register
CR01 as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
0/1 0/1
TOC0
0
0
1
1
1
1
Enables TO0 output
Reverses output on coincidence between
TM0 and CR00
Specifies initial value of TO0 output F/F
Reverses output on coincidence between
TM0 and CR01
Set one-shot pulse output mode
Caution: Set a value in the following range to CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark:
0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with
the one-shot pulse output function. For details, refer to Figures 6-2, 6-3, and 6-4.
137
µPD1615, µPD16F15, µPD1616
Figure 6-30: Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge
specified)
Sets 08H to TMC0
(TM0 count starts)
Count clock
TM0 count value
CR01 set value
CR00 set value
TI00 pin input
INTTM01
0000
0001
0000
N
N
N+1 N+2
M-2 M-1
M
N
M+1 M+2 M+3
N
N
M
M
M
M
INTTM00
TO0 pin output
Caution: The 16-bit timer register starts operating as soon as a value other than 0, 0 (operation
stop mode) has been set to TMC02 and TMC03.
138
µPD1615, µPD16F15, µPD1616
6.5 16-Bit Timer/Event Counter Operating Precautions
(1) Error on starting timer
An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been
started.
This is because the 16-bit timer register (TM0) is started asynchronously in respect to the count pulse.
Figure 6-31: Start Timing of 16-Bit Timer Register
Count pulses
0000H
0001H
0002H
0003H
0004H
TM0 count value
Timer starts
(2) 16-bit compare register setting
Set another value than 0000H to the 16-bit captured compare register CR00, CR01. This means, that
a 1-pulse count operation cannot be performed, when it is used as event counter.
(3) Setting compare register during timer count operation
If the value to which the current value of the 16-bit capture/compare register 00 (CR00) has been
changed is less than the value of the 16-bit timer register (TM0), TM0 continues counting, overflows,
and starts counting again from 0. If the new value of CR00 (M) is less than the old value (N), the timer
must be restarted after the value of CR00 has been changed.
Figure 6-32: Timing after Changing Compare Register during Timer Count Operation
Count pulse
N
M
CR00
X - 1
X
FFFFH
0000H
0001H
0002H
TM0 count
Remark:
N > X > M
139
µPD1615, µPD16F15, µPD1616
(4) Data hold timing of capture register
If the valid edge is input to the TI00 pin while the 16-bit capture/compare register 01 (CR01) is read,
CR01 performs the capture operation, but this capture value is not guaranteed. However, the interrupt
request flag (INTTM01) is set as a result of detection of the valid edge.
Figure 6-33: Data Hold Timing of Capture Register
Count pulse
N
N+1
N+2
M
M+1
M+2
TM0 count
Edge input
Interrupt request flag
Capture read signal
CR01 interrupt value
X
N+1
Capture
(5) Setting valid edge
Before setting the valid edge of the TI00 pin, stop the timer operation by resetting bits 2 and 3 (TMC02
and TMC03) of the 16-bit timer mode control register to 0, 0. Set the valid edge by using bits 4 and
5 (ES00 and ES01) of the prescaler mode register 0 (PRM0).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is output, do not set OSPT to 1. Do not output the one-shot pulse again
until INTTM00, which occurs on coincidence between TM0 and CR00, occurs.
(b) One-shot pulse output with external trigger
If the external trigger occurs while a one-shot pulse is output, it is ignored.
140
µPD1615, µPD16F15, µPD1616
7) Operation of OVF0 flag
The OVF0 flag is set to 1 in the following case:
Select mode in which 16-bit timer/counter is cleared and started on coincidence between TM0 and
CR00.
↓
Set CR00 to FFFFH
↓
When TM0 counts up from FFFFH to 0000H
Figure 6-34: Operation Timing of OVF0 Flag
Count pulse
CR00
FFFFH
TM0
FFFEH
FFFFH
0000H
0001H
OVF0
INTTM00
(8) Contending operations
(a) The contending operation between the read time of 16-bit capture/compare register (CR00/
CR01) and capture trigger input (CR00/CR01 used as capture register)
Capture/trigger input is prior to the other. The data read from CR00/CR01 is not defined.
(b) The coincidence timing of contending operation between the write period of 16-bit capture/
compare register (CR00/CR01) and 16-bit timer register (TM0) (CR00/CR01 used as a
compare register)
The coincidence discriminant is not performed normally. Do not write any data to CR00/CR01 near
the coincidence timing.
141
µPD1615, µPD16F15, µPD1616
[Memo]
142
µPD1615, µPD16F15, µPD1616
Chapter 7 8-Bit Timer/Event Counters 50 and 51
7.1 8-Bit Timer/Event Counters 50 and 51 Functions
The 8-bit timer event counters 50 and 51 (TM50, TM51) have the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
143
µPD1615, µPD16F15, µPD1616
(1) 8-bit interval timer
Interrupts are generated at the preset time intervals.
Table 7-1: 8-Bit Timer/Event Counter 50 Interval Times
Minimum Interval Width
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
Maximum Interval Width
29 x 1/fX (64 µs)
211 x 1/fX (256 µs)
213 x 1/fX (1 ms)
Resolution
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
25 x 1/fX (4 µs)
25 x 1/fX (4 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
219 x 1/fX (65 ms)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
Table 7-2: 8-Bit Timer/Event Counter 51 Interval Times
Minimum Interval Width
1/fX (125 ns)
Maximum Interval Width
28 x 1/fX (32 µs)
Resolution
1/fX (125 ns)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
212 x 1/fX (512 µs)
214 x 1/fX (2 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
218 x 1/fX (32 ms)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
Remarks: 1. fX: Main system clock oscillation frequency
2. Values in parentheses when operated at fX = 8.0 MHz.
144
µPD1615, µPD16F15, µPD1616
(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
Table 7-3: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges
Minimum Pulse Width
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
Maximum Pulse Width
29 x 1/fX (64 µs)
211 x 1/fX (256 µs)
213 x 1/fX (1 ms)
Resolution
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
25 x 1/fX (4 µs)
25 x 1/fX (4 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
219 x 1/fX (65 ms)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
Table 7-4: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges
Minimum Pulse Width
1/fX (125 ns)
Maximum Pulse Width
28 x 1/fX (32 µs)
Resolution
1/fX (125 ns)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
29 x 1/fX (512 µs)
211 x 1/fX (2 ms)
213 x 1/fX (4 ms)
215 x 1/fX (8 ms)
220 x 1/fX (32 ms)
21 x 1/fX (2 µs)
23 x 1/fX (8 µs)
25 x 1/fX (16 µs)
27 x 1/fX (32 µs)
212 x 1/fX (128 µs)
Remarks: 1. fX: Main system clock oscillation frequency
2. Values in parentheses when operated at fX = 8.0 MHz.
(4) PWM output
TM50 and TM51 can generate an 8-bit resolution PWM output.
145
µPD1615, µPD16F15, µPD1616
7.2 8-Bit Timer/Event Counters 50 and 51 Configurations
The 8-bit timer/event counters 50 and 51 consist of the following hardware.
Table 7-5: 8-Bit Timer/Event Counters 50 and 51 Configurations
Item
Timer register
Register
Configuration
8 bits x 2 (TM50, TM51)
Compare register 8 bits x 2 (CR50, CR51)
2 (TO50, TO51)
Timer output
Timer clock select register 50 and 51 (TCL50, TCL51)
8-bit timer mode control registers 5 and 6 (TMC50, TMC51)
Port mode registers 0 (PM0)
Control register
Figure 7-1: 8-Bit Timer/Event Counter 50 Block Diagram
Internal Bus
8-Bit Compare
Register (CR50)
fx/21
fx/23
fx/25
fx/27
fx/28
fx/211
Match
INTTM50
Note
Output
Control
8-Bit Timer
Register n (TM50)
OVF
TO50/P06/TI50
TI50/P06/TO50
Clear
Selector
6
4
2
TCL TCL TCL
502 501 500
TCE TMC LVS LVR TMC TOE
50
506
50
50 501
50
Timer Clock Select
Register 50
8-Bit Timer Mode
Control Register 50
Internal Bus
Note:
Refer to Figure 7-2 for details of configurations of 8-bit timer/event counters 50 and 51
output control circuits.
146
µPD1615, µPD16F15, µPD1616
Figure 7-2: 8-Bit Timer/Event Counter 51 Block Diagram
Internal Bus
8-Bit Compare
Register (CR51)
Match
fx
INTTM51
fx/24
fx/26
fx/27
fx/28
fx/210
Note
Output
Control
8-Bit Timer
Register n (TM51)
OVF
TO51/P07/TI51
TI51/P07/TO51
Clear
Selector
6
4
2
TCL TCL TCL
512 511 510
TMC TCE LVS LVR TMC TOE
51 516 51 51 511 51
Timer Clock Select
Register 51
8-Bit Timer Mode
Control Register 51
Internal Bus
Note:
Refer to Figure 7-3 for details of configurations of 8-bit timer/event counters 50 and 51
output control circuits.
147
µPD1615, µPD16F15, µPD1616
Figure 7-3: Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit
TMCn1
TMCn6
RESET
R
LVRn
LVSn
Q
TO50/P06/TI50,
TO51/P07/TI51
S
TMCn1
INV
PM06,
PM07
P06, P07
Output Latch
TMCn6
INTTMn
PWM Output Circuit
Timer Output F/F2
TCEn
INTTMn
OVFn
R
Level
F/F
Q
S
TOEn
Remarks: 1. The section in the line is an output control circuit.
2. n = 50, 51
(1) Compare register 50 and 51 (CR50, 51)
These 8-bit registers compare the value set to CR50 to 8-bit timer register 5 (TM50) count value, and
the value set to CR51 to the 8-bit timer register 51 (TM51) count value, and, if they match, generate
interrupts request (INTTM50 and INTTM51, respectively).
CR50 and CR51 are set with an 8-bit memory manipulation instruction. They cannot be set with a
16-bit memory manipulation instruction. The 00H to FFH values can be set.
RESET input sets CR50 and CR51 values to 00H.
Caution: To use PWM mode, set CRn value before setting TMCn (n = 50, 51) to PWM mode.
(2) 8-bit timer registers 50 and 51 (TM50, TM51)
These 8-bit registers count count pulses.
TM50 and TM51 are read with an 8-bit memory manipulation instruction.
RESET input sets TM50 and TM51 to 00H.
148
µPD1615, µPD16F15, µPD1616
7.3 8-Bit Timer/Event Counters 50 and 51 Control Registers
The following three types of registers are used to control the 8-bit timer/event counters 50 and 51.
• Timer clock select register 50 and 51 (TCL50, TCL51)
• 8-bit timer mode control registers 50 and 51 (TMC50, TMC51)
• Port mode register 0 (PM0)
(1) Timer clock select register 50 (TCL50)
This register sets count clocks of 8-bit timer register 50.
TCL50 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL50 to 00H.
Figure 7-4: Timer Clock Select Register 50 Format
Address
FF71H
After Reset
00H
R/W
R/W
Symbol
TCL50
7
0
6
0
5
0
4
0
3
0
2
1
0
TCL501TCL500
TCL502
8-bit Timer Register 50 Count Clock Selection
TCL502 TCL501TCL500
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI50 falling edge Note
TI50 rising edge Note
fX
/21 (4.0 MHz)
f
X
X
X
X
X
/23 (1.0 MHz)
/25 (250 kHz)
/27 (62.5 kHz)
/28 (31.25 kHz)
/211 (3.9 kHz)
f
f
f
f
Other than above
Setting prohibited
Note:
When clock is input from the external, timer output (PWM output) cannot be used.
Caution: When rewriting TCL50 to other data, stop the timer operation beforehand.
Remarks: 1. fX: Main system clock oscillation frequency
2. TI50: 8-bit timer register 50 input pin
3. Values in parentheses apply to operation with fX = 8.0 MHz
149
µPD1615, µPD16F15, µPD1616
(2) Timer clock select register 51 (TCL51)
This register sets count clocks of 8-bit timer register 51.
TCL51 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL51 to 00H.
Figure 7-5: Timer Clock Select Register 51 Format
Address
FF75H
After Reset
00H
R/W
R/W
Symbol
TCL51
7
0
6
0
5
0
4
0
3
0
2
1
0
TCL511TCL510
TCL512
8-bit Timer Register 51 Count Clock Selection
TCL512 TCL511TCL510
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI51 falling edge Note
TI51 rising edge Note
f
f
f
f
f
f
X
X
X
X
X
X
(8.0 MHz)
/24 (500 kHz)
/26 (125 kHz)
/27 (62.5 kHz)
/28 (31.25 kHz)
/210 (7.8 kHz)
Other than above
Setting prohibited
Note:
When clock is input from the external, timer output (PWM output) cannot be used.
Caution: When rewriting TCL51 to other data, stop the timer operation beforehand.
Remarks: 1. fX: Main system clock oscillation frequency
2. TI51: 8-bit timer register 51 input pin
3. Values in parentheses apply to operation with fX = 8.0 MHz
150
µPD1615, µPD16F15, µPD1616
(3) 8-bit timer mode control register 50 (TMC50)
This register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer
register 50 and controls operation of 8-bit timer/event counter 50 output control circuit.
It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion
enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/
disabling.
TMC50 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC50 to 04H.
Figure 7-6: 8-Bit Timer Output Control Register 50 Format
Address
FF70H
After Reset
04H
R/W
R/W
Symbol <7>
6
5
0
4
0
<3> <2>
1
<0>
TCE50 TMC506
LVS50 LVR50 TMC501TOE50
TMC50
TOE50 8-Bit Timer/Event Counter 50 Output Control
0
1
Output disabled (Port mode)
Output enabled
In PWM Mode
In Other Mode
TMC501
Active level selection Timer output F/F1 control
0
1
Active high
Active low
Inversion operation disabled
Inversion operation enabled
8-Bit Timer/Event Counter 50 Timer
Output F/F1 Status Setting
LVR50
LVS50
0
0
1
1
0
1
0
1
No change
Timer output F/F1 reset (0)
Timer output F/F1 set (1)
Setting prohibited
TMC506 8-Bit Timer/Event Counter 50 Operating Mode Selection
0
1
Clear & start mode on match of TM50 and CR50
PWM mode (free-running)
TCE50 8-Bit Timer Register 50 Operation Control
0
1
Operation Stop (TM50 clear to 0)
Operation Enable
Cautions: 1. Timer operation must be stopped before setting TMC50.
2. If LVS50 and LVR50 are read after data are set, they will be 0.
3. Be sure to set bit 4 and bit 5 to 0.
Note:
If TM50 is used as clock generation for SIO30, no clock will be supplied to SIO30
unless TOE50 is set to 1. In this case a square wave signal is output from the TO50
pin.
151
µPD1615, µPD16F15, µPD1616
(4) 8-bit timer mode control register 51 (TMC51)
This register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer
register 51 and controls operation of 8-bit timer/event counter 51 output control circuit.
It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion
enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 51 timer output enabling/
disabling.
TMC51 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC51 to 04H.
Figure 7-7: 8-Bit Timer Output Control Register 51 Format
Address
FF74H
After Reset
04H
R/W
R/W
Symbol <7>
6
5
0
4
0
<3> <2>
1
<0>
TCE51 TMC516
LVS51 LVR6 TMC511TOE51
TMC51
TOE51 8-Bit Timer/Event Counter 51 Output Control
0
6
Output disabled (Port mode)
Output enabled
In PWM Mode
In Other Mode
TMC511
Active level selection Timer output F/F1 control
0
1
Active high
Active low
Inversion operation disabled
Inversion operation enabled
8-Bit Timer/Event Counter 51 Timer
Output F/F1 Status Setting
LVS51 LVR51
0
0
1
1
0
1
0
1
No change
Timer output F/F1 reset (0)
Timer output F/F1 set (1)
Setting prohibited
TMC516 8-Bit Timer/Event Counter 51 Operating Mode Selection
0
1
Clear & start mode on match of TM51 and CR51
PWM mode (free-running)
TCE51 8-Bit Timer Register 51 Operation Control
0
1
Operation Stop (TM51 clear to 0)
Operation Enable
Cautions 1. Timer operation must be stopped before setting TMC51.
2. If LVS51 and LVR51 are read after data are set, they will be 0.
3. Be sure to set bit 4 and bit 5 to 0.
152
µPD1615, µPD16F15, µPD1616
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P06/TI50/TO50 and P07/TI51/TO51 pins for timer output, set PM06, PM07 and output
latches of P06 and P07 to 0.
PM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0 to FFH.
Figure 7-8: Port Mode Register 0 Format
After
Reset
7
6
5
1
4
1
3
1
2
1
0
Address
FF20H
R/W
R/W
Symbol
PM0
PM07 PM06
PM02 PM01 PM00
FFH
PM0n P0n Pin Input/Output Mode Selection (n=0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
153
µPD1615, µPD16F15, µPD1616
7.4 8-Bit Timer/Event Counters 50 and 51 Operations
7.4.1 Interval timer operations
Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 7-9 allows
operation as an interval timer. Interrupts are generated repeatedly using the count value preset in 8-
bit compare registers (CR50 and CR51) as the interval.
When the count value of the 8-bit timer register 50 or 51 (TM50, TM51) matches the value set to
CR50 or CR51, counting continues with the TM50 or TM51 value cleared to 0 and the interrupt request
signal (INTTM50, INTTM51) is generated.
Count clock of the 8-bit timer register 50 (TM50) can be selected with the timer clock select register
50 (TCL50) and count clock of the 8 bit timer register 51 (TM51) can be selected with the timer clock
select register 51 (TCL51).
Figure 7-9: 8-Bit Timer Mode Control Register Settings for Interval Timer Operation
TCEn TMCn6
LVSn LVRn TMCn1 TOEn
0/1 0/1 0/1 0/1
1
0
0
0
TMCn
Clear and start on match of TMn and CRn
TMn operation enable
Remarks: 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval
timer. See 9.3 (3), (4) for details.
2. n = 50, 51
Figure 7-10: Interval Timer Operation Timings (1/3)
(a) When N = 00H to FFH
t
Count Clock
TMn Count Value
00
01
N
00
01
N
00
Clear
01
N
N
Clear
N
N
N
CRn
TCEn
Count Start
INTTMn
Interrupt Acknowledge
Interval Time
Interrupt Acknowledge
Interval Time
TOn
Interval Time
Remarks: 1. Interval time = (N + 1) x t: N = 00H to FFH
2. n = 50, 51
3. Signal output at TO50, when defined as square wave output.
154
µPD1615, µPD16F15, µPD1616
Figure 7-10: Interval Timer Operation Timings (2/3)
(b) When CRn = 00H
t
Count clock
TMn 00H
00H 00H
00H 00H
CRn
TCEn
INTTMn
TIOn
Interval time
(c) When CRn = FFH
t
Count clock
TMn
01
FE
FF
FF
00
FE
FF
FF
00
CRn
FF
TCEn
INTTMn
Interrupt received
Interrupt
received
TIOn
Interval time
Remark:
n = 50, 51
155
µPD1615, µPD16F15, µPD1616
Figure 7-10: Interval Timer Operation Timings (3/3)
(d) Operated by CR5n transition (M < N)
Count clock
TMn
N
00H
M
N
FFH 00H
M
M
00H
CRn
N
TCEn
INTTMn
TIOn
CRn transition
TMn overflows since M < N
(e) Operated by CR5n transition (M > N)
Count clock
TMn
NÐ1
N
N
00H 01H
N
MÐ1
M
00H 01H
CRn
M
TCEn
INTTMn
TIOn
CRn transition
Remark:
n = 50, 51
156
µPD1615, µPD16F15, µPD1616
Table 7-6: 8-Bit Timer/Event Counters 50 Interval Times
TCLn2 TCLn1 TCLn0
Minimum Interval Time
Tin input cycle
Maximum Interval Time
28 x Tin input cycle
28 x Tin input cycle
29 x 1/fX (64 µs)
211 x 1/fX (256 µs)
213 x 1/fX (1 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
219 x 1/fX (65 ms)
Resolution
Tin input edge input cycle
Tin input edge input cycle
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
25 x 1/fX (4 µs)
27 x 1/fX (16 µs)
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
Tin input cycle
1
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
25 x 1/fX (4 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
1
0
0
1
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
1
Other than above
Setting prohibited
Table 7-7: 8-Bit Timer/Event Counters 51 Interval Times
TCLn2 TCLn1 TCLn0
Minimum Interval Time
Tin input cycle
Tin input cycle
1/fX (125 ns)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
Maximum Interval Time
28 x Tin input cycle
28 x Tin input cycle
28 x 1/fX (32 µs)
212 x 1/fX (512 µs)
214 x 1/fX (2 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
218x 1/fX (32 ms)
Resolution
Tin input edge input cycle
Tin input edge input cycle
1/fX (125 ns)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
Other than above
Setting prohibited
Remarks: 1. fX: Main system clock oscillation frequency
2. Values in parentheses apply to operation with fX = 8.0 MHz.
3. n = 50, 51
157
µPD1615, µPD16F15, µPD1616
7.4.2 External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI50/P06/
TO50 and TI51/P07/TO51 pins with 8-bit timer registers 50 and 51 (TM50 and TM51).
TM50 and TM51 are incremented each time the valid edge specified with timer clock select registers
50 and 51 (TCL50 and TCL51) is input. Either rising or falling edge can be selected.
When the TM50 and TM51 counted values match the values of 8-bit compare registers (CR50 and
CR51), TM50 and TM51 are cleared to 0 and the interrupt request signals (INTTM50 and INTTM51) are
generated.
Figure 7-11: 8-Bit Timer Mode Control Register Setting for External Event Counter Operation
TCEn TMCn6
LVSn LVRn TMCn1 TOEn
1
0
0
0
x
x
x
0
TMCn
TOn output disable
Clear & start mode on match of TMn and CRn
TMn operation enable
Remarks: 1. n = 50, 51
2. x: don’t care
Figure 7-12: External Event Counter Operation Timings (with Rising Edge Specified)
Count Clock
TMn Count Value
CRn
00
01
02
13
04
05
N
N-1
N
00
01
02
03
TCEn
INTTMn
Remarks: 1. N = 00H to FFH
2. n = 50, 51
158
µPD1615, µPD16F15, µPD1616
7.4.3 Square-wave output
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare
registers (CR50 and CR51).
The TO50/P06/TI50 or TO51/P07/TI51 pin output status is reversed at intervals of the count value
preset to CR50 or CR51 by setting bit 1 (TMC501) and bit 0 (TOE50) of the 8-bit timer output control
register 5 (TMC50), or bit 1 (TMC511) and bit 0 (TOE51) of the 8-bit timer mode control register 6
(TMC51) to 1.
This enables a square wave of any selected frequency to be output.
Figure 7-13: 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation
TCEn TMCn6
LVSn LVRn TMCn1 TOEn
0/1 0/1
1
0
0
0
1
1
TMCn
TOn output enable
Inversion of output on match of TMn and CRn
Specifies TO1 output F/F1 initial value
Clear and start mode on match of TMn and CRn
TMn operation enable
Caution: When TI50/P06/TO50 or TI51/P07/TO51 pin is used as the timer output, set port
mode register (PM00 or PM07) and output latch to 0.
Remark:
n = 50, 51
Figure 7-14: Square-wave Output Operation Timing
Count clock
01H
00H
TMn count value
00H 01H
Count start
N
N-1
02H
N-1
00H
02H
N
N
CRn
T0nNote
Note:
TOn output initial value can be set by bits 2 and 3 (LVRn, LVSn) of the 8-bit timer mode control
register TCMn.
Remark:
n = 50, 51
159
µPD1615, µPD16F15, µPD1616
Table 7-8: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges
Minimum Pulse Time
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
Maximum Pulse Time
29 x 1/fX (64 µs)
211 x 1/fX (256 µs)
213 x 1/fX (1 ms)
Resolution
21 x 1/fX (250 ns)
23 x 1/fX (1 µs)
25 x 1/fX (4 µs)
25 x 1/fX (4 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
219 x 1/fX (65 ms)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
211 x 1/fX (256 µs)
Table 7-9: 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges
Minimum Pulse Time
1/fX (125 ns)
Maximum Pulse Time
28 x 1/fX (32 µs)
Resolution
1/fX (125 ns)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
212 x 1/fX (512 µs)
214 x 1/fX (2 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8 ms)
218 x 1/fX (32 ms)
24 x 1/fX (2 µs)
26 x 1/fX (8 µs)
27 x 1/fX (16 µs)
28 x 1/fX (32 µs)
210 x 1/fX (128 µs)
Remarks: 1. f: Main system clock oscillation frequency
2. Values in parentheses when operated at fX = 8.0 MHz.
3. n = 50, 51
160
µPD1615, µPD16F15, µPD1616
7.4.4 PWM output operations
Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 7-15 allows
operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare
registers (CR50 and CR51) output from the TO50/P06/TI50 or TO51/P07/TI51 pin.
Select the active level of PWM pulse with bit 1 of the 8-bit timer mode control register 50 (TMC50)
or bit 1 of the 8-bit timer mode control register 51 (TMC51).
This PWM pulse has an 8-bit resolution. The pulse can be converted into an analog voltage by
integrating it with an external low-pass filter (LPF). Count clock of the 8-bit timer register 50 (TM50)
can be selected with the timer clock select register 50 (TCL50) and count clock of the 8-bit timer register
51 (TM51) can be selected with the timer clock select register 51 (TCL51).
PWM output enable/disable can be selected with bit 0 (TOE50) of TMC50 or bit 0 (TOE51) of TMC51.
Figure 7-15: 8-Bit Timer Control Register Settings for PWM Output Operation
TCEn TMCn6
LVSn LVRn TMCn1 TOEn
0/1
1
1
0
0
x
x
1
TMCn
TOn output enable
Sets active level
PWM mode
TMn operation enable
Remarks: 1. n = 50, 51
2. x: don’t care
161
µPD1615, µPD16F15, µPD1616
Figure 7-16: PWM Output Operation Timing (Active high setting)
CRn Changing
(M N)
Count Clock
00
01
02
FF
00
01
02
N
N+1
N+2 N+3 00
TMn Count Value
CRn
M
N
N
TCEn
INTTMn
OVFn
TOn
Inactive Level
Inactive Level
Active Level
Inactive Level
Remark:
n = 50, 51
Figure 7-17: PWM Output Operation Timings (CRn0 = 00H, active high setting)
CRn Changing
(M 00)
Count Clock
00
01
02
FF
00
01
02
FF
00
01
02
00
TMn Count Value
CRn
M
00
00
TCEn
INTTMn
OVFn
TOn
Inactive Level
Inactive Level
Remark:
n = 50, 51
162
µPD1615, µPD16F15, µPD1616
Figure 7-18: PWM Output Operation Timings (CRn = FFH, active high setting)
Count Clock
00
01
02
FF
00
01
02
FF
00
01
02
00
TMn Count Value
CRn
FF
FF
FF
TCEn
INTTMn
OVFn
TOn
Inactive Level
Inactive Level
Active Level
Inactive Level
Active Level
Remark:
n = 50, 51
Figure 7-19: PWM Output Operation Timings (CRn changing, active high setting)
CRn Changing
(N M)
Count
Clock
TMn
Count
Value
FF
00
01
02
N
N+1 N+2
N
FF
00
01
02
M
M+3 00
M+1 M+2
M
CRn0
N
M
TCEn
INTTMn
OVFn
TOn
Active Level
Inactive Level
Active Level
Inactive Level
Remark:
n = 50, 51
Caution: If CRn is changed during TMn operation, the value changed is not reflected until TMn
overflows.
163
µPD1615, µPD16F15, µPD1616
7.5 Cautions on 8-Bit Timer/Event Counters 50 and 51
(1) Timer start errors
An error with a maximum of one clock might occur concerning the time required for a match signal
to be generated after the timer starts. This is because 8-bit timer registers 50 and 51 are started
asynchronously with the count pulse.
Figure 7-20: 8-bit Timer Registers 50 and 51 Start Timings
Count Pulse
TMn Count Value
00H
01H
02H
03H
04H
Timer Start
Remark:
n = 50, 51
(2) Compare registers 50 and 51 sets
The 8-bit compare registers (CR50 and CR51) can be set to 00H.
Thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be
carried out.
Figure 7-21: External Event Counter Operation Timings
TIn Input
CRn
TMn Count Value
TOn
00H
00H
00H
00H
00H
Interrupt Request Flag
Remark:
n = 50, 51
164
µPD1615, µPD16F15, µPD1616
(3) Operation after compare register change during timer count operation
If the values after the 8-bit compare registers (CR50 and CR51) are changed are smaller than those
of 8-bit timer registers (TM50 and TM51), TM50 and TM51 continue counting, overflow and then restarts
counting from 0. Thus, if the value (M) after CR50 and CR51 change is smaller than that (N) before
change it is necessary to restart the timer after changing CR50 and CR51.
Figure 7-22: Timings after Compare Register Change during Timer Count Operation
Count Pulse
CRn
N
M
TMn Count Value
X-1
X
FFH
00H
01H
02H
Remark:
n = 50, 51
165
µPD1615, µPD16F15, µPD1616
[Memo]
166
µPD1615, µPD16F15, µPD1616
Chapter 8 Watch Timer
8.1 Watch Timer Functions
The watch timer has the following functions:
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
The figure 8-1 shows Watch Timer Block Diagram.
Figure 8-1: Block Diagram of Watch Timer
Clear
f
/27
X
5-bit counter
INTWT
INTWTI
9-bit prescaler
f
W
f
W
f
W
f
W
f
W
f
W
f
W
29
Clear
24 25 26 27 28
f
XT
WTM7 WTM6 WTM5 WTM4 WTM3
0
WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
167
µPD1615, µPD16F15, µPD1616
(1) Watch timer
When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated
at 0.5 second intervals.
(2) Interval timer
Interrupt requests (INTWTI) are generated at the preset time interval.
Table 8-1: Interval Time Selection
Interval
Time
When operated at
fx=8.00 MHz
When operated at
fxT=32.768 KHz
24/fw
256 µs
488 µs
25/fw
26/fw
27/fw
28/fw
29/fw
512 µs
1 ms
977 µs
1,95 ms
3,91 ms
7,81 ms
15,6 ms
2 ms
4 ms
8,19 ms
Remark:
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
8.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 8-2: Watch Timer Configuration
Item
Configuration
Counter
5 bits x 1
9 bits x 1
Prescaler
Control register
Watch timer mode control register (WTM)
168
µPD1615, µPD16F15, µPD1616
8.3 Watch Timer Mode Register (WTM)
This register sets the watch timer count clock, the watch timer operating mode, and prescaler interval
time and enables/disables prescaler and 5-bit counter operations. WTM is set with a 1-bit or 8-bit
memory manipulation instruction.
RESET input sets WTM to 00H.
Figure 8-2: Watch Timer Mode Control Register (WTM) Format
Symbol
WTM
7
6
5
4
3
2
0
1
0
Address AfterReset R/W
WTM7
WTM6
WTM5
WTM4
WTM3
WTM1
WTM0
FF41H
00H
R/W
WTM7
Watch Timer Count Clock Selection
0
1
Input clock set to fX/27
Input clock set to fXT
WTM6
WTM5
WTM4
Prescaler Interval Time Selection
fX = 8.00 MHz Operation
24/fw (256 µs)
25/fw (512 µs)
26/fw (1 ms)
27/fw (2 ms)
28/fw (4 ms)
fXT = 32.768 kHz Operation
24/fw (488 µs)
25/fw (977 µs)
26/fw (1.95 ms)
27/fw (3.91 ms)
28/fw (7.81 ms)
29/fw (15.6 ms)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
29/fw (8.19 ms)
Other than above
Setting prohibited
WTM3
Watch Operating Mode Selections
0
1
Normal operating mode (interrupt generation at 214/fw)
Fast feed operating mode (interrupt generation at 25/fw)
WTM1
5-Bit Counter Operation Control
0
1
Clear after operation stop
Operation enable
WTM0
Prescaler Operation Control
0
1
Clear after operation stop
Operation enable
Caution: When the watch timer is used, the prescaler should not be cleared frequently. When
rewriting WTM4 to WTM6 to other data, stop the timer operation beforehand.
7
Remarks: 1. fw: Watch timer clock frequency (fx/2 or fxt)
2. fx: Main system clock oscillation frequency
3. fxt: Subsystem clock oscillation frequency
169
µPD1615, µPD16F15, µPD1616
8.4 Watch Timer Operations
8.4.1 Watch timer operation
When the 32.768-kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second
interval.
The watch timer is generated interrupt request at the constant time interval.
When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register is set to 1, the 5-bit
counter is cleared and the count operation stops.
For simultaneous operation of the interval timer, zero-second start can be achieved by setting WTM1
to 0.
8.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt request repeatedly at an interval
of the preset count value.
The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control
register (WTM).
Table 8-3: Interval Timer Operation
Interval
Time
fx=8.00 MHz
Operation
fxT=32.768 MHz
Operation
WTM6 WTM5 WTM4
24 x 1/fw
24 x 1/fw
24 x 1/fw
24 x 1/fw
24 x 1/fw
24 x 1/fw
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
256 µs
488 µs
512 µs
1 ms
977 µs
1.95 ms
3.91 ms
7.81 ms
15.6 ms
2 ms
4 ms
8.19 ms
Other than above
Setting prohibited
Remark:
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
170
µPD1615, µPD16F15, µPD1616
Figure 8-3: Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H
Overflow
Overflow
Start
Count clock fw
Watch timer
interrupt INTWT
Interrupt time of watch timer (0.5s) Interrupt time of watch timer (0.5s)
Interval timer
interrupt INTWTI
Interval timer
(T)
T
Remark:
fW: Watch timer clock frequency
171
µPD1615, µPD16F15, µPD1616
[Memo]
172
µPD1615, µPD16F15, µPD1616
Chapter 9 Watchdog Timer
9.1 Watchdog Timer Functions
The watchdog timer has the following functions:
• Watchdog timer
• Interval timer
Caution: Select the watchdog timer mode or the interval timer mode with the watchdog timer
mode register (WDTM).
(1) Watchdog timer mode
An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-
maskable interrupt request or RESET can be generated.
Table 9-1: Watchdog Timer Inadvertent Program Overrun Detection Times
Runaway Detection Time
212 x 1/fX
213 x 1/fX
214 x 1/fX
215 x 1/fX
216 x 1/fX
217 x 1/fX
218 x 1/fX
220 x 1/fX
212 x 1/fX (512 µs)
213 x 1/fX (1 ms)
214 x 1/fX (2 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8.19 ms)
217 x 1/fX (16.38 ms)
218 x 1/fX (32.76 ms)
220 x 1/fX (131 ms)
Remark:
Figures in parentheses apply to operation with fX = 8.0 MHz.
(2) Interval timer mode
Interrupts are generated at the preset time intervals.
Table 9-2: Interval Times
Interval Time
212 x 1/fX (512 µs)
212 x 1/fX
213 x 1/fX
214 x 1/fX
215 x 1/fX
216 x 1/fX
217 x 1/fX
218 x 1/fX
220 x 1/fX
213 x 1/fX (1 ms)
214 x 1/fX (2 ms)
215 x 1/fX (4 ms)
216 x 1/fX (8.19 ms)
217 x 1/fX (16.38 ms)
218 x 1/fX (32.76 ms)
220 x 1/fX (131 ms)
Remark:
Figures in parentheses apply to operation with fX = 8.0 MHz.
173
µPD1615, µPD16F15, µPD1616
9.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware.
Table 9-3: Watchdog Timer Configuration
Item
Configuration
Timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
Control register
Figure 9-1: Watchdog Timer Block Diagram
Internal Bus
fX /212
Prescaler
TMMK
fX
28
RUN
fX
fX
fX
fX
fX
fX
INTWDT
21
22
23
24
25
26
Maskable Interrupt
Request
TMIF
Control
Circuit
8-Bit
Counter
RESET
INTWDT
Non-Maskable
Interrupt Request
3
WDCS2 WDCS1
WDTM4 WDTM3
WDCS0
Watchdog Timer Clock
Selection Register
Watchdog Timer
Mode Register
Internal Bus
174
µPD1615, µPD16F15, µPD1616
9.3 Watchdog Timer Control Registers
The following two types of registers are used to control the watchdog timer.
• Watchdog timer clock select register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock select register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-2: Watchdog Timer Clock Select Register Format
Symbol
WDCS
7
0
6
0
5
0
4
0
3
0
2
1
0
Address AfterReset R/W
FF42H 00H R/W
WDCS2 WDCS1 WDCS0
WDCS2 WDCS1 WDCS0
Overflow time of watchdog 1 interval timer
fX/212 (512 µs)
fX/213 (1 ms)
fX/214 (2 ms)
fX/215 (4 ms)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/216 (8.19 ms)
fX/217 (16.38 ms)
fX/218 (32.76 ms)
fX/220 (131 ms)
Caution: When rewriting WDCS to other data, stop the timer operation beforehand.
Remarks: 1. fx: Main system clock oscillation frequency
2. Figures in parentheses apply to operation with fX = 8.0 MHz.
175
µPD1615, µPD16F15, µPD1616
(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 9-3: Watchdog Timer Mode Register Format
Symbol
WDTM
7
6
0
5
0
4
3
2
0
1
0
0
0
Address AfterReset R/W
FFF9H 00H R/W
RUN
WDTM4 WDTM3
WDTM4 WDTM3 Watchdog Timer Operation Mode Selection Note 1
Interval timer mode
0
1
1
X
0
1
(Maskable interrupt occurs upon generation of
an overflow)
Watchdog timer mode 1
(Non-maskable interrupt occurs upon
generation of an overflow)
Watchdog timer mode 2
(Reset operation is activated upon generation
of an overflow)
RUN
Watchdog Timer Operation Mode Selection Note 2
0
1
Count stop
Counter is cleared and counting starts
Notes:
1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
2. Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
Caution: When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time
is up to 0.5 % shorter than the time set by watchdog timer clock select register.
Remark:
x = don't care.
176
µPD1615, µPD16F15, µPD1616
9.4 Watchdog Timer Operations
9.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer
is operated to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected
with bits 0 to 2 (WDCS0 to WDCS2) of the timer clock select register (WDCS).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set
RUN to 1 within the set overrun detection time interval. The watchdog timer can be cleared and counting
is started by setting RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time
is past, system reset or a non-maskable interrupt request is generated according to the WDTM bit 3
(WDTM3) value.
The watchdog timer can be cleared when RUN is set to 1.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set
RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual overrun detection time may be shorter than the set time by a maximum
of 0.5 %.
2. When the subsystem clock is selected for CPU clock, watchdog timer count
operation is stopped.
Table 9-4: Watchdog Timer Overrun Detection Time
WDCS2 WDCS1 WDCS0
Runaway Detection Time
fX/212 (512 µs)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/213 (1 ms)
fX/214 (2 ms)
fX/215 (4 ms)
fX/216 (8.19 ms)
fX/217 (16.38 ms)
fX/218 (32.76 ms)
fX/220 (131 ms)
Remarks: 1. fx: Main system clock oscillation frequency
2. Figures in parentheses apply to operation with fX = 8.0 MHz.
177
µPD1615, µPD16F15, µPD1616
9.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval
of the preset count value when bit 3 (WDTM3) of the watchdog timer mode register (WDTM) is set to
0, respectively.
When the watchdog timer operates as interval timer, the interrupt mask flag (TMMK4) and priority
specify flag (TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated.
Among maskable interrupts, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit
7 (RUN) of WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP
instruction.
Cautions: 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected),
the interval timer mode is not set unless RESET input is applied.
2. The interval time just after setting with WDTM may be shorter than the set time
by a maximum of 0.5 %.
3. When the subsystem clock is selected for CPU clock, watchdog timer count
operation is stopped.
Table 9-5: Interval Timer Interval Time
WDCS2 WDCS1 WDCS0
Interval Time
fX/212 (512 µs)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/213 (1 ms)
fX/214 (2 ms)
fX/215 (4 ms)
fX/216 (8.19 ms)
fX/217 (16.38 ms)
fX/218 (32.76 ms)
fX/220 (131 ms)
Remarks: 1. fx: Main system clock oscillation frequency
2. Figures in parentheses apply to operation with fX = 8.0 MHz.
178
µPD1615, µPD16F15, µPD1616
[Memo]
179
µPD1615, µPD16F15, µPD1616
Chapter 10 Clock Output Control Circuit
10.1 Clock Output Control Circuit Functions
The clock output control circuit is intended for carrier output during remote controlled transmission
and clock output for supply to peripheral LSI. Clocks selected with the clock output selection register
(CKS) are output from the PCL/P120/S7 pin.
Follow the procedure below to output clock pulses.
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (CCS0
to CCS2) of CKS.
(2) Set the P120 output latch to 0.
(3) Set bit 0 (PM120) of port mode register 120 to 0 (set to output mode).
(4) Set bit 4 (CLOE) of clock output selection register to 1.
Caution: Clock output cannot be used when setting the output latch to 1.
Remark:
When clock output enable/disable is switched, the clock output control circuit does not
output pulses with small widths (See the portions marked with * in Figure 12-1).
Figure 10-1: Remote Controlled Output Application Example
CLOE
*
*
PCL/P120/S7 Pin Output
180
µPD1615, µPD16F15, µPD1616
10.2 Clock Output Control Circuit Configuration
The clock output control circuit consists of the following hardware.
Table 10-1: Clock Output Control Circuit Configuration
Item
Configuration
Clock output selection register (CKS)
Port mode register 3 (PM3)
Control register
Figure 10-2: Clock Output Control Circuit Block Diagram
f
X
f
X
/2
/22
/23
/24
/25
/26
/27
f
f
f
f
f
f
X
X
X
X
X
X
f
Synchronizing
Circuit
PCL/P120/S7
X
T
4
P120
Output Latch
CLOE CCS2 CCS1 CCS0
PM120
Port Mode Register 12
Clock Output Selection Register
Internal Bus
181
µPD1615, µPD16F15, µPD1616
10.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function.
• Clock output selection register (CKS)
• Port mode register 12 (PM12)
(1) Clock Output Selection Register (CKS)
This register sets PCL output clock.
CKS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CKS to 00H.
Caution:
When enabling PCL output, set CCS50 to CCS52, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
Figure 10-3: Clock Output Selection Register Format
Symbol
CKS
6
0
5
0
4
3
2
1
0
Address AfterReset R/W
FF40H 00H R/W
0
CLOE
CCS3
CCS2
CCS1
CCS0
CCS3
CCS2
CCS1
CCS0
PCL Output Clock Selection
fX (8 MHz)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fX/21 (4 MHz)
fX/22 (2 MHz)
fX/23 (1 MHz)
fX/24 (500 kHz)
fX/25 (250 kHz)
fX/26 (125 kHz)
fX/27 (62.5 kHz)
fXT (32.7 kHz)
Other than above
Setting prohibited
CLOE
PCL Output Control
0
1
Output disable
Output enable
Remarks: 1. fx: Main system clock oscillation frequency
2. fxT: subsystem clock oscillation frequency.
3. Figures in parentheses apply to operation with fX = 8.0 MHz and fxT = 32.718 kHz.
182
µPD1615, µPD16F15, µPD1616
(2) Port Mode Register 12 (PM12)
This register sets port 12 input/output in 1-bit units.
When using the P120/PCL/S7 pin for clock output function, set PM120 and output latch of P120
to 0. PM12 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM12 to FFH.
Figure 10-4: Port Mode Register 12 Format
Symbol
PM12
7
6
5
4
3
2
1
0
Address AfterReset R/W
FF2CH FFH R/W
PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PM12n P12n pin input/output mode selection (n = 0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
(3) Port Function Register 12 (PF12)
This register sets the port function of port 12 in 1-bit units.
When using the PCL output, the register PF12 has to be set to port function.
PF12 is with an 1-bit or an 8-bit memory manipulation instruction.
RESET input sets PM12 to 00H.
Figure 10-5: Port Function Register 12 (PF12) Format
Symbol
PF12
7
6
5
4
3
2
1
0
Address AfterReset R/W
FF5CH 00H R/W
PF127
PF126
PF125
PF124
PF123
PF122
PF121
PF120
PF12n
P12n port function selection (n = 0 to 7)
0
1
Port mode
LCD mode
Note:
For the µPD1616 set always 00H to PF12.
183
µPD1615, µPD16F15, µPD1616
[Memo]
184
µPD1615, µPD16F15, µPD1616
Chapter 11 A/D Converter
11.1 A/D Converter Functions
The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It
can control up to 4 analog input channels (ANI0 to ANI3).
This A/D converter has the following functions:
(1) A/D conversion with 8-bit resolution
One channel of analog input is selected from ANI0 to ANI3, and A/D conversion is repeatedly
executed with a resolution of 8 bits. Each time the conversion has been completed, an interrupt
request (INTAD) is generated.
(2) Power-fail detection function
This function is to detect for example a voltage drop in the battery of an automobile. The result
of A/D conversion (value of the ADCR1 register) and the value of PFT register (PFT: power-fail
compare threshold value register) are compared. If the condition for comparison is satisfied, the
INTAD is generated.
Figure 11-1: A/D Converter Block Diagram
Sample & hold circuit
AVDD
/AVREF
Voltage comparator
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
Successive
approximation
register (SAR)
AVss
Control
circuit
INTAD
3
A/D conversion result
register (ADCR1)
ADS10
ADS12 ADS11
ADCS1 FR12 FR11 FR10
A/D converter mode register
Analog input channel
specification register
Internal bus
185
µPD1615, µPD16F15, µPD1616
Figure 11-2: Power-Fail Detection Function Block Diagram
PFCM
PFEN
ANI0/P10
INTAD
ANI1/P11
A/D converter
Comparator
ANI2/P12
ANI3/P13
Power-fail compare
threshold value
register (PFT)
PFEN
PFCM
Power-fail compare
mode register (PFM)
Internal bus
11.2 A/D Converter Configuration
A/D converter consists of the following hardware.
Table 11-1: A/D Converter Configuration
Item
Configuration
Analog input
Register
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register (ADCR1)
A/D converter mode register (ADM1)
Analog input channel specification register (ADS1)
Power-fail compare mode register (PFM)
Power-fail compare threshold value register (PFT)
Control register
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value
applied from the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is set (end of A/D conversion), the SAR contents are
transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR1)
This register holds the A/D conversion result. Each time when the A/D conversion ends, the
conversion result is loaded from the successive approximation register.
ADCR1 is read with an 8-bit memory manipulation instruction.
RESET input clears ADCR1 to 00H.
Caution: If a write operation is executed to the A/D converter mode register (ADM1) and the
analog input channel specification register (ADS1) the contents of ADCR1 are
undefined. Read the conversion result before a write operation is executed to ADM1
and ADS1. If a timing other than the above is used, the correct conversion result may
not be read.
186
µPD1615, µPD16F15, µPD1616
(3) Sample & hold circuit
The sample & hold circuit samples each analog input sequentially applied from the input circuit, and
sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during
A/D conversion.
(4) Voltagecomparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is in AVDD to AVSS, and generates a voltage to be compared to the analog
input.
(6) ANI0 to ANI3 pins
These are four analog input pins to input analog signals to the A/D converter. ANI0 to ANI3 are
alternate-function pins that can also be used for digital input.
Caution: Use ANI0 to ANI3 input voltages within the specification range. If a voltage higher
than AVDD or lower than AVSS is applied (even if within the absolute maximum rating
range), the conversion value of that channel will be undefined and the conversion
values of other channels may also be affected.
(7) AVDD/AVREF pin
This pin inputs the A/D converter reference voltage and is used as the AD-converter power supply
pin. The supply power has to be connected when the A/D converter is used.
It converts signals input to ANI0 to ANI3 into digital signals according to the voltage applied
between AVDD/AVREF and AVSS.
(8) AVSS pin
This is the GND potential pin of the A/D converter. Always keep it at the same potential as the
VSS pin even when not using the A/D converter.
187
µPD1615, µPD16F15, µPD1616
11.3 A/D Converter Control Registers
The following 4 types of registers are used to control A/D converter.
• A/D converter mode register (ADM1)
• Analog input channel specification register (ADS1)
• Power-fail compare mode register (PFM)
• Power-fail compare threshold value register (PFT)
(1) A/D converter mode register (ADM1)
This register sets the conversion time for analog input to be A/D converted, conversion start/stop
and external trigger. ADM1 is set with an 8-bit memory manipulation instruction.
RESET input clears ADM1 to 00H.
Figure 11-3: A/D Converter Mode Register (ADM1) Format
Symbol
ADM1
7
6
0
5
4
3
2
0
1
0
0
0
Address After Reset R/W
FF80H 00H R/W
ADCS1
FR12
FR11
FR10
ADCS1
A/D Conversion Operation Control
0
1
Stop conversion operation
Enable conversion operation
FR12
FR11
FR10
Conversion Time Selection Note
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/fx
120/fx
96/fx
288/fx
240/fx
192/fx
Other than above
Setting prohibited
Note:
Set FR10 to FR12 that the A/D conversion time is 15 µs or more.
Caution: Bits 0 to 2 and bit 6 must be set to 0.
Remark: fx: Main system clock oscillation frequency
188
µPD1615, µPD16F15, µPD1616
(2) Analog input channel specification register (ADS1)
This register specifies the analog voltage input port for A/D conversion.
ADS1 is set with an 8-bit memory manipulation instruction.
RESET input clears ADS1 to 00H.
Figure 11-4: Analog Input Channel Specification Register (ADS1) Format
Symbol
ADS1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address After Reset R/W
FF81H 00H R/W
ADS11 ADS10
ADS11 ADS10
Analog Input Channel Specification
0
0
1
1
0
1
0
1
ANI0
ANI1
ANI2
ANI3
Caution: Bits 2 to 7 must be set to 0.
189
µPD1615, µPD16F15, µPD1616
(3) Power-fail compare mode register (PFM)
The power-fail compare mode register (PFM) controls a comparison operation.
RESET input clears PFM to 00H.
Figure 11-5: Power-Fail Compare Mode Register (PFM) Format
Symbol
PFM
7
6
5
0
4
0
3
0
2
0
1
0
0
0
Address After Reset R/W
FF82H 00H R/W
PFEN
PFCM
PFEN
Enables Power-Fail Comparison
0
1
Disables power-fail comparison (used as normal A/D converter)
Enables power-fail comparison (used to detect power failure)
PFCM
Power-Fail Compare Mode Selection
0
0
1
1
ADCR1 ≥ PFT
ADCR1 < PFT
ADCR1 ≥ PFT
ADCR1 < PFT
Generates interrupt request signal INTAD
Does not generate interrupt request signal INTAD
Does not generate interrupt request signal INTAD
Generates interrupt request signal INTAD
Caution: Bits 0 to 5 must be set to 0.
(4) Power-fail compare threshold value register (PFT)
The power-fail compare threshold value register (PFT) sets a threshold value against which the
result of A/D conversion is to be compared.
PFT is set with an 8-bit memory manipulation instruction.
RESET input clears PFT to 00H.
Figure 11-6: Power-fail compare threshold value register (PFT)
Symbol
PFT
7
6
5
4
3
2
1
0
Address After Reset R/W
FF83H 00H R/W
PFT7
PFT6
PFT5
PFT4
PFT3
PFT2
PFT1
PFT0
190
µPD1615, µPD16F15, µPD1616
11.4 A/D Converter Operations
11.4.1 Basic operations of A/D converter
<1> Select one channel for A/D conversion with the analog input channel specification register
(ADS1).
<2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold
state and the input analog voltage is held until the A/D conversion operation is ended.
<4> Bit 7 of the successive approximation register (SAR) is set internally so that the tap selector
starts with a series resistor string voltage tap of (1/2) AVDD.
<5> The voltage difference between the series resistor string voltage tap and analog input is
compared with the voltage comparator. If the analog input is greater than (1/2) AVDD, the MSB
of SAR remains set. If the analog input is smaller than (1/2) AVDD, the MSB is reset.
<6> Next, bit 6 of SAR is automatically set, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 7, as described
below.
• Bit 7 = 1: (3/4) AVDD
• Bit 7 = 0: (1/4) AVDD
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as
follows.
• Analog input voltage ≥ Voltage tap: Bit 6 = 1
• Analog input voltage < Voltage tap: Bit 6 = 0
<7> Comparison is continued in this way up to bit 0 of SAR.
<8> Upon completion of the comparison of 8 bits, an effective digital result value remains in SAR,
and the result value is transferred to and latched in the A/D conversion result register (ADCR1).
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
Caution: The first A/D conversion value just after A/D conversion is undefined.
191
µPD1615, µPD16F15, µPD1616
Figure 11-7: Basic Operation of 8-Bit A/D Converter
Conversion time
Sampling time
Sampling
A/D converter
operation
A/D conversion
C0H
or
40H
Conversion
result
SAR
Undefined
80H
Conversion
result
ADCR1
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode
register (ADM1) is reset (to 0) by software.
If a write operation to the ADM1 and analog input channel specification register (ADS1) is performed
during an A/D conversion operation, the conversion operation is initialized, and if the ADCS1 bit is set
(to 1), conversion starts again from the beginning.
RESET input sets the A/D conversion result register (ADCR1) to 00H.
192
µPD1615, µPD16F15, µPD1616
11.4.2 Input voltage and conversion results
The relation between the analog input voltage input to the analog input pins (ANI0 to ANI3) and
the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the
following expression.
ADCR1 = INT ( VIN x 256 + 0.5)
AVDD
or
(ADCR1 – 0.5) x AVDD - VIN < (ADCR1 + 0.5) x AVDD
256
256
where, INT( ) : Function which returns integer part of value in parentheses
VIN
: Analog input voltage
: AVDD pin voltage
AVDD
ADCR1 : A/D conversion result register (ADCR1) value
Figure 11-8 shows the relation between the analog input voltage and the A/D conversion result.
Figure 11-8: Relation between Analog Input Voltage and A/D Conversion Result
255
254
253
A/D conversion result
(ADCR1)
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511
512 256 512 256 512
1
512 256 512 256 512 256
Input voltage/AVDD
193
µPD1615, µPD16F15, µPD1616
11.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One analog input channel is selected
from among ANI0 to ANI3 with the analog input channel specification register (ADS1) and A/D
conversion is performed.
The following two types of functions can be selected by setting the PFEN flag of the PFM register.
(1) Normal 8-bit A/D converter (PFEN = 0)
(2) Power-fail detection function (PFEN = 1)
(1) A/D conversion (when PFEN = 0)
When bit 7 (ADCS1) of the A/D converter mode register (ADM1) is set to 1 and bit 7 of the power-
fail compare mode register (PFM) is set to 0, A/D conversion of the voltage applied to the analog
input pin specified with the analog input channel specification register (ADS1) starts.
Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result
register (ADCR1), and the interrupt request signal (INTAD) is generated. After one A/D conversion
operation is started and ended, the next conversion operation is immediately started. A/D
conversion operations are repeated until new data is written to ADS1.
If ADS1 is rewritten during A/D conversion operation, the A/D conversion operation under
execution is stopped, and A/D conversion of a newly selected analog input channel is started.
If data with ADCS1 set to 0 is written to ADM1 during A/D conversion operation, the A/D
conversion operation stops immediately.
(2) Power-fail detection function (when PFEN = 1)
When bit 7 (ADCS1) of the A/D converter mode register (ADM1) and bit 7 (PFEN) of the power-
fail compare mode register (PFM) are set to 1, A/D conversion of the voltage applied to the analog
input pin specified with the analog input channel specification register (ADS1) starts.
Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result
register (ADCR1), compared with the value of the power-fail compare threshold value register
(PFT), the INTAD is generated under the condition specified by the PFCM flag of the PFM register.
Caution: When executing power-fail comparison, the interrupt request signal (INTAD) is not
generated on completion of the first conversion after ADCS1 has been set to 1.
INTAD is valid from completion of the second conversion.
194
µPD1615, µPD16F15, µPD1616
Figure 11-9: A/D Conversion
ADM1 rewrite
ADCS1 = 1
ADS1 rewrite
ANIn
ADCS1 = 0
ANIm
A/D conversion
ANIn
ANIn
ANIm
Conversion suspended;
Conversion results are not stored
Stop
ADCR1
ANIn
ANIn
ANIm
INTAD
(PFEN = 0)
INTAD
(PFEN = 1)
First conversion Condition satisfied
Remarks: 1. n = 0, 1, ..., 7
2. m = 0, 1, ..., 7
195
µPD1615, µPD16F15, µPD1616
11.5 A/D Converter Precautions
(1) Current consumption in standby mode
A/D converter stops operating in the standby mode. At this time, current consumption can be
reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop
conversion.
Figure 11-10 shows how to reduce the current consumption in the standby mode.
Figure 11-10: Example Method of Reducing Current Consumption in Standby Mode
AVDD
AD-converter power supply
ADCS1
AV
DD AVREF
/
AVREF
P-ch
Series resistor string
AVSS
(2) Input range of ANI0 to ANI3
The input voltages of ANI0 to ANI3 should be within the specification range. In particular, if a
voltage higher than AVDD/AVREF or lower than AVSS is input (even if within the absolute maximum
rating range), the conversion value of that channel will be undefined and the conversion values
of other channels may also be affected.
(3) Contendingoperations
<1> Contention between A/D conversion result register (ADCR1) write and ADCR1 read by
instruction upon the end of conversion
ADCR1 read is given priority. After the read operation, the new conversion result is written
to ADCR1.
<2> ContentionbetweenADCR1writeandA/Dconvertermoderegister(ADM1)writeoranalog
input channel specification register (ADS1) write upon the end of conversion
ADM1 or ADS1 write is given priority. ADCR1 write is not performed, nor is the conversion
end interrupt request signal (INTAD) generated.
196
µPD1615, µPD16F15, µPD1616
(4) Noisecountermeasures
To maintain 8-bit resolution, attention must be paid to noise input to pin AVDD/AVREF and pins
ANI0 to ANI3. Because the effect increases in proportion to the output impedance of the analog
input source, it is recommended that a capacitor be connected externally as shown in the
Figure 11-11 to reduce noise.
Figure 11-11: Analog Input Pin Handling
REF
V
If there is a possibility that noise equal to or higher than AVDD/A
or equal to or lower than AVSS
may enter, clamp with a diode with a
value (0.3 V or lower).
small V
F
Analog power
supply and
reference
voltage
AVDD /AVREF
input
ANI0 to ANI3
C = 100 to 1000 pF
SS
AV
VSS
(5) ANI0 to ANI3
The analog input pins (ANI0 to ANI3) also function as input port pins (P10 to P13).
When A/D conversion is performed with any of pins ANI0 to ANI3 selected, do not execute a port
input instruction while conversion is in progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the
expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid
applying pulses to pins adjacent to the pin undergoing A/D conversion.
(6) AVDD/AVREF pin input impedance
A series resistor string of approximately 21 kΩ is connected between the AVDD/AVREF pin and the
AVSS pin.
Therefore,iftheoutputimpedanceofthereferencevoltageishigh,thiswillresultinparallelconnection
totheseriesresistorstringbetweentheAVDD pinandtheAVSS pin, andtherewillbealargereference
voltage error.
197
µPD1615, µPD16F15, µPD1616
(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification
register (ADS1) is changed.
Caution is therefore required if a change of analog input pin is performed during A/D conversion.
The A/D conversion result and conversion end interrupt request flag for the pre-change analog
input may be set just before the ADS1 rewrite, if the ADIF is read immediately after the ADS1
rewrite, the ADIF may be set despite to the fact that the A/D conversion for the post-change analog
input has not ended.
When the A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion
operation is resumed.
Figure 11-12: A/D Conversion End Interrupt Request Generation Timing
ADS1 rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
ADS1 rewrite
(start of ANIn conversion)
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR1
INTAD
ANIn
ANIn
ANIm
ANIm
Remarks: 1. n = 0, 1, ..., 7
2. m = 0, 1, ..., 7
(8) Read of A/D conversion result register (ADCR1)
WhenawriteoperationisexecutedtoA/Dconvertermoderegister(ADM1)andanaloginputchannel
specification register (ADS1), the contents of ADCR1 are undefined. Read the conversion result
before write operation is executed to ADM1, ADS1. If a timing other than the above is used, the
correct conversion result may not be read.
198
µPD1615, µPD16F15, µPD1616
11.6 Cautions on Emulation
Toperformdebuggingwithanin-circuitemulator(IE-78001-R-A), theD/Aconvertermoderegister(DAM0)
must be set. DAM0 is a register used to set the I/O board (IE-78K0-NS-P04).
11.6.1 D/A converter mode register (DAM0)
DAM0 is necessary if the power-fail detection function is used. Unless DAM0 is set, the power-fail
detection function cannot be used. DAM0 is a write-only register.
Because the IE-78K0-NS-P04 uses an external analog comparator and a D/A converter to implement
part of the power-fail detection function, the reference voltage must be controlled. Therefore, set bit 0
(DACE) of DAM0 to 1 when using the power-fail detection function.
Figure 11-13: D/A Converter Mode Register (DAM0) Format
Symbol
DAM0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address After Reset R/W
FF84H 00H
DACE
W
DACE
Reference Voltage Control
0
1
Disabled
Enabled (when power-fail detection function is used)
Cautions: 1. DAM0 is a special register that must be set when debugging is performed with an
in-circuit emulator. Even if this register is used, the operation of the µPD1615
Subseries is not affected. However, delete the instruction that manipulates this
register from the program at the final stage of debugging.
2. Bits 7 to 1 must be set to 0.
199
µPD1615, µPD16F15, µPD1616
[Memo]
200
µPD1615, µPD16F15, µPD1616
Chapter 12 Serial Interface Outline
12.1 Serial Interface Outline
The µPD1615 subseries incorporates two channels of serial interfaces.
Table 12-1: Differences between the Serial Interface Channels
Serial Transfer Mode
SIO 30 (3-wire serial I/O)
UART
µPD1615
µPD16F15
µPD1616
¡
¡
¡
¡
¡
¡
Remark:
¢ : Provided
— : Not provided
201
µPD1615, µPD16F15, µPD1616
[Memo]
202
µPD1615, µPD16F15, µPD1616
Chapter 13 Serial Interface SIO30
13.1 Serial Interface Channel 30 Functions
The SIO30 has the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used if serial transfer is not performed. For details, see 15.5.1 Operation Stop Mode.
(2) 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3), serial output line
(SO3), and serial input line (SI3).
Sincesimultaneoustransmitandreceiveoperationsareenabledin3-wireserialI/Omode, theprocessing
time for data transfers is reduced.
The first bit in the 8-bit data in serial transfers is fixed as the MSB.
3-wireserialI/OmodeisusefulforconnectiontoaperipheralI/Odevicethatincludesaclock-synchronous
serial interface, like a display controller, etc. For details see 13.5.2 Three-Wire Serial I/O Mode.
Figure 13-1 shows a block diagram of the SIO30.
Figure 13-1: Block Diagram of SIO30
Internal bus
8
Direction control circuit
8
Serial I/O shift register
SI3/P127/S0
30 (SIO30)
SO3/P126/S1
Interruption request
signal generator
Serial clock
counter
SCK3/P125/S2
INTCSI3
f
f
X
X
/22
/24
Serial clock
control circuit
Selector
TM50
CSIE30
MODE0
SCL301
SCL300
203
µPD1615, µPD16F15, µPD1616
13.2 Serial Interface Channel 30 Configuration
The SIO30 includes the following hardware.
Table 13-1: Composition of SIO30
Item
Configuration
Serial I/O shift register 30 (SIO30)
Serial operation mode register 30 (CSIM30)
Registers
Control registers
(1) Serial I/O shift register 30 (SIO30)
This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift
operations) synchronized with the serial clock.
SIO30 is set by an 8-bit memory manipulation instruction.
When “1” is set to bit 7 (CSIE30) of the serial operation mode register 30 (CSIM30), a serial operation
can be started by writing data to or reading data from SIO30.
When transmitting, data written to SIO30 is output via the serial output (SO3).
When receiving, data is read from the serial input (SI3) and written to SIO30.
The RESET signal resets the register value to 00H.
Caution: Do not access SIO30 during a transmit operation unless the access is triggered
by a transfer start. (Read is disabled when MODE = 0 and write is disabled when
MODE = 1.)
13.3 List of SFRs (Special Function Registers)
Table 13-2: List of SFRs (Special Function Registers)
Units available for bit manipulation
SFR name
Symbol
R/W
Value when reset
00H
1 bit
8 bits
16 bits
—
Serial operation mode register 30
Serial I/O shift register 30
CSIM30
SIO30
R/W
—
—
204
µPD1615, µPD16F15, µPD1616
13.4 Serial Interface Control Registers
The SIO3 uses the following type of register for control functions.
• Serial operation mode register 30 (CSIM30)
(1) Serial operation mode register 30 (CSIM30)
This register is used to enable or disable SIO30’s serial clock, operation modes, and specific
operations.
CSIM30 can be set via a 1-bit or 8-bit memory manipulation instruction.
The RESET input sets the value to 00H.
Figure 13-2: Format of Serial Operation Mode Register 30 (CSIM30)
Address: FF6FH When reset: 00H
R/W
5
Symbol
CSIM30
7
6
0
4
0
3
0
2
1
0
CSIE30
0
MODE0
SCL301
SCL300
Enable/disable specification for SIO30
Serial counter
CSIE30
Note 1
Shift register operation
Operation stop
Port
Port function
0
1
Clear
Operationenable
Count operation enable
Serial operation + port function
Transfer operation modes and flags
Transfer start trigger
Write to SIO30
MODE0
Operationmode
P126/SO3/SA
SO3 output
0
1
Transmit/receive mode
Note 2
Receive-only mode
Read from SIO30
Port function
SCL301
SCL300
Clock selection
0
0
1
1
0
1
0
1
External clock input
2
fx/2
fx/2
4
TM50 output
Notes:
1. When CSIE30 = 0 (SIO30 operation stop status), the pins connected to SI3 and SO3 can
be used for port functions.
2. When MODE0 = 1 (Receive mode), pin P126/SO3/S1 can be used for port function.
Caution: If TM50 is used as clock generation for SIO30, no clock will be supplied to SIO30
unless TOE50 is set to 1. In this case a square wave output signal is output from the
TO50 pin.
205
µPD1615, µPD16F15, µPD1616
13.5
Serial Interface Operations
This section explains on two modes of SIO30.
13.5.1 Operation stop mode
This mode is used if the serial transfers are not performed to reduce power consumption.
During the operation stop mode, the pins can be used as normal I/O ports as well.
(1) Register settings
The operation stop mode can be set via the serial operation mode register 30 (CSIM30).
CSIM30 can be set via 1-bit or 8-bit memory manipulation instructions.
The RESET input sets the value to 00H.
Figure 13-3: Format of Serial Operation Mode Register 30 (CSIM30)
Address: FF6FH When reset: 00H
R/W
5
Symbol
CSIM30
7
6
0
4
0
3
0
2
1
0
CSIE30
0
MODE0
SCL301
SCL300
SIO30 operation enable/disable specification
CSIE30
Note
Shift register operation
Operation stop
Serial counter
Port
0
1
Clear
Count operation enable
Port function
Serial operation + port function
Operationenable
Note:
When CSIE30 = 0 (SIO30 operation stop status), the pins connected to SI3 and SO3 can
be used for port functions.
206
µPD1615, µPD16F15, µPD1616
13.5.2 Three-wire serial I/O mode
The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-
synchronous serial interface, a display controller, etc.
This mode executes the data transfer via three lines: a serial clock line (SCK3), serial output line
(SO3), and serial input line (SI3).
(1) Register settings
The 3-wire serial I/O mode is set via serial operation mode register 30 (CSIM30).
CSIM30 can be set via 1-bit or 8-bit memory manipulation instructions.
The RESET input set the value to 00H .
Figure 13-4: Format of Serial Operation Mode Register 30 (CSIM30)
Address: FF6FH When reset: 00H
R/W
5
Symbol
CSIM30
7
6
0
4
0
3
0
2
1
0
CSIE30
0
MODE0
SCL301
SCL300
Enable/disable specification for SIO30
Serial counter
CSIE30
Note 1
Shift register operation
Operation stop
Port
Port function
0
1
Clear
Operationenable
Count operation enable
Serial operation + port function
Transfer operation modes and flags
Transfer start trigger
Write to SIO30
MODE0
Operationmode
P126/SO3/S1
SO3 output
0
1
Transmit/receive mode
Note 2
Receive-only mode
Read from SIO30
Port function
SCL301
SCL300
Clock selection (fX = 8.00 MHz)
0
0
1
1
0
1
0
1
External clock input
2
fx/2
fx/2
4
TM50 output
Note:
1. When CSIE30 = 0 (SIO30 operation stop status), the pins connected to SI3 and SO3 can
be used for port functions.
2. When M0DE0 = 1 (Receive mode), pin P126/SO3/S1 can be used for port function.
Caution: If TM50 is used as clock generation for SIO30, no clock will be supplied to SIO30
unless TOE50 is set to 1. In this case a square wave output signal is output from the
TO50 pin.
207
µPD1615, µPD16F15, µPD1616
(2) Communication Operations
In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is
sent or received synchronized with the serial clock.
The serial I/O shift register 30 (SIO30) is shifted synchronized with the falling edge of the serial clock.
The transmission data is held in the SO3 latch and is output from the SO3 pin. The data is received
via the SI30 pin synchronized with the rising edge of the serial clock is latched to SIO30.
The completion of an 8-bit transfer automatically stops operation of SIO30 and sets a serial transfer
completion flag.
Figure 13-5: Timing of Three-wire Serial I/O Mode
Serial clock
SI3
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO3
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Serial transfer
completion flag
Transfer completion
Transfer starts in synchronized with the serial clock’s falling edge
(3) Transfer start
A serial transfer starts when the following two conditions have been satisfied and transfer data has been
set to serial I/O shift register 30 (SIO30).
• The SIO30 operation control bit (CSIE30) = 1
• After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level.
• Transmit/receive mode
When CSIE30 = 1 and MODE0 = 0, transfer starts when writing to SIO30.
• Receive-only mode
When CSIE30 = 1 and MODE0 = 1, transfer starts when reading from SIO30.
Caution: After the data has been written to SIO30, the transfer will not start even if the CSIE30
bit value is set to “1”.
The completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial
transfer completion flag.
208
µPD1615, µPD16F15, µPD1616
[Memo]
209
µPD1615, µPD16F15, µPD1616
Chapter 14 Serial Interface UART
14.1 Serial Interface UART Functions
The serial interface UART has the following two modes.
(1) Operation stop mode
This mode is used if the serial transfer is performed to reduce power consumption.
For details, see 14.5.1 Operation Stop Mode.
(2) Asynchronous serial interface (UART) mode
This mode enables the full-duplex operation where one byte of data is transmitted and received after
the start bit.
The on-chip dedicated UART baud rate generator enables communications using a wide range of
selectable baud rates.
For details, see 14.5.2 Asynchronous Serial Interface (UART) Mode.
Figure 14-1 shows a block diagram of the UART macro.
Figure 14-1: Block Diagram of UART
Internal bus
ASIM0
Receive
buffer
RXB0
TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0
RxS0
ASIS0
Transmit
shift
register
Receive
shift
register
TXS0
RxD0/P123/S4
TxD0/P124/S3
PE0 FE0 OVE0
Receive
control
parity
Transmit
control
parity
INTSER
INTST
INTSR
check
addition
Baud rate
generator
f
X
/2 - f
/28
X
210
µPD1615, µPD16F15, µPD1616
14.2 Serial Interface UART Configuration
The UART includes the following hardware.
Table 14-1: Configuration of UART
Item
Configuration
Transmit shift register 1 (TXS0)
Receive shift register 1 (RXS0)
Registers
Receive buffer register (RXB0)
Control registers
Asynchronous serial interface mode register (ASIM0)
Asynchronous serial interface status register (ASIS0)
Baud rate generator control register (BRGC0)
(1) Transmit shift register 1 (TXS0)
This register is for setting the transmit data. The data is written to TXS0 for transmission as serial data.
When the data length is set as 7 bits, bits 0 to 6 of the data written to TXS0 are transmitted as serial
data. Writing data to TXS0 starts the transmit operation.
TXS0 can be written via 8-bit memory manipulation instructions. It cannot be read.
When RESET is input, its value is FFH.
Caution:
Do not write to TXS0 during a transmit operation.
The same address is assigned to TXS0 and the receive buffer register (RXB0). A read
operation reads values from RXB0.
(2) Receive shift register 1 (RXS0)
This register converts serial data input via the RxD pin to parallel data. When one byte of the data is
received at this register, the receive data is transferred to the receive buffer register (RXB0).
RXS0 cannot be manipulated directly by a program.
(3) Receive buffer register (RXB0)
This register is used to hold receive data. When one byte of data is received, one byte of new receive
data is transferred from the receive shift register (RXS0).
When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXB0. The MSB must be
set to “0” in RXB0.
RXB0 can be read to via 8-bit memory manipulation instructions. It cannot be written to.
When RESET is input, its value is FFH.
Caution:
The same address is assigned to RXB0 and the transmit shift register (TXS0). During
a write operation, values are written to TXS0.
(4) Transmission control circuit
The transmission control circuit controls transmit operations, such as adding a start bit, parity bit, and
stop bit to data that is written to the transmit shift register (TXS0), based on the values set to the
asynchronous serial interface mode register (ASIM0).
(5) Reception control circuit
The reception control circuit controls the receive operations based on the values set to the asynchronous
serial interface mode register (ASIM0). During a receive operation, it performs error checking, such as
parityerrors, andsetsvariousvaluestotheasynchronousserialinterfacestatusregister(ASIS0)according
to the type of error that is detected.
211
µPD1615, µPD16F15, µPD1616
14.3 List of SFRS (Special Function Registers)
Table 14-2: List of SFRs (Special Function Registers)
Units available for bit
manipulation
Value
when
reset
SFR name
Transmit shift register
Symbol R/W
1 bit
8 bits 16 bits
TXS0
RXB0
W
R
—
¢
—
FFH
Receive buffer register
¢
¢
¢
—
—
Asynchronous serial interface mode register
ASIM0 R/W
Asynchronous serial interface status register ASIS0
W
—
00H
BRGC
Baud rate generator control register
0
R/W
—
¢
—
14.4 Serial Interface Control Registers
The UART uses the following three types of registers for control functions.
• Asynchronous serial interface mode register (ASIM0)
• Asynchronous serial interface status register (ASIS0)
• Baud rate generator control register (BRGC0)
(1) Asynchronous serial interface mode register (ASIM0)
This is an 8-bit register that controls the UART serial transfer operation.
ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions.
RESET input sets the value to 00H.
Figure 14-2 shows the format of ASIM0.
212
µPD1615, µPD16F15, µPD1616
Figure 14-2: Format of Asynchronous Serial Interface Mode Register (ASIM0)
Address: FFA0H When reset: 00H
R/W
5
Symbol
ASIM0
7
6
4
3
2
1
0
0
TXE0
RXE0
PS01
PS00
CL0
SL0
ISRM0
TXE0
RXE0
Operationmode
Operation stop
RxD0/P123/S4pin functionTxD0/P124/S3pin function
0
0
0
1
Port function
Port function
Port function
UART0 mode
(receive only)
Serialoperation
1
1
0
1
UART0 mode
(transmit only)
Port function
Serial operation
Serial operation
UART0 mode
Serial operation
(transmit and receive)
PS01
PS00
Parity bit specification
0
0
0
1
No parity
Zero parity always added during transmittion
No parity detection during reception (parity errors do not occur)
1
1
0
1
Odd aprity
Even parity
CL0
0
Character length specification
7 bits
1
8 bits
SL0
0
Stop bit length specification for transmit data
1 bit
1
2 bits
ISRM0
Receive completion interrupt control when error occurs
0
1
Receive completion interrupt is issued when an error occurs
Receive completion interrupt is not issued when an error occurs
Caution:
Do not switch the operation mode until after the current serial transmit/receive
operation has stopped.
213
µPD1615, µPD16F15, µPD1616
(2) Asynchronous serial interface status register (ASIS0)
When a receive error occurs during UART mode, this register indicates the type of error.
ASIS0 can be read using an 8-bit memory manipulation instruction.
When RESET is input, its value is 00H.
Figure 14-3: Format of Asynchronous Serial Interface Status Register (ASIS0)
Address: FFA1H When reset: 00H
R
Symbol
ASIS0
7
0
6
0
5
0
4
0
3
0
2
1
0
PE0
FE0
OVE0
PE0
0
Parity error flag
Framing error flag
Overrun error flag
No parity error
Parity error
0
(Incorrect parity bit detected)
FE0
0
No framing error
Note 1
1
Framing error
(Stop bit not detected)
OVE0
0
1
No overrun error
Note 2
Overrun error
(Nextreceiveoperationwascompletedbeforedatawasreadfromreceivebufferregister)
Notes:
1. Even if a stop bit length of two bits has been set to bit 2 (SL0) in the asynchronous serial
interface mode register (ASIM0), the stop bit detection during a receive operation only
applies to a stop bit length of 1 bit.
2. Be sure to read the contents of the receive buffer register (RXB0) when an overrun error
has occurred.
Until the contents of RXB0 are read, further overrun errors will occur when receiving data.
(3) Baud rate generator control register (BRGC0)
This register sets the serial clock for UART.
BRGC can be set via an 8-bit memory manipulation instruction.
When RESET is input, its value is 00H.
Figure 14-4 shows the format of BRGC0.
214
µPD1615, µPD16F15, µPD1616
Figure 14-4: Format of Baud Rate Generator Control Register (BRGC0)
Address: FFA2H When reset: 00H
R/W
5
Symbol
BRGC0
7
0
6
4
3
2
1
0
TPS02
TPS01
TPS00
MDL03
MDL02
MDL01
MDL00
(fX = 8.00 MHz)
TPS02
TPS01
TPS00
Source clock selection for 5-bit counter
n
1
2
3
4
5
6
7
8
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2
2
3
4
5
6
7
8
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
MDL03
MDL02
MDL01
MDL00
Inputclockselectionforbaudrategenerator
fSCK/16
k
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
Setting prohibit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
Caution: Writing to BRGC0 during a communication operation may cause abnormal output
from the baud rate generator and disable further communication operations.
Therefore, do not write to BRGC0 during a communication operation.
Remarks: 1. fSCK: Source clock for 5-bit counter
2. n: Value set via TPS00 to TPS02 (1 ≤ n ≤ 8)
3. k: Value set via MDL00 to MDL03 (0 ≤ k ≤ 14)
215
µPD1615, µPD16F15, µPD1616
14.5
Serial Interface Operations
This section explains the three modes of the UART.
14.5.1 Operation stop mode
This mode is used when serial transfers are not performed to reduce power consumption.
In the operation stop mode, pins can be used as ordinary ports.
(1) Register settings
Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM0).
ASIM0 can be set via 1-bit or 8-bit memory manipulation instructions.
When RESET is input, its value is 00H.
Figure 14-5: Register Settings
Address: FFA0H When reset: 00H
R/W
5
Symbol
ASIM0
7
6
4
3
2
1
0
0
TXE0
RXE0
PS01
PS00
CL0
SL0
ISRM0
TXE0
RXE0
Operationmode
Operation stop
RxD0/P123/S4pin functionTxD0/P124/S3pin function
0
0
0
1
Port function
Port function
Port function
UART0 mode
(receive only)
Serialoperation
1
1
0
1
UART0 mode
(transmit only)
Port function
Serialoperation
Serialoperation
UART0 mode
Serialoperation
(transmit and receive)
Caution: Do not switch the operation mode until after the current serial transmit/receive
operation has stopped.
14.5.2 Asynchronous serial interface (UART) mode
This mode enables full-duplex operation where one byte of the data is transmitted or received
after the start bit.
The on-chip dedicated UART baud rate generator enables communications by using a wide range of
selectable baud rates.
(1) Register settings
The UART mode settings are made via the asynchronous serial interface mode register (ASIM0),
asynchronous serial interface status register (ASIS0), and the baud rate generator control register
(BRGC0).
216
µPD1615, µPD16F15, µPD1616
(a) Asynchronous serial interface mode register (ASIM0)
ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions.
When RESET is input, its value is 00H.
Figure 14-6: Asynchronous serial interface mode register (ASIM0)
Address: FFA0H When reset: 00H
R/W
5
Symbol
ASIM0
7
6
4
3
2
1
0
0
TXE0
RXE0
PS01
PS00
CL0
SL0
ISRM0
TXE0
PEX0
Operation mode
RxD0/P123/S4pin functionTxD0/P124/S3pin function
0
0
0
1
Operation stop
Port function
Port function
Port function
UART0 mode
(receive only)
Serialoperation
1
1
0
1
UART0 mode
(transmit only)
Port function
Serial operation
Serial operation
UART0 mode
Serial operation
(transmit and receive)
PS01
PS00
Parity bit specification
0
0
0
1
No parity
Zero parity always added during transmittion
No parity detection during reception (parity errors do not occur)
1
1
0
1
Odd aprity
Even parity
CL0
0
Character length specification
7 bits
0
8 bits
SL0
0
Stop bit length specification for transmit data
1 bit
1
2 bits
ISRM0
Receive completion interrupt control when error occurs
0
1
Receive completion interrupt is issued when an error occurs
Receive completion interrupt is not issued when an error occurs
Caution:
Do not switch the operation mode until after the current serial transmit/receive
operation has stopped.
217
µPD1615, µPD16F15, µPD1616
(b) Asynchronous serial interface status register (ASIS0)
ASIS0 can be read using an 8-bit memory manipulation instruction.
When RESET is input, its value is 00H.
Figure 14-7: Asynchronous serial interface status register (ASIS0)
Address: FFA1H When reset: 00H
R
Symbol
ASIS0
7
0
6
0
5
0
4
0
3
0
2
1
0
PE0
FE0
OVE0
PE0
0
Parity error flag
Framing error flag
Overrun error flag
No parity error
Parity error
1
(Incorrect parity bit detected)
FE0
0
No framing error
Note 1
1
Framing error
(Stop bit not detected)
OVE0
0
1
No overrun error
Note 2
Overrun error
(Next receive operation was completed before data was read from receive buffer register)
Notes:
1. Even if a stop bit length of two bits has been set to bit 2 (SL0) in the asynchronous serial
interface mode register (ASIM0), stop bit detection during a receive operation only applies
to a stop bit length of 1 bit.
2. Be sure to read the contents of the receive buffer register (RXB0) when an overrun error
has occurred.
Until the contents of RXB0 are read, further overrun errors will occur when receiving data.
218
µPD1615, µPD16F15, µPD1616
(c) Baud rate generator control register (BRGC0)
BRGC0 can be set by an 8-bit memory manipulation instruction.
When RESET is input, its value is 00H.
Figure 14-8: Baud rate generator control register (BRGC0)
Address: FFA2H When reset: 00H
R/W
Symbol
BRGC0
7
0
6
5
4
3
2
1
0
TPS02
TPS01
TPS00
MDL03
MDL02
MDL01
MDL00
(fX = 8.00 MHz)
TPS02
TPS01
TPS00
Source clock selection for 5-bit counter
n
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
MDL03
MDL02
MDL01
MDL00
Input clock selection for baud rate generator
k
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
Setting prohibit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
Caution: Writing to BRGC0 during a communication operation may cause abnormal output
from the baud rate generator and disable further communication operations. There-
fore, do not write to BRGC0 during a communication operation.
Remarks: 1. fSCK: Source clock for 5-bit counter
2. n: Value set via TPS00 to TPS02 (1 ≤ n ≤ 8)
3. k: Value set via MDL00 to MDL03 (0 ≤ k ≤ 14)
219
µPD1615, µPD16F15, µPD1616
The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main
system clock.
• Use of main system clock to generate a transmit/receive clock for baud rate
The main system clock is divided to generate the transmit/receive clock. The baud rate generated
by the main system clock is determined according to the following formula.
fX
[Baud rate] =
[bps]
2n+1(k + 16)
fX : Oscillation frequency of main system clock (in Hz)
n : Value set via TPS00 to TPS02 (1 ≤ n ≤ 8)
For details, see Table 17-3.
k : Value set via MDL00 to MDL02 (0 ≤ k ≤ 14)
Table 17-3 shows the relation between the 5-bit counter’s source clock assigned to bits 4 to 6 (TPS00
to TPS02) of BRGC0 and the “n” value in the above formula.
Table 14-3: Relation between 5-bit Counter’s Source Clock and “n” Value
TPS02
TPS01
TPS00
5-bit counter’s source clock selected
n
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
Remark: fX: Oscillation frequency of main system clock.
220
µPD1615, µPD16F15, µPD1616
• Error tolerance range for baud rates
The tolerance range for baud rates depends on the number of bits per frame and the counter’s
division rate [1/(16 + k)].
Table 14-4 describes the relation between the main system clock and the baud rate and Figure
14-9 shows an example of a baud rate error tolerance range.
Table 14-4: Relation between Main System Clock and Baud Rate
fx = 8.000 MHz
BRGC0
fx = 4.000 MHz
BRGC0
Baud rate
(bps)
ERR(%)
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
ERR(%)
0.16
0.16
0.16
0.16
0.16
0.00
0.16
–
600
1200
7AH
6AH
5AH
4AH
3AH
2AH
1AH
0AH
02H
6AH
5AH
4AH
3AH
2AH
1AH
0AH
–
2400
4800
9600
19200
38400
76800
115200
–
–
Remarks: 1. fX: Oscillation frequency of main system clock
2. n: Value set via TPS00 to TPS02 (1 ≤ n ≤ 8)
3. k: Value set via MDL00 to MDL03 (0 ≤ k ≤ 14)
221
µPD1615, µPD16F15, µPD1616
Figure 14-9: Error Tolerance (when k = 0), including Sampling Errors
Ideal
sampling
point
32T
64T
256T
288T
320T
352T
304T
P
336T
Basic timing
(clock cycle T)
START
START
D0
D7
STOP
15.5T
STOP
High-speed clock
(clock cycle T’)
enabling normal
reception
D0
D7
P
Sampling error
0.5T
30.45T
60.9T
67.1T
304.5T
15.5T
Low-speed clock
(clock cycle T”)
enabling normal
reception
START
D0
D7
P
STOP
33.55T
301.95T
335.5T
Remark:
T: 5-bit counter’s source clock cycle
Baud rate error tolerance (when k = 0) =
±15.5
320
x 100 = 4.8438 (%)
222
µPD1615, µPD16F15, µPD1616
(2) Communication operations
(a) Data format
As shown in Figure 14-10, the format of the transmit/receive data consists of a start bit, character
bits, a parity bit, and one or more stop bits.
The asynchronous serial interface mode register (ASIM0) is used to set the character bit length, parity
selection, and stop bit length within each data frame.
Figure 14-10: Format of Transmit/Receive Data in Asynchronous Serial Interface
1 data frame
Start
bit
Parity
bit
Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
• Start bit ............. 1 bit
• Character bits ... 7 bits or 8 bits
• Parity bit ...........
• Stop bit(s) ........
Even parity, odd parity, zero parity, or no parity
1 bit or 2 bits
When “7 bits” is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid,
so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7)
must be set to “0”.
The asynchronous serial interface mode register (ASIM0) and the baud rate generator control register
(BRGC0) are used to set the serial transfer rate.
If a receive error occurs, information about the receive error can be recognized by reading the
asynchronous serial interface status register (ASIS0).
223
µPD1615, µPD16F15, µPD1616
(b) Parity types and operations
The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used
by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit
(the odd-number bit) can be detected. When zero parity or no parity is set, errors are not detected.
(1)Even parity
• During transmission
The number of bits in transmit data that includes a parity bit is controlled so that there are an even
number of “1” bits. The value of the parity bit is as follows.
If the transmit data contains an odd number of “1” bits : the parity bit value is “1”
If the transmit data contains an even number of “1” bits: the parity bit value is “0”
• During reception
The number of “1” bits is counted among the transfer data that include a parity bit, and a parity
error occurs when the result is an odd number.
(2)Odd parity
• During transmission
The number of bits in transmit data that includes a parity bit is controlled so that there is an odd
number of “1” bits. The value of the parity bit is as follows.
If the transmit data contains an odd number of “1” bits : the parity bit value is “0”
If the transmit data contains an even number of “1” bits: the parity bit value is “1”
• During reception
The number of “1” bits is counted among the transfer data that include a parity bit, and a parity
error occurs when the result is an even number.
(3)Zero parity
During transmission, the parity bit is set to “0” regardless of the transmit data.
During reception, the parity bit is not checked. Therefore, no parity errors will occur regardless
of whether the parity bit is a “0” or a “1”.
(4)No parity
No parity bit is added to the transmit data.
During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no
parity errors will occur.
224
µPD1615, µPD16F15, µPD1616
(c) Transmission
The transmit operation is started when transmit data is written to the transmit shift register (TXS0).
A start bit, parity bit, and stop bit(s) are automatically added to the data.
Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a
transmit completion interrupt (INTST) is issued.
The timing of the transmit completion interrupt is shown in Figure 14-11.
Figure 14-11: Timing of Asynchronous Serial Interface Transmit Completion Interrupt
(i) Stop bit length: 1 bit
TxD0 (output)
INTST
START
D0
D1
D2
D6
D7
Parity STOP
(ii) Stop bit length: 2 bits
TxD0 (output)
INTST
START
D0
D1
D2
D6
D7
Parity
STOP
Caution: Do not write to the asynchronous serial interface mode register (ASIM0) during a
transmit operation. Writing to ASIM0 during a transmit operation may disable further
transmit operations (in such cases, enter a RESET to restore normal operation).
Whether or not a transmit operation is in progress can be determined via software
using the transmit completion interrupt (INTST) or the interrupt request flag (STIF)
that is set by INTST.
225
µPD1615, µPD16F15, µPD1616
(d) Reception
The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface
mode register (ASIM0), and input data via RxD pin is sampled.
The serial clock specified by ASIM0 is used when sampling the RxD0 pin.
When the RxD0 pin goes low, the 5-bit counter begins counting and the start timing signal for data
sampling is output if half of the specified baud rate time has elapsed. If the sampling of the RxD0 pin
input of this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit
counter is initialized and starts counting and data sampling begins. After the start bit is recognized,
the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data
frame is completed.
Once the reception of one data frame is completed, the receive data in the shift register is transferred
to the receive buffer register (RXB0) and a receive completion interrupt (INTSR) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB0
and INTSR occurs (see Figure 14-9).
If the RXE0 bit is reset (to “0”) during a receive operation, the receive operation is stopped
immediately.
At this time, neither the contents of RXB0 and ASIS0 do not change, nor does INTSR or INTSER occur.
Figure 14-12 shows the timing of the asynchronous serial interface receive completion interrupt.
Figure 14-12: Timing of Asynchronous Serial Interface Receive Completion Interrupt
RxD0 (input)
INTSR
START
D0
D1
D2
D6
D7
Parity STOP
Caution: Be sure to read the contents of the receive buffer register (RXB0) even when a receive
error has occurred. Overrun errors will occur during the next data receive operations
and the receive error status will remain until the contents of RXB0 are read.
226
µPD1615, µPD16F15, µPD1616
(e) Receive errors
Three types of errors can occur during a receive operation: parity error, framing error, or overrun
error.
If, as the result of the data reception, an error flag is set to the asynchronous serial interface
status register (ASIS0), a receive error interrupt (INTSER) will occur. Receive error interrupts are
generated before receive interrupts (INTSR). Table 17-5 lists the causes behind receive errors.
As part of receive error interrupt (INTSER) servicing, the contents of ASIS0 can be read to determine
which type of error occurred during the receive operation (see Table 14-5 and Figure 14-13).
The content of ASIS0 is reset (to “0”) if the receive buffer register (RXB0) is read or when the next
data is received (if the next data contains an error, another error flag will be set).
Table 14-5: Causes of Receive Errors
Receiveerror
Parity error
Cause
ASIS0 value
04H
Parity specified during transmission does not match parity of receive data
Framingerror Stop bit was not detected
Overrunerror Reception of the next data was completed before data was read from the
receive buffer register
02H
01H
Figure 14-13: Receive Error Timing
RxD0 (input)
START
D0
D1
D2
D6
D7
Parity STOP
INTSR
INTSER
INTSER
(When parity error occurs)
Cautions: 1. The contents of ASIS0 are reset (to “0”) when the receive buffer register (RXB0) is
read or when the next data is received. To obtain information about the error, be sure
to read the contents of ASIS0 before reading RXB0.
2. Be sure to read the contents of the receive buffer register (RXB0) even when a receive
errorhasoccurred. Overrunerrorswilloccurduringthenextdatareceiveoperations
and the receive error status will remain until the contents of RXB0 are read.
227
µPD1615, µPD16F15, µPD1616
14.6 Standby Function
Serial transfer operations can be performed during HALT mode.
During STOP mode, serial transfer operations are stopped and the values in the asynchronous serial
interface mode register (ASIM0), transmit shift register (TXS0), receive shift register (RxS0), and
receive buffer register (RXB0) remain as they were just before the clock was stopped.
Output from the TxD0 pin retains the immediately previous data if the clock is stopped (if the system
enters STOP mode) during a transmit operation. If the clock is stopped during a receive operation, the
data received before the clock was stopped is retained and all subsequent operations are stopped. The
receive operation can be restarted once the clock is restarted.
228
µPD1615, µPD16F15, µPD1616
[Memo]
229
µPD1615, µPD16F15, µPD1616
Chapter 15 VAN Controller
15.1 Features
- The VAN UART is compatible with the ISO 11519 VAN standard, Part 3, revision 4.00.
- The VAN UART executes all the VAN frame types:
* Programmed in autonomous mode (RANK bit = 0), it performs the transmission and reception of
data frames (transmits from the SOF field or from the IDEN field) and read frames as well as the
in frame response.
* Programmed in synchronous mode (RANK bit = 1), it performs the transmission (transmits from
the IDEN field only) and reception of data and read frames as well as the in frame response.
- The transmission and reception of these frames can be done up to 500 kTS/s for an 8 MHz
quartz clock.
- The VAN frame is encoded in Enhanced Manchester.
- In autonomous mode the choice of the bus speed is programmable via a 4 bit prescaler
(DIAG_CTRL_REG register). A bit of this prescaler performing a division by 1,2,3 or 5 permits the
use of “non binary” quartz clocks having a frequency of 3, 5 or 6 MHz.
- The VAN UART carries out the collision detection and goes into receive mode if lost arbitration
before the end of the current Time Slot (TS). The circuit generates an interrupt if required by the
user. The collision is not considered as an error.
- The VAN UART re-synchronises the transmission and reception clocks at each edge detected on
the bus line.
- The VAN UART incorporates a cell calculating the CRC in transmission and in reception.
- The VAN UART integrates the line diagnosis function, which consists of:
* The digital filtering of the outputs of the three comparators RXD0, RXD1 and RXD2.
* Asynchronous diagnosis.
* Synchronous diagnosis.
* Transmission diagnosis (with enable bit).
* Protocol error (8 consecutive dominant TS).
* Possibility to force one of the three comparators.
- The VAN UART signals the errors that occurred on the VAN bus and generate an interrupt con-
nected to each error if required by the user.
3 bits implanted in the status register STAT_REG differentiate the errors in transmission or in
reception.
230
µPD1615, µPD16F15, µPD1616
15.2
Overview of the VAN Bus
15.2.1 VAN UART Description
The VAN UART cell integrated in this microcontroller is comform to the VAN Standard (ISO 11519,
Part 3, Rev 4.00).
15.2.2 VAN UART Interface
Figure 15-1: VAN UART Interface
UDL-I/F
Data
Bus bridge Block
Data
Status
Status
UDL
TxVAN
Rx0VAN
UDLCCL register
UDLCKEN 0 0 0 0 0 0
UDLCCL
VAN-UART
0
Rx1VAN
Rx2VAN
CLK
X1
Interrupt control
WDT
RESET
RESET
Chip
RESET
The VAN UART is realised with one transmit register and one receive register. The application
software may check the status registers in order to get information of the bus state and the re-
ceived or transmitted messages. The device has the capability to generate an interrupt as soon as
one byte is transmitted or received. Care has to be taken when transmitting or receiving in order
not to miss the TBE (INT1) or RDA (INT2) interrupts occuring on every byte (TBE means transmit
buffer empty and RDA means received data available). At each of these interrupts, the application
software has to perform a data exchange between the application and the TX/RX register.
231
µPD1615, µPD16F15, µPD1616
Figure 15-2: VAN UART Block Diagram
Rx0VAN
TxVAN
Rx1VAN
Rx2VAN
Diagnosis Logic
VAN CORE
VAN UART
Registers
TX/RX Shift Register
RKO_REG
IFR_REG
CRC Generator/Checker
Bit Time Logic
CTRL_REG
CONF_REG
DIAG_CTRL_REG
Error
Management
Logic
Bit Stream
Processor
Interface Management Logic
Internal Bus
Interface Management Logic (IML) :
The IML executes the CPU’s transmission and reception commands and controls the data transfer
between CPU, Rx/Tx and VAN registers. It provides the VAN UART interface with Rx/Tx data from
the memory mapped Register Block. It sets and resets the VAN status informations and generates
interrupts to the CPU. It also generates the bit clock according the divider chosen by application
software.
232
µPD1615, µPD16F15, µPD1616
This divider divides the input clock by the value defined in the VAN Prescaler. The following
picture shows the generation of the VAN clock :
Figure 15-3: Generation of the VAN Clock
CPU's
CK0
.
1, 2, 3, 5
CK2
—
.
CK1
.
—
.
2
.
CK3
—
.
2
CKCO
The prescaler (CK0-CK3) is chosen in the DIAG_CTRL_REG register.
VAN Core :
The VAN Core incorporates two main state machines (transmission and reception) and controls the
output driver TxVAN, the CRC logic and the Tx/Rx shift register. It also controls the synchroniza-
tion to the VAN bus (according to VAN specifications) by the Bit Time Logic (BTL). It also detects
all the symbols included in a VAN frame like the Start Of Frame (SOF), the End Of Data (EOD),
the Acknowledge (ACK), the End Of Frame (EOF) or the Inter Frame Separation (IFS). It codes
and decodes any VAN data according to the Enhanced-Manchester code.
Bit Stream Processor (BSP) :
The BSP is a sequencer that controls the data stream between the IML (parallel data) and the VAN
bus line (serial data). It controls the BTL with regard to transmission, reception, arbitration and
generates error signals according to the VAN bus specifications.
Error Management Logic (EML) :
The EML is responsible for the fault confinement of the VAN protocol. It also sets and resets the
error flag bits and interrupts and changes the error status bits in the Status register.
Any error on the VAN bus line generates an interrupt if enabled by the application software (INT0
interrupt).
233
µPD1615, µPD16F15, µPD1616
Cyclic Redundancy Check (CRC) generator and checker :
The CRC generator consists of a 15-bit shift register and the logic required to generate the
checksum of the bit-stream. It informs the EML about the result of a receiver checksum.
The checksum is generated by the polynomial :
g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1
This logic performs the calculation of the CRC in transmission and in reception.
Receive/Transmit (RX/TX) register :
The Rx/Tx register is a 8-bit shift register controlled by the VAN Core. It is loaded or read by the
IML which holds the data to be transmitted or the data that was received.
Bit Time Logic (BTL) :
The BTL is responsible for counting the bits and the bytes. It also resynchronise the bits according
to VAN specifications.
Diagnosis Logic and Output Driver:
The Diagnosis Logic is responsible to hold the communication whenever one of the two wires of
the VAN bus line (DATA and /DATA) is short-circuited to ground or battery or is opened-circuit. It
decides on which line Rx0VAN, Rx1VAN or Rx2VAN, the VAN UART will continue to communicate.
Operating on the RXD0 line is named «nominal or differential mode» because there is no default
neither on the DATA line nor on the /DATA one.
Operating on the Rx1VAN or Rx2VAN line is named «degraded mode» since there is a default on
DATA or /DATA and it is no longer a differential communication.
Assuming the Diagnosis Logic decides to put the device in the «degraded mode», it can also put it
back to the «differential mode» when the problem on the DATA or /DATA has disapeared.
VAN UART Registers :
The register block consists of 21 registers which are described in more details in the following
paragraphs.
234
µPD1615, µPD16F15, µPD1616
15.3 Functional description
15.3.1 Overview of the VAN UART Registers
Figure 15-4: Overview of the VAN UART Registers
RK0_REG
IFR_REG
F800H
F801H
TX6
TX5
TX4
TX3
TX2
TX1
TX0
IFR7
0
IFR6
IFR5
IFR4
IFR3
IFR2
IFR1
IFR0
STOP-
TR
ACK-
REQ
LAST-
BYTE
SOFT-
RESET
CTRK_REG
F802H
F803H
F804H
0
0
0
0
0
CONFIG_REG
DIAG_CTRL_REG
0
IT12
CK0
RANK
IFR
MSK1
DIA1
MSK0
DIA0
DIAG-
TOP
ENAB_
EMECB
CK3
CK2
CK1
MSK1_MSG_REG
MSK1_LSG_REG
AC1_MSG_REG
AC1_LSG_REG
MSK2_MSG_REG
MSK2_LSG_REG
AC2_MSG_REG
AC2_LSG_REG
AC3_MSG_REG
AC3_LSG_REG
AC4_MSG_REG
AC4_LSG_REG
F805H
F806H
F807H
F808H
F809H
F80AH
F80BH
F80CH
F80DH
F80EH
F80FH
F810H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LA_
RESP
STAT_REG
F811H
0
EOM
LA
ACK
ERR2
ERR1
ERR0
REC_REG
F812H
F813H
F820H
RX7
0
RX6
0
RX5
0
RX4
0
RX3
0
RX2
SC
RX1
SB
RX0
SA
0
DIAG_STAT_REG
INT_ENABLE_REG
GIE
RDAE
TBEE
FTE
FRE
LAE
EOME
235
µPD1615, µPD16F15, µPD1616
15.3.2 Autonomous mode functions
15.3.2.1 Autonomous mode features
The user sets the VAN UART in autonomous mode by setting the RANK bit to 0. The transmission
clock is the quartz clock divided by the prescaler chosen by the user in the DIAG_CTRL_REG
register.
For example:
To be able to detect the frames, whose speed is 250 kTS/s, the minimum frequency of this quartz
clock must be 4 MHz.
The component executes all VAN frame types:
* The transmission of data transmit (write) or data request (read) frames (SOF included or rank 0)
at any speed up to 500 kTS/s (with an 8 MHz quartz) depending on the division ratio chosen in the
DIAG_CTRL_REG register.
* The reception of data frames at the same speeds depending on the programming of the
prescaler.
* The transmission of data transmit or data request frames from the address field (synchronisation
on the start bit or rank 1) at any speed depending on the programming of the prescaler.
* The transmission of in frame responses (or rank 16) at any speed depending on the programming
of the prescaler.
15.3.2.2 Programming of the prescaler in Rank 0 transmission (SOF included)
Programming of the prescaler permits Rank 0 frames to be transmitted at different speeds without
changing the quartz clock.
For example:
W hen an 8 MHz quartz clock supplies the UART, it is capable of sweeping the range 62,5 kTS/s
to 500 kTS/s in rank 0 transmission.
The prescaler is chosen using the DIAG_CTRL_REG register with the 4 bits CK3, CK2, CK1 and
CK0. The 2 least significant bits CK1 and CK0 are used to program a divider by 1, 2, 3 or 5 whilst
the 2 other bits are used to program a divider to a power of 2.
Figure 15-5: Prescaler in Rank 0 transmission
CPU's Clock
CK0
.
1, 2, 3, 5
CK2
—
.
CK1
.
—
.
2
.
CK3
—
.
2
CKCOR
236
µPD1615, µPD16F15, µPD1616
Table 15-1: Network Speeds as a Function of the Quartz Clock and the Chosen Division Ratio
Quartz (MHz)
1
2
3
4
5
6
8
Div
Ratio
Network speed (KTS)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
62.5
125
250
125
500
250
31.25
62.5
3
62.5
31.25
31.25
15.625
125
5
62.5
31.25
31.25
15.625
2
31.25
62.5
125
250
125
4
15.625
31.25
62.5
6
62.5
62.5
31.25
10
2
31.25
62.5
125
250
125
4
15.625
31.25
62.5
6
10
4
15.625
7.81
31.25
62.5
125
8
15.625
31.25
62.5
12
20
15.3.2.3 Transmission features in autonomous mode
A transmit request is triggered by writing in the rank0 transmit register RK0_REG when the compo-
nent is in receive or in idle (typically after an EOM interrupt).
A rank 0 transmission start by the transmission of the SOF symbol following the detection of the
EOF symbol (8 recessive TS) followed by the IFS symbol (4 recessive TS).
If these 12 recessive TS could not be detected on the network, the component then synchronises
itself on the start bit seen on the bus. The transmission request is satisfied but transformed into
rank 1 transmission.
In the autonomous mode, the component performs also the in frame response (IFR). To do this,
the bit IFR must be set to 1 in the CTRL_REG register. In addition, the component must be in
reception on the R/W bit of the command field of the VAN frame (please note that this receive
state can be due to a lost of arbitration during the first or the second identifier byte).
The VAN UART compares the received identifier with one or more identifiers located in the MSK
(mask) and AC (Acceptance Code) registers and generates or not a received byte interrupt. Then,
the microcontroller accepts or refuses to respond in the frame (whether this identifier corresponds
or not to an in frame response).
Writing of the first byte of the response in the IFR transmit register IFR_REG shows an
acceptation.
Not writing shows a refusal.
237
µPD1615, µPD16F15, µPD1616
15.3.3 Synchronous mode functions
15.3.3.1 Synchronous mode features
The user sets the VAN UART in synchronous mode by setting the RANK bit to 1 in the control
register CTRL_REG. The transmission clock is the quartz clock divided by the prescaler chosen
by the user in the DIAG_CTRL_REG register.
For example:
To be able to detect the frames, whose speed is 250 kTS/s, the minimum frequency of this quartz
clock must be 4 MHz.
The component can no longer transmit rank 0 frames. However, it can receive data frames. It can
transmit rank 1 frames (data frames and read frames synchronised on the start bit) and in frame
responses. The range of speeds depends on the frequency of the quartz clock; at 8MHz, the range
spreads from 62,5 kTS/s to 500 kTS/s.
15.3.3.2 Transmission features in synchronous mode
For rank 1 transmission, the transmit request is still triggered by writing in the Rank0 transmit
register RK0_REG when the component is in receive or in idle (typically after an EOM interrupt).
The transmission is triggered after the detection of a start bit. The transmission characteristic of
an in frame response is identical to that mentioned in autonomous mode.
15.3.4 Handling of a collision
The UART automatically goes into reception during a lost arbitration after collision detection. This
lost arbitration may be signalled either by interrupt, if it is enabled by the user (LAE bit of the
INT_ENABLE_REG register), or by reading the LA bit in the status register STAT_REG.
15.3.5 Executing the CRC
15.3.5.1 CRC transmission
The transmission of the CRC is possible thanks to a CRC module integrated in the UART.
It is performed by the following way:
The LAST-BYTE bit in the CTRL_REG register is set when there are no more bytes to transmit.
The UART then automatically completes the frame by the two CRC bytes followed by the EOD
symbol. In the case of a read frame, the LAST-BYTE bit should be set after the second identifier
byte because if the requested node does not send its data, the UART will complete the frame by
sending immediately the 2 CRC bytes.
Therefore, such a frame does not contain any data. This case is described in detail further.
238
µPD1615, µPD16F15, µPD1616
15.3.5.2 Reception of the CRC
For high-speed applications, the UART incorporates a CRC module, which compares the received
CRC with the calculated CRC. This comparison is carried out in transmission and in reception,
giving place, in the latter case, to the transmission of a possible acknowledge.
15.3.6 Control of the acknowledge bit
In reception, if the EOD symbol has been detected and if the CRC is correct, then if the ACK-REQ
bit is set to 1 in the CTRL_REG register before the end of the EOD field, a positive acknowledge
is transmitted. Otherwise, the UART stays in reception, which is equivalent to a negative acknowl-
edge.
The acknowledge bit is decoded in transmission as in reception and its value is indicated in the
STAT_REG register by the ACK bit. The microcontroller compares the value of the ACK bit with
the RAK bit received (and memorised) in the command field of the VAN frame.
15.3.7 Error control and Interrupt control
15.3.7.1 Error control
3 bits ERR2, ERR1 and ERR0 encode any error in transmission or in reception in the status
register STAT_REG.
Table 15-2: Error Table
ERR2
ERR1
ERR0
Type of error
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
no error : initialisation
Physical violation
Not used
Code Violation in reception
Not used
CRC error in reception
Format error ( ACK )
Transmission or Reception
lock up
1
1
1
Information on the error table:
When the code violation received is 00 on the TS 8 and 9 of a byte, the error signalled is a CRC
error in reception as it is not possible to distinguish this violation from the EOD symbol. Any other
code violation received is signalled by a code violation in reception.
239
µPD1615, µPD16F15, µPD1616
15.3.7.2 Interrupt control
An error is signalled by an interrupt if the user defines it. Any interrupt that would have been
generated after the detection of an error is deleted.
The interrupt sources are listed below:
LA_RESP
EOM
LA
:
:
:
:
:
Lost arbitration in the RTR bit (Response)
End of message
Lost arbitration
FT
Failed transmit (refer to ERR0, ERR1, ERR2 for status)
Failed receive (refer to ERR0, ERR1, ERR2 for status)
FR
These sources generate the INT0 interrupt.
TBE
RDA
:
:
Transmit buffer empty
This source generates the INT1 interrupt.
Received data available
This source generates the INT2 interrupt.
- EOM interrupt
The EOM interrupt appears at the end of the acknowledgement field if no error has occurred in the
frame. Otherwise, it appears as soon as an error is detected. This permits, in particular to detect
errors that could occur in the identification field and to synchronise on it.
This interrupt is generated on INT0.
It can be disabled in the INT_ENABLE_REG register by the EOME bit.
It can also be masked by VEMK bit in MKOL register.
- LA interrupt
The LA interrupt appears at the end of the byte where the collision occurred even if the UART has
automatically switched to the reception mode in the current Time Slot.
This interrupt is also generated on INT0.
This interrupt is signalled in the REG-STAT register by the LA bit.
It can be disabled in the INT_ENABLE_REG register by the LAE bit.
- LA_RESP interrupt
The LA_RESP interrupt appears when the UART performs a read frame and when the collision
occurred on the RTR bit. That means that response is in progress. The UART has automatically
switched to the reception mode to receive that response.
This interrupt is also generated on the INT0 pin.
This interrupt is signalled in the REG-STAT register by the LA_RESP bit.
It can be also disabled in the INT_ENABLE_REG register by the LAE bit.
- TBE interrupt
The TBE interrupt appears at the start of the 9th TS of a new byte before the old RK0_REG or
IFR_REG register has been loaded in the transmit/receive shift register.
This interrupt is generated on INT1.
It can be disabled in the INT_ENABLE_REG register by the TBEE bit.
It can also be masked by VTMK bit in MKOL register.
240
µPD1615, µPD16F15, µPD1616
It signifies that a byte must be loaded into the RK0_REG or IFR_REG register, but can be ignored
if the microcontroller has no more bytes to transmit. In this case, it sets the LAST-BYTE bit in the
control register CTRL_REG for the transmission of the CRC.
- RDA interrupt
The RDA interrupt appears at the start of the 9th TS of the current byte before the RECEP_REG
register has been loaded by the transmit/receive shift register.
This interrupt is generated on INT2.
It can be disabled in the INT_ENABLE_REG register by the bit RDAE.
It can also be masked by VRMK bit in MKOL register.
It signifies that the byte contained in the RECEP_REG register must be read.
- Case of an in frame response:
The user can choose to perform or not the in frame response using the IFR bit in the control
register CTRL_REG.
If IFR = 0, the component cannot perform the in frame response.
If IFR = 1, the component is able to respond in the frame under conditions (see the
transmission characteristics of rank 16). The interrupts are generated following two
manners:
If IT12 = 0, the interrupts are generated byte after byte. The comparison of the identifier field is
made by UART.
If IT12 = 1, the interrupts are generated byte after byte except during the second byte of the
identifier where one RDA interrupt appears at the end of the 12th bit of the VAN identi
fier field. This allows the microcontroller to make the comparison itself. In this case,
the UART supplies the byte for the address comparison and helps the microcontroller
to search for the byte to be transmitted in the in frame response…
Table 15-3: Frame Responce
0 0 0 0
4 bits
IDEN2
4 bits
…after the RDA interrupt at the 12th bit, so as to be able to add to an address to
point on the table of bytes to be transmitted without needing to mask the 4 most
significant bits of this byte.
- FT interrupt
The FT interrupt appears after a physical violation, a format error (acknowledge error in transmis-
sion) or a transmission lock-up (when there is no write access to the transmission register or to
the control register between the transmission of two consecutive bytes). In case of a transmission
lock-up, the UART does not complete the frame with the two bytes of CRC and stops just after the
last byte loaded.
The bits ERR2, ERR1 and ERR0 signal the error in the status register STAT_REG.
It is generated on INT0.
241
µPD1615, µPD16F15, µPD1616
It can be disabled in the INT_ENABLE_REG register by the FTE bit.
- FR interrupt
The FR interrupt appears after a code violation, a CRC error or a format error (acknowledgement
error in reception) or a reception lock-up (when there is no read access to the reception register
between the reception of two consecutive bytes). In case of a reception lock-up, the UART does
not receive the rest of the frame and stops just after the last byte.
The bits ERR2, ERR1 and ERR0 signal the error in the status register STAT_REG.
It is generated on INT0.
It can be disabled in the INT_ENABLE_REG register by the FRE bit.
242
µPD1615, µPD16F15, µPD1616
15.4 VAN UART Registers
The VAN UART consists of the following registers.
Table 15-4: VAN UART Registers
Manipulatable bit unit
1bit 16bit
Address
Register NAME
SYMBOL
After Reset
R/W
8bit
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
F800H
F801H
F802H
F803H
F804H
F805H
F806H
F807H
F808H
F809H
F80AH
F80BH
F80CH
F80DH
F80EH
F80FH
F810H
F811H
F812H
F813H
F820H
Rank 0 Register
RK0_REG
IFR_REG
FFH
FFH
00H
08H
17H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
08H
FFH
00H
00H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
In Frame Transmit Register
Control Register
CTRL_REG
Configuration Register
Diagnosis Control Register
Mask1 Register
CONF_REG
DIAG_CTRL_REG
MSK1_MSB_REG
MSK1_LSB_REG
AC1_MSB_REG
AC1_LSB_REG
MSK2_MSB_REG
MSK2_LSB_REG
AC2_MSB_REG
AC2_LSB_REG
AC3_MSB_REG
AC3_LSB_REG
AC4_MSB_REG
AC4_LSB_REG
STAT_REG
Mask1 Register
Acceptance Code 1
Acceptance Code 1
Mask2 Register
Mask2 Register
Acceptance Code
Acceptance Code
Acceptance Code
Acceptance Code
Acceptance Code
Acceptance Code
Status Register
Receive Register
REC_REG
R
Diagnosis Status Register
Interrupt Enable Register
DIAG_STAT_REG
INT_ENABLE_REG
R
R/W
243
µPD1615, µPD16F15, µPD1616
15.4.1 Rank0 Transmission Register (RK0_REG)
The rank0 transmission register is loaded by the microcontroller to trigger a transmit request.
RK0_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input set this register to FFH.
Figure 15-6: Rank0 Transmission Register Format
Symbol
7
6
5
4
3
2
1
0
Address
F800H
After Reset
FFH
R/W
R/W
RK0_REG
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
It is also loaded each time the INT1 interrupt is generated, except if the microcontroller has no
more bytes to transmit. In this case, it sets, instead, the LAST-BYTE bit in the control register
CTRL_REG.
For a standard transmission (rank0 or rank1), the microcontroller has up to one byte duration to
load this register.
For the in frame response, it has up to one byte duration if the IT12 bit is set to 0 or up to only 4
TS if the IT12 bit is set to 1.
The loading limit is 14/16 of the last TS of the byte. If this limit is no met, the component will
detect a lock up error and will signal it.
The transmission is done MSB first (TX7 is transmitted first).
244
µPD1615, µPD16F15, µPD1616
15.4.2 In Frame Response Register (IFR_REG)
The IFR Transmit Register is written when the user wish to transmit an In Frame Response (IFR).
IFR_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input set this register to FFH.
Figure 15-7: Frame Responce Register Format
Symbol
7
6
5
4
3
2
1
0
Address
F801H
After Reset
FFH
R/W
R/W
IFR_REG
IFR7
IFR6
IFR5
IFR4
IFR3
IFR2
IFR1
IFR0
The VAN UART will receive the identification field (12 bits), compares it with the Acceptance
Codes and start the transmission by the 16th bit of the frame. This kind of transmission is named
«rank16 frame».
No IFR is transmitted if this register is not written.
The application software should only write data bytes in this register (28 maximum) and not ad-
dress bytes. These datas correspond to the datas to be answered in the IFR. This software must
specify the last byte of data in the CTRL_REG register.
The device will transmit an In Frame Response only if the identification field that was received on
the VAN bus matches with one of the Acceptance Codes.
Every byte transmitted generates a INT1 interrupt corresponding to the TBE status (Transmit
Buffer Empty) meaning that the IFR_REG register was loaded in the shift register. A writing in this
register resets the internal TBE flag.
- Case of lost arbitration during the identification field of a rank0 frame
The following picture shows an arbitration during the identification field of a rank0 frame. That
means the VAN UART has first tried to transmit a rank0 frame. Nevertherless , at the same
moment, another VAN node is also communicating with a higher priority identification field. The
VAN UART looses the arbitration and goes into the receive mode.
It can happen that this frame was also a request frame for the VAN UART.
In order to handle these cases, the application software has to write in both registers (RK0 and
IFR) to prevent from this kind of arbitration. The VAN UART will then select automatically the right
register. If a lost arbitration has occured, the IFR_REG is selected otherwise the RK0_REG is
chosen.
245
µPD1615, µPD16F15, µPD1616
Figure 15-8: Frame Responce Register Function
5D
5D
A
DAT=33
RTR=0
VAN UART
8F
Other
In Frame
Responce
Lost
Arbitration
First Byte
Received
LA
INT0
INT1
INT2
WRITE RK0 and IFR
Registers with first Data Byte
246
µPD1615, µPD16F15, µPD1616
15.4.3 Control Register (CTRL_REG)
The Control Register is used to control the VAN UART during the transmisision or to initiate a
RESET.
CTRL_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input set this register to 00H.
Figure 15-9: Control Register Format
After
Symbol
7
6
5
4
3
2
1
0
Address
R/W
R/W
Reset
STOP-
TR
ACK-
REQ
LAST-
BYTE
SOFT-
RESET
CTRL_REG
0
0
0
0
F802H
00H
Note:
The bits of this register are “SET ONLY type “ bits. They are set by the application software
and resetted automatically by the VAN UART. Writing 0 in these bits will have no effect.
STOP-TR: Stop Transmit
Table 15-5: Stop Transmit
STOP-TR
Stop Transmit
0
1
No influence
Stop the transmission in progress
It can be used in any type of transmission.
ACK-REQ: Acknowledge Request
Table 15-6: Acknowledge Request
ACK-REQ
Acknowledge Request
No influence
0
1
Transmit request of an acknowledge bit
The microcontroller decodes the value of the RAK bit (bit 2 of the 2nd byte of the frame). Accord-
ing to this value, it will choose to set the ACK-REQ bit in the control register CTRL-REG or not.
Note that ACK-REQ occupies the same position as RAK in the byte.
247
µPD1615, µPD16F15, µPD1616
Figure 15-10: Control Register Block Diagram
Byte 2 of the Frame
memorised
in the microcontroller
RTR
IDEN3
IDEN2
IDEN0 EXT RAK R/W
IDEN1
CTRL_REG
of the UART
SOFT
RESET
REQ BYTE
STOP ACK LAST
TR
Therefore, a mask with 04h of the 2nd byte needs to be made and written in the control register.
Figure 15-11: Control Register Function
6
7
5
8
9
CRC2
ACK
EOD
Last Limit
The last limit for setting the ACK-REQ is 13/16 of the 2nd TS of the EOD symbol.
Following the results of the frame (identifier recognised and correct CRC), the acknowledge bit
may be transmitted.
LAST-BYTE:
Table 15-7: Last-Byte
LAST-BYTE
0
Last transmission Byte
No influence
Sign to the VAN UART that the current byte is
the last one
1
Figure 15-12: Last-Byte
13/16
2
1
4
5
3
6
8
0
7
0
9
Data or Iden
Last Limit
CRC
248
µPD1615, µPD16F15, µPD1616
The UART places the 2 CRC bytes after it. This may occur during a write frame or a read frame:
in the case of a write frame, the last byte of data is signalled after the last data is transmitted. In
the case of a read frame, the last byte is signalled after loading the 2nd identifier. The LAST-BYTE
bit must be activated, as, if the response is missing, the CRC will be automatically set by the
UART following the identifier n°2.
SOFT-RESET: Software reset
Table 15-8: Software Reset
SOFT-RESET
0
Soft Reset
No influence
Software reset with the initialisation of the VAN
UART
1
This bit should be used if a major problem is detected during the operation of the VAN UART, or if
it is incorrectly used. The result is the same as a hardware reset. The VAN UART must be re-
configured.
249
µPD1615, µPD16F15, µPD1616
15.4.4 Configuration Register (CONF_REG)
The Configuration Register is used to configure the interrupt generation, the UART mode and
response and the mask function.
CONF_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input set this register to 08H.
Figure 15-13: Configuration Register (CONF_REG) Format
Symbol
7
0
6
0
5
0
4
3
2
1
0
Address
F803H
After Reset
08H
R/W
R/W
CONF_REG
IT12
RANK
IFR
MSK1
MSK0
IT12: Enable / Disable interrupt on the 12th bit of the identifier field.
Table 15-9: Enable / Disable interrupt on the 12th bit of the identifier field
IT12
0
Interrupt on the 12th bit of the identifier field
Disables the interrupt on the 12th bit of the identifier
field. The UART only supplies «byte» interrupts
during a frame.
Enables the interrupt on the 12th bit of the identifier
field. This allows the microcontroler to receive the
whole identifier and to compare it if necessary.
1
Case where IT12 = 0
Figure 15-14: Case where IT12 = 0
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
IDEN2 + COM
IDEN1
SOF
INT2
Reception
IFR
INT1
"Byte" Interrupts
250
µPD1615, µPD16F15, µPD1616
Case where IT12 = 1
Figure 15-15: Case where IT12 = 1
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
IDEN2 + COM
IDEN1
SOF
INT2
Reception
IFR
INT1
"Byte" Interrupts
"Nibble" interrupt
to the third TS (i.e. to the 1st TS
of the Manchester bit) to gain
one TS at the address comparison level.
The UART supplies 0000IDEN2 to make
the responce search easier
RANK: Rank 0 / Rank 1 mode
Table 15-10: Rank 0 / Rank 1 mode
RANK
VAN UART Mode Selection
0
1
VAN UART in autonomous mode
VAN UART in synchronous mode
In autonomous mode, a quartz clock is compulsory for the generation of the SOF symbol. The
precision needed is +/-1%.
Remark:
On initialisation, the UART is set in synchronous mode and disables
the in frame response.
IFR: Enable / Disable In Frame Response
Table 15-11: Enable / Disable In Frame Response
IFR
0
In Frame Response
Disables the in frame response
Enables the in frame response
1
251
µPD1615, µPD16F15, µPD1616
MSK1, MSK0: Mask Enable / Disable
Table 15-12: Mask Enable / Disable
Function
MSK1
MSK0
0
0
1
1
0
1
0
1
Masks 1 and 2 activated (all identifiers filtered)
Mask1 inhibited
Mask2 inhibited
Masks 1 and 2 inhibited (all identifiers accepted)
MSK1 and MSK0 combinations allow enabling or disabling all or part of the mask mechanism
applied on the identification field described further on.
252
µPD1615, µPD16F15, µPD1616
15.4.5 Diagnosis Control Register (DIAG_CTRL_REG)
The Diagnosis Control Register allows to configure the bus speed, the communication mode and
diagnostic functions.
DIAG_CTRL_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input set this register to 17H.
Figure 15-16:
Diagnosis Control Register (DIAG_CTRL_REG) Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F804H
R/W
R/W
DIAG_CT
RL_REG
DIAG- ENAB_E
TOP MECB
CK3
CK2
CK1
CK0
DIA1 DIA0
17H
CK3, CK2, CK1 and CK0: Prescaler.
The prescaler is used to fix the division ratio between the quartz clock and the speed of the bus.
This prescaler is defined in 4 bits.
The least significant bits CK3 and CK2 are used to pre-divide by a ratio of 1,2,3 or 5. So, the
UART can operate with quartz frequencies other than to the powers of 2.
This pre-divider by 3 or 5 permits an operation at “round” speeds in terms of Kbits/s or KTS/s with
“non binary” frequencies such as 3, 5, 6 MHz.
Figure 15-17:
Prescaler Block Diagram
CPU's CK
CK0
CK1
.
1, 2, 3, 5
CK2
—
.
.
—
.
2
.
CK3
—
.
2
CKCOR
253
µPD1615, µPD16F15, µPD1616
Table 15-13: Prescaler - Network Speeds as a Function of the Quartz Clock and the Chosen
Division Ratio
Quartz (MHz)
1
2
3
4
5
6
8
Div
Ratio
Network speed (KTS)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
62.5
125
250
125
500
250
31.25
62.5
3
62.5
31.25
31.25
15.625
125
5
62.5
31.25
31.25
15.625
2
31.25
62.5
125
250
125
4
15.625
31.25
62.5
6
62.5
62.5
31.25
10
2
31.25
62.5
125
250
125
4
15.625
31.25
62.5
6
10
4
15.625
7.81
31.25
62.5
125
8
15.625
31.25
62.5
12
20
DIAG-TOP: Synchronous diagnosis clock.
Table 15-14: Synchronous Diagnosis Clock
DIAG-TOP
Synchronous diagnosis clock selection
No pulse on the internal DIAG-CLOCK signal
Pulse on the internal DIAG-CLOCK signal
0
1
The pulse on the internal DIAG-CLOCK signal is used for the synchronous diagnosis clock (see
Information on the characteristics of the clock DIAG-CLOCK in the paragraph describing the diag-
nosis function).
EN-EMECB: Enable the transmit diagnosis.
Table 15-15: Enable the Transmit Diagnosis
EN-EMECB
Transmit diagnostic
0
1
Enables the transmission diagnosis
Disables the transmission diagnosis
Due to the diagnosis set-up problems in transmission, this bit permits this part of the diagnosis to
be disabled or enabled.
254
µPD1615, µPD16F15, µPD1616
DIA1, DIA0: Choice of communication mode
Table 15-16: Choice of Communication Mode
DIA1
DIA0
Communication mode
0
0
1
1
0
1
0
1
Forced operation on RXD0
Forced operation on RXD1
Forced operation on RXD2
Automatic operation
The 2 least significant bits DIA1 and DIA0 allow the user to choose the communication mode.
255
µPD1615, µPD16F15, µPD1616
15.4.6 Mask1 registers (MSK1_MSB_REG, MSK1_LSB_REG)
These 2 registers allow to compare the 12 bits of the VAN identification field plus the EXT bit.
MSK1_MSB_REG, MSK1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets these registers to 00H.
Figure 15-18-1:
Mask1 register MSK1_MSB_REG Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F805H
R/W
R/W
MSK_MSB_REG
B11
B10
B9
B8
B7
B6
B5
B4
00H
Figure 15-18-2:
Mask1 register MSK1_LSB_REG Format
After
Reset
Symbol
7
6
5
4
3
2
0
1
0
0
0
Address
F806H
R/W
R/W
MSK_LSB_REG
B3
B2
B1
B0
Ext
00H
Writing «0» enables the comparison of the corresponding bit.
Writing «1» disables the comparison of the corresponding bit that becomes a «don’t care bit».
256
µPD1615, µPD16F15, µPD1616
15.4.7 Acceptance Code 1 registers (AC1_MSB_REG, AC1_LSB_REG)
These 2 registers allow to choose the code acceptance which is the value of the identification field
that the user wish to match with. They work together with the MSK1 registers.
AC1_MSB_REG, AC1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets these registers to 00H.
Figure 15-19-1: Acceptance Code 1 register AC1_MSB_REG
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F807H
R/W
R/W
AC1_MSB_REG
00H
Figure 15-19-2: Acceptance Code 1 register AC1_LSB_REG
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F808H
R/W
R/W
AC1_LSB_REG
00H
The behaviour of the receive interrupt (INT2) according this comparison is described in the para-
graph «Receive Interrupt Behaviour».
257
µPD1615, µPD16F15, µPD1616
15.4.8 Mask2 registers (MSK2_MSB_REG, MSK2_LSB_REG)
These 2 registers allow to compare the 12 bits of the VAN identification field plus the EXT bit.
MSK1_MSB_REG, MSK1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets these registers to 00H.
Figure 15-20-1:
Mask2 register MSK2_MSB_REG Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F809H
R/W
R/W
MSK2_MSB
_REG
B11
B10
B9
B8
B7
B6
B5
B4
00H
Figure 15-20-2:
Mask2 register MSK2_LSB_REG Format
After
Reset
Symbol
7
6
5
4
3
2
0
1
0
0
0
Address
F80AH
R/W
R/W
MSK2_LSB
_REG
B3
B2
B1
B0
Ext
00H
Writing «0» enables the comparison of the corresponding bit.
Writing «1» disables the comparison of the corresponding bit that becomes a «don’t care bit».
258
µPD1615, µPD16F15, µPD1616
15.4.9 Acceptance Code 2, 3 and 4 Registers (AC2_MSB_REG, AC2_LSB_REG,
AC3_MSB_REG, AC3_LSB_REG, AC4_MSB_REG, AC4_LSB_REG)
These 6 registers allow to choose the code acceptance which is the value of the identification field
that the user wish to match with. They work together with the MSK2 registers.
AC2_MSB_REG, AC2_LSB_REG, AC3_MSB_REG, AC3_LSB_REG, AC4_MSB_REG,
AC4_LSB_REG are set with a 1-bit or 8-bit manipulation instruction.
RESET input sets these registers to 00H.
Figure 15-21:
Acceptance Code 2, 3 and 4 Registers Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F80BH
R/W
R/W
AC2_MSB_REG B11 B10
B9
B8
B7
B6
B5
B4
00H
After
Reset
Symbol
7
6
5
4
3
2
0
1
0
0
0
Address
F80CH
R/W
R/W
AC2_LSB_REG
B3
B2
B1
B0
Ext
00H
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F80DH
R/W
R/W
AC3_MSB_REG B11 B10
B9
B8
B7
B6
B5
B4
00H
After
Reset
Symbol
7
6
5
4
3
2
0
1
0
0
0
Address
F80EH
R/W
R/W
AC3_LSB_REG
B3
B2
B1
B0
Ext
00H
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F80FH
R/W
R/W
AC4_MSB_REG B11 B10
B9
B8
B7
B6
B5
B4
00H
After
Reset
Symbol
7
6
5
4
3
2
0
1
0
0
0
Address
F810H
R/W
R/W
AC4_LSB_REG
B3
B2
B1
B0
Ext
00H
The behaviour of the receive interrupt (INT2) according this comparison is described in the
paragraph «Receive Interrupt Behaviour».
259
µPD1615, µPD16F15, µPD1616
15.4.10 Status Register (STAT_REG)
This register allows to control a lost arbitration, the end of message, the acknowledge and the
error type during a transmission or a reception.
STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction.
RESET input sets this register to 08H.
Figure 15-22:
Status Register (STAT_REG) Format
After
Reset
Symbol
7
0
6
5
4
3
2
1
0
Address
F811H
R/W
R
LA_R
ESP
ERR
2
ERR
1
ERR
0
STAT_REG
EOM
LA
ACK
08H
LA_RESP, LA:
Table 15-17: LA_RESP, LA
LA_RESP
0
Lost Arbitration information
Arbitration is not lost during RTR bit
Arbitration lost during the RTR bit of the command
field. It is considered as a lost arbitration due to a
response.
1
LA
0
Lost Arbitration information
Arbitration is not lost
Arbitration lost not in the RTR bit of the command
field
1
The UART automatically goes into reception after loosing arbitration during a collision.
These 2 kinds of collision may be signalled either by interrupt (INT0), if enabled by the user (LAE
bit of the INT_ENABLE_REG register), or by reading these 2 bits in the status register STAT_REG.
It is worthwhile noting that reading the status register causes all the bits to be reset to 0 (except
ACK, which is set to 1).
EOM:
Table 15-18: EOM
EOM
0
End of Message
End of Message as not given under a.) or b.).
a.) If the frame is correct, the EOM flag is
set after the EOD symbol and the
ERR2, ERR1, ERR0 bits show 000.
b.) If the frame is not correct, the EOM flag
is also set when the error is
1
detected and the ERR2, ERR1, ERR0
bits show this error.
260
µPD1615, µPD16F15, µPD1616
The EOM flag is set when a VAN frame is transmitted or received correctly or incorrectly.
These 2 kinds of EOM may be signalled either by interrupt (INT0), if enabled by the user (EOME
bit of the INT_ENABLE_REG register), or by reading the EOM bit in the status register
STAT_REG.
During an EOM interrupt (INT0), the microcontroller can read:
- LA:
Signals a possible collision with lost arbitration in the current frame. The application
software should memorise this information to retry the transmission of this frame.
- LA_RESP:Indicates a lost arbitration during the RTR bit. This lost arbitration is due to a
response.
- ACK:
Indicates the value of the acknowledge bit:
0: positive
1: no acknowledge
The ACK bit is described in the paragraph “Control of the acknowledge bit “.
Signals the type of transmit or receive error.
- Err:
The ERRx bits are described in the paragraph “Error control” where the bit combina
tion are given.
261
µPD1615, µPD16F15, µPD1616
15.4.11 Receive register (REC_REG)
This register is used as receive register of a reception.
STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction.
RESET input sets this register to FFH.
Figure 15-23: Receive register (REC_REG) Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
Address
F812H
R/W
R
REC_REG RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
FFH
The receive register is read by the microcontroller each time the RDA interrupt (INT2) is generated
by the UART indicating that a new byte is received.
The reading limit of the receive register is 13/16 of the last TS of the byte or 13/16 of the third TS
of the second byte of identifier in case of IT12 is set. If this limit is not met, the component will
detect an overrun and will signal a lock up error.
The reception is done MSB first (RX7 is received first).
Receive interrupt behaviour :
The RDA receive interrupt (INT2) is generated only if the received VAN identifier matches with one
of the identifiers written in the ACx registers. The AC1 registers work with the MSK1 mask regis-
ters and the AC2, AC3 and AC4 registers work with the MSK2 mask registers.
Since the VAN identifier is built with 12 bits, it is received over 2 bytes. Three cases can occur :
* The received identifier does not match at all. The VAN UART does not produce any interrupt.
* The first byte matches but not the second one. The VAN UART generates the first receive inter-
rupt (INT2) but since the second identifier byte does not match, the UART will wait for the end of
the current frame to generate the EOM interrupt (INT0).
* The whole received identifier matches. The VAN UART generates all the receive interrups and
the EOM interrupt.
262
µPD1615, µPD16F15, µPD1616
15.4.12 Diagnosis Status Register (DIAG_STAT_REG)
This register is used for the diagnose of the receive lines.
DIAG_STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction.
RESET input sets this register to 00H.
Figure 15-24: Diagnosis Status Register (DIAG_STAT_REG) Format
After
Reset
Symbol
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
F813H
R/W
R
DIAG_STAT
_REG
SC
SB
SA
00H
The bits SA and SB indicate the line chosen by the diagnosis circuit.
Table 15-19: The bits SA and SB
SB
0
SA
0
Line chosen
Differential mode ( Rx0VAN )-- No fault
0
1
DATAB mode ( Rx2VAN ) -- Fault on DATA
DATA mode ( Rx1VAN ) -- Fault on DATAB
Major Error
1
0
1
1
To perform this diagnosis, the circuit needs the synchronous diagnosis clock (SDC).
The synchronous diagnosis circuit is necessary to go back to the nominal mode, which is the
differential mode.
If no fault is detected between two edges of this clock, the circuit goes back to the nominal mode
(line Rx0VAN). This delay of one synchronous diagnosis clock period, is used to solve bad contact
problems (on connectors for example). Thus, it is equal to a few milliseconds or even a few dozen
milliseconds. Anyway, this is very large comparing to the TS clock (duration of TS).
To generate it, the user must set DIAG-TOP to 1 in the diagnosis control register
DIAG_CTRL_REG.
Table 15-20: The bit SC
SC
1
VAN UART comparator comparison
Discrepancy between the 3 comparator Rx0VAN,
Rx1VAN and Rx2VAN during the reception.
No discrepancy between the 3 comparator
Rx0VAN, Rx1VAN and Rx2VAN during the
reception.
0
In normal operation, the SC bit equals 0, the 3 comparators give an identical result.
263
µPD1615, µPD16F15, µPD1616
15.4.13 Interrupt enable register (INT_ENABLE_REG)
This register allows to enable/disable the interrupt sources of the VAN UART.
INT_ENABLE_REG is set with a 1-bit or an 8-bit manipulation instruction.
RESET input sets this register to 00H.
Figure 15-25: Interrupt enable register (INT_ENABLE_REG) Format
After
Reset
Symbol
7
6
5
4
3
2
1
0
0
Address
F820H
R/W
R/W
INT_ENA
BLE_REG
RDA
E
TBE
E
EOM
E
GIE
FTE
FRE
LAE
00H
Table 15-21: Interrupt enable register (INT_ENABLE_REG) (1/2)
GIE: Global Interrupt Enable
GIE
0
Global Interrupt enable
Disables all the interrupt sources
Enables interrupt sources which can be disabled
one by one with the following bits…
1
RDAE: RDA Enable
RDAE
Receive interrupt
0
1
Receive interrupt disabled
Receive interrupt enabled
TBEE: TBE Enable
TBEE
Transmit interrupt
0
1
Transmit interrupt disabled
Transmit interrupt enabled
FTE: FT Enable
FTE
0
1
Fail transmit interrupt
Failed transmit interrupt disabled
Failed transmit interrupt enabled
264
µPD1615, µPD16F15, µPD1616
Table 15-21: Interrupt enable register (INT_ENABLE_REG) (2/2)
This interrupt will coincide with an EOM interrupt, as an error will cause a premature end of
message.
FRE: FR Enable
FRE
Fail receive interrupt
0
1
Failed receive interrupt disabled
Failed receive interrupt enabled
This interrupt will coincide with an EOM interrupt, as an error will cause a premature end of
message.
LAE: LA Enable
LAE
0
1
Lost arbitration interrupt
Lost arbitration interrupt disabled
Lost arbitration interrupt enabled
EOME: EOM Enable
EOME
End of Message interrupt
0
1
End of Message interrupt disabled
End of Message interrupt enabled
This interrupt occurs in the case of an end of message, i.e. after the acknowledge field or during
an error (premature end of message).
265
µPD1615, µPD16F15, µPD1616
15.4.14 VAN clock selection register (UDLCCL)
This SFR register enables the clock suppply to the VAN UART. UDLCCL is set with a 1-bit or an
8-bit manipulation instruction.
RESET input sets this register to 00H.
Figure 15-26: VAN clock selection register (UDLCCL) Format
Addres
s
After
Reset
Symbol
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
UDLCCL UDLCKEN
FF78H
00H
Table 15-22: VAN clock selection register (UDLCCL)
UDLCKEN
VAN UDL clock control
Disable VAN clock supply
Enable VAN clock supply
0
1
Caution : The VAN UART clock is disable at RESET. Application software must enable it in order
to handle VAN frame.
266
µPD1615, µPD16F15, µPD1616
15.5 VAN UART initialisation
1) Enable the clock via UDLCCL SFR register.
2) Configure the component:
a) Choose the UART mode of operation owing to the RANK bit in the configuration register
b) Enable or disable the In Frame Response using the IFR bit in the same register
c) Enable or disable the generation of the IT12 interrupt using the IT12 bit in the same register
d) Enable or disable the identifier filtering mechanism using the MSK1 and MSK0 bits in the
same register
e) Program the MSKx and ACx registers if filtering is enabled.
3) Program the prescaler to choose the network communication speed.
4) Enable the interrupts for the micro and the VAN UART.
267
µPD1615, µPD16F15, µPD1616
[Memo]
268
µPD1615, µPD16F15, µPD1616
Chapter 16 LCD Controller/Driver
16.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver incorporated in the µPD1615 subseries are shown below.
(1) Automatic output of segment signals and common signals is possible by automatic writing of the
display data memory.
(2) Any of five display modes can be selected.
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Any of four frame frequencies can be selected in each display mode.
(4) Maximum of 40 segment signal outputs (S0 to S39); 4 common signal outputs (COM0 to COM3).
The prt function register (PF) has to be set to LCD mode to allow the segment signal output. This
LCD mode can be set bit-wise.
The maximum number of displayable pixels in each display mode is shown in Table 16-1.
Table 16-1: Maximum Number of Display Pixels
Bias
Method
Time
division
Common Signals Used
Maximum Number of Pixels
-
Static
COM0 (COM1, 2, 3)
COM0, COM1
40 (40 segments x 1 common)
80 (40 segments x 2 commons)
2
3
3
4
1/2
COM0 - COM2
COM0 - COM3
120 (40 segments x 3 commons)
160 (40 segments x 4 commons)
1/3
269
µPD1615, µPD16F15, µPD1616
16.2 LCD Controller/Driver Configuration
The LCD controller/driver is composed of the following hardware.
Table 16-2: LCD Controller/Driver Configuration
Item
Configuration
Segment signals : 40
Display outputs
Segment signal input/output port dual function : 40
Common signals : 4 (COM0 to COM3)
LCD display mode register (LCDM)
Control registers
LCD display control register (LCDC)
Figure 16-1: LCD Controller/Driver Block Diagram
Internal bus
Display data memory
LCD display mode register (LCDM)
FA00H
LCD display control
register (LCDC)
FA27H
LCDC1 LCDC2
LDON
LCDM2 LCDM1 LCDM0
LIPS
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
3
LCD clock selector
fLCD
3 2 1 0
selector
3 2 1 0
selector
3 2 1 0
selector
3 2 1 0
selector
... ... ...
... ... ...
... ... ...
Timing controller
... ... ...
... ... ... ... ...
... ... ...
LCD driver voltage controller
Note
Note
Note
Common driver
Note
S24/P97
VLC0
S0/P127... ... ... ... ...S23/P100
... ... ... S39/P80 COM0 COM1 COM2 COM3
V
LC1 VLC2
Note: Segment driver
270
µPD1615, µPD16F15, µPD1616
Figure 16-2: LCD Clock Select Circuit Block Diagram
fx/214
Prescaler
LCD /23
f
f
f
f
LCD/22
LCDCL
LCD /2
LCD
2
LCDC3
LCDC2
LCD display mode register
Internal bus
Remarks: 1. LCDCL : LCD clock
2. fLDC : LCD clock frequency
271
µPD1615, µPD16F15, µPD1616
16.3 LCD Controller/Driver Control Registers
The LCD controller/driver is controlled by the following two registers.
• LCD display mode register (LCDM)
• LCD display control register (LCDC)
(1) LCD display mode register (LCDM)
This register sets display operation enabling/ disabling, the LCD driving power and the LCD
display mode.
LCDM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDM to 00H.
Figure 16-3: LCD Display Mode Register Format
Symbol
LCDM
7
6
5
4
3
2
1
0
Address AfterReset R/W
FFB0H 00H R/W
LCDON
0
0
LIPS
0
LCDM2 LCDM1 LCDM0
LCDON
LCD Display Enable/Disable
Display off
0
1
Display on
LIPS
LCD driving power supply selection
0
1
Does not supply power to LCD
Supplies power to LCD from VDD pin
Selects display mode of LCD controller/driver
LCDM2 LCDM1 LCDM0
Time division
Bias mode
1/3
0
0
0
0
1
0
0
1
0
1
0
4
3
2
3
0
1/3
1
1/2
1
1/2
0
Static display mode
Other than above
Setting prohibited
272
µPD1615, µPD16F15, µPD1616
Table 16-3: Frame Frequencies (Hz)
Frame frequency (Hz)
LCDC3
LCDC2
fx=4.0 MHz
fx=8.0 MHz
Static
244
122
61
1/2
1/3
1/4
61
Static
488
244
122
61
1/2
1/3
162.8
81.4
40.7
20.3
1/4
122
61
0
0
1
1
0
1
0
1
122
61
81.4
40.7
20.3
10.2
244
122
61
30.5
15.3
7.6
30.5
15.3
30.5
15.3
30.5
30.5
Remark:
1.Figures in parentheses apply to operation with fx = 4.0 MHz or fx = 8.0 MHz.
273
µPD1615, µPD16F15, µPD1616
(2) LCD display clock control register (LCDC)
This register sets the LCD clock.
LCDC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC to 00H.
Figure 16-4: LCD Display Clock Control Register Format
Symbol
LCDC
7
0
6
0
5
0
4
0
3
2
1
0
0
0
Address AfterReset R/W
FFB2H 00H R/W
LCDC3 LCDC2
LCDC3
LCDC2
Selection of LCD clock
fx/217
fx/216
fx/215
fx/214
0
0
1
1
0
1
0
0
274
µPD1615, µPD16F15, µPD1616
16.4 LCD Controller/Driver Settings
LCD controller/driver settings should be performed as shown below. When the LCD controller/driver
is used, the watch timer should be set to the operational state beforehand.
<1>Set the initial value in the display data memory (FA00H to FA27H).
<2>Set the pins to be used as segment outputs in the port function registers (PF8 to PF12).
<3>Set the display mode, operating mode in the LCD display mode register (LCDM), and the LCD
clock in the LCD clock control register (LCDC).
Next, set data in the display data memory according to the display contents.
275
µPD1615, µPD16F15, µPD1616
16.5 LCD Display Data Memory
The LCD display data memory is mapped onto addresses FA00H to FA27H. The data stored in the
LCD display data memory can be displayed on an LCD panel by the LCD controller/driver.
Figure 16-5 shows the relationship between the LCD display data memory contents and the segment
outputs/common outputs.
Any area not used for display can be used as normal RAM.
Figure 16-5: Relationship between LCD Display Data Memory Contents
and Segment/Common Outputs
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Address
FA27H
S0
S1
S2
S3
FA26H
FA25H
FA24H
S37
S38
S39
FA02H
FA01H
FA00H
COM3 COM2 COM1 COM0
Caution: The higher 4 bits of the LCD display data memory do not incorporate memory. Be
sure to set them to 0.
276
µPD1615, µPD16F15, µPD1616
16.6 Common Signals and Segment Signals
An individual pixel on an LCD panel lights when the potential difference of the corresponding common
signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD).
As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals,
it is driven by AC voltage.
(1) Common signals
For common signals, the selection timing order is as shown in Table 16-4 according to the number
of time divisions set, and operations are repeated with these as the cycle. In the static display
mode, the same signal is output to COM0 through COM3.
With 2-time-division operation, pins COM2 and COM3 are left open, and with 3-time-division
operation, the COM3 pin is left open.
Table 16-4: COM Signals
COM signal
COM0
COM1
COM2
Open
COM3
Time division
Static
2-time division
3-time division
4-time division
Open
Open
(2) Segment signals
Segment signals correspond to a 40-byte LCD display data memory. Each display data memory
bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3
timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. If
the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin
(S0 to S39).
Consequently, it is necessary to check what combination of front surface electrodes (correspond-
ing to the segment signals) and rear surface electrodes (corresponding to the common signals)
of the LCD display to be used form the display pattern, and then write bit data corresponding on
a one-to-one basis with the pattern to be displayed.
In addition, because LCD display data memory bits 1 and 2 are not used with the static display
mode, bits 2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the
3-time-division method, these can be used for other than display purposes.
Bits 4 to 7 are fixed at 0.
277
µPD1615, µPD16F15, µPD1616
(3) Common signal and segment signal output waveforms
The voltages shown in Table 16-5 are output in the common signals and segment signals.
The ±VLCD ON voltage is only produced when the common signal and segment signal are both
at the selection voltage; other combinations produce the OFF voltage.
Table 16-5: LCD Drive Voltages
a) Static display mode
Segment
Select
Non-select
VLC0, VSS1
0 V, 0 V
Common
VSS1, VLC0
-VLCD, +VLCD
VLC0, VSS1
(b) 1/2 bias method
Segment
Select
VSS1, VLC0
Non-select
Common
VLC0, VSS1
0 V, 0 V
Select level
VLC0, VSS1
-VLCD, +VLCD
-1/2 VLCD, +1/2 VLCD
Non-select level
VLC1 = VLC2
+1/2 VLCD, -1/2 VLCD
(c) 1/3 bias method
Segment
Select
VSS1, VLC0
Non-select
VLC1, VLC2
Common
Select level
Non-select level
VLC0, VSS1
VLC2, VLC1
-VLCD, +VLCD
-1/3 VLCD, +1/3 VLCD
-1/3 VLCD, +1/3 VLCD
-1/3 VLCD, +1/3 VLCD
278
µPD1615, µPD16F15, µPD1616
Figure 16-6 shows the common signal waveform, and Figure 16-7 shows the common signal and
segment signal voltages and phases.
Figure 16-6: Common Signal Waveform
(a) Static display mode
V
V
LC0
SS1
COMn
(Static)
V
LCD
TF = T
Remarks: 1.T: One LCDCL cycle
2.TF: Frame frequency
(b) 1/2 bias method
V
V
V
LC0
COMn
LC2
SS1
V
LCD
(Divided by 2)
TF = 2 x T
V
V
V
LC0
COMn
LC2
V
LCD
(Divided by 3)
SS1
TF = 3 x T
Remarks: 1.T: One LCDCL cycle
2.TF: Frame frequency
(c) 1/3 bias method
V
V
V
V
LC0
COMn
LC1
V
LCD
LC2
SS1
(Divided by 3)
TF = 3 x T
VLC0
VLC1
VLC2
VSS1
COMn
V
LCD
(Divided by 4)
TF = 4 x T
Remarks: 1.T: One LCDCL cycle
2.TF: Frame frequency
279
µPD1615, µPD16F15, µPD1616
Figure 16-7: Common Signal and Static Signal Voltages and Phases
(a) Static display mode
Selected
Not selected
V
LC0
V
LCD
Common signal
Segment signal
V
V
SS1
LC0
VLCD
V
SS1
T
T
Remark: T : One LCDCL cycle
(b) 1/2 bias method
Selected
Not selected
V
V
V
LC0
LC2
SS1
V
LCD
Common signal
Segment signal
V
V
V
LC0
LC2
SS1
VLCD
T
T
Remark: T : One LCDCL cycle
(c) 1/3 bias method
Selected
Not selected
V
LC0
V
V
LC1
LC2
V
LCD
Common signal
Segment signal
V
SS1
V
V
V
LC0
LC1
LC2
VLCD
V
SS1
T
T
Remark: T : One LCDCL cycle
280
µPD1615, µPD16F15, µPD1616
16.7 Supply of LCD Drive Voltages VLC0, VLC1, VLC2
The split resistors makes it possible to produce LCD drive voltages appropriate to the various bias
methods shown in Table 16-6 without using external split resistors.
Table 16-6: LCD Drive Voltages (with On-Chip Split Resistor)connected externally
Bias Method
No bias
1/2 bias
1/3 bias
LCD
(static mode)
Drive Voltage
VLC0
VLC1
VLC2
VLCD
VLCD
VLCD
2/3 VLCD
1/3 VLCD
2/3 VLCD
1/3 VLCD
1/2 VLCD
An example of supply of the LCD drive voltage from off-chip is shown in Figure 16-9. Stepless
LCD drive voltages can be supplied by means of variable resistor r.
Note:
The 1615 Subseries has no split resistors inside. The split resistors have to be set
externally for the different LCD voltages.
281
µPD1615, µPD16F15, µPD1616
Figure 16-8: LCD Drive Power Supply Connection Examples (with External Split Resistor)
Note
(a) Static display mode
(Example with VDD1 = 5 V, VLCD = 5 V)
VDD1
P-ch
LIPS
VLC0
VLC1
VLC2
VSS1
VLCD
VSS1
Note: LIPS should always be set to 1 (including in standby mode).
(b) 1/2 bias method
(c) 1/3 bias method
(Example with VDD1 = 5 V, VLCD = 5 V)
(Example with VDD1 = 5 V, VLCD = 5 V)
VDD1
VDD1
P-ch
LIPS
P-ch
LIPS
VLC0
VLC0
R
R
R
VLC1
VLC2
VSS1
VLC1
VLC2
VSS1
VLCD
VLCD
R
V
R
V
SS1
SS1
Caution: The LCD split resistors have to be set externally.
282
µPD1615, µPD16F15, µPD1616
Figure 16-9: Example of LCD Drive Voltage Supply from Off-Chip
VDD1
P-ch
LIPS
VLC0
R
VLC1
VLC2
VSS1
VLCD
R
R
V
SS1
3R
3R + r
=
VLCD
DD1
V
Caution: The LCD split resistors have to be set externally.
283
µPD1615, µPD16F15, µPD1616
16.8 Display Modes
16.8.1 Static display example
Figure 16-11 shows the connection of a static type 5-digit LCD panel with the display pattern shown
in Figure 16-10 with segment (S0 to S39) and common (COM0) signals. The display example is
“123.45,” and the display data memory contents (addresses FA68H to FA27H) correspond to this.
An explanation is given here taking the example of the third digit “3.” ( ). In accordance with the
display pattern in Figure 16-10, selection and non-selection voltages must be output to pins S16
through S23 as shown in Table 16-7 at the COM0 common signal timing.
Table 16-7: Selection and Non-Selection Voltages (COM0)
Segment
S16
S
S17
S
S18
S
S19
S
S20
NS
S21
S
S22
NS
S23
S
Common
COM0
S: Selection, NS: Non-selection
From this, it can be seen that 10101111 must be prepared in the BIT0 bits of the display data memory
corresponding to S16 to S23.
The LCD drive waveforms for S19, S20, and COM0 are shown in Figure 16-12. When S19 is at the
selection voltage at the timing for selection with COM0, it can be seen that the +VLCD/–VLCD AC square
wave, which is the LCD illumination (ON) level, is generated.
Shorting the COM0 through COM3 lines increases the current drive capability because the same
waveform as COM0 is output to COM1 through COM3.
Figure 16-10: Static LCD Display Pattern and Electrode Connections
S8n+3
S
8n+4
S
S
S
S
8n+2
8n+5
COM0
S
8n+6
8n+1
8n
S8n+7
n = 0 to 4
284
µPD1615, µPD16F15, µPD1616
Figure 16-11: Static LCD Panel Connection Example
COM3
COM2
COM1
COM0
Can be shorted
S0
S1
FA27H
6
S2
S3
S4
S5
S6
S7
S8
5
4
3
2
1
0
FA1FH
S9
E
D
C
S10
S11
S12
B
A
9
S13
S14
S15
8
S16
S17
S18
7
6
5
4
S19
S20
S21
S22
3
2
1
S23
S24
0
FA0FH
S25
S26
S27
E
D
C
B
A
9
S28
S29
S30
S31
S32
8
7
6
S33
S34
S35
5
4
S36
S37
S38
S39
3
2
1
FA00H
285
µPD1615, µPD16F15, µPD1616
Figure 16-12: Static LCD Drive Waveform Examples
TF
V
LC0
SS1
COM0
V
V
LC0
SS1
S19
V
V
LC0
SS1
S20
V
+VLCD
COM0-S19
0
–VLCD
+VLCD
COM0-S20
0
–VLCD
286
µPD1615, µPD16F15, µPD1616
16.8.2 2-time-division display example
Figure 16-14 shows the connection of a 2-time-division type 10-digit LCD panel with the display
pattern shown in Figure 16-13 with segment signals (S0 to S39) and common signals (COM0, COM1).
The display example is “123456.7890,” and the display data memory contents correspond to this.
An explanation is given here taking the example of the eighth digit “3” ( ). In accordance with the
display pattern in Figure 16-13, selection and non-selection voltages must be output to pins S28
through S31 as shown in Table 16-8 at the COM0 and COM1 common signal timings.
Table 16-8: Selection and Non-Selection Voltages (COM0, COM1)
Segment
S28
S29
S30
S31
Common
COM0
S
S
S
NS
S
NS
S
COM1
NS
S: Selection, NS: Non-selection
From this, it can be seen that, for example, xx10 must be prepared in the display data memory
corresponding to S31.
Examples of the LCD drive waveforms between S31 and the common signals are shown in
Figure 16-15. When S31 is at the selection voltage at the COM1 selection timing, it can be seen
that the +VLCD/–VLCD AC square wave, which is the LCD illumination (ON) level, is generated.
Figure 16-13: 2-Time-Division LCD Display Pattern and Electrode Connections
COM0
S4n + 2
S4n + 1
S4n + 3
S4n
COM1
n = 0 to 9
287
µPD1615, µPD16F15, µPD1616
Figure 16-14: 2-Time-Division LCD Panel Connection Example
COM3
COM2
COM1
COM0
Open
Open
S0
S1
FA27H
6
S2
S3
S4
S5
S6
S7
S8
5
4
3
2
1
0
FA1FH
S9
E
D
C
S10
S11
S12
B
A
9
S13
S14
S15
8
S16
S17
S18
7
6
5
4
S19
S20
S21
S22
3
2
1
S23
S24
0
FA0FH
S25
S26
S27
S28
E
D
C
B
A
9
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
8
7
6
5
4
3
2
1
FA00H
Remark:In bits marked X, any data can be stored because this is a 2-time-division display.
288
µPD1615, µPD16F15, µPD1616
Figure 16-15: 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
TF
V
V
V
LC0
LC1(VLC2
)
)
)
COM0
SS1
V
V
V
LC0
LC1(VLC2
SS1
COM1
V
V
V
LC0
LC1(VLC2
SS1
S31
+VLCD
+1/2VLCD
COM0-S31
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
COM1-S31
0
–1/2VLCD
–VLCD
289
µPD1615, µPD16F15, µPD1616
16.8.3 3-time-division display example
Figure 16-17 shows the connection of a 3-time-division type 13-digit LCD panel with the display
pattern shown in Figure 16-16 with segment signals (S0 to S38) and common signals (COM0 to COM2).
The display example is “123456.7890123,” and the display data memory contents correspond to this.
An explanation is given here taking the example of the eighth digit “6.” ( ) . In accordance with
the display pattern in Figure 16-16, selection and non-selection voltages must be output to pins S21
through S23 as shown in Table 16-9 at the COM0 to COM2 common signal timings.
Table 16-9: Selection and Non-Selection Voltages (COM0 to COM2)
Segment
S21
S22
S23
Common
COM0
NS
S
S
S
S
S
S
-
COM1
COM2
S
S: Selection, NS: Non-selection
From this, it can be seen that x110 must be prepared in the display data memory (address FA12H)
corresponding to S21.
Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure
16-18 (1/2 bias method) and Figure 16-19 (1/3 bias method). When S21 is at the selection voltage
at the COM1 selection timing, and S21 is at the selection voltage at the COM2 selection timing, it can
be seen that the +VLCD/–VLCD AC square wave, which is the LCD illumination (ON) level, is generated.
Figure 16-16: 3-Time-Division LCD Display Pattern and Electrode Connections
COM0
S3n + 1
S3n + 2
S3n
COM1
COM2
n = 0 to 12
290
µPD1615, µPD16F15, µPD1616
Figure 16-17: 3-Time-Division LCD Panel Connection Example
COM3
COM2
COM1
COM0
Open
S0
F
A27H
S1
S2
6
5
4
S3
S4
S5
S6
3
2
1
0
S7
S8
FA1FH
E
S9
S10
S11
S12
D
C
B
A
9
S13
S14
S15
S16
S17
S18
S19
8
7
6
5
4
3
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
2
1
0
FA0FH
E
D
C
B
A
9
S30
S31
S32
S33
S34
S35
8
7
6
5
4
S36
S37
S38
3
2
1
FA00H
Remarks: 1. x’ : Irrelevant bits because they have no corresponding segment in the LCD panel
2. x : Irrelevant bits because this is a 3-time-division display
291
µPD1615, µPD16F15, µPD1616
Figure 16-18: 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
T
F
VLC0
V
LC1(VLC2
)
)
)
)
COM0
COM1
VSS1
V
V
V
LC0
LC1(VLC2
SS1
V
V
V
LC0
LC1(VLC2
SS1
COM2
S21
VLC0
V
LC1(VLC2
SS1
V
+VLCD
+1/2VLCD
COM0-S21
COM1-S21
COM2-S21
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
0
–1/2VLCD
–VLCD
292
µPD1615, µPD16F15, µPD1616
Figure 16-19: 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
VLC1
COM0
VLC2
VSS1
VLC0
VLC1
COM1
VLC2
VSS1
VLC0
VLC1
COM2
VLC2
VSS1
VLC0
VLC1
S21
VLC2
VSS1
+VLCD
+1/3VLCD
COM0-S21
0
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
COM1-S21
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
COM2-S21
–1/3VLCD
–VLCD
293
µPD1615, µPD16F15, µPD1616
16.8.4 4-time-division display example
Figure 16-21 shows the connection of a 4-time-division type 20-digit LCD panel with the display
pattern shown in Figure 16-20 with segment signals (S0 to S39) and common signals (COM0 to COM3).
The display example is “123456.78901234567890,” and the display data memory contents correspond
to this.
An explanation is given here taking the example of the 15th digit “6.” ( ). In accordance with the
display pattern in Figure 16-20, selection and non-selection voltages must be output to pins S28 and
S29 as shown in Table 16-10 at the COM0 to COM3 common signal timings.
Table 16-10: Selection and Non-Selection Voltages (COM0 to COM3)
Segment
S28
S29
Common
COM0
S
NS
S
S
S
S
S
COM1
COM2
COM3
S
S: Selection, NS: Non-selection
From this, it can be seen that 1101 must be prepared in the display data memory (address FA0BH)
corresponding to S28.
Examples of the LCD drive waveforms between S28 and the COM0 and COM1 signals are shown
in Figure 16-22 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When
S28 is at the selection voltage at the COM0 selection timing, it can be seen that the +VLCD/–VLCD AC
square wave, which is the LCD illumination (ON) level, is generated.
Figure 16-20: 4-Time-Division LCD Display Pattern and Electrode Connections
S
2n
COM0
COM2
COM1
COM3
S
2n + 1
n = 0 to 18
294
µPD1615, µPD16F15, µPD1616
Figure 16-21: 4-Time-Division LCD Panel Connection Example
COM3
COM2
COM1
COM0
S0
S1
S2
S3
FA27H
6
5
4
S4
S5
S6
S7
S8
3
2
1
0
FA1FH
S9
E
D
C
S10
S11
S12
B
A
9
S13
S14
S15
8
S16
S17
S18
S19
7
6
5
4
S20
S21
3
2
S22
S23
1
0
S24
FA0FH
S25
S26
S27
E
D
C
B
A
9
S28
S29
S30
S31
S32
S33
S34
S35
8
7
6
5
4
S36
S37
3
2
S38
S39
1
FA00H
295
µPD1615, µPD16F15, µPD1616
Figure 16-22: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
VLC1
COM0
VLC2
VSS1
VLC0
VLC1
COM1
VLC2
VSS1
VLC0
VLC1
COM2
VLC2
VSS1
VLC0
VLC1
COM3
VLC2
VSS1
VLC0
VLC1
S28
VLC2
VSS1
+VLCD
+1/3VLCD
0
COM0-S28
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
COM1-S28
–1/3VLCD
–VLCD
296
µPD1615, µPD16F15, µPD1616
[Memo]
297
µPD1615, µPD16F15, µPD1616
Chapter 17 Sound Generator
17.1 Sound Generator Function
The sound generator has the function to sound the buzzer from an external speaker, and the following
two signals are output.
(1) Basic cycle output signal (with/without amplitude)
A buzzer signal with a variable frequency in a range of 0.25 to 7.3 kHz (at fx = 8.00 MHz) can
be output. The amplitude of the basic cycle output signal can be varied by ANDing the basic cycle
output signal with the 7-bit-resolution PWM signal, to enable control of the buzzer sound volume.
(2) Amplitude output signal
A PWM signal with a 7-bit resolution for variable amplitude can be independently output.
Figure 17-1 shows the sound generator block diagram and Figure17-2 shows the concept of each
signal.
Figure 17-1: Sound Generator Block Diagram
Internal bus
Sound generator control register (SGCR)
SGCL1SGCL0
TCE SGOB SGCL2
SGCL0
2
fX
1/2
f
SG1
f
SG2
5-bit counter
Comparator
Clear
1/2
SGO/
SGOF/
P47
PWM amplitude
S
R
Q
SGOA/
P46
Comparator
SGOB
7
4
P46 output
latch
SGBR3SGBR2
SGBR1SGBR0
SGAM6SGAM5SGAM4SGAM3
SGAM2SGAM1SGAM0
PM46
Port mode
Sound generator buzzer
control register (SGBR)
Sound generator amplitude
register (SGAM)
register 4 (PM4)
Internal bus
298
µPD1615, µPD16F15, µPD1616
Figure 17-2: Concept of Each Signal
Basic cycle output SGOF
(without amplitude)
Amplitude output SGOA
Basic cycle output SGO
(with amplitude)
17.2 Sound Generator Configuration
The sound generator consists of the following hardware.
Table 17-1: Sound Generator Configuration
Item
Counter
Configuration
8 bits x 1, 5 bits x 1
SGO/SGOF (with/without append bit of basic cycle output)
SGOA (amplitude output)
SG output
Sound generator control register (SGCR)
Sound generator buzzer control register (SGBR)
Sound generator amplitude register (SGAM)
Control register
299
µPD1615, µPD16F15, µPD1616
17.3 Sound Generator Control Registers
The following three types of registers are used to control the sound generator.
• Sound generator control register (SGCR)
• Sound generator buzzer control register (SGBR)
• Sound generator amplitude control register (SGAM)
(1)Sound generator control register (SGCR)
SGCR is a register which sets up the following four types.
• Controls sound generator output
• Selects output of sound generator
• Selects sound generator input frequency fSG1
• Selects 5-bit counter input frequency fSG2
SGCR is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SGCR to 00H.
Figure 17-3 shows the SGCR format.
300
µPD1615, µPD16F15, µPD1616
Figure 17-3: Sound Generator Control Register (SGCR) Format
Symbol
SGCR
7
6
0
5
0
4
0
3
2
1
0
Address After Reset R/W
FF66H 00H R/W
TCE
SGOB
SGCL2 SGCL1 SGCL0
TCE
0
Sound Generator Output Selection
Timer operation stopped
SGOF/SGO and SGOA for low-level output
Sound generator operation
1
SGOF/SGO and SGOA for output
Caution: Before setting the TCE bit, set all the other bits.
Remark:
SGOF: Basic cycle signal (without amplitude)
SGO: Basic cycle signal (with amplitude)
SGOA: Amplitude signal
SGOB
Sound Generator Output Selection
Selects SGOF and SGOA outputs
Selects SGO and PCL outputs
0
1
SGCL2 SGCL1
5-Bit Counter Input Frequency fSG2 Selection
fSG2 = fSG1/25
fSG2 = fSG1/26
fSG2 = fSG1/27
fSG2 = fSG1/28
0
0
1
1
0
1
0
1
SGCL0
Sound Generator Input Frequency Selection
0
1
fSG1 = fX/27
fSG1 = fX/28
Cautions: 1. When rewriting SGCR to other data, stop the timer operation (TCE = 0) beforehand.
2. Bits 4 to 6 must be set to 0.
301
µPD1615, µPD16F15, µPD1616
The sound generator output frequency fSG can be calculated by the following expression.
(SGCL0 – SGCL1 – 2 x SGCL2 – 7)
fSG = 2
x {fx/(SGBR + 17)}
Substitute set 0 or 1 to SGCL0 to SGCL2 in the above expression. Substitute a decimal value to SGBR.
Where fx = 8 MHz, SGCL0 to SGCL2 is (1, 0, 0), and SGBR0 to SGBR3 is (1, 1, 1, 1), SGBR = 15.
Therefore,
(1 – 0 – 2 x 0 – 7)
fSG = 2
x {fx/(15 + 17)}
= 3.906 kHz
(2) Sound generator buzzer control register (SGBR)
SGBR is a register that sets the basic frequency of the sound generator output signal.
SGBR is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SGBR to 00H.
Figure 17-4 shows the SGBR format.
Figure 17-4: Sound Generator Buzzer Control Register (SGBR) Format
Symbol
SGBR
7
0
6
0
5
0
4
0
3
2
1
0
Address After Reset R/W
FF68H 00H R/W
SGBR3 SGBR2 SGBR1 SGBR0
Cautions: 1. When rewriting SGBR to other data, stop the timer operation (TCE = 0) beforehand.
2. Bits 4 to 7 must be set to 0.
302
µPD1615, µPD16F15, µPD1616
Figure 17-5: Sound Generator Frequency Selection
SGBR
SGCL2,1 (Hz)
SGCL0
4-bit comparator
00
01
10
11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7352.9
6944.4
6578.9
6250.0
5952.4
5681.8
5434.8
5208.3
5000.0
4807.7
4629.6
4464.3
4310.3
4166.7
4032.3
3906.3
3676.5
3472.2
3289.5
3125.0
2976.2
2840.9
2717.4
2604.2
2500.0
2403.8
2314.8
2232.1
2155.2
2083.3
2016.1
1953.1
3676.5
3472.2
3289.5
3125.0
2976.2
2840.9
2717.4
2604.2
2500.0
2403.8
2314.8
2232.1
2155.2
2083.3
2016.1
1953.1
1838.2
1736.1
1644.7
1562.5
1488.1
1420.5
1358.7
1302.1
1250.0
1201.9
1157.4
1116.1
1077.6
1041.7
1008.1
976.6
1838.2
1736.1
1644.7
1562.5
1488.1
1420.5
1358.7
1302.1
1250.0
1201.9
1157.4
1116.1
1077.6
1041.7
1008.1
976.6
919.1
868.1
822.4
781.3
744.0
710.2
679.3
651.0
625.0
601.0
578.7
558.0
538.8
520.8
504.0
488.3
919.1
868.1
822.4
781.3
744.0
710.2
679.3
651.0
625.0
601.0
578.7
558.0
538.8
520.8
504.0
488.3
459.6
434.0
411.2
390.6
372.0
355.1
339.7
325.5
312.5
300.5
289.4
279.0
269.4
260.4
252.0
244.1
0
1
(3) Sound generator amplitude register (SGAM)
SGAM is a register that sets the amplitude of the sound generator output signal.
SGAM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SGAM to 00H.
Figure 17-6 shows the SGAM format.
303
µPD1615, µPD16F15, µPD1616
Figure 17-6: Sound Generator Amplitude Register (SGAM) Format
Symbol
SGAM
7
0
6
5
4
3
2
1
0
Address After Reset R/W
FF67H 00H R/W
SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0
Amplitude
0/128
SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
¦
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2/128
3/128
4/128
5/128
6/128
7/128
8/128
9/128
10/128
11/128
12/128
13/128
14/128
15/128
16/128
17/128
18/128
19/128
20/128
21/128
22/128
23/128
24/128
25/128
26/128
27/128
28/128
29/128
30/128
31/128
¦
0
1
1
1
1
1
1
128/128
Cautions: 1. When rewriting the contents of SGAM, the timer operation does not need to be
stopped. However, note that a high level may be output for one period due to
rewrite timing.
2. Bit 7 must be set to 0.
304
µPD1615, µPD16F15, µPD1616
17.4 Sound Generator Operations
17.4.1 To output basic cycle signal SGOF (without amplitude)
Select SGOF output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to “0”.
The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3
is output.
At the same time, the amplitude signal with an amplitude specified by the SGAM0 to SGAM6 is output
from the SGOA pin.
Figure 17-7: Sound Generator Output Operation Timing without Amplitude
n
n
n
n
n
n
Timer
Comparator 1 coincidence
SGOF
SGOA
17.4.2 To output basic cycle signal SGO (with amplitude)
Select SGO output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to “1”.
The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3
is output.
When SGO output is selected, the SGOA pin can be used as a PCL output (clock output) or I/O port
pin.
Figure 17-8: Sound Generator Output Operation Timing with Amplitude
n
n
n
n
n
n
Timer
Comparator 1 coincidence
SGOF
SGOA
SGO
305
µPD1615, µPD16F15, µPD1616
[Memo]
306
µPD1615, µPD16F15, µPD1616
Chapter 18 Interrupt Functions
18.1 Interrupt Function Types
The following three types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt
priority control and is given top priority over all other interrupt requests.
It generates a standby release signal.
The non-maskable interrupt has one source of interrupt request from the watchdog timer.
(2) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt
priority group and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H,
and PR1L).
Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts
with the same priority are simultaneously generated, each interrupts has a predetermined priority
(see Table 18-1).
A standby release signal is generated.
The maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal
interrupt requests.
(3) Software interrupt
This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged
even in a disabled state. The software interrupt does not undergo interrupt priority control.
307
µPD1615, µPD16F15, µPD1616
18.2 Interrupt Sources and Configuration
There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources.
Table 18-1: Interrupt Source List
Basic
struct
ure
Vector
code
address
Interrupt
type
Priority
(default)
Interrupt request source
Reset input
type
Resetting
-
-
RESET
0000H
0004H
Non-
maskable
Watchdog timer overflow (when non-maskable
interrupt is selected)
INTWDT
( A )
( B )
Watchdog timer overflow (when interval timer is
selected)
0
INTWDT
1
2
3
4
5
6
INTVE
INTVT
INTVR
INTP0
INTP1
INTP2
0006H
0008H
000AH
000CH
000EH
0010H
INTVE → VAN-End of Message
INTVT → VAN-Emission
INTVR → VAN-Reception
External interrupt pin input edge detection
( C )
Agreement between TM00 and CR00 (when
compare register is specified)
TI01 valid edge detection (when capture register is
specified)
Agreement between TM00 and CR01 (when
compare register is specified)
TI00 valid edge detection (when capture register is
specified)
7
8
INTTM00
INTTM01
0012H
0014H
Maskable
9
INTTM50 Agreement between TM50 and CR50
INTTM51 Agreement between TM51 and CR51
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
0026H
003EH
10
11
12
13
14
15
16
17
-
( B)
INTWTI
INTWT
INTCSI3
INTSER
INTSR
INTST
INTAD
BRK
Watch timer interval interrupt
Watch interrupt
SIO30 transfer completion
UART0 reception error occurrence
UART0 reception completion
UART0 transmission completion
A/D conversion end
Software
Execution of BRK instruction
( D)
Notes:
1. Default priorities are intended for two or more simultaneously generated maskable
interrupt requests. 0 is the highest priority and 26 is the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) of Figure 18-1.
308
µPD1615, µPD16F15, µPD1616
Figure 18-1: Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Vector Table
Priority Control
Circuit
Interrupt
Request
Address
Generator
Standby
Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
IE
PR
ISP
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
IF
Standby
Release Signal
IF
IE
:
:
Interrupt request flag
Interrupt enable flag
ISP : Inservice priority flag
MK : Interrupt mask flag
PR : Priority specify flag
309
µPD1615, µPD16F15, µPD1616
Figure 18-1: Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(EGN, EGP)
MK
IE
PR
ISP
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
IF
Standby
Release Signal
(D) Software interrupt
Internal Bus
Vector Table
Address
Generator
Interrupt
Request
Priority Control
Circuit
IF
IE
:
:
Interrupt request flag
Interrupt enable flag
ISP : Inservice priority flag
MK : Interrupt mask flag
PR : Priority specify flag
310
µPD1615, µPD16F15, µPD1616
18.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L)
• Interrupt mask flag register (MK0L, MK0H, MK1L)
• Priority specify flag register (PR0L, PR0H, PR1L)
• External interrupt mode register (EGP, EGN)
• Program status word (PSW)
Table 18-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags
corresponding to interrupt request sources.
Table 18-2: Various Flags Corresponding to Interrupt Request Sources
Interrupt Request
Signal Name
Interrupt Request Flag
Interrupt Mask Flag
Priority Specify Flag
INTWDT
WDTIF
VEIF
WDTMK
VEMK
WDTPR
VEPR
INTVE
INTVT
VTIF
VTMK
VTPR
INTVR
INTP0
VRIF
VRMK
VRPR
PIF0
PMK0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTTM00
INTTM01
INTM50
INTM51
INTWTI
INTWT
INTCSI3
INTSER
INTSR
INTST
TMIF00
TMIF01
TMIF50
TMIF51
WTIIF
WTIF
CSIIF3
SERIF
SRIF
TMMK00
TMMK01
TMMK50
TMMK51
WTIMK
WTMK
CSIMK3
SERMK
SRMK
TMPR00
TMPR01
TMPR50
TMPR51
WTIPR
WTPR
CSIPR3
SERPR
SRPR
STIF
STMK
STPR
INTAD
ADIF
ADMK
ADPR
311
µPD1615, µPD16F15, µPD1616
(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
Theinterruptrequestflagissetto1whenthecorrespondinginterruptrequestisgeneratedoraninstruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H
are used as a 16-bit register IF0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to 00H.
Figure 18-2: Interrupt Request Flag Register Format
After
Reset
Address
FFE0H
R/W
R/W
1
0
Symbol
IF0L
6
5
4
3
2
7
00H
TMIF00 PIF2
VTIF VEIF WDTIF
PIF1
PIF0
VRIF
FFE1H
FFE2H
00H
00H
R/W
R/W
IF0H
IF1L
CSIIF3
0
TMIF01
SERIF
0
WTIF WTIIFTMIF51TMIF50
SRIF
0
ADIF
0
0
0
STIF
xxIFx
Interrupt Request Flag
No interrupt request signal
0
1
Interrupt request signal is generated;
Interrupt request state
Cautions: 1. WDTIF flag is R/W enabled only when a watchdog timer is used as an interval timer.
If used in the watchdog timer mode 1, set WDTIF flag to 0.
2. Set always 0 in IF1L bit 2 to bit 7.
312
µPD1615, µPD16F15, µPD1616
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to
set standby clear enable/disable.
MK0L, MK0H and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and
IF0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 18-3: Interrupt Mask Flag Register Format
After
Reset
Address
FFE4H
R/W
R/W
1
0
Symbol
MK0L
6
5
4
3
2
7
00H
TMMK00 PMK2
PMK1 PMK0
VRMK VTMK
VEMK WDTMK
FFE5H
FFE6H
00H
00H
R/W
R/W
MK0H
MK1L
SRMK SERMK CSIMK3 WTMK WTIMK TMMK51 TMMK50TMMK01
1
1
1
1
1
1
ADMK STMK
xxMK
x
Interrupt Servicing Control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Cautions: 1. If WDTMK flag is read when a watchdog timer is used as a non-maskable interrupt,
MK0 value becomes undefined.
2. Set always 1 in MK1L bit 2 to bit 7.
313
µPD1615, µPD16F15, µPD1616
(3) Priority specify flag registers (PR0L, PR0H, PR1L)
The priority specify flag is used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H
are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 18-4: Priority Specify Flag Register Format
After
Reset
Address
FFE8H
R/W
R/W
1
0
Symbol
PR0L
6
5
4
3
2
7
00H
PPR2
PPR1
PPR0
VRPR
TMPR00
VTPR
VEPR WDTPR
FFE9H
FFEAH
00H
00H
R/W
R/W
PR0H
PR1L
SRPR SERPR
CSIPR3
0
WTIPR
0
TMPR01
STPR
WTPR
0
TMPR51 TMPR50
0
0
0
ADPR
xxPRx
Priority Level Selection
High priority level
Low priority level
0
1
Cautions: 1. When a watchdog timer is used as a non-maskable interrupt, set 1 in WDTPR flag.
2. Set always 1 in PR1L bit 2 to bit 7.
314
µPD1615, µPD16F15, µPD1616
(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable
register (EGN)
EGP and EGN specify the valid edge to be detected on pins P00 to P02.
EGP and EGN can be read or written to with a 1-bit or 8-bit memory manipulation instruction.
These registers are set to 00H when the RESET signal is output.
Figure 18-5: Formats of External Interrupt Rising Edge Enable Register and External Inter-
rupt Falling Edge Enable Register
Symbol
EGP
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF48H
On Reset R/W
00H R/W
EGP2
EGP1
EGP0
Symbol
EGN
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF49H
On Reset R/W
00H R/W
EGN2
EGN1
EGN0
EGPn
EGNn
Valid edge of INTPn pin (n = 0 – 4)
0
0
1
1
0
1
0
1
Interrupt disable
Falling edge
Rising edge
Both rising and falling edges
315
µPD1615, µPD16F15, µPD1616
(5) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status
for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control
multiple interrupt servicing are mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction
and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, and when
the BRK instruction is executed, the contents of PSW automatically is saved into a stack and the IE
flag is reset to 0. If a maskable interrupt request is acknowledged contents of the priority specify flag
of the acknowledged interrupt are transferred to the ISP flag. The acknowledged contents of PSW is
also saved into the stack with the PUSH PSW instruction. It is reset from the stack with the RETI,
RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 18-6: Program Status Word Format
After
Reset
7
6
Z
5
4
3
2
0
<1> <0>
ISP CY
02H
PSW
IE
RBS1 AC RBS0
Used when Normal Instruction is Executed
ISP
0
Priority of Interrupt Currently Being Received
High-priority interrupt servicing
(low-priority interrupt disable)
Interrupt request not acknowledged or low-priority
interrupt servicing
1
(all-maskable interrupts enable)
IE
0
Interrupt Request Acknowledge Enable/Disable
Disable
Enable
1
316
µPD1615, µPD16F15, µPD1616
18.4 Interrupt Servicing Operations
18.4.1 Non-maskable interrupt request acknowledge operation
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request
acknowledge disable state. It does not undergo interrupt priority control and has highest priority over
all other interrupts.
If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the
stacks, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents
are loaded into PC and branched.
A new non-maskable interrupt request generated during execution of a non-maskable interrupt
servicing program is acknowledged after the current execution of the non-maskable interrupt servicing
program is terminated (following RETI instruction execution) and one main routine instruction is
executed. If a new non-maskable interrupt request is generated twice or more during non-maskable
interrupt service program execution, only one non-maskable interrupt request is acknowledged after
termination of the non-maskable interrupt service program execution.
317
µPD1615, µPD16F15, µPD1616
Figure 18-7: Flowchart from Non-Maskable Interrupt Generation to Acknowledge
Start
WDTM4 = 1
(with watchdog timer
No
mode selected)?
Interval timer
Yes
No
Overflow in WDT?
Yes
WDTM3 = 0
(with non-maskable
No
interrupt selected)?
Reset processing
Yes
Interrupt request generation
No
WDT interrupt servicing?
Interrupt request
held pending
Yes
Interrupt control
register unaccessed?
No
Yes
Interrupt
service start
WDTM: Watchdog timer mode register
WDT:
Watchdog timer
Figure 18-8: Non-Maskable Interrupt Request Acknowledge Timing
PSW and PC Save, Jump Interrupt Sevicing
to Interrupt Servicing
Program
CPU Instruction
WDTIF
Instruction
Instruction
WDTIF: Watchdog timer interrupt request flag
318
µPD1615, µPD16F15, µPD1616
Figure 18-9: Non-Maskable Interrupt Request Acknowledge Operation
(a) If a new non-maskable interrupt request is generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request
1 Instruction
Execution
NMI Request
NMI Request Reserve
Reserved NMI Request Processing
(b) If two non-maskable interrupt requests are generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request
NMI
Request
Reserved
Reserved
1 Instruction
Execution
NMI
Request
Although two or more NMI requests
have been generated, only one
request has been acknowledged.
319
µPD1615, µPD16F15, µPD1616
18.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1
and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an
interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not
acknowledged during high-priority interrupt service (with ISP flag reset to 0).
Wait times maskable interrupt request generation to interrupt servicing are as follows.
Table 18-3: Times from Maskable Interrupt Request Generation to Interrupt Service
MinimumTime
7 clocks
MaximumTimeNote
32 clocks
When xxPRx = 0
When xxPRx = 1
8 clocks
33 clocks
Note:
If an interrupt request is generated just before a divide instruction, the wait time is
maximized.
1
fCPU
Remark:
1 clock:
(fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for
higher priority with the priority specify flag is acknowledged first. If two or more requests are specified
for the same priority with the priority specify flag, the interrupt request with the higher default priority
is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 18-10 shows interrupt request acknowledge algorithms.
When a maskable interrupt request is acknowledged, the contents of program status word (PSW) and
program counter (PC) are saved to stacks, in this order. Then, the IE flag is reset (to 0), and the value
of the acknowledged interrupt priority specify flag is transferred to the ISP flag. Further, the vector table
data determined for each interrupt request is loaded into PC and branched.
Return from the interrupt is possible with the RETI instruction.
320
µPD1615, µPD16F15, µPD1616
Figure 18-10: Interrupt Request Acknowledge Processing Algorithm
Start
No
xxIF = 1?
Yes (Interrupt Request
Generation)
No
xxMK = 0?
Yes
Interrupt request
reserve
Yes (High priority)
xxPR = 0?
No (Low Priority)
Any high-
priority interrupt among
simultaneously generated
xxPR = 0 interrupts?
Any
Yes
simultaneously
generated xxPR = 0
interrupts?
Yes
Yes
Interrupt request
reserve
Interrupt request
reserve
No
No
No
Any
IE = 1?
Yes
simultaneously
generated high-priority
interrupts?
Interrupt request
reserve
Interrupt request
reserve
Vectored interrupt
servicing
No
No
No
IE = 1?
Yes
Interrupt request
reserve
ISP = 1?
Yes
Interrupt request
reserve
Vectored interrupt
servicing
xxIF : Interrupt request flag
xxMK : Interrupt mask flag
xxPR : Priority specify flag
IE
: Flag to control maskable interrupt request acknowledge
ISP : Flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is
being
serviced, 1 = interrupt request is not acknowledged or an interrupt with lower
serviced)
priority is being
321
µPD1615, µPD16F15, µPD1616
Figure 18-11: Interrupt Request Acknowledge Timing (Minimum Time)
6 Clocks
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
CPU Processing
Instruction
Instruction
xxIF
(xxPR = 1)
8 Clocks
xxIF
(xxPR = 0)
7 Clocks
1
fCPU
Remark:
1 clock:
(fCPU: CPU clock)
Figure 18-12: Interrupt Request Acknowledge Timing (Maximum Time)
25 Clocks
6 Clocks
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
CPU Processing
Instruction
Divide Instruction
xxIF
(xxPR = 1)
33 Clocks
xxIF
(xxPR = 0)
32 Clocks
1
fCPU
Remark:
1 clock:
(fCPU: CPU clock)
18.4.3 Software interrupt request acknowledge operation
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot
be disabled.
If a software interrupt is acknowledged, the contents of program status word (PSW) and program
counter (PC) are saved to stacks, in this order. Then the IE flag is reset (to 0), and the contents of
the vector tables (003EH and 003FH) are loaded into PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution: Do not use the RETI instruction for returning from the software interrupt.
322
µPD1615, µPD16F15, µPD1616
18.4.4 Multiple interrupt servicing
A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt.
A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1)
(except non-maskable interrupt). As soon as an interrupt request is acknowledged, it enters the
acknowledge disable state (IE = 0). Therefore, in order to enable a multiple interrupt, it is necessary
to set the interrupt enable state by setting the IE flag (1) with the EI instruction during interrupt servicing.
Even in an interrupt enabled state, a multiple interrupt may not be enabled. However, it is controlled
according to the interrupt priority. There are two priorities, the default priority and the programmable
priority. The multiple interrupt is controlled by the programmable priority control.
If an interrupt request with the same or higher priority than that of the interrupt being serviced is
generated, it is acknowledged as a multiple interrupt. In the case of an interrupt with a priority lower
than that of the interrupt being processed, it is not acknowledged as a multiple interrupt.
Interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority
is reserved and acknowledged following one instruction execution of the main processing after the
completion of the interrupt being serviced.
During non-maskable interrupt servicing, multiple interrupts are not enabled.
Table 18-4 shows an interrupt request enabled for multiple interrupt during interrupt servicing, and
Figure 18-13 shows multiple interrupt examples.
Table 18-4: Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Multiple Interrupt
Request
Maskable Interrupt Request
xxPR = 0 xxPR = 1
Non-maskable
InterruptRequest
Interrupt being Serviced
IE = 1
IE = 0
IE = 1
IE = 0
Non-maskableinterrupt
Maskable interrupt
D
E
E
E
D
E
E
E
D
D
D
D
D
D
E
E
D
D
D
D
ISP = 0
ISP = 1
Softwareinterrupt
Remarks: 1. E: Multiple interrupt enable
2. D: Multiple interrupt disable
3. ISP and IE are the flags contained in PSW
ISP = 0: An interrupt with higher priority is being serviced
ISP = 1: An interrupt request is not accepted or an interrupt with lower priority is being
serviced
IE = 0: Interrupt request acknowledge is disabled
IE = 1: Interrupt request acknowledge is enabled
4. xxPR is a flag contained in PR0L, PR0H, and PRIL
xxPR = 0: Higher priority level
xxPR = 1: Lower priority level
323
µPD1615, µPD16F15, µPD1616
Figure 18-13: Multiple Interrupt Example (1/2)
Example 1. Two multiple interrupts generated
Main Processing
EI
INTxx
Servicing
INTyy
Servicing
INTzz
Servicing
IE = 0
IE = 0
IE = 0
EI
EI
INTyy
INTzz
(PR = 0)
(PR = 0)
INTxx
(PR = 1)
RETI
RETI
RETI
During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a
multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge,
and the interrupt request acknowledge enable state is set.
Example 2. Multiple interrupt is not generated by priority control
Main Processing
INTxx
INTyy
Servicing
Servicing
EI
IE = 0
EI
INTyy
(PR = 1)
INTxx
(PR = 0)
RETI
1 Instruction
Execution
IE = 0
RETI
The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because
the interrupt priority is lower than that of INTxx, and a multiple interrupt is not generated. INTyy request
is retained and acknowledged after execution of 1 instruction execution of the main processing.
PR = 0 : Higher priority level
PR = 1 : Lower priority level
IE = 0 : Interrupt request acknowledge disable
324
µPD1615, µPD16F15, µPD1616
Figure 18-13: Multiple Interrupt Example (2/2)
Example 3. A multiple interrupt is not generated because interrupts are not enabled
Main Processing
EI
INTxx
Servicing
INTyy
Servicing
IE = 0
INTyy
(PR = 0)
INTxx
(PR = 0)
RETI
IE = 0
1 Instruction
Execution
RETI
Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued),
interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy
request is reserved and acknowledged after 1 instruction execution of the main processing.
PR = 0 : Higher priority level
IE = 0 : Interrupt request acknowledge disable
325
µPD1615, µPD16F15, µPD1616
18.4.5 Interrupt request reserve
Some instructions may reserve the acknowledge of an instruction request until the completion of the
execution of the next instruction even if the interupt request is generated during the execution. The
following shows such instructions (interrupt request reserve instruction).
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1/CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT
• BF
PSW.bit, $addr16
PSW.bit, $addr16
• BTCLRPSW.bit, $addr16
• EI
• DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0,
INTM1 registers
Caution: BRK instruction is not an interrupt request reserve instruction described above.
However, in a software interrupt started by the execution of BRK instruction, the
IE flag is cleared to 0. Therefore, interrupt requests are not acknowledged even
when a maskable interrupt request is issued during the execution of the BRK
instruction. However, non-maskable interrupt requests are acknowledged.
Figure 18-14 shows the interrupt request hold timing.
Figure 18-14: Interrupt Request Hold
Save PSW and PC,
Jump to interrupt service
Interrupt service
program
CPU processing
xxIF
Instruction N
Instruction M
Remarks: 1. Instruction N: Instruction that holds interrupts requests
2. Instruction M: Instructions other than interrupt request pending instruction
3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
326
µPD1615, µPD16F15, µPD1616
[Memo]
327
µPD1615, µPD16F15, µPD1616
Chapter 19 Standby Function
19.1 Standby Function and Configuration
19.1.1 Standby function
The standby function is designed to decrease power consumption of the system. The following two
modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU
operation clock. System clock oscillator continues oscillation. In this mode, current consumption
cannot be decreased as in the STOP mode. The HALT mode is valid to restart immediately upon
interrupt request and to carry out intermittent operations such as watch applications.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator
stops and the whole system stops. CPU current consumption can be considerably decreased.
Data memory low-voltage hold (down to VDD = 2.0 V) is possible. Thus, the STOP mode is effective
to hold data memory contents with ultra-low current consumption. Because this mode can be cleared
upon interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is necessary to secure an oscillation stabilization time after the STOP
mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt
request.
In any mode, all the contents of the register, flag, and data memory just before standby mode setting
are held. The input/output port output latch and output buffer statuses are also held.
Cautions: 1. The STOP mode can be used only when the system operates with the main system
clock (subsystem clock oscillation cannot be stopped). The HALT mode can be
used with either the main system clock or the subsystem clock.
2. When proceeding to the STOP mode, be sure to stop the peripheral hardware
operation and execute the STOP instruction.
3. The following sequence is recommended for power consumption reduction of the
A/D converter when the standby function is used: first clear bit 7 (CS) to 0 to stop
the A/D conversion operation, and then execute the HALT or STOP instruction.
328
µPD1615, µPD16F15, µPD1616
19.1.2 Standby function control register
A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is
controlled with the oscillation stabilization time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
17
RESET input sets OSTS to 04H. However, it takes 2 /fx until the STOP mode is cleared by RESET
input.
Figure 19-1: Oscillation Stabilization Time Select Register Format
After
Reset
Symbol
OSTS
7
0
6
5
0
4
0
3
2
1
0
Address
FFFAH
R/W
R/W
0
0
OSTS0
04H
OSTS2 OSTS1
Selection of Oscillation Stabilization
Time when STOP Mode is Released
OSTS2OSTS1OSTS0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
212/f
214/f
215/f
216/f
217/f
x
x
x
x
x
(512 s)
µ
(2 ms)
(4.1 ms)
(8.19 ms)
(16.38 ms)
0
Other than above Setting prohibited
Caution: The wait time after STOP mode clear does not include the time (see “a” in the
illustration below) from STOP mode clear to clock oscillation start, regardless of
clearance by RESET input or by interrupt generation.
STOP Mode Clear
X1 Pin
Voltage
Waveform
a
VSS
Remarks: 1. fx: Main system clock oscillation frequency
2. Values in parentheses apply to operating at fx = 8.00 MHz
329
µPD1615, µPD16F15, µPD1616
19.2 Standby Function Operations
19.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock
or the subsystem clock. The operating status in the HALT mode is described below.
Table 19-1: HALT Mode Operating Status
HALT mode setting
HALT execution during main
system clock operation
HALT execution during
subsystem clock operation
(Main system clock stops)
Item
Both main and subsystem clocks can be oscillated / Clock supply to
the CPU stops
Clock generator
CPU
Operation stops
Port (output latch)
Status before HALT mode setting is held
Operable when TI00 is selected
as count clock
16-bit timer /event counter (TM0)
Operable
8-bit timer event counter
(TM50/TM51)
Operable when TI00 is selected
as count clock
Operable
Operable when fxt is selected as
count clock
Watch timer
Operable
Watchdog timer
A/D converter
Operable
Operation stops
Operable
Operable
Operable
Operable
Operable
Operable
Operation stops
Serial I/F - SIO30
Serial I/F - UART
VAN
Operable at external SCK
Operation stops
Operation stops
Sound generator
External interrupt (INTP0 to INTP2)
LCD
Operation stops
Operation stops
330
µPD1615, µPD16F15, µPD1616
(2) HALT mode clear
The HALT mode can be cleared with the following four types of sources.
(a) Clear upon unmasked interrupt request
An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is
enabled, vectored interrupt service is carried out. If disabled, the next address instruction is
executed.
Figure 19-2: HALT Mode Clear upon Interrupt Generation
HALT
Instruction
Wait
Wait
Standby
Release Signal
Operating
Mode
HALT Mode
Operating Mode
Oscillation
Clock
Remarks: 1. The broken line indicates the case when the interrupt request which has cleared the
standby status is acknowledged.
2. Wait time will be as follows:
• When vectored interrupt service is carried out: 8 to 9 clocks
• When vectored interrupt service is not carried out:
2 to 3 clocks
(b) Clear upon non-maskable interrupt request
The HALT mode is cleared and vectored interrupt service is carried out whether interrupt
acknowledge is enabled or disabled.
331
µPD1615, µPD16F15, µPD1616
(c) Clear upon RESET input
As is the case with normal reset operation, a program is executed after branch to the reset vector
address.
Figure 19-3: HALT Mode Release by RESET Input
Wait
(217/f
: 16.3 ms)
x
HALT
Instruction
RESET
Signal
Oscillation
Stabilization
Wait Status
Operating
Mode
Reset
Period
Operating
Mode
HALT Mode
Oscillation
Oscillation
stop
Oscillation
Clock
Remarks: 1. fx: Main system clock oscillation frequency
2. Values in parentheses apply to operation at fx = 8.0 MHz
Table 19-2: Operation after HALT Mode Release
Release Source
MKxx
PRxx
IE
0
1
0
x
ISP
x
Operation
0
0
0
0
0
1
0
0
1
1
1
x
Next address instruction execution
Interrupt service execution
x
1
Maskable interrupt
request
Next address instruction execution
0
1
x
1
Interrupt service execution
HALT mode hold
x
Non-maskable interrupt
request
-
-
-
-
x
x
x
x
Interrupt service execution
Reset processing
RESET input
x: Don't care.
332
µPD1615, µPD16F15, µPD1616
19.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system
clock.
Cautions: 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-
up resistor to minimize leakage current at the crystal oscillator. Thus, do not use
the STOP mode in a system where an external clock is used for the main system
clock.
2. Because the interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set. Thus, the STOP
mode is reset to the HALT mode immediately after execution of the STOP
instruction. After the wait set using the oscillation stabilization time
select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Table 19-3: STOP Mode Operating Status
STOP mode setting
With subsystem clock
Without subsystem clock
Item
Clock generator
Only main system clock stops oscillation
Operation stops
CPU
Port (output latch)
Status before STOP mode setting is held
16-bit timer /event counter (TM0)
8-bit timer event counter 5 and 6
Operable when TI00 is selected as count clock
Operable when TI50 or TI51 are selected as count clock
Operable when fxt is selected as
Operation stops
Watch timer
count clock
Watchdog timer
A/D converter
Operation stops
Operation stops
Operable at external SCK
Operation stops
Operation stops
Operation stops
Operable
Serial I/F - SIO30
Serial I/F - UART
VAN
Sound generator
External interrupt (INTP0 to INTP2)
LCD
Operation stops
333
µPD1615, µPD16F15, µPD1616
(2) STOP mode release
The STOP mode can be cleared with the following three types of sources.
(a) Release by unmasked interrupt request
An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is
enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
If interrupt acknowledge is disabled, the next address instruction is executed.
Figure 19-4: STOP Mode Release by Interrupt Generation
Wait
STOP
Instruction
(Time set by OSTS)
Standby
Release Signal
Operationg
Mode
Oscillation Stabilization
Wait Status
Operating
Mode
STOP Mode
Oscillation
Oscillation Stop
Oscillation
Clock
Remark:
The broken line indicates the case when the interrupt request which has cleared the
standby status is acknowledged.
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µPD1615, µPD16F15, µPD1616
(b) Release by RESET input
The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is
carried out.
Figure 19-5: Release by STOP Mode RESET Input
Wait
(217/f
: 16.3 ms)
x
STOP
Instruction
RESET
Signal
Oscillation
Stabilization
Wait Status
Operating
Mode
Reset
Period
Operating
Mode
STOP Mode
Oscillation
Oscillation Stop
Oscillation
Clock
Remarks 1. fx: Main system clock oscillation frequency
2. Values in parentheses apply to operation at fx = 5.0 MHz
Table 19-4: Operation after STOP Mode Release
Release Source
MKxx
PRxx
IE
0
1
0
x
ISP
x
Operation
0
0
0
0
0
1
0
0
1
1
1
x
Next address instruction execution
Interrupt service execution
x
1
Maskable interrupt
request
Next address instruction execution
0
1
x
1
Interrupt service execution
STOP mode hold
x
Non-maskable interrupt
request
-
-
-
-
x
x
x
x
Interrupt service execution
Reset processing
RESET input
x: Don’t care.
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Chapter 20 Reset Function
20.1 Reset Function
The following two operations are available to generate the reset signal.
(1) External reset input with RESET pin
(2) Internal reset by watchdog timer overrun time detection
External reset and internal reset have no functional differences. In both cases, program execution
starts at the address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and
each hardware is set to the status as shown in Table 20-1. Each pin has high impedance during reset
input or during oscillation stabilization time just after reset clear.
When a high level is input to the RESET input, the reset is cleared and program execution starts after
17
the lapse of oscillation stabilization time (2 /fx). The reset applied by watchdog timer overflow is
automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization
17
time (2 /fx) (see Figure 20-2 to 20-4).
Cautions: 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. During reset input, main system clock oscillation remains stopped but subsystem
clock oscillation continues.
3. When the STOP mode is cleared by reset, the STOP mode contents are held during
reset input. However, the port pin becomes high-impedance.
Figure 20-1: Block Diagram of Reset Function
Reset
Signal
RESET
Reset Control Circuit
Over-
flow
Interrupt
Function
Watchdog Timer
Stop
Count Clock
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µPD1615, µPD16F15, µPD1616
Figure 20-2: Timing of Reset Input by RESET Input
X1
Oscillation
Stabilization
Time Wait
Reset Period
(Oscillation Stop)
Normal Operation
(Reset Processing)
Normal Operation
RESET
Internal
Reset Signal
Delay
Delay
High Impedance
Port Pin
Figure 20-3: Timing of Reset due to Watchdog Timer Overflow
X1
Reset Period
(Oscillation Stop)
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
Normal Operation
Watchdog
Timer Overflow
Internal
Reset Signal
High Impedance
Port Pin
Figure 20-4: Timing of Reset Input in STOP Mode by RESET Input
X1
STOP Instruction Execution
Oscillation
Stabilization
Time Wait
Stop Status
(Oscillation Stop)
Normal Operation
(Reset Processing)
Reset Period
(Oscillation Stop)
Normal Operation
RESET
Internal
Reset Signal
Delay
Delay
High Impedance
Port Pin
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µPD1615, µPD16F15, µPD1616
Table 20-1: Hardware Status after Reset (1/2)
Hardware
Status after Reset
The contents of reset
vector tables
(0000H and 0001H)
are set
Note 1
Program counter (PC)
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
Note 2
Data memory
Undefined)
RAM
Note 2
General register
Undefined)
Ports 0, 4, 8 to 12
(P0, P4, P8 to P12)
Port (Output latch)
00H
Port mode register (PM0, PM4, PM8 to PM12)
Port function register (PF8 to PF12)
FFH
00H
04H
CFH
0CH
04H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
04H
00H
00H
00H
00H
00H
00H
00H
Processor clock control register (PCC)
Memory size switching register (IMS)
Internal expansion RAM size switching register (IXS)
Oscillation stabilization time select register (OSTS)
Timer register (TM0)
Capture/compare register (CR00, CR01)
Prescaler selection register (PRM0)
Mode control register (TMC0)
Capture/compare control register 0 (CRC0)
Output control register (TOC0)
Timer register (TM50, TM51)
16-bit timer/event
counter 0
Compare register (CR50, CR51)
Clock select register (TLC50, TLC51)
Mode control register (TMC50, TMC51)
Mode register (WTM)
8-bit timer/event
counters 50 and 51
Watch timer
Clock selection register (WDCS)
Mode register (WDTM)
Watchdog timer
PCL clock output
Clock output selection register (CKS)
Control register (SGCR)
Sound generator
Amplitude control register (SGAM)
Buzzer control register (SGBC)
Notes:
1. During reset input or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remains unchanged
after reset.
2. The post-reset status is held in the standby mode.
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µPD1615, µPD16F15, µPD1616
Table 20-1: Hardware Status after Reset (2/2)
Hardware
Status after Reset
Operating mode register 0 (CSIM30)
Shift register 0 (CSIO30)
00H
00H
00H
00H
00H
00H
00H
Operating mode register 1 (CSIM31)
Shift register 1 (CSIO31)
Serial interface
Asynchronous mode register (ASIM0)
Asynchronous status register (ASIS0)
Baudrate generator control register (BRGC0)
Transmit shift register (TXS0)
FFH
Receive buffer register (RXB0)
Mode register (ADM1)
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
Conversion result register (ADCR1)
Input select register (ADS1)
A/D converter
Power fail comparator mode (PFM)
Power fail threshold register (PFT)
Mode register (LCDM)
LCD controller/driver
Control register (LCDC)
Request flag register (IF0L, IF0H, IF1L)
Mask flag register (MK0L, MK0H, MK1L)
Priority specify flag register (PR0L, PR0H, PR1L)
External interrupt rising edge register (EGP)
External interrupt falling edge register (EGN)
UDL clock control register (UDLCCL)
Interrupt
VAN
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µPD1615, µPD16F15, µPD1616
[Memo]
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µPD1615, µPD16F15, µPD1616
Chapter 21 µPD16F15
The µPD16F15 replaces the internal mask ROM of the µPD1615 / µPD1616 with flash memory to which
a program can be written, deleted and overwritten while mounted on the substrate.
Table 21-1 lists the differences among the µPD16F15 and the mask ROM versions.
Table 21-1: Differences among µPD16F15 and Mask ROM Versions
Item
µPD16F15
Mask ROM Versions
Available
None
See data sheet of each product
IC pin
None
Available
VPP pin
Electrical characteristics
Caution: Flash memory versions and mask ROM versions differ in their noise tolerance and
noise emission. If replacing flash memory versions with mask ROM versions when
changing from test production to mass production, be sure to perform sufficient
evaluation with CS versions (not ES versions) of mask ROM versions.
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µPD1615, µPD16F15, µPD1616
21.1 Memory Size Switching Register (IMS)
This register specifies the internal memory size by using the memory size switching register (IMS),
so that the same memory map as on the mask ROM version can be achieved.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets this register to CFH.
Figure 21-1: Memory Size Switching Register Format
After
Reset
Symbol
7
6
5
4
0
3
2
1
0
Address
FFF0H
R/W
R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
Note
ROM3 ROM2 ROM1 ROM0 Internal ROM size selection
1
1
0
1
0
1
0
1
32 Kbytes
60 Kbytes
Other than above
Setting prohibited
RAM2 RAM1 RAM0 Internal high-speed RAM size selection
1
1
0
1024 bytes
Other than above
Setting prohibited
Note:
The values after reset depend on the product (See Table 21-2).
Table 21-2: Values of the Memory Size Switching Register for the Different Devices
Part Number
µPD1615, µPD1616
µPD16F15
Value
C8H
CFH
Caution: When the µPD1615/16F15 and the µPD1616 are used, be sure to set the value of the
IMS register as given in the Table 21-2.
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µPD1615, µPD16F15, µPD1616
21.2 Internal Extension RAM Size Switching Register
The µPD16F15 allow users to define its internal expansion RAM size by using the internal expansion
RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version
with a different internal extension RAM is possible.
The IXS is set by an 8-bit memory manipulation instruction.
RESET signal input sets IXS to 0CH.
Caution: When the µPD1615/µPD16F15 and the µPD1616 are used, be sure to set the value
specified in the Table 21-3 to IXS. Other settings are prohibited.
Figure 21-2: Internal Extension RAM Size Switching Register Format
After
Reset
R/W
W
Symbol
IXS
7
0
6
0
5
0
4
0
3
2
1
0
Address
FFF4H
IXRAM3 IXRAM2
IXRAM1
IXRAM0
0CH
Internal extension RAM
capacity selection
IXRAM3
IXRAM2
IXRAM1
IXRAM0
1
1
0
0
1
1
1
0
512 bytes
1024 bytes
Other than above
Setting prohibited
The value whitch is set in the IXS that has the identical memory map to the mask ROM versions is
given in the Table 21-3.
Table 21-3: Examples of internal Extension RAM Size Switching Register Settings
Relevant Mask ROM Version
µPD1615, µPD1616
µPD16F15
IXS Setting
0BH
0AH
Caution: When the µPD1615/16F15 and the µPD1616 are used, be sure to set the value of the
IXS register as given in the Table 21-3.
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21.3 Flash memory programming
On-board writing of flash memory (with device mounted on target system) is supported.
On-board writing is done after connecting a dedicated flash writer to the host machine and target
system.
Moreover, writingtoflashmemorycanalsobeperformedusingaflashmemorywritingadapterconnected
to the Flash Programmer.
21.3.1 Selection of transmission method
Writing to flash memory is performed using Flashpro and serial communication. Select the transmission
method for writing from Table 21-4. For the selection of the transmission method, a format like the one
shown in Figure 21-3 is used. The transmission methods are selected with the VPP pulse numbers shown
in Table 21-4.
Table 21-4 Transmission Method List
Number of
Channels
Number of
VPP Pulses
Transmission Method
3-wire serial I/O
Pin Used
SI3/P127
1
SO3/P126
1
SCK3/P125
P40 (Serial clock input)
P41(Serial data input)
P42(Serial data input)
RxD0/P123
Pseudo 3-wire serial I/O
UART
1
1
12
8
TxD0/P124
Cautions: 1. Be sure to select the number of Vpp pulses shown in Table 25-3 for the transmission
method.
2. If performing write operations to flash memory with the UART transmission method,
set the main system clock oscillation frequency to 4 MHz or higher.
Figure 21-3: Transmission Method Selection Format
VPP pulses
10 V
VDD
VSS
VDD
VPP
RESET
Flash write mode
VSS
21.3.2 Initialization of the programming mode
When VPP reaches up to 10 V with RESET terminal activated, on-board programming mode becomes
available.
After release of RESET, the programming mode is selected by the number of VPP pulses.
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µPD1615, µPD16F15, µPD1616
21.3.3 Flash memory programming function
Flash memory writing is performed through command and data transmit/receive operations using the
selected transmission method. The main functions are listed in Table 21-5.
Table 21-5: Main Functions of Flash Memory Programming
Function
Description
Detects write stop and transmission synchronization.
Compares entire memory contents and input data.
Deletes the entire memory contents.
Reset
Batch verify
Batch delete
Batch blank check
High-speedwrite
Checks the deletion status of the entire memory.
Performs writing to flash memory according to write start address and number of write data
(bytes).
Continuous write
Performs successive write operations using the data input with high-speed write operation.
Checks the current operation mode and operation end.
Status
Oscillation frequency setting
Delete time setting
Baud rate setting
Silicon signature read
Inputs the resonator oscillation frequency information.
Inputs the memory delete time.
Sets the transmission rate when the UART method is used.
Outputs the device name, memory capacity, and device block information.
21.3.4 Flashpro connection
Connection of Flashpro and µPD16F15 differs depending on communication method (3-wire serial I/
O, UART). Each case of connection shows in Figures 21-4, 21-5 and 21-6.
Figure 21-4: Connection of Flashpro Using 3-Wire Serial I/O Method
Flash Programmer
µPD16F15
PP
PP
V
V
V
DD
DD
V
RESET
RESET
SCK
SO
SCK3
SI3
SI
SO3
GND
V
SS
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µPD1615, µPD16F15, µPD1616
Figure 21-5: Flashpro Connection Using UART Method
Flash Programmer
µPD16F15
PP
V
VPP
VDD
VDD
RESET
SO
RESET
RXD0
TXD0
SI
VSS
GND
Figure 21-6: Flashpro Connection Using Pseudo 3-wire Serial I/O
Flash Programmer
µPD16F15
PP
V
V
V
PP
DD
DD
V
RESET
SCK
SO
RESET
(Serial clock input)
(Serial data input)
(Serial data output)
SI
SS
GND
V
VPP:
10.3 V applied from the on-board programming tool.
RESET:
A RESET is generated and the device is set to the on-board programming mode.
System clock: The CPU clock for the device may be supplied by the on-board program tool. Alternatively
the crystal or ceramic oscillator on the target H/W can be used in the on-board programming
mode. The external system clock has to be connected with the X1 pin on the device.
VDD:
Thepowersupplyforthedevicemaybesuppliedbytheon-boardprogramtool. Alternatively
the power supply on the target H/W can be used in the on-board programming mode.
Ground level VSS.
GND:
SCK:
SI:
Serial clock generated by the on-board programming tool.
Serial data sent by the on-board programming tool.
Serial data sent by the device.
SO:
RXD0:
TXD0:
Serial data sent by the on-board programming tool.
Serial data sent by the device.
21.3.5 Flash programming precautions
• Please make sure that the signals used by the on-board programming tool do not conflict with other
devices on the target H/W.
• A read functionality is not supported because of software protection. Only a verify operation of the
whole Flash EPROM is supported. In verify mode data from start address to final address (EFFFH)
hastobesuppliedbytheprogrammingtool. Thedevicecompareseachdatawithon-chipflashcontent
and replies with a signal for O.K. or not O.K.
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[Memo]
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Chapter 22 Instruction Set
This chapter describes each instruction set of the µPD1615 subseries as list table. For details of
its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL -
Instruction (U12326E).”
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µPD1615, µPD16F15, µPD1616
22.1 Legends Used in Operation List
22.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description
method of the instruction operand identifier (refer to the assembler specifications for detail). When there
are two or more description methods, select one of them. Alphabetic letters in capitals and symbols,
#, !, $ and [ ] are key words and must be described as they are. Each symbol has the following meaning.
• # : Immediate data specification
• ! : Absolute address specification
• $ : Relative address specification
• [ ] : Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label,
be sure to describe the #, !, $, and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names
in parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 22-1: Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbolNote
rp
sfr
sfrp
Special-function register symbol (16-bit manipulatable register even addresses only)Note
saddr
FE20H-FF1FH Immediate data or labels
saddrp
FE20H-FF1FH Immediate data or labels (even address only)
addr16
0000H-FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H-0FFFH Immediate data or labels
addr11
addr5
0040H-007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn
RB0 to RB3
Note:
Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark:
For special-function register symbols, refer to "Table 3-3: Special-Function Register List".
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µPD1615, µPD16F15, µPD1616
22.1.2 Description of “operation” column
A
: A register; 8-bit accumulator
: X register
X
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
AX
BC
DE
HL
PC
SP
: AX register pair; 16-bit accumulator
: BC register pair
: DE register pair
: HL register pair
: Programcounter
: Stack pointer
PSW : Program status word
CY
AC
Z
: Carry flag
: Auxiliary carry flag
: Zero flag
RBS : Register bank select flag
IE : Interrupt request enable flag
NMIS : Non-maskable interrupt servicing flag
( ) : Memory contents indicated by address or register contents in parentheses
XH, XL : Higher 8 bits and lower 8 bits of 16-bit register
: Logical product (AND)
: Logical sum (OR)
: Exclusive logical sum (exclusive OR)
——
: Inverted data
addr16 : 16-bit immediate data or label
jdisp8 : Signed 8-bit data (displacement value)
22.1.3 Description of “flag operation” column
(Blank) : Not affected
0
: Cleared to 0
1
: Set to 1
X
R
: Set/cleared according to the result
: Previously saved value is restored
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µPD1615, µPD16F15, µPD1616
22.2 Operation List
Clock
Flag
Instruction
Group
Mnemonic
Operands
r, #byte
Byte
Operation
Note 1
Note 2
Z
AC CY
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
4
6
–
2
2
4
4
–
–
8
8
–
–
–
4
4
4
4
8
8
6
6
6
6
2
4
–
8
4
4
8
8
8
–
7
7
–
–
5
5
5
5
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
saddr, #byte
sfr, #byte
A, r
Note 3
Note 3
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
9 + n A ← (addr16)
9 + m (addr16) ← A
MOV
7
5
5
PSW ← byte
A ← PSW
x
x
x
x
x
x
PSW, A
PSW ← A
A, [DE]
5 + n A ← (DE)
5 + m (DE) ← A
5 + n A ← (HL)
5 + m (HL) ← A
8-bit data
transfer
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
9 + n A ← (HL + byte)
9 + m (HL + byte) ← A
7 + n A ← (HL + B)
7 + m (HL + B) ← A
7 + n A ← (HL + C)
7 + m (HL + C) ← A
Note 3
–
6
6
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ (sfr)
A, !addr16
A, [DE]
10 + n + m A ↔ (addr16)
6 + n + m A ↔ (DE)
XCH
A, [HL]
6 + n + m A ↔ (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
10 + n + m A ↔ (HL + byte)
10 + n + m A ↔ (HL + B)
10 + n + m A ↔ (HL + C)
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except “r = A”
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
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µPD1615, µPD16F15, µPD1616
Clock
Flag
Instruction
Group
Mnemonic
Operands
rp, #word
Byte
Operation
Note 1
Note 2
Z
AC CY
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
6
8
–
6
6
–
–
4
4
–
10
10
8
rp ← word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
8
16-bit data
transfer
MOVW
8
sfrp, AX
8
sfrp ← AX
Note 3
Note 3
AX, rp
–
AX ← rp
rp, AX
–
rp ← AX
AX, !addr16
!addr16, AX
AX, rp
10 12 + 2n AX ← (addr16)
10 12 + 2m (addr16) ← AX
Note 3
Note 4
XCHW
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
–
–
8
–
–
5
AX × rp
A, #byte
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
r, A
r, CY ← r + A
A, saddr
A, CY ← A + (saddr)
ADD
A, !addr16
A, [HL]
9 + n A, CY ← A + (addr16)
5 + n A, CY ← A + (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
9 + n A, CY ← A + (HL + byte)
9 + n A, CY ← A + (HL + B)
9 + n A, CY ← A + (HL + C)
8-bit
operation
–
8
–
–
5
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
saddr, #byte
A, r
Note 4
r, A
r, CY ← r + A + CY
A, saddr
A, CY ← A + (saddr) + CY
ADDC
A, !addr16
A, [HL]
9 + n A, CY ← A + (addr16) + CY
5 + n A, CY ← A + (HL) + CY
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A, CY ← A + (HL + byte) + CY
9 + n A, CY ← A + (HL + B) + CY
9 + n A, CY ← A + (HL + C) + CY
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
353
µPD1615, µPD16F15, µPD1616
Clock
Flag
Instruction
Group
Mnemonic
Operands
A, #byte
Byte
Operation
A, CY ← A – byte
Note 1
Note 2
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
–
8
–
–
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr), CY ← (saddr) – byte
A, CY ← A – r
Note 3
Note 3
Note 3
r, A
r, CY ← r – A
A, saddr
A, !addr16
A, [HL]
A, CY ← A – (saddr)
SUB
9 + n A, CY ← A – (addr16)
5 + n A, CY ← A – (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A, CY ← A – (HL + byte)
9 + n A, CY ← A – (HL + B)
9 + n A, CY ← A – (HL + C)
–
8
–
–
5
A, CY ← A – byte – CY
(saddr), CY ← (saddr) – byte – CY
A, CY ← A – r – CY
r, A
r, CY ← r – A – CY
A, saddr
A, !addr16
A, [HL]
A, CY ← A – (saddr) – CY
8-bit
SUBC
operation
9 + n A, CY ← A – (addr16) – CY
5 + n A, CY ← A – (HL) – CY
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A, CY ← A – (HL + byte) – CY
9 + n A, CY ← A – (HL + B) – CY
9 + n A, CY ← A – (HL + C) – CY
–
8
–
–
5
A ← A byte
(saddr) ← (saddr) byte
A ← A
r ← r
r
r, A
A
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
AND
9 + n A ← A (addr16)
5 + n A ← A [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A ← A [HL + byte]
9 + n A ← A [HL + B]
9 + n A ← A [HL + C]
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
354
µPD1615, µPD16F15, µPD1616
Clock
Flag
Instruction
Group
Mnemonic
Operands
A, #byte
Byte
Operation
Note 1
Note 2
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
–
8
–
–
5
A ← A byte
saddr, #byte
A, r
(saddr) ← (saddr) byte
Note 3
Note 3
Note 3
A ← A
r ← r
r
r, A
A
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
OR
9 + n A ← A (addr16)
5 + n A ← A (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A ← A (HL + byte)
9 + n A ← A (HL + B)
9 + n A ← A (HL + C)
–
8
–
–
5
A ← A byte
(saddr) ← (saddr) byte
A ← A
r ← r
r
r, A
A
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
8-bit
XOR
operation
9 + n A ← A (addr16)
5 + n A ← A (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A ← A (HL + byte)
9 + n A ← A (HL + B)
9 + n A ← A (HL + C)
–
8
–
–
5
A – byte
(saddr) – byte
A – r
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
r, A
r – A
A, saddr
A, !addr16
A, [HL]
A – (saddr)
CMP
9 + n A – (addr16)
5 + n A – (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A – (HL + byte)
9 + n A – (HL + B)
9 + n A – (HL + C)
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
355
µPD1615, µPD16F15, µPD1616
Instruction
Group
Mnemonic
Operands
AX, #word
Byte
Operation
AX, CY ← AX + word
x
x
x
ADDW
SUBW
CMPW
MULU
DIVUW
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
6
6
–
–
–
–
–
–
6
–
6
–
–
–
–
–
–
x
x
x
x
x
x
16-bit
AX, #word
AX, CY ← AX – word
AX – word
operation
AX, #word
6
X
16
25
2
AX ← A x X
Multiply/
divide
C
AX (Quotient), C (Remainder) ← AX ÷ C
r ← r + 1
r
x
x
x
x
x
x
x
x
INC
saddr
r
4
(saddr) ← (saddr) + 1
r ← r – 1
Increment/
decrement
2
DEC
saddr
rp
4
(saddr) ← (saddr) – 1
rp ← rp + 1
INCW
DECW
ROR
4
rp
4
rp ← rp – 1
A, 1
A, 1
A, 1
A, 1
2
(CY, A7 ← A0, Am – 1 ← Am) x 1 time
(CY, A0 ← A7, Am + 1 ← Am) x 1 time
(CY ← A0, A7 ← CY, Am – 1 ← Am) x 1 time
(CY ← A7, A0 ← CY, Am + 1 ← Am) x 1 time
x
x
x
x
ROL
2
RORC
ROLC
2
2
Rotate
A3 – 0 ← (HL)3 – 0, (HL)7 – 4 ← A3 – 0,
(HL)3 – 0 ← (HL)7 – 4
ROR4
[HL]
[HL]
2
2
2
2
10
10
4
12 + n + m
A3 – 0 ← (HL)7 – 4, (HL)3 – 0 ← A3 – 0,
(HL)7 – 4 ← (HL)3 – 0
ROL4
12 + n + m
Decimal Adjust Accumulator after
Addition
ADJBA
ADJBS
–
–
x
x
x
x
x
x
BCD
adjust
Decimal Adjust Accumulator after
Subtract
4
CY, saddr.bit
CY, sfr.bit
3
3
2
3
2
3
3
2
3
2
6
–
4
–
6
6
–
4
–
6
7
7
–
7
CY ← (saddr.bit)
CY ← sfr.bit
x
x
x
x
x
CY, A.bit
CY ← A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
CY ← PSW.bit
Bit
7 + n CY ← (HL).bit
MOV1
manipu-
late
8
8
–
8
(saddr.bit) ← CY
sfr.bit ← CY
A.bit, CY
A.bit ← CY
PSW.bit, CY
[HL].bit, CY
PSW.bit ← CY
x
x
8 + n + m (HL).bit ← CY
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
356
µPD1615, µPD16F15, µPD1616
Clock
Flag
Instruction
Group
Mnemonic
Operands
CY, saddr.bit
Byte
Operation
Note 1
Note 2
Z
AC CY
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
6
–
4
–
6
6
–
4
–
6
6
–
4
–
6
4
–
4
–
6
4
–
4
–
6
2
2
2
7
7
–
7
CY ← CY (saddr.bit)
CY ← CY sfr.bit
CY ← CY A.bit
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
AND1
CY ← CY PSW.bit
7 + n CY ← CY (HL).bit
7
7
–
7
CY ← CY (saddr.bit)
CY ← CY sfr.bit
CY ← CY A.bit
OR1
CY ← CY PSW.bit
7 + n CY ← CY (HL).bit
7
7
–
7
CY ← CY (saddr.bit)
CY ← CY sfr.bit
CY ← CY A.bit
XOR1
SET1
CLR1
Bit
manipu-
late
CY ← CY PSW.bit
7 + n CY ← CY (HL).bit
6
8
–
6
(saddr.bit) ← 1
sfr.bit ← 1
A.bit
A.bit ← 1
PSW.bit
[HL].bit
PSW.bit ← 1
x
x
x
x
x
8 + n + m (HL).bit ← 1
saddr.bit
sfr.bit
6
8
–
6
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
PSW.bit ← 0
x
8 + n + m (HL).bit ← 0
SET1
CLR1
NOT1
CY
–
–
–
CY ← 1
CY ← 0
CY ← CY
1
0
x
CY
CY
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
357
µPD1615, µPD16F15, µPD1616
Clock
Flag
Instruction
Group
Mnemonic
Operands
Byte
3
Operation
,(SP–2)←(PC+3) ,
Note 1
Note 2
Z
AC CY
(SP–1)← (PC+3)
H
L
CALL
!addr16
!addr11
7
5
–
PC addr16, SP
←
← SP – 2
(SP – 1) ← (PC + 2)
H
, (SP – 2) ← (PC + 2)
addr11,
L
L
,
CALLF
CALLT
2
1
–
–
PC15 – 11
←
00001, PC10 – 0 ←
SP
← SP – 2
(SP – 1) ← (PC + 1)
H
, (SP – 2) ← (PC + 1)
,
PCH
PCL
←
←
(00000000, addr5 + 1),
(00000000, addr5),
[addr5]
6
SP
← SP – 2
Call/return
(SP – 1)
(SP – 3)
←
←
PSW, (SP – 2)
(PC + 1)L, PCH
←
←
(PC + 1)H,
(003FH),
BRK
RET
1
1
1
6
6
6
–
–
–
PCL
←
(003EH), SP
← SP – 3, IE ← 0
PCH
←
(SP + 1), PCL
←
(SP),
SP
←
SP + 2
(SP + 1), PCL
PCH
←
←
←
(SP),
RETI
PSW
NMIS
←
(SP + 2), SP
0
SP + 3,
R
R
R
R
R
←
PCH
←
(SP + 1), PCL
(SP + 2), SP
←
←
(SP),
RETB
PUSH
1
1
1
1
1
6
2
4
2
4
–
–
–
–
–
R
PSW
←
SP + 3
PSW
rp
(SP – 1)
(SP – 1)
←
PSW, SP
←
SP – 1
←
rpH, (SP – 2)
←
rpL,
SP
←
SP – 2
PSW
rp
PSW
←
(SP), SP
←
SP + 1
R
R
R
Stack
manipu-
late
POP
rpH
SP
←
(SP + 1), rpL
SP + 2
← (SP),
←
←
←
←
←
←
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
4
2
2
3
2
2
2
2
2
2
–
–
–
6
6
8
6
6
6
6
10
8
SP
SP
AX
PC
PC
word
MOVW
AX
8
SP
–
addr16
Uncondi-
tional
BR
–
PC + 2 + jdisp8
branch
–
PCH ← A, PCL ← X
BC
$addr16
$addr16
$addr16
$addr16
–
PC
PC
PC
PC
←
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
BNC
BZ
–
←
←
←
Conditional
branch
–
BNZ
–
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
358
µPD1615, µPD16F15, µPD1616
Instruction
Group
Mnemonic
Operands
Byte
Operation
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
3
4
3
3
3
4
4
3
4
3
8
–
9
11
–
PC ← PC + 3 + jdisp8 if(saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSW.bit = 1
BT
8
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
–
9
10
10
–
11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 1
11
11
–
PC ← PC + 4 + jdisp8 if(saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
BF
8
PSW.bit, $addr16
[HL].bit, $addr16
–
11
10
11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 0
PC ← PC + 4 + jdisp8
Conditional
branch
saddr.bit, $addr16
4
10
12
if(saddr.bit) = 1
then reset(saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
4
3
4
3
2
2
3
–
8
12
then reset sfr.bit
BTCLR
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
–
PC ← PC + 4 + jdisp8 if PSW.bit = 1
–
12
x
x
x
then reset PSW.bit
PC ← PC + 3 + jdisp8 if (HL).bit = 1
10
6
12 + n + m
then reset (HL).bit
B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
–
–
C ← C –1, then
DBNZ
C, $addr16
6
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
saddr. $addr16
RBn
8
10
SEL
NOP
EI
2
1
2
2
2
2
4
2
–
–
6
6
–
–
6
6
–
–
RBS1, 0 ← n
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
CPU
control
DI
HALT
STOP
Set STOP Mode
Notes:
1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks: 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC
register.
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
359
µPD1615, µPD16F15, µPD1616
22.3 Instructions Listed by Addressing Type
(1) 8-bitinstructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
360
µPD1615, µPD16F15, µPD1616
SecondOperand
[HL + byte]
#byte
A
rNote
sfr saddr !addr16 PSW [DE] [HL] [HL+B] $addr16
1
None
First Operand
A
[HL+C]
ADD
ADDC
SUB
SUBC
AND
OR
MOV MOV MOV MOV MOV MOV MOV MOV
ROR
XCH XCH XCH XCH
XCH XCH XCH
ADD ADD
ROL
ADD
ADDC
SUB
SUBC
AND
OR
ADD ADD
ADDC ADDC
SUB SUB
SUBC SUBC
AND AND
RORC
ROLC
ADDC ADDC
SUB SUB
SUBC SUBC
AND AND
XOR
CMP
OR
OR
OR
OR
XOR
CMP
XOR XOR
CMP CMP
XOR XOR
CMP CMP
r
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
sfr
DBNZ
DBNZ
MOV MOV
saddr
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL + byte]
[HL + B]
MOV
[HL + C]
X
C
MULU
DIVUW
Note:
Except r = A
361
µPD1615, µPD16F15, µPD1616
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
SecondOperand
#word
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
1st Operand
AX
ADDW
SUBW
CMPW
MOVW
XCHW
MOVW
MOVW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note:
Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
SecondOperand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
CLR1
BF
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
362
µPD1615, µPD16F15, µPD1616
(4) Call/instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
SecondOperand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
BR
First Operand
Basic instruction
BR
CALL
BR
BC
BNC
BZ
BNZ
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
363
µPD1615, µPD16F15, µPD1616
[Memo]
364
µPD1615, µPD16F15, µPD1616
Appendix A Development Tools
The following development tools are available for the development of systems that employ the
µPD1615 Subseries.
Figure A-1 shows the development tool configuration.
Figure A-1: Development Tool Configuration
Embedded Software
Language Processing Software
• Assembler package
• C compiler package
• C library source file
• System simulator
• Integrated debugger
• Device file
• Realtime OS, OS
• Fuzzy inference development
support system
Host machine
(PC or EWS)
Interface adapter
Flash memory
Flash writer
In-circuit emulator
CPU core board
I/O board
Probe board
Flash memory
write adapter
On-chip flash
memory version
Emulation probe
Conversion socket or
conversion adapter
Target system
365
µPD1615, µPD16F15, µPD1616
A.1 Language Processing Software
RA78K/0
This assembler converts programs written in mnemonics into an object code
Assembler Package
executable with a microcomputer.
Further, this assembler is provided with functions capable of automatically creating
symbol tables and branch instruction optimization.
This assembler is used in combination with an optional device file (DF780949).
Part Number: µSxxxxRA78K0
CC78K/0
This compiler converts programs written in C language into object code executable
with a microcomputer.
C Compiler Package
This compiler is used in combination with an optional assembler package (RA78K/0)
and device file (1615).
Part Number: µSxxxxCC78K0
Note 1, 2
DF1615
This file contains information peculiar to the device.
Device File
This file is used in combination with the RA78K/0, CC78K/0, SM78K0, and ID78K0.
Part Number: µSxxxxDF1615
CC78K/0-L
This is a source program of functions configuring the object library included in the C
compiler package (CC78K/0).
C Library Source File
It is required for matching the object library included in the CC78K/0 with to the
customer’s specifications.
Part Number: µSxxxxCC78K0-L
Notes:
1. Used in common with RA78K/0, CC78K0, SM78K0 and ID78K0.
2. Underdevelopment
Remark:
xxxx in the part number differs depending on the host machine and OS used.
µSxxxxRA78K0
µSxxxxCC78K0
µSxxxxDF780948
µSxxxxCC78K0-L
xxxx
Host Machine
PC-9800 Series
OS
Supply Medium
3.5-inch 2HD
5A13
5A10
7B13
7B10
3H15
3P16
3K15
3M15
MS-DOS
Note
(Ver.3.30 to Ver.6.2
See A.4
)
5-inch 2HD
IBM PC/AT or compatible
3.5-INCH 2HD
5-inch 2HD
TM
TM
HP9000 Series 300
HP-UX
(rel.7.05B)
Cartrige tape (QIC-24)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
TM
HP9000 Series 700
HP-UX (rel.9.01)
TM
TM
SPARCstation
SunOS
(rel.4.1.1)
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
Note:
The task swap function is not supported by the software listed above, although it is provided
in MS-DOS version 5.0 and later.
366
µPD1615, µPD16F15, µPD1616
A.2 Flash Memory Writing Tools
Dedicated flash writer for microcontrollers with on-chip flash memory.
Flashpro is a product of Naitoudensei Machida Seisakusho, Co., Ltd.
Flashpro
Flash Writer
µPD1615 Subseries flash memory writing adapter used connected to Flashpro.
These are products of Naitoudensei Machida Seisakusho, Co., Ltd.
• FA-80GC-SL: 80-pin plastic QFP (14 x 14 mm)
Flash memory writing adapter
FA-80GC-SL
A.3 Debugging Tools
A.3.1 Hardware
In-circuit emulator serves to debug hardware and software when developing
application systems using the 78K/0 Series. It corresponds to integrated debugger
ID78K0. This emulator is used in combination with an emulation probe an
interface adapter for connection to a host mashine.
IE-78001-R-A Note
In-Circuit Emulator
IE-70000-PC-IF-C
Interface Adapter
This adapter is required when using an IBM PC/AT or compatible as the IE-
780000-SL host mashine.
IE-78K/0-NS-P04 Note
I/O Board
This board is used to perform emulation of device specific peripheral hardware.
This board is used in combination with an in-circuit emulator and probe board.
IE-1615-NS-EM4
Probe Board
This board is used to perform pin connection changes.
IE-78K0-R-EX1
Probe Extender Board
This board is used for a pin connection change betwwen the probe board and the
probe.
This probe is used to connect the in-circuit emulator and the target system. It is
for 80-pin plastic QFP. An 80-pin conversion socket is included to facilitate target
system development.
EP-78230GC-R
Emulation Probe
This conversion socket is used to connect a target system substrate designed to
allow mounting of the 80-pin plastic QFP and the EP-78230GC-R.
EV-9200GC-80
Note:
Under development.
367
µPD1615, µPD16F15, µPD1616
A.3.2 Software (1/2)
SM78K0
This system simulator is used to perform debugging at C source level or assembler
System Simulator
level while simulating the operatin of the target system on a host machine.
The SM78K0 operates on Windows.
Use of the SM78K0 allows the execution of application logical testing and
performance testing on an independent basis from hardware development without
having to use an in-circuit emulator, thereby providing higher development efficiency
and software quality.
Part Number: µSxxxxSM78K0-L
Remark:
xxxx in the part number differs depending on the host machine and OS used.
µSxxxxSM78K0
xxxx
Host Machine
PC-9800 Series
OS
Supply Medium
3.5-inch 2HD
Note
(Ver.3.30 to Ver.6.2
MS-DOS
) +
AA13
AB13
BB13
Windows (Ver. 3.0 to Ver. 3.1)
IBM PC/AT and compatible
(Windows Japanese version)
See A.4
3.5-inch 2HC
3.5-inch 2HC
IBM PC/AT and compatible
(Windows English version)
Note:
1. The task swap funtion is not supported by the software listed above, although it is
provided in MS-DOS version 5.0 and later.
2. The system simulator does not support the µPD1615 subseries.
368
µPD1615, µPD16F15, µPD1616
A.3.2 Software (2/2)
ID78K0
This is a control program used to debug the 78K/0 Series.
Integrated Debugger
The graphical user interfaces employed are Windows for personal computers and
OSF/Motif for EWSs, offering the standard appearance and operability typical of
these interfaces. Further, debugging functions supporting C language are rein-
forced, and the trace result can be displayed in C language level by using a window
integrating function that associates the source program, disassemble display, and
memory display with the trace result. In addition, it can enhance the debugging
efficiency of a program using a real-time OS by incorporating function expansion
modules such as a task debugger and system performance analyzer.
This debugger is used in combination with an optional device file.
Part Number: µSxxxxID78K0
Notes 1, 2
DF1615
File containing information peculiar to the device.
Device File
Used in combination with optional RA78K/0, CC78K/0, SM78K0, or ID78K0.
Part Number: µSxxxxDF1615.
Notes:
1. The DF1615 can be used in conjunction with the RA78K/0, CC78K/0, SM78K0 and
ID78K0.
2. Under development.
Remark:
xxxx in the part number differs depending on the host machine and OS used.
µSxxxxID78K0
µSxxxxDF1615
xxxx
Host Machine
PC-9800 Series
OS
Supply Medium
3.5-inch 2HD
(Ver.3.30toVer.6.2Note)+
MS-DOS
AA13
AB13
BB13
Windows (Ver. 3.1)
IBM PC/AT or compatible
(Japanese Windows)
See A.4
3.5-inch 2HC
3.5-inch 2HC
IBM PC/AT or compatible
(English Windows)
3P16
3K15
3K13
3R16
3R13
3M15
HP9000 Series 700
SPARCstation
HP-UX (rel.9.01)
SunOS (rel.4.1.1)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
3.5-inch 2HC
TM
TM
NEWS
(RISC)
NEWS-OS
(6.1x)
1/4 inch CGMT
3.5-inch 2HC
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
Cartridge tape (QIC-24)
Note:
The task swap function is not supported by the software listed above, although it is provided
in MS-DOS version 5.0 and later.
369
µPD1615, µPD16F15, µPD1616
A.4 OS for IBM PC
The following OSs for IBM PCs are supported.
To operate SM78K0, ID78K0, and FE9200 (see B.2 Fuzzy Inference Development Support System),
Windows (Ver. 3.0 to Ver. 3.1) is necessary.
OS
Version
PC DOS
Ver. 5.02 to Ver. 6.3
Note
Note
J6.1/V
to J6.3V
TM
Note
IBM DOS
MS-DOS
J5.02/V
Ver. 5.0 to Ver. 6.22
Note
Note
5.0/V
to 6.2/V
Note:
Caution:
Only English mode is supported.
Although Ver. 5.0 and above have a task swapping function, this function cannot be
used with this software.
370
µPD1615, µPD16F15, µPD1616
A.5 Development Environment when Using IE-78001-R-A
When using the IE-78001-R-A as the in-circuit emulator, the following debugging tools are required.
In-circuit emulator is used to debug hardware and software when an application
IE-78001-R-A
In-Circuit Emulator
systems using the 78K/0 Series is developed. It suports the integrated debugger
ID78K0. This emulator is used in combination with an emulation probe and an
interface adapter that connects the emulator with the host mashine..
IE-70000-98-IF-B
IE-70000-98N-IN
IE-70000-PC-IF-C
Interface Adapter
See A.3.1 Hardware
Adapter cable necessary when using an EWS as the host mashine of the IE-
780000-R-A. This cable is connected to the board in the IE-780000-R-A. As
E-78000-R-SV3
Interface Adapter
Ethernet TM, 10Base-5 is supported. If other methods are used, a commercially
available conversion adapter is necessary.
IE-78K/0-NS-P04
I/O Board
IE-1615-NS-EM4
Probe Board
IE-78K0-R-EX1
Probe Extender Board
EP-78230GC-R
Emulation Probe
See also A.3.1 Hardware
EV-9200GC-80
371
µPD1615, µPD16F15, µPD1616
[Memo]
372
µPD1615, µPD16F15, µPD1616
Appendix B Embedded Software
For efficient development and maintenance of the µPD1615 Subseries, the following embedded
software products are available.
373
µPD1615, µPD16F15, µPD1616
B.1 Real-Time OS (1/2)
RX78K/0
RX78K/0 is a real-time OS conforming with the µITRON specifications.
Real-time OS
Tool (configurator) for generating nucleus of RX78K/0 and plural information tables
is supplied.
Used in combination with an optional assembler package (RA78K/0) and device file.
Part number: µSxxxxRX78013-∆∆∆∆
Caution:
Remark:
When purchasing the RX78K/0, fill in the purchase application form in advance and
sign the User Agreement.
xxxx and ∆∆∆ in the part number differ depending on the host machine and OS used.
µSxxxxMX78013-∆∆∆∆
∆ ∆ ∆ ∆
Product Outline
Evaluation object
Upper limit of mass-production quantity
Do not use for mass-produced products.
001
100K
001M
010M
S01
Object for mass-produced product
0.1 million units
1 million units
10 million units
Source program
Host Machine
Source program for mass-produced object
xxxx
5A13
5A10
7B13
7B10
3H15
3P16
3K15
3M15
OS
Supply Medium
3.5-inch 2HD
PC-9800 Series
MS-DOS
Note
(Ver. 3.30 to Ver.6.2
)
5-inch 2HD
IBM PC/AT and compatible
See A.4.
3.5-inch 2HC
5-inch 2HC
HP9000 Series 300
HP9000 Series 700
SPARCstation
HP-UX (rel.7.05B)
HP-UX (rel.9.01)
SunOS (rel.4.1.1)
EWS-UX/V (rel.4.0)
Cartrige tape (QIC-24)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
EWS4800 Series (RISC)
Note:
The task swap function is not supported by the software listed above, although it is provided
in MS-DOS version 5.0 and later.
374
µPD1615, µPD16F15, µPD1616
B.1 Real-Time OS (2/2)
MX78K0
OS
µTRON specification subset OS. Nucleus of MX78K0 is supplied.
This OS performs task management, event management, and time management.
It controls the task execution sequence for task management and selects the task
to be executed next.
Part number: µSxxxxMX78K0-∆∆∆
Remark:
xxxx and ∆∆∆ in the part number differ depending on the host machine and OS used.
µSxxxxMX78K0-∆∆∆
∆ ∆ ∆
001
xx
Product Outline
Evaluation object
Note
Use for trial product.
Object for mass-produced product
Source program
Use for mass-produced product.
S01
Can be purchased only when object for
mass-produced product is purchased.
xxxx
5A13
5A10
7B13
7B10
3H15
3P16
3K15
3M15
Host Machine
OS
Supply Medium
3.5-inch 2HD
PC-9800 Series
MS-DOS
Note
(Ver. 3.30 to Ver.6.2
)
5-inch 2HD
IBM PC/AT and compatible
See A.4.
3.5-inch 2HC
5-inch 2HC
HP9000 Series 300
HP9000 Series 700
SPARCstation
HP-UX (rel.7.05B)
HP-UX (rel.9.01)
SunOS (rel.4.1.1)
EWS-UX/V (rel.4.0)
Cartrige tape (QIC-24)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
EWS4800 Series (RISC)
Note:
The task swap function is not supported by the software listed above, although it is provided
in MS-DOS version 5.0 and later.
375
µPD1615, µPD16F15, µPD1616
B.2 Fuzzy Inference Development Support System
FE9000/FE9200
Program that supports input, edit, and evaluation (simulation) of fuzzy knowledge
Fuzzy knowledge data creation tool
data (fuzzy rule and membership function).
FE9200 works on Windows.
Part number: µSxxxxFE9000 (PC-9800 Series)
µSxxxxFE9200 (IBM PC/AT and compatible machines)
FT9080/FT9085
Translator
Program that translates fuzzy knowledge data obtained by using fuzzy knowledge
data creation tool into assembler source program for RA78K0.
Part number: µSxxxxFT9080 (PC-9800 Series)
µSxxxxFT9085 (IBM PC/AT and compatible machines)
FI78K0
Program that executes fuzzy inference. Executes fuzzy inference when linked with
Fuzzy inference module
fuzzy knowledge data translated by translator.
Part number: µSxxxxFI78K0 (PC-9800 Series, IBM PC/AT and compatible
machines)
FD78K0
Support software for evaluation and adjustment of fuzzy knowledge data by using
Fuzzy inference debugger in-circuit emulator and at hardware level.
Part number: µSxxxxFD78K0 (PC-9800 Series, PC/AT and compatible machines)
Remark:
xxxx in the part number differs depending on the host machine and the OS used.
µSxxxxFE9000
µSxxxxFT9080
µSxxxxFI78K0
µSxxxxFD78K0
xxxx
5A13
5A10
Host machine
PC-9800 Series
OS
Supply media
3.5" 2HD
5" 2HD
MS-DOS
(Ver. 3.30 to Ver. 6.2
Note
)
Note:
MS-DOS Ver. 5.0 and later have the task swap function, but this function cannot be used
for the above software.
µSxxxxFE9200
µSxxxxFT9085
µSxxxxFI78K0
µSxxxxFD78K0
xxxx
7B13
7B10
Host machine
IBM PC/AT and compatible
machines
OS
Supply media
3.5" 2HC
5" 2HC
See A.4.
376
µPD1615, µPD16F15, µPD1616
[Memo]
377
µPD1615, µPD16F15, µPD1616
Appendix C Register Index
C.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D conversion result register 1 (ADCR1) … 186
A/D converter mode register (ADM1) … 188
Analog input channel specification register (ADS1) … 189
Asynchronous serial interface mode register (ASIM0) … 212, 213, 216, 217
Asynchronous serial interface status register (ASIS0) … 214, 218
[B]
Baud rate generator control register (BRGC0) … 214, 216, 219
[C]
Capture/compare control register (CRC0) … 113, 116, 120, 122, 123, 125, 129, 133
Capture/compare register 00 (CR00) … 111, 129
Capture/compare register 01 (CR01) … 112, 126
Clock output selection register (CKS) … 182
[D]
D/A converter mode register (DAM0) … 199
[E]
8-bit compare register 50 (CR50) … 148
8-bit compare register 51 (CR51) … 148
8-bit counter 50 (TM50) … 144, 145, 146, 158
8-bit counter 51 (TM51) … 144, 145, 146, 158
8-bit timer mode control register 50 (TMC50) … 149, 154
8-bit timer mode control register 51 (TMC51) … 150, 154
External interrupt falling edge register (EGN) … 313, 317
External interrupt rising edge register (EGP) … 313, 317
[I]
Internal extension RAM size switching register (IXS) ... 341
Interrupt mask flag register 0H (MK0H) … 313, 315
Interrupt mask flag register 0L (MK0L) … 313, 315
Interrupt mask flag register 1L (MK1L) … 313, 315
Interrupt request flag register 0H (IF0H) … 313, 314
Interrupt request flag register 0L (IF0L) … 313, 314
Interrupt request flag register 1L (IF1L) … 313, 314
[L]
LCD display mode register (LCDM) ... 334, 345
LCD display control register (LCDC) ... 335
378
µPD1615, µPD16F15, µPD1616
M]
Memory size switching register (IMS) … 382, 406
[O]
Oscillation stabilization time selection register (OSTS) … 331
[P]
Port 0 (P0) … 81
Port 1 (P1) … 83
Port 4 (P4) … 84
Port 8 (P8) … 85
Port 9 (P9) … 86
Port 10 (P10) … 87
Port 11 (P11) … 88
Port 12 (P12) … 89
Port function register 8 (PF8) … 90, 92
Port function register 9 (PF9) … 90, 92
Port function register 10 (PF10) … 90, 92
Port function register 11 (PF11) … 90, 92
Port function register 12 (PF12) … 90, 92, 117, 183
Port mode register 0 (PM0) … 90, 91, 113, 153
Port mode register 4 (PM4) … 90, 91
Port mode register 8 (PM8) … 90, 91
Port mode register 9 (PM9) … 90, 91
Port mode register 10 (PM10) … 90, 91
Port mode register 11 (PM11) … 90, 91
Port mode register 12 (PM12) … 90, 91, 117, 183
Power-fail compare mode register (PFM) ... 190
Power-fail compare threshold value register (PFT) ... 190
Prescaler selection register (PRM0) … 113, 118
Priority specify flag register 0H (PR0H) … 313, 316
Pirority specify flag register 0L (PR0L) … 313, 316
Priority specify flag register 1L (PR1L) … 313, 316
Processor clock control register (PCC) … 97
Program status word (PSW) … 313, 318
[R]
Receive buffer register (RXB0) … 211
Receive shift register (RXS0) … 211
379
µPD1615, µPD16F15, µPD1616
[S]
Serial I/O shift register 30 (SIO30) … 203, 204, 208
Serial operation mode register 30 (CSIM30) … 205, 206, 207
16-bit timer mode control register (TMC0) … 113, 114, 120, 122, 123, 125, 129, 133
16-bit timer output control register (TOC0) … 113, 117, 122, 133
16-bit timer register (TM0) … 109
Sound generator control register (SGCR) ... 303
Sound generator buzzer control register (SGBR) ... 304, 305
Sound generator amplitude register (SGAM) ... 306
Successive approximation register (SAR) ... 186
[T]
Timer clock selection register 50 (TCL50) … 149
Timer clock selection register 51 (TCL51) … 150
Transmit shift register (TXS0) … 211
[V]
VAN UART Rank0 Transmission Register (RK0_REG) … 244
VAN UART In Frame Response Register (IFR_REG) … 245, 246
VAN UART Control Register (CTRL_REG) … 247, 248
VAN UART Configuration Register (CONF_REG) … 250
VAN UART Diagnosis Control Register (DIAG_CTRL_REG) … 253
VAN UART Mask1 register (MSK1_MSB_REG ) … 256
VAN UART Mask2 register (MSK2_MSB_REG) … 258
VAN UART Mask1 register ( MSK1_LSB_REG) … 256
VAN UART Mask2 register (MSK2_LSB_REG) … 258
VAN UART Acceptance Code 1 register (AC1_MSB_REG) … 257
VAN UART Acceptance Code 1 register ( AC1_LSB_REG) … 257
VAN UART Acceptance Code 2 Register (AC2_MSB_REG) … 259
VAN UART Acceptance Code 2 Register (AC2_LSB_REG) … 259
VAN UART Acceptance Code 3 Register (AC3_MSB_REG) … 259
VAN UART Acceptance Code 3 Register (AC3_LSB_REG) … 259
VAN UART Acceptance Code 4 Register (AC4_MSB_REG) … 259
VAN UART Acceptance Code 4 Register (AC4_LSB_REG) … 259
VAN UART Receive register (REC_REG) … 262
VAN UART Diagnosis Status Register (DIAG_STAT_REG) … 263
VAN UART Interrupt enable register (INT_ENABLE_REG) … 264
VAN clock selection register (UDLCCL) … 265
VAN UART Status Register (STAT_REG) … 260
[W]
Watch timer mode control register (WTM) … 169
Watchdog timer clock selection register (WDCS) … 175
Watchdog timer mode register (WDTM) … 176
380
µPD1615, µPD16F15, µPD1616
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
ADCR1 : A/D conversion result register 1
ADM1 : A/D converter mode register
ADS1
: Analog input channel specification register
ASIM0 : Asynchronous serial interface mode register
ASIS0 : Asynchronous serial interface status register
BRGC0 : Baud rate generator control register
CKS
: Clock output selection register
: Capture/compare register 00
: Capture/compare register 01
: 8-bit compare register 50
: 8-bit compare register 51
CR00
CR01
CR50
CR51
CRC0 : Capture/compare control register
CSIM30 : Serial operation mode register 0
DAM0 : D/A converter mode register
EGN
EGP
IF0H
IF0L
IF1L
IMS
: External interrupt falling edge enable register
: External interrupt rising edge enable register
: Interrupt request flag register 0H
: Interrupt request flag register 0L
: Interrupt request flag register 1L
: Memory size switching register
IXS
: Internal extension RAM size switching register
: LCD display control register
LCDC
LCDM : LCD display mode register
MK0H : Interrupt mask flag register 0H
MK0L
MK1L
: Interrupt mask flag register 0L
: Interrupt mask flag register 1L
OSTS : Oscillation stabilization time selection register
381
µPD1615, µPD16F15, µPD1616
P0
: Port 0
P1
: Port 1
P4
: Port 4
P8
: Port 8
P9
: Port 9
P10
: Port 10
P11
: Port 11
P12
: Port 12
PCC
PF8
PF9
PF10
PF11
PF12
PFM
PFT
PM0
PM4
PM8
PM9
PM10
PM11
PM12
PR0H
PR0L
PR1L
: Processor clock contrtol register
: Port function register 8
: Port function register 9
: Port function register 10
: Port function register 11
: Port function register 12
: Power-fail compare mode register
: Power-fail compare threshold value register
: Port mode register 0
: Port mode register 4
: Port mode register 8
: Port mode register 9
: Port mode register 10
: Port mode register 11
: Port mode register 12
: Priority specify flag register 0H
: Priority specify flag register 0L
: Priority specify flag register 1L
PRM0 : Prescaler mode register 0
PSW
RXB0
RXS0
: Program status word
: Receive buffer register
: Receive shift register
382
µPD1615, µPD16F15, µPD1616
SAR
: Successive approximation register
SGAM : Sound generator amplitude register
SGBC : Sound generator buzzer control register
SGCR : Sound generator control register
SIO30 : Serial I/O shift register 30
TCL50 : Timer clock selection register 50
TCL51 : Timer clock selection register 51
TM0
: 16-bit timer register 0
: 8-bit counter 50
TM50
TM51
: 8-bit counter 51
TMC0 : 16-bit timer mode control register 0
TMC50 : 8-bit timer mode control register 50
TMC51 : 8-bit timer mode control register 51
TOC0
TXS0
: 16-bit timer output control register
: Transmit shift register
UDLCCL : UDL clock control register
WDCS : Watchdog timer clock selection register
WDTM : Watchdog timer mode register
WTM
: Watch timer mode control register
383
µPD1615, µPD16F15, µPD1616
[Memo]
384
µPD1615, µPD16F15, µPD1616
Appendix D Revision History
The following shows the revision history up to present. Application portions signifies the chapter
of each edition.
Edition No.
Major items revised
RevisedSections
385
µPD1615, µPD16F15, µPD1616
Appendix D Revision History
Edition No.
Major items revised
Revised Sections
386
µPD1615, µPD16F15, µPD1616
[Memo]
387
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相关型号：
UPD17002CU
Microcontroller, 4-Bit, MROM, 8MHz, CMOS, PDIP48, 0.600 INCH, SHRINK, PLASTIC, DIP-48
NEC
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