UPD17103GS-XXX-E1-A [RENESAS]
UPD17103GS-XXX-E1-A;型号: | UPD17103GS-XXX-E1-A |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | UPD17103GS-XXX-E1-A 微控制器 光电二极管 外围集成电路 |
文件: | 总104页 (文件大小:544K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17145(A1), 17147(A1), 17149(A1)
SMALL, GENERAL-PURPOSE
4-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD17145(A1), 17147(A1), and 17149(A1) are 4-bit single-chip microcontrollers integrating an 8-bit
A/D converter (4 channels), a timer function (3 channels), and a serial interface.
These microcontrollers employ a CPU of the general-purpose register type that can execute direct memory
operations and direct memory-to-memory data transfer for efficient programming. All the instructions consist
of 16 bits per word.
In addition, a one-time PROM version, the µPD17P149, is also available for program evaluation.
The functions of these microcontrollers are described in detail in the following User’s Manual. Be sure
to read the following manual when designing your system:
µPD17145 Subseries User’s Manual: IEU-1383
FEATURES
•
•
17K architecture
: General-purpose register type
: Instruction length fixed to 16 bits
: µPD17145(A1) : 2 KB (1024 × 16 bits)
: µPD17147(A1) : 4 KB (2048 × 16 bits)
: µPD17149(A1) : 8 KB (4096 × 16 bits)
: 110 × 4 bits
Program memory (ROM)
•
•
•
•
•
•
•
•
Data memory (RAM)
External interrupt
Instruction execution time
8-bit A/D converter
Timer
: 1 (INT pin, with sense input)
: 2 µs (at 8 MHz: ceramic oscillation)
: 4 channels, absolute accuracy: ±1.5 LSB MAX. (VDD = 4.0 to 5.5 V)
: 3 channels
Serial interface
: 1 channel (clocked 3-wire)
POC circuit (mask option)
Operating voltage
: VDD = 2.7 to 5.5 V (at 400 kHz to 2 MHz)
: VDD = 4.5 to 5.5 V (at 400 kHz to 8 MHz)
: Ta = –40 to +110 ˚C
•
Operating temperature
APPLICATIONS
Automotive electronics, etc.
Unless contextually excluded, references in this data sheet to the µPD17149 (A1) mean the µPD17145
(A1) and µPD17147 (A1).
The information in this document is subject to change without notice.
Document No. U13233EJ1V1DS00 (1st edition)
(Previous No. IC-3580)
Date Published January 1998 N CP(K)
Printed in Japan
1995
©
µPD17145(A1), 17147(A1), 17149(A1)
ORDERING INFORMATION
Part Number
Package
Quality Grade
µPD17145CT(A1)-×××
µPD17145GT(A1)-×××
µPD17147CT(A1)-×××
µPD17147GT(A1)-×××
µPD17149CT(A1)-×××
µPD17149GT(A1)-×××
28-pin plastic shrink DIP (400 mil)
28-pin plastic SOP (375 mil)
Special
Special
Special
Special
Special
Special
28-pin plastic shrink DIP (400 mil)
28-pin plastic SOP (375 mil)
28-pin plastic shrink DIP (400 mil)
28-pin plastic SOP (375 mil)
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD17145(A1), 17147(A1), 17149(A1)
FUNCTION LIST
Part Number
µPD17145 (A1)
µPD17147 (A1)
µPD17149 (A1)
Item
ROM capacity
RAM capacity
Stack
2 KB (1024 × 16 bits)
110 × 4 bits
4 KB (2048 × 16 bits)
8 KB (4096 × 16 bits)
Address stack × 5, interrupt stack × 3
• I/O
: 20
: 2
I/O ports
23
• Input
• Sense input (INT pinNote
)
: 1
A/D converter input
4 channels (shared with port pins), absolute accuracy: ±1.5 LSB MAX.
• 8-bit timer/counter:
2 channels (can be used as 1 channel of 16-bit timer)
Timer
3 channels
• 7-bit basic interval timer:
1 channel (can be used as watchdog timer)
Serial interface
1 channel (3-wire)
• Multiple interrupt by hardware (3 levels MAX.)
• External interrupt (INT): 1
Rising edge, falling edge, or both rising and falling
edges selectable for detection.
Interrupt
• Timer 0 (TM0)
• Timer 1 (TM1)
• Internal interrupt: 4
• Basic interval timer (BTM)
• Serial interface (SIO)
Instruction execution time
Standby function
2 µs (at 8 MHz, ceramic oscillation)
HALT, STOP
Mask option
POC circuit
(Can be used in application circuit that operates on VDD = 5 V ± 10 %, 400 kHz to 4 MHz)
2.7 to 5.5 V (at 400 kHz to 2 MHz)
4.5 to 5.5 V (at 400 kHz to 8 MHz)
28-pin plastic shrink DIP (400 mil)
28-pin plastic SOP (375 mil)
Operating voltage
Package
Quality grade is "standard" and not (A1).
µPD17P149
One-time PROM version
Operating temperature range: Ta = –40 to +85 ˚C
Note
The INT pin is used as an input pin (sense input) when the external interrupt function is not used.
The status of this pin is read by using the INT flag of a control register, not by a port register.
Caution The PROM version is functionally compatible with the mask ROM versions but its internal
circuit and part of the electrical characteristics are different from those of the mask ROM
versions. To replace the PROM version with a mask ROM version, thoroughly conduct
application evaluation by using a sample of the mask ROM version.
3
µPD17145(A1), 17147(A1), 17149(A1)
PIN CONFIGURATION (Top View)
28-pin plastic shrink DIP (400 mil)
28-pin plastic SOP (375 mil)
V
DD
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
P0F
1
/VREF
X
X
IN
2
P0C
P0C
P0C
P0C
3
/ADC
/ADC
/ADC
/ADC
P0B
P0B
P0B
P0B
P0A
P0A
P0A
P0A
3
2
3
OUT
2
4
RESET
INT
µ
µ
µ
µ
µ
µ
1
0
1
0
3
5
P0F /RLS
0
6
P0D
0
/SCK
7
P0D
1
/SO
2
1
0
3
2
1
0
8
P0D
P0D
2
/SI
9
3
/TM1OUT
10
11
12
13
14
P0E
P0E
P0E
P0E
0
1
2
3
ADC0-ADC3
GND
: analog input
: ground
INT
: external interrupt input
: port 0A
P0A0 to P0A3
P0B0 to P0B3
P0C0 to P0C3
P0D0 to P0D3
P0E0 to P0E3
: port 0B
: port 0C
: port 0D
: port 0E
P0F0 and P0F1 : port 0F
RESET
RLS
: reset input
: standby release signal input
: serial clock I/O
: serial data input
: serial data output
: timer 1 output
SCK
SI
SO
TM1OUT
VDD
: power
VREF
: A/D converter reference voltage
: for system clock oscillation
XIN, XOUT
4
µPD17145(A1), 17147(A1), 17149(A1)
BLOCK DIAGRAM
VDD
X
IN
Clock
Divider
System Clock
Generator
XOUT
fx/2N
CPU CLOCK CLK STOP
RF
INT
P0A
P0A
P0A
P0A
3
IRQTM0
IRQTM1
IRQBTM
IRQSIO
RAM
P0A
(CMOS)
2
Interrupt
Controller
1
110 × 4 bits
0
SYSTEM REG.
P0B
P0B
P0B
P0B
3
IRQBTM
P0B
(CMOS)
2
fx/2N
Basic Interval Timer
1
0
IRQTM1
Timer 1
ALU
P0C
P0C
P0C
P0C
3
/ADC
/ADC
/ADC
/ADC
3
fx/2N
fx/2N
P0C
(CMOS)
2
2
1
1
IRQTM0
Timer 0
0
0
A/D
Converter
P0E
P0E
P0E
3
P0E
(N-ch)
2
P0F /VREF
1
1
P0F
P0E
0
Instruction
Decoder
Note 1
ROM
P0F /RLS
0
P0D
3
/TM1OUT
P0D /SI
P0D /SO
P0D /SCK
RESET
GND
P0D
(N-ch)
2
1
Program Counter
Stack Note 2
0
Serial
Interface
TM1
IRQSIO
Notes 1. The ROM capacity of each product is as follows:
1024 × 16 bits: µPD17145(A1)
2048 × 16 bits: µPD17147(A1)
4096 × 16 bits: µPD17149(A1)
2. The stack capacity of each product is as follows:
5 × 10 bits: µPD17145(A1)
5 × 11 bits: µPD17147(A1)
5 × 12 bits: µPD17149(A1)
Remark CMOS or N-ch in ( ) indicate the output format of the port.
CMOS : CMOS push-pull output
N-ch : N-ch open-drain output
5
µPD17145(A1), 17147(A1), 17149(A1)
CONTENTS
1.
PIN .....................................................................................................................................9
1.1. Pin Function ..................................................................................................................................... 9
1.2 Equivalent Circuit of Pin ............................................................................................................... 11
1.3 Handling of Unused Pins .............................................................................................................. 15
1.4 Note on Using RESET and P0F0/RLS Pins ............................................................................... 16
2.
PROGRAM MEMORY (ROM)...................................................................................... 17
2.1 Configuration of Program Memory .............................................................................................. 17
3.
PROGRAM COUNTER (PC) ....................................................................................... 18
3.1 Configuration of Program Counter .............................................................................................. 18
3.2 Operation of Program Counter .................................................................................................... 18
4.
STACK ........................................................................................................................... 19
4.1 Configuration of Stack .................................................................................................................. 19
4.2 Stack Function ............................................................................................................................... 19
5.
DATA MEMORY (RAM) ............................................................................................... 20
5.1 Configuration of Data Memory..................................................................................................... 20
6.
GENERAL REGISTER (GR)........................................................................................ 21
6.1 General Register Pointer (RP)..................................................................................................... 21
7.
SYSTEM REGISTER (SYSREG) ................................................................................ 22
7.1 Configuration of System Register ............................................................................................... 22
8.
REGISTER FILE (RF) .................................................................................................. 24
8.1 Configuration of Register File ...................................................................................................... 24
8.2 Function of Register File .............................................................................................................. 25
9.
DATA BUFFER (DBF) ................................................................................................. 26
9.1 Configuration of Data Buffer ........................................................................................................ 26
9.2 Function of Data Buffer ................................................................................................................ 27
10. ALU BLOCK .................................................................................................................. 28
10.1 Configuration of ALU Block .......................................................................................................... 28
11. PORTS ........................................................................................................................... 30
11.1 Port 0A (P0A0, P0A1, P0A2, P0A3) .............................................................................................. 30
11.2 Port 0B (P0B0, P0B1, P0B2, P0B3) .............................................................................................. 31
11.3 Port 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3) ................................................... 32
11.4 Port 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM1OUT) ........................................................ 33
11.5 Port 0E (P0E0, P0E1, P0E2, P0E3) .............................................................................................. 34
11.6 Port 0F (P0F0/RLS, P0F1/VREF) ................................................................................................... 34
6
µPD17145(A1), 17147(A1), 17149(A1)
12. 8-BIT TIMERS/COUNTERS (TM0, TM1) ................................................................... 35
12.1 Configuration of 8-Bit Timers/Counters ..................................................................................... 35
13. BASIC INTERVAL TIMER (BTM) ............................................................................... 39
13.1 Configuration of Basic Interval Timer ........................................................................................ 39
13.2 Registers Controlling Basic Interval Timer ............................................................................... 41
13.3 Watchdog Timer Function ........................................................................................................... 43
14. A/D CONVERTER......................................................................................................... 45
14.1 Configuration of A/D Converter .................................................................................................. 45
14.2 Function of A/D Converter........................................................................................................... 46
14.3 Operation of A/D Converter ........................................................................................................ 47
15. SERIAL INTERFACE (SIO) ......................................................................................... 50
15.1 Function of Serial Interface......................................................................................................... 50
15.2 Operation Mode of 3-Wire Serial Interface ............................................................................... 52
16. INTERRUPT FUNCTION.............................................................................................. 54
16.1 Types of Interrupt Causes and Vector Addresses ................................................................... 54
16.2 Hardware of Interrupt Control Circuit......................................................................................... 55
17. STANDBY FUNCTION ................................................................................................. 56
17.1 Outline of Standby Function ....................................................................................................... 56
17.2 HALT Mode ................................................................................................................................... 58
17.3 STOP Mode ................................................................................................................................... 60
18. RESET............................................................................................................................ 63
18.1 Reset Function.............................................................................................................................. 63
18.2 Reset Operation ........................................................................................................................... 64
19. POC CIRCUIT (MASK OPTION)................................................................................. 65
19.1 Function of POC Circuit............................................................................................................... 65
19.2 Conditions to Use POC Circuit ................................................................................................... 66
20. INSTRUCTION SET...................................................................................................... 67
20.1 Outline of Instruction Set............................................................................................................. 67
20.2 Legend ........................................................................................................................................... 68
20.3 Instruction Set............................................................................................................................... 69
20.4 Assembler (AS17K) Embedded Macro Instruction ................................................................... 71
21. ASSEMBLER RESERVED WORDS........................................................................... 72
21.1 Mask Option Directive.................................................................................................................. 72
21.2 Reserved Symbols ....................................................................................................................... 74
22. ELECTRICAL SPECIFICATIONS ............................................................................... 82
23. CHARACTERISTIC CURVE (REFERENCE VALUE)............................................... 88
7
µPD17145(A1), 17147(A1), 17149(A1)
24. PACKAGE DRAWINGS ....................................................................................................90
25. RECOMMENDED SOLDERING CONDITIONS ..............................................................94
APPENDIX A. FUNCTION COMPARISON BETWEEN µPD17145 SUBSERIES AND
THE µPD17135A AND 17137A ......................................................................96
APPENDIX B. DEVELOPMENT TOOLS .................................................................................98
8
µPD17145(A1), 17147(A1), 17149(A1)
1. PIN
1.1. Pin Function
Function
Pin Number
1
Symbol
Output Format
—
After Reset
—
Power supply.
VDD
Referencevoltageinputtoport0FandA/Dconverter.
• Pull-up resistor can be connected by mask
option.
2
P0F1/VREF
Input
Input (P0F1)
• P0F1
• Bit 1 of 2-bit input port (P0F)
• VREF
• Reference voltage input pin of A/D converter
Analog input to port 0C and A/D converter.
• P0C3-P0C0
P0C3/ADC3
to
3 to 6
• 4-bit I/O port
CMOS push-pull
Input (P0C)
• Can be set in input or output mode bitwise.
• ADC3-ADC0
P0C0/ADC0
• Analog inputs to A/D converter.
Port 0B.
7
8
9
P0B3
P0B2
P0B1
• 4-bit I/O port
• Can be set in input or output mode in 4-bit
CMOS push-pull
Input
units.
10
P0B0
• Pull-up resistor can be connected in 4-bit units
via software.
11
12
13
P0A3
P0A2
P0A1
Port 0A.
• 4-bit I/O port.
• Can be set in input or output mode in 4-bit
CMOS push-pull
Input
units.
14
P0A0
• Pull-up resistor can be connected in 4-bit units
via software.
Port 0E.
15
16
17
P0E3
P0E2
P0E1
• 4-bit I/O port.
• Can be set in input or output mode in 4-bit
N-ch
open-drain
Input
units.
18
P0E0
• Pull-up resistor can be connected in 4-bit units
via software.
Port 0D that is also used for timer 1 output, serial
19
P0D3/TM1OUT
data input, serial data output, and serial clock I/O.
• Pull-up resistor can be connected bitwise via
software.
• P0D3-P0D0
• 4-bit I/O port.
N-ch
open-drain
Input (P0D)
• Can be set in input or output mode bitwise.
• TM1OUT
• Timer 1 output
• SI
20
21
22
P0D2/SI
P0D1/SO
P0D0/SCK
• Serial data input
• SO
• Serial data output
• SCK
• Serial clock I/O
9
µPD17145(A1), 17147(A1), 17149(A1)
Pin Number
Symbol
Output Format
After Reset
Input (P0F0)
Function
Port 0F or standby mode release signal input.
• Pull-up resistor can be connected by mask
option.
• R0F0
23
P0F0/RLS
Input
• Bit 0 of 2-bit input port (P0F)
• RLS
• Standby mode release signal input
External interrupt request signal input. Also used
to release standby mode.
24
25
INT
Input
Input
Input
Input
• Pull-up resistor can be connected by mask
option.
System reset input.
RESET
• Pull-up resistor can be connected by mask
option.
For system clock oscillation.
26
27
XOUT
XIN
—
—
—
—
Connect ceramic resonator across XIN and XOUT.
GND
28
GND
10
µPD17145(A1), 17147(A1), 17149(A1)
1.2 Equivalent Circuit of Pin
The input/output circuit of each pin is shown below, partially simplified.
(1) P0A0 to P0A3 and P0B0 to P0B3
V
DD
V
DD
pull-up
flag
P-ch
data
Output latch
P-ch
N-ch
output
disable
Selector
Input buffer
11
µPD17145(A1), 17147(A1), 17149(A1)
(2) P0C0/ADC0 to P0C3/ADC3
VDD
data
Output latch
P-ch
N-ch
output
disable
input
disable
Selector
Input buffer
A/D
converter
(3) P0D3/TM1OUT and P0D1/SO
VDD
pull-up flag
P-ch
Output
data
latch
N-ch
output
disable
Selector
Input buffer
12
µPD17145(A1), 17147(A1), 17149(A1)
(4) P0D2/SI and P0D0/SCK
VDD
pull-up flag
P-ch
Output
latch
data
N-ch
output
disable
Selector
Input buffer
(5) P0E0 to P0E3
V
DD
pull-up
flag
P-ch
Output
latch
data
N-ch
output
disable
Selector
Input buffer
(6) P0F0/RLS
V
DD
Input buffer
Mask option
stand-by
release
13
µPD17145(A1), 17147(A1), 17149(A1)
(7) P0F1/VREF
VDD
Input buffer
A/D select
Mask option
A/D end
STOP mode
VREF
P-ch
(8) RESET and INT
V
DD
Mask option
Input buffer
14
µPD17145(A1), 17147(A1), 17149(A1)
1.3 Handling of Unused Pins
Handle unused pins as shown in the table below.
Table 1-1. Handling of Unused Pins
Handling
Pin Name
Internally
Externally
Connect on-chip pull-up resistor via
software.
P0A, P0B, P0D, P0E
P0C
Open
Connect to VDD via pull-up resistor, or
—
to GND via pull-down resistorNote 1
.
Input
mode
Do not connect on-chip pull-up resistor
by mask option.
Directly connect to VDD or GND.
Open
P0F1
Connect on-chip pull-up resistor by mask
option.
Do not connect on-chip pull-up resistor
by mask option.
Note 2
P0F0
Directly connect to GND.
Port
P0A, P0B, P0C (CMOS
—
port)
P0D
Output low level.
Output
mode
(N-ch open-drain port)
Open
Do not connect pull-up on-chip resistor
via software, but output low level.
P0E
(N-ch open-drain port) Connect on-chip pull-up resistor via
software and output high level.
Do not connect on-chip pull-up resistor
by mask option.
Directly connect to VDD or GND.
Open
External interrupt (INT)
Connect on-chip pull-up resistor by mask
option.
Do not connect on-chip pull-up resistor
by mask option.
RESETNote 3
Directly connect to VDD.
(when only internal
POC circuit is used)
Connect on chip pull-up resistor by
mask option.
Notes 1. Take into consideration the drive capability and current dissipation of a port when the port is
externally pulled up or down. To pull up or down the port with a high resistance, exercise care
so that noise is not superimposed on the port pin. The appropriate value of the pull-up or pull-
down resistor differs depending on the application circuit. Generally, select a resistor of several
10 kΩ.
2. The P0F0/RLS pin is also used to set a test mode. When this pin is not used, do not connect a
pull-up resistor to it by mask option, but directly connect it to GND.
3. In an application circuit where a high reliability is required, be sure to input the RESET signal from
an external source. The RESET pin is also used to set a test mode. When this pin is not used,
directly connect it to VDD.
Caution It is recommended to fix the input/output mode, pull-up resistor by software, and the output
level of the pin by repeatedly setting them in each loop of the program.
15
µPD17145(A1), 17147(A1), 17149(A1)
1.4 Note on Using RESET and P0F0/RLS Pins
The RESET and P0F0/RLS pins also have a function to set a test mode in which the internal operation of the
µPD17149(A1) is tested (for IC test only), in addition to the function described in 1.1 Pin Function.
If a voltage higher than VDD is applied to these pins, the test mode is set. If a noise higher than VDD is
superimposed on these pins during normal operation, therefore, the test mode is set by mistake, affecting normal
operation.
If the wiring length of the RESET or P0F0/RLS pin is too long, for example, noise may be superimposed on
the pin.
To prevent this, the wiring length must be kept as short as possible. Otherwise, use a diode or capacitor as
shown below.
● Connect a low-VF diode between VDD
● Connect a capacitor between VDD
and RESET, P0F0/RLS
and RESET, P0F0/RLS
V
DD
V
DD
V
DD
V
DD
Diode with
low V
RESET, P0F
0
/RLS
RESET, P0F /RLS
0
F
16
µPD17145(A1), 17147(A1), 17149(A1)
2. PROGRAM MEMORY (ROM)
Table 2-1 shows the program memory configuration of the µPD17145(A1), 17147(A1), and 17149(A1).
Table 2-1. Program Memory Configuration
Part Number
µPD17145(A1)
µPD17147(A1)
µPD17149(A1)
Program Memory Capacity
2 KB (1024 × 16 bits)
4 KB (2048 × 16 bits)
8 KB (4096 × 16 bits)
Program Memory Address
0000H-03FFH
0000H-07FFH
0000H-0FFFH
The program memory stores programs and constant data tables.
The program memory is addressed by the program counter.
Addresses 0000H-0005H are allocated to a reset start address and various interrupt vector addresses.
2.1 Configuration of Program Memory
Figure 2-1 shows the program memory map. The program memory is divided in units called “pages” each
of which consists of 2K steps with one step made up of 16 bits.
Addresses 0000H-07FFH (page 0) of the program memory can be specified by the direct subroutine call
instruction. The entire address range of the program memory, 0000H-0FFFH, can be specified by the branch,
indirect subroutine call, and table reference instructions.
Figure 2-1. Program Memory Map
Address
Reset start address
0000H
0001H
0002H
0003H
0004H
0005H
Serial interface interrupt vector
Basic interval timer interrupt vector
Timer 1 interrupt vector
BR addr instruction
branch address
BR @AR instruction
branch address
Timer 0 interrupt vector
CALL addr
instruction subroutine
entry address
Page 0
External (INT) interrupt vector
CALL @AR instruction
subroutine entry address
MOVT DBF,
@AR instruction
table reference address
(With
(With
(With
µ
µ
µ
PD17145(A1))
03FFH
07FFH
0FFFH
PD17147(A1))
Page 1
PD17149(A1))
16 bits
17
µPD17145(A1), 17147(A1), 17149(A1)
3. PROGRAM COUNTER (PC)
The program counter is used to address the program memory.
3.1 Configuration of Program Counter
The program counter is a 10-/11-/12-bit binary counter as shown in Figure 3-1.
Figure 3-1. Program Counter
MSB
LSB
PC0
PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC ( µPD17145(A1))
PC ( µPD17147(A1))
PC ( µPD17149(A1))
3.2 Operation of Program Counter
Usually, the contents of the program counter are automatically incremented each time an instruction has been
executed. When reset has been effected, when a branch, subroutine call, return, or table reference instruction
has been executed, or when an interrupt has been acknowledged, the address of the program memory to be
executed next is set to the program counter.
Figure 3-2. Value of Program Counter after Instruction Execution
Bit of Program Counter
Value of Program Counter
Instruction
At reset
PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
BR addr
Value specified by addr
CALL addr
BR @AR
CALL @AR
Contents of address register (AR)
(MOVT DBF, @AR)
RET
RETSK
Contents of address stack indicated by stack pointer (return address)
Vector address of each interrupt
RETI
When interrupt is acknowledged
Remark The µPD17145(A1) does not have PC11 and PC10. The µPD17147(A1) does not have PC11.
18
µPD17145(A1), 17147(A1), 17149(A1)
4. STACK
The stack is a register to which the return address of the program or the contents of the system registers,
which are described later, are saved when a subroutine call instruction is executed or when an interrupt is
acknowledged.
4.1 Configuration of Stack
Figure 4-1 shows the configuration of the stack.
The stack consists of a 3-bit binary counter, stack pointer (SP), five 10-bit (µPD17145(A1)), 11-bit
(µPD17147(A1)), or 12-bit (µPD17149(A1)) address stack registers (ASRs), and three 5-bit interrupt stack
registers (INTSKs).
Figure 4-1. Configuration of Stack
Stack pointer
(SP)
Address stack registers
(ASRs)
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b2
b1
b0
0H
1H
2H
3H
4H
Address stack register 0
Address stack register 1
Address stack register 2
Address stack register 3
Address stack register 4
SPb
2
SPb
1
SPb
0
SP is initialized to 5H at
reset.
Interrupt stack registers
(INTSKs)
0H BCDSK0 CMPSK0 CYSK0
1H BCDSK1 CMPSK1 CYSK1
2H BCDSK2 CMPSK2 CYSK2
ZSK0
ZSK1
ZSK2
IXESK0
IXESK1
IXESK2
4.2 Stack Function
The stack is used to save a return address when the subroutine call or table reference instruction is executed.
When an interrupt is acknowledged, the return address of the program and the contents of the program status
word (PSWORD) are automatically saved to the stack. After they are saved to the stack, all the bits of PSWORD
are cleared to 0.
19
µPD17145(A1), 17147(A1), 17149(A1)
5. DATA MEMORY (RAM)
The data memory is used to store data for operation and control. Data can always be written to or read from
this memory by using an instruction.
5.1 Configuration of Data Memory
The data memory is assigned addresses each consisting of 7 bits. The higher 3 bits of an address are called
a “row address”, while the lower 4 bits are called a “column address”.
Take address 1AH for example. The row address of this address is 1H and the column address is 0AH.
One address consists of 4 bits (= 1 nibble) of memory.
The data memory consists of an area to which the user can save data, and areas to which special functions
are allocated in advance. These areas are:
• System register (SYSREG)
• Data buffer (DBF)
• Port register
(Refer to 7. SYSTEM REGISTER (SYSREG).)
(Refer to 9. DATA BUFFER (DBF).)
(Refer to 11. PORT.)
Figure 5-1. Configuration of Data Memory
Column address
BANK0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DBF3 DBF2 DBF1 DBF0
0
1
Example :
Address
2
3
4
5
6
7
1AH of BANK0
P0E
(4 bits) (2 bits)
P0F
P0A
P0B
P0C
P0D
(4 bits) (4 bits) (4 bits) (4 bits)
System register
20
µPD17145(A1), 17147(A1), 17149(A1)
6. GENERAL REGISTER (GR)
As its name implies, the general register is used for general purposes such as data transfer and operation.
The general register of the 17K series is not a fixed area, but an area specified on the data memory by using
the general register pointer (RP). Therefore, a part of the data memory area can be specified as a general
register as necessary, so that data can be transferred between data memory areas and the data in the data
memory can be operated with a single instruction.
6.1 General Register Pointer (RP)
RP is a pointer that specifies part of the data memory as the general register. RP specifies the bank and
row addresses of a data memory area that is to be specified as the general register. Consisting of a total of
7 bits, RP is assigned to 7DH (RPH) and 7EH (RPL), and the higher 3 bits of the system register (refer to 7.
SYSTEM REGISTER (SYSREG)).
RPH specifies a bank, and RPL specifies a data memory row address.
Figure 6-1. Configuration of General Register Pointer
Column address
BANK0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
General register
area when
RPH = 0000B,
RPL = 010×B
General register (16 nibbles)
Row addresses
0H to 7H can be
specified by
general register
pointer (RP).
Row
address
System register
RP
Address
Name
7DH
7EH
General register
pointer (RP)
Symbol
Bit
RPH
RPL
b3
b2
b1
b0
b3
b2
b1
b0
B
C
D
Data
0
0
0
0
Reset
0
0
0
0
0
0
0
21
µPD17145(A1), 17147(A1), 17149(A1)
7. SYSTEM REGISTER (SYSREG)
The system register (SYSREG) is a register that directly controls the CPU, and is located on the data memory.
7.1 Configuration of System Register
Figure 7-1 shows the location of the system register on the data memory. As shown in this figure, the system
register is located at addresses 74H-7FH of the data memory.
Because the system register is located on the data memory, it can be manipulated by all the data memory
manipulation instructions. It is therefore possible to specify the system register as a general register.
Figure 7-1. Location of System Register on Data Memory
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data memory
(BANK0)
Port register
System register (SYSREG)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Figure 7-2 shows the configuration of the system register. As shown in this figure, the system register consists
of the following seven registers:
• Address register
(AR)
• Window register
(WR)
• Bank register
(BANK)
(IX)
• Index register
• Data memory row address pointer
• General register pointer
• Program status word
(MP)
(RP)
(PSWORD)
22
µPD17145(A1), 17147(A1), 17149(A1)
Figure 7-2. Configuration of System Register
Address
Name
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
Index register
(IX)
Program
status
word
General register
pointer
Window Bank
register register
(WR) (BANK)
Address register
(AR)
Data memory
row address
pointer (MP)
(RP)
(PSWORD)
IXH
MPH
IXM
Symbol
Bit
AR3
AR2
AR1
AR0
WR
BANK
IXL
RPH
RPL
PSW
MPL
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b
3
b2
b1
b
0
b3
b2
b1
b
0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b
0
b3
b2
b1
b
0
b3
b2
b1
b0
(IX)
M
P
E
B C C
C M Y Z X
D P
I
DataNote1 0 0 0 0 Note2
0 0 0 0
(BANK)
0 0 0 0
(MP)
0 0 0 0
(RP)
E
(AR)
Initial
Undefi-
ned
value at 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Notes 1. 0 in this field means that the bit is “fixed to 0”.
2. b3 and b2 of AR2 of the µPD17145(A1) are fixed to 0. b3 of AR2 of the µPD17147(A1) is fixed to
0.
23
µPD17145(A1), 17147(A1), 17149(A1)
8. REGISTER FILE (RF)
The register file is a register that mainly sets the conditions of the peripheral hardware.
8.1 Configuration of Register File
8.1.1 Configuration of register file
Figure 8-1 shows the configuration of the register file.
As shown in this figure, the register file consists of 128 nibbles (128 × 4 bits). Like the data memory, the
register file is assigned addresses in 4-bit units, with row addresses 0H-7H and column addresses 0H-0FH.
Addresses 00H-3FH of the register file are called a control register.
Figure 8-1. Configuration of Register File
Register file
Column address
0
1 2 3 4 5 6 7 8 9 A B C D E F
0
1
2
3
4
5
6
7
Control register
8.1.2 Register file and data memory
Figure 8-2 shows the relationships between the register file and data memory.
As shown in this figure, addresses 40H to 7FH of the register file overlaps the data memory.
It seems from the program as if addresses 40H to 7FH of the data memory exist at addresses 40H-7FH of
the register file.
24
µPD17145(A1), 17147(A1), 17149(A1)
Figure 8-2. Relationships between Register File and Data Memory
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data memory
BANK0
System register
Port register
0
1
2
3
Control register
Register file
8.2 Function of Register File
8.2.1 Function of register file
The register file is a collection of registers that set the conditions of the peripheral hardware by using the PEEK
or POKE instruction.
The registers that control the peripheral hardware are allocated to addresses 00H-3FH. These registers are
called control registers.
Addresses 40H-7FH of the register file overlap the ordinary data memory. These addresses can therefore
be read or written by not only the MOV instruction but also the PEEK and POKE instructions.
8.2.2 Functions of control registers
The control registers are used to set the conditions of the peripheral hardware listed below.
For the details of the peripheral hardware and control registers, refer to the description of each peripheral
hardware.
• Port
• 8-bit timers/counters (TM0, TM1)
• Basic interval timer (BTM)
• A/D converter
• Serial interface (SIO)
• Interrupt function
• Stack pointer (SP)
25
µPD17145(A1), 17147(A1), 17149(A1)
9. DATA BUFFER (DBF)
The data buffer consists of 4 nibbles allocated to addresses 0CH-0FH of BANK0 of the data memory.
This area is a data storage area that transfers data with the peripheral hardware of the CPU (address register,
serial interface, timers 0 and 1, and A/D converter) by using the GET or PUT instruction. Moreover, the constants
on the program memory can be read to the data buffer by using the MOVT DBF, @AR instruction.
9.1 Configuration of Data Buffer
Figure 9-1 shows the location of the data buffer on the data memory.
As shown in this figure, the data buffer is allocated addresses 0CH-0FH of the data memory, and consists
of a total of 16 bits or 4 nibbles (4 × 4 bits).
Figure 9-1. Location of Data Buffer
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data buffer
(DBF)
0
1
2
3
4
5
6
7
Data memory
BANK0
System register (SYSREG)
Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer consists of 16
bits of the data memory, with the bit 0 of address 0FH as the LSB and bit 3 of address 0CH as the MSB.
Figure 9-2. Configuration of Data Buffer
Address
Bit
0CH
0DH
0EH
0FH
Data memory
BANK0
b
3
b2
b
1
b
0
b
3
b2
b
1
b
0
8
b
3
7
b2
b
1
b
0
4
b
3
3
b2
b
1
b
0
0
b15
b
14
b
13
b12
b11
b
10
b
9
b
b
b6
b
5
b
b
b2
b
1
b
Bit
Data buffer
Symbol
DBF3
DBF2
Data
DBF1
DBF0
L
S
B
M
S
B
Data
Because the data buffer is located on the data memory, it can be manipulated by all the data memory
manipulation instructions.
26
µPD17145(A1), 17147(A1), 17149(A1)
9.2 Function of Data Buffer
The data buffer has two main functions.
One is to transfer data with the peripheral hardware, and the other is to read the constant data on the program
memory (table reference). Figure 9-3 shows the relationships between the data buffer and peripheral hardware.
Figure 9-3. Data Buffer and Peripheral Hardware
Data buffer
(DBF)
Peripheral address Peripheral hardware
01H
02H
03H
04H
40H
45H
Shift register (SIOSFR)
Timer 0 modulo register (TM0M)
Timer 1 modulo register (TM1M)
Internal bus
Program memory
(ROM)
A/D converter data
register (ADCR)
Constant data
Address register (AR)
Timer 0 timer 1 count
register (TM0TM1C)
27
µPD17145(A1), 17147(A1), 17149(A1)
10. ALU BLOCK
The ALU executes arithmetic and logical operations, bit judgment, and rotation processing of 4-bit data.
10.1 Configuration of ALU Block
Figure 10-1 shows the configuration of the ALU block.
As shown, the ALU block consists of an ALU that processes 4-bit data, and peripheral circuits such as
temporary registers A and B, status flip-flops that control the status of the ALU, and a decimal adjustment circuit
that is used when a BCD operation is performed.
The status flip-flops are a zero flag FF, carry flag FF, compare flag FF, and BCD flag FF, as shown in Figure
10-1.
The status flip-flops correspond to the zero flag (Z), carry flag (CY), compare flag (CMP), and BCD flag (BCD)
of the program status word (PSWORD: addresses 7EH, 7FH) on a one-to-one basis.
28
µPD17145(A1), 17147(A1), 17149(A1)
Figure 10-1. Configuration of ALU Block
Data bus
Temporary register
A
Temporary register
Status flip-flop
B
ALU
• Arithmetic operation
• Logical operation
• Bit judgment
• Compare judgment
• Rotation processing
Decimal adjustment
circuit
Address
7EH
7FH
Program status word
(PSWORD)
Name
Bit
b
0
b3
b2
b1
b0
Flag
BCD
CMP
CY
Z
IXE
Status flip-flop
BCD
flag
FF
CMP
flag
FF
CY
flag
FF
Z
flag
FF
Functional Outline
Indicates that result of arithmetic operation is 0.
Stores carry or borrow resulting from arithmetic
operation.
Specifies whether result of arithmetic operation
is stored.
Specifies whether decimal adjustment is
performed when arithmetic operation is executed.
29
µPD17145(A1), 17147(A1), 17149(A1)
11. PORTS
11.1 Port 0A (P0A0, P0A1, P0A2, P0A3)
Port 0A is a 4-bit I/O port with an output latch. It is mapped at address 70H of BANK0 of the data memory.
The output format is CMOS push-pull output.
This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0AGIO
(bit 0 of address 2CH) on the register file.
When P0AGIO = 0, all the pins of port 0A are set in the input mode. When an instruction that reads the data
of the port register is executed at this time, the pin status is read.
When P0AGIO = 1, all the pins of port 0A are set in the output mode, and the contents written to the output
latch are output to the pins. When an instruction that reads the port status is executed with the port set in the
output mode, the contents of the output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected is specified by P0AGPU (bit 0 at address 0CH) of the register file. All the four pins are pulled up
when P0AGPU = 1. When P0AGPU = 0, the pull-up resistor is not connected.
P0AGIO and P0AGPU are cleared to “0” at reset, and all the P0A pins are set in the input mode without the
pull-up resistor connected. The value of the output latch is also cleared to “0”.
Table 11-1. Writing and Reading Port Register (0.70H)
P0AGIO
Input/Output
Mode of Pin
Input
BANK0 70H
RF: 2CH, bit 0
Write
Enabled
Read
0
1
P0A pin status
Output
Write to P0A latch
P0A latch contents
30
µPD17145(A1), 17147(A1), 17149(A1)
11.2 Port 0B (P0B0, P0B1, P0B2, P0B3)
Port 0B is a 4-bit I/O port with an output latch. It is mapped at address 71H of BANK0 of the data memory.
The output format is CMOS push-pull output.
This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0BGIO
(bit 1 of address 2CH) on the register file.
When P0BGIO = 0, all the pins of port 0B are set in the input mode. When an instruction that reads the data
of the port register is executed at this time, the pin status is read.
When P0BGIO = 1, all the pins of port 0B are set in the output mode, and the contents written to the output
latch are output to the pins. When an instruction that reads the port status is executed with the port set in the
output mode, the contents of the output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected is specified by P0BGPU (bit 1 at address 0CH) of the register file. All the four-bit pins are pulled
up when P0BGPU = 1. When P0BGPU = 0, the pull-up resistor is not connected.
P0BGIO and P0BGPU are cleared to “0” at reset, and all the P0B pins are set in the input mode without the
pull-up resistor connected. The value of the output latch is also cleared to “0”.
Table 11-2. Writing and Reading Port Register (0.71H)
P0BGIO
Input/Output
Mode of Pin
Input
BANK0 71H
RF: 2CH, bit 1
Write
Enabled
Read
0
1
P0B pin status
Output
Write to P0B latch
P0B latch contents
31
µPD17145(A1), 17147(A1), 17149(A1)
11.3 Port 0C (P0C0/ADC0, P0C1/ADC1, P0C2/ADC2, P0C3/ADC3)
Port 0C is a 4-bit I/O port with an output latch. It is mapped at address 72H of BANK0 of the data memory.
The output format is CMOS push-pull output.
This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by
P0CBIO0-P0CBIO3 (address 1CH) on the register file.
When P0CBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Cn, is set in the input mode. When an instruction
that reads the data of the port register is executed at this time, the pin status is read. When P0CBIOn = 1 (n
= 0 to 3), the P0Cn pin is set in the output mode, and the contents written to the output latch are output to the
pin. When an instruction that reads the port status is executed with a port pin set in the output mode, the contents
of the output latch, instead of the pin status, are read.
At reset, P0CBIO0-P0CBIO3 are cleared to “0”, setting all the P0C pins in the input mode. The contents of
the output latch are also cleared to “0” at this time.
Port 0C is also used to input analog voltages to the A/D converter. Whether each pin of the port is used as
a port pin or analog input pin is specified by P0C0IDI-P0C3IDI (address 1BH) on the register file.
When P0CnIDI = 0 (n = 0-3), the P0Cn/ADCn pin functions as a port pin. When P0CnIDI = 1 (n = 0 to 3), the
P0Cn/ADCn pin functions as an analog input pin of the A/D converter. If any of the P0CnIDI (n = 0 to 3) bits
is set to “1”, the P0F1/VREF pin is used as the VREF pin.
When a pin of port 0C is used as an analog input pin of the A/D converter, set the P0CnIDI corresponding
to the pin to which an analog voltage is applied to 1, to disable the port input function. Moreover, clear P0CBIOn
(n = 0-3) to 0 to set the input port mode. The pin used as an analog input pin is selected by ADCCH0 and ADCCH1
(bits 1 and 0 of address 22H) on the register file.
At reset, P0CBIO0-P0CBIO3, P0C0IDI-P0C3IDI, ADCCH0, and ADCCH1 are cleared to 0, setting the input
port mode.
Table 11-3. Selecting Port or A/D Converter Mode
(n = 0 to 3)
P0CnIDI
RF:1BH
P0CBIOn
BANK0 72H
Function
RF:1CH
Write
Read
0
1
0
Input port
Port output
Enabled. P0C latch
Enabled. P0C latch
Enabled. P0C latch
Pin status
0
Contents of P0C latch
Contents of P0C latch
Analog input of A/DNote 1
1
Output port and analog
input of A/DNote 2
1
Enabled. P0C latch
Contents of P0C latch
Notes 1. Normal setting when the P0C pins are used as the analog input pins of the A/D converter.
2. The P0C pins function as output port pins. At this time, the analog input voltages change with
the output from the port. To use the pins as analog input pins, be sure to clear P0CBIOn to
0.
32
µPD17145(A1), 17147(A1), 17149(A1)
11.4 Port 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TM1OUT)
Port 0D is a 4-bit I/O port with an output latch. It is mapped at address 73H of BANK0 of the data memory.
The output format is N-ch open-drain output.
This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by
P0DBIO0-P0DBIO3 (address 2BH) on the register file.
When P0DBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Dn, is set in the input mode. When an instruction
that reads the data of the port register is executed at this time, the pin status is read. When P0DBIOn = 1, the
P0Dn pin is set in the output mode, and the contents written to the output latch are output to the pin. When
an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the
output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected or not is specified bitwise by using P0DBPU0-P0DBPU3 (address 0DH) on the register file. When
P0DBPUn = 1, the P0Dn pin is pulled up. When P0DBPUn = 0, the pull-up resistor is not connected.
At reset, P0DBIOn is cleared to “0”, setting all the P0D pins in the input mode. The contents of the output
latch are also cleared to “0” at this time. Note that the contents of the output latch are not changed even if the
status of P0DBIOn is changed from “1” to “0”.
Port 0D is also used as serial interface input/output and timer 1 output pins. Whether the P0D0 to P0D2 pins
are used as port pins or serial interface I/O pins (SCK, SO, and SI) is specified by SIOEN (bit 0 of 0BH) on the
register file. Whether the P0D3 pin is used as a port pin or timer 1 output (TM1OUT) pin is specified by TM1OSEL
(bit 3 of 0BH) on the register file. If TM1OSEL = 1, “1” is output when timer 1 is reset, and the output is inverted
each time the count value of timer 1 coincides with the contents of the modulo register.
Table 11-4. Contents of Register File and Pin Function
(n = 0 to 3)
Value of Register File
SIOEN
Pin Function
TM1OSEL
RF: 0BH
Bit 3
P0DBIOn
RF: 0BH
RF: 2BH
P0D0/SCK
P0D1/SO
P0D2/SI
P0D3/TM1OUT
Bit 0
Bit n
0
1
0
1
0
1
0
1
Input port
0
1
0
1
Output port
0
1
Input port
SCK
SCK
SO
SI
SI
Output port
Input port
Output port
TM1OUT
SO
33
µPD17145(A1), 17147(A1), 17149(A1)
Table 11-5. Read Contents of Port Register (0.73H)
Port Mode
Read Contents of Port Register (0.73H)
Pin status
Input port
Output port
Contents of output latch
Contents of output latch
Pin status
Internal clock selected as serial clock
External clock selected as serial clock
SCK
SI
Pin status
SO
Contents of output latch
Contents of output latch
TM1OUT
11.5 Port 0E (P0E0, P0E1, P0E2, P0E3)
Port 0E is a 4-bit I/O port with an output latch. It is mapped at address 6EH of BANK0 of the data memory.
The output format is N-ch open-drain output.
This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0EGIO
(bit 2 of address 2CH) on the register file.
When P0EGIO = 0, all the pins of port 0E are set in the input mode. When an instruction that reads the data
of the port register is executed at this time, the pin status is read.
When P0EGIO = 1, all the pins of port 0E are set in the output port, and the contents written to the output
latch are output to the pins. When an instruction that reads the port status is executed with the port set in the
output mode, the contents of the output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected is specified by P0EGPU (bit 2 at address 0CH) of the register file. All the four-bit pins are pulled
up when P0EGPU = 1. When P0EGPU = 0, the pull-up resistor is not connected.
P0EGIO is cleared to “0” at reset, and all the P0E pins are set in the input mode. The value of the output
latch is also cleared to “0”.
Table 11-6. Writing and Reading Port Register (0.6EH)
(n = 0 to 3)
P0EGIO
Input/Output
Mode of Pin
Input
BANK0 6EH
RF: 2CH, bit 2
Write
Enabled
Read
0
1
P0E pin status
Output
Write to P0E latch
P0E latch contents
11.6 Port 0F (P0F0/RLS, P0F1/VREF)
Port 0F is a 2-bit input port and mapped at address 6FH of BANK0 of the data memory. A pull-up resistor
can be connected on-chip bitwise to this port by mask option.
If a read instruction that reads the port register is executed when both pins of port 0F are used as input port
pins, the higher 2 bits of the register are fixed to 0, and the pin statuses are read to the lower 2 bits. Executing
a write instruction is meaningless as the contents of the port register remain unchanged.
The P0F0/RLS pin is also used to input a standby mode release signal.
The P0F1/VREF pin inputs a reference voltage to the A/D converter when even one of the bits of P0CnIDI (RF:
address 1BH, n = 0 to 3) is set to “1”. If an instruction is executed to read the port register when the P0F1/VREF
pin functions as the VREF pin, bit 1 of address 6FH is always cleared to 0.
34
µPD17145(A1), 17147(A1), 17149(A1)
12. 8-BIT TIMERS/COUNTERS (TM0, TM1)
The µPD17149(A1) is provided with two 8-bit timers/counters: timer 0 (TM0) and timer 1 (TM1).
By using the count-up signal of timer 0 as the count pulse to timer 1, the two 8-bit timers can be used as a
16-bit timer.
Each timer is controlled through hardware manipulation by using the PUT or GET instruction or manipulation
of the registers on the register file by using the PEEK or POKE instruction.
12.1 Configuration of 8-Bit Timers/Counters
Figure 12-1 shows the configuration of the 8-bit timers/counters. An 8-bit timer/counter consists of an 8-bit
count register, an 8-bit modulo register, a comparator that compares the value of the count register with that
of the modulo register, and a selector that selects the count pulse.
Cautions 1. The modulo register is a write register.
2. The count register is a read register.
35
µPD17145(A1), 17147(A1), 17149(A1)
Figure 12-1. Configuration of 8-Bit Timer/Counter
Data buffer
(DBF)
Internal bus
Interrupt control
Timer 0 mode
register (RF:0FH)
register (RF:11H)
INT
TM0EN TM0RES TM0CK1 TM0CK0
Timer 0 modulo
register (8)
(TM0M)
2
Timer 0 count-up signal
(to timer 1)
Coincidence
Timer 0
comparator (8)
Latch
Timer 0
count register (8)
(TM0C)
D
Q
System clock/16
IRQTM0 set signal
System clock/512
System clock/64
CLK
R
Clear
INT
Reset
Internal reset
IRQTM0 clear signal
Data buffer
(DBF)
Internal bus
Serial interface
control register
(RF:0BH)
Port control
register of bit I/O
(RF:2BH)
Timer 1 mode
register (RF:12H)
TM1OSEL
P0DBIO3
TM1EN TM1RES TM1CK1 TM1CK0
Timer 1 modulo
register (8)
(TM1M)
P0DB
3
output latch
P0D3/
TM1OUT
Coincidence
2
Timer 1
comparator (8)
TM1OUT
FF
Reset
Latch
Timer 1
count register (8)
(TM1C)
D
Q
System clock/128
IRQTM1 set signal
System clock/8192
System clock/16
Timer 0 count up
CLK
R
Clear
Reset
Internal reset
IRQTM1 clear signal
36
µPD17145(A1), 17147(A1), 17149(A1)
Figure 12-2. Timer 0 Mode Register
Bit 2
Bit 1
Bit 0
Bit 3
RF : 11H
TM0RES TM0CK1 TM0CK0
R/W
TM0EN
Read/write
Read = R, write = W
0
0
0
Initial value at reset
0
TM0CK1 TM0CK0 Selects count pulse of timer 0
0
0
1
1
0
1
0
1
System clock/16
System clock/512
System clock/64
INT pin
TM0RES
0
Resets timer 0
Does not affect timer 0
Resets timer 0 count register and
IRQTM0
1
Remark TM0RES is automatically cleared to 0 after it has been
set to 1. When it is read, "0" is always read.
TM0EN
Timer 0 start command
Stops counting of timer 0
Resumes counting of timer 0
0
1
Remark TM0EN can be used as a status flag that detects
the count status of timer 0 (1 : counting in progress,
0 : counting stopped)
37
µPD17145(A1), 17147(A1), 17149(A1)
Figure 12-3. Timer 1 Mode Register
Bit 3
Bit 2
Bit 1
Bit 0
RF : 12H
TM1EN TM1RES TM1CK1 TM1CK0
R/W
Read/write
Initial value at reset
1
0
0
0
TM1CK1 TM1CK0 Selects count pulse of timer 1
0
0
1
0
1
0
System clock/128
System clock/8192
System clock/16
Count-up signal from
timer 0
1
1
TM1RES
0
Resets timer 1
Does not affect timer 1
Resets timer 1 count register and
IRQTM1
1
Remark TM1RES is automatically cleared to 0 after it has been
set to 1. When it is read, "0" is always read.
TM1EN
Timer 1 start command
Stops counting of timer 1
Resumes counting of timer 1
0
1
Remark TM1EN can be used as a status flag that detects
the count status of timer 1 (1 : counting in progress,
0 : counting stopped)
38
µPD17145(A1), 17147(A1), 17149(A1)
13. BASIC INTERVAL TIMER (BTM)
The µPD17149(A1) is provided with a 7-bit basic interval timer. This timer has the following functions:
(1) Generates reference time.
(2) Selects and counts wait time when standby mode is released.
(3) Watchdog timer function to detect program runaway.
13.1 Configuration of Basic Interval Timer
Figure 13-1 shows the configuration of the basic interval timer.
39
µPD17145(A1), 17147(A1), 17149(A1)
Figure 13-1. Configuration of Basic Interval Timer
Internal bus
Watchdog timer mode
register (RF:13H)
BTM mode
register (RF:13H)
BTMISEL BTMRES BTMCK1 BTMCK0
WDTRES
0
0
WDTEN
2
f
BTM
25
Reset
IRQBTM
set signal
Selector
f
BTM
27
f
BTM
(2)
Basic interval timer
(7-bit divider)
Selector
(3)
Reset
signal
System clock/16384
System clock/4096
System clock/512
System clock/16
Reset
1-bit
divider
(4)
R
S
Q
(1)
1-shot pulse
generator
Outputs "1" while counting 0 to 7 during counting
from 0 to 255.
Remark (1) to (4) in the figure correspond to the signals in the timing chart in Figure 13-4.
40
µPD17145(A1), 17147(A1), 17149(A1)
13.2 Registers Controlling Basic Interval Timer
The basic interval timer is controlled by the BTM mode register and watchdog timer mode register.
Figures 13-2 and 13-3 show the configuration of each register.
Figure 13-2. BTM Mode Register
RF : 13H
Bit 3
Bit 2
Bit 1
Bit 0
BTMISEL BTMRES BTMCK1 BTMCK0
R/W
Read = R, Write = W
Read/write
Initial value at reset
0
0
0
0
Selects count pulse to BTM
BTMCK1 BTMCK0
System clock/16
0
0
1
1
0
1
0
1
(1 instruction execution time)
System clock/16384
(1024 instruction execution time)
System clock/4096
(256 instruction execution time)
System clock/512
(32 instruction execution time)
BTMRES
0
Resets BTM
Does not affect basic interval timer
(BTM)
Resets binary counter of basic interval
timer (BTM)
1
Remark BTMRES is automatically cleared to 0
after it has been set to 1. When it is read,
"0" is always read.
BTMISEL
0
Selects interval timer
Sets interval timer to 1/128 of count pulse
1
Sets interval timer to 1/32 of count pulse
41
µPD17145(A1), 17147(A1), 17149(A1)
Figure 13-3. Watchdog Timer Mode Register
RF : 03H
Bit 3
Bit 2
0
Bit 1
0
Bit 0
WDTRES
WDTEN
Read = R, Write = W
R/W
Read/write
0
0
0
0
Initial value at reset
WDTEN
Enable watchdog timer
Stops watchdog timer.
Starts watchdog timer.
0
1
Remark 1. WDTEN cannot be cleared to 0 by
program.
2. WDTEN is automatically cleared to 0
after it has been set to 1. When it is
read, "0" is always read.
WDTRES
0
Resets watchdog timer
Does not affect watchdog timer.
Resets flip-flop that retains overflow carry of
BTM used for watchdog timer.
1
Remark WDTRES is automatically cleared to 0
after it has been set to 1. When it is
read, "0" is always read.
42
µPD17145(A1), 17147(A1), 17149(A1)
13.3 Watchdog Timer Function
The basic interval timer can also be used as a watchdog timer that detects a program runaway.
13.3.1 Function of watchdog timer
The watchdog timer is a counter that generates a reset signal at fixed time intervals. By inhibiting generation
of this reset signal by program, the system can be reset (started from address 0000H) if the system becomes
runaway due to external noise (if the watchdog timer is not reset within specific time).
This function allows the program to escape from the runaway status because a reset signal is generated at
fixed time intervals even when the program jumps to an unexpected routine and enters an indefinite loop due
to external noise.
13.3.2 Operation of watchdog timer
When WDTEN is set to 1, the 1-bit divider is enabled to operate, and the basic interval timer starts operating
as an 8-bit watchdog timer.
Once the watchdog timer has been started, it cannot be stopped until the device is reset and WDTEN is
cleared to 0.
Reset effected by the watchdog timer can be inhibited in the following two ways:
(1) Repeatedly set WDTRES in the program.
(2) Repeatedly set BTMRES in the program.
In the case of (1), WDTRES must be set while the count value of the watchdog timer is 8 to 191 (before it
reaches 192). Therefore, program so that “SET1 WDTRES” is executed at least once in a cycle shorter than
that in which the watchdog timer counts 184.
In the case of (2), BTMRES must be set before the basic interval timer (BTM) counts 128. Therefore, program
so that “SET1 BTMRES” is executed at least once in a cycle shorter than that in which BTM counts 128. In this
case, however, interrupts cannot be processed with BTM.
Caution BTM is not reset even if WDTEN is set. Therefore, before setting WDTEN first, be sure to
set BTMRES to reset BTM.
Example
SET1 BTMRES
SET2 WDTEN, WDTRES
43
µPD17145(A1), 17147(A1), 17149(A1)
Figure 13-4. Timing Chart of Watchdog Timer (when WDTRES flag is used)
255
255
255
192
192
192
192
Count value of watchdog timer
128
128
128
128
64
8
8
8
0
0
0
0
WDTEN
WDTRES
acknowledge period
WDTRES
acknowledge period
WDTRES
acknowledge period
WDTRES
1-shot pulse generator
output (1)
(4)
f
BTM/27 (2)
( ↓ IRQBTM set)
f
BTM/28 (3)
Watchdog reset signal
(active high)
Reset signal is not generated
44
µPD17145(A1), 17147(A1), 17149(A1)
14. A/D CONVERTER
The µPD17149(A1) is provided with an A/D converter with 4 analog input channels (P0C0/ADC0-P0C3/ADC3)
and a resolution of 8 bits.
This A/D converter is of the successive approximation type and operates in the following two modes:
1
2
Successive mode in which 8-bit A/D conversion is sequentially performed starting from the most
significant bit
Single mode in which an input analog voltage is compared with the set value of an 8-bit data register
14.1 Configuration of A/D Converter
Figure 14-1 shows the configuration of the A/D converter.
Figure 14-1. Block Diagram of A/D Converter
Remark n = 0 to 3
Internal bus
RF: 20H
RF: 22H
RF: 21H
Read signal
0
0
ADCCH1 ADCCH0
0
0
0
ADCSTRT
ADCSOFT
0
ADCCMP ADCEND
Output
latch
P0CnIDI
P0CBIOn
Selector
Control circuit
8
Comparator
4
8-bit data register Note
(ADCR)
Selector
P0Cn/ADCn
A/D end signal
STOP instruction signal
8
Tap decoder
P0F /VREF
1
3R/2
R
R
R/2
D/A converter
4
P0F input data
1
P0CnIDI
Note
The 8-bit data register (ADCR) is cleared to 00H when the STOP instruction is executed.
45
µPD17145(A1), 17147(A1), 17149(A1)
14.2 Function of A/D Converter
(1) ADC0 to ADC3 pins
These pins input analog voltages to the four channels of the A/D converter. The analog voltages are
converted into digital signals. The A/D converter is provided with a sample and hold circuit, and an analog
input voltage being converted into a digital signal is internally held.
(2) VREF pin
This pin inputs a reference voltage to the A/D converter.
The signals input to ADC0 to ADC3 are converted into digital signals based on the voltage applied across
VREF and GND. The A/D converter of the µPD17149(A1) has a function to automatically stop the current
flowing into the VREF pin when the A/D converter does not operate. A current flows into the VREF pin in the
following cases:
1
2
In successive mode (ADCSOFT = 0)
Since the ADCSTRT flag has been set to 1 until the ADCEND flag is set to 1.
In single mode (ADCSOFT = 1)
Since the ADCSTRT flag has been set to 1 or a value has been written to the 8-bit data register until
the result of comparison by the comparator is written to the ADCCMP flag.
Remarks 1. If the HALT instruction is executed during A/D conversion, the A/D converter operates,
in the successive mode, until the ADCEND flag is set, or in the single mode, until the
result of conversion is stored to the ADCCMP flag. Therefore, a current flows to the VREF
pin during this period.
2. A/D conversion in progress is stopped if the STOP instruction is executed. In this case,
the A/D converter is initialized, and the current flowing to the VREF pin is cut (the A/D
converter does not operate even if the STOP mode has been released).
(3) 8-bit data register (ADCR)
This is an 8-bit register that stores the result of A/D conversion of successive approximation type in the
successive mode. The contents of this register are read by using the GET instruction. In the single mode,
the contents of the 8-bit data register are converted into an analog voltage by an internal D/A converter and
is compared by the comparator with an analog signal input from the ADCn pin. A value can be written to
this register by using the PUT instruction.
(4) Comparator
The comparator compares the analog input voltage with the voltage output by the D/A converter. If the
analog input voltage is high, it outputs “1”; if the voltage is low, the comparator outputs “0”. The result of
comparison is stored to the 8-bit data register (ADCR) in the successive mode, and to the ADCCMP flag
in the single mode.
46
µPD17145(A1), 17147(A1), 17149(A1)
14.3 Operation of A/D Converter
The operation of the A/D converter can be executed in two modes, depending on the setting of the ADCSOFT
flag: successive and single modes.
ADCSOFT
Operation Mode of A/D Converter
Successive mode (A/D conversion)
Single mode (compare operation)
0
1
Figure 14-2. Relationships between Analog Input Voltage and Digital Conversion Result
Ideal conversion result
FFH
FEH
FDH
N
03H
02H
01H
(× VDD
)
00H
254
256
255
256
256
256
0
1
256
2
256
N
256
Analog input voltage (V)
47
µPD17145(A1), 17147(A1), 17149(A1)
(1) Timing in successive mode (A/D conversion)
Figure 14-3. Timing in Successive Mode (A/D Conversion)
→ Number of executed instructions (instruction cycle)
POKE
1
2
3
4
5
6
7
8
9
24
GET
Sampling
Sampling
Sampling
ADCSTRT executed
ADCR read
ADCSTRT
ADCEND
Highest 1 bit
determined
Highest 2 bits
determined
All 8 bits
determined
8-bit data
register
Previous data
Initial value:80H
Caution Sampling is performed eight times while A/D conversion is executed once.
If the analog input voltage changes heavily during A/D conversion, A/D conversion cannot
be performed accurately. To obtain an accurate conversion result, it is necessary to
minimize the changes in the analog input voltage during A/D conversion.
Remark One sampling time = 14/fx (1.75 µs, at 8 MHz)
Sampling repeat cycle = 48/fx (6 µs, at 8 MHz)
Sampling capacitor capacitance = 100 pF (MAX.)
48
µPD17145(A1), 17147(A1), 17149(A1)
(2) Timing in single mode (compare operation)
Figure 14-4. Timing in Single Mode (Compare Operation)
→ Number of executed instructions (instruction cycle)
POKE PEEK PUT
1
2
1
2
PEEK
Sampling
Sampling
ADCSTRT executed
ADCCMP read
ADCCMP read
ADCSTRT
ADCEND
Previous data
Comparison result
Comparison result
ADCCMP
After 1 has been written to ADCSTRT in the single mode (execution of the POKE instruction), a value is
stored to ADCCMP three instructions after, and the result of comparison can be read by the PEEK
instruction. Even if data is set to ADCR (execution of the PUT instruction), comparison is started in the same
manner as ADCSTRT, and the result of comparison can be read three instructions after.
The ADCCMP flag is cleared to 0 when reset is executed or when an instruction that writes data to ADCR
is executed.
Caution Be sure to set ADCSOFT to 1 before setting a value to ADCR. When ADCSOFT = 0, no value
can be set to ADCR (the PUT ADCR, DBF instruction is invalidated).
Remark Sampling time = 14/fx (1.75 µs, at 8 MHz)
Sampling capacitor capacitance = 100 pF (MAX.)
49
µPD17145(A1), 17147(A1), 17149(A1)
15. SERIAL INTERFACE (SIO)
The serial interface of the µPD17149(A1) consists of an 8-bit shift register (SIOSFR), a serial mode register,
and a serial clock counter, and is used to input/output serial data.
15.1 Function of Serial Interface
The serial interface can transmit or receive 8-bit data in synchronization with the clock by using three wires:
serial clock input (SCK), serial data output (SO), and serial data input (SI) pins. This serial interface can connect
various peripheral I/O devices in a mode compatible with the method employed for the µPD7500 series and 75X
series.
(1) Serial clock
Four types of serial clocks, three internal and one external, can be selected. If an internal clock is selected
as the serial clock, the selected clock is automatically output to the P0D0/SCK pin.
Table 15-1. Serial Clocks
SIOCK1
SIOCK0
Selected Serial Clock
External clock from SCK pin
System clock/16
0
0
1
1
0
1
0
1
System clock/128
System clock/1024
(2) Transfer operation
Each pin of port 0D (P0D0/SCK, P0D1/SO, P0D2/SI) functions as a serial interface pin when SIOEN is set
to 1. If SIOTS is set to 1 at this time, the serial interface starts its operation in synchronization with the falling
edge of the external or internal clock. If SIOTS is set, IRQSIO is automatically cleared.
Data is transferred starting from the most significant bit of the shift register in synchronization with the rising
edge of the serial clock, and the information on the SI pin is stored to the shift register, starting from the
least significant bit, in synchronization with the rising edge of the serial clock.
When 8-bit data has been completely transferred, SIOTS is automatically cleared, and IRQSIO is set.
Remark When serial transfer is executed, transfer is started only from the most significant bit of the
contents of the shift register. In other words, transfer cannot be started from the least significant
bit. The status of the SI pin is always loaded to the shift register in synchronization with the rising
edge of the serial clock.
50
µPD17145(A1), 17147(A1), 17149(A1)
Figure 15-1. Block Diagram of Serial Interface
P0D2/SI
LSB
MSB
Shift register (SIOSFR)
SIOTS SIOHIZ SIOCK1 SIOCK0
Output
latch
IRQSIO
clear signal
P0D
1/SO
P0D
1
output latch
One shot
IRQSIO
set signal
Serial clock
counter
P0D
0
/SCK
Carry
Clear
Clock
S
R
Q
P0D
0
output latch
Selector
SIOEN
P0DBIO0
P0DBIO1
Caution The output latch of the shift register is independent of the output latch of P0D1. Therefore,
even if an output instruction is executed to P0D1, the status of the output latch of the shift
register is not affected. The output latch of the shift register is cleared to “0” by RESET
input. After that, it holds the status of the LSB of the previously transferred data.
51
µPD17145(A1), 17147(A1), 17149(A1)
15.2 Operation Mode of 3-Wire Serial Interface
The serial interface can operate in the following two modes. When the serial interface function is selected,
the P0D2/SI pin always inputs data in synchronization with the serial clock.
• 8-bit transmission/reception mode (simultaneous transmission/reception)
• 8-bit reception mode (SO pin: high-impedance state)
Table 15-2. Operation Modes of Serial Interface
SIOEN
SIOHIZ
P0D0/SI Pin
P0D1/SO Pin
SO
Operation Mode of Serial Interface
8-bit transmission/reception mode
8-bit reception mode
1
0
1
×
SI
SI
1
P0D1 (input)
P0D1 (I/O)
0
P0D0 (I/O)
General-purpose port mode
× : Don't care
(1) 8-bit transmission/reception mode (simultaneous transmission/reception)
Input or output of serial data is controlled by the serial clock. The MSB of the shift register is output to the
SO line at the falling edge of the serial clock (SCK pin signal). The contents of the shift register are shifted
1 bit at the rising edge of the serial clock. At the same time, the data on the SI line is loaded to the LSB
of the shift register.
The serial clock counter (3-bit counter) sets an interrupt request flag (IRQSIO <- 1) each time it has counted
eight serial clocks.
Figure 15-2. Timing in 8-Bit Transmission/Reception Mode (Simultaneous Transmission/Reception)
SCK pin
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI pin
SO pin
IRQSIO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Starts transfer in synchronization with falling of SCK pin
Executes instruction that writes "1" to SIOTS (transfer start command)
End of transfer
Remark DI: serial data input
DO: serial data output
52
µPD17145(A1), 17147(A1), 17149(A1)
(2) 8-bit reception mode (SO pin: high-impedance state)
The P0D1/SO pin goes into a high-impedance state when SIOHIZ = 1. If supply of the serial clock is started
at this time by writing “1” to SIOTS, the serial interface only receives data.
Because the P0D1/SO pin goes into a high-impedance state, it can be used as an input port pin (P0D1).
Figure 15-3. Timing in 8-Bit Reception Mode
1
2
3
4
5
6
7
8
SCK pin
SI pin
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi - Z
SO pin
IRQSIO
End of transfer
Starts transfer in synchronization with falling of SCK pin
Executes instruction that writes "1" to SIOTS (transfer start command)
Remark DI: serial data input
(3) Operation stop mode
When the value of SIOTS (RF: address 02H, bit 3) is 0, the serial interface is set in the operation stop mode.
In this mode, serial transfer is not executed.
Because the shift register does not perform the shift operation in this mode, it can be used as an ordinary
8-bit register.
53
µPD17145(A1), 17147(A1), 17149(A1)
16. INTERRUPT FUNCTION
The µPD17149(A1) has five interrupt causes, of which four are internal and one is external, enabling various
applications.
The interrupt control circuit of the µPD17149(A1) has the following features and can perform interrupt
processing at extremely high speeds:
(a) Acknowledging an interrupt can be controlled by interrupt mask enable flag (INTE) and interrupt enable
flag (IP×××).
(b) Interrupt request flags (IRQ×××) can be tested and cleared (occurrence of an interrupt can be checked
by software).
(c) Multiple interrupts of up to 3 levels can be processed.
(d) The standby mode (STOP or HALT) can be released by an interrupt request (releasing condition can be
selected by the interrupt enable flag).
Caution Only the BCD, CMP, CY, Z, and IXE flags are automatically saved to the stack by
hardware when interrupt processing is performed. Up to three levels of multiple
interrupts can be processed. If the peripheral hardware (timers, A/D converter, etc.)
is accessed during interrupt processing, the contents of DBF and WR are not saved by
the hardware. It is therefore recommended that DBF and WR be saved to the RAM by
software at the beginning of interrupt processing, and that their contents be restored
immediately before the interrupt processing.
16.1 Types of Interrupt Causes and Vector Addresses
All the interrupts of the µPD17149 (A1) are vectored interrupts, and therefore, program execution branches
to a vector address corresponding to the interrupt cause when an interrupt has been acknowledged. Table 16-
1 shows the types of interrupt causes and vector addresses.
If two or more interrupts occur at the same time, or if two or more pending interrupts are enabled all at once,
processing is performed according to the priority shown in Table 16-1.
Table 16-1. Types of Interrupt Causes
Vector
Internal
Interrupt Cause Priority
IRQ Flag
IP Flag
IP
IEG Flag
Remark
Address
/External
INT pin
1
2
3
4
5
0005H
0004H
0003H
0002H
0001H
IRQ
IEGMD0, 1
RF:1FH
External
Internal
Internal
Internal
Internal
Rising, falling, or
(RF: 0FH, bit 0)
RF: 3FH,
bit 0
RF: 2FH,
bit 0
both rising and fall-
ing edges selectable
Timer 0
Timer 1
IRQTM0
RF: 3EH,
bit 0
IPTM0
RF: 2FH,
bit 1
—
IRQTM1
RF: 3DH,
bit 0
IPTM1
RF: 2FH,
bit 2
—
—
Basic interval
timer
IRQBTM
RF: 3CH,
bit 0
IPBTM
RF: 2FH,
bit 3
Serial interface
IRQSIO
RF: 3BH,
bit 0
IPSIO
RF: 2EH,
bit 0
—
54
µPD17145(A1), 17147(A1), 17149(A1)
16.2 Hardware of Interrupt Control Circuit
This section describes each flag of the interrupt control circuit.
(1) Interrupt request flags and interrupt enable flags
An interrupt request flag (IRQ×××) is set to 1 when an interrupt request is generated, and automatically
cleared to 0 when interrupt processing is executed.
An interrupt enable flag (IP×××) is provided for each interrupt request flag. The corresponding interrupt is
enabled when this flag is “1”, and disabled when the flag is “0”.
(2) EI/DI instruction
Whether an interrupt that has been acknowledged is executed is specified by the EI or DI instruction.
When the EI instruction is executed, an interrupt enable flag (INTE) that enables acknowledging an interrupt
is set to 1. The INTE flag is not registered on the register file. Therefore, the status of this flag cannot be
checked by an instruction.
The DI instruction clears the INTE flag to “0”, disabling all the interrupts.
The INTE flag is also cleared to 0 at reset, and therefore all the interrupts are disabled.
Table 16-2. Interrupt Request Flags and Interrupt Enable Flags
Interrupt Request Flag
IRQ
Interrupt Request Flag Setting Signal
Interrupt Enable Flag
IP
Sets when edge of INT pin input signal is detected.
Edge to be detected is selected by IEGMD0 and IEGMD1
flags.
IRQTM0
IRQTM1
IRQBTM
Set by coincidence signal from timer 0.
Set by coincidence signal from timer 1.
IPTM0
IPTM1
IPBTM
Set by overflow from basic interval timer (reference time
interval signal).
IRQSIO
Set when serial interface completes serial data transfer.
IPSIO
55
µPD17145(A1), 17147(A1), 17149(A1)
17. STANDBY FUNCTION
17.1 Outline of Standby Function
The current dissipation of the µPD17149(A1) can be reduced by using the standby function. This function
can be effected in two modes: STOP and HALT.
The STOP mode stops the system clock. In this mode, the current dissipation by the CPU is minimized with
only leakage current flowing. The CPU therefore does not operate, but the contents of the data memory are
retained.
In the HALT mode, oscillation of the clock continues. However, supply of the clock to the CPU is stopped.
Therefore, the CPU stops operating. This mode cannot reduce the current dissipation as much as the STOP
mode. However, because the system clock continues oscillating, the operation can be started immediately after
the HALT mode has been released. In both the STOP and HALT modes, the statuses of the data memory,
registers, and the output latches of the output ports immediately before the standby mode is set are retained
(except STOP 0000B). Therefore, set the port status so that the current dissipation of the entire system is
reduced before the standby mode is set.
56
µPD17145(A1), 17147(A1), 17149(A1)
Table 17-1. Status in Standby Mode
STOP Mode
HALT Mode
Setting
STOP instruction
HALT instruction
instruction
Clock
oscillation
circuit
Stops oscillation
Continues oscillation
CPU
RAM
Port
TM0
• Stops operation
• Retains previous status
• Retains previous statusNote
• Can operate only when INT input is selected
as count clock
• Operable
• Operable
• Stops when system clock is selected
(count value is retained)
TM1
• Stops operation
(count value is reset to “0”)
(count up is disabled)
BTM
SIO
• Stops operation (count value is retained)
• Operable
• Operable
• Can operate only when external clock is
selected as serial clockNote
A/D
INT
• Stops operationNote (ADCR <- 00H)
• Can operate
• Operable
• Operable
Note
As soon as the STOP 0000B instruction is executed, the pins of these peripherals are set in the input
port mode, even when the control signal functions of the pins are used.
Cautions 1. Be sure to execute the NOP instruction immediately before the STOP and HALT
instructions.
2. If both the interrupt request flag and interrupt enable flag corresponding to an interrupt
are set, and if the interrupt is specified to release the standby mode, the standby mode
is not set even if the STOP or HALT instruction is executed.
57
µPD17145(A1), 17147(A1), 17149(A1)
17.2 HALT Mode
17.2.1 Setting HALT mode
The HALT mode is set when the HALT instruction is executed.
The operand of the HALT instruction, b3b2b1b0, specifies the condition under which the HALT mode is
released.
Table 17-2. HALT Mode Releasing Condition
Format: HALT b3b2b1b0B
Bit
b3
b2
b1
b0
HALT mode releasing conditionNote 1
Enables releasing HALT mode by IRQ××× when 1Notes 2, 4
Fixed to “0”
Enables forced release of HALT mode by IRQTM1 when 1Notes 3, 4
Enables releasing HALT mode by RLS input when 1Note 4
Notes 1. Only reset (RESET input or POC) is valid when HALT 0000B is specified.
2. IP××× must be set to 1.
3. The HALT mode is released regardless of the status of IPTM1.
4. Even if the HALT instruction is executed with IRQ××× = 1 or RLS input being low, the HALT
instruction is ignored (treated as an NOP instruction), and the HALT mode is not set.
17.2.2 Start address after HALT mode is released
The start address from which the program execution is started after the HALT mode has been released differs
depending on the interrupt enable condition and the condition under which the HALT mode has been released.
Table 17-3. Start Address after HALT Mode Is Released
Releasing Condition
ResetNote 1
Start Address after Release
Address 0
RLS
Address next to that of HALT instruction
Address next to that of HALT instruction in DI status
IRQ×××Note 2
Interrupt vector in EI status
(if two or more IRQ××× flags are set, interrupt vector with higher priority)
Notes 1. RESET input and POC are valid as reset.
2. IP××× must be set to 1 except when the HALT mode is forcibly released by IRQTM1.
58
µPD17145(A1), 17147(A1), 17149(A1)
Figure 17-1. Releasing HALT Mode
(a) By RESET input
HALT instruction executed
TM1 counts up
↓
↓
RESET
Operation mode
HALT mode
System reset status
WAIT a
Operation mode
(starts from address 0)
WAIT a : Wait time until TM1 counts 256 clocks divided by 128
256×128/fX (approx. 4 ms at fX =8 MHz)
(b) By RLS input
HALT instruction executed
↓
RLS
Operation mode
HALT mode
Operation mode
Operation mode
Operation mode
(c) By IRQ××× (in DI status)
HALT instruction executed
↓
IRQ×××
Operation mode
HALT mode
(d) By IRQ××× (in EI status)
Interrupt processing
acknowledged
HALT instruction executed
↓
↓
IRQ×××
Operation mode
HALT mode
59
µPD17145(A1), 17147(A1), 17149(A1)
17.3 STOP Mode
17.3.1 Setting STOP mode
The STOP mode is set when the STOP instruction is executed.
The operand of the STOP instruction, b3b2b1b0, specifies the condition under which the STOP mode is
released.
Table 17-4. STOP Mode Releasing Condition
Format: STOP b3b2b1b0B
Bit
b3
b2
b1
b0
STOP mode releasing conditionNote 1
Enables releasing HALT mode by IRQ××× when 1Notes 2, 4
Fixed to “0”
Fixed to “0”
Enables releasing STOP mode by RLS input when 1Notes 3, 4
Notes 1. Only reset (RESET input or POC) is valid when STOP 0000B is specified. When STOP
0000B is executed, the internal circuitry of the microcontroller is initialized to the status
immediately after reset.
2. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1.
3. b0 alone cannot be set to 1 (STOP 0001B is prohibited).
Before setting b0 to 1, be sure to set b3 to 1.
4. Even if the STOP instruction is executed with IRQ××× = 1 or the RLS input being low, the
STOP instruction is ignored (treated as an NOP instruction), and the STOP mode is not set.
17.3.2 Start address after STOP mode is released
The start address from which the program execution is started after the STOP mode has been released differs
depending on the condition under which the STOP mode has been released, and interrupt enable condition.
Table 17-5. Start Address after STOP Mode Is Released
Releasing Condition
ResetNote 1
Start Address after Release
Address 0
RLS
Address next to that of STOP instruction
Address next to that of HALT instruction in DI status
IRQ×××Note 2
Interrupt vector in EI status
(if two or more IRQ××× flags are set, interrupt vector with higher priority)
Notes 1. RESET input and POC are valid as reset.
2. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1.
60
µPD17145(A1), 17147(A1), 17149(A1)
Figure 17-2. Releasing STOP Mode
(a) By RESET input
STOP instruction executed
TM1 counts up
↓
↓
RESET
Operation mode
STOP mode
System reset status
WAIT b
Operation mode
(starts from address 0)
WAIT b : Wait time until TM1 counts 256 clocks divided by 128
α
α
256 × 128/f
X
+
(apporox. 4 ms + at f
X
= 8 MHz)
α
: Oscillation growth time (differs depending on the oscillator)
(b) By RLS input
STOP instruction executed
TM1 counts up
↓
↓
RLS
Operation mode
STOP mode
WAIT c
Operation mode
WAIT c : Wait time until TM1 counts clocks divided by m n times
n × m/f (n and m are values immediately before STOP mode is set)
: Oscillation growth time (differs depending on the oscillator)
X
+
α
α
(c) By IRQ××× (in DI status)
STOP instruction executed
TM1 counts up
↓
↓
IRQ×××
Operation mode
STOP mode
WAIT c
Operation mode
WAIT c : Wait time until TM1 counts clocks divided by m n times
α
(n and m are values immediately before STOP mode is set)
n × m/f
X
+
α
: Oscillation growth time (differs depending on the oscillator)
61
µPD17145(A1), 17147(A1), 17149(A1)
(d) By IRQ××× (in EI status)
TM1 counts up, interrupt
processing acknowledged
STOP instruction executed
↓
↓
IRQ×××
Operation mode
STOP mode
WAIT c
Operation mode
WAIT c : Wait time until TM1 counts clocks divided by m n times
n × m/f (n and m are values immediately before STOP mode is set)
: Oscillation growth time (differs depending on the oscillator)
X
+
α
α
62
µPD17145(A1), 17147(A1), 17149(A1)
18. RESET
The µPD17149 (A1) can be reset not only by the RESET input, but also by the internal POC circuit that detects
a supply voltage drop, watchdog timer function that resets the microcontroller if program runaway occurs, and
overflow or underflow of the address stack. Note, however, that the internal POC circuit is a mask option.
18.1 Reset Function
The reset function initializes the device operation. How the device is initialized differs depending on the type
of reset.
Table 18-1. Hardware Status at Reset
• RESET Input
• RESET Input in
Standby Mode
• Overflow of Watchdog
Timer
during Operation
Type of Reset
• Reset by Internal
POC Circuit
• Reset by Internal
POC Circuit in
• Overflow and
Hardware
Underflow of Stack
Standby Mode
Program counter
0000H
Input
0000H
Input
0000H
Input
Input/output
Port
Contents of output
latch
0
0
Undefined
Undefined
General-purpose
data memory
Undefined
Retains contents
(except DBF)
General-purpose
data memory
DBF
Undefined
0
Undefined
0
Undefined
0
System register
(except WR)
WR
Undefined
Retains contents
Undefined
SP = 5H, IRQTM1 = 1, TM1EN = 1,
IRQBTM = 1, INT = status at that time.
Others are 0. Refer to 8. REGISTER FILE
(RF).
SP = 5H, INT = status
at that time. Others
retain contents.
Control register
Timer 0: 00H,
Count register
Modulo register
00H
FFH
00H
FFH
Timer 0 and
timer 1
timer 1: undefined
FFH
Undefined. However,
40H if watchdog timer
overflows.
Binary counter of basic interval timer
Undefined
Undefined
Shift register (SIOSFR)
Output latch
Data register of A/D converter (ADCR)
Undefined
Retains contents
Undefined
Undefined
00H
Serial interface
0
0
00H
00H
63
µPD17145(A1), 17147(A1), 17149(A1)
Figure 18-1. Configuration of Reset Block
V
DD
POC circuit
(mask option)
Mask option
Internal
reset signal
RESET
18.2 Reset Operation
Figure 18-2 shows the operation when the system is reset by using the RESET pin.
When the RESET pin is made high, oscillation of the system clock is started, oscillation stabilization wait time
specified by timer 1 elapses, and program execution is started from address 0000H.
These operations are also performed if the system is reset by the POC circuit.
If the system is reset by using an overflow of the watchdog timer or an overflow or underflow of the stack,
the oscillation stabilization wait time (WAIT a) does not elapse, and program execution is started from address
0000H after the internal circuitry has been initialized.
Figure 18-2. Reset Operation
RESET
TM1EN
TM1RES
Reset
WAIT aNote
Operation mode
Operation mode
Note
Oscillation stabilization wait time. An operation mode is set when system clock is counted
128 × 256 times by timer 1 (time required to executed 2048 instructions: approx. 4 ms at 8 MHz).
64
µPD17145(A1), 17147(A1), 17149(A1)
19. POC CIRCUIT (MASK OPTION)
The POC circuit monitors the supply voltage. When the supply voltage is turned ON/OFF, it automatically
resets the internal circuitry of the microcontroller. This circuit can be used in an application circuit with a clock
frequency of 400 kHz to 4 MHz.
The µPD17149 (A1) can be provided with the POC circuit by mask option.
Caution The POC circuit is not provided to the PROM model (µPD17P149).
19.1 Function of POC Circuit
The POC circuit has the following functions:
• Generates internal reset signal when VDD ≤ VPOC
• Clears internal reset signal when VDD > VPOC
(where, VDD: supply voltage, VPOC: POC detection voltage)
Figure 19-1. Operation of POC Circuit
VDD
5.5 V
4.5 V
V
POC
2.7 V
Note 3
Note 3
0 V
→ t
Internal reset signal
Reset
Operation modeNote 4
Reset
↑
Note 1
Note 2
Operation guaranteed range
65
µPD17145(A1), 17147(A1), 17149(A1)
Notes 1. Actually, oscillation stabilization wait time specified by timer 1 elapses before the operation mode
is set. This time is equal to that required for executing about 2048 instructions (approx. 8 ms at
4 MHz).
2. To reset the microcontroller again when the supply voltage drops, the status in which the voltage
drops below VPOC must be maintained at least for the duration of the reset detection pulse width
tSAMP.
Therefore, reset is actually effected with a delay time of up to tSAMP.
3. The operation is not guaranteed if the supply voltage drops below the rated minimum value (2.7
V).
However, the POC circuit is designed to generate the internal reset signal so long as it is possible,
regardless of oscillation. Therefore, the internal circuitry is reset when the voltage supplied to
it has reached the level at which the circuitry can operate.
4. If the supply voltage abruptly increases (3 V/ms MIN.), the POC circuit may generate the internal
reset signal, even in an operation mode, to prevent program runaway.
Remark For the values of VPOC and tSAMP, refer to 22. ELECTRICAL SPECIFICATIONS.
19.2 Conditions to Use POC Circuit
The POC circuit can be used when the application circuit satisfies the following conditions:
• The application circuit does not require a high reliability.
• The operating voltage must range from 4.5 to 5.5 V.
• The clock frequency must range from 400 kHz to 4 MHz.
• The supply voltage must satisfy the ratings of the POC circuit.
Cautions 1. If the application circuit requires an extremely high reliability, design the circuit so that
the RESET signal is input from an external source.
2. The current dissipation in the standby mode slightly increases if the POC circuit is
used.
Remark The guaranteed operating voltage range of the POC circuit is VDD = 2.7 to 5.5 V.
66
µPD17145(A1), 17147(A1), 17149(A1)
20. INSTRUCTION SET
20.1 Outline of Instruction Set
b15
b14-b11
0
1
BIN
HEX
0000
0001
0010
0011
0100
0101
0110
0
1
2
3
4
5
6
ADD
SUB
ADDC
SUBC
AND
XOR
OR
r, m
ADD
SUB
ADDC
SUBC
AND
XOR
OR
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
r, m
r, m
r, m
r, m
r, m
r, m
INC
AR
INC
IX
MOVT
BR
DBF, @AR
@AR
@AR
CALL
RET
RETSK
EI
DI
0111
7
RETI
PUSH
POP
GET
PUT
PEEK
POKE
RORC
STOP
HALT
NOP
LD
AR
AR
DBF, p
p, DBF
WR, rf
rf, WR
r
s
h
1000
1001
1010
1011
1100
1101
1110
1111
8
9
r, m
ST
m, r
SKE
MOV
SKNE
BR
m, #n4
SKGE
MOV
SKLT
CALL
MOV
SKT
m, #n4
m, @r
m, #n4
addr
A
B
C
D
E
F
@r, m
m, #n4
addr (page 0)
addr (page 1)
BR
m, #n4
m, #n
m, #n
SKF
67
µPD17145(A1), 17147(A1), 17149(A1)
20.2 Legend
AR
ASR
addr
BANK
CMP
CY
DBF
h
: address register
: address stack register indicated by stack pointer
: program memory address (lower 11 bits)
: bank register
: compare flag
: carry flag
: data buffer
: halt release condition
INTEF
INTR
INTSK
IX
: interrupt enable flag
: register automatically saved to the stack when interrupt processing is performed
: interrupt stack register
: index register
MP
MPE
m
: data memory row address pointer
: memory pointer enable flag
: data memory address indicated by mR, mC
: data memory row address (high)
: data memory column address (low)
: bit position (4 bits)
mR
mC
n
n4
: immediate data (4 bits)
PAGE
PC
p
: page (bit 11 of program counter)
: program counter
: peripheral address
pH
: peripheral address (higher 3 bits)
: peripheral address (lower 4 bits)
: general register column address
: register file address
pL
r
rf
rfR
: register file row address (higher 3 bits)
: register file column address (lower 4 bits)
: stack pointer
rfC
SP
s
: stop release condition
WR
(×)
: window register
: contents addressed by ×
68
µPD17145(A1), 17147(A1), 17149(A1)
20.3 Instruction Set
In-
struc-
tion
Instruction code
Mnemonic
Operand
Operation
op code
00000
10000
00010
10010
00111
00111
00001
10001
00011
10011
00110
10110
00100
10100
00101
10101
11110
11111
01001
01011
11001
11011
Operand
mC
r, m
(r) ← (r) + (m)
mR
mR
mR
mR
r
ADD
ADDC
INC
m, #n4
r, m
(m) ← (m) + n4
(r) ← (r) + (m) + CY
(m) ← (m) + n4 + CY
AR ← AR + 1
mC
n4
r
mC
m, #n4
AR
mC
n4
000 1001 0000
000 1000 0000
IX
IX ← IX + 1
r, m
(r) ← (r) – (m)
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
r
SUB
SUBC
OR
m, #n4
r, m
(m) ← (m) – n4
(r) ← (r) – (m) – CY
(m) ← (m) – n4 – CY
(r) ← (r) (m)
n4
r
m, #n4
r, m
n4
r
m, #n4
r, m
(m) ← (m) n4
(r) ← (r) (m)
n4
r
AND
XOR
m, #n4
r, m
(m) ← (m) n4
(r) ← (r) (m)
n4
r
m, #n4
m, #n
m, #n
m, #n4
m, #n4
m, #n4
m, #n4
(m) ← (m) n4
n4
n
SKT
CMP ← 0, if (m) n = n, then skip
CMP ← 0, if (m) n = 0, then skip
(m) – n4, skip if zero
SKF
n
SKE
n4
n4
n4
n4
SKNE
SKGE
SKLT
(m) – n4, skip if not zero
(m) – n4, skip if not borrow
(m) – n4, skip if borrow
→ CY → (r) b3 → (r) b2 → (r) b1 → (r) b0
RORC
r
00111
000 0111
r
LD
ST
r, m
m, r
(r) ← (m)
01000
11000
mR
mR
mC
mC
r
r
(m) ← (r)
if MPE = 1: (MP, (r)) ← (m)
if MPE = 0: (BANK, mR, (r)) ← (m)
if MPE = 1: (m) ← (MP, (r))
if MPE = 0: (m) ← (BANK, mR, (r))
(m) ← n4
@r, m
m, @r
01010
11010
mR
mC
r
MOV
mR
mC
mC
r
m, #n4
11101
00111
mR
n4
SP ← SP –1, ASR ← PC, PC ← AR,
DBF ← (PC), PC ← ASR, SP ← SP +1
SP ← SP –1, ASR ← AR
AR ← ASR, SP ← SP +1
WR ← (rf)
MOVT
DVF, @AR
000 0001 0000
PUSH
POP
AR
00111
00111
00111
00111
00111
00111
000 1101 0000
000 1100 0000
rfR 0011 rfC
rfR 0010 rfC
pH 1011 pL
pH 1010 pL
AR
PEEK
POKE
GET
WR, rf
rf, WR
DBF, p
p, DBF
(rf) ← WR
DBF ← (p)
PUT
(p) ← DBF
69
µPD17145(A1), 17147(A1), 17149(A1)
Instruction code
In-
struc-
tion
Mnemonic
BR
Operand
Operation
op code
Note
Operand
addr
addr
Note
@AR
PC ← AR
00111
000 0100 0000
SP ← SP – 1, ASR ← PC,
PC ← addr
addr
11100
00111
addr
CALL
SP ← SP – 1, ASR ← PC,
PC ← AR
@AR
000 0101 0000
RET
RETSK
RETI
EI
PC ← ASR, SP ← SP + 1
PC ← ASR, SP ← SP + 1 and skip
PC ← ASR, INTR ← INTSK, SP ← SP + 1
INTEF ← 1
00111
00111
00111
00111
00111
00111
00111
00111
000 1110 0000
001 1110 0000
100 1110 0000
000 1111 0000
001 1111 0000
DI
INTEF ← 0
STOP
HALT
NOP
s
STOP
010 1111
011 1111
s
h
HALT
h
No operation
100 1111 0000
Note
The operation and op code of “BR addr” of the µPD17145(A1), 17147(A1), and µPD17149(A1) are
as follows:
(a) µPD17145(A1), 17147(A1)
Mnemonic Operand
Operation
op code
01100
BR
addr
PC ← addr, PAGE ← 0
(b) µPD17149(A1)
Mnemonic Operand
BR addr
Operation
op code
01100
PC ← addr, PAGE ← 0
PC ← addr, PAGE ← 1
01101
70
µPD17145(A1), 17147(A1), 17149(A1)
20.4 Assembler (AS17K) Embedded Macro Instruction
Legend
flag n:
< >:
FLG type symbol
Can be omitted
Mnemonic
Operand
Operation
if (flag 1) to (flag n) = all “1”, then skip
if (flag 1) to (flag n) = all“0”, then skip
(flag 1) to (flag n) ← 1
n
SKTn
SKFn
SETn
CLRn
flag 1, …flag n
flag 1, …flag n
flag 1, …flag n
flag 1, …flag n
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
(flag 1) to (flag n) ← 0
if (flag n) = “0”, then (flag n) ← 1
if (flag n) = “1”, then (flag n) ← 0
if description = NOT flag n, then (flag n) ← 0
if description = flag n, then (flag n) ← 1
(BANK) ← n
NOTn
flag 1, …flag n
1 ≤ n ≤ 4
<NOT> flag 1,
INITFLG
BANKn
1 ≤ n ≤ 4
…<<NOT> flag n>
n = 0
71
µPD17145(A1), 17147(A1), 17149(A1)
21. ASSEMBLER RESERVED WORDS
21.1 Mask Option Directive
The µPD17149 (A1) has the following mask options:
• Internal pull-up resistor of RESET pin
• Internal pull-up resistor of P0F1 and P0F0 pins
• Internal pull-up resistor of INT pin
• Internal POC circuit
When developing a program, it is necessary to specify all the above mask options in the source program by
using a mask option definition directive (pseudo instruction).
21.1.1 Specifying mask option
The mask option is described in the assembler source program by using the following directives:
• OPTION directive, ENDOP directive
• Mask option definition directive
(1) OPTION and ENDOP directives
These directives specify the range in which the mask option is specified (mask option definition block).
Specify the mask option by describing a mask option definition directive in the area sandwiched between
the OPTION and ENDOP directives.
Format
Symbol field
[label:]
Mnemonic field
OPTION
Operand field
Comment field
[;comment]
ENDOP
72
µPD17145(A1), 17147(A1), 17149(A1)
(2) Mask option definition directives
Table 21-1. Mask Option Definition Directives
Option
Definition Directive and Format
OPTRES <operand>
Operand
OPEN
Defined Contents
None
Internal pull-up resistor
of RESET pin
PULLUP
OPEN
Defined
None
Internal pull-up resistor
of P0F1 and P0F0 pins
Internal pull-up resistor
of INT pin
OPTP0F <operand 1>, <operand 2>Note
OPTINT <operand>
PULLUP
OPEN
Defined
None
PULLUP
NOUSE
USE
Defined
Not used
Used
Internal POC circuit
OPTPOC <operand>
Note
<operand 1> specifies the mask option of the P0F1 pin, and <operand 2> specifies that of the P0F0
pin.
(3) Example of mask option description
; Example of describing mask option of the µPD17149 (A1)
MASK_OPTION:
OPTION
; start of mask option definition block
OPTRES PULLUP
; connects internal pull-up resistor to RESET pin
OPTP0F PULLUP, OPEN ; connects internal pull-up resistor to P0F1, and leaves P0F0 open (exter-
nally pulled up)
OPTINT PULLUP
OPTPOC NOUSE
ENDOP
; connects internal pull-up resistor to INT pin
; internal POC circuit is not used
; End of mask option definition block
73
µPD17145(A1), 17147(A1), 17149(A1)
21.2 Reserved Symbols
The following tables show the reserved symbols defined by the device file (AS17149) of the µPD17149(A1):
System register (SYSREG)
Symbol Name
AR3
Attribute
MEM
Value
0.74H
Read/Write
R
Description
Bits b15-b12 of address register
Bits b11-b8 of address register
Bits b7-b4 of address register
Bits b3-b0 of address register
Window register
AR2
AR1
AR0
WR
MEM
MEM
MEM
MEM
MEM
MEM
MEM
FLG
0.75H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0.76H
0.77H
0.78H
BANK
IXH
0.79H
Bank register
0.7AH
0.7AH
0.7AH.3
0.7BH
0.7BH
0.7CH
0.7DH
0.7EH
0.7FH
Index register, high
MPH
MPE
IXM
MPL
IXL
Data memory row address pointer, high
Memory pointer enable flag
Index register, middle
Data memory row address pointer, low
Index register, low
MEM
MEM
MEM
MEM
MEM
MEM
FLG
RPH
RPL
PSW
BCD
CMP
CY
General register pointer, high
General register pointer, low
Program status word
0.7EH.0
0.7FH.3
0.7FH.2
0.7FH.1
0.7FH.0
BCD flag
FLG
Compare flag
FLG
Carry flag
Z
FLG
Zero flag
IXE
FLG
Index enable flag
74
µPD17145(A1), 17147(A1), 17149(A1)
Figure 21-1. Configuration of System Register
Address
Name
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
Index register
(IX)
Window
register
(WR)
Bank
register
(BANK)
Program
status word
(PSWORD)
General register
pointer
Address register
(AR)
Data memory row
(RP)
address pointer
(MP)
IXH
MPH
IXM
Symbol
Bit
AR3
AR2
AR1
AR0
WR
BANK
IXL
RPH
RPL
PSW
MPL
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b
3
b2
b1
b
0
b3
b2
b1
b
0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
(IX)
M
P
E
B C C
C M Y Z X
D P
I
DataNote 1
0 0 0 0 Note 2
0 0 0 0
(BANK)
0 0 0 0
(MP)
0 0 0 0
(RP)
E
(AR)
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Undefined
at reset
Notes 1. “0” in this field means that the bit is fixed to “0”.
2. b3 and b2 of AR2 of the µPD17145 (A1) are fixed to 0. b3 of AR2 of the µPD17147 (A1) is fixed
to 0.
75
µPD17145(A1), 17147(A1), 17149(A1)
Data buffer (DBF)
Symbol Name
DBF3
Attribute
MEM
Value
0.0CH
0.0DH
0.0EH
0.0FH
Read/Write
R/W
Description
Bits 15 to 12 of DBF
Bits 11 to 8 of DBF
DBF2
MEM
MEM
MEM
R/W
DBF1
R/W
Bits 7 to 4 of DBF
DBF0
R/W
Bits 3 to 0 of DBF
Port register
Symbol Name
P0A3
P0A2
P0A1
P0A0
P0B3
P0B2
P0B1
P0B0
P0C3
P0C2
P0C1
P0C0
P0D3
P0D2
P0D1
P0D0
P0E3
P0E2
P0E1
P0E0
P0F1
Attribute
Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Bit 3 of port 0A
Bit 2 of port 0A
Bit 1 of port 0A
Bit 0 of port 0A
Bit 3 of port 0B
Bit 2 of port 0B
Bit 1 of port 0B
Bit 0 of port 0B
Bit 3 of port 0C
Bit 2 of port 0C
Bit 1 of port 0C
Bit 0 of port 0C
Bit 3 of port 0D
Bit 2 of port 0D
Bit 1 of port 0D
Bit 0 of port 0D
Bit 3 of port 0E
Bit 2 of port 0E
Bit 1 of port 0E
Bit 0 of port 0E
Bit 1 of port 0F
Bit 0 of port 0F
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
0.70H.3
0.70H.2
0.70H.1
0.70H.0
0.71H.3
0.71H.2
0.71H.1
0.71H.0
0.72H.3
0.72H.2
0.72H.1
0.72H.0
0.73H.3
0.73H.2
0.73H.1
0.73H.0
0.6EH.3
0.6EH.2
0.6EH.1
0.6EH.0
0.6FH.1
0.6FH.0
P0F0
R
76
µPD17145(A1), 17147(A1), 17149(A1)
Register file (control registers)
Symbol Name
SP
Attribute
MEM
Value
0.81H
Read/Write
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Stack pointer
SIOTS
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
0.82H.3
0.82H.2
0.82H.1
0.82H.0
0.83H.3
0.83H.0
0.8BH.3
0.8BH.0
0.8CH.2
0.8CH.1
0.8CH.0
0.8DH.3
0.8DH.2
0.8DH.1
0.8DH.0
0.8FH.0
0.91H.3
0.91H.2
0.91H.1
0.91H.0
0.92H.3
0.92H.2
0.92H.1
0.92H.0
0.93H.3
0.93H.2
0.93H.1
0.93H.0
0.9BH.3
0.9BH.2
0.9BH.1
0.9BH.0
0.9CH.3
0.9CH.2
0.9CH.1
0.9CH.0
0.9FH.1
0.9FH.0
Serial interface start flag
SIOHIZ
P0D1/SO pin function select flag
SIOCK1
SIOCK0
WDTRES
WDTEN
TM1OSEL
SIOEN
Bit 1 of serial clock select flag
Bit 0 of serial clock select flag
Watchdog timer reset flag
Watchdog timer enable flag
P0D3/TM1OUT pin function select flag
Serial interface enable flag
P0EGPU
P0BGPU
P0AGPU
P0DBPU3
P0DBPU2
P0DBPU1
P0DBPU0
INT
P0E group pull-up select flag (pull-up = 1)
P0B group pull-up select flag (pull-up = 1)
P0A group pull-up select flag (pull-up = 1)
P0D3 pull-up select flag (pull-up = 1)
P0D2 pull-up select flag (pull-up = 1)
P0D1 pull-up select flag (pull-up = 1)
P0D0 pull-up select flag (pull-up = 1)
INT pin status flag
TM0EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer 0 enable flag
TM0RES
TM0CK1
TM0CK0
TM1EN
Timer 0 reset flag
Bit 1 of timer 0 count pulse select flag
Bit 0 of timer 0 count pulse select flag
Timer 1 enable flag
TM1RES
TM1CK1
TM1CK0
BTMISEL
BTMRES
BTMCK1
BTMCK0
P0C3IDI
P0C2IDI
P0C1IDI
P0C0IDI
P0CBIO3
P0CBIO2
P0CBIO1
P0CBIO0
IEGMD1
IEGMD0
Timer 1 reset flag
Bit 1 of timer 1 count pulse select flag
Bit 0 of timer 1 count pulse select flag
Basic interval timer interrupt request clock select flag
Basic interval timer reset flag
Bit 1 of basic interval timer count pulse select flag
Bit 0 of basic interval timer count pulse select flag
P0C3 input port disable flag (selects ADC3/P0C3 pin function)
P0C2 input port disable flag (selects ADC2/P0C2 pin function)
P0C1 input port disable flag (selects ADC1/P0C1 pin function)
P0C0 input port disable flag (selects ADC0/P0C0 pin function)
P0C3 input/output select flag (1 = output port)
P0C2 input/output select flag (1 = output port)
P0C1 input/output select flag (1 = output port)
P0C0 input/output select flag (1 = output port)
Bit 1 of INT pin edge detection select flag
Bit 0 of INT pin edge detection select flag
77
µPD17145(A1), 17147(A1), 17149(A1)
Register file (control registers)
Symbol Name
ADCSTRT
Attribute
FLG
Value
Read/Write
Description
0.0A0H.0
0.0A1H.3
0.0A1H.1
R/W
R/W
R
A/D converter start flag (read: always “0”)
A/D converter mode select flag (1 = single mode)
ADCSOFT
FLG
FLG
ADCCMP
A/D converter comparator comparison result flag
(valid only in single mode)
ADCEND
ADCCH3
ADCCH2
ADCCH1
ADCCH0
P0DBIO3
P0DBIO2
P0DBIO1
P0DBIO0
P0EGIO
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
0.0A1H.0
0.0A2H.3
0.0A2H.2
0.0A2H.1
0.0A2H.0
0.0ABH.3
0.0ABH.2
0.0ABH.1
0.0ABH.0
0.0ACH.2
R
A/D converter conversion end flag
Dummy flag
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dummy flag
Bit 1 of A/D converter channel select flag
Bit 0 of A/D converter channel select flag
P0D3 input/output select flag (1 = output port)
P0D2 input/output select flag (1 = output port)
P0D1 input/output select flag (1 = output port)
P0D0 input/output select flag (1 = output port)
P0E group input/output select flag
(1 = all P0E as output port)
P0BGIO
P0AGIO
FLG
FLG
0.0ACH.1
0.0ACH.0
R/W
R/W
P0B group input/output select flag
(1 = all P0B as output port)
P0A group input/output select flag
(1 = all P0A as output port)
IPSIO
IPBTM
IPTM1
IPTM0
IP
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
0.0AEH.0
0.0AFH.3
0.0AFH.2
0.0AFH.1
0.0AFH.0
0.0BBH.0
0.0BCH.0
0.0BDH.0
0.0BEH.0
0.0BFH.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial interface interrupt enable flag
Basic interval timer interrupt enable flag
Timer 1 interrupt enable flag
Timer 0 interrupt enable flag
INT pin interrupt enable flag
IRQSIO
IRQBTM
IRQTM1
IRQTM0
IRQ
Serial interface interrupt request flag
Basic interval timer interrupt request flag
Timer 1 interrupt request flag
Timer 0 interrupt request flag
INT pin interrupt request flag
78
µPD17145(A1), 17147(A1), 17149(A1)
Peripheral hardware registers
Symbol Name
SIOSFR
Attribute
DAT
Value
01H
02H
03H
04H
45H
40H
Read/Write
Description
R/W
W
Peripheral address of shift register
TM0M
TM1M
ADCR
TM0TM1C
AR
DAT
DAT
DAT
DAT
DAT
Peripheral address of timer 0 modulo register
Peripheral address of timer 1 modulo register
Peripheral address of A/D converter data register
Peripheral address of timer 0 timer 1 count register
W
R/W
R
R/W
Peripheral address of address register for GET/PUT/
PUSH/CALL/BR/MOVT/INC instruction
Others
Symbol Name
Attribute
Value
0FH
Description
DBF
IX
DAT
DAT
Fixed operand value of PUT, GET, and MOVT instructions
Fixed operand value of INC instruction
01H
79
µPD17145(A1), 17147(A1), 17149(A1)
Figure 21-2. Configuration of Control Register
Column address
Row
address
0
1
2
3
4
5
6
7
Item
S
I
S
I
S
I
S
I
W
D
T
W
D
T
S
P
O
T
S
O
H
I
O
C
K
1
O
C
K
0
0
0
R
E
S
0
0
0
0
E
N
Symbol
At reset
0
(8)
Z
1
0
1
T
0
0
0
0
0
0
R/W
R/W
R/W
Read/
Write
T
M
0
T
T
T
M
1
T
T
M
1
T
M
1
B
T
B
B
T
B
T
M
0
M M
M
1
T
0
0
M M M M
E
N
R
E
S
C C
E
N
R
E
S
C
K
1
C
K
0
I
R
E
S
C
K
1
C
K
0
Symbol
At reset
K
1
K
0
S
E
L
1
(9)
0
0
0
0
1
0
0
0
0
0
0
0
R/W
R/W
R/W
Read/
Write
A
D
C
S
T
A
D
C
S
O
F
A
D
C
A
D
C
E
N
D
A
D
C
C
H
3
A
D
C
C
H
2
A
D
C
C
H
1
A
D
C
C
H
0
Symbol
0
0
0
0
0
0
0
C
M
P
2
(A)
R
T
T
At reset
0
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
Read/
Write
Symbol
At reset
3
(B)
Read/
Write
Remark ( ) is the address when the assembler (AS17K) is used.
All the flags of the control register are registered to the device file as assembler reserved words,
and are convenient for program development.
80
µPD17145(A1), 17147(A1), 17149(A1)
Figure 21-2. Configuration of Control Register
8
9
A
B
C
D
E
F
T
M
1
S
I
P
0
P
0
P
0
P
0
P
0
P
0
P
0
I
N
T
O
E
N
E
G
P
U
B
G
P
U
A
G
P
U
D
B
P
U
3
D
B
P
U
2
D
B
P
U
1
D
B
P
U
0
O
S
E
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note
R/W
R/W
R/W
R
P
0
C
3
I
P
0
C
2
I
P
P
0
C
0
I
P
0
C
B
I
P
0
C
B
I
P
P
0
C
B
I
I
I
0
C
1
I
0
C
B
I
E
G
M
D
1
E
G
M
D
0
0
0
0
0
D
I
D
I
D
I
D
I
O
3
O
2
O
1
O
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
P
0
D
B
I
P
0
D
B
I
P
P
0
D
B
I
P
0
P
P
0
I
I
I
I
I
0
D
B
I
0
B
G
I
P
S
I
P
B
T
M
P
T
M
1
P
T
M
0
P
E
G
I
A
G
I
0
0
0
0
0
0
0
0
O
O
3
O
2
O
1
O
0
O
O
O
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
I
I
I
I
I
R
Q
S
I
R
Q
B
T
R
Q
T
R
Q
T
R
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M
1
M
0
O
M
0
0
0
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Note
INT flag differs depending on the status of the INT pin at that time.
81
µPD17145(A1), 17147(A1), 17149(A1)
22. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Supply voltage
Symbol
VDD
Condition
Ratings
Unit
V
–0.3 to +7.0
A/D converter reference voltage
VREF
–0.3 to VDD + 0.3
V
P0A, P0B, P0C, P0D, P0E, P0F,
INT, RESET, XIN
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Per P0A, P0B, or P0C
Peak value
–15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
Effective value
Peak value
–7.5
Note
High-level output current
IOH
Total of P0A, P0B,
and P0C
–30
Effective value
Peak value
–15
Per P0A, P0B, or P0C
15
Effective value
Peak value
7.5
Per P0D or P0E
30
Note
Low-level output current
IOL
Effective value
Peak value
15
100
Total of P0A, P0B, P0C,
P0D, and P0E
Effective value
50
Operating temperature
Storage temperature
Topt
Tstg
–40 to +110
–65 to +150
140
°C
28-pin plastic shrink DIP
28-pin plastic SOP
mW
mW
Power dissipation
Pd
Ta = 85 °C
85
Note
[Effective value] = [Peak value] × √Duty
Caution If the value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. The absolute maximum ratings are the values exceeding
which may physically damage the product. Be sure to use the product with these values
not exceeded.
Recommended Supply Voltage Range (Ta = –40 to +110 °C)
Parameter
Symbol
Condition
fx = 400 kHz to 2 MHz
MIN.
2.7
TYP.
MAX.
5.5
Unit
V
CPU (other than A/D
converter and POC
circuit)
fx = 400 kHz to 4 MHz
fx = 400 kHz to 8 MHz
3.6
5.5
V
4.5
5.5
V
Supply voltage
VDD
Absolute accuracy:
±1.5LSB, 2.5 V ≤
VREF ≤ VDD
A/D converter
4.0
4.5
5.5
5.5
V
V
POC circuit (mask option)
fx = 400 kHz to 4 MHz
82
µPD17145(A1), 17147(A1), 17149(A1)
DC Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)
Parameter
Symbol
VIH1
Condition
P0A, P0B, P0C, P0D, P0E, P0F
RESET, SCK, SI, INT
XIN
MIN.
TYP.
MAX.
VDD
Unit
V
0.7VDD
Input voltage, high
VIH2
0.8VDD
VDD
V
VIH3
VDD – 0.5
VDD
V
VIL1
P0A, P0B, P0C, P0D, P0E, P0F
RESET, SCK, SI, INT
XIN
0
0
0
0.3VDD
0.2VDD
0.4
V
Input voltage, low
VIL2
V
VIL3
V
4.5 ≤ VDD ≤ 5.5
VDD – 0.3
VDD – 0.3
V
V
V
V
IOH = –1.0 mA
2.7 ≤ VDD < 4.5
IOH = –0.5 mA
4.5 ≤ VDD ≤ 5.5
IOL = 1.0 mA
Output voltage, high
VOH
P0A, P0B, P0C
0.3
0.3
VOL1
VOL2
P0A, P0B, P0C, P0D, P0E
2.7 ≤ VDD < 4.5
IOL = 0.5 mA
Output voltage, low
P0D, P0E
4.5 ≤ VDD ≤ 5.5
2.7 ≤ VDD < 4.5
1.0
2.0
5
V
IOL = 15 mA
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
ILIH
ILIL
P0A, P0B, P0C, P0D, P0E, P0F
P0A, P0B, P0C, P0D, P0E, P0F
P0A, P0B, P0C, P0D, P0E
P0A, P0B, P0C, P0D, P0E
P0A, P0B, P0E, P0F, RESET, INT
P0D
VIN = VDD
VIN = 0 V
VOUT = VDD
VOUT = 0 V
µA
µA
µA
µA
kΩ
kΩ
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
–5
ILOH
ILOL
5
–5
50
3
100
10
250
30
Internal pull-up
resistorNote 1
RPULL
fx = 8.0 MHz VDD = 5 V ± 10 %
fx = 4.0 MHz VDD = 5 V ± 10 %
fx = 2.0 MHz VDD = 3 V ± 10 %
2.0
1.4
0.5
0.9
0.3
1.0
0.9
0.3
0.7
0.3
3.0
2.0
4.5
3.3
1.5
1.7
1.0
2.0
1.9
1.0
1.5
0.9
30
IDD1
Operation mode
VDD = 5 V ± 10 %
fx = 400 kHz
VDD = 3 V ± 10 %
fx = 8.0 MHz VDD = 5 V ± 10 %
fx = 4.0 MHz VDD = 5 V ± 10 %
fx = 2.0 MHz VDD = 3 V ± 10 %
Supply currentNote 2
IDD2
HALT mode
STOP mode
VDD = 5 V ± 10 %
fx = 400 kHz
VDD = 3 V ± 10 %
VDD = 5 V ± 10 %
VDD = 3 V ± 10 %
IDD3
30
Notes 1. The pull-up resistors of P0F, RESET, and INT are mask options.
2. Excluding the current of the A/D converter and POC circuit, and the current flowing into the internal
pull-up resistor.
83
µPD17145(A1), 17147(A1), 17149(A1)
AC Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 ˚C)
Parameter
Symbol
tCY
Condition
MIN.
1.9
TYP.
MAX.
41
Unit
µs
VDD = 4.5 to 5.5 V
VDD = 3.6 to 5.5 V
CPU clock cycle time
(instruction execution
time)
3.9
41
µs
7.9
41
µs
INT input frequency
(TM0 count clock input)
INT high-, low-level width
(external interrupt input)
fINT
0
400
kHz
tINTH,
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
10
50
10
50
10
50
µs
µs
µs
µs
µs
µs
tINTL
RESET low-level width
RLS low-level width
tRSL
tRLSL
Remark tCY = 16/fx (fx: system clock oscillation frequency)
Interrupt input timing
t
INTL
t
INTH
INT
RESET input timing
t
RSL
RESET
RLS input timing
t
RLSL
RLS
84
µPD17145(A1), 17147(A1), 17149(A1)
Serial transfer operation (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)
Parameter
Symbol
Condition
VDD = 4.5 to 5.5 V
MIN.
2.0
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
Input
Output
Input
10
RL = 1 kΩ,
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
2.0
SCK cycle time
tKCY
CL = 100 pF
8
Internal pull-up,
CL = 100 pF
32
64
VDD = 4.5 to 5.5 V
1.0
5.0
SCK high-, low-level
width
tKH,
tKL
RL = 1 kΩ,
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
t
t
KCY/2 – 0.6
KCY/2 – 1.2
CL = 100 pF
Internal pull-up,
CL = 100 pF
Output
t
KCY/2 – 12
KCY/2 – 24
100
t
SI setup time (to SCK ↑)
SI hold time (from SCK ↑)
tSIK
tKSI
100
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
0.8
1.4
14
RL = 1 kΩ, CL = 100 pF
SO output delay time
tKSO
from SCK ↓
Internal pull-up,
CL = 100 pF
26
Remark RL: load resistance of output line
CL: load capacitance of output line
VDD
RL
Output line
CL
Serial transfer timing
t
KCY
t
KL
t KH
SCK
t
SIK
t KSI
Input data
SI
t
KSO
SO
Output data
85
µPD17145(A1), 17147(A1), 17149(A1)
A/D Converter (VDD = 4.0 to 5.5 V, Ta = –40 to +110 °C)
Parameter
Resolution
Symbol
Condition
MIN.
8
TYP.
8
MAX.
8
Unit
bit
Absolute accuracyNote 1
Conversion timeNote 2
Analog input voltage
Reference input voltage
A/D converter circuit current
VREF pin current
2.5 V ≤ VREF ≤ VDD
±1.5
25 tCY
VREF
VDD
LSB
µs
tCONV
VADIN
VREF
IADC
0
V
2.5
V
When A/D converter operates
1.0
0.1
2.0
mA
mA
IREF
0.3
Notes 1. Absolute accuracy excluding quantization error (±0.5LSB)
2. Time since a conversion start instruction has been executed until conversion ends (ADCEND =
1) (50 µs at 8 MHz).
Remark tCY = 16/fx (fx: system clock oscillation frequency)
POC Circuit (mask optionNote 1) (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)
Parameter
Symbol
VPOC
Condition
MIN.
3.6
TYP.
4.0
MAX.
4.45
0.08
Unit
V
POC detection voltageNote 2
Supply voltage fall speed
Reset detection pulse width
POC circuit current
tPOCS
tSAMP
IPOC
V/ms
ms
1
3.0
10
µA
Notes 1. The POC circuit can be used in an application circuit that operates at VDD = 4.5 to 5.5 V,
fx = 400 kHz to 4 MHz.
2. This is the voltage at which the POC circuit clears its internal reset operation. The internal reset
is cleared when VPOC < VDD.
86
µPD17145(A1), 17147(A1), 17149(A1)
Oscillator Characteristics (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C)
ResonatorNote
Symbol
Condition
MIN.
0.39
0.39
0.39
TYP.
MAX.
2.04
4.08
8.16
Unit
MHz
MHz
MHz
Ceramic resonator
Oscillation frequency
VDD = 3.6 to 5.5 V
VDD = 4.5 to 5.5 V
Note
Do not use a resonator whose oscillation growth time exceeds 2 ms.
Recommended Ceramic Resonator (Ta = –40 to +110 °C)
Recommended Constants
Operating Supply Voltage [V]
Manufac-
Part Number
Remark
turer
C1 [pF]
220
C2 [pF]
220
Rd [kΩ]
MIN.
2.7
2.7
2.7
3.6
3.6
4.5
4.5
MAX.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
CSB400JA
5.6
0
CSA2.00MGA040
100
100
For
CST2.00MGA040 Unnecessary (C-contained type)
0
automotive
electronics
Murata
CSA4.00MGA
CST4.00MGWA
CSA8.00MTZA
CST8.00MTWA
30
Unnecessary (C-contained type)
30 30
Unnecessary (C-contained type)
30
0
Mfg. Co.
0
0
0
External Circuit Example
XIN
X
OUT
Rd
C1
C2
87
µPD17145(A1), 17147(A1), 17149(A1)
23. CHARACTERISTIC CURVE (REFERENCE VALUE)
(Ta = 25 ˚C)
4.0
XIN
XOUT
C1
C2
3.0
2.0
1.0
CSA 8.00MTZA (C1 = C2 = 30 pF)
CSA 4.00MGA (C1 = C2 = 30 pF)
CSA 2.00MGA040 (C1 = C2 = 100 pF)
Operation mode (8 MHz)
Operation mode (4 MHz)
Operation mode (2 MHz)
HALT mode (8 MHz)
HALT mode (2 MHz)
HALT mode (4 MHz)
2.7
3.6
5.5
0
2.0
3.0
4.0
5.0
Supply voltage VDD [V]
IOL vs. VOL Characteristic Example 1 (P0A, P0B, P0C)
(Ta = 25 ˚C)
20
15
10
5
VDD = 5.0 V
V
DD = 4.5 V
VDD = 3.5 V
0
1
2
3
Low-level output voltage VOL [V]
Caution The absolute maximum rating is 15 mA (peak value) per pin.
88
µPD17145(A1), 17147(A1), 17149(A1)
IOL vs. VOL Characteristics Example 2 (P0D, P0E)
(Ta = 25 ˚C)
30
V
DD = 5.0 V
DD = 4.5 V
V
VDD = 3.5 V
20
10
0
1
2
Low-level output voltage VOL [V]
Caution The absolute maximum rating is 30 mA (peak value) per pin.
IOH vs. (VDD - VOH) Characteristic Example
(Ta = 25 ˚C)
– 20
– 15
– 10
– 5
VDD = 5.0 V
V
DD = 4.5 V
DD = 3.5 V
V
0
1
2
3
V
DD – VOH [V]
Caution The absolute maximum rating is –15 mA (peak value) per pin.
89
µPD17145(A1), 17147(A1), 17149(A1)
24. PACKAGE DRAWINGS
28 PIN PLASTIC SHRINK DIP (400 mil)
28
15
1
14
A
K
L
F
C
B
M
M
R
N
D
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch)
of its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
B
C
28.46 MAX.
2.67 MAX.
1.778 (T.P.)
1.121 MAX.
0.106 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.85 MIN.
3.2±0.3
0.033 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.400 (T.P.)
0.339
0.51 MIN.
4.31 MAX.
5.08 MAX.
10.16 (T.P.)
8.6
J
K
L
+0.10
0.25
+0.004
0.010
M
–0.05
–0.003
N
R
0.17
0.007
0~15°
0~15°
S28C-70-400B-1
Caution The ES model differs from the mass-produced model in terms of outline dimensions and
materials. Refer to the drawing of the ES model.
90
µPD17145(A1), 17147(A1), 17149(A1)
28 PIN PLASTIC SOP (375 mil)
28
15
detail of lead end
1
14
A
H
I
J
L
B
C
N
M
M
D
P28GT-50-375B-1
NOTE
ITEM
MILLIMETERS
18.2 MAX.
INCHES
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
A
B
C
D
E
F
0.717 MAX.
0.034 MAX.
0.845 MAX.
1.27 (T.P.)
0.050 (T.P.)
+0.10
+0.004
0.40
0.016
–0.05
–0.003
0.125 0.075
2.9 MAX.
2.50 0.2
10.3 0.3
7.2 0.2
0.005 0.003
0.115 MAX.
+0.009
G
H
I
0.098
–0.008
+0.012
0.406
–0.013
+0.009
0.283
–0.008
J
1.6 0.2
0.063 0.008
+0.10
+0.004
K
L
0.15
0.006
–0.05
–0.002
+0.009
0.8 0.2
0.12
0.031
–0.008
M
N
0.005
0.004
0.10
Caution The ES model differs from the mass-produced model in terms of outline dimension and
materials. Refer to the drawing of the ES model.
91
µPD17145(A1), 17147(A1), 17149(A1)
28 PIN CERAMIC SHRINK DIP (400 mil) (For ES)
28
15
1
14
A
K
L
F
C
B
R
M
M
N
D
NOTES
ITEM MILLIMETERS
INCHES
1.103 MAX.
0.201 MAX.
0.070 (T.P.)
0.018±0.002
0.031 MIN.
0.118±0.04
0.039 MIN.
0.106
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
28.0 MAX.
5.1 MAX.
1.778 (T.P.)
0.46±0.05
0.8 MIN.
3.0±1.0
2) ltem "K" to center of leads when formed parallel.
1.0 MIN.
2.7
J
4.3 MAX.
10.16 (T.P.)
9.84
0.170 MAX.
0.400 (T.P.)
0.387
K
L
+0.002
0.010
M
0.25±0.05
–0.003
N
R
0.25
0.010
0~15°
0~15°
P28D-70-400B-1
92
µPD17145(A1), 17147(A1), 17149(A1)
28 PIN CERAMIC SOP (For ES)
A
D
C
NOTE
ITEM MILLIMETERS
INCHES
+0.008
0.709
The lengths of leads ( 1 ) and the height of potting ( 2 ) are
not to be specified because the lead cutting process and
the potting process are not controlled.
A
18.0±0.2
–0.009
0.05 (T.P.)
+0.002
C
D
1.27 (T.P.)
0.4±0.05
0.016
–0.003
G
I
1.52±0.15
8.4±0.15
0.06±0.006
+0.006
0.331
–0.007
J
K
T
16.4
0.646
0.15±0.025
1.0
0.006±0.001
0.039
X28B-50B1
93
µPD17145(A1), 17147(A1), 17149(A1)
25. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For the other soldering conditions and methods, consult NEC.
Table 25-1. Soldering Conditions of Surface Mount Type
µPD17145GT(A1)-×××: 28-pin plastic SOP (375 mil)
µPD17147GT(A1)-×××: 28-pin plastic SOP (375 mil)
µPD17149GT(A1)-×××: 28-pin plastic SOP (375 mil)
Symbol of Recommended
Soldering Method
Soldering Condition
Condition
Package peak temperature: 235 °C, Time: 30 seconds max.
(210 °C min.), Number of times: 2 max., DurationNote
:
7 (after that, prebaking is necessary for 20 hours at 125 °C.)
<Remarks>
Infrared reflow
IR35-207-2
(1) Start second reflow after the device temperature that has
risen because of the first reflow has fallen to room
temperature.
(2) Do not clean flux with water after the first reflow.
Package peak temperature: 215 °C, Time: 40 seconds max.
(200 ˚C min.), Number of times: 2 max., DurationNote
:
7 (after that, prebaking is necessary for 20 hours at 125 °C.)
<Remarks>
VPS
VP15-207-2
(1) Start second reflow after the device temperature that has
risen because of the first reflow has fallen to room
temperature.
(2) Do not clean flux with water after the first reflow.
Pin partial heating
Pin temperature: 300 °C max., Time: 3 seconds max. (per side
—
of device)
Note
Number of storage days after the dry pack was opened. Storage conditions: 25 °C, 65 %RH max.
Caution Do not use two or more soldering methods in combination (except pin partial heating).
94
µPD17145(A1), 17147(A1), 17149(A1)
Table 25-2. Soldering Conditions of Insertion Type
µPD17145CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)
µPD17147CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)
µPD17149CT(A1)-×××: 28-pin plastic shrink DIP (400 mil)
Soldering Method
Wave soldering (pin only)
Pin partial heating
Soldering Condition
Solder bath temperature: 260 ˚C max., Time: 10 seconds max.
Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of pin)
Caution When performing wave soldering, exercise care that only the pins are wetted with solder
and that no part of the package must be wetted.
95
µPD17145(A1), 17147(A1), 17149(A1)
APPENDIX A. FUNCTION COMPARISON BETWEEN µPD17145 SUBSERIES AND THE µPD17135A
AND 17137A
µPD17145
µPD17147
4 KB
µPD17149
µPD17135A
µPD17137A
ROM
RAM
Stack
2 KB
8 KB
2 KB
4 KB
110 × 4 bits
112 × 4 bits
Address stack × 5 levels
Interrupt stack × 3 levels
Instruction execution time
(clock, operating voltage)
2 µs (8 MHz, 4.5 to 5.5 V)
4 µs (4 MHz, 3.6 to 5.5 V)
8 µs (2 MHz, 2.7 to 5.5 V)
2 µs (8 MHz, 4.5 to 5.5 V)
4 µs (4 MHz, 2.7 to 5.5 V)
CMOS I/O
Input
12 (P0A, P0B, P0C)
2 (P0F0, P0F1)
1 (INT)
1 (P1B0)
1 (INT)
Sense input
I/O
Can be pulled up by mask option
N-ch open-drain I/O
8 (P0D, P0E voltage: VDD)
P0D pull-up: software
P0E pull-up: software
8 (P0D, P1A voltage: 9 V)
P0D pull-up: mask option
P1A pull-up: mask option
Internal pull-up resistor
100 kΩ TYP. (except P0D)
10 kΩ TYP. (P0D)
100 kΩ TYP.
A/D converter
8 bits × 4 channels
8 bits × 4 channels
(VDD = 4.5 to 5.5 V)
(operating voltage)
Reference voltage pin
8-bit (TM0, TM1)
(VDD = 4.0 to 5.5 V)
VREF (VREF = 2.5 V to VDD)
None (VREF = VADC = VDD)
2 (timer output: TM1OUT)
2 (timer output: TM0OUT)
TM0 clock:
system clock/512
system clock/64
system clock/16
INT
TM0 clock:
system clock/256
system clock/64
system clock/16
INT
TM1 clock:
system clock/8192
system clock/128
system clock/16
TM0 count up
TM1 clock:
system clock/1024
system clock/512
system clock/256
TM0 count up
Basic interval (BTM)
1 (also used as watchdog timer)
Count clock: system clock/16384
system clock/4096
1 (also used as watchdog timer)
Count clock: system clock/8192
system clock/4096
system clock/512
TM0 count up
system clock/16
INT
Interrupt
SIO
External
1
1
(with AC zero cross detection)
Internal
4 (TM0, TM1, BTM, SIO)
1 (clocked 3-wire)
Output latch
Independent of P0D1 latch
HALT, STOP
Shared with P0D1 latch
HALT, STOP
Standby function
(can be released by RLS input pin)
96
µPD17145(A1), 17147(A1), 17149(A1)
µPD17145
µPD17147
µPD17149
µPD17135A
µPD17137A
Oscillation stabilization
wait time
128 × 256 counts
512 × 256 counts
POC function
Package
Mask option
Internal
28-pin plastic SDIP (400 mil)
28-pin plastic SOP (375 mil)
One-time PROM
µPD17P149
µPD17P137A
Caution The µPD17145 subseries is not pin-compatible with the µPD17135A and 17137A. The
µPD17145 subseries does not include a product equivalent to the µPD17134A and 17136A
(RC oscillation type). For the electrical specifications of each product, refer to the Data
Sheet of the product.
97
µPD17145(A1), 17147(A1), 17149(A1)
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for developing programs for the µPD17145(A1), 17147(A1),
and 17149(A1):
Hardware
Name
Outline
IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators that can be used with any
products in the 17K series. IE-17K and IE-17K-ET are connected to PC-9800 series
or IBM PC/AT as the host machine with RS-232-C. EMU-17K is inserted into an
expansion slot of the PC-9800 series.
In-circuit emulator
IE-17K,
These in-circuit emulators operate as the emulator for a device when used in
combination with the dedicated system evaluation board (SE board) of the device.
When man-machine interface, SIMPLEHOST , is used a sophisticated debugging
environment can be realized. EMU-17K also has a function that allows real-time
monitoring of the contents of the data memory.
IE-17K-ETNote 1
EMU-17KNote 2
,
SE board (SE-17145)
SE-17145 is an SE board for the µPD17145 subseries. It can be used alone to
evaluate the system, or in combination with an in-circuit emulator for debugging.
Emulation probe
(EP-17K28CT)
EP-17K28CT is an emulation probe for the 17K series 28-pin shrink DIP (400 mil).
Emulation probe
(EP-17K28GT)
EP-17K28GT is an emulation probe for the 17K series 28-pin SOP (375 mil).
It connects the SE board and target system when used with EV-9500GT-28Note 3
.
Conversion adapter
(EV-9500GT-28Note 3
EV-9500GT-28 is an adapter for the 28-pin SOP (375 mil). It is used to connect EP-
17K28GT and target system.
)
PROM programmerNote 4
(AF-9703, AF-9704,
AF-9705 or AF-9706)
AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers supporting the
µPD17P149. By connecting programmer adapter AF-9808M to these programmers,
the µPD17P149 can be programmed.
Programmer adapterNote 4
(AF-9808M)
AF-9808M is an adapter used to program the µPD17P149, in combination with AF-
9703, AF-9704, AF-9705, or AF-9706.
Notes 1. Low-cost model: external power supply type
2. This is a product of IC Corporation. For details, consult IC Corporation (Tokyo (03) 3447-3793).
3. Two EV-97500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are separately
available as a set.
4. These are products of Ando Electric Corporation. For details, consult Ando Electric Corporation
(Tokyo (03) 3733-1151).
98
µPD17145(A1), 17147(A1), 17149(A1)
Software
Supply
Outline
Name
Host Machine
OS
Order Code
µS5A10AS17K
µS5A13AS17K
µS7B10AS17K
µS7B13AS17K
µS5A10AS17145Note
µS5A13AS17145Note
µS7B10AS17145Note
µS7B13AS17145Note
µS5A10IE17K
µS5A13IE17K
µS7B10IE17K
µS7B13IE17K
Media
AS17K is an assembler that
can be used with any prod-
ucts in the 17K series. To
develop the program of the
µPD17145(A1), 17147(A1),
and 17149(A1), the AS17K
and a device file (AS17145,
AS17147, or AS17149) are
used in combination.
5"2HD
PC-9800
series
MS-DOS
17K series
assembler
(AS17K)
3.5"2HD
5"2HC
IBM PC/AT
PC DOS
3.5"2HC
5"2HD
AS17145, AS17147, and
AS17149 are device files
for the µPD17145(A1),
17147(A1), 17149(A1),
and µPD17P149. They can
be used in combination with
the assembler for the 17K
series (AS17K).
PC-9800
series
Device file
MS-DOS
PC DOS
3.5"2HD
5"2HC
AS17145,
AS17147,
AS17149
IBM PC/AT
3.5"2HC
5"2HD
SIMPLEHOST is software that
serves as man-machine
PC-9800
series
MS-DOS
interface on Windows when
a program is developed by
using an in-circuit emulator
and a personal computer.
Support software
(SIMPLEHOST)
3.5"2HD
5"2HC
Windows
PC DOS
IBM PC/AT
3.5"2HC
Note
µS××××AS17145 includes AS17145, AS17147, and AS17149.
Remark The version of the OS supported is as follows:
OS
Version
MS-DOS
PC DOS
Windows
Ver. 3.30 to Ver. 5.00ANote
Ver. 3.1 to Ver. 5.0Note
Ver. 3.0 to Ver. 3.1
Note
Although MS-DOS Ver.5.00/5.00A and
PC DOS Ver. 5.0 have a task swap
function, this function cannot be used
with this software.
99
µPD17145(A1), 17147(A1), 17149(A1)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
100
µPD17145(A1), 17147(A1), 17149(A1)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 250-3583
Tel: 01-504-2787
Fax: 01908-670-290
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics Italiana s.r.1.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 08-63 80 388
Fax: 011-6465-6829
J97. 8
101
µPD17145(A1), 17147(A1), 17149(A1)
SIMPLEHOST is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corpora-
tion in the United States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
相关型号:
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Microcontroller, 4-Bit, MROM, 8MHz, CMOS, PDIP22, 0.300 INCH, SHRINK, PLASTIC, DIP-22
NEC
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