UPD431000AGU-B15X-9JH-A [RENESAS]
128KX8 STANDARD SRAM, 150ns, PDSO32, 8 X 13.40 MM, PLASTIC, TSOP1-32;
| 型号： | UPD431000AGU-B15X-9JH-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 128KX8 STANDARD SRAM, 150ns, PDSO32, 8 X 13.40 MM, PLASTIC, TSOP1-32 ISM频段 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
μPD431000A-X
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
Description
The μPD431000A-X is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The μPD431000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available.
In addition to this, A and B versions are low voltage operations.
The μPD431000A-X is packed in 32-pin PLASTIC SOP, 32-pin PLASTIC TSOP (I) (8 × 13.4 mm) and (8 × 20 mm).
Features
• 131,072 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Operating ambient temperature: TA = –25 to +85 °C
• Low VCC data retention: 2.0 V (MIN.)
• Output Enable input for easy application
• Two Chip Enable inputs: /CE1, CE2
Part number
Access time
ns (MAX.)
Operating supply Operating ambient
Supply current
voltage
V
temperature
°C
At operating At standby At data retention
mA (MAX.) μA (MAX.)
μA (MAX.) Note1
μPD431000A-xxX
μPD431000A-AxxX
70, 85
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
–25 to +85
70
50
2.5
70 Note2, 100
35 Note3
30 Note4
26 Note5
22 Note6
μPD431000A-BxxX 70 Note2, 100, 120, 150
Notes 1. TA ≤ 40 °C
2. VCC = 4.5 to 5.5 V
3. 70 mA (VCC > 3.6 V)
4. 70 mA (VCC > 3.3 V)
5. 50 μA (VCC > 3.6 V)
6. 50 μA (VCC > 3.3 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M10430EJBV0DS00 (11th edition)
Date Published November 2008
Printed in Japan
1995
μPD431000A-X
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient
Remark
voltage
V
temperature
°C
μPD431000AGW-70X
32-pin PLASTIC SOP
(13.34 mm (525))
70
4.5 to 5.5
–25 to +85
–
μPD431000AGZ-70X-KJH
μPD431000AGZ-85X-KJH
μPD431000AGZ-A10X-KJH
μPD431000AGZ-B10X-KJH
μPD431000AGZ-B12X-KJH
μPD431000AGZ-B15X-KJH
μPD431000AGU-B10X-9JH
μPD431000AGU-B12X-9JH
μPD431000AGU-B15X-9JH
μPD431000AGW-70X-A
32-pin PLASTIC TSOP (I)
(8 × 20) (Normal bent)
85
100
100
120
150
100
120
150
70
3.0 to 5.5
2.7 to 5.5
A version
B version
32-pin PLASTIC TSOP (I)
2.7 to 5.5
4.5 to 5.5
B version
(8 × 13.4) (Normal bent)
32-pin PLASTIC SOP
(13.34 mm (525))
–
μPD431000AGZ-70X-KJH-A
μPD431000AGZ-85X-KJH-A
32-pin PLASTIC TSOP (I)
(8 × 20) (Normal bent)
85
μPD431000AGZ-A10X-KJH-A
100
3.0 to 5.5
2.7 to 5.5
A version
B version
μPD431000AGZ-B10X-KJH-A
μPD431000AGZ-B12X-KJH-A
μPD431000AGZ-B15X-KJH-A
100
120
150
100
120
150
μPD431000AGU-B10X-9JH-A 32-pin PLASTIC TSOP (I)
μPD431000AGU-B12X-9JH-A (8 × 13.4) (Normal bent)
μPD431000AGU-B15X-9JH-A
2.7 to 5.5
B version
Remark Products with -A at the end of the part number are lead-free products.
2
Data Sheet M10430EJBV0DS
μPD431000A-X
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-pin PLASTIC SOP (13.34 mm (525))
[μPD431000AGW-xxX]
[μPD431000AGW-xxX-A]
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
2
A15
CE2
/WE
A13
A8
3
4
5
A6
6
A5
7
A9
A4
8
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O1
I/O2
I/O3
GND
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark
3
Data Sheet M10430EJBV0DS
μPD431000A-X
32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
[μPD431000AGZ-xxX-KJH]
[μPD431000AGZ-AxxX-KJH]
[μPD431000AGZ-BxxX-KJH]
[μPD431000AGZ-xxX-KJH-A]
[μPD431000AGZ-AxxX-KJH-A]
[μPD431000AGZ-BxxX-KJH-A]
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
A0 - A16 : Address inputs
I/O1 - I/O8: Data inputs / outputs
/CE1, CE2: Chip Enable 1, 2
/OE : Output Enable
VCC : Power supply
GND : Ground
/WE
: Write Enable
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M10430EJBV0DS
μPD431000A-X
32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
[μPD431000AGU-BxxX-9JH]
[μPD431000AGU-BxxX-9JH-A]
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M10430EJBV0DS
μPD431000A-X
Block Diagram
VCC
GND
A0
A16
Address
buffer
Row
decoder
Memory cell array
1,048,576 bits
Sense amplifier /
Switching circuit
I/O1
Input data
controller
Output data
controller
I/O8
Column decoder
Address buffer
/CE1
CE2
/OE
/WE
Truth Table
/CE1
CE2
×
/OE
×
/WE
×
Mode
I/O
Supply current
H
×
L
L
L
Not selected
High impedance
ISB
L
×
×
H
H
L
H
Output disable
Read
ICCA
H
H
DOUT
DIN
H
×
L
Write
Remark × : VIH or VIL
6
Data Sheet M10430EJBV0DS
μPD431000A-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
–0.5 Note to +7.0
–0.5 Note to VCC + 0.5
–25 to +85
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
μPD431000A-xxX μPD431000A-AxxX μPD431000A-BxxX
Unit
MIN.
4.5
MAX.
5.5
MIN.
3.0
MAX.
5.5
MIN.
2.7
MAX.
5.5
Supply voltage
VCC
VIH
VIL
TA
V
V
High level input voltage
2.4
VCC+0.5
+0.6
2.4
VCC+0.5
+0.5
2.4
VCC+0.5
+0.5
Low level input voltage
–0.3 Note
–25
–0.3 Note
–25
–0.3 Note
–25
V
Operating ambient temperature
+85
+85
+85
°C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Input / Output capacitance
Symbol
CIN
Test conditions
MIN.
TYP.
MAX.
6
Unit
pF
VIN = 0 V
VI/O = 0 V
CI/O
10
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are not 100% tested.
7
Data Sheet M10430EJBV0DS
μPD431000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
μPD431000A-xxX
μPD431000A-AxxX μPD431000A-BxxX Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 –1.0
+1.0 –1.0
+1.0
+1.0
μA
μA
I/O leakage
current
ILO
VI/O = 0 V to VCC,
/CE1 = VIH or CE2 = VIL
or /WE = VIL or /OE = VIH
/CE1 = VIL, CE2 = VIH,
Operating
ICCA1
ICCA2
ICCA3
40
–
70
–
40
15
70
35
–
40
–
70
–
mA
supply current
II/O = 0 mA
VCC ≤ 3.6 V
Minimum cycle time VCC ≤ 3.3 V
/CE1 = VIL, CE2 = VIH,
–
15
30
15
–
15
–
15
10
–
II/O = 0 mA,
VCC ≤ 3.6 V
VCC ≤ 3.3 V
Cycle time = ∞
–
8
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
Cycle time = 1 μs, II/O = 0 mA,
10
10
10
VIL ≤ 0.2 V,
VCC ≤ 3.6 V
VCC ≤ 3.3 V
–
–
8
–
–
7
VIH ≥ VCC – 0.2 V
Standby
ISB
ISB1
ISB2
/CE1 = VIH or CE2 = VIL
VCC ≤ 3.6 V
3
3
3
mA
supply current
–
2
–
VCC ≤ 3.3 V
–
–
2
/CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V
1
–
–
1
–
–
50
–
–
0.5
–
50
26
–
–
–
50
–
μA
VCC ≤ 3.6 V
VCC ≤ 3.3 V
–
0.5
–
22
50
–
CE2 ≤ 0.2 V
50
–
–
50
26
–
VCC ≤ 3.6 V
VCC ≤ 3.3 V
0.5
–
–
–
0.5
22
High level
VOH
VOL
IOH = –1.0 mA, VCC ≥ 4.5 V
IOH = –0.5 mA
2.4
–
2.4
2.4
0.4
–
2.4
2.4
0.4
0.4
V
V
output voltage
Low level
IOL = 2.1 mA, VCC ≥ 4.5 V
IOL = 1.0 mA
0.4
0.4
output voltage
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
8
Data Sheet M10430EJBV0DS
μPD431000A-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[μPD431000A-70X, μPD431000A-85X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
Test points
1.5 V
1.5 V
0.6 V
Output Waveform
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tCO1, tCO2, tOE, tOH)
(tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
1.8 kΩ
I/O (Output)
I/O (Output)
990 Ω
990 Ω
100 pF
5 pF
CL
CL
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[μPD431000A-A10X, μPD431000A-B10X, μPD431000A-B12X, μPD431000A-B15X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
Test points
1.5 V
1.5 V
0.5 V
Output Waveform
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Part number
Output load condition
tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW
μPD431000A-A10X, μPD431000A-B10X, μPD431000A-B12X
μPD431000A-B15X
1TTL + 50 pF
1TTL + 100 pF
1TTL + 5 pF
1TTL + 5 pF
9
Data Sheet M10430EJBV0DS
μPD431000A-X
Read Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
VCC ≥ 3.0 V
Unit Condition
μPD431000A-70X μPD431000A-85X μPD431000A-A10X
μPD431000A-AxxX
μPD431000A-BxxX
MIN.
70
MAX.
MIN.
85
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
ns
Address access time
70
70
70
35
85
85
85
45
100
100
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
25
25
25
30
30
30
35
35
35
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/2)
Parameter
Symbol
VCC ≥ 2.7 V
μPD431000A-B10X μPD431000A-B12X μPD431000A-B15X
Unit Condition
MIN.
100
MAX.
MIN.
120
MAX.
MIN.
150
MAX.
Read cycle time
tRC
tAA
ns
Address access time
100
100
100
50
120
120
120
60
150
150
150
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
35
35
35
40
40
40
50
50
50
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
10
Data Sheet M10430EJBV0DS
μPD431000A-X
Read Cycle Timing Chart
t
RC
Address (Input)
/CE1 (Input)
t
AA
t
OH
t
CO1
CO2
t
t
HZ1
t
t
LZ1
CE2 (Input)
/OE (Input)
t
HZ2
LZ2
t
OE
t
OHZ
t
OLZ
High impedance
I/O (Output)
Data out
Remark In read cycle, /WE should be fixed to high level.
11
Data Sheet M10430EJBV0DS
μPD431000A-X
Write Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
VCC ≥ 3.0 V
Unit Condition
μPD431000A-70X μPD431000A-85X μPD431000A-A10X
μPD431000A-AxxX
μPD431000A-BxxX
MIN.
70
55
55
55
0
MAX.
MIN.
85
70
70
70
0
MAX.
MIN.
100
80
80
80
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
tAS
Write pulse width
tWP
tWR
tDW
tDH
50
5
60
5
60
0
Write recovery time
Data valid to end of write
Data hold time
35
0
35
0
60
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
25
30
35
ns
ns
Note
5
5
5
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Write Cycle (2/2)
Parameter
Symbol
VCC ≥ 2.7
μPD431000A-B10X μPD431000A-B12X μPD431000A-B15X
Unit Condition
MIN.
100
80
80
80
0
MAX.
MIN.
120
100
100
100
0
MAX.
MIN.
150
120
120
120
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
tAS
Write pulse width
tWP
tWR
tDW
tDH
60
0
85
100
0
Write recovery time
0
Data valid to end of write
Data hold time
60
0
60
80
0
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
35
40
50
ns
ns
Note
5
5
5
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M10430EJBV0DS
μPD431000A-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
t
CW1
CW2
/CE1 (Input)
CE2 (Input)
t
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
13
Data Sheet M10430EJBV0DS
μPD431000A-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
Address (Input)
t
AS
t
CW1
/CE1 (Input)
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
DW
t
DH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
Address (Input)
/CE1 (Input)
CE2 (Input)
t
CW1
t
AS
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
14
Data Sheet M10430EJBV0DS
μPD431000A-X
Low VCC Data Retention Characteristics (TA = –25 to +85 °C)
Parameter
Symbol
Test Condition
μPD431000A-xxX
μPD431000A-AxxX
μPD431000A-BxxX
Unit
MIN.
TYP.
MAX.
Data retention supply voltage
Data retention supply current
VCCDR1
/CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V
2.0
2.0
5.5
5.5
V
VCCDR2 CE2 ≤ 0.2 V
ICCDR1
ICCDR2
tCDR
VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V
VCC = 3.0 V, CE2 ≤ 0.2 V
0.5
0.5
20 Note
20 Note
μA
ns
ms
Chip deselection
0
5
to data retention mode
Operation recovery time
tR
Note 2.5 μA (TA ≤ 40 °C)
15
Data Sheet M10430EJBV0DS
μPD431000A-X
Data Retention Timing Chart
(1) /CE1 Controlled
t
CDR
Data retention mode
t
R
V
CC
4.5 VNote
/CE1
V
IH (MIN.)
VCCDR (MIN.)
/CE1 ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or
CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
t
CDR
Data retention mode
t
R
V
CC
4.5 VNote
V
IH (MIN.)
V
CCDR (MIN.)
CE2
VIL (MAX.)
CE2 ≤ 0.2 V
GND
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
16
Data Sheet M10430EJBV0DS
μPD431000A-X
Package Drawings
32-PIN PLASTIC SOP (13.34 mm (525))
32
17
detail of lead end
P
1
16
A
H
F
I
G
J
S
B
L
N
S
C
K
D
M
M
ITEM MILLIMETERS
E
A
B
C
20.61 MAX.
0.78 MAX.
1.27 (T.P.)
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.10
0.40
D
−0.05
E
F
G
H
I
0.15 0.05
2.95 MAX.
2.7
14.1 0.3
11.3
J
1.4 0.2
+0.10
0.20
K
−0.05
L
M
N
0.8 0.2
0.12
0.10
+7°
3°
P
−3°
P32GW-50-525A-1
17
Data Sheet M10430EJBV0DS
μPD431000A-X
32-PIN PLASTIC TSOP(I) (8x20)
detail of lead end
1
32
F
G
R
Q
L
16
17
S
E
P
I
J
A
S
C
B
M
D
M
K
N
S
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
8.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
0.97 0.08
18.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
K
L
M
N
P
0.10
0.10
20.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S32GZ-50-KJH1-2
18
Data Sheet M10430EJBV0DS
μPD431000A-X
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
S
T
R
L
16
17
U
Q
P
I
J
A
G
S
H
B
C
M
K
N
S
D
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
1.0 0.05
12.4 0.2
11.8 0.1
0.8 0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4 0.2
0.1 0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6 0.15
P32GU-50-9JH-2
19
Data Sheet M10430EJBV0DS
μPD431000A-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD431000A-X.
Types of Surface Mount Device
μPD431000AGW-xxX
: 32-pin PLASTIC SOP (13.34 mm (525))
μPD431000AGZ-xxX-KJH
: 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGZ-AxxX-KJH : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGZ-BxxX-KJH : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGU-BxxX-9JH : 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
μPD431000AGW-xxX-A
: 32-pin PLASTIC SOP (13.34 mm (525))
μPD431000AGZ-xxX-KJH-A : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGZ-AxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGZ-BxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent)
μPD431000AGU-BxxX-9JH-A : 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
20
Data Sheet M10430EJBV0DS
μPD431000A-X
Revision History
Edition/
Page
This Previous
Type of
revision
Description
Date
edition
edition
11th edition/
Nov. 2008
through
through
Modification Ordering Information revised.
21
Data Sheet M10430EJBV0DS
μPD431000A-X
[MEMO]
22
Data Sheet M10430EJBV0DS
μPD431000A-X
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
23
Data Sheet M10430EJBV0DS
μPD431000A-X
•
The information in this document is current as of November, 2008. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data
books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or
types are available in every country. Please check with an NEC Electronics sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on
a
customer-designated "quality assurance program" for a specific application. The recommended applications
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support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
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