UPD44164365AF5-E40-EQ2-A [RENESAS]
512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165;
| 型号： | UPD44164365AF5-E40-EQ2-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总42页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
18M-BIT DDRII SRAM SEPARATE I/O
2-WORD BURST OPERATION
Description
The μPD44164085A-A is a 2,097,152-word by 8-bit, the μPD44164095A-A is a 2,097,152-word by 9-bit, the
μPD44164185A-A is a 1,048,576-word by 18-bit and the μPD44164365A-A is a 524,288-word by 36-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD44164085A-A, μPD44164095A-A, μPD44164185A-A and μPD44164365A-A integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the
positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA package (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports
• DDR read or write operation initiated each cycle
• Pipelined double data rate operation
• Separate data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
• User programmable impedance output
• Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
• Operating ambient temperature: Commercial TA = 0 to +70°C
(-E33, -E37, -E40, -E50)
Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M19868EJ1V0DS00 (1st edition)
Date Published July 2009
Printed in Japan
2009
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Ordering Information
(1) Operating Ambient Temperature TA = 0 to +70°C
Part number
Cycle
Time
ns
Clock
Frequency
MHz
Organization
(word x bit)
Package
Operating
Ambient
Temperature
μPD44164085AF5-E33-EQ2-A
μPD44164085AF5-E40-EQ2-A
μPD44164085AF5-E50-EQ2-A
μPD44164095AF5-E33-EQ2-A
μPD44164095AF5-E40-EQ2-A
μPD44164095AF5-E50-EQ2-A
μPD44164185AF5-E33-EQ2-A
μPD44164185AF5-E37-EQ2-A
μPD44164185AF5-E40-EQ2-A
μPD44164185AF5-E50-EQ2-A
μPD44164365AF5-E33-EQ2-A
μPD44164365AF5-E40-EQ2-A
μPD44164365AF5-E50-EQ2-A
3.3
4.0
5.0
3.3
4.0
5.0
3.3
3.7
4.0
5.0
3.3
4.0
5.0
300
250
200
300
250
200
300
270
250
200
300
250
200
2M x 8-bit
2M x 9-bit
1M x 18-bit
165-pin PLASTIC
BGA (13 x 15)
Commercial
(TA = 0 to +70°C)
Lead-free
512K x 36-bit
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
2
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
(2) Operating Ambient Temperature TA = –40 to +85°C
Part number
Cycle
Time
ns
Clock
Frequency
MHz
Organization
(word x bit)
Package
Operating
Ambient
Temperature
μPD44164085AF5-E37Y-EQ2-A
μPD44164085AF5-E40Y-EQ2-A
μPD44164085AF5-E50Y-EQ2-A
μPD44164095AF5-E37Y-EQ2-A
μPD44164095AF5-E40Y-EQ2-A
μPD44164095AF5-E50Y-EQ2-A
μPD44164185AF5-E37Y-EQ2-A
μPD44164185AF5-E40Y-EQ2-A
μPD44164185AF5-E50Y-EQ2-A
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
270
250
200
270
250
200
270
250
200
2M x 8-bit
2M x 9-bit
1M x 18-bit
165-pin PLASTIC
BGA (13 x 15)
Industrial
(TA = –40 to +85°C)
Lead-free
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
Data Sheet M19868EJ1V0DS
3
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Pin Configurations
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164085A-A]
2M x 8-bit
1
CQ#
NC
2
3
A
4
5
6
7
NC
NW0#
A
8
9
A
10
VSS
NC
NC
NC
D2
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
B
C
D
E
F
VSS
NC
NC
D4
R, W# NW1#
K#
K
LD#
A
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
NC
NC
Q7
A
A
NC
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
A
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
D5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
VREF
Q1
G
H
J
NC
DLL#
NC
VREF
NC
NC
Q6
K
L
NC
NC
NC
NC
NC
NC
TMS
NC
M
N
P
R
NC
NC
D7
NC
VSS
VSS
NC
NC
TCK
A
A
C
A
A
TDO
A
A
C#
A
A
A
: Address inputs
: Data inputs
DLL#
: DLL/PLL disable
D0 to D7
Q0 to Q7
LD#
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Data outputs
: Synchronous load
: Read Write input
TCK
TDO
VREF
VDD
R, W#
NW0#, NW1#
K, K#
: Nibble Write data select
: Input clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
NC
: No connection
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
4
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164095A-A]
2M x 9-bit
1
CQ#
NC
2
3
A
4
5
6
7
NC
BW0#
A
8
9
A
10
VSS
NC
NC
NC
D3
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
VSS
NC
NC
D5
R, W#
A
NC
NC
A
K#
K
LD#
A
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
A
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
VREF
Q2
G
H
J
NC
DLL#
NC
VREF
NC
NC
Q7
K
L
NC
NC
NC
NC
NC
D0
NC
M
N
P
R
NC
NC
D8
NC
VSS
VSS
NC
NC
TCK
A
A
C
A
A
TDO
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
DLL#
: DLL/PLL disable
D0 to D8
Q0 to Q8
LD#
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Data outputs
: Synchronous load
: Read Write input
TCK
TDO
VREF
VDD
R, W#
BW0#
K, K#
: Byte Write data select
: Input clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
NC
: No connection
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M19868EJ1V0DS
5
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164185A-A]
1M x 18-bit
1
CQ#
NC
2
3
4
5
6
7
NC
BW0#
A
8
9
A
10
VSS
NC
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
VSS
Q9
NC
R, W# BW1#
K#
K
LD#
A
D9
A
NC
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
A
VSS
NC
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
D6
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
Q12
D13
VREF
NC
NC
NC
VREF
Q4
G
H
J
NC
DLL#
NC
K
L
NC
NC
D3
NC
Q15
NC
NC
Q1
M
N
P
R
NC
NC
D17
NC
VSS
VSS
NC
D0
NC
A
A
C
A
A
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
DLL#
: DLL/PLL disable
D0 to D17
Q0 to Q17
LD#
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Data outputs
: Synchronous load
: Read Write input
TCK
TDO
VREF
VDD
R, W#
BW0#, BW1#
K, K#
: Byte Write data select
: Input clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
NC
: No connection
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 3A and 10A are expansion addresses: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.
2A and 10A of this product can also be used as NC.
6
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164365A-A]
512K x 36-bit
1
2
3
4
5
6
7
BW1#
BW0#
A
8
9
10
VSS
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
VSS
NC
R, W# BW2#
K#
K
LD#
A
NC
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
A
BW3#
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
A
A
C
A
A
D0
A
A
C#
A
A
A
TMS
A
: Address inputs
: Data inputs
DLL#
: DLL/PLL disable
D0 to D35
Q0 to Q35
LD#
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
TCK
TDO
VREF
VDD
R, W#
BW0# to BW3#
K, K#
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
NC
: No connection
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 3A, 9A and 10A are expansion addresses: 9A for 36Mb, 3A for 72Mb and 10A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M19868EJ1V0DS
7
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Pin Identification
(1/2)
Symbol
Description
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). These
inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
D0 to Dxx
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Q0 to Qxx
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges
if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the
LD# and R, W# command. See Pin Configurations for ball site location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
LD#
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).
R, W#
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#
is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times
around the rising edge of K.
BWx#
NWx#
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, #C is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and
C# are fixed to HIGH (i.e. toggle of C and C#)
K, K#
C, C#
8
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
(2/2)
Symbol
Description
CQ, CQ#
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also
stop.
ZQ
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be
connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon
power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
DLL#
DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL circuit being used, if DLL# = LOW. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a
10 kΩ or less resistor.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
VREF
VDD
IEEE 1149.1 Test Output: 1.8 V I/O level.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for
range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC
Operating Conditions and DC Characteristics for range.
VSS
NC
Power Supply: Ground
No Connect: These signals are not connected internally.
Data Sheet M19868EJ1V0DS
9
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Block Diagram
[μPD44164085A-A]
20
ADDRESS
LD#
ADDRESS
20
R, W#
REGISTRY
& LOGIC
K
K#
R, W#
NW0#
NW1#
220 x 16
DATA
16
16
8
2
16
8
D0 to D7
Q0 to Q7
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
LD#
CQ,
CQ#
K
K
K
C, C#
K#
OR
K, K#
[μPD44164095A-A]
20
ADDRESS
LD#
ADDRESS
REGISTRY
& LOGIC
20
R, W#
K
K#
R, W#
BW0#
220 x 18
DATA
18
18
9
2
18
9
D0 to D8
Q0 to Q8
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
LD#
CQ,
CQ#
K
K
K
C, C#
OR
K#
K, K#
10
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
[μPD44164185A-A]
19
ADDRESS
LD#
ADDRESS
19
R, W#
REGISTRY
& LOGIC
K
K#
R, W#
BW0#
BW1#
219 x 36
DATA
36
36
18
2
36
18
Q0 to Q17
REGISTRY
& LOGIC
D0 to D17
MEMORY
ARRAY
MUX
LD#
CQ,
CQ#
K
K
K
C, C#
K#
OR
K, K#
[μPD44164365A-A]
18
ADDRESS
LD#
ADDRESS
REGISTRY
& LOGIC
18
R, W#
K
K#
R, W#
BW0#
BW1#
BW2#
BW3#
218 x 72
DATA
72
72
36
2
72
Q0 to Q35
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
36
D0 to D35
CQ,
CQ#
LD#
K
K
K
C, C#
OR
K#
K, K#
Data Sheet M19868EJ1V0DS
11
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Power-on Sequence
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable.
1. Clock starts after VDD/VDDQ stable
The clock is supplied from a controller.
(a)
V
DD/VDDQ
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
DLL#
Clock
Fix HIGH (or tied to VDDQ)
20 ns (MIN.)
Clock Start Note
1,024 cycles or more
Stable Clock
Normal Operation
Start
Note Input a stable clock from the start.
(b)
V
DD/VDD
Q
DLL#
Clock
V
DD/VDDQ Stable (< 0.1 V DC per 50 ns)
Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation
Start
Clock Start
(c)
V
DD/VDDQ
V
DD/VDDQ Stable (< 0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
DLL#
Clock
30 ns. (MIN.)
Clock Stop
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation
Start
Clock Start
12
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
2. Clock starts before VDD/VDDQ stable
The clock is supplied from a clock generator.
(a)
V
DD/VDDQ
V
DD/VDDQ Stable (< 0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
DLL#
Clock
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation Start
30 ns. (MIN.)
Clock Stop
Clock Start
(b)
V
DD/VDDQ
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
30 ns (MIN.)
DLL# LOW
HIGH or LOW
DLL#
Clock
Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
1,024 cycles or more Normal
Stable Clock
Operation
Start
Clock keep running
Clock Start
Data Sheet M19868EJ1V0DS
13
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Truth Table
Operation
LD# R, W#
CLK
D or Q
Data in
WRITE cycle
L
L
L
L → H
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Input data
Input clock
D(A+0)
D(A+1)
K(t+1) ↑
K#(t+1) ↑
H
L → H
Data out
Output data
Output clock
D = X, Q = High-Z
Previous state
Load address, read data on two
consecutive C and C# rising edge
NOP (No operation)
Q(A+0)
Q(A+1)
C#(t+1) ↑
C(t+2) ↑
H
X
X
X
L → H
Clock stop
Stopped
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
14
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Byte Write Operation
[μPD44164085A-A]
Operation
K
L → H
–
K#
–
NW0#
NW1#
Write D0 to D7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
Write D0 to D3
Write D4 to D7
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44164095A-A]
Operation
K
L → H
–
K#
–
BW0#
Write D0 to D8
Write nothing
0
0
1
1
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44164185A-A]
Operation
K
K#
–
BW0#
BW1#
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
L → H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Data Sheet M19868EJ1V0DS
15
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
[μPD44164365A-A]
Operation
K
L → H
–
K#
–
BW0#
BW1#
BW2#
BW3#
Write D0 to D35
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
L → H
–
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
16
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Load, Count = 2
READ DOUBLE
Write
Read
WRITE DOUBLE
Count = Count + 2
Count = Count + 2
Load
NOP,
NOP,
Count = 2
Count = 2
NOP
NOP
Supply voltage provided
Power UP
Remark State machine control timing sequence is controlled by K.
Data Sheet M19868EJ1V0DS
17
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
Unit
V
Supply voltage
+2.5
Output supply voltage
Input voltage
VDDQ
VIN
VDD
V
VDD + 0.5 (2.5 V MAX.)
V
Input / Output voltage
Operating ambient temperature
VI/O
VDDQ + 0.5 (2.5 V MAX.)
V
TA
Commercial
Industrial
+70
+85
°C
–40
–55
Storage temperature
Tstg
+125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit
V
Note
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
VDDQ
VIH (DC)
VIL (DC)
VIN
1.4
VDD
V
1
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.95
V
1, 2
1, 2
1, 2
V
–0.3
V
VREF
0.68
V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions
Parameter
Input HIGH voltage
Input LOW voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
VREF + 0.2
–
TYP.
MAX.
–
Unit
V
Note
1
1
VREF – 0.2
V
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
18
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
DC Characteristics (VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit Note
x8, x9 x18
x36
Input leakage current
I/O leakage current
Operating supply
current
ILI
–2
–2
–
–
+2
+2
μA
μA
ILO
IDD
Note1
Commercial
-E33
-E37
-E40
-E50
-E37Y
520
–
570
520
490
420
540
510
430
300
290
280
260
310
300
280
VDDQ
660 mA
(TA = 0 to +70°C)
–
(Read cycle/
450
390
500
470
410
300
–
570
Write cycle)
490
Industrial
–
(TA = –40 to +85°C) -E40Y
-E50Y
–
–
Standby supply
current
ISB1
Note1
Commercial
-E33
-E37
-E40
-E50
-E37Y
300 mA
(TA = 0 to +70°C)
–
280
260
–
(NOP)
280
260
310
300
280
Industrial
(TA = –40 to +85°C) -E40Y
-E50Y
–
–
Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA
VOH Note2
VDDQ – 0.2
VDDQ/2–0.12
VSS
–
–
–
–
V
4, 5
4, 5
4, 5
4, 5
VDDQ/2+0.12
0.2
V
V
V
Output LOW voltage VOL(Low) IOL ≤ 0.1 mA
VOL Note3
VDDQ/2–0.12
VDDQ/2+0.12
Notes 1. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.
2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15 % for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15 for values of 175 Ω ≤ RQ ≤ 350 Ω.
4. AC load current is higher than the shown DC values.
5. HSTL outputs meet JEDEC HSTL Class I standards.
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
Input capacitance (Address, Control)
Input / Output capacitance
(D, Q, CQ, CQ#)
4
6
5
7
CI/O
VI/O = 0 V
pF
Clock Input capacitance
Cclk
Vclk = 0 V
5
6
pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Resistance
Parameter
Thermal resistance
Symbol
Test conditions
MIN.
TYP.
25.1
MAX.
Unit
θ j-a
°C/W
(junction – ambient)
Thermal resistance
(junction – case)
θ j-c
2.8
°C/W
Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.
Data Sheet M19868EJ1V0DS
19
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
AC Characteristics (VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD )
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.75 V
Test Points
0.25 V
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
V
DDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
20
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Read and Write Cycle
Parameter
Symbol
-E33
-E37, -E37Y -E40, -E40Y -E50, -E50Y Unit Note
(270 MHz)
(250 MHz) (200 MHz)
(300 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K→K#, C→C#)
TKHKH
TKC var
TKHKL
ns
ns
ns
ns
ns
1
2
3.7
−
8.4
0.2
−
4.0
–
8.4
0.2
–
5.0
–
8.4
0.2
–
3.3
–
8.4
0.2
–
1.5
1.5
1.7
1.6
1.6
1.8
2.0
2.0
2.2
1.32
1.32
1.49
TKLKH
TKHK#H
−
–
–
–
−
–
–
–
Clock# HIGH to Clock HIGH
(K#→K, C#→C)
TK#HKH
ns
ns
1.7
−
1.8
–
2.2
–
1.49
–
Clock to data clock
270 to 300 MHz TKHCH
250 to 270 MHz
200 to 250 MHz
167 to 200 MHz
133 to 167 MHz
< 133 MHz
0
1.45
1.65
1.8
2.3
2.8
3.55
–
–
–
1.65
1.8
2.3
2.8
3.55
–
–
–
–
–
–
–
(K→C, K#→C#)
0
0
–
–
0
0
0
0
1.8
2.3
2.8
3.55
–
–
0
–
0
0
2.3
2.8
3.55
–
0
0
0
0
0
0
0
0
DLL/PLL lock time (K, C)
K static to DLL/PLL reset
TKC lock
Cycle
ns
3
4
1,024
30
1,024
30
1,024
30
1,024
30
TKC reset
–
–
–
–
Output Times
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
TCHQV
TCHQX
ns
ns
ns
ns
ns
ns
ns
ns
−
−0.45
−
0.45
−
–
– 0.45
–
0.45
–
–
– 0.45
–
0.45
–
–
– 0.45
–
0.45
–
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
0.45
−
0.45
–
0.45
–
0.45
–
−0.45
−
– 0.45
–
– 0.45
–
– 0.45
–
5
5
0.3
−
0.3
–
0.35
–
0.27
–
−0.3
−
– 0.3
–
– 0.35
–
– 0.27
–
0.45
−
0.45
–
0.45
–
0.45
–
C HIGH to output Low-Z
TCHQX1
−0.45
– 0.45
– 0.45
– 0.45
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
TAVKH
TIVKH
ns
ns
6
6
0.5
0.5
−
−
0.5
0.5
–
–
0.6
0.6
–
–
0.4
0.4
–
–
Data inputs and write data select
inputs (BWx#, NWx#) valid to
K, K# rising edge
TDVKH
ns
6
−
0.35
–
0.4
–
0.3
–
0.35
Hold Times
K rising edge to address hold
K rising edge to
TKHAX
TKHIX
ns
ns
6
6
0.5
0.5
−
−
0.5
0.5
–
–
0.6
0.6
–
–
0.4
0.4
–
–
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs and
write data select inputs (BWx#, NWx#)
hold
TKHDX
ns
6
−
0.35
–
0.4
–
0.3
–
0.35
Data Sheet M19868EJ1V0DS
21
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in
this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DLL/PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
6. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
22
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Read and Write Timing
NOP
WRITE
(burst of 2)
WRITE
(burst of 2)
READ
(burst of 2)
READ
(burst of 2)
READ
(burst of 2)
NOP
1
2
3
4
5
6
7
8
K
TKHKL TKLKH
TKHKH
TKHK#H
TK#HKH
K#
LD#
TIVKH
R, W#
TKHIX
A0
A2
A4
TDVKH TKHDX
A1
A3
Address
TDVKH TKHDX
TKHAX
TAVKH
Data in
D21
D22
D31
D32
Data out
Q01
Q02
Q11
Q12
Q41
Q42
Qx2
TCHQX1
TCHQZ
TCQHQV
TCQHQX
TCHQX
TCHQX
TCHQV
TCHQV
CQ
TCHCQX
TCHCQV
CQ#
TCHCQX
TCHCQV
TKHCH
C
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
C#
Remarks 1. Q01 refers to output from address A0+0.
Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
2. Outputs are disabled (high impedance) 2.5 clocks after the last READ (LD# = LOW, R, W# = HIGH) is
input in the sequences of [READ]-[NOP] and [READ]-[WRITE].
3. In this example, if address A4 = A3, data Q41 = D31 and Q42 = D32.
Write data is forwarded immediately as read results.
Data Sheet M19868EJ1V0DS
23
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Application Example
R =
250 Ω
R =
250 Ω
ZQ
CQ#
CQ
Q
ZQ
CQ#
CQ
Q
. . .
SRAM#1
SRAM#4
D
A
D
A
LD# R, W# BWx# C/C# K/K#
LD# R, W# BWx# C/C# K/K#
V
t
SRAM
Controller
R
Data In
Vt
Data Out
Address
LD#
R
Vt
R
R, W#
BW#
SRAM#1 CQ/CQ#
Vt
R
R
SRAM#4 CQ/CQ#
Vt
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω
Vt = Vref
Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.
24
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
2R
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
10R
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
ILI
Conditions
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
μA
JTAG Input leakage current
JTAG I/O leakage current
0 V ≤ VIN ≤ VDD
–
–
ILO
0 V ≤ VIN ≤ VDDQ,
μA
Outputs disabled
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
VIH
VIL
1.3
–0.3
1.6
1.4
–
–
–
–
–
–
–
VDD+0.3
V
V
V
V
V
V
+0.5
–
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 μA
| IOHT | = 2 mA
IOLC = 100 μA
IOLT = 2 mA
–
JTAG output LOW voltage
0.2
0.4
–
Data Sheet M19868EJ1V0DS
25
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0 V
0.9 V
Test Points
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
26
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
JTAG AC Characteristics
Parameter
Clock
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
50
–
–
–
–
–
–
20
–
ns
MHz
ns
tTHTL
tTLTH
20
20
–
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
–
–
–
–
ns
ns
10
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
tMVTH
tDVTH
tCS
5
5
5
–
–
–
–
–
–
ns
ns
ns
Hold time
TMS hold time
tTHMX
tTHDX
tCH
5
5
5
–
–
–
–
–
–
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
JTAG Timing Diagram
t
THTH
TCK
t
MVTH
t
THTL
t
TLTH
TMS
TDI
t
THMX
t
DVTH
t
THDX
t
TLOV
t
TLOX
TDO
Data Sheet M19868EJ1V0DS
27
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
107
bit
Boundary register
bit
ID Register Definition
Part number
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 0001 1000
0000 0000 0101 0101
0000 0000 0001 1001
0000 0000 0001 1010
ID [11:1] vendor ID no. ID [0] fix bit
μPD44164085A-A
μPD44164095A-A
μPD44164185A-A
μPD44164365A-A
2M x 8
2M x 9
XXXX
XXXX
XXXX
XXXX
00000010000
00000010000
00000010000
00000010000
1
1
1
1
1M x 18
512K x 36
28
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
SCAN Exit Order
Bit
Signal name
x9 x18 x36
Bump
ID
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
no.
x8
no.
x8
X9
x18 x36
no.
x8
X9
x18 x36
1
C#
C
A
6R
6P
6N
7P
7N
7R
8R
8P
9R
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
NC
NC
NC
NC
Q4
D4
NC D15 10D
NC Q15 9E
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
NC
Q4
D4
NC
NC
NC
NC
NC
NC
Q5
D5
NC
NC
NC
NC
NC
NC
Q6
D6
NC
NC
NC
NC
NC
NC
Q7
D7
NC
NC Q28 2C
2
Q5 Q11 Q20 3E
D5 D11 D20 2D
3
Q7
D7
Q7 10C
D7 11D
4
A
NC
NC
NC D29 2E
NC Q29 1E
5
A
NC D16 9C
NC Q16 9D
6
A
NC Q12 Q21 2F
NC D12 D21 3F
7
A
Q8
D8
Q8 11B
D8 11C
8
A
NC
NC
NC D30 1G
NC Q30 1F
9
A
NC
NC
NC
NC
NC D17 9B
NC Q17 10B
11A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC Q0
NC D0
Q0
D0
Q0 11P
D0 10P
D9 10N
Q6 Q13 Q22 3G
D6 D13 D22 2G
CQ
–
Internal
NC NC NC
NC NC NC
NC
NC
NC D31
NC Q31
1J
2J
Q9
9P
A
A
A
NC
9A
8B
7C
6C
8A
NC NC
NC NC
Q1
D1
Q1 10M
D1 11N
A
A
A
NC Q14 Q23 3K
NC D14 D23 3J
NC NC NC D10 9M
NC NC NC Q10 9N
NC
NC
NC D32 2K
NC Q32 1K
LD#
NC
Q0
D0
Q1
D1
Q2
D2
Q2 11L
D2 11M
NC
NC BW1# 7A
Q7 Q15 Q24
D7 D15 D24
2L
3L
55 NW0# BW0# BW0# BW0# 7B
NC NC NC D11 9L
NC NC NC Q11 10L
56
57
58
K
6B
6A
NC
NC
NC D33 1M
NC Q33 1L
K#
NC NC
NC NC
Q3
D3
Q3 11K
D3 10K
NC
NC
NC BW3# 5B
NC Q16 Q25 3N
NC D16 D25 3M
59 NW1# NC BW1# BW2# 5A
NC NC NC D12 9J
NC NC NC Q12 9K
60
61
62
63
64
65
66
67
68
69
70
71
72
R, W#
4A
5C
4B
3A
1H
1A
NC
NC
NC D34 1N
NC Q34 2M
A
A
Q1
D1
Q2
D2
Q4
D4
Q4 10J
D4 11J
11H
Q8 Q17 Q26 3P
D8 D17 D26 2N
A
A
NC
NC
ZQ
DLL#
CQ#
100 NC
101 NC
102
NC
NC
NC D35 2P
NC NC NC D13 10G
NC NC NC Q13 9G
NC Q35 1P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q9 Q18 2B
D9 D18 3B
NC D27 1C
NC Q27 1B
A
A
A
A
A
A
3R
4R
4P
5P
5N
5R
NC NC
NC NC
Q5
D5
Q5 11F
D5 11G
103
104
NC NC NC D14 9F
NC NC NC Q14 10F
105
NC Q10 Q19 3D
NC D10 D19 3C
106
Q2
D2
Q3
D3
Q6
D6
Q6 11E
D6 10E
107
NC
NC D28 1D
Data Sheet M19868EJ1V0DS
29
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
JTAG Instructions
Instructions
EXTEST
Description
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
2
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
2
2
1
1
0
1
1
1
Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
30
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ, CQ#
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Q
EXTEST
0
1
0
1
0
1
0
1
0
1
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
Boundary Scan
Register
Remark The output pin statuses during each instruction vary
according to the Control-Register status (value of Boundary
Scan Register, bit no. 48).
CAPTURE
Register
There are three statuses:
SRAM
Output
Update
Register
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG ctrl”.
Update
QDR
Pad
SRAM
SRAM
Output
Driver
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
High-Z
High-Z
JTAG ctrl
Data Sheet M19868EJ1V0DS
31
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ, CQ#
Q
Pad
Pad
–
EXTEST
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Pad
Pad
–
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
No definition
–
–
Pad
Pad
Internal
Internal
–
Pad
Pad
Internal
Pad
–
No definition
–
–
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are
SRAM
Output
Update
Register
Pad
captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
32
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix
them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also
when the TAP controller is not used.
Data Sheet M19868EJ1V0DS
33
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
34
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
Data Sheet M19868EJ1V0DS
35
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Package Drawing
165-PIN PLASTIC BGA (13x15)
B
E
w
S
B
ZD
ZE
11
10
9
8
A
7
6
D
5
4
3
2
1
R P N M L K J H G F E D C B A
w
S A
INDEX MARK
A
A2
y1
S
S
y
e
S
A1
(UNIT:mm)
ITEM DIMENSIONS
M
φ
φ
x
b
S A B
D
E
13.00 0.10
15.00 0.10
0.15
w
e
1.00
A
1.40 0.11
0.40 0.05
1.00
A1
A2
b
0.50 0.05
0.08
x
y
0.10
y1
ZD
ZE
0.20
1.50
0.50
P165F5-100-EQ2
36
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44164085AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164095AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164185AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164365AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the
ground and so forth.
Data Sheet M19868EJ1V0DS
37
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
[ MEMO ]
38
Data Sheet M19868EJ1V0DS
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M19868EJ1V0DS
39
μPD44164085A-A, 44164095A-A, 44164185A-A, 44164365A-A
•
The information in this document is current as of July, 2009. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,
etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or
types are available in every country. Please check with an NEC Electronics sales representative for
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
•
•
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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persons, as the result of defects of NEC Electronics products.
•
•
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The "Specific" quality grade applies only to NEC Electronics products developed based on
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(Note)
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