UPD44321322F1-A60Y-FQ2 [RENESAS]
IC,SYNC SRAM,1MX32,CMOS,BGA,165PIN,PLASTIC;
| 型号： | UPD44321322F1-A60Y-FQ2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SYNC SRAM,1MX32,CMOS,BGA,165PIN,PLASTIC 静态存储器 |
| 文件： | 总40页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD44321182, 44321322, 44321362
32M-BIT ZEROSBTM SRAM
PIPELINED OPERATION
Description
The µPD44321182 is a 2,097,152-word by 18-bit, the µPD44321322 is a 1,048,576-word by 32-bit and the
µPD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using
full CMOS six-transistor memory cell.
The µPD44321182, µPD44321322 and µPD44321362 are optimized to eliminate dead cycles for read to write, or
write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst
counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD44321182, µPD44321322 and µPD44321362 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The µPD44321182, µPD44321322 and µPD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm
package thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.
Features
• Low voltage core supply : VDD = 3.3 ± 0.165V (-A44, -A50, -A60, -A44Y, -A50Y, -A60Y)
VDD = 2.5 ± 0.125V (-C50, -C60, -C50Y, -C60Y)
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -C50, -C60)
TA = –40 to +85 °C (-A44Y, -A50Y, -A60Y, -C50Y, -C60Y)
• 100 percent bus utilization
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• All registers triggered off positive clock edge
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4 (µPD44321322 and µPD44321362)
/BW1 and /BW2 (µPD44321182)
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
The mark
shows major revised points.
Document No. M16024EJ1V0DS00 (1st edition)
Date Published December 2002 NS CP(K)
Printed in Japan
2002
µPD44321182, 44321322, 44321362
Ordering Information
(1/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Operating
Temperature
°C
Package
µPD44321182GF-A44 Note
µPD44321182GF-A50
2.8
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
3.2
3.5
3.2
3.5
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
3.2
3.5
3.2
3.5
3.2
3.5
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
3.3 ± 0.165
3.3 V or
0 to 70
100-pin PLASTIC LQFP
(14 x 20)
2.5 V LVTTL
µPD44321182GF-A60
µPD44321322GF-A44 Note
µPD44321322GF-A50
µPD44321322GF-A60
µPD44321362GF-A44 Note
µPD44321362GF-A50
µPD44321362GF-A60
µPD44321182GF-C50
2.5 ± 0.125
2.5 V LVTTL
µPD44321182GF-C60
µPD44321322GF-C50
µPD44321322GF-C60
µPD44321362GF-C50
µPD44321362GF-C60
µPD44321182F1-A44-FQ2 Note
µPD44321182F1-A50-FQ2 Note
µPD44321182F1-A60-FQ2 Note
µPD44321322F1-A44-FQ2 Note
µPD44321322F1-A50-FQ2 Note
µPD44321322F1-A60-FQ2 Note
µPD44321362F1-A44-FQ2 Note
µPD44321362F1-A50-FQ2 Note
µPD44321362F1-A60-FQ2 Note
µPD44321182F1-C50-FQ2 Note
µPD44321182F1-C60-FQ2 Note
µPD44321322F1-C50-FQ2 Note
µPD44321322F1-C60-FQ2 Note
µPD44321362F1-C50-FQ2 Note
µPD44321362F1-C60-FQ2 Note
3.3 ± 0.165
3.3 V or
165-pin PLASTIC FBGA
(15 x 17)
2.5 V LVTTL
2.5 ± 0.125
2.5 V LVTTL
Note Under development
2
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Operating
Temperature
°C
Package
µPD44321182GF-A44Y Note
µPD44321182GF-A50Y
2.8
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
3.2
3.5
3.2
3.5
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
2.8
3.2
3.5
3.2
3.5
3.2
3.5
3.2
3.5
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
3.3 ± 0.165
3.3 V or
–40 to +85
100-pin PLASTIC LQFP
(14 x 20)
2.5 V LVTTL
µPD44321182GF-A60Y
µPD44321322GF-A44Y Note
µPD44321322GF-A50Y
µPD44321322GF-A60Y
µPD44321362GF-A44Y Note
µPD44321362GF-A50Y
µPD44321362GF-A60Y
µPD44321182GF-C50Y
2.5 ± 0.125
2.5 V LVTTL
µPD44321182GF-C60Y
µPD44321322GF-C50Y
µPD44321322GF-C60Y
µPD44321362GF-C50Y
µPD44321362GF-C60Y
µPD44321182F1-A44Y-FQ2 Note
µPD44321182F1-A50Y-FQ2 Note
µPD44321182F1-A60Y-FQ2 Note
µPD44321322F1-A44Y-FQ2 Note
µPD44321322F1-A50Y-FQ2 Note
µPD44321322F1-A60Y-FQ2 Note
µPD44321362F1-A44Y-FQ2 Note
µPD44321362F1-A50Y-FQ2 Note
µPD44321362F1-A60Y-FQ2 Note
µPD44321182F1-C50Y-FQ2 Note
µPD44321182F1-C60Y-FQ2 Note
µPD44321322F1-C50Y-FQ2 Note
µPD44321322F1-C60Y-FQ2 Note
µPD44321362F1-C50Y-FQ2 Note
µPD44321362F1-C60Y-FQ2 Note
3.3 ± 0.165
3.3 V or
165-pin PLASTIC FBGA
(15 x 17)
2.5 V LVTTL
2.5 ± 0.125
2.5 V LVTTL
Note Under development
3
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 × 20)
[µPD44321182GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
NC
2
NC
3
NC
VDDQ
VSSQ
NC
4
VDDQ
VSSQ
NC
5
6
NC
7
I/OP1
I/O8
I/O7
VSSQ
VDDQ
I/O6
I/O5
VSS
I/O9
8
I/O10
VSSQ
VDDQ
I/O11
I/O12
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
VDD
VDD
ZZ
VDD
VSS
I/O13
I/O14
VDDQ
VSSQ
I/O15
I/O16
I/OP2
NC
I/O4
I/O3
VDDQ
VSSQ
I/O2
I/O1
NC
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
4
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Pin Identifications
[µPD44321182GF]
Symbol
Pin No.
Description
A0 to A20
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83, 84, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1
74
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
I/OP2
24
ADV
85
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1, /BW2
/G
93, 94
86
CLK
89
/CKE
87
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
31
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, No Connection
52, 53, 56, 57, 75, 78, 79, 95, 96
5
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
100-pin PLASTIC LQFP (14 × 20)
[µPD44321322GF, µPD44321362GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
2
I/O18
3
I/O15
V
DD
Q
Q
4
V
V
DD
Q
V
SS
5
SSQ
I/O19
I/O20
I/O21
I/O22
6
I/O14
I/O13
I/O12
I/O11
7
8
9
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
VDD
DD
Q
I/O23
I/O24
I/O10
I/O9
VDD
VDD
VDD
V
V
V
SS
DD
DD
V
SS
ZZ
I/O25
I/O26
I/O8
I/O7
V
DD
Q
Q
V
V
DD
Q
V
SS
SSQ
I/O27
I/O28
I/O29
I/O30
I/O6
I/O5
I/O4
I/O3
V
SS
Q
Q
V
V
SS
Q
VDD
DD
Q
I/O31
I/O32
I/O2
I/O1
I/OP4, NC
I/OP1, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
6
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[µPD44321322GF, µPD44321362GF]
Symbol
Pin No.
Description
A0 to A19
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83, 84, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
85
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1 to /BW4
/G
93, 94, 95, 96
86
89
87
31
CLK
/CKE
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
38, 39, 42
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD44321322GF.
I/OP1 to I/OP4 are used in the µPD44321362GF.
7
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
165-pin PLASTIC FBGA (15 x 17)
[µPD44321182F1]
Top View
1
NC
2
A7
3
4
/BW2
NC
5
NC
6
7
8
9
10
A9
11
A20
NC
A
B
C
D
E
F
/CE
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
/CKE
/WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
/G
A17
NC
A6
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A18
A8
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A12
A2
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A19
A10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
A14
A15
I/OP1
I/O8
I/O7
I/O6
I/O5
ZZ
NC
I/O9
I/O10
I/O11
I/O12
VDD
NC
NC
NC
G
H
J
NC
NC
I/O13
I/O14
I/O15
I/O16
I/OP2
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
NC
K
L
NC
NC
NC
NC
M
N
P
R
NC
NC
NC
NC
NC
TDI
TMS
TDO
TCK
NC
MODE
A5
A3
A0
A11
A16
Remark Refer to Package Drawings for the index mark.
8
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[µPD44321182F1]
Symbol
Pin No.
Description
A0 to A20
6R, 6P, 4R, 3R, 3P, 2R, 2B, 2A, 10B, 10A, 8R, 9R, Synchronous Address Input
4P, 9P, 10P, 10R, 11R, 9A, 9B, 8P, 11A
I/O1 to I/O16
10M, 10L, 10K, 10J, 11G, 11F, 11E, 11D, 2D, 2E,
Synchronous Data In,
2F, 2G, 1J, 1K, 1L, 1M
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1
11C
1N
I/OP2
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
ADV
8A
/CE, CE2, /CE2
/WE
3A, 3B, 6A
7B
/BW1, /BW2
/G
5B, 4A
8B
CLK
6B
/CKE
7A
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
1R
ZZ
11H
VDD
2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D,
8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M
4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M,
6C, 6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D,
7E, 7F, 7G, 7H, 7J, 7K, 7L, 7M, 8C, 8N
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D,
9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N
1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1P, 2C, 2J, 2K,
2L, 2M, 2N, 2P, 3H, 4B, 5A, 5N, 6N, 7N, 9H,
10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B,
11J, 11K, 11L, 11M, 11N, 11P
5R
VSS
Ground
VDDQ
NC
Output Buffer Power Supply
No Connection
TMS
TDI
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
5P
TCK
TDO
7R
7P
9
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
165-pin PLASTIC FBGA (15 x 17)
[µPD44321322F1, µPD44321362F1]
Top View
1
NC
2
3
4
5
6
7
8
9
10
A9
11
NC
A
B
C
D
E
F
A7
/CE
/BW3
/BW4
VSS
/BW2
/BW1
VSS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
/CKE
/WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
/G
A17
NC
A6
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A18
A8
NC
I/OP3,NC
I/O17
I/O18
I/O19
I/O20
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A19
A10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
I/OP2,NC
I/O12
I/O11
I/O10
I/O9
I/O21
I/O22
I/O23
I/O24
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
I/O16
I/O15
I/O14
I/O13
NC
VSS
VSS
G
H
J
VSS
VSS
ZZ
I/O25
I/O26
I/O27
I/O28
I/OP4,NC
NC
I/O29
I/O30
I/O31
I/O32
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A4
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O8
I/O7
I/O6
I/O5
NC
I/O4
K
L
VSS
I/O3
VSS
I/O2
M
N
P
R
VSS
I/O1
NC
I/OP1,NC
NC
NC
A12
A2
TDI
TMS
TDO
TCK
A14
A15
MODE
A5
A3
A0
A11
A16
Remark Refer to Package Drawings for the index mark.
10
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[µPD44321322GF, µPD44321362GF]
Symbol
Pin No.
Description
A0 to A19
6R, 6P, 4R, 3R, 3P, 2R, 2B, 2A, 10B, 10A, 8R,
9R, 4P, 9P, 10P, 10R, 11R, 9A, 9B, 8P
Synchronous Address Input
I/O1 to I/O32
11M, 11L, 11K, 11J, 10M, 10L, 10K, 10J, 11G, 11F, Synchronous Data In,
11E, 11D, 10G, 10F, 10E, 10D, 1D, 1E, 1F, 1G,
Synchronous / Asynchronous Data Out
2D, 2E, 2F, 2G,1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NC Note
I/OP4, NCNote
ADV
11N
Synchronous Data In (Parity),
11C
Synchronous / Asynchronous Data Out (Parity)
1C
1N
8A
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
/CE, CE2, /CE2
/WE
3A, 3B, 6A
7B
/BW1 to /BW4
/G
5B, 5A, 4A, 4B
8B
6B
7A
1R
CLK
/CKE
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
ZZ
11H
VDD
2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D, 8E,
8F, 8G, 8H, 8J, 8K, 8L, 8M
VSS
4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M,
6C, 6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D,
7E, 7F, 7G, 7H, 7J, 7K, 7L, 7M, 8C, 8N
Ground
VDDQ
NC
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, Output Buffer Power Supply
9F, 9G, 9J, 9K, 9L, 9M, 9N
1A, 1B, 1H, 1P, 2C, 2N, 2P, 3H, 5N, 6N, 7N, 9H,
No Connection
10C, 10H, 10N, 11A, 11B, 11P
TMS
TDI
5R
5P
7R
7P
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
TCK
TDO
Note NC (No Connection) is used in the µPD44321322GF.
I/OP1 to I/OP4 are used in the µPD44321362GF.
11
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Block Diagrams
[µPD44321182]
21
19
21
A0 to A20
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
21
21
Write address
register 1
Write address
register 0
Memory Cell Array
1,024 rows
ADV
/BW1
/BW2
Write registry and
data coherency
control logic
Write
drivers
18
18
I/O1 to I/O16
I/OP1, I/OP2
2,048 x 18 columns
(37,748,736 bits)
/WE
E
E
18
18
18
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
Burst Sequence
[µPD44321182]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, A1, A0
A20 to A2, A1, /A0
A20 to A2, /A1, A0
A20 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
12
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[µPD44321322, µPD44321362]
20
18
20
A0 to A19
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
20
20
Write address
register 1
Write address
register 0
Memory Cell Array
1,024 rows
ADV
/BW1
/BW2
/BW3
/BW4
/WE
Write registry and
data coherency
control logic
Write
drivers
32/36
32/36
I/O1 to I/O32
I/OP1 to I/OP4
1,024 x 32 columns
(33,554,432 bits)
1,024 x 36 columns
(37,748,736 bits)
E
E
32/36
32/36
32/36
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
[µPD44321322, µPD44321362]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, A1, A0
A19 to A2, A1, /A0
A19 to A2, /A1, A0
A19 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
13
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
State Diagram
DS
BURST
DS
DS
DESELECT
READ
WRITE
DS
DS
WRITE
READ
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
BURST
BURST
WRITE
WRITE
READ
BURST
READ
BURST
WRITE
BURST
BURST
Command
DS
Operation
Deselect
Read
Write
New Read
New Write
Burst
Burst Read, Burst Write or Continue Deselect
Remarks 1. States change on the rising edge of the clock.
2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only
blocks the clock (CLK) input and does not change the state of the device.
14
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Asynchronous Truth Table
Operation
Read Cycle
/G
L
I/O
Data-Out
High-Z
Read Cycle
H
×
Write Cycle
High-Z, Data-In
High-Z
Deselected
×
Remark × : don’t care
Synchronous Truth Table
Operation
Deselected
/CE
H
×
CE2 /CE2 ADV
/WE /BWs /CKE
CLK
I/O
Address
None
Note
×
L
×
×
H
×
H
×
H
×
×
×
×
H
×
L
×
L
×
L
×
×
L
L
×
×
×
×
H
×
L
×
L
×
×
×
×
×
×
×
×
L
L
H
H
×
L
L
L
L
L
L
L
L
L
L
H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
High-Z
High-Z
High-Z
High-Z
Data-Out
Data-Out
Data-In
Data-In
High-Z
High-Z
−
1
1
1
1
Deselected
None
Deselected
×
L
None
Continue Deselected
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Write Abort
Write Cycle / Write Abort
Stall / Ignore Clock Edge
×
H
L
None
L
External
Next
×
H
L
L
External
Next
×
H
L
L
External
Next
×
H
×
×
Current
2
Notes 1. Deselect status is held until new “Begin Burst” entry.
2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Low-
impedance). If it occurs during a write cycle, the bus will remain High impedance. No write operation will
be performed during the Ignore Clock Edge cycle.
Remarks 1. × : don’t care
2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
15
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Partial Truth Table for Write Enables
[µPD44321182]
Operation
/WE
H
/BW1
/BW2
Read Cycle
×
L
×
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
Write Abort / NOP
L
L
H
L
L
L
L
H
H
Remark × : don’t care
[µPD44321322, µPD44321362]
Operation
/WE
H
L
/BW1
/BW2
/BW3
/BW4
Read Cycle
×
L
×
H
L
×
H
H
L
×
H
H
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
L
H
H
H
L
L
H
H
L
L
H
L
L
L
Write Abort / NOP
L
H
H
H
H
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
≤ 0.2 V
Chip Status
Active
Active
Sleep
Open
≥ VDD − 0.2 V
16
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
MIN.
–0.5
TYP.
MAX.
+4.0
Unit
V
VDD
-A44, -A50, -A60
-A44Y, -A50Y, -A60Y
-C50, -C60
–0.5
+3.0
-C50Y, -C60Y
Output supply voltage
Input voltage
VDDQ
VIN
–0.5
–0.5 Note
–0.5 Note
0
VDD
VDD + 0.5
VDDQ + 0.5
70
V
V
Input / Output voltage
Operating ambient
temperature
VI/O
TA
V
-A44, -A50, -A60, -C50, -C60
°C
-A44Y, -A50Y, -A60Y, -C50Y, -C60Y
–40
+85
Storage temperature
Tstg
–55
+125
°C
Note –2.0 V (MIN.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
(1/2)
Unit
Parameter
Symbol
Conditions
-A44, -A50, -A60
-A44Y, -A50Y, -A60Y
MIN.
TYP.
3.3
MAX.
Supply voltage
VDD
3.135
3.465
V
2.5 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
–0.3 Note
2.5
2.9
V
V
V
VDDQ + 0.3
+0.7
VIL
VDDQ
VIH
3.135
2.0
–0.3 Note
3.3
3.465
VDDQ +
+0.8
V
V
V
VIL
Note –0.8 V (MIN.) (Pulse width : 2 ns)
Recommended DC Operating Conditions
(2/2)
Parameter
Symbol
Conditions
-C50, -C60
Unit
-C50Y, -C60Y
MIN.
2.375
2.375
1.7
TYP.
2.5
MAX.
2.625
Supply voltage
VDD
VDDQ
VIH
V
V
V
V
Output supply voltage
High level input voltage
Low level input voltage
2.5
2.625
VDDQ + 0.3
+0.7
VIL
–0.3 Note
Note –0.8 V (MIN.) (Pulse width : 2 ns)
17
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
DC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
Parameter
Input leakage current
I/O leakage current
Operating supply current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled.
ILO
–2
+2
µA
IDD
Device selected,
Cycle = MAX.
-A44
440
mA
-A44Y
VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA
-A50, -C50
-A50Y, -C50Y
-A60, -C60
-A60Y, -C60Y
410
360
70
Standby supply current
ISB
Device deselected, Cycle = 0 MHz,
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
Device deselected, Cycle = 0 MHz,
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
VI/O ≤ 0.2 V, All inputs are static.
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
mA
ISB1
60
ISB2
ISBZZ
VOH
VOL
130
60
Power down supply current
2.5 V LVTTL Interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL Interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test condition
VIN = 0 V
MIN.
TYP.
MAX.
6.0
Unit
pF
Input capacitance
Input / Output capacitance
Clock input capacitance
CI/O
VI/O = 0 V
8.0
pF
Cclk
Vclk = 0 V
6.0
pF
Remark These parameters are periodically sampled and not 100% tested.
18
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
AC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time≤ 2.4 ns)
2.4 V
1.2 V
Test points
1.2 V
1.2 V
VSS
Output waveform
1.2 V
Test points
3.3 V LVTTL Interface
Input waveform (Rise / Fall time≤ 3.0 ns)
3.0 V
1.5 V
Test points
Test points
1.5 V
VSS
Output waveform
1.5 V
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
Figure External load at test
ZO = 50 Ω
I/O (Output)
C
L
50 Ω
VT = +1.2 V / +1.5 V
Remark CL includes capacitances of the probe and jig, and stray capacitances.
19
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Read and Write Cycle
Parameter
Symbol
-A44
-A44Y
-A50, -C50
-A50Y, -C50Y
(200 MHz)
-A60, -C60
-A60Y, -C60Y
(167 MHz)
Unit Notes
(225 MHz)
Standard
Alias
TCYC
TCD
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
TKLKH
TAVKH
ns
ns
ns
4.4
–
–
2.8
2.8
–
5
–
–
3.2
3.2
–
6
–
–
3.5
3.5
–
Clock access time
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output High-Z
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
TOE
–
–
–
TDC1
TDC2
TOLZ
TOHZ
TCZ
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
1.5
1.5
0
1.5
1.5
0
1.5
1.5
0
–
–
–
1
1
–
–
–
0
2.8
2.8
–
0
3.2
3.2
–
0
3.5
3.5
–
1, 2
1.5
1.8
1.8
1.4
1.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
TCH
TCL
–
–
–
Setup times
Address
TAS
–
–
–
Address advance TADVVKH TADVS
Clock enable
Chip enable
Data in
TEVKH
TCVKH
TDVKH
TWVKH
TKHAX
TCES
TCSS
TDS
Write enable
Address
TWS
TAH
Hold times
0.4
0.5
–
0.5
–
ns
–
Address advance TKHADVX TADVH
Clock enable
Chip enable
Data in
TKHEX
TKHCX
TKHDX
TKHWX
TZZE
TCEH
TCSH
TDH
Write enable
TWH
TZZE
TZZR
Power down entry time
–
–
–
–
–
–
ns
ns
8.8
8.8
10
10
12
12
Power down recovery time
TZZR
Notes 1. Transition is measured 200 mV from steady state.
2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min.,
VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).
20
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
READ / WRITE CYCLE
1
2
TKHKH
3
4
5
6
7
8
9
10
CLK
TKHKL TKLKH
TEVKH TKHEX
TCVKH TKHCX
/CKE
/CEs Note 1
ADV
TADVVKH TKHADVX
TWVKH TKHWX
TWVKH TKHWX
/WE
/BWs Note 2
Address
A1
A2
A3
A4
A5
A6
A7
TAVKH TKHAX
High-Z
High-Z
High-Z
D (A1)
D (A2)
D (A2+1)
D (A5)
Data In
TDVKH TKHDX
TKHQX1
TKHQX2
Q (A3)
TGLQV TKHQZ
High-Z
High-Z
Q (A4)
Q (A4+1)
Q (A6)
Data Out
/G
TKHQX2
TGHQZ
TKHQV
TGLQX
BURST
WRITE
D (A2+1)
BURST
READ
Q (A4+1)
WRITE
D (A1)
WRITE
D (A2)
READ
Q (A3)
READ
Q (A4)
WRITE
D (A5)
READ
Q (A6)
WRITE
Q (A7)
Command
DESELECT
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When
/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables
(/BW1, /BW2, /BW3 or /BW4) are LOW.
21
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
NOP, STALL AND DESELECT CYCLE
1
2
3
4
5
6
7
8
9
10
CLK
/CKE
/CEs
ADV
/WE
/BWs
Address
A1
A2
A3
A4
A5
High-Z
High-Z
High-Z
D (A1)
D (A4)
Data In
TKHQZ
High-Z
High-Z
Q (A2)
Q (A3)
Q (A5)
TKHQX2
Data Out
WRITE
D (A1)
READ
Q (A2)
READ
Q (A3)
WRITE
D (A4)
READ
Q (A5)
CONTINUE
DESELECT
Command
STALL
STALL
NOP
DESELECT
22
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
POWER DOWN (ZZ) CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
TKHKH
CLK
/CKE
TKHKL TKLKH
/CEs Note
ADV
/WE Note
/BWs
Address
/G
A1
A2
High-Z
High-Z
Data Out
ZZ
Q1 (A2)
Q (A1)
TZZE
TZZR
Power Down (ISBZZ) State
Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power
down state entry.
23
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
JTAG Specifications
Only the 165-pin PLASTIC FBGA package of µPD44321182, µPD44321322 and µPD44321362 support a limited set
of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin Name
TCK
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling
edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
Test Data Input. This is the input side of the serial registers placed between TDI and TDO.The register placed
between TDI and TDO is deter-mined by the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (VDD = 3.3 ± 0.165 V)
(1/2)
Note
Parameter
Symbol
Conditions
0 V ≤ VIN ≤ VDD
MIN.
TYP.
MAX.
Unit
JTAG Input leakage current
JTAG I/O leakage current
ILI
–5.0
–5.0
+5.0
+5.0
µA
µA
–
–
ILO
0 V ≤ VIN ≤ VDDQ ,
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
JTAG output low voltage
VIH
VIL
2.0
–0.3
2.4
–
–
–
–
–
VDD+0.3
+0.5
–
V
V
V
V
VOH
VOL
IOH = –4 mA
IOL = 8 mA
0.4
JTAG DC Characteristics (VDD = 2.5 ± 0.125 V)
(2/2)
Note
Parameter
Symbol
ILI
Conditions
0 V ≤ VIN ≤ VDD
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
µA
JTAG Input leakage current
JTAG I/O leakage current
–
–
ILO
0 V ≤ VIN ≤ VDDQ ,
µA
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
VIH
VIL
1.7
–0.3
1.7
VDD+0.3
+0.5
V
V
V
–
–
VOH
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
2.1
JTAG output low voltage
VOL
0.7
0.4
V
24
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
JTAG AC Test Conditions
[-A44, -A50, -A60, -A44Y, -A50Y, -A60Y]
Input waveform (rise / fall time ≤ 1 ns )
Output waveform
1.5 V
1.5 V
Test Points
[-C50, -C60, -C50Y, -C60Y]
Input waveform (rise / fall time ≤ 1 ns )
2.4 V
1.2 V
1.2 V
Test Points
0 V
Output waveform
1.2 V
1.2 V
Test Points
Output load
VTT = 1.2 V / 1.5 V
50 Ω
Z
O
= 50 Ω
TDO
20 pF
25
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
JTAG AC Characteristics
Parameter
Symbol
tTHTH
Conditions
MIN.
100
40
TYP.
MAX.
Unit
ns
Note
Clock Cycle Time (TCK)
Clock Phase Time (TCK)
Setup Time (TMS / TDI)
Hold Time (TMS / TDI)
TCK Low to TDO Valid (TDO)
–
–
tTHTL / tTLTH
tMVTH / tDVTH
tTHMX / tTHDX
tTLQV
ns
10
–
ns
10
–
ns
–
20
ns
JTAG Timing Diagram
26
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
Bypass register
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the
input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
77
bit
Boundary register
bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 0010 1100
0000 0000 0010 1101
0000 0000 0010 1110
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
µPD44321182
µPD44321322
µPD44321362
2M x 18
1M x 32
1M x 36
XXXX
XXXX
XXXX
1
1
1
00000010000
00000010000
27
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
SCAN Exit Order
[ µPD44321322 (1M words by 32 bits) ]
[ µPD44321362 (1M words by 36 bits) ]
[ µPD44321182 (2M words by 18 bits) ]
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
1
NC
A19
A10
A11
A13
A14
A15
A16
NC
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
NC
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1
NC
A19
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
/BW2
/BW3
/BW4
CE2
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
2
2
3
8R
3
A10
8R
4
9R
/BW2
NC
4
A11
9R
5
9P
5
A13
9P
6
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
11B
10A
10B
9A
CE2
/CE
A7
6
A14
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
11B
10A
10B
9A
7
7
A15
/CE1
A7
8
8
A16
9
A6
9
NC
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
ZZ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
ZZ
NC
NC
NC
I/OP1, NC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/OP2, NC
NC
NC
NC
NC
I/OP3, NC
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/OP4, NC
A5
NC
NC
NC
NC
NC
NC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/OP1
NC
NC
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/OP2
NC
1K
1L
1K
1L
1M
1N
2K
2L
1M
2J
NC
2K
2L
NC
NC
NC
NC
2M
2J
2M
1N
2R
1R
3P
3R
4R
4P
6P
6R
A20
NC
NC
A5
2R
1R
3P
3R
4R
4P
6P
6R
NC
A9
MODE
A4
A9
MODE
A4
A8
A8
A17
A18
ADV
/G
A3
A17
A3
9B
A2
A18
9B
A2
8A
A12
A1
ADV
/G
8A
A12
8B
8B
A1
/CKE
7A
A0
/CKE
7A
A0
38
39
/WE
CLK
7B
6B
38
39
/WE
CLK
7B
6B
28
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
JTAG Instructions
Instructions
EXTEST
Description
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to high impedance any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS
SAMPLE
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (High impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Cording
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
Note
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
29
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
TAP Controller State Diagram
Disabling The Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.
TDO should be left unconnected.
30
Preliminary Data Sheet M16024EJ1V0DS
Test Logic Operation (Instruction Scan)
TCK
TMS
µ
Contoroller
state
TDI
Instruction
Register state
IDCODE
New Instruction
Output Inactive
TDO
Test Logic (Data Scan)
TCK
TMS
µ
Controller
state
TDI
Instructin
Register state
Instruction
IDCODE
Output Inactive
TDO
µPD44321182, 44321322, 44321362
Package Drawings
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
14.0 0.2
16.0 0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125 0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
33
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
165-PIN PLASTIC FBGA (15x17)
E
w S B
ZD
ZE
B
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
w S A
INDEX MARK
y1 S
A2
h
A
S
ITEM MILLIMETERS
A1
e
y
D
E
15.00
17.00
2.50
1.50
1.00
0.60
1.40
0.40
1.00
0.45
0.08
0.08
0.15
0.20
S
ZD
ZE
e
φ M
x
φ
b
S A B
h
A
A1
A2
b
y
x
w
y1
This package drawing is a preliminary version. It may be changed in the future.
34
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD44321182, µPD44321322 and
µPD44321362.
Types of Surface Mount Devices
µPD44321182GF
µPD44321322GF
µPD44321362GF
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
µPD44321182F1-FQ2 : 165-pin PLASTIC FBGA (15 x 17)
µPD44321322F1-FQ2 : 165-pin PLASTIC FBGA (15 x 17)
µPD44321362F1-FQ2 : 165-pin PLASTIC FBGA (15 x 17)
35
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
Revision History
Edition/
Page
Previous
edition
Type of
revision
Location
Description
Date
This
(Previous edition → This edition)
edition
1st edition/ Throughout Throughout Modification
−
Preliminary Product Information
Dec. 2002
Deletion
Addition
→ Preliminary Data Sheet
µPD44321162
−
−
Extended operating temperature products
(TA = −40 to +85 °C)
pp.2, 3
p.27
pp.2, 3
p.27
Addition
Addition
Ordering Information Under development
(225 MHz and 165-pin PLASTIC FBGA (15 x 17))
ID Register Definition Addition of ID [27:12] part no.
36
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[MEMO]
37
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
[MEMO]
38
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
39
Preliminary Data Sheet M16024EJ1V0DS
µPD44321182, 44321322, 44321362
ZEROSB is a trademark of NEC Electronics Corporation.
•
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
©2020 ICPDF网 联系我们和版权申明