UPD44324092BF5-E33-FQ1-A

Datasheet

μPD44324092B

μPD44324182B

μPD44324362B

R10DS0036EJ0200

Rev.2.00

36M-BIT DDR II SRAM

2-WORD BURST OPERATION

August 2, 2011

Description

The μPD44324092B is a 4,194,304-word by 9-bit, the μPD44324182B is a 2,097,152-word by 18-bit and the

μPD44324362B is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44324092B, μPD44324182B and μPD44324362B integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the

positive edge of K and K#. These products are suitable for application which require synchronous operation,

high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 0.1 V power supply

• 165-pin PLASTIC BGA (15 x 17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 3.5ns (287MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

R10DS0036EJ0100 Rev.2.00

August 2, 2011

Page 1 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Ordering Information (1/2)

Organization

(word x bit)

4M x 9

Operating Ambient

Temperature

Cycle

time

Clock

frequency

Part No.

Package

μPD44324092BF5-E33-FQ1-A

μPD44324092BF5-E35-FQ1-A

μPD44324092BF5-E40-FQ1-A

μPD44324092BF5-E50-FQ1-A

μPD44324182BF5-E33-FQ1-A

μPD44324182BF5-E35-FQ1-A

μPD44324182BF5-E40-FQ1-A

μPD44324182BF5-E50-FQ1-A

μPD44324362BF5-E33-FQ1-A

μPD44324362BF5-E35-FQ1-A

μPD44324362BF5-E40-FQ1-A

μPD44324362BF5-E50-FQ1-A

μPD44324092BF5-E33-FQ1

μPD44324092BF5-E35-FQ1

μPD44324092BF5-E40-FQ1

μPD44324092BF5-E50-FQ1

μPD44324182BF5-E33-FQ1

μPD44324182BF5-E35-FQ1

μPD44324182BF5-E40-FQ1

μPD44324182BF5-E50-FQ1

μPD44324362BF5-E33-FQ1

μPD44324362BF5-E35-FQ1

μPD44324362BF5-E40-FQ1

μPD44324362BF5-E50-FQ1

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

165-pin

PLASTIC BGA

(15 x 17)

Ta = 0 to 70°C

Lead-free

2M x 18

1M x 36

4M x 9

165-pin

PLASTIC BGA

(15 x 17)

Ta = 0 to 70°C

Lead

2M x 18

1M x 36

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 2 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Ordering Information (2/2)

Organization

(word x bit)

4M x 9

Operating Ambient

Temperature

Cycle

time

Clock

frequency

Part No.

Package

μPD44324092BF5-E33Y-FQ1-A

μPD44324092BF5-E35Y-FQ1-A

μPD44324092BF5-E40Y-FQ1-A

μPD44324092BF5-E50Y-FQ1-A

μPD44324182BF5-E33Y-FQ1-A

μPD44324182BF5-E35Y-FQ1-A

μPD44324182BF5-E40Y-FQ1-A

μPD44324182BF5-E50Y-FQ1-A

μPD44324362BF5-E33Y-FQ1-A

μPD44324362BF5-E35Y-FQ1-A

μPD44324362BF5-E40Y-FQ1-A

μPD44324362BF5-E50Y-FQ1-A

μPD44324092BF5-E33Y-FQ1

μPD44324092BF5-E35Y-FQ1

μPD44324092BF5-E40Y-FQ1

μPD44324092BF5-E50Y-FQ1

μPD44324182BF5-E33Y-FQ1

μPD44324182BF5-E35Y-FQ1

μPD44324182BF5-E40Y-FQ1

μPD44324182BF5-E50Y-FQ1

μPD44324362BF5-E33Y-FQ1

μPD44324362BF5-E35Y-FQ1

μPD44324362BF5-E40Y-FQ1

μPD44324362BF5-E50Y-FQ1

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

3.3ns

3.5ns

4.0ns

5.0ns

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

300MHz

287MHz

250MHz

200MHz

165-pin

PLASTIC BGA

(15 x 17)

Ta = −40 to 85°C

Lead-free

2M x 18

1M x 36

4M x 9

165-pin

PLASTIC BGA

(15 x 17)

Ta = −40 to 85°C

Lead

2M x 18

1M x 36

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 3 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Pin Arrangement

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44324092B]

4M x 9

1

CQ#

NC

2

3

A

4

5

NC

NC/288M

A

6

7

NC/144M

BW0#

A

8

9

A

10

A

11

CQ

DQ4

NC

A

B

C

D

E

F

R, W#

A

K#

K

LD#

A

VSS/72M

NC

DQ5

NC

DQ6

VDDQ

NC

DQ8

A

NC

VDDQ

NC

A

NC

VREF

DQ2

NC

TMS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ3

NC

G

H

J

NC

DLL#

NC

VREF

NC

ZQ

NC

K

L

NC

DQ7

NC

DQ1

NC

M

N

P

R

NC

VSS

NC

A

C

A

DQ0

TDI

TDO

TCK

A

C#

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ8

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V_REF

V_DD

R, W#

BW0#

K, K#

C, C#

: Output clock

V

_DDQ

: Power Supply

CQ, CQ#

ZQ

: Echo clock

V_SS

NC

: Ground

: Output impedance matching

: PLL disable

: No connection

DLL#

NC/xxM : Expansion address for xxMb

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Dimensions for the index mark.

3. 2A, 7A and 5B are expansion addresses : 2A for 72Mb

: 2A and 7A for 144Mb

: 2A, 7A and 5B for 288Mb

2A of this product can also be used as NC.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 4 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Pin Arrangement

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44324182B]

2M x 18

1

CQ#

NC

2

3

4

5

6

7

NC/144M

BW0#

A

8

9

A

10

A

11

CQ

A

B

C

D

E

F

A

R, W#

A

BW1#

NC/288M

A

K#

K

LD#

A

VSS/72M

DQ9

NC

VDDQ

NC

A

NC

DQ8

NC

VSS

A0

VSS

A

VSS

DQ7

NC

DQ10

DQ11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

NC

DQ13

VDDQ

NC

DLL#

NC

VREF

NC

VREF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

VSS

NC

A

C

A

NC

DQ0

TDI

TDO

TCK

A

C#

A

TMS

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ17

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

V^DD

R, W#

BW0#, BW1#

K, K#

C, C#

: Output clock

V^DDQ

V^SS

: Power Supply

CQ, CQ#

ZQ

: Echo clock

: Ground

: Output impedance matching

: PLL disable

NC

: No connection

DLL#

NC/xxM : Expansion address for xxMb

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Dimensions for the index mark.

3. 2A, 7A and 5B are expansion addresses : 2A for 72Mb

: 2A and 7A for 144Mb

: 2A, 7A and 5B for 288Mb

2A of this product can also be used as NC.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 5 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Pin Arrangement

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44324362B]

1M x 36

1

CQ#

NC

2

3

4

5

6

7

BW1#

BW0#

A

8

9

A

10

11

CQ

A

B

C

D

E

F

A

R, W# BW2#

K#

K

LD#

A

VSS/144M

DQ27

NC

VSS/72M

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

BW3#

A

NC

VDDQ

NC

A

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

NC

VSS

A0

VSS

A

VSS

DQ17

NC

DQ29

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ15

NC

DQ30

DQ31

VREF

NC

G

H

J

NC

DLL#

NC

VREF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

NC

DQ11

NC

DQ35

NC

VSS

NC

A

C

A

DQ9

TMS

TDO

TCK

A

C#

A

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ35

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

TDI

TCK

TDO

V^REF

V^DD

R, W#

BW0# to BW3# : Byte Write data select

K, K#

C, C#

CQ, CQ#

ZQ

: Input clock

: Output clock

V^DDQ

V^SS

: Power Supply

: Echo clock

: Ground

: Output impedance matching

: PLL disable

NC

: No connection

DLL#

NC/xxM : Expansion address for xxMb

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Dimensions for the index mark.

3. 2A and 10A are expansion addresses : 10A for 72Mb

: 10A and 2A for 144Mb

2A and 10A of this product can also be used as NC.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 6 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Pin Description

(1/2)

Symbol

A0

A

Type

Input

Description

Synchronous Address Inputs: These inputs are registered and must meet the setup and

hold times around the rising edge of K. All transactions operate on a burst of two words

(one clock period of bus activity). A0 is used as the lowest order address bit permitting a

random starting address within the burst operation on x18 and x36 devices. These inputs

are ignored when device is deselected, i.e., NOP (LD# = HIGH).

DQ0 to

DQxx

Input/Output

Synchronous Data IOs: Input data must meet setup and hold times around the rising

edges of K and K#. Output data is synchronized to the respective C and C# data clocks

or to K and K# if C and C# are tied to HIGH.

x9 device uses DQ0 to DQ8.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

LD#

Input

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be

defined. This definition includes address and read/write direction. All transactions operate

on a burst of 2 data (one clock period of bus activity).

R, W#

BWx#

Synchronous Read/Write Input: When LD# is LOW, this input designates the access type

(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#

must meet the setup and hold times around the rising edge of K.

Synchronous Byte Writes: When LOW these inputs cause their respective byte to be

registered and written during WRITE cycles. These signals must meet setup and hold

times around the rising edges of K and K# for each of the two rising edges comprising the

WRITE cycle. See Pin Arrangement for signal to data relationships.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx# and Dxx.

K, K#

C, C#

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge

of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally

180 degrees out of phase with K. All synchronous inputs must meet setup and hold times

around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output

data. The rising edge of C# is used as the output timing reference for first output data.

The rising edge of C is used as the output reference for second output data. Ideally, C# is

180 degrees out of phase with C. When use of K and K# as the reference instead of C

and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C#

are fixed to HIGH (i.e. toggle of C and C#)

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August 2, 2011

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μPD44324092B, μPD44324182B, μPD44324362B

(2/2)

Symbol

Type

Description

CQ, CQ#

Output

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched

to the synchronous data outputs and can be used as a data valid indication. These signals

run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are

stopped in the single clock mode), CQ and CQ# will also stop.

ZQ

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the

system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,

where RQ is a resistor from this bump to ground. The output impedance can be

minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND

or left unconnected. The output impedance is adjusted every 20 μs upon power-up to

account for drifts in supply voltage and temperature. After replacement for a resistor, the

new output impedance is reset by implementing power-on sequence.

DLL#

PLL Disable: When debugging the system or board, the operation can be performed at a

clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =

LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must

be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.

TMS

TDI

Input

Output

−

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the

JTAG function is not used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG

function is not used in the circuit.

TDO

IEEE 1149.1 Test Output: 1.8 V I/O level.

When providing any external voltage to TDO signal, it is recommended to pull up to VDD.

VREF

VDD

HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the

input buffers.

Supply

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC

Characteristics for range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.

See Recommended DC Operating Conditions and DC Characteristics for range.

VSS

NC

Supply

Power Supply: Ground

−

No Connect: These signals are not connected internally.

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August 2, 2011

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μPD44324092B, μPD44324182B, μPD44324362B

Block Diagram

CLK

Burst

Logic

A0'

A0

D0

Q0

R

Address

Register

Address

LD#

W#

E

Compare

C#

C

A0''

A0'''

Output control

Logic

Write address

Register

K

E

A0'

Input

Register

/A0'

A0'

ZQ

0

2 :1

MUX

Memory

Array

CLK

/A0'

K

1

A0'

Output Buffer

E

DQ

0

1

K#

Input

Register

E

A0'''

Output Enable

Register

C

R, W#

R, W#`

Register

E

R10DS0036EJ0200 Rev.2.00

August 2, 2011

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μPD44324092B, μPD44324182B, μPD44324362B

Power-On Sequence in DDR II SRAM

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

The following power-up supply voltage application is recommended: V_SS, V_DD, V_DDQ, V_REF, then V_IN. V_DDand

V

_DDQ can be applied simultaneously, as long as V_DDQ does not exceed V_DDby more than 0.5 V during power-up.

The following power-down supply voltage removal sequence is recommended: V_IN, V_REF, V_DDQ, V_DD, V_SS. V_DD

and V_DDQ can be removed simultaneously, as long as V_DDQ does not exceed V_DDby more than 0.5 V during

power-down.

Power-On Sequence

Apply power and tie DLL# to HIGH.

- Apply V_DDbefore V_DDQ.

- Apply V_DDQ before V_REFor at the same time as V_REF

.

Provide stable clock for more than 20 μs to lock the PLL.

PLL Constraints

The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as

TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is

enabled, then the PLL may lock onto an undesired clock frequency.

Power-On Waveforms

V

DD/VDDQ

V

DD/VDDQ Stable (< ±0.1 V DC per 50 ns)

Fix HIGH (or tied to V^DDQ)

DLL#

Clock

20 μs or more

Stable Clock

Unstable Clock

Normal Operation

Start

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μPD44324092B, μPD44324182B, μPD44324362B

Burst Sequence

Linear Burst Sequence Table

[μPD44324182B, μPD44324362B]

A0

0

A0

1

External Address

1st Internal Burst Address

1

0

Truth Table

Operation

LD# R, W# CLK

DQ

WRITE cycle

L

L → H

Data in

Load address, input write data on

consecutive K and K# rising edge

READ cycle

Input data

Input clock

Data out

D(A1)

D(A2)

K(t+1) ↑

K#(t+1) ↑

L

H

L → H

Load address, read data on

consecutive C and C# rising edge

NOP (No operation)

Clock stop

Output data

Output clock

Q(A1)

Q(A2)

C#(t+1) ↑

C(t+2) ↑

H

×

L → H

High-Z

Previous state

×

Stopped

Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst

address in accordance with the linear burst sequence.

7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

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μPD44324092B, μPD44324182B, μPD44324362B

Byte Write Operation

[μPD44324092B]

Operation

K

L → H

−

L → H

−

K#

−

L → H

−

BW0#

Write DQ0 to DQ8

0

1

Write nothing

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[μPD44324182B]

Operation

K

L → H

−

L → H

−

L → H

−

L → H

−

K#

−

L → H

−

L → H

−

L → H

−

BW0#

BW1#

Write DQ0 to DQ17

Write DQ0 to DQ8

Write DQ9 to DQ17

Write nothing

0

1

0

1

0

1

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD44324362B]

Operation

K

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

K#

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

BW0#

BW1#

BW2#

BW3#

Write DQ0 to DQ35

Write DQ0 to DQ8

Write DQ9 to DQ17

Write DQ18 to DQ26

Write DQ27 to DQ35

Write nothing

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

R10DS0036EJ0200 Rev.2.00

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Page 12 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 2

WRITE DOUBLE

Load, Count = 2

READ DOUBLE

Write

Read

Count = Count + 2

Load

NOP,

Count = 2

NOP

Supply voltage provided

Power UP

Remarks 1. A0 is internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 2.

2. State machine control timing sequence is controlled by K.

R10DS0036EJ0200 Rev.2.00

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Page 13 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Electrical Characteristics

Absolute Maximum Ratings

Parameter

Supply voltage

Symbol

Conditions

Rating

−0.5 to +2.5

Unit

V

V_DD

Output supply voltage

Input voltage

V_DD

Q

−0.5 to V_DD

V

V_IN

V_I/O

TA

−0.5 to V_DD+0.5 (2.5 V MAX.)

−0.5 to V_DDQ+0.5 (2.5 V MAX.)

0 to 70

V

Input / Output voltage

Operating ambient temperature

V

(E** series)

°C

(E**Y series)

−40 to 85

Storage temperature

Tstg

−55 to +125

°C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T^A= 0 to 70°C, TA = −40 to 85°C)

Parameter

Supply voltage

Symbol Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit Note

V_DD

1.8

V

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

V_DD

Q

1.4

V_DD

V

1

V_{IH (DC)}

V_{IL (DC)}

V_IN

V_REF+0.1

−0.3

V_DDQ+0.3

V_REF−0.1

V_DDQ+0.3

0.95

1, 2

−0.3

V_REF

0.68

Notes 1. During normal operation, V_DDQ must not exceed V_DD

.

2. Power-up: V_IH≤ V_DDQ +0.3 V and V_DD≤ 1.7 V and V_DDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol Conditions

MIN.

MAX.

Unit Note

V_{IH (AC)}

V_{IL (AC)}

V_REF+0.2

V

1

V_REF−0.2

Note 1. Overshoot: V_{IH (AC)}≤ V_DD+0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V_{IL (AC)}≥ −0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

R10DS0036EJ0200 Rev.2.00

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Page 14 of 36

μPD44324092B, μPD44324182B, μPD44324362B

DC Characteristics 1 (T^A= 0 to 70°C, V_DD= 1.8 0.1 V)

Parameter

Symbol

Test condition

MIN.

MAX.

x18 x36

+2

Unit Note

x9

Input leakage current

I/O leakage current

ILI

−2

μA

ILO

IDD

+2

Operating supply current

(Read cycle / Write cycle)

VIN ≤ VIL or VIN ≥ VIH, -E33

440 470 510 mA

430 460 500

410 430 470

380 390 420

390 410 430 mA

380 400 420

370 380 400

340 350 370

II/O = 0 mA,

-E35

-E40

-E50

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH, -E33

II/O = 0 mA,

Cycle = MAX.

Inputs static

-E35

-E40

-E50

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note1

VOL(Low) IOL ≤ 0.1 mA

VOL Note2

V_DDQ−0.2

V_DDQ/2−0.12

V_SS

V_DD

Q

V

3, 4

V_DDQ/2+0.12

0.2

V_DDQ/2−0.12

V_DDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | I_OH| = (V_DDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I_OL= (V_DDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I standards.

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August 2, 2011

Page 15 of 36

μPD44324092B, μPD44324182B, μPD44324362B

DC Characteristics 2 (T^A= −40 to 85°C, V_DD= 1.8 0.1 V)

Parameter

Symbol

Test condition

MIN.

MAX.

x18 x36

+2

Unit Note

x9

Input leakage current

I/O leakage current

ILI

−2

μA

ILO

IDD

+2

Operating supply current

(Read cycle / Write cycle)

VIN ≤ VIL or VIN ≥ VIH, -E33Y

570 600 640 mA

560 590 630

540 560 600

510 520 550

510 530 550 mA

500 520 540

490 500 520

460 470 490

II/O = 0 mA,

-E35Y

-E40Y

-E50Y

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH, -E33Y

II/O = 0 mA,

Cycle = MAX.

Inputs static

-E35Y

-E40Y

-E50Y

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note1

VOL(Low) IOL ≤ 0.1 mA

VOL Note2

V_DDQ−0.2

V_DDQ/2−0.12

V_SS

V_DD

Q

V

3, 4

V_DDQ/2+0.12

0.2

V_DDQ/2−0.12

V_DDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | I_OH| = (V_DDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I_OL= (V_DDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I standards.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 16 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Capacitance (TA = 25°C, f = 1 MHz)

Parameter

Input capacitance

Symbol

Test conditions

MIN.

MAX.

Unit

C_IN

V_IN= 0 V

5

pF

(Address, Control)

Input / Output capacitance

(DQ, CQ, CQ#)

C_I/O

C_clk

V_I/O= 0 V

V_clk= 0 V

7

6

pF

Clock Input capacitance

Remark These parameters are periodically sampled and not 100% tested.

Thermal Characteristics

Parameter

Thermal resistance

Symbol

Substrate

4-layer

Airflow

TYP.

Unit

θ ja

0 m/s

1 m/s

0 m/s

1 m/s

0 m/s

1 m/s

0 m/s

1 m/s

21.2

13.4

20.2

13.0

0.02

0.06

0.02

0.05

2.58

°C/W

from junction to ambient air

8-layer

4-layer

8-layer

Thermal characterization parameter

from junction to the top center

of the package surface

Ψ jt

θ jc

Thermal resistance

from junction to case

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 17 of 36

μPD44324092B, μPD44324182B, μPD44324362B

AC Characteristics (TA = 0 to 70°C or TA = −40 to 85°C, V_DD= 1.8 0.1 V)

AC Test Conditions (V^DD= 1.8 0.1 V, V_DDQ = 1.4 V to V_DD

)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

V

DDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 18 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Read and Write Cycle

Parameter

Symbol

-E33, E33Y -E35, E35Y -E40, E40Y -E50, E50Y

(300 MHz) (287 MHz) (250 MHz) (200 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Unit Note

Clock

Average Clock cycle time

(K, K#, C, C#)

TKHKH

3.3

8.4

0.2

3.5

8.4

0.2

4.0

8.4

0.2

5.0

8.4

0.2

ns

1

2

Clock phase jitter (K, K#, C, C#)

Clock HIGH time (K, K#, C, C#)

Clock LOW time (K, K#, C, C#)

Clock HIGH to Clock# HIGH

(K → K#, C → C#)

TKC var

TKHKL

ns

1.32

1.49

1.5

1.7

1.6

1.8

2.0

2.2

TKLKH

TKHK#H

Clock# HIGH to Clock HIGH

(K# → K, C# → C)

Clock to data clock

TK#HKH

TKHCH

1.49

0

1.7

0

1.8

0

2.2

0

ns

1.45

1.65

1.8

2.3

(K → C, K# → C#)

PLL lock time (K, C)

TKC lock

20

30

20

30

20

30

20

30

μs

ns

3

4

K static to PLL reset

TKC reset

Output Times

CQ HIGH to CQ# HIGH

(CQ → CQ#)

CQ# HIGH to CQ HIGH

TCQHCQ#H 1.24

TCQ#HCQH 1.24

TCHQV

1.35

1.55

1.95

ns

5

(CQ# → CQ)

C, C# HIGH to output valid

C, C# HIGH to output hold

C, C# HIGH to echo clock valid

C, C# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

C HIGH to output High-Z

C HIGH to output Low-Z

0.45

0.27

0.45

0.3

0.45

0.3

0.45

0.35

0.45

ns

TCHQX

−0.45

−0.3

−0.45

−0.3

−0.45

−0.35

−0.45

TCHCQV

TCHCQX −0.45

TCQHQV

6

TCQHQX −0.27

TCHQZ

0.45

TCHQX1 −0.45

−0.45

Setup Times

Address valid to K rising edge

Synchronous load input (LD#),

read write input (R, W#) valid to

K rising edge

TAVKH

TIVKH

0.4

0.5

0.6

ns

7

Data inputs and write data

select inputs (BWx#) valid to

K, K# rising edge

TDVKH

0.3

0.35

0.4

ns

7

Hold Times

K rising edge to address hold

K rising edge to

TKHAX

TKHIX

0.4

0.5

0.6

ns

7

synchronous load input (LD#),

read write input (R, W#) hold

K, K# rising edge to data inputs

and write data select inputs

(BWx#) hold

TKHDX

0.3

0.35

0.4

ns

7

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 19 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock

cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

3.

V_DDslew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.

PLL lock time begins once V_DDand input clock are stable.

It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

K

TKC reset

or

K

TKC reset

5. Guaranteed by design.

6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold

times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise

noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

5. V_DDQ is 1.5 V DC.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 20 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Read and Write Timing

READ

(burst of 2) (burst of 2) (burst of 2)

NOP

READ

(burst of 2) (burst of 2)

NOP

WRITE

READ

1

2

3

4

5

6

7

8

9

10

TKHKH

K

TKHKL

TKLKH

TKHK#H

TK#HKH

K#

LD#

TIVKH

TKHIX

R, W#

TAVKH TKHAX

A0

A1

A2

A3

A4

Address

DQ

TKHDX

TDVKH

D20

D21

D30

D31

Q00 Q01 Q10

TCHQX

Q11

Qx2

Q40 Q41

TCQHQX

TCQHQV

TCHQX1

TCHQV

TCHQZ

TCHQX

TKHCH

TCHQV

TKHCH

CQ

TCHCQX

TCHCQV

TCQHCQ#H TCQ#HCQH

CQ#

C

TCHCQX

TCHCQV

TKHKL TKLKH TKHKH TKHK#H TK#HKH

C#

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =

HIGH) is input in the sequences of [READ]-[NOP].

3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;

however, at high clock frequencies it may be required to prevent bus contention.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 21 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Application Example

R =

250 Ω

R =

250 Ω

ZQ

CQ#

CQ

CQ#

. . .

SRAM#1

CQ

SRAM#4

DQ

A

DQ

A

LD# R, W# BWx# C/C# K/K#

V

t

SRAM

Controller

R

Data IO

Vt

Address

LD#

R

R, W#

BW#

SRAM#1 CQ/CQ#

Vt

R

SRAM#4 CQ/CQ#

Vt

Source CLK/CLK#

Return CLK/CLK#

Vt

R

R = 50 Ω

Vt = Vref

Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 22 of 36

μPD44324092B, μPD44324182B, μPD44324362B

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

Description

2R

Test Clock Input. All input are captured on the rising edge of TCK and all

outputs propagate from the falling edge of TCK.

TMS

TDI

10R

11R

Test Mode Select. This is the command input for the TAP controller state

machine.

Test Data Input. This is the input side of the serial registers placed between

TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP controller state machine and the instruction that is currently

loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between

TDI and TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 0.1 V, unless otherwise noted)

Parameter

Symbol

Conditions

MIN.

−5.0

MAX.

+5.0

Unit

μA

JTAG Input leakage current

JTAG I/O leakage current

I_LI

0 V ≤ V_IN≤ V_DD

0 V ≤ V_IN≤ V_DDQ,

Outputs disabled

I_LO

μA

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

V_IH

V_IL

1.3

−0.3

1.6

V_DD+0.3

+0.5

V

V_OH1

V_OH2

V_OL1

V_OL2

| I_OHC| = 100 μA

| I_OHT| = 2 mA

I_OLC= 100 μA

I_OLT= 2 mA

1.4

JTAG output LOW voltage

0.2

0.4

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 23 of 36

μPD44324092B, μPD44324182B, μPD44324362B

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

Test Points

0 V

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 24 of 36

μPD44324092B, μPD44324182B, μPD44324362B

JTAG AC Characteristics (T^A= 0 to 70°C)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Clock

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

t_THTH

f_TF

t_THTL

t_TLTH

50

ns

MHz

ns

20

ns

Output time

TCK LOW to TDO unknown

t_TLOX

t_TLOV

0

ns

TCK LOW to TDO valid

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

t_MVTH

t_DVTH

t_CS

5

ns

Hold time

TMS hold time

t_THMX

t_THDX

t_CH

5

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

t

THTH

TCK

t

MVTH

t

THTL

t

TLTH

TMS

TDI

t

THMX

t

DVTH

t

THDX

t

TLOV

t

TLOX

TDO

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 25 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller

when it is moved into the run-test/idle or the various data register state. The register can

be loaded when it is placed between the TDI and TDO pins. The instruction register is

automatically preloaded with the IDCODE instruction at power-up whenever the controller

is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It

allows serial test data to be passed through the RAMs TAP to another device in the scan

chain with as little delay as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit

code when the controller is put in capture-DR state with the IDCODE command loaded in

the instruction register. The register is then placed between the TDI and TDO pins when

the controller is moved into shift-DR state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents

of the RAMs I/O ring when the controller is in capture-DR state and then is placed

between the TDI and TDO pins when the controller is moved to shift-DR state. Several

TAP instructions can be used to activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary

register location. The first column defines the bit’s position in the boundary register. The

second column is the name of the input or I/O at the bump and the third column is the

bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

ID [31:28] vendor

revision no.

ID [11:1] vendor

ID no.

Part number

Organization

4M x 9

ID [27:12] part no.

ID [0] fix bit

μPD44324092B

μPD44324182B

μPD44324362B

XXXX

0000 0000 0011 1110

0000 0000 0011 1111

0000 0000 0100 0000

00000010000

1

2M x 18

1M x 36

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 26 of 36

μPD44324092B, μPD44324182B, μPD44324362B

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

no.

x9

x18 x36

no.

x9

x18 x36

no.

x9

x18 x36

NC

1

2

C#

C

6R

6P

6N

7P

7N

7R

8R

8P

9R

11P

37

38

39

40

41

42

NC

10D

9E

73

2C

74 DQ5 DQ11 DQ20 3E

3

A

NC DQ7 DQ17 10C

NC NC DQ16 11D

75

76

77

78

79

80

81

NC

NC DQ29 2D

4

A

NC

2E

1E

5

A

NC

9C

9D

6

A

NC DQ12 DQ30 2F

NC NC DQ21 3F

7

A

43 DQ4 DQ8 DQ8 11B

NC NC DQ7 11C

8

A

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

NC

1G

1F

9

A

NC

CQ

A

9B

10B

10

11

12

13

14

15

16

17

DQ0

82 DQ6 DQ13 DQ22 3G

NC

NC DQ9 10P

11A

83

84

85

86

87

88

89

90

NC

NC DQ31 2G

NC

10N

9P

A

VSS 10A

9A

DLL#

NC

1H

1J

2J

A

NC DQ1 DQ11 10M

NC NC DQ10 11N

A

8B

NC

A

7C

NC DQ14 DQ23 3K

NC NC DQ32 3J

NC

9M

9N

A

A0

LD#

A0

6C

8A

NC

2K

1K

18 DQ1 DQ2 DQ2 11L

NC

NC BW1# 7A

19

20

21

22

23

24

25

NC

NC DQ1 11M

BW0#

K

7B

6B

6A

91 DQ7 DQ15 DQ33 2L

NC

9L

92

93

94

95

96

97

98

NC

NC DQ24 3L

10L

K#

NC

1M

1L

NC DQ3 DQ3 11K

NC NC DQ12 10K

NC

NC BW3# 5B

NC BW1# BW2# 5A

NC DQ16 DQ25 3N

NC NC DQ34 3M

NC

9J

R, W#

A

4A

5C

4B

3A

2A

1A

9K

NC

1N

2M

26 DQ2 DQ4 DQ13 10J

A

27

28

29

30

31

32

33

34

NC

NC DQ4 11J

A

99 DQ8 DQ17 DQ26 3P

ZQ

NC

11H

10G

9G

VSS

CQ#

100 NC

101

NC DQ35 2N

NC

A

2P

1P

NC DQ9 DQ27 2B

NC NC DQ18 3B

102

NC DQ5 DQ5 11F

NC NC DQ14 11G

103

3R

NC

1C

1B

104

A

4R

NC

9F

105

A

4P

10F

NC DQ10 DQ19 3D

NC NC DQ28 3C

NC 1D

106

A

5P

35 DQ3 DQ6 DQ6 11E

36 NC NC DQ15 10E

107

A

5N

108

A

5R

–

109

Internal

Remark Bump ID 10A of bit no. 48 can also be used as NC if the product is x36.

Bump ID 2A of bit no. 64 can also be used as NC.

The register always indicates LOW, however.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 27 of 36

μPD44324092B, μPD44324182B, μPD44324362B

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested.

Boundary-scan register cells at output pins are used to apply test vectors, while those at

input pins capture test results. Typically, the first test vector to be applied using the

EXTEST instruction will be shifted into the boundary scan register using the PRELOAD

instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and

the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the

controller is in capture-DR mode and places the ID register between the TDI and TDO pins

in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up

and any time the controller is placed in the test-logic-reset state.

When the BYPASS instruction is loaded in the instruction register, the bypass register is

placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-

DR state. This allows the board level scan path to be shortened to facilitate testing of other

devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the

SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP

controller into the capture-DR state loads the data in the RAMs input and DQ pins into the

boundary scan register. Because the RAM clock(s) are independent from the TAP clock

(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input

buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample

metastable input will not harm the device, repeatable results cannot be expected. RAM

input signals must be stabilized for long enough to meet the TAPs input data capture setup

plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other

TAP operation except capturing the I/O ring contents into the boundary scan register.

Moving the controller to shift-DR state then places the boundary scan register between the

TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are

forced to an inactive drive state (high impedance) and the boundary register is connected

between TDI and TDO when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 28 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Output Pin States of CQ, CQ# and DQ

Instructions

Control-Register Status

Output Pin Status

CQ,CQ#

Update

SRAM

High-Z

SRAM

DQ

EXTEST

0

1

0

1

0

1

0

1

0

1

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 109).

Boundary Scan

Register

CAPTURE

Register

There are three statuses:

Update : Contents of the “Update Register” are output to the

output pin (DDR Pad).

SRAM

Output

Update

Register

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (DDR Pad).

High-Z :The output pin (DDR Pad) becomes high

impedance by controlling of the “High-Z JTAG

ctrl”.

Update

DDR

Pad

SRAM

Output

Driver

High-Z

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 29 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Boundary Scan Register Status of Output Pins CQ, CQ# and DQ

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ,CQ#

DQ

Pad

−

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

−

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

No definition

−

Pad

Internal

−

Pad

Internal

Pad

−

No definition

−

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

Boundary Scan

Register

CAPTURE

Register

There are two statuses:

Internal

Pad

: Contents of the output pin (DDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Register.

SRAM

Output

Update

Register

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

DDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 30 of 36

μPD44324092B, μPD44324182B, μPD44324362B

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with

normal operation of the device, TCK must be tied to V_SSto preclude mid level inputs. TDI and TMS may be left open

but fix them to V_DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected

also when the TAP controller is not used.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 31 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Run-Test/Idle

Update-IR

Exit1-IR

Shift-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Test-Logic-Reset

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 32 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Test-Logic-Reset

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Update-DR

Exit1-DR

Shift-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Capture-DR

Select-DR-Scan

Run-Test/Idle

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 33 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Package Dimensions

165-PIN PLASTIC BGA(15x17)

w S

B

ZD

B

E

ZE

11

10

9

8

7

A

6

5

D

4

3

2

1

R P N M L K J H G F E D C B A

INDEX MARK

w

S A

A

(UNIT:mm)

ITEM DIMENSIONS

A2

y1

S

D

E

15.00 0.10

17.00 0.10

0.30

S

w

A

1.35 0.11

0.37 0.05

0.98

A1

A2

e

y

e

x

A1

A B

S

1.00

M

b

S

+0.10

b

0.50

0.05

x

0.10

y

0.15

y1

ZD

ZE

0.25

2.50

1.50

P165F5-100-FQ1-1

Renesas Electronics Corporation 2010

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 34 of 36

μPD44324092B, μPD44324182B, μPD44324362B

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD44324092BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)

μPD44324182BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)

μPD44324362BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to

the ground and so forth.

R10DS0036EJ0200 Rev.2.00

August 2, 2011

Page 35 of 36

Revision History

μPD44324092B, μPD44324182B, μPD44324362B

Description

Summary

Rev.

1st edition

Date

Page

-

’08.03.01

New Preliminary Data Sheet

2nd edition ’10.03.01

P14

P15

DC Characteristics (Modification, Spec of I_DDand I_SB1

Thermal Characteristics (Modification, Spec)

)

Rev.1.00

Rev.2.00

’10.09.10

’11.08.02

Throughout Preliminary Data Sheet → Data Sheet

Throughout Add Lead and the extended temperature operation product

All trademarks and registered trademarks are the property of their respective owners.

C - 36

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Colophon 1.0


型号：	UPD44324092BF5-E33-FQ1-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	4MX9 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165 双倍数据速率静态存储器
文件：	总37页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44324092BF5-E33-FQ1-A [RENESAS]

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