UPD44644082F5-E50-FQ1-A

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44644082, 44644092, 44644182, 44644362

μ

72M-BIT DDR II SRAM

2-WORD BURST OPERATION

Description

The μPD44644082 is a 8,388,608-word by 8-bit, the μPD44644092 is a 8,388,608-word by 9-bit, the μPD44644182 is a

4,194,304-word by 18-bit and the μPD44644362 is a 2,097,152-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44644082, μPD44644092, μPD44644182 and μPD44644362 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K

and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 0.1 V power supply

• 165-pin PLASTIC BGA package (15 x 17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18228EJ2V0DS00 (2nd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

2006

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

μPD44644082, 44644092, 44644182, 44644362

Ordering Information

Part number

Cycle

Time

ns

Clock

Frequency

MHz

Organization Core Supply

I/O

Package

(word x bit)

Voltage

V

Interface

μPD44644082F5-E37-FQ1

μPD44644082F5-E40-FQ1

μPD44644082F5-E50-FQ1

μPD44644092F5-E37-FQ1

μPD44644092F5-E40-FQ1

μPD44644092F5-E50-FQ1

μPD44644182F5-E37-FQ1

μPD44644182F5-E40-FQ1

μPD44644182F5-E50-FQ1

μPD44644362F5-E37-FQ1

μPD44644362F5-E40-FQ1

μPD44644362F5-E50-FQ1

μPD44644082F5-E37-FQ1-A

μPD44644082F5-E40-FQ1-A

μPD44644082F5-E50-FQ1-A

μPD44644092F5-E37-FQ1-A

μPD44644092F5-E40-FQ1-A

μPD44644092F5-E50-FQ1-A

μPD44644182F5-E37-FQ1-A

μPD44644182F5-E40-FQ1-A

μPD44644182F5-E50-FQ1-A

μPD44644362F5-E37-FQ1-A

μPD44644362F5-E40-FQ1-A

μPD44644362F5-E50-FQ1-A

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

270

250

200

270

250

200

270

250

200

270

250

200

270

250

200

270

250

200

270

250

200

270

250

200

8M x 8-bit

1.8 0.1

HSTL

165-pin PLASTIC

BGA (15 x 17)

8M x 9-bit

4M x 18-bit

2M x 36-bit

8M x 8-bit

8M x 9-bit

4M x 18-bit

2M x 36-bit

1.8 0.1

HSTL

165-pin PLASTIC

BGA (15 x 17)

Lead-free

Remark Products with -A at the end of the part number are lead-free products.

Preliminary Data Sheet M18228EJ2V0DS

2

μPD44644082, 44644092, 44644182, 44644362

Pin Configurations

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44644082]

8M x 8-bit

1

CQ#

NC

2

3

A

4

5

6

7

8

9

A

10

A

11

CQ

DQ3

NC

DQ2

NC

ZQ

A

B

C

D

E

F

A

R, W# NW1#

K#

K

NC

NW0#

A

LD#

A

NC

VREF

NC

DQ6

NC

TCK

NC

DQ4

NC

DQ5

VDDQ

NC

DQ7

A

NC

A

NC

VDDQ

NC

A

NC

VREF

DQ1

NC

TMS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

G

H

J

NC

DLL#

NC

DQ0

NC

TDI

K

L

NC

M

N

P

R

NC

VSS

NC

A

C

A

TDO

A

C#

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

DQ0 to DQ7

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Nibble Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

NW0#, NW1#

K, K#

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

: DLL/PLL disable

NC

: No connection

DLL#

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Drawing for the index mark.

3. 7A is expansion address for 144Mb.

Preliminary Data Sheet M18228EJ2V0DS

3

μPD44644082, 44644092, 44644182, 44644362

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44644092]

8M x 9-bit

1

CQ#

NC

2

3

A

4

5

6

7

NC

BW0#

A

8

9

A

10

A

11

CQ

DQ4

NC

A

B

C

D

E

F

A

R, W#

A

NC

A

K#

K

LD#

A

NC

VREF

NC

DQ7

NC

TCK

NC

DQ5

NC

DQ6

VDDQ

NC

DQ8

A

NC

VDDQ

NC

A

NC

VREF

DQ2

NC

TMS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ3

NC

G

H

J

NC

DLL#

NC

ZQ

NC

K

L

NC

DQ1

NC

M

N

P

R

NC

VSS

NC

A

C

A

DQ0

TDI

TDO

A

C#

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

DQ0 to DQ8

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0#

K, K#

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

: DLL/PLL disable

NC

: No connection

DLL#

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Drawing for the index mark.

3. 7A is expansion address for 144Mb.

Preliminary Data Sheet M18228EJ2V0DS

4

μPD44644082, 44644092, 44644182, 44644362

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44644182]

4M x 18-bit

1

CQ#

NC

2

A

3

4

5

6

7

8

9

A

10

A

11

CQ

A

B

C

D

E

F

A

R, W# BW1#

K#

K

NC

BW0#

A

LD#

A

DQ9

NC

A

NC

A

NC

VDDQ

NC

A

NC

DQ8

NC

VSS

A0

VSS

A

VSS

DQ7

NC

DQ10

DQ11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

NC

DQ13

VDDQ

NC

DLL#

NC

VREF

NC

VREF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

VSS

NC

A

C

A

NC

DQ0

TDI

TDO

TCK

A

C#

A

TMS

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

DQ0 to DQ17

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0#, BW1#

K, K#

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

: DLL/PLL disable

NC

: No connection

DLL#

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Drawing for the index mark.

3. 7A is expansion address for 144Mb.

Preliminary Data Sheet M18228EJ2V0DS

5

μPD44644082, 44644092, 44644182, 44644362

165-pin PLASTIC BGA (15 x 17)

(Top View)

[μPD44644362]

2M x 36-bit

1

CQ#

NC

2

3

4

5

6

7

BW1#

BW0#

A

8

9

A

10

A

11

CQ

A

B

C

D

E

F

V^SS

A

R, W# BW2#

K#

K

LD#

A

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

BW3#

A

NC

VDDQ

NC

A

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

NC

VSS

A0

VSS

A

VSS

DQ17

NC

DQ29

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ15

NC

DQ30

DQ31

VREF

NC

G

H

J

NC

DLL#

NC

VREF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

NC

DQ11

NC

DQ35

NC

VSS

NC

A

C

A

DQ9

TMS

TDO

TCK

A

C#

A

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

DQ0 to DQ35

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0# to BW3#

K, K#

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

: DLL/PLL disable

NC

: No connection

DLL#

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Drawing for the index mark.

3. 2A is expansion address for 144Mb. 2A of this product can also be used as NC.

Preliminary Data Sheet M18228EJ2V0DS

6

μPD44644082, 44644092, 44644182, 44644362

Pin Identification

(1/2)

Symbol

Description

A0

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used

as the lowest order address bit permitting a random starting address within the burst operation on x18 and x36

devices. These inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).

DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output

data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH.

x8 device uses DQ0 to DQ7.

x9 device uses DQ0 to DQ8.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

LD#

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus

activity).

R, W#

Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#

is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times

around the rising edge of K.

BWx#

NWx#

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Configurations

for signal to data relationships.

x8 device uses NW0#, NW1#.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx#, NWx# and Dxx.

K, K#

C, C#

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All

synchronous inputs must meet setup and hold times around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

C# is used as the output timing reference for first output data. The rising edge of C is used as the output

reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the

reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and

C# are fixed to HIGH (i.e. toggle of C and C#)

Preliminary Data Sheet M18228EJ2V0DS

7

μPD44644082, 44644092, 44644182, 44644362

(2/2)

Symbol

Description

CQ, CQ#

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ

tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also

stop.

<R>

ZQ

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be

connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon

power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new

output impedance is reset by implementing power-on sequence.

DLL#

DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency

slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics

cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a

10 kΩ or less resistor.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

TDO

VREF

VDD

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

IEEE 1149.1 Test Output: 1.8 V I/O level.

HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for

range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended

DC Operating Conditions and DC Characteristics for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are not connected internally.

<R>

Preliminary Data Sheet M18228EJ2V0DS

8

μPD44644082, 44644092, 44644182, 44644362

Block Diagram

CLK

Burst

Logic

A0'

A0

D0

Q0

R

Address

Register

Address

LD#

W#

E

Compare

C#

C

A0''

A0'''

Output control

Logic

Write address

Register

K

E

A0'

Input

Register

/A0'

A0'

ZQ

0

2 :1

MUX

Memory

Array

CLK

/A0'

K

1

A0'

Output Buffer

E

DQ

0

1

K#

Input

Register

E

A0'''

Output Enable

Register

C

R, W#

R, W#`

Register

E

Preliminary Data Sheet M18228EJ2V0DS

9

μPD44644082, 44644092, 44644182, 44644362

<R>

Power-On Sequence in DDR II SRAM

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

The following power-up supply voltage application is recommended: V^SS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ

can be applied simultaneously, as long as V^DDQ does not exceed VDD by more than 0.5 V during power-up. The

following power-down supply voltage removal sequence is recommended: V^IN, VREF, VDDQ, VDD, VSS. VDD and VDDQ

can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.

Power-On Sequence

Apply power and tie DLL# to HIGH.

- Apply V^DDbefore VDDQ.

- Apply V^DDQ before VREF or at the same time as VREF.

Provide stable clock for more than 1,024 cycles to lock the DLL/PLL.

DLL/PLL Constraints

The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified

as TKC var. The DLL/PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the

DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.

Power-On Waveforms

VDD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

DLL#

Clock

Fix HIGH (or tied to V^DDQ)

1,024 cycles or more

Unstable Clock

Normal Operation

Start

Stable Clock

Preliminary Data Sheet M18228EJ2V0DS

10

μPD44644082, 44644092, 44644182, 44644362

Burst Sequence

Linear Burst Sequence Table

[μPD44644182, μPD44644362]

A0

0

A0

1

External Address

1st Internal Burst Address

1

0

Truth Table

Operation

LD# R, W#

CLK

DQ

WRITE cycle

L

L → H

Data in

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

Input clock

D(A1)

D(A2)

K(t+1) ↑

K#(t+1) ↑

L

H

L → H

Data out

Output data

Output clock

High-Z

Previous state

Load address, read data on two

consecutive C and C# rising edge

NOP (No operation)

Clock stop

Q(A1)

Q(A2)

C#(t+1) ↑

C(t+2) ↑

H

×

L → H

×

Stopped

Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst

address in accordance with the linear burst sequence.

7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet M18228EJ2V0DS

11

μPD44644082, 44644092, 44644182, 44644362

Byte Write Operation

[μPD44644082]

Operation

K

K#

−

NW0#

NW1#

Write DQ0 to DQ7

L → H

0

1

0

1

0

1

−

L → H

−

L → H

−

Write DQ0 to DQ3

Write DQ4 to DQ7

Write nothing

L → H

−

L → H

−

L → H

−

L → H

−

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST

<R>

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD44644092]

Operation

K

L → H

−

K#

−

BW0#

Write DQ0 to DQ8

Write nothing

0

1

L → H

−

L → H

−

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

<R>

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[μPD44644182]

Operation

K

L → H

−

K#

−

BW0#

BW1#

Write DQ0 to DQ17

Write DQ0 to DQ8

Write DQ9 to DQ17

Write nothing

0

1

0

1

0

1

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

<R>

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Preliminary Data Sheet M18228EJ2V0DS

12

μPD44644082, 44644092, 44644182, 44644362

[μPD44644362]

Operation

K

K#

−

BW0#

BW1#

BW2#

BW3#

Write DQ0 to DQ35

Write DQ0 to DQ8

Write DQ9 to DQ17

Write DQ18 to DQ26

Write DQ27 to DQ35

Write nothing

L → H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

−

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

<R>

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Preliminary Data Sheet M18228EJ2V0DS

13

μPD44644082, 44644092, 44644182, 44644362

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 2

Write

Load, Count = 2

READ DOUBLE

Read

WRITE DOUBLE

Count = Count + 2

Load

NOP,

Count = 2

NOP

Supply voltage provided

Power UP

Remarks 1. A0 is internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 2.

2. State machine control timing sequence is controlled by K.

Preliminary Data Sheet M18228EJ2V0DS

14

μPD44644082, 44644092, 44644182, 44644362

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol Conditions

MIN.

−0.5

0

TYP.

MAX.

Unit

V

Supply voltage

VDD

VDDQ

VIN

+2.5

Output supply voltage

Input voltage

VDD

VDD+0.5 (2.5 V MAX.)

VDDQ+0.5 (2.5 V MAX.)

70

V

Input / Output voltage

Operating ambient temperature

Storage temperature

VI/O

TA

V

°C

Tstg

−55

+125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD

Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit

V

Note

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

VDD

V

1

VREF+0.1

−0.3

VDDQ+0.3

VREF−0.1

VDDQ+0.3

0.95

V

1, 2

V

−0.3

V

VREF

0.68

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ+0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (TA = 0 to 70°C)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF+0.2

−

TYP.

MAX.

−

Unit

V

Note

1

VREF−0.2

V

<R>

Note 1. Overshoot: VIH (AC) ≤ VDD+0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ −0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Preliminary Data Sheet M18228EJ2V0DS

15

μPD44644082, 44644092, 44644182, 44644362

<R>

DC Characteristics (TA = 0 to 70°C, VDD = 1.8 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

x8, x9 x18 x36

+2

Unit Note

Input leakage current

I/O leakage current

ILI

−2

−

μA

ILO

IDD

+2

Operating supply current

(Read cycle / Write cycle)

Note1

100% read cycles -E37

T.B.D.

mA

and

-E40

T.B.D.

100% write cycles -E50

T.B.D.

50% read cycles

and

-E37

-E40

-E50

-E37

-E40

-E50

T.B.D.

50% write cycles

T.B.D.

Standby supply current

(NOP)

ISB1

Note1

T.B.D.

mA

T.B.D.

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note2

VDDQ−0.2

VDDQ/2−0.12

VSS

−

VDDQ

V

4, 5

VDDQ/2+0.12

0.2

VOL(Low) IOL ≤ 0.1 mA

VOL Note3

VDDQ/2−0.12

VDDQ/2+0.12

Notes 1. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.

2. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

4. AC load current is higher than the shown DC values.

5. HSTL outputs meet JEDEC HSTL Class I and standards.

Capacitance (TA = 25°C, f = 1 MHz)

Parameter

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

Input capacitance (Address, Control)

Input / Output capacitance

(DQ, CQ, CQ#)

4

6

5

7

pF

CI/O

VI/O = 0 V

Clock Input capacitance

Cclk

Vclk = 0 V

5

6

pF

Remark These parameters are periodically sampled and not 100% tested.

Thermal Resistance

Parameter

Thermal resistance

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

θ j-a

T.B.D.

°C/W

(junction − ambient)

Thermal resistance

(junction − case)

θ j-c

T.B.D.

°C/W

Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.

Preliminary Data Sheet M18228EJ2V0DS

16

μPD44644082, 44644092, 44644182, 44644362

AC Characteristics (TA = 0 to 70°C, VDD = 1.8 0.1 V)

AC Test Conditions (V^DD= 1.8 0.1 V, VDDQ = 1.4 V to VDD)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

VDDQ / 2

0.75 V

50 Ω

VREF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Preliminary Data Sheet M18228EJ2V0DS

17

μPD44644082, 44644092, 44644182, 44644362

Read and Write Cycle

-E37

-E40

-E50

Parameter

Symbol

Unit Note

(270 MHz)

(250 MHz)

(200 MHz)

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Clock

Average Clock cycle time (K, K#, C, C#)

Clock phase jitter (K, K#, C, C#)

Clock HIGH time (K, K#, C, C#)

Clock LOW time (K, K#, C, C#)

Clock HIGH to Clock# HIGH

(K → K#, C → C#)

TKHKH

TKC var

TKHKL

TKLKH

TKHK#H

3.7

−

8.4

0.2

−

4.0

−

8.4

0.2

−

5.0

−

8.4

0.2

−

ns

1

2

1.5

1.7

1.6

1.8

2.0

2.2

−

Clock# HIGH to Clock HIGH

(K# → K, C# → C)

TK#HKH

TKHCH

1.7

−

1.8

−

2.2

−

ns

Clock to data clock

250 to 270 MHz

200 to 250 MHz

167 to 200 MHz

133 to 167 MHz

< 133 MHz

0

1.65

1.8

2.3

2.8

3.55

−

1.8

2.3

2.8

3.55

−

(K → C, K# → C#)

0

−

0

2.3

2.8

3.55

−

0

DLL/PLL lock time (K, C)

K static to DLL/PLL reset

TKC lock

1,024

30

1,024

30

1,024

30

Cycle

ns

3

4

TKC reset

−

Output Times

<R>

CQ HIGH to CQ# HIGH (CQ → CQ#)

CQ# HIGH to CQ HIGH (CQ# → CQ)

C, C# HIGH to output valid

TCQHCQ#H

TCQ#HCQH

TCHQV

1.5

−

1.65

−

2.15

−

ns

5

0.45

C, C# HIGH to output hold

TCHQX

−0.45

−

−0.45

−

−0.45

−

C, C# HIGH to echo clock valid

C, C# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

C HIGH to output High-Z

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

0.45

−

0.45

−

0.45

−

−0.45

−

−0.45

−

−0.45

−

0.3

−

0.3

−

0.35

−

6

−0.3

−

−0.3

−

−0.35

−

0.45

−

0.45

−

0.45

−

C HIGH to output Low-Z

TCHQX1

−0.45

Setup Times

Address valid to K rising edge

Synchronous load input (LD#),

read write input (R, W#) valid to

K rising edge

TAVKH

TIVKH

0.5

−

0.5

−

0.6

−

ns

7

Data inputs and write data select

inputs (BWx#, NWx#) valid to

K, K# rising edge

TDVKH

0.35

−

0.35

−

0.4

−

ns

7

Hold Times

K rising edge to address hold

K rising edge to

TKHAX

TKHIX

0.5

−

0.5

−

0.6

−

ns

7

synchronous load input (LD#),

read write input (R, W#) hold

K, K# rising edge to data inputs and

write data select inputs (BWx#, NWx#)

hold

TKHDX

0.35

−

0.35

−

0.4

−

ns

7

Preliminary Data Sheet M18228EJ2V0DS

18

μPD44644082, 44644092, 44644182, 44644362

<R>

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock in

this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

3. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.

DLL/PLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

<R>

K

TKC reset

or

K

TKC reset

5. Guaranteed by design.

<R>

6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold

times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise

noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

5. V^DDQ is 1.5 V DC.

Preliminary Data Sheet M18228EJ2V0DS

19

μPD44644082, 44644092, 44644182, 44644362

<R>

Read and Write Timing

READ

(burst of 2) (burst of 2) (burst of 2)

NOP

READ

(burst of 2) (burst of 2)

NOP

WRITE

READ

1

2

3

4

5

6

7

8

9

10

TKHKH

K

TKHKL

TKLKH

TKHK#H

TK#HKH

K#

LD#

TIVKH

TKHIX

R, W#

TAVKH TKHAX

Address

A0

A1

A2

A3

A4

TKHDX

TDVKH

D21

D22

D31

D32

DQ

CQ

Q01 Q02 Q11

TCHQX

Q12

Qx2

Q41 Q42

TCQHQX

TCHQX1

TCHQV

TCHQZ

TCHQX

TKHCH

TCQHQV

TKHCH

TCHQV

TCHCQX

TCHCQV

TCQHCQ#H TCQ#HCQH

CQ#

C

TCHCQX

TCHCQV

TKHKL TKLKH TKHKH TKHK#H TK#HKH

C#

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (high impedance) 2.5 clocks after the last READ (LD# = LOW, R, W# = HIGH) is

input in the sequences of [READ]-[NOP].

3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;

however, at high clock frequencies it may be required to prevent bus contention.

Preliminary Data Sheet M18228EJ2V0DS

20

μPD44644082, 44644092, 44644182, 44644362

Application Example

R =

250 Ω

R =

250 Ω

ZQ

CQ#

CQ

ZQ

CQ#

CQ

. . .

SRAM#1

SRAM#4

DQ

A

DQ

A

LD# R, W# BWx# C/C# K/K#

V

t

SRAM

Controller

R

Data IO

V

t

Address

LD#

R

R, W#

BW#

SRAM#1 CQ/CQ#

V

t

R

SRAM#4 CQ/CQ#

V

t

Source CLK/CLK#

Return CLK/CLK#

V

t

R

R = 50 Ω

Vt = Vref

Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.

Preliminary Data Sheet M18228EJ2V0DS

21

μPD44644082, 44644092, 44644182, 44644362

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

TMS

TDI

10R

11R

Test Mode Select. This is the command input for the TAP controller state machine.

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between TDI and

TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

−5.0

TYP.

MAX.

+5.0

Unit

μA

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

−

ILO

0 V ≤ VIN ≤ VDDQ,

μA

Outputs disabled

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

VIH

VIL

1.3

−0.3

1.6

1.4

−

VDD+0.3

V

+0.5

−

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 μA

| IOHT | = 2 mA

IOLC = 100 μA

IOLT = 2 mA

−

JTAG output LOW voltage

0.2

0.4

−

Preliminary Data Sheet M18228EJ2V0DS

22

μPD44644082, 44644092, 44644182, 44644362

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

Preliminary Data Sheet M18228EJ2V0DS

23

μPD44644082, 44644092, 44644182, 44644362

JTAG AC Characteristics (TA = 0 to 70°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

tTHTH

fTF

50

−

20

−

ns

MHz

ns

tTHTL

tTLTH

20

−

ns

Output time

TCK LOW to TDO unknown

TCK LOW to TDO valid

tTLOX

tTLOV

0

−

ns

−

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

tMVTH

tDVTH

tCS

5

−

ns

Hold time

TMS hold time

tTHMX

tTHDX

tCH

5

−

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

tTHTH

TCK

tMVTH

tTHTL

tTLTH

TMS

TDI

tTHMX

tDVTH

tTHDX

tTLOV

tTLOX

TDO

Preliminary Data Sheet M18228EJ2V0DS

24

μPD44644082, 44644092, 44644182, 44644362

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

Part number Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 0111 1000

0000 0000 0111 1001

0000 0000 0111 1010

0000 0000 0111 1011

ID [11:1] vendor ID no.

00000010000

ID [0] fix bit

μPD44644082

μPD44644092

μPD44644182

μPD44644362

8M x 8

8M x 9

XXXX

1

00000010000

4M x 18

2M x 36

00000010000

Preliminary Data Sheet M18228EJ2V0DS

25

μPD44644082, 44644092, 44644182, 44644362

SCAN Exit Order

Bit

Signal name

x9 x18 x36

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

x9 x18 x36

Bump

ID

no.

x8

no.

x8

x9

x18 x36

no.

x8

1

2

3

4

5

6

7

8

9

C#

C

A

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

NC

10D

9E

73

NC NC NC NC

2C

74 DQ4 DQ5 DQ11 DQ20 3E

NC DQ7 DQ17 10C

75

76

77

78

79

80

81

NC NC NC DQ29 2D

A

NC

NC DQ16 11D

NC NC NC NC

2E

1E

A

NC

9C

9D

A

NC NC DQ12 DQ30 2F

NC NC NC DQ21 3F

A

43 DQ3 DQ4 DQ8 DQ8 11B

A

44

45

46

47

48

49

50

51

52

53

54

NC

NC DQ7 11C

NC NC NC NC

1G

1F

A

NC

9B

10B

11A

10A

9A

10 NC DQ0 DQ0 DQ0 11P

11 NC NC NC DQ9 10P

12 NC NC NC NC 10N

82 DQ5 DQ6 DQ13 DQ22 3G

CQ

A

83

84

85

86

87

88

89

90

NC NC NC DQ31 2G

DLL#

1H

1J

2J

13 NC NC NC NC

9P

A

NC NC NC NC

14 NC NC DQ1 DQ11 10M

15 NC NC NC DQ10 11N

A

8B

A

7C

NC NC DQ14 DQ23 3K

NC NC NC DQ32 3J

16 NC NC NC NC

17 NC NC NC NC

9M

9N

A

A0

6C

LD#

8A

NC NC NC NC

2K

1K

18 DQ0 DQ1 DQ2 DQ2 11L

19 NC NC NC DQ1 11M

NC

NC NC BW1# 7A

55 NW0# BW0# BW0# BW0# 7B

91 DQ6 DQ7 DQ15 DQ33 2L

20 NC NC NC NC

21 NC NC NC NC

9L

56

57

58

K

6B

6A

92

93

94

95

96

97

98

NC NC NC DQ24 3L

NC NC NC NC 1M

10L

K#

22 NC NC DQ3 DQ3 11K

23 NC NC NC DQ12 10K

NC

NC BW3# 5B

NC NC NC NC

1L

59 NW1# NC BW1# BW2# 5A

NC NC DQ16 DQ25 3N

NC NC NC DQ34 3M

24 NC NC NC NC

25 NC NC NC NC

9J

60

61

62

63

64

65

66

67

68

69

70

71

72

R, W#

4A

5C

4B

3A

2A

1A

9K

A

NC NC NC NC

1N

26 DQ1 DQ2 DQ4 DQ13 10J

27 NC NC NC DQ4 11J

NC NC NC NC 2M

99 DQ7 DQ8 DQ17 DQ26 3P

100 NC NC NC DQ35 2N

28

29 NC NC NC NC 10G

30 NC NC NC NC 9G

ZQ

11H

A

VSS

CQ#

101 NC NC NC NC

102 NC NC NC NC

2P

1P

NC

NC DQ9 DQ27 2B

31 NC NC DQ5 DQ5 11F

32 NC NC NC DQ14 11G

NC

NC DQ18 3B

103

104

105

106

107

108

109

A

–

3R

NC

1C

1B

4R

33 NC NC NC NC

34 NC NC NC NC

9F

4P

10F

NC DQ10 DQ19 3D

5P

35 DQ2 DQ3 DQ6 DQ6 11E

36 NC NC NC DQ15 10E

NC

NC DQ28 3C

NC NC 1D

5N

5R

Internal

Remark Bump ID 2A of bit no. 64 can also be used as NC if the product is x36.

The register always indicates LOW, however.

Preliminary Data Sheet M18228EJ2V0DS

26

μPD44644082, 44644092, 44644182, 44644362

JTAG Instructions

Instructions

EXTEST

Description

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

BYPASS

When the BYPASS instruction is loaded in the instruction register, the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD

SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

Preliminary Data Sheet M18228EJ2V0DS

27

μPD44644082, 44644092, 44644182, 44644362

Output Pin States of CQ, CQ# and DQ

Instructions

Control-Register Status

Output Pin Status

CQ,CQ#

Update

SRAM

High-Z

SRAM

DQ

EXTEST

0

1

0

1

0

1

0

1

0

1

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Boundary Scan

Register

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 109).

CAPTURE

Register

There are three statuses:

SRAM

Output

Update : Contents of the “Update Register” are output to the

output pin (QDR Pad).

Update

Register

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG ctrl”.

Update

QDR

Pad

SRAM

Output

Driver

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

Preliminary Data Sheet M18228EJ2V0DS

28

μPD44644082, 44644092, 44644182, 44644362

Boundary Scan Register Status of Output Pins CQ, CQ# and DQ

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ,CQ#

DQ

Pad

−

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

−

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

No definition

−

Pad

Internal

−

Pad

Internal

Pad

−

No definition

−

Boundary Scan

Register

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

CAPTURE

Register

There are two statuses:

Internal

SRAM

Output

Update

Register

Pad

: Contents of the output pin (QDR Pad) are

captured in the “CAPTURE Register” in the

Boundary Scan Register.

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

Preliminary Data Sheet M18228EJ2V0DS

29

μPD44644082, 44644092, 44644182, 44644362

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix

them to V^DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also

when the TAP controller is not used.

Preliminary Data Sheet M18228EJ2V0DS

30

μPD44644082, 44644092, 44644182, 44644362

Package Drawing

165-PIN PLASTIC BGA (15x17)

B

E

w

S

B

ZD

ZE

11

10

9

8

A

7

6

D

5

4

3

2

1

R P N M L K J H G F E D C B A

w

S A

INDEX MARK

A

A2

y1

S

y

e

S

A1

(UNIT:mm)

ITEM DIMENSIONS

M

b

x

S A B

D

E

15.00 0.10

17.00 0.10

0.15

w

e

1.00

A

1.40 0.11

0.40 0.05

1.00

A1

A2

b

0.50 0.05

0.08

x

y

0.10

y1

ZD

ZE

0.20

2.50

1.50

This package drawing is a preliminary version. It may be changed in the future.

Preliminary Data Sheet M18228EJ2V0DS

33

μPD44644082, 44644092, 44644182, 44644362

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD44644082F5-FQ1

μPD44644092F5-FQ1

μPD44644182F5-FQ1

μPD44644362F5-FQ1

:

165-pin PLASTIC BGA (15 x 17)

μPD44644082F5-FQ1-A : 165-pin PLASTIC BGA (15 x 17)

μPD44644092F5-FQ1-A : 165-pin PLASTIC BGA (15 x 17)

μPD44644182F5-FQ1-A : 165-pin PLASTIC BGA (15 x 17)

μPD44644362F5-FQ1-A : 165-pin PLASTIC BGA (15 x 17)

Preliminary Data Sheet M18228EJ2V0DS

34

μPD44644082, 44644092, 44644182, 44644362

Revision History

Edition/

Page

revision

Location

Description

Date

This

(Previous edition → This edition)

edition

p.8

edition

p.8

2nd edition/

Feb. 2007

Modification Pin Identification ZQ, DLL#, NC

Text has been modified.

p.10

pp.10, 11

p.13

Modification Power-On Sequence in DDR II SRAM

Text and timing chart have been modified.

Remark 2 has been added.

pp.12, 13

p.15

Addition

Byte Write Operation

p.15

Modification Recommended AC Operating Conditions Note 1 has been modified.

Modification DC Characteristics Operating supply current has been modified.

p.16

p.18

Addition

Modification

Addition

Read and Write Cycle

TCQHCQ#H and TCQ#HCQH have been added.

Note 1 has been modified.

p.19

Note 4, 5 have been added.

p.20

Addition

Read and Write Timing

TCQHCQ#H and TCQ#HCQH have been added.

Preliminary Data Sheet M18228EJ2V0DS

35

μPD44644082, 44644092, 44644182, 44644362

[ MEMO ]

Preliminary Data Sheet M18228EJ2V0DS

36

μPD44644082, 44644092, 44644182, 44644362

[ MEMO ]

Preliminary Data Sheet M18228EJ2V0DS

37

μPD44644082, 44644092, 44644182, 44644362

[ MEMO ]

Preliminary Data Sheet M18228EJ2V0DS

38

μPD44644082, 44644092, 44644182, 44644362

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

Preliminary Data Sheet M18228EJ2V0DS

39

μPD44644082, 44644092, 44644182, 44644362

•

The information in this document is current as of February, 2007. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD44644082F5-E50-FQ1-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	DDR SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165 双倍数据速率静态存储器
文件：	总40页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44644082F5-E50-FQ1-A [RENESAS]

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