UPD46184182BF1-E33-EQ1-A

Datasheet

μPD46184182B

μPD46184362B

R10DS0114EJ0200

Rev.2.00

18M-BIT DDR II SRAM

2-WORD BURST OPERATION

Nov 09, 2012

Description

The μPD46184182B is a 1,048,576-word by 18-bit and the μPD46184362B is a 524,288-word by 36-bit synchronous

double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD46184182B and μPD46184362B integrate unique synchronous peripheral circuitry and a burst counter. All input

registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

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Nov 09, 2012

Page 1 of 34

μPD46184182B, μPD46184362B

Ordering Information

Core

Supply

Voltage

Operating

Ambient

Organization

Cycle

time

Clock

frequency

Part No.

Package

(word x bit)

Temperature

μPD46184182BF1-E33-EQ1-A

μPD46184182BF1-E40-EQ1-A

μPD46184362BF1-E33-EQ1-A

μPD46184362BF1-E40-EQ1-A

μPD46184182BF1-E33Y-EQ1-A

μPD46184182BF1-E40Y-EQ1-A

μPD46184362BF1-E33Y-EQ1-A

μPD46184362BF1-E40Y-EQ1-A

μPD46184182BF1-E33-EQ1

μPD46184182BF1-E40-EQ1

μPD46184362BF1-E33-EQ1

μPD46184362BF1-E40-EQ1

μPD46184182BF1-E33Y-EQ1

μPD46184182BF1-E40Y-EQ1

μPD46184362BF1-E33Y-EQ1

μPD46184362BF1-E40Y-EQ1

1M x 18

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

3.3ns

4.0ns

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

300MHz

250MHz

TA = 0 to 70°C

165-pin

PLASTIC

BGA

1.8 ± ±0.1 V

512K x 36

1M x 18

(13 x 15)

Lead-free

1.8 ± ±0.1 V TA = −40 to 85°C

512K x 36

1M x 18

TA = 0 to 70°C

165-pin

PLASTIC

BGA

1.8 ± ±0.1 V

512K x 36

1M x 18

(13 x 15)

Lead

1.8 ± ±0.1 V TA = −40 to 85°C

512K x 36

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Nov 09, 2012

Page 2 of 34

μPD46184182B, μPD46184362B

Pin Arrangement

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD46184182B]

1M x 18

1

CQ#

NC

2

VSS/72M

DQ9

NC

3

4

5

BW1#

NC/288M

A

6

7

NC/144M

BW0#

A

8

9

A

10

VSS/36M

NC

11

CQ

A

B

C

D

E

F

A

R, W#

A

K#

K

LD#

A

NC

VDDQ

NC

A

DQ8

NC

VSS

A0

VSS

A

VSS

DQ7

NC

DQ10

DQ11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

NC

DQ13

VDDQ

NC

DLL#

NC

VREF

NC

VREF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

VSS

NC

A

C

A

NC

DQ0

TDI

TDO

TCK

A

C#

A

TMS

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ17

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

V^DD

R, W#

BW0#, BW1#

K, K#

C, C#

: Output clock

V^DDQ

V^SS

: Power Supply

CQ, CQ#

ZQ

: Echo clock

: Ground

: Output impedance matching

: PLL disable

NC

: No connection

DLL#

NC/xxM : Expansion address for xxMb

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Dimensions for the index mark.

3. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb

: 10A and 2A for 72Mb

: 10A, 2A and 7A for 144Mb

: 10A, 2A, 7A and 5B for 288Mb

2A and 10A of this product can also be used as NC.

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Nov 09, 2012

Page 3 of 34

μPD46184182B, μPD46184362B

Pin Arrangement

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD46184362B]

512K x 36

1

CQ#

NC

2

3

4

5

6

7

BW1#

BW0#

A

8

9

A

10

VSS/72M

NC

11

A

B

C

D

E

F

R, W# BW2#

K#

K

LD#

A

CQ

VSS/144M NC/36M

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

BW3#

A

NC

VDDQ

NC

A

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

NC

VSS

A0

VSS

A

VSS

DQ17

NC

DQ29

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ15

NC

DQ30

DQ31

VREF

NC

G

H

J

NC

DLL#

NC

VREF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

NC

DQ11

NC

DQ35

NC

VSS

NC

A

C

A

DQ9

TMS

TDO

TCK

A

C#

A

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ35

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

TDI

TCK

TDO

V^REF

V^DD

R, W#

BW0# to BW3# : Byte Write data select

K, K#

C, C#

CQ, CQ#

ZQ

: Input clock

: Output clock

V^DDQ

V^SS

: Power Supply

: Echo clock

: Ground

: Output impedance matching

: PLL disable

NC

: No connection

DLL#

NC/xxM : Expansion address for xxMb

Remarks 1. ×××# indicates active LOW.

2. Refer to Package Dimensions for the index mark.

3. 2A, 3A and 10A are expansion addresses : 3A for 36Mb

: 3A and 10A for 72Mb

: 3A, 10A and 2A for 144Mb

2A and 10A of this product can also be used as NC.

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Nov 09, 2012

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μPD46184182B, μPD46184362B

Pin Description

(1/2)

Symbol

Type

Input

Description

A0

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and

hold times around the rising edge of K. All transactions operate on a burst of two words

(one clock period of bus activity). A0 is used as the lowest order address bit permitting a

random starting address within the burst operation on x18 and x36 devices. These inputs

are ignored when device is deselected, i.e., NOP (LD# = HIGH).

DQ0 to

DQxx

Input/Outpu Synchronous Data IOs: Input data must meet setup and hold times around the rising

t

edges of K and K#. Output data is synchronized to the respective C and C# data clocks

or to K and K# if C and C# are tied to HIGH.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

LD#

Input

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be

defined. This definition includes address and read/write direction. All transactions operate

on a burst of 2 data (one clock period of bus activity).

R, W#

BWx#

Synchronous Read/Write Input: When LD# is LOW, this input designates the access type

(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#

must meet the setup and hold times around the rising edge of K.

Synchronous Byte Writes: When LOW these inputs cause their respective byte to be

registered and written during WRITE cycles. These signals must meet setup and hold

times around the rising edges of K and K# for each of the two rising edges comprising the

WRITE cycle. See Pin Arrangement for signal to data relationships.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx# and Dxx.

K, K#

C, C#

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge

of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally

180 degrees out of phase with K. All synchronous inputs must meet setup and hold times

around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output

data. The rising edge of C# is used as the output timing reference for first output data.

The rising edge of C is used as the output reference for second output data. Ideally, C# is

180 degrees out of phase with C. When use of K and K# as the reference instead of C

and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C#

are fixed to HIGH (i.e. toggle of C and C#)

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μPD46184182B, μPD46184362B

(2/2)

Symbol

Type

Description

CQ, CQ#

Output

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched

to the synchronous data outputs and can be used as a data valid indication. These signals

run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are

stopped in the single clock mode), CQ and CQ# will also stop.

ZQ

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the

system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,

where RQ is a resistor from this bump to ground. The output impedance can be

minimized by directly connect ZQ to V^DDQ. This pin cannot be connected directly to GND

or left unconnected. The output impedance is adjusted every 20 μs upon power-up to

account for drifts in supply voltage and temperature. After replacement for a resistor, the

new output impedance is reset by implementing power-on sequence.

DLL#

PLL Disable: When debugging the system or board, the operation can be performed at a

clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =

LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must

be HIGH and it can be connected to V^DDQ through a 10 kΩ or less resistor.

TMS

TDI

Input

Output

−

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the

JTAG function is not used in the circuit.

TCK

TDO

VREF

VDD

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG

function is not used in the circuit.

IEEE 1149.1 Test Output: 1.8 V I/O level.

When providing any external voltage to TDO signal, it is recommended to pull up to V^DD.

HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the

input buffers.

Supply

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC

Characteristics for range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.

See Recommended DC Operating Conditions and DC Characteristics for range.

VSS

Supply

Power Supply: Ground

NC

−

No Connect: These signals are not connected internally.

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μPD46184182B, μPD46184362B

Block Diagram

CLK

Burst

Logic

A0'

A0

D0

Q0

R

Address

W#

Register

E

LD#

Compare

C#

C

A0''

A0'''

Output control

Logic

Write address

Register

K

E

A0'

Input

Register

/A0'

A0'

ZQ

0

2 :1

MUX

Memory

Array

CLK

/A0'

K

1

A0'

Output Buffer

E

DQ

0

1

K#

Input

Register

E

A0'''

Output Enable

Register

C

R, W#

R, W#`

Register

E

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Nov 09, 2012

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μPD46184182B, μPD46184362B

Power-On Sequence in DDR II SRAM

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

The following power-up supply voltage application is recommended: V_SS, V_DD, V_DDQ, V_REF, then V_IN. V_DDand V_DD

can be applied simultaneously, as long as V_DDQ does not exceed V_DDby more than 0.5 V during power-up. The

Q

following power-down supply voltage removal sequence is recommended: V_IN, V_REF, V_DDQ, V_DD, V_SS. V_DDand V_DD

can be removed simultaneously, as long as V_DDQ does not exceed V_DDby more than 0.5 V during power-down.

Q

Power-On Sequence

Apply power and tie DLL# to HIGH.

Apply V_DDQ before V_REFor at the same time as V_REF

.

Provide stable clock for more than 20 μs to lock the PLL.

Continuous min.4 NOP(LD# = high) cycles are required after PLL lock up is done.

PLL Constraints

The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as

TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is

enabled, then the PLL may lock onto an undesired clock frequency.

Power-On Waveforms

V

DD/VDDQ

V

DD/VDDQ Stable (< ±0.1 V DC per 50 ns)

Fix HIGH (or tied to V^DDQ)

DLL#

Clock

20 μs or more

Stable Clock

Unstable Clock

Normal Operation

Start

4 Times NOP

LD#

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μPD46184182B, μPD46184362B

Burst Sequence

Linear Burst Sequence Table

A0

1

External Address

0

1

1st Internal Burst Address

0

Truth Table

Operation

LD# R, W# CLK

DQ

WRITE cycle

L

L → H

Data in

Load address, input write data on

consecutive K and K# rising edge

READ cycle

Input data

Input clock

Data out

D(A1)

D(A2)

K(t+1) ↑

K#(t+1) ↑

L

H

L → H

Load address, read data on

consecutive C and C# rising edge

NOP (No operation)

Clock stop

Output data

Output clock

Q(A1)

Q(A2)

C#(t+1) ↑

C(t+2) ↑

H

×

L → H

High-Z

Previous state

×

Stopped

Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst

address in accordance with the linear burst sequence.

7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

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μPD46184182B, μPD46184362B

Byte Write Operation

[μPD46184182B]

Operation

K

L → H

−±

L → H

−±

L → H

−±

L → H

−±

K#

−±

L → H

−±

L → H

−±

L → H

−±

BW0#

BW1#

Write DQ0 to DQ17

0

1

0

1

0

1

Write DQ0 to DQ8

Write DQ9 to DQ17

Write nothing

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD46184362B]

Operation

K

L → H

−±

L → H

−±

L → H

−±

L → H

−±

L → H

−±

L → H

−±

K#

−±

L → H

−±

L → H

−±

L → H

−±

L → H

−±

L → H

−±

BW0#

BW1#

BW2#

BW3#

Write DQ0 to DQ35

Write DQ0 to DQ8

Write DQ9 to DQ17

Write DQ18 to DQ26

Write DQ27 to DQ35

Write nothing

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

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μPD46184182B, μPD46184362B

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 2

WRITE DOUBLE

Load, Count = 2

READ DOUBLE

Write

Read

Count = Count + 2

Load

NOP,

Count = 2

NOP

Supply voltage provided

Power UP

Remarks 1. A0 is internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 2.

2. State machine control timing sequence is controlled by K.

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μPD46184182B, μPD46184362B

Electrical Characteristics

Absolute Maximum Ratings

Parameter

Supply voltage

Symbol

Conditions

Rating

−0.5 to +2.5±

Unit

V

V_DD

Output supply voltage

Input voltage

V_DD

Q

−0.5 to V_DD

V

V_IN

V_I/O

TA

−0.5 to V_DD+0.5 (2.5 V MAX.)

−0.5 to V_DDQ+0.5 (2.5 V MAX.)

0 to 70

V

Input / Output voltage

Operating ambient temperature

V

(E** series)

°C

°C±

°C

(E**Y series)

−40 to 85

Storage temperature

Tstg

−55 to +125±

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T^A= 0 to 70°C, TA = −40 to 85°C)

Parameter

Supply voltage

Symbol Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit Note

V_DD

1.8

V

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

V_DD

Q

1.4

V_DD

V

1

V_{IH (DC)}

V_{IL (DC)}

V_IN

V_REF+0.1

−0.3

V_DDQ+0.3

V_REF±−0.1

V_DDQ+0.3

0.95

1, 2

−0.3

V_REF

0.68

Notes 1. During normal operation, V_DDQ must not exceed V_DD

.

2. Power-up: VIH ≤ V_DDQ + 0.3 V and V_DD≤ 1.7 V and V_DDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol Conditions

MIN.

MAX.

Unit Note

V_{IH (AC)}

V_{IL (AC)}

V_REF±+0.2

V

1

±

V_REF±−0.2

Note 1. Overshoot: V_{IH (AC)}≤ V_DD+ 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V_{IL (AC)}≥±−0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

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μPD46184182B, μPD46184362B

DC Characteristics 1 (T^A= 0 to 70°C, V_DD= 1.8 ± 0.1 V)

MAX.

Parameter

Symbol

Test condition

MIN.

Unit Note

x18

x36

Input leakage current

I/O leakage current

ILI

−2

μA

+2

ILO

IDD

Operating supply current

(Read cycle / Write cycle)

VIN ≤ VIL or VIN ≥ VIH,

II/O = 0 mA,

-E33

-E40

-E33

-E40

470

430

410

380

510

470

430

400

mA

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH,

II/O = 0 mA,

Cycle = MAX.

Inputs static

|IOH| ≤ 0.1 mA

Note1

mA

V_DDQ

Output HIGH voltage

Output LOW voltage

VOH(Low)

VOH

V_DDQ−0.2

V_DDQ/2−0.12

V_SS

V

3, 4

V_DDQ/2+0.12

0.2

VOL(Low)

VOL

IOL ≤ 0.1 mA

Note2

V_DDQ/2−0.12

V_DDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | I_OH| = (V_DDQ/2)/(RQ/5) ± 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I_OL= (V_DDQ/2)/(RQ/5) ± 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I standards.

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μPD46184182B, μPD46184362B

DC Characteristics 2 (T^A= −40 to 85°C, V_DD= 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

MAX.

Unit Note

x18

x36

Input leakage current

I/O leakage current

ILI

−2

+2

μA

ILO

IDD

Operating supply current

(Read cycle / Write cycle)

VIN ≤ VIL or VIN ≥ VIH,

II/O = 0 mA,

-E33Y

-E40Y

-E33Y

-E40Y

600

560

530

500

640

600

550

520

mA

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH,

II/O = 0 mA,

mA

Cycle = MAX.

Inputs static

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH

VOL(Low) IOL ≤ 0.1 mA

VOL

V_DDQ−0.2

V_DDQ/2−0.12

V_SS

V_DD

Q

V

3, 4

Note1

V_DDQ/2+0.12

0.2

Note2

V_DDQ/2−0.12

V_DDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | I_OH| = (V_DDQ/2)/(RQ/5) ± 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I_OL= (V_DDQ/2)/(RQ/5) ± 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I standards.

R10DS0114EJ0200 Rev.2.00

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Page 14 of 34

μPD46184182B, μPD46184362B

Capacitance (TA = 25°C, f = 1 MHz)

Parameter

Symbol

Test conditions

MIN.

MAX.

Unit

Input capacitance

C_IN

V_IN= 0 V

5

pF

(Address, Control)

Input / Output capacitance

(DQ, CQ, CQ#)

C_I/O

C_clk

V_I/O= 0 V

V_clk= 0 V

7

6

pF

Clock Input capacitance

Remark These parameters are periodically sampled and not 100% tested.

Thermal Characteristics

Parameter

Thermal resistance

Symbol

Substrate

4-layer

Airflow

TYP.

Unit

θ ja

0 m/s

1 m/s

0 m/s

1 m/s

0 m/s

1 m/s

0 m/s

1 m/s

16.5

13.2

15.5

12.6

0.07

0.13

0.06

0.12

3.86

°C/W

°C/W±

°C/W

from junction to ambient air

8-layer

4-layer

8-layer

Thermal characterization parameter

from junction to the top center

of the package surface

Ψ jt±

±

Thermal resistance

from junction to case

θ jc

R10DS0114EJ0200 Rev.2.00

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μPD46184182B, μPD46184362B

AC Characteristics (TA = 0 to 70°C, TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)

AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

V

DDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

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Page 16 of 34

μPD46184182B, μPD46184362B

Read and Write Cycle

Parameter

Symbol

-E33,-E33Y

(300 MHz)

-E40,-E40Y

(250 MHz)

Unit

Note

MIN.

MAX.

MIN.

MAX.

Clock

Average Clock cycle time

(K, K#, C, C#)

TKHKH

3.3

8.4

0.2

4.0

8.4

0.2

ns

1

2

Clock phase jitter (K, K#, C, C#)

Clock HIGH time (K, K#, C, C#)

Clock LOW time (K, K#, C, C#)

Clock HIGH to Clock# HIGH

(K → K#, C → C#)

TKC var

TKHKL

TKLKH

ns

1.32

1.49

1.6

1.8

TKHK#H

Clock# HIGH to Clock HIGH

(K# → K, C# → C)

Clock to data clock

TK#HKH

TKHCH

1.49

0

1.8

0

ns

1.45

1.8

(K → C, K# → C#)

PLL lock time (K, C)

TKC lock

20

30

20

30

μs

ns

3

4

K static to PLL reset

TKC reset

Output Times

CQ HIGH to CQ# HIGH

(CQ → CQ#)

CQ# HIGH to CQ HIGH

TCQHCQ#H

TCQ#HCQH

1.24±

1.55±

ns

5

(CQ# → CQ)

C, C# HIGH to output valid

C, C# HIGH to output hold

C, C# HIGH to echo clock valid

C, C# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

C HIGH to output High-Z

C HIGH to output Low-Z

TCHQV

TCHQX

0.45

0.27

0.45

0.3

ns

−0.45

−0.27

−0.45

−0.3

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

6

0.45

TCHQX1

−0.45

Setup Times

Address valid to K rising edge

Synchronous load input (LD#),

read write input (R, W#) valid to

K rising edge

TAVKH

TIVKH

0.4

0.5

ns

7

Data inputs and write data

select inputs (BWx#) valid to

K, K# rising edge

TDVKH

0.3

0.35

ns

7

Hold Times

K rising edge to address hold

K rising edge to

TKHAX

TKHIX

0.4

0.5

ns

7

synchronous load input (LD#),

read write input (R, W#) hold

K, K# rising edge to data inputs

and write data select inputs

(BWx#) hold

TKHDX

0.3

0.35

ns

7

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Nov 09, 2012

Page 17 of 34

μPD46184182B, μPD46184362B

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock

cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

3.

V_DDslew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.

PLL lock time begins once V_DDand input clock are stable.

It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

K

TKC reset

or

K

TKC reset

5. Guaranteed by design.

6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold

times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise

noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

5. V_DDQ is 1.5 V DC.

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Nov 09, 2012

Page 18 of 34

μPD46184182B, μPD46184362B

Read and Write Timing

READ

(burst of 2) (burst of 2) (burst of 2)

NOP

READ

(burst of 2) (burst of 2)

NOP

WRITE

READ

1

2

3

4

5

6

7

8

9

10

TKHKH

K

TKHKL

TKLKH

TKHK#H

TK#HKH

K#

LD#

TIVKH

TKHIX

R, W#

TAVKH TKHAX

A0

A1

A2

A3

A4

Address

DQ

TKHDX

TDVKH

D20

D21

D30

D31

Q00 Q01 Q10

TCHQX

Q11

Qx2

Q40 Q41

TCQHQX

TCQHQV

TCHQX1

TCHQV

TCHQZ

TCHQX

TKHCH

TCHQV

TKHCH

CQ

TCHCQX

TCHCQV

TCQHCQ#H TCQ#HCQH

CQ#

C

TCHCQX

TCHCQV

TKHKL TKLKH TKHKH TKHK#H TK#HKH

C#

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =

HIGH) is input in the sequences of [READ]-[NOP].

3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;

however, at high clock frequencies it may be required to prevent bus contention.

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Nov 09, 2012

Page 19 of 34

μPD46184182B, μPD46184362B

Application Example

R =

250 Ω

R =

250 Ω

ZQ

CQ#

CQ

ZQ

CQ#

CQ

. . .

SRAM#1

SRAM#4

DQ

A

DQ

A

LD# R, W# BWx# C/C# K/K#

V

t

SRAM

Controller

R

Data IO

Vt

Address

LD#

R

R, W#

BW#

SRAM#1 CQ/CQ#

Vt

R

SRAM#4 CQ/CQ#

Vt

Source CLK/CLK#

Return CLK/CLK#

Vt

R

R = 50 Ω

Vt = Vref

Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.

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Nov 09, 2012

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μPD46184182B, μPD46184362B

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

Description

2R

Test Clock Input. All input are captured on the rising edge of TCK and all

outputs propagate from the falling edge of TCK.

TMS

TDI

10R

11R

Test Mode Select. This is the command input for the TAP controller state

machine.

Test Data Input. This is the input side of the serial registers placed between

TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP controller state machine and the instruction that is currently

loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between

TDI and TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter

Symbol

Conditions

MIN.

−5.0

MAX.

+5.0

Unit

JTAG Input leakage current

JTAG I/O leakage current

I_LI

0 V ≤ V_IN≤ V_DD

0 V ≤ V_IN≤ V_DDQ,

Outputs disabled

μA

±

I_LO

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

V_IH

V_IL

1.3

−0.3

1.6

V_DD+0.3

+0.5

V

V_OH1

V_OH2

V_OL1

V_OL2

| I_OHC| = 100 μA

V

| I_OHT| = 2 mA

1.4

V

JTAG output LOW voltage

I

_OLC= 100 μA

0.2

0.4

V

I_OLT= 2 mA

V

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 21 of 34

μPD46184182B, μPD46184362B

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 22 of 34

μPD46184182B, μPD46184362B

JTAG AC Characteristics (T^A= 0 to 70°C)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Clock

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

t_THTH

f_TF

t_THTL

t_TLTH

50

±

ns

MHz

ns

20

ns

Output time

TCK LOW to TDO unknown

TCK LOW to TDO valid

t_TLOX

t_TLOV

0

ns

±

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

t_MVTH

t_DVTH

t_CS

5

ns

Hold time

TMS hold time

t_THMX

t_THDX

t_CH

5

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

t

THTH

TCK

t

MVTH

t

THTL

t

TLTH

TMS

TDI

t

THMX

t

DVTH

t

THDX

t

TLOV

t

TLOX

TDO

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Nov 09, 2012

Page 23 of 34

μPD46184182B, μPD46184362B

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller

when it is moved into the run-test/idle or the various data register state. The register can

be loaded when it is placed between the TDI and TDO pins. The instruction register is

automatically preloaded with the IDCODE instruction at power-up whenever the controller

is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It

allows serial test data to be passed through the RAMs TAP to another device in the scan

chain with as little delay as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit

code when the controller is put in capture-DR state with the IDCODE command loaded in

the instruction register. The register is then placed between the TDI and TDO pins when

the controller is moved into shift-DR state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents

of the RAMs I/O ring when the controller is in capture-DR state and then is placed

between the TDI and TDO pins when the controller is moved to shift-DR state. Several

TAP instructions can be used to activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary

register location. The first column defines the bit’s position in the boundary register. The

second column is the name of the input or I/O at the bump and the third column is the

bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

107

bit

Boundary register

bit

ID Register Definition

ID [31:28] vendor

revision no.

ID [11:1] vendor

ID no.

Part number

Organization

ID [27:12] part no.

ID [0] fix bit

μPD46184182B

μPD46184362B

1M x 18

512K x 36

XXXX

0000 0000 0001 0011

0000 0000 0001 0100

00000010000

1

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μPD46184182B, μPD46184362B

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

no.

x18

x36

no.

x18

x36

no.

x18

x36

1

C#

C

6R

6P

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

NC

10D

9E

73

74

NC

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1J

2

DQ11

NC

DQ20

DQ29

3

A

6N

DQ7

NC

DQ17

DQ16

10C

11D

9C

75

4

A

7P

76

NC

5

A

7N

NC

77

6

A

7R

9D

78

DQ12

NC

DQ30

DQ21

DQ8

7

A

8R

11B

11C

9B

79

8

A

8P

NC

DQ7

80

NC

9

A

9R

NC

CQ

–

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

DQ0

11P

10P

10N

9P

10B

11A

Internal

9A

82

DQ13

NC

DQ22

DQ31

NC

DQ9

83

NC

84

NC

A

85

2J

DQ1

NC

DQ11

DQ10

10M

11N

9M

A

8B

86

DQ14

NC

DQ23

DQ32

3K

3J

A

7C

87

A0

NC

6C

88

NC

2K

1K

2L

9N

LD#

8A

89

DQ2

11L

11M

9L

NC

BW1#

7A

90

DQ15

NC

DQ33

DQ24

NC

DQ1

BW0#

K

7B

91

3L

NC

6B

92

NC

1M

1L

10L

11K

10K

9J

K#

6A

93

DQ3

BW3#

BW2#

5B

94

DQ16

NC

DQ25

DQ34

3N

3M

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

DQ12

BW1#

5A

95

NC

R, W#

4A

96

NC

9K

A

5C

97

DQ4

NC

DQ13

DQ4

10J

11J

11H

10G

9G

4B

98

DQ17

NC

DQ26

DQ35

A

NC

3A

99

ZQ

NC

DLL#

CQ#

1H

100

101

102

103

104

105

106

107

NC

A

1A

NC

DQ9

NC

DQ27

DQ18

2B

DQ5

11F

11G

9F

3B

A

NC

DQ14

DQ15

NC

1C

A

NC

1B

A

10F

11E

10E

DQ10

NC

DQ19

DQ28

3D

A

DQ6

3C

A

NC

1D

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μPD46184182B, μPD46184362B

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested.

Boundary-scan register cells at output pins are used to apply test vectors, while those at

input pins capture test results. Typically, the first test vector to be applied using the

EXTEST instruction will be shifted into the boundary scan register using the PRELOAD

instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and

the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the

controller is in capture-DR mode and places the ID register between the TDI and TDO pins

in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up

and any time the controller is placed in the test-logic-reset state.

When the BYPASS instruction is loaded in the instruction register, the bypass register is

placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-

DR state. This allows the board level scan path to be shortened to facilitate testing of other

devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the

SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP

controller into the capture-DR state loads the data in the RAMs input and DQ pins into the

boundary scan register. Because the RAM clock(s) are independent from the TAP clock

(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input

buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample

metastable input will not harm the device, repeatable results cannot be expected. RAM

input signals must be stabilized for long enough to meet the TAPs input data capture setup

plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other

TAP operation except capturing the I/O ring contents into the boundary scan register.

Moving the controller to shift-DR state then places the boundary scan register between the

TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are

forced to an inactive drive state (high impedance) and the boundary register is connected

between TDI and TDO when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 26 of 34

μPD46184182B, μPD46184362B

Output Pin States of CQ, CQ# and DQ

Instructions

Control-Register Status

Output Pin Status

CQ,CQ#

Update

SRAM

High-Z

SRAM

DQ

EXTEST

0

1

0

1

0

1

0

1

0

1

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 48).

Boundary Scan

Register

CAPTURE

Register

There are three statuses:

Update : Contents of the “Update Register” are output to the

output pin (DDR Pad).

SRAM

Output

Update

Register

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (DDR Pad).

High-Z :The output pin (DDR Pad) becomes high

impedance by controlling of the “High-Z JTAG

ctrl”.

Update

DDR

Pad

SRAM

Output

Driver

High-Z

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

R10DS0114EJ0200 Rev.2.00

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Page 27 of 34

μPD46184182B, μPD46184362B

Boundary Scan Register Status of Output Pins CQ, CQ# and DQ

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ,CQ#

Pad

DQ

Pad

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

−±−

No definition

−±−

Pad

Internal

−±−

Internal

Pad

No definition

−±−

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

Boundary Scan

Register

CAPTURE

Register

There are two statuses:

Internal

Pad

: Contents of the output pin (DDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Register.

SRAM

Output

Update

Register

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

DDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 28 of 34

μPD46184182B, μPD46184362B

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with

normal operation of the device, TCK must be tied to V_SSto preclude mid level inputs. TDI and TMS may be left open

but fix them to V_DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected

also when the TAP controller is not used.

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 29 of 34

μPD46184182B, μPD46184362B

Run-Test/Idle

Update-IR

Exit1-IR

Shift-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Test-Logic-Reset

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Nov 09, 2012

Page 30 of 34

μPD46184182B, μPD46184362B

Test-Logic-Reset

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Update-DR

Exit1-DR

Shift-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Capture-DR

Select-DR-Scan

Run-Test/Idle

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 31 of 34

μPD46184182B, μPD46184362B

Package Dimensions

165-PIN PLASTIC BGA(13x15)

w

S

B

ZD

B

E

ZE

11

10

9

8

7

A

6

5

D

4

3

2

1

R P N M L K J H G F E D C B A

w

S A

INDEX MARK

A

(UNIT:mm)

ITEM DIMENSIONS

A2

y1

S

D

E

13.00±0.10

15.00±0.10

0.30

S

w

A

1.35±0.11

0.37±0.05

0.98

A1

A2

e

y

e

x

A1

S

1.00

M

b

A B

+0.10

−0.05

b

0.50

x

0.10

0.15

y

y1

ZD

ZE

0.25

1.50

0.50

T165F1-100-EQ1

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 32 of 34

μPD46184182B, μPD46184362B

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD46184182BF1-EQ1

μPD46184362BF1-EQ1

:

165-pin PLASTIC BGA (13 x 15)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to

the ground and so forth.

R10DS0114EJ0200 Rev.2.00

Nov 09, 2012

Page 33 of 34

Revision History

μPD46184182B, μPD46184362B

Description

Summary

Rev.

Date

Page

-

Rev.1.00

Rev.2.00

’12.06.01

’12.11.09

New Data Sheet

Addition : -E33,-E33Y series, Lead series

Deletion : -E50,-E50Y series

ALL

All trademarks and registered trademarks are the property of their respective owners.

C - 34


型号：	UPD46184182BF1-E33-EQ1-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	DDR SRAM 时钟双倍数据速率静态存储器内存集成电路
文件：	总34页 (文件大小：605K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD46184182BF1-E33-EQ1-A [RENESAS]

相关型号：

UPD46184182BF1-E40-EQ1

UPD46184182BF1-E40Y-EQ1

UPD46184184BF1-E33-EQ1

UPD46184184BF1-E33-EQ1-A

UPD46184184BF1-E33Y-EQ1

UPD46184184BF1-E40-EQ1

UPD46184184BF1-E40-EQ1-A

UPD46184184BF1-E40Y-EQ1

UPD46184184BF1-E40Y-EQ1-A

UPD46184185BF1-E33-EQ1