UPD4704G [RENESAS]
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT BIDIRECTIONAL BINARY COUNTER, PDSO20, 0.300 INCH, PLASTIC, SOP-20;
| 型号： | UPD4704G |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT BIDIRECTIONAL BINARY COUNTER, PDSO20, 0.300 INCH, PLASTIC, SOP-20 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4704
EXTENSION 8-BIT UP/DOWN COUNTER
CMOS INTEGRATED CIRCUITS
DESCRIPTION
The µPD4704 is 8-bit up/down counters for extension of the µPD4702 incremental encoder counter. They perform
an up/down-count using an 8-bit width with a µPD4702 carry or borrow signal as input. In addition, a carry output
and borrow output are also provided for further extension of the count width, enabling extension to be performed
in 8-bit units.
FEATURES
•
•
•
•
8-bit up/down counter for extension of µPD4702
Count data output controllable (latch and 3-state output)
Extension carry and borrow outputs
CMOS, single +5 V power supply
PIN NAMES
PIN CONFIGURATION (Top View)
Up
: Up-count input
Down : Down-count input
Reset : Counter reset input
Reset
A
1
20
19
18
17
16
15
14
13
12
11
V
DD
2
Carry
Borrow
STB
STB
OE
: Latch strobe signal input
: Output control signal input
: Count data outputs
B
3
CD0-7
NC
4
Carry : Carry pulse output
Borrow : Borrow pulse output
CD
CD
CD
CD
0
5
OE
1
2
3
6
CD
CD
CD
CD
NC
7
6
5
7
ORDERING INFORMATION
8
NC
9
4
Part Number
µPD4704C
µPD4704G
Package
20-pin plastic DIP
20-pin plastic SOP (300 mil)
VSS
10
(300 mil)
Document No. IC-3305A (2nd edition)
(O. D. No. IC-8762B)
Date Published April 1997 P
Printed in Japan
1993
©
µPD4704
BLOCK DIAGRAM
Reset
A
B
Carry
Phase
Discrimination
Edge Detection
8-Bit Up/Down Counter
Borrow
STB
OE
8-Bit Latch
3-State Output
CD0–7
PIN FUNCTIONS
Pin Name
Input/Output
Input
Function
Up
Up-count & down-count signal input pins
Count is performed on rise of signal.
Down
D0 to 7
Output
Count data output pins. Activated when OE is “L”, high impedance outputs when OE
is “H”.
(3-state)
Carry
Output
Output
8-bit counter carry signal output pin (active-low)
8-bit counter borrow signal output pin (active-low)
Borrow
RESET
Input
8-bit counter reset signal output pin
Counter is reset when this pin is “H”.
(Schmitt)
OE
Input
Input
Count data output control signal input pin
STB
Counter data output latch signal. Data is latched on the fall of STB, and is held while
STB = “L”.
VDD
Power supply input pin
Ground pin
GND
2
µPD4704
TRUTH TABLE 1 (COUNTER BLOCK)
× : H or L
UP
×
DOWN
RESET
Carry
Borrow
Remarks
×
H
H
L
×
×
×
×
Reset
H
Reset
H
×
Down-count
Up-count
H
L
L
L
L
L
×
×
×
H
L
×
×
×
L
H
L
Disabled (count undefined)
Disabled (count undefined)
L
L
H
L
Borrow output when count = 00H
Carry output when count = 0FFH
H
TRUTH TABLE 2 (LATCH & OUTPUT BLOCKS)
× : H or L
STB
×
OE
H
L
CD0 to CD7
Output disable (3-state)
Output enable
×
H
×
Data through (count value load)
Data latch (count value retention)
L
×
3
µPD4704
1. DESCRIPTION OF OPERATIONS
(1) Count operation
The µPD4704 is designed as 8-bit up/down counter for extension of the µPD4702. The first-stage Carry output
is connected to the UP input of the µPD4704, and similarly, the Borrow output is connected to the DOWN input. A
count is executed on the rising edge of the UP input or DOWN input.
If the µPD4704 is to be used alone, without being connected to the µPD4702, either UP or the DOWN must be "H".
If a count pulse is input to UP or DOWN while the other is "L", the count value may change.
(2) Latch operation
An R-S flip-flop is inserted in the latch circuit input as shown in Fig. 1, and when STB is changed from "H" to "L"
while the UP or DOWN input is "L", the internal latch signal STB' remains at "H" until the end of the count operation.
Therefore, latching is not performed during a count operation. If STB changes from "H" to "L" tSUDSTB1 (40 ns) or
more after the falling edge of UP or DOWN, the post-count data is latched, and if STB changes from "H" to "L" within
tSUDSTB2 (10 ns) after the falling edge of UP or DOWN, then conversely, the pre-count data is latched.
Caution is required since, when UP or DOWN is "L" (during a count operation), the latch operation is kept waiting
even if STB is changed from "H" to "L", and therefore if a reset is executed the latch contents will also be reset (see
Figs. 2 and 3).
Fig. 1 STB Input Circuit
From UP/DOWN Circuit
Count Clock
STB'
STB
4
µPD4704
Fig. 2 Relation Between STB Timing and Counter Value
UP/DOWN
STB
tSUDSTB1
tSUDSTB2
Post-count value latched
Either pre- or post-count value latched
Pre-count value latched
Fig. 3 STB and RESET Timing
UP/DOWN
tSUDSTB1
tDUDCD
RESET
STB
If STB changes from "H" to "L" and a reset is
executed in this period, the latch is also reset.
(3) Carry & borrow outputs
If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the
Carry output (the pulse width is virtually the same as the UP or DOWN pulse L period). Similarly, if the counter
performs a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output.
A Borrow pulse is also output if a down-count operation is performed while RESET is "H" (during a reset), and
therefore, when a µPD4704 is added, a reset must be executed at the same time.
5
µPD4704
2. OPERATING PRECAUTIONS
As the µPD4704 incorporates an 8-bit counter, a large transient current flows in the case of a count value which
changes all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the
power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 µF)
be connected between VDD and VSS right next to the IC as shown in Fig. 4.
Fig. 4 Decoupling Capacitor
+5 V
C
VDD
µPD4704
C : 0.1 uF tantalum electrolytic laminated
ceramic capacitor, etc.
VSS
6
µPD4704
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS = 0 V)
PARAMETER
Supply voltage
SYMBOL
VDD
RATING
–0.5 to +7.0
UNIT
V
Input voltage
VI
–1.0 to VDD +1.0
–0.5 to VDD +0.5
–40 to +85
V
Output voltage
VO
V
Operating temperature
Storage temperature
Permissible loss
Topt
Tstg
°C
–65 to +150
°C
PD
500 (DIP)
200 (SOP)
RATING
mW
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %)
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
MIN.
MAX.
0.8
Input voltage low
VIL
VIH
VIH
VOL
VOH
IDD
V
V
Reset
2.6
2.2
Input voltage high
Other than the above
IOL = 12 mA
V
Output voltage low
0.45
V
Output voltage high
IOH = –4 mA
VDD – 0.8
V
Static consumption current
Input current
VI = VDD, VSS
50
1.0
10
12
µA
µA
µA
mA
V
II
VI = VDD, VSS
–1.0
–10
3-state output leak current
Dynamic consumption current
Hysteresis voltage
IOFF
IDD dyn
VH
fIN = 16 MHz, CL = 50 pF
Reset
0.2
AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %)
PARAMETER
Cycle
SYMBOL
tCYCT
TEST CONDITIONS
fin = 16 MHz
MIN.
60
MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWUDL
tPWUDH
tSRSUD
tSUDM
25
Up
Input pulse width
35
Down
Setup time
0
Up/down switchover setupt time
Reset time
100
tDRSCD
tDUDCD
tDOECD
tDSTBCD
tFOECD
60
70
Output delay
CD0 to 7
Output delay
50
Output delay
50
Float time
40
tDUDCB1
tDUDCB2
tPWCB
50
Carry
Output delay
100
Borrow
Output pulse width
Reset pulse width
30
40
40
10
RESET
STB
tPWRS
tSUDSTB1
tSUDSTB2
Setting time
7
µPD4704
AC Timings
Fig. 1 Up/Down Signal Input Timing
tCYCT
tPWUDL
tPWUDH
UP/DOWN
tCYCT
tPWUDH
tSUDM
tPWUDL
Fig. 2 Count Data Output Timing
tPWRS
tSRSUD
RESET
UP/DOWN
tDRSCD
tDUDCD
Hi-Z
Hi-Z
CD0–CD7
OE
tDOECD
tFOECD
tDSTBCD
tDSTBCD
tSUDSTB1
STB
Fig. 3 Carry/Borrow Signal Output Timing
tDUDCB1
tDUDCB2
UP/DOWN
tPWCB
Carry
tDUDCB1
tDUDCB2
tPWCB
Borrow
Fig. 4 Strobe Signal Output Timing
tSUDSTB1
tSUDSTB2
UP/DOWN
STB
8
µPD4704
Consumption Current Measurement Circuit
Measurement Conditions
A, B inputs
fIN = 16 MHz
A
B
D0
D1
2.6 V
0.8 V
CL
CL
STB input connected to VDD or OE input connected to VSS.
Load on all outputs, CL = 50 pF.
VDD
STB
OE
D7
CL
AC Test Input Waveform
VIH
VIL
VIH = 2.6 V (RESET input)
VIH = 2.2 V (inputs other than RESET)
VIL = 0.8 V
Timing measurement is performed at 1.5 V.
•
3 state output
Output
Output
OE
1.5 V
tDFOECD
R
C
C
tDOECD
VOH
90 %
1.5 V
VDD
R
0 V
VDD
Output
10 %
1.5 V
VOL
R = 1 kΩ
C = 50 pF
9
µPD4704
Sample Application Circuits
16-bit counter
8
Data Bus
Incremental Rotary Encoder
8
8
A
Carry
UP
Borrow
B
Down
D0
D0
D7
STB
OE
STB
OE
R
D7
R
RESET
µPD4702
µPD4704
CSL
CSH
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
10
µPD4704
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product.
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
TYPES OF SURFACE MOUNT DEVICE
For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (IEI-1207).
µPD4704G
Soldering process
Infrared ray reflow
Soldering conditions
Symbol
Peak package’s surface temperature: 235 °C or below,
Reflow time: 30 seconds or below (210 °C or higher),
Number of reflow process: 2, Exposure limit*: None
IR35-00-2
VPS
Peak package’s surface temperature: 215 °C or below,
Reflow time: 40 seconds or below (200 °C or higher),
Number of reflow process: 2, Exposure limit*: None
VP15-00-2
WS60-00-1
●
Wave soldering
Partial heating method
Solder temperature: 260 °C or below,
Flow time: 10 seconds or below,
Number of flow process: 1, Exposure limit*: None
Terminal temperature: 300 °C or below,
Flow time: 10 seconds or below,
Exposure limit*: None
*
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Note Do not apply more than a single process at once, except for “Partial heating method”.
TYPES OF THROUGH HOLE MOUNT DEVICE
µPD4704C
Soldering process
Wave soldering
Soldering conditions
Solder temperature: 260 °C or below,
Symbol
Flow time: 10 seconds or below
REFERENCE
Dcodument name
Document No.
IEI-1212
NEC semiconductor device reliability/quality control system
Quality grade on NEC semiconductor devices
Semiconductor device mounting technology manual
Semiconductor device package manual
IEI-1209
IEI-1207
IEI-1213
Guide to quality assurance for semiconductor devices
Semiconductor selection guide
MEI-1202
MF-1134
11
µPD4704
20PIN PLASTIC DIP (300 mil)
20
11
10
1
A
K
L
P
I
J
H
C
F
D
R
M
G
B
M
N
NOTES
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
25.40 MAX.
1.27 MAX.
2.54 (T.P.)
1.000 MAX.
0.050 MAX.
0.100 (T.P.)
2) ltem "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
1.1 MIN.
3.5±0.3
0.043 MIN.
0.138±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.300 (T.P.)
0.252
0.51 MIN.
4.31 MAX.
5.08 MAX.
7.62 (T.P.)
6.4
J
K
L
+0.10
0.25
+0.004
0.010
M
–0.05
–0.003
N
P
R
0.25
0.01
0.9 MIN.
0~15°
0.035 MIN.
0~15°
P20C-100-300A,C-1
12
µPD4704
20 PIN PLASTIC SOP (300 mil)
20
11
detail of lead end
1
10
A
H
I
J
L
B
C
N
M
M
D
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
13.00 MAX.
0.78 MAX.
1.27 (T.P.)
0.512 MAX.
0.031 MAX.
0.050 (T.P.)
+0.10
0.40
+0.004
0.016
D
–0.05
–0.003
E
F
G
H
I
0.1±0.1
1.8 MAX.
1.55
0.004±0.004
0.071 MAX.
0.061
7.7±0.3
5.6
0.303±0.012
0.220
J
1.1
0.043
+0.004
0.008
+0.10
0.20
K
L
–0.002
–0.05
+0.008
0.024
0.6±0.2
–0.009
M
N
0.12
0.10
0.005
0.004
+7°
3°
+7°
3°
P
–3°
–3°
P20GM-50-300B, C-4
13
µPD4704
[MEMO]
14
µPD4704
[MEMO]
15
µPD4704
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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