UPD48576236FF-E24-DW1-A

Datasheet

μPD48576209

μPD48576218

μPD48576236

R10DS0063EJ0300

Rev.3.00

576M-BIT Low Latency DRAM

Common I/O

Oct 01, 2012

Description

The μPD48576209 is a 67,108,864-word by 9 bit, the μPD48576218 is a 33,554,432 word by 18 bit and the

μPD48576236 is a 16,777,216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with

advanced CMOS technology using one-transistor memory cell.

The μPD48576209, μPD48576218 and μPD48576236 integrate unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and

CK#. These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

Specification

Features

• Density: 576M bit

• SRAM-type interface

• Organization

• Double-data-rate architecture

• PLL circuitry

-

Common I/O: 8M words x 9 bits x 8 banks

4M words x 18 bits x 8 banks

• Cycle time:

1.875 ns @ t^RC= 15 ns

2M words x 36 bits x 8 banks

2.5 ns @ tRC = 15 ns

2.5 ns @ t^RC= 20 ns

3.3 ns @ t^RC= 20 ns

• Operating frequency: 533 / 400 / 300 MHz

• Interface: HSTL I/O

• Package: 144-pin TAPE FBGA

• Non-multiplexed addresses

-

Package size: 18.5 x 11

Leaded and Lead free

• Multiplexing option is available.

• Power supply

• Data mask for WRITE commands

• Differential input clocks (CK and CK#)

• Differential input data clocks (DK and DK#)

• Data valid signal (QVLD)

-

2.5 V V^EXT

1.8 V V^DD

1.5 V or 1.8 V V^DDQ

• Refresh command

-

Auto Refresh

• Programmable burst length: 2 / 4 / 8 (x9 / x18 / x36)

• User programmable impedance output (25 Ω - 60 Ω)

• JTAG boundary scan

16K cycle / 32 ms for each bank

128K cycle / 32 ms for total

• Operating case temperature : Tc = 0 to 95°C

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 1 of 52

μPD48576209, μPD48576218, μPD48576236

Ordering Information

Part number

Cycle

Clock

Random Organization Core Supply Core Supply Output Supply Package

Time Frequency Cycle

(word x bit)

Voltage

(VEXT)

V

Voltage

(VDD)

V

Voltage

(VDDQ)

V

ns

1.875

2.5

MHz

533

400

300

533

400

300

533

400

300

533

400

300

533

400

300

533

400

300

ns

15

20

15

20

15

20

15

20

15

20

15

20

μPD48576209FF-E18-DW1-A

μPD48576209FF-E24-DW1-A

μPD48576209FF-E25-DW1-A

μPD48576209FF-E33-DW1-A

μPD48576218FF-E18-DW1-A

μPD48576218FF-E24-DW1-A

μPD48576218FF-E25-DW1-A

μPD48576218FF-E33-DW1-A

μPD48576236FF-E18-DW1-A

μPD48576236FF-E24-DW1-A

μPD48576236FF-E25-DW1-A

μPD48576236FF-E33-DW1-A

μPD48576209FF-E18-DW1

μPD48576209FF-E24-DW1

μPD48576209FF-E25-DW1

μPD48576209FF-E33-DW1

μPD48576218FF-E18-DW1

μPD48576218FF-E24-DW1

μPD48576218FF-E25-DW1

μPD48576218FF-E33-DW1

μPD48576236FF-E18-DW1

μPD48576236FF-E24-DW1

μPD48576236FF-E25-DW1

μPD48576236FF-E33-DW1

64 M x 9

2.5 + 0.13

2.5 – 0.12

1.8 ± 0.1

1.5 ± 0.1

or

144-pin

TAPE FBGA

(18.5 x 11)

2.5

1.8 ± 0.1

3.3

1.875

2.5

32 M x 18

16 M x 36

64 M x 9

Lead-free

2.5

3.3

1.875

2.5

3.3

1.875

2.5

2.5 + 0.13

2.5 – 0.12

1.8 ± 0.1

1.5 ± 0.1

or

144-pin

TAPE FBGA

(18.5 x 11)

2.5

1.8 ± 0.1

3.3

1.875

2.5

32 M x 18

16 M x 36

Lead

2.5

3.3

1.875

2.5

3.3

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Oct 01, 2012

Page 2 of 52

μPD48576209, μPD48576218, μPD48576236

Pin Arrangement

# indicates active LOW signal.

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x9]

1

2

3

4

5

6

7

8

9

10

VEXT

DQ0

DQ1

QK0#

DQ2

DQ3

A2

11

12

TCK

V^DD

V^TT

A

B

C

D

E

F

V^REF

VDD

VTT

VSS

VEXT

VSS

TMS

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

V^SSQ

V^DDQ

V^SSQ

V^DDQ

V^SSQ

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VDD

Note 1

QK0

VSS

(A22)

Note 3

DNU

Note 3

DNU

A21

A5

A20

QVLD

A0

G

H

J

A8

A6

A7

VSS

V^DD

VDD

VSS

A17

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

A1

A4

BA2

Note 2

NF

A9

Note 2

NF

VSS

A3

VDD

BA0

BA1

A14

A11

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

CK

K

L

DK

REF#

WE#

A18

A15

VSS

DK#

CS#

A16

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

VDD

CK#

A13

A10

A19

DM

VSS

M

N

P

R

T

VDD

A12

DQ4

DQ5

DQ6

DQ7

DQ8

VEXT

V^SSQ

V^DDQ

V^SSQ

V^DDQ

V^SSQ

VSS

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VSS

V^SS

V^TT

VTT

U

V

VDD

V^DD

TDI

VREF

ZQ

VEXT

TDO

Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address

input signal. This may optionally be connected to V^SS, or left open.

2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal.

This may optionally be connected to V^SS, or left open.

3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may

optionally be connected to V^SS, or left open.

CK, CK#

CS#

: Input clock

TMS

TDI

TCK

TDO

VREF

VEXT

VDD

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Chip select

WE#

: WRITE command

: Refresh command

: Address inputs

REF#

A0–A21

A22

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

BA0–BA2

DQ0–DQ8

DK, DK#

DM

: Power Supply

V^DDQ

VSS

: DQ Power Supply

: Ground

VSSQ

V^TT

: DQ Ground

QK0, QK0#

QVLD

ZQ

: Power Supply

NF

: No function

: Output impedance matching

DNU

: Do not use

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Oct 01, 2012

Page 3 of 52

μPD48576209, μPD48576218, μPD48576236

# indicates active LOW signal.

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x18]

1

2

3

4

5

6

7

8

9

10

VEXT

DQ0

DQ1

QK0#

DQ2

DQ3

A2

11

12

TCK

V^DD

V^TT

A

B

C

D

E

F

V^REF

VDD

VTT

Note 1

(A22)

Note 1

VSS

VEXT

DQ4

DQ5

DQ6

DQ7

DQ8

A7

VSS

TMS

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

V^SSQ

V^DDQ

V^SSQ

V^DDQ

V^SSQ

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VDD

QK0

VSS

A20

QVLD

A0

Note 3

DNU

Note 3

DNU

(A21)

A5

A8

G

H

J

A6

A1

A4

BA2

A9

VSS

A3

Note 2

V^DD

VDD

BA0

BA1

A14

A11

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

Note 3

DNU

CK

NF

K

L

DK

REF#

WE#

A18

A15

VSS

DK#

CS#

A16

Note 3

DNU

Note 3

DNU

VDD

CK#

A13

A10

A19

DM

VSS

M

N

P

R

T

A17

VDD

A12

DQ14

DQ15

QK1#

DQ16

DQ17

VEXT

V^SSQ

V^DDQ

VSSQ

V^DDQ

V^SSQ

VSS

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VEXT

QK1

V^SS

V^TT

Note 3

DNU

Note 3

DNU

VTT

U

V

VDD

V^DD

TDI

VREF

ZQ

TDO

Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address

input signal. This may optionally be connected to V^SS, or left open.

2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal.

This may optionally be connected to V^SS, or left open.

3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may

optionally be connected to VSS, or left open.

CK, CK#

CS#

: Input clock

TMS

TDI

TCK

TDO

V^REF

V^EXT

VDD

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Chip select

WE#

: WRITE command

: Refresh command

: Address inputs

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

REF#

A0–A20

A21–A22

BA0–BA2

DQ0–DQ17

DK, DK#

DM

: Power Supply

VDDQ

V^SS

: DQ Power Supply

: Ground

VSSQ

VTT

: DQ Ground

QK0–QK1, QK0#–QK1#

QVLD

: Power Supply

NF

: No function

ZQ

: Output impedance

matching

DNU

: Do not use

# indicates active LOW signal.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 4 of 52

μPD48576209, μPD48576218, μPD48576236

144-pin TAPE FBGA (18.5 x 11)

(Top View) [Common I/O x36]

1

2

3

4

5

6

7

8

9

10

11

12

TCK

VDD

VTT

A

B

C

D

E

F

V^REF

VDD

VTT

VSS

VEXT

DQ9

DQ11

DQ13

DQ15

DQ17

A7

VSS

VEXT

DQ1

DQ3

QK0#

DQ5

DQ7

A2

TMS

DQ0

DQ2

QK0

DQ4

DQ6

A1

DQ8

DQ10

DQ12

DQ14

DQ16

A6

VSSQ

VDDQ

V^SSQ

V^DDQ

VSSQ

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VDD

Note

VSS

Note

(A20)

(A22)

Note

(A21)

A5

A8

QVLD

G

H

J

A0

A3

BA2

DK0

DK1

REF#

WE#

A18

A15

VSS

A9

VSS

A4

DK0#

DK1#

CS#

VDD

BA0

BA1

A14

CK

K

L

VDD

CK#

A13

A10

A19

DM

VSS

VTT

VSS

M

N

P

R

T

A16

A17

VDD

A12

A11

DQ24

DQ22

QK1

DQ20

DQ18

ZQ

DQ25

DQ23

QK1#

DQ21

DQ19

VEXT

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VSS

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

VSS

DQ35

DQ33

DQ31

DQ29

DQ27

VEXT

DQ34

DQ32

DQ30

DQ28

DQ26

TDO

VTT

U

V

VDD

TDI

VREF

Note Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input

signal. This may optionally be connected to V^SS, or left open.

CK, CK#

: Input clock

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

CS#

: Chip select

WE#

: WRITE command

: Refresh command

: Address inputs

TCK

TDO

V^REF

V^EXT

V^DD

REF#

A0–A19

A20–A22

: Reserved for the future

: Bank address input

: Data input/output

: Input data clock

: Input data Mask

: Output data clock

: Data Valid

BA0–BA2

: Power Supply

DQ0–DQ35

V^DDQ

V^SS

: DQ Power Supply

: Ground

DK0–DK1, DK0#–DK1#

DM

V^SSQ

V^TT

: DQ Ground

QK0–QK1, QK0#–QK1#

: Power Supply

QVLD

ZQ

: Output impedance matching

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 5 of 52

μPD48576209, μPD48576218, μPD48576236

Pin Description

(1/2)

Symbol

Type

Description

CK, CK#

Input

Clock inputs:

CK and CK# are differential clock inputs. This input clock pair registers address and control inputs

on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.

CS#

Input

Chip select

CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the

command is disabled, new commands are ignored, but internal operations continue.

WE#, REF#

A0–A21

WRITE command pin, Refresh command pin:

WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the

command to be executed.

Address inputs:

A0–A21 define the row and column addresses for READ and WRITE operations. During a MODE

REGISTER SET, the address inputs define the register settings. They are sampled at the rising

edge of CK.

In the x36 configuration, A20–A21 are reserved for address expansion; in the x18 configuration, A21

is reserved for address expansion. These expansion addresses can be treated as address inputs,

but they do not affect the operation of the device.

A22

Input

Reserved for future use:

These signals should be tied to VSS or leave open.

Bank address inputs;

BA0–BA2

DQx–DQxx

Select to which internal bank a command is being applied.

Data input/output:

Input

/Output

The DQ signals form the 9/18/36 bit data bus. During READ commands, the data is referenced to

both edges of QKx. During WRITE commands, the data is sampled at both edges of DKx.

x 9 device uses DQ0 to DQ8.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

Output data clocks:

QKx, QKx#

Output

QKx and QKx# are opposite polarity, output data clocks. They are always free running and edge-

aligned with data output from the μPD48576209/18/36. QKx# is ideally 180 degrees out of phase

with QKx.

For the x36 device, QK0 and QK0# are aligned with DQ0–DQ17. QK1 and QK1# are aligned with

DQ18–DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0–DQ8. QK1 and QK1# are

aligned with DQ9–DQ17. For the x9 device, QK0 and QK0# are aligned with DQ0–DQ8.

DKx, DKx#

Input

Input data clock;

DKx and DKx# are the differential input data clocks. All input data is referenced to both edges of DK.

DK# is ideally 180 degrees out of phase with DK.

For the x36 device, DQ0–DQ17 are referenced to DK0 and DK0#, and DQ18–DQ35 are referenced

to DK1 and DK1#. For the x9 and x18 devices, all DQs are referenced to DK and DK#.

DM

Input

Input data mask;

The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled

HIGH along with the WRITE input data. DM is sampled on both edges of DK (DK1 for the x36

configuration). The signal should be V^SSif not used.

QVLD

Output

Data valid;

The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#.

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Oct 01, 2012

Page 6 of 52

μPD48576209, μPD48576218, μPD48576236

(2/2)

Symbol

Type

Description

ZQ

Input

External impedance [25 Ω – 60 Ω];

This signal is used to tune the device outputs to the system data bus impedance. DQ output

/Output

impedance is set to 0.2 x RQ, where RQ is a resistor from this signal to V^SS. Connecting ZQ to VSS

invokes the minimum impedance mode. Connecting ZQ to V^DDQ invokes the maximum impedance

mode. Refer to Figure 2-5. Mode Register Bit Map to activate this function.

TMS , TDI

Input

JTAG function pins:

IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used in

the circuit

TCK

TDO

Input

JTAG function pin;

IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used in the circuit.

Output

JTAG function pin;

IEEE 1149.1 test output: JTAG output.

This ball may be left as no connect if JTAG function is not used.

Input reference voltage;

VREF

VEXT

VDD

Input

Nominally VDDQ/2. Provides a reference voltage for the input buffers.

Power supply;

Supply

2.5 V nominal. See Recommended DC Operating Conditions for range.

Power supply;

1.8 V nominal. See Recommended DC Operating Conditions for range.

DQ power supply;

VDDQ

Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity.

See Recommended DC Operating Conditions for range.

Ground

VSS

Supply

VSSQ

DQ ground;

Isolated on the device for improved noise immunity.

Power supply;

VTT

Supply

Isolated termination supply. Nominally, V^DDQ/2. See Recommended DC Operating Conditions for

range.

NF

No function;

These balls may be connected to VSS.

Do not use;

DNU

These balls may be connected to VSS.

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Oct 01, 2012

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μPD48576209, μPD48576218, μPD48576236

Block Diagram

A0-Axx , B0, B1, B2

Column Address

Row Address

Refresh

Counter

Buffer

Row Decoder

Memory Array

Bank 0

Memory Array

Bank 1

Memory Array

Bank 2

Memory Array

Bank 3

Row Decoder

Memory Array

Bank 4

Memory Array

Bank 5

Memory Array

Bank 6

Memory Array

Bank 7

Output Data Valid

Output Data Clock

QKx, QKx#

Input Buffers

Output Buffers

Control Logic and Timing Generator

QVLD

DQxx

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Oct 01, 2012

Page 8 of 52

μPD48576209, μPD48576218, μPD48576236

Contents

1. Electrical Characteristics....................................................................................................10

2. Operation...............................................................................................................................17

2.1 Command Operation.................................................................................................17

2.2 Description of Commands........................................................................................17

2.3 Initialization................................................................................................................18

2.4 Power-On Sequence..................................................................................................19

2.5 Programmable Impedance Output Buffer ...............................................................19

2.6 PLL Reset...................................................................................................................19

2.7 Clock Input.................................................................................................................19

2.8 Mode Register Set Command (MRS) .......................................................................21

2.9 Read & Write configuration (Non Multiplexed Address Mode)..............................22

2.10 Write Operation (WRITE)...........................................................................................23

2.11 Read Operation (READ) ............................................................................................26

2.12 Refresh Operation: AUTO REFRESH Command (AREF) .......................................30

2.13 On-Die Termination ...................................................................................................31

2.14 Operation with Multiplexed Address .......................................................................34

2.15 Address Mapping in Multiplexed Mode ...................................................................36

2.16 Read & Write configuration in Multiplexed Address Mode....................................37

2.17 Refresh Command in Multiplexed Address Mode ..................................................37

2.18 Input Slew Rate Derating ..........................................................................................39

3. JTAG Specification...............................................................................................................43

4. Package Dimension..............................................................................................................50

5. Recommended Soldering Condition...................................................................................50

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μPD48576209, μPD48576218, μPD48576236

1. Electrical Characteristics

Absolute Maximum Ratings

Parameter

Supply voltage

Symbol

V_EXT

Conditions

Rating

Unit

V

–0.3 to +2.8

–0.3 to +2.1

Supply voltage

V_DD

V

Output supply voltage,

Input voltage, Input / Output voltage

Input / Output voltage

Junction temperature

Storage temperature

V_DDQ

V

V_IH/ V_IL

T_jMAX.

T_stg

–0.3 to +2.1

110

V

°C

–55 to +125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions

0°C ≤ T^C≤ 95°C; 1.7 V ≤ VDD ≤ 1.9 V, unless otherwise noted.

Parameter

Symbol Conditions

MIN.

2.38

1.7

TYP.

2.5

MAX.

2.63

1.9

Unit

V

Note

Supply voltage

VEXT

VDD

1

Supply voltage

1.8

V

Output supply voltage

Reference Voltage

Termination voltage

Input HIGH voltage

Input LOW voltage

VDDQ

VREF

1.4

VDD

V

1, 2, 3

1, 4, 5

1, 6

1

0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ

V

VTT

0.95 x VREF

VREF + 0.1

VREF

1.05 x VREF

V

VIH (DC)

VIL (DC)

V

VREF – 0.1

V

1

Notes 1. All voltage referenced to V^SS(GND).

2. During normal operation, V^DDQ must not exceed VDD.

3. V^DDQ can be set to a nominal 1.5 V 0.1 V or 1.8 V 0.1 V supply.

4. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track

variations in V^DDQ.

5. Peak-to-peak AC noise on V^REFmust not exceed 2% VREF(DC).

6. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.

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Page 10 of 52

μPD48576209, μPD48576218, μPD48576236

DC Characteristics

0°C ≤ T^C≤ 95°C; 1.7 V ≤ VDD ≤ 1.9 V, unless otherwise noted

Parameter

Input leakage current

Output leakage current

Reference voltage current

Output high current

Symbol Test condition

MIN.

–5

MAX.

+5

Unit Note

ILI

ILO

μA

1,2

3,4

–5

+5

IREF

–5

+5

μA

IOH

IOL

VOH = VDDQ/2

VOL = VDDQ/2

(VDDQ/2) / (1.15 x RQ/5) (VDDQ/2) / (0.85 x RQ/5)

mA

Output low current

Notes 1. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) for values of 125 Ω ≤ RQ ≤ 300 Ω.

2. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) for values of 125 Ω ≤ RQ ≤ 300 Ω.

3. I^OHand IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows

into the device.

4. If MRS bit A8 is 0, use RQ = 250 Ω in the equation in lieu of presence of an external impedance matched

resistor.

Capacitance (TA = 25 °C, f = 1MHz)

Parameter

Symbol

Test conditions

MIN.

1.5

MAX.

2.5

Unit

pF

Address / Control Input capacitance

I/O, Output, Other capacitance

(DQ, DM, QK, QVLD)

CIN

VIN = 0 V

CI/O

VI/O = 0 V

3.5

5.0

pF

Clock Input capacitance

JTAG pins

Cclk

CJ

Vclk = 0 V

VJ = 0 V

2.0

3.0

5.0

pF

Remark These parameters are periodically sampled and not 100% tested.

Capacitance is not tested on ZQ pin.

Recommended AC Operating Conditions

0°C ≤ TC ≤ 95°C; 1.7 V ≤ V_DD≤ 1.9 V, unless otherwise noted

Parameter

Symbol Conditions

MIN.

MAX.

Unit Note

Input HIGH voltage

Input LOW voltage

VIH (AC)

VIL (AC)

VREF + 0.2

V

1

VREF – 0.2

Note 1. Overshoot: VIH (AC) ≤ VDDQ + 0.7 V for t ≤ tCK/2

Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ tCK/2

Control input signals may not have pulse widths less than t^CKH(MIN.) or operate at cycle rates less than tCK

(MIN.).

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 11 of 52

μPD48576209, μPD48576218, μPD48576236

DC Characteristics

I_DD/ I_SBOperating Conditions

Parameter

Symbol

Test condition

MAX.

Unit

–E18 –E24 –E25 –E33

x9/x18 55

55

Standby current

ISB1

tCK = Idle

VDD

mA

All banks idle, no inputs toggling

x36

55

5

VEXT

VDD

5

x9/x18

x36

Active standby

current

ISB2

IDD1

CS# = HIGH, No commands, half bank / address /

data change once every four clock cycles

250

5

215

5

215

5

190

5

mA

VEXT

VDD

x9/x18

x36

Operating current

BL=2, sequential bank access, bank transitions

once every tRC, half address transitions once

every tRC, read followed by write sequence,

continuous data during WRITE commands.

BL=4, sequential bank access, bank transitions

once every tRC, half address transitions once

every tRC, read followed by write sequence,

continuous data during WRITE commands.

BL=8, sequential bank access, bank transitions

once every tRC, half address transitions once

every tRC, read followed by write sequence,

continuous data during WRITE commands.

Eight bank cyclic refresh, continuous

390

407

10

331

346

10

321

336

10

291

306

10

VEXT

VDD

VEXT

VDD

VEXT

VDD

x9/x18

x36

IDD2

422

445

10

367

387

10

357

377

10

336

353

10

mA

x9/x18

x36

IDD3

439

488

15

381

419

15

371

409

15

350

388

15

x9/x18

x36

Burst refresh

current

IREF1

IREF2

IDD2W

IDD4W

IDD8W

IDD2R

IDD4R

IDD8R

692

670

45

540

545

30

540

545

30

419

430

25

mA

address/data, command bus remains in refresh

for all banks

VEXT

VDD

x9/x18

x36

Disturbed

Single bank refresh, sequential bank access,

half address transitions once every tRC,

continuous data

286

295

10

265

10

260

10

194

215

10

refresh current

VEXT

Operating burst

write current

BL=2, cyclic bank access, half of address bits

change every clock cycle, continuous data,

measurement is taken during continuous WRITE

BL=4, cyclic bank access, half of address bits

change every two clocks, continuous data,

measurement is taken during continuous WRITE

BL=8, cyclic bank access, half of address bits

change every four clocks, continuous data,

measurement is taken during continuous WRITE

BL=2, cyclic bank access, half of address bits

change every clock cycle, measurement is taken

during continuous READ

VDD X9/x18 1078

X36 1105

872

891

35

872

891

35

716

731

30

VEXT

VDD

40

784

832

25

x9/x18

x36

Operating burst

write current

645

681

20

645

681

20

538

565

20

VEXT

VDD

x9/x18

x36

Operating burst

write current

625

706

25

520

579

20

520

579

20

442

487

20

VEXT

VDD

x9/x18

x36

Operating burst

read current

949

999

40

735

779

35

735

779

35

566

601

30

VEXT

VDD

x9/x18

x36

Operating burst

read current

BL=4, cyclic bank access, half of address bits

change every two clocks, measurement is taken

during continuous READ

659

685

25

503

535

20

503

535

20

400

424

20

VEXT

VDD

x9/x18

x36

Operating burst

read current

BL=8, cyclic bank access, half of address bits

497

567

25

389

441

20

389

441

20

308

349

20

change every four clocks, measurement is taken

during continuous READ

VEXT

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 12 of 52

μPD48576209, μPD48576218, μPD48576236

Remarks1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ 95°C; 1.7 V ≤ VDD ≤ 1.9 V,

2.38 V ≤ V^EXT≤ 2.63 V, 1.4 V ≤ VDDQ ≤ VDD, VREF = VDDQ/2

2. t^CK= tDK = MIN., tRC = MIN.

3. Input slew rate is specified in Recommended DC Operating Conditions and Recommended AC

Operating Conditions.

4. I^DDparameters are specified with ODT disabled.

5. Continuous data is defined as half the DQ signals changing between HIGH and LOW every half clock

cycles (twice per clock).

6. Continuous address is defined as half the address signals between HIGH and LOW every clock cycles

(once per clock).

7. Sequential bank access is defined as the bank address incrementing by one ever t^RC.

8. Cyclic bank access is defined as the bank address incrementing by one for each command access. For

BL=4 this is every other clock.

9. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions

more than per clock cycle.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 13 of 52

μPD48576209, μPD48576218, μPD48576236

AC Characteristics

AC Test Conditions

Input waveform

VDDQ

VIH(AC) MIN.

VIL(AC) MAX.

V

SS

Rise Time:

2 V/ns

Fall Time:

2 V/ns

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

VTT

50Ω

Test point

10pF

DQ

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 14 of 52

μPD48576209, μPD48576218, μPD48576236

AC Characteristics <Read and Write Cycle>

Parameter

Symbol

–E18

–E24

–E25

–E33

Unit Note

(533 MHz)

(400 MHz)

(300 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Clock cycle time (CK,CK#,DK,DK#)

Clock frequency (CK,CK#,DK,DK#)

Random Cycle time

tCK, tDK

tRC

1.875

175

5.7

2.5

175

15

5.7

2.5

175

20

5.7

3.3

175

20

5.7

ns

MHz

ns

533

400

300

15

Clock Jitter: period

tJIT PER

tJIT CC

–100

100

200

0.55

0.3

–150

150

300

0.55

0.5

–150

150

300

0.55

0.5

–200

200

400

ps

1, 2

Clock Jitter: cycle-to-cycle

Clock HIGH time (CK,CK#,DK,DK#)

Clock LOW time (CK,CK#,DK,DK#)

Clock to input data clock

Mode register set cycle time

to any command

tCKH, tDKH

tCKL, tDKL

tCKDK

0.45

–0.3

6

0.45

–0.45

6

0.45

–0.45

6

0.45

–0.45

6

0.55 Cycle

1.0

ns

tMRSC

Cycle

PLL Lock time

tCK Lock

15

30

15

30

15

30

15

30

μs

Clock static to PLL reset

Output Times

tCK Reset

ns

Output data clock HIGH time

Output data clock LOW time

QK edge to clock edge skew

QK edge to output data edge

QK edge to any output data

QK edge to QVLD

tQKH

tQKL

0.9

1.1

0.9

1.1

0.25

0.2

0.3

0.9

1.1

0.9

1.1

tCKH

tCKL

ns

tCKQK

–0.2

0.2

–0.25

–0.2

–0.3

–0.25

–0.2

–0.3

0.25

0.2

0.3

–0.3

–0.25

–0.35

0.3

tQKQ0, tQKQ1 –0.12

0.12

0.22

0.25

0.35

ns

3, 5

4, 5

tQKQ

–0.22

ns

tQKVLD

ns

Setup Times

Address/command and input

Data-in and data mask to DK

Hold Times

tAS/tCS

tDS

0.3

0.4

0.5

0.3

ns

0.17

0.25

Address/command and input

Data-in and data mask to DK

tAH/tCH

tDH

0.3

0.4

0.5

0.3

ns

0.17

0.25

Notes 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

2. Frequency drift is not allowed.

3. tQKQ0 is referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18.

t^QKQ1is referenced to DQ18–DQ35 in x36 and DQ9–DQ17 in x18.

4. tQKQ takes into account the skew between any QKx and any DQ.

5. tQKQ, tQKQX are guaranteed by design.

Remark All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing

point with V^REFof the command, address, and data signals.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 15 of 52

μPD48576209, μPD48576218, μPD48576236

Figure 1-1. Clock / Input Data Clock Command / Address Timings

t

CK

t

CKH

tCKL

CK#

CK

COMMAND,

ADDRESS

VALID

t

CKDK

t

CKDK

tAS

tAH

DKx#

DKx

t

DK

t

DKH

tDKL

Don’t care

Temperature and Thermal Impedance

Temperature Limits

Parameter

Symbol

MIN.

MAX.

+110

+100

+95

Unit

°C

Note

Reliability junction temperature

Operating junction temperature

Operating case temperature

TJ

TC

0

1

2

3

°C

Notes 1. Temperatures greater than 110°C may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at or above this is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability of the part.

2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow.

3. MAX operating case temperature; T^Cis measured in the center of the package. Device functionality is not guaranteed if the

device exceeds maximum T^Cduring operation.

Thermal Impedance

Substrate

Ball

θja (°C/W)

θjb

(°C/W)

10.29

10.13

θjc

(°C/W)

1.22

Air Flow = 0 m/s Air Flow = 1 m/s Air Flow = 2 m/s

4 - Layer

Lead

21.49

21.32

17.33

17.18

16.15

16.01

Lead free

1.22

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 16 of 52

μPD48576209, μPD48576218, μPD48576236

2. Operation

2.1 Command Operation

According to the functional signal description, the following command sequences are possible. All input states or sequences not

shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK.

Table 2-1. Address Widths at Different Burst Lengths

Burst Length

Configuration

x18

x9

x36

BL=2

BL=4

BL=8

A0–A21

A0–A20

A0–A19

A0–A20

A0–A19

A0–A18

A0–A17

A0–A19

A0–A18

Table 2-2. Command Table

Operation

Code

CS#

WE#

REF#

A0–An^Note1

BA0–BA2 Note

Device DESELECT / No Operation DESEL / NOP

H

L

X

L

X

L

X

MRS: Mode Register Set

READ

MRS

READ

WRITE

AREF

OPCODE

X

2

3

H

L

H

L

A

X

BA

WRITE

AUTO REFRESH

H

Notes 1. n = 21.

2. Only A0–A17 are used for the MRS command.

3. See Table 2-1.

Remark X = “Don’t Care”, H = logic HIGH, L = logic LOW, A = valid address, BA = valid bank address

2.2 Description of Commands

DESEL / NOP ^Note1

The NOP command is used to perform a no operation to the μPD48576209/18/36, which essentially deselects the chip. Use the

NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are

not affected. Output values depend on command history.

MRS

The mode register is set via the address inputs A0–A17. See Figure 2-5. Mode Register Bit Map for further information. The

MRS command can only be issued when all banks are idle and no bursts are in progress.

READ

The READ command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs selects the bank, and the

address provided on inputs A0–A21 selects the data location within the bank.

WRITE

The WRITE command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs selects the bank, and

the address provided on inputs A0–A21 selects the data location within the bank. Input data appearing on the DQ is written to the

memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the

corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored

(i.e., this part of the data word will not be written).

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 17 of 52

μPD48576209, μPD48576218, μPD48576236

AREF

The AREF is used during normal operation of the μPD48576209/18/36 to refresh the memory content of a bank. The

command is non-persistent, so it must be issued each time a refresh is required. The value on the BA0–BA2 inputs

selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a

“Don’t Care” during the AREF command. The μPD48576209/18/36 requires 64K cycles at an average periodic interval

Note2

of 0.244μs

(MAX.). To improve efficiency, eight AREF commands (one for each bank) can be posted to

μPD48576209/18/36 at periodic intervals of 1.95 μs ^Note3

.

Within a period of 32 ms, the entire memory must be refreshed. The delay between the AREF command and a

subsequent command to same bank must be at least t^RCas continuous refresh. Other refresh strategies, such as burst

refresh, are also possible.

Notes 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.

2. Actual refresh is 32 ms / 16k / 8 = 0.244 μs.

3. Actual refresh is 32 ms / 16k = 1.95 μs.

2.3 Initialization

The μPD48576209/18/36 must be powered up and initialized in a predefined manner. Operational procedures other

than those specified may result in undefined operations or permanent damage to the device. The following sequence is

used for Power-Up:

1. Apply power (V^EXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD

and VEXT before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF and VTT. Although

there is no timing relation between V^EXTand VDD, the chip starts the power-up sequence only after both voltages

are at their nominal levels. V^DDQ supply must not be applied before VDD supply. CK/CK# must meet VID(DC)

prior to being applied. Maintain all remaining balls in NOP conditions.

Note No rule of apply power sequence is the design target.

2. Maintain stable conditions for 200 μs (MIN.).

3. Issue at least three or more consecutive MRS commands: two dummies or more plus one valid MRS. It is

recommended that all address pins are held LOW during the dummy MRS commands.

4. t^MRSCafter valid MRS, an AUTO REFRESH command to all 8 banks must be issued and wait for 15 μs with

CK/CK# toggling in order to lock the PLL prior to normal operation.

5. After t^RC, the chip is ready for normal operation.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 18 of 52

μPD48576209, μPD48576218, μPD48576236

2.4 Power-On Sequence

Figure 2-1. Power-Up Sequence

VEXT

V

DD

V

DDQ

V

REF

VTT

CK#

CK

MRS

NOP

RF0

RF1

RF7

AC

COMMAND

ADDRESS

NOP

Note 2

Note 1, 2

A

200μs MIN.

tMRSC

tRC

Refresh all banks

15μs

Don't care

Notes 1. Recommended all address pins held LOW during dummy MRS commands.

2. A10-A17 must be LOW.

Remark MRS : MRS command

RFp : REFRESH bank p

AC : Any command

2.5 Programmable Impedance Output Buffer

The μPD48576209/18/36 is equipped with programmable impedance output buffers. This allows a user to match the

driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the

ZQ ball and V^SS. The value of the resistor must be five times the desired impedance. For example, a 300 Ω resistor is

required for an output impedance of 60 Ω. To ensure that output impedance is one fifth the value of RQ (within 15

percent), the range of RQ is 125 Ω to 300 Ω. Output impedance updates may be required because, over time, variations

may occur in supply voltage and temperature. The device samples the value of RQ. An impedance update is transparent

to the system and does not affect device operation. All data sheet timing and current specifications are met during an

update.

2.6 PLL Reset

The μPD48576209/18/36 utilizes internal Phase-locked loops for maximum output, data valid windows. It can be

placed into a stopped-clock state to minimize power with a modest restart time of 15 μs. The clock (CK/CK#) must be

toggled for 15 μs in order to stabilize PLL circuits for next READ operation.

2.7 Clock Input

Table 2-3. Clock Input Operation Conditions

Parameter

Symbol

Conditions

CK and CK#

MIN.

-0.3

MAX.

Unit Note

Clock Input Voltage Level

VIN (DC)

VID (DC)

VID (AC)

VIX (AC)

VDDQ + 0.3

VDDQ + 0.6

VDDQ/2 + 0.15

V

Clock Input Differential Voltage Level

Clock Input Crossing Point Voltage Level

0.2

V

8

9

0.4

VDDQ/2 - 0.15

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 19 of 52

μPD48576209, μPD48576218, μPD48576236

Figure 2-2. Clock Input

Maximum Clock Level

VIN(DC) MAX.

CK#

V

IX(AC) MAX.

Note 10

V

DDQ/2 + 0.15

DDQ/2

DDQ/2 - 0.15

Note11

ID(DC)

Note12

ID(AC)

V

IX(AC) MIN.

CK

IN(DC) MIN.

Minimum Clock Level

V

Notes 1. DKx and DKx# have the same requirements as CK and CK#.

2. All voltages referenced to VSS.

3. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal

reference/supply voltage levels; but the related specifications and device operations are tested for the full

voltage range specified.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing

is still referenced to V^REF(or the crossing point for CK/CK#), and parameters specifications are tested for the

specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to

test the device is 2V/ns in the range between V^IL(AC)and VIH(AC).

5. The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will

effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as

the signal does not ring back above[below] the DC input LOW[HIGH] level).

6. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK#

cross. The input reference level for signal other than CK/CK# is V^REF.

7. CK and CK# input slew rate must be >= 2V/ns (>=4V/ns if measured differentially).

8. VID is the magnitude of the difference between the input level on CK and input level on CK#.

9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC

level of the same.

10.CK and CK# must cross within the region.

11.CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2.

12.Minimum peak-to-peak swing.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 20 of 52

μPD48576209, μPD48576218, μPD48576236

2.8 Mode Register Set Command (MRS)

The mode register stores the data for controlling the operating modes of the memory. It programs the

μPD48576209/18/36 configuration, burst length, and I/O options. During a MRS command, the address inputs A0–A17

are sampled and stored in the mode register. t^MRSCmust be met before any command can be issued to the

μPD48576209/18/36. The mode register may be set at any time during device operation. However, any pending

operations are not guaranteed to successfully complete, and all memory cell data are not guaranteed.

Since MRS is used for internal test mode entry, bits A10–A17 must be set to all “0” at the MRS setting.

Figure 2-3. Mode Register Set Timing

t

MRSC

CK#

CK

MRS

NOP

AC

COMMAND

QVLD

QKx

QKx#

Don’t care

Remark MRS: MRS command

AC : any command

Figure 2-4. Mode Register Set

CK#

CK

CS#

WE#

REF#

ADDRESS

COD

BANK

ADDRESS

Don’t care

Remark COD: code to be loaded into the register.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 21 of 52

μPD48576209, μPD48576218, μPD48576236

Figure 2-5. Mode Register Bit Map

A17-A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Note 1

Reserved

Impedance

Matching

On-Die

Termination

Address

Mux

PLL Reset

Unused

Burst Length

Configuration

On-Die

Configuration

A2 A1 A0

Termination

PLL Reset

Burst Length

A4 A3

A9

Termination

A7

BL

PLL Reset

Configuration

0

1

Disabled (default)

Enabled

0

1

0

1

0

1

0

1

2 (default)

4

PLL reset (default)

PLL enabled

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 ^{Note 2}(default)

1 ^{Note 2}

8 ^{Note 2}

2

3

Impedance

Matching

Not valid

Address Mux

Note 2

4

A8

Resistor

A5 Address Mux

5

Note 3

Internal 50 Ω

Reserved

Nonmultiplexed

(default)

0

1

(default)

0

Note 4

External

1

Address multiplexed

Notes 1. Bits A10–A17 must be set to all ‘0’. A18-An are “Don’t Care”.

2. BL=8 is not available for configuration 1 and 4.

3. ±30% temperature variation.

4. Within 15%.

2.9 Read & Write configuration (Non Multiplexed Address Mode)

Table 2-4 shows, for different operating frequencies, the different μPD48576209/18/36 configurations that can be

programmed into the mode register. The READ and WRITE latency (t^RLand tWL) values along with the row cycle times

(t^RC) are shown in clock cycles as well as in nanoseconds.

Table 2-4. Configuration Table

Parameter

Configuration

3

Unit

Note2

Note2, 3

5

2

1

4

tRC

4

5

6

8

3

4

5

tCK

tRL

tWL

6

7

8

9

5

6

tCK

Valid frequency range

266-175

400-175

533-175

200-175

333-175

MHz

Notes 1. Apply to the entire table. t^RC< 20 ns in any configuration only available with –E24 and –E18 speed grades.

2. BL= 8 is not available.

3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank.

In this instance the minimum t^RCis 4 cycles.

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μPD48576209, μPD48576218, μPD48576236

2.10 Write Operation (WRITE)

Write accesses are initiated with a WRITE command, as shown in Figure 2-6. Row and bank addresses are provided

together with the WRITE command. During WRITE commands, data will be registered at both edges of DK according

to the programmed burst length (BL). A WRITE latency (WL) one cycle longer than the programmed READ latency

(RL + 1) is present, with the first valid data registered at the first rising DK edge WL cycles after the WRITE command.

Any WRITE burst may be followed by a subsequent READ command. Figure 2-10. WRITE Followed By READ: BL=2,

RL=4, WL=5, Configuration 1 and Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1

illustrate the timing requirements for a WRITE followed by a READ for bursts of two and four, respectively.

Setup and hold times for incoming input data relative to the DK edges are specified as t^DSand tDH. The input data is

masked if the corresponding DM signal is HIGH. The setup and hold times for data mask are also t^DSand tDH.

Figure 2-6. WRITE Command

CK#

CK

CS#

WE#

REF#

ADDRESS

A

BANK

ADDRESS

BA

Don’t care

Remark A : Address

BA: Bank address

Figure 2-7. Basic WRITE Burst / DM Timing

CK#

CK

t

CKDK

DKx#

DKx

Write

Latency

tDS

tDH

tDS

tDH

DQ

DM

D0

D1

D2

D3

Data

masked

Data

masked

tDS

tDH

Don't care

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μPD48576209, μPD48576218, μPD48576236

Figure 2-8. WRITE Burst Basic Sequence: BL=2, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

WR

A

BA0

BA1

BA2

BA3

BA0

BA4

BA5

BA6

BA7

WL = 5

DK#

DK

DQ

D0a D0b D1a D1b D2a D2b D3a D3

Don’t care

Figure 2-9. WRITE Burst Basic Sequence: BL=4, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

WR

NOP

WR

NOP

WR

NOP

WR

NOP

WR

A

BA0

BA1

BA0

BA3

BA0

WL = 5

DK#

DK

DQ

D0a D0b D0c D0d D1a D1b D1c D1

Don’t care

Remarks 1.

WR

A/Bap

WL

: WRITE command

: Address A of bank p

: WRITE latency

Dpq

: Data q to bank p

2. Any free bank may be used in any given command. The sequence shown is only one example of

a bank sequence.

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μPD48576209, μPD48576218, μPD48576236

Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

ADDRESS

WR

NOP

RD

NOP

RL = 4

NOP

A

BA0

BA1

BA2

WL = 5

DKx#

DKx

DQ

D0a D0b

Q1a Q1b Q2a Q2b

QVLD

QKx

QKx#

Don’t care

Undefined

Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

ADDRESS

WR

NOP

RD

NOP

RD

NOP

A

BA0

BA1

BA2

RL = 4

WL = 5

DKx#

DKx

DQ

D0a D0b D0c D0d

Q1a Q1b Q1c Q1d Q2a

QVLD

QKx

QKx#

Don’t care

Undefined

Remark WR

: WRITE command

: READ command

RD

A/BAp : Address A of bank p

WL

RL

: WRITE latency

: READ latency

Dpq

Qpq

: Data q to bank p

: Data q from bank p

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μPD48576209, μPD48576218, μPD48576236

2.11 Read Operation (READ)

Read accesses are initiated with a READ command, as shown in Figure 2-12. Row and bank addresses are provided

with the READ command.

During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable

READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next

half clock cycle.

The skew between QK and the crossing point of CK is specified as t^CKQK. tQKQ0 is the skew between QK0 and the last

valid data edge considered the data generated at the DQ0–DQ17 in x36 and DQ0–DQ8 in x18 data signals. t^QKQ1is the

skew between QK1 and the last valid data edge considered the data generated at the DQ18–DQ35 in x36 and DQ9–

DQ17 in x18 data signals. t^QKQxis derived at each QKx clock edge and is not cumulative over time.

After completion of a burst, assuming no other commands have been initiated, DQ will go High-Z. Back-to-back READ

commands are possible, producing a continuous flow of output data.

Minimum READ data valid window can be expressed as MIN.(t^QKH, tQKL) – 2 x MAX.(tQKQx)

Any READ burst may be followed by a subsequent WRITE command. Figure 2-16. READ followed by WRITE, BL=2,

RL=4, WL=5, Configuration 1 and Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1

illustrate the timing requirements for a READ followed by a WRITE.

Figure 2-12. READ Command

CK#

CK

CS#

WE#

REF#

A

ADDRESS

BANK

ADDRESS

BA

Don’t care

Remark A : Address

BA: Bank address

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μPD48576209, μPD48576218, μPD48576236

Figure 2-13. Basic READ Burst Timing

tCKH

tCKL

tCK

CK#

CK

tQKL

tQKH

tCKQK

QKx

QKx#

tQKVLD

QVLD

DQ

Q0

Q1

Q2

Q3

tQKQ

Note 1

Undefined

Note 1. Minimum READ data valid window can be expressed as MIN.(t^QKH, tQKL) – 2 x MAX.(tQKQx)

t^CKHand tCKL are recommended to have 50% / 50% duty.

Remarks

1. t^QKQ0is referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18.

t^QKQ1is referenced to DQ18–DQ35 in x36 and DQ9–DQ17 in x18.

2. t^QKQtakes into account the skew between any QKx and any DQ.

3. t^CKQKis specified as CK rising edge to QK rising edge.

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Figure 2-14. READ Burst Basic Sequence: BL=2, RL=4, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

RD

A

BA0

BA1

BA2

BA3

BA0

BA7

BA6

BA5

BA4

RL = 4

QKx

QKx#

QVLD

DQ

Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a

Don’t care

Undefined

Figure 2-15. READ Burst Basic Sequence: BL=4, RL=4, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

RD

NOP

RD

NOP

RD

NOP

RD

NOP

RD

A

BA0

BA1

BA0

BA1

BA3

RL = 4

QKx

QKx#

QVLD

DQ

Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a

Don’t care

Undefined

Remark RD

: READ command

A/BAp : Address A of bank p

RL

: READ latency

Qpq

: Data q from bank p

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μPD48576209, μPD48576218, μPD48576236

Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

ADDRESS

RD

WR

NOP

A

BA0

BA1

BA2

RL = 4

WL = 5

DKx#

DKx

D2a D2b

DQ

Q0a Q0b

D1a D1b

QVLD

QKx

QKx#

Don’t care

Undefined

Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1

0

1

2

3

4

5

6

7

CK#

CK

RD

NOP

WR

NOP

COMMAND

ADDRESS

A

BA0

BA1

WL = 5

RL = 4

DKx#

DKx

DQ

Q0a Q0b Q0c Q0d

D1a D1b

QVLD

QKx

QKx#

Don’t care

Undefined

Remark WR

: WRITE command

: READ command

RD

A/BAp : Address A of bank p

WL

RL

: WRITE latency

: READ latency

Dpq

Qpq

: Data q to bank p

: Data q from bank p

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μPD48576209, μPD48576218, μPD48576236

2.12 Refresh Operation: AUTO REFRESH Command (AREF)

AREF is used to perform a REFRESH cycle on one row in a specific bank. The row addresses are generated by an

internal refresh counter; external address balls are “Don’t Care.” The delay between the AREF command and a

subsequent command to the same bank must be at least t^RC.

Within a period of 32 ms (t^REF), the entire memory must be refreshed. Figure 2-19 illustrates an example of a

continuous refresh sequence. Other refresh strategies, such as burst refresh, are also possible.

Figure 2-18. AUTO REFRESH Command

CK#

CK

CS#

WE#

REF#

ADDRESS

BANK

BA

ADDRESS

Don’t care

Remark BA: Bank address

Figure 2-19. AUTO REFRESH Cycle

CK#

CK

ARFx

ACy

ACx

ACy

COMMAND

tRC

Don’t care

Remarks 1. ACx : Any command on bank x

ARFx : Auto refresh bank x

ACy : Any command on different bank.

2. t^RCis configuration-dependent. Refer to Table 2-4. Configuration Table.

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μPD48576209, μPD48576218, μPD48576236

2.13 On-Die Termination

On-die termination (ODT) is enabled by setting A9 to “1” during an MRS command. With ODT on, all the DQs and

DM are terminated to V^TTwith a resistance RTT. The command, address, and clock signals are not terminated. Figure 2-

20 below shows the equivalent circuit of a DQ receiver with ODT. ODTs are dynamically switched off during READ

commands and are designed to be off prior to the μPD48576209/18/36 driving the bus. Similarly, ODTs are designed to

switch on after the μPD48576209/18/36 has issued the last piece of data.

Table 2-5. On-Die Termination DC Parameters

Description

Termination voltage

On-Die termination

Symbol

VTT

MIN.

0.95 x VREF

125

MAX.

1.05 x VREF

185

Units

V

Note

1, 2

3

RTT

Ω

Notes 1. All voltages referenced to V^SS(GND).

2. V^TTis expected to be set equal to VREF and must track variations in the DC level of VREF.

3. The R^TTvalue is measured at 95°C TC.

Figure 2-20. On- Die Termination-Equivalent Circuit

V

TT

sw

RTT

DQ

Receiver

Figure 2-21. READ Burst with ODT: BL=2, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

RD

NOP

A

BA0

BA1

BA2

RL = 4

QKx

QKx#

QVLD

DQ

Q0a Q0b Q1a Q1b Q2a Q2b

ODT

ODT ON

ODT OFF

Don’t care

Undefined

Remark

RD

A/BAp : Address A of bank p

RL : READ latency

Qpq : Data q from bank p

: READ command

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μPD48576209, μPD48576218, μPD48576236

Figure 2-22. READ NOP READ with ODT: BL=2, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

RD

NOP

RD

NOP

A

BA0

BA2

RL = 4

QKx

QKx#

QVLD

DQ

Q0a Q0b

Q2a Q2b

ODT

ODT ON

ODT OFF

ODT ON

Don’t care

Undefined

Figure 2-23. READ NOP NOP READ with ODT: BL=2, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

RD

NOP

RD

NOP

A

ADDRESS

BA0

BA2

RL = 4

QKx

QKx#

QVLD

DQ

Q0a Q0b

Q2a Q2b

ODT

ODT ON

ODT OFF

ODT ON

Don’t care

Undefined

Remark RD

A/BAp: Address A of bank p

RL : READ latency

Qpq : Data q from bank p

: READ command

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μPD48576209, μPD48576218, μPD48576236

Figure 2-24. READ followed by WRITE with ODT: BL=2, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

ADDRESS

RD

WR

NOP

A

BA0

BA1

BA2

RL = 4

WL = 5

DKx#

DKx

Q0a Q0b

D2a D2b

DQ

D1a D1b

QKx

QKx#

ODT

ODT ON

ODT OFF

Don’t care

Undefined

Figure 2-25. WRITE followed by READ with ODT: BL=2, Configuration 1

0

1

2

3

4

5

6

7

8

9

CK#

CK

COMMAND

ADDRESS

WR

NOP

RD

NOP

RL= 4

NOP

A

BA0

BA1

BA2

WL= 5

DKx#

DKx

DQ

D0a D0b

Q1a Q1b Q2a Q2b

QKx

QKx#

ODT

ODT ON

ODT OFF

Don’t care

Undefined

Remark

RD

: READ command

: WRITE command

WR

A/BAp : Address A of bank p

RL

: READ latency

WL

Qpq

Dpq

: WRITE latency

: Data q from bank p

: Data q to bank p

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μPD48576209, μPD48576218, μPD48576236

2.14 Operation with Multiplexed Address

In multiplexed address mode, the address can be provided to the μPD48576209/18/36 in two parts that are latched

into the memory with two consecutive rising clock edges. This provides the advantage that a maximum of 11 address

balls are required to control the μPD48576209/18/36, reducing the number of balls on the controller side. The data bus

efficiency in continuous burst mode is not affected for BL=4 and BL=8 since at least two clocks are required to read the

data out of the memory. The bank addresses are delivered to the μPD48576209/18/36 at the same time as the WRITE

command and the first address part, Ax.

This option is available by setting bit A5 to “1” in the mode register. Once this bit is set, the READ, WRITE, and

MRS commands follow the format described in Figure 2-26. See Figure 2-28. Power-Up Sequence in Multiplexed

Address Mode for the power-up sequence.

Figure 2-26. Command Description in Multiplexed

READ

WRITE

MRS

CK#

CK

CS#

WE#

REF#

Ax

Ay

Ax

Ay

Ax

Ay

ADDRESS

BANK

ADDRESS

BA

Don’t care

Remarks 1. Ax, Ay : Address

BA : Bank Address

2. The minimum setup and hold times of the two address parts are defined t^ASand tAH.

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μPD48576209, μPD48576218, μPD48576236

Figure 2-27. Mode Register Set Command in Multiplexed Address Mode

Ax

Ay

A17 ••••• A10

A9

A8

A5

A4

A3

A0

A9

A8

A4

A3

Note 1

Impedance

Matching

Address

Mux

On-Die

Termination

Burst Length

Configuration

Unused

PLL Reset

Reserved

On-Die

Termination

Configuration

PLL Reset

Burst Length

A4x A3x

A9x

Termination

A9y

BL

PLL Reset

A4y A3y A0x

Configuration

1

^{Note 2}(default)

0

1

Disabled (default)

Enabled

0

1

0

1

0

1

2 (default)

4

0

1

PLL reset (default)

PLL enabled

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 ^{Note 2}

8 ^{Note 2}

2

Not valid

Impedance

Matching

3

4 ^{Note 2}

A8x

Resistor

A5x

Address Mux

5

Note 3

Reserved

Nonmultiplexed

(default)

0

(default)

0

1

Note 4

1

External

Address multiplexed

Notes 1. Bits A10–A17 must be set to all ‘0’.

2. BL=8 is not available for configuration 1 and 4.

3. ±30% temperature variation.

4. Within 15%.

Remark The address A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in

the multiplexed address mode.

Figure 2-28. Power-Up Sequence in Multiplexed Address Mode

VEXT

V

DD

V

DDQ

V

REF

VTT

CK#

CK

NOP

Ay

MRS

RF0

RF1

RF7

AC

COMMAND

ADDRESS

NOP

Note 1, 2

Note 2, 3

Note 4

A

Ax

A

1 cycle

MIN.

200μs MIN.

1 cycle

MIN.

tMRSC

tRC

Refresh all banks

15μs

Don't care

Notes 1. Recommended all address pins held LOW during dummy MRS command.

2. A10-A17 must be LOW.

3. Address A5 must be set HIGH (muxed address mode setting when μPD48576209/18/36 is in normal mode

of operation).

4. Address A5 must be set HIGH (muxed address mode setting when μPD48576209/18/36 is already in

muxed address mode).

Remark MRS: MRS command

RFp : REFRESH Bank p

AC : any command

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μPD48576209, μPD48576218, μPD48576236

2.15 Address Mapping in Multiplexed Mode

The address mapping is described in Table 2-6 as a function of data width and burst length.

Table 2-6. Address Mapping in Multiplexed Address Mode

Data

Burst

Ball

Address

A9

Width Length

A0

X

A3

A1

A3

A1

A3

A1

A3

A1

A3

A1

A3

A1

A3

A1

A3

A1

A3

A1

A4

A2

A4

A2

A4

A2

A4

A2

A4

A2

A4

A2

A4

A2

A4

A2

A4

A2

A5

X

A8

A6

A8

A6

A8

A6

A8

A6

A8

A6

A8

A6

A8

A6

A8

A6

A8

A6

A10

A19

A10

X

A13

A11

A13

A11

A13

A11

A13

A11

A13

A11

A13

A11

A13

A11

A13

A11

A13

A11

A14

A12

A14

A12

A14

A12

A14

A12

A14

A12

A14

A12

A14

A12

A14

A12

A14

A12

A17

A16

A17

A16

A17

A16

A17

A16

A17

A16

A17

A16

A17

A16

A17

A16

A17

A16

A18

A15

A18

A15

X

x36

x18

x9

BL=2

BL=4

BL=8

BL=2

BL=4

BL=8

BL=2

BL=4

BL=8

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

Ax

Ay

A7

A0

X

A5

X

A9

A7

A0

X

A5

X

A9

A10

X

A7

A15

A18

A15

A18

A15

A18

A15

A18

A15

A18

A15

A18

A15

A0

A20

A0

X

A5

X

A9

A10

A19

A10

A19

A10

X

A7

A5

X

A9

A7

A0

X

A5

X

A9

A7

A0

A20

A0

A20

A0

X

A5

A21

A5

X

A9

A10

A19

A10

A19

A10

A19

A7

A9

A7

A5

X

A9

A7

Remark X means “Don’t care”.

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μPD48576209, μPD48576218, μPD48576236

2.16 Read & Write configuration in Multiplexed Address Mode

In multiplexed address mode, the READ and WRITE latencies are increased by one clock cycle. The

μPD48576209/18/36 cycle time remains the same, as described in Table 2-7.

Table 2-7. Configuration in Multiplexed Address Mode

Parameter

Configuration

3

Unit

Note2

Note2, 3

5

2

1

4

tRC

4

5

6

8

9

3

4

5

tCK

tRL

tWL

7

8

6

7

10

tCK

Valid frequency range

266-175

400-175

533-175

200-175

333-175

MHz

Notes 1. Apply to the entire table. tRC < 20 ns in any configuration is only available with –E24 and –E18 speed grades.

2. BL = 8 is not available.

3. The minimum t^RCis typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank.

In this instance the minimum t^RCis 4 cycles.

2.17 Refresh Command in Multiplexed Address Mode

Similar to other commands, the refresh command is executed on the next rising clock edge when in the multiplexed

address mode. However, since only bank address is required for AREF, the next command can be applied on the

following clock. The operation of the AREF command and any other command is represented in Figure 2-29.

Figure 2-29. Burst REFRESH Operation

11

10

9

0

1

2

3

4

5

6

7

8

CK#

CK

NOP

COMMAND

AC

AREF

AC

AREF

COMMAND

ADDRESS

Ax

Ay

Ax

Ay

BANK

BAp

BA0

BA1

BA2

BA3

BA4

BA5

BA6

BAp

BA7

ADDRESS

BANK

ADDRESS

Don’t care

Remark AREF

: AUTO REFRESH

: Any command

: First part Ax of address

AC

Ax

Ay

: Second part Ay of address

BAp

: Bank p is chosen so that t^RCis met.

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Figure 2-30. WRITE Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

WR

NOP

Ay

WR

NOP

WR

NOP

Ay

WR

NOP

Ay

WR

Ax

BA0

Ax

BA1

Ax

BA2

Ax

BA3

Ax

BA0

Ay

WL = 6

DKx#

DKx

DQ

D0a D0b D0c D0d D1a D1

Don’t care

Figure 2-31. READ Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1, RL=5

0

1

2

3

4

5

6

7

8

CK#

CK

COMMAND

ADDRESS

RD

NOP

Ay

RD

NOP

Ay

RD

NOP

Ay

RD

NOP

Ay

RD

Ax

BA0

Ax

BA1

Ax

BA2

Ax

BA0

Ax

BA1

RL = 5

QKx

QKx#

QVLD

DQ

Q0a Q0b Q0c Q0d Q1a Q1b Q1c

Don’t care

Undefined

Remark WR

: WRITE command

: READ command

: Address Ax of bank p

: Address Ay of bank p

: Data q to bank p

: Data q from bank p

: WRITE latency

RD

Ax/BAp

Ay

Dpq

Qpq

WL

RL

: READ latency

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 38 of 52

μPD48576209, μPD48576218, μPD48576236

2.18 Input Slew Rate Derating

Table 2-8 on page 40 and Table 2-9 on page 41 define the address, command, and data setup and hold derating values.

These values are added to the default tAS/tCS/tDS and tAH/tCH/tDH specifications when the slew rate of any of these

input signals is less than the 2 V/ns the nominal setup and hold specifications are based upon.

To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the

“tAS/tCS V^REFto CK/CK# Crossing” and the tAH/tCH default specification to the “tAH/tCH CK/CK# Crossing to

V^REF” derated values on Table 2-8. The derated data setup and hold values can be determined in a like manner using the

“tDS V^REFto CK/CK# Crossing” and “tDH to CK/CK# Crossing to VREF” values on Table 2-9.

The derating values on Table 2-8 and Table 2-9 apply to all speed grades.

The setup times on Table 2-8 and Table 2-9 represent a rising signal. In this case, the time from which the rising signal

crosses V^IH(AC)MIN to the CK/CK# cross point is static and must be maintained across all slew rates. The derated setup

timing represents the point at which the rising signal crosses V^REF(DC)to the CK/CK# cross point. This derated valueis

calculated by determining the time needed to maintain the given slew rate and the delta between V^IH(AC)MIN and the

CK/CK# cross point. The setup values in Table 2-8 and Table 2-9 are also valid for falling signals (with respect to

V^IL[AC]MAX and the CK/CK# cross point).

The hold times in Table 2-8 and Table 2-9 represent falling signals. In this case, the time from the CK/CK# cross point

to when the signal crosses V^IH(DC)MIN is static and must be maintained across all slew rates. The derated hold timing

represents the delta between the CK/CK# cross point to when the falling signal crosses V^REF(DC). This derated value is

calculated by determining the time needed to maintain the given slew rate and the delta between the CK/CK# cross

point and V^IH(DC). The hold values in Table 2-8 and Table 2-9 are also valid for rising signals (with respect to VIL[DC]

MAX and the CK and CK# cross point).

Note: The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 39 of 52

μPD48576209, μPD48576218, μPD48576236

Table 2-8. Address and Command Setup and Hold Derating Values

REF

t

IH(AC)

t

t t

AH/ CH

Command/

Address Slew

Rate (V/ns)

AS/ CS V

to

AS/ CS V

AH/ CH

CK/CK#

Crossing

MIN to CK/CK#

Crossing

CK/CK#

Crossing to

CK/CK#

Crossing to

IH(DC)

Unit

REF

V

MIN

CK, CK# Differential Slew Rate: 2.0 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0

5

-100

0

-50

ps

3

11

18

25

33

43

54

67

82

100

6

9

13

17

22

27

34

41

50

CK, CK# Differential Slew Rate: 1.5 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

30

35

-70

30

33

36

39

43

47

52

57

64

71

80

-20

ps

41

48

55

63

73

84

97

112

130

CK, CK# Differential Slew Rate: 1.0 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

60

65

-40

60

63

10

ps

71

66

78

69

85

73

93

77

103

114

127

142

160

82

87

94

101

110

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 40 of 52

μPD48576209, μPD48576218, μPD48576236

Table 2-9. Data Setup and Hold Derating Values

Data Slew Rate

(V/ns)

tDS VREF to

DK/DK#

Crossing

tDS VIH(AC)

MIN to DK/DK#

Crossing

tDH DK/DK#

Crossing to

VREF

tDH DK/DK#

Crossing to

VIH(DC) MIN

Unit

DK, DK# Differential Slew Rate: 2.0 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0

5

-100

0

-50

ps

3

11

18

25

33

43

54

67

82

100

6

9

13

17

22

27

34

41

50

DK, DK# Differential Slew Rate: 1.5 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

30

35

-70

30

33

36

39

43

47

52

57

64

71

80

-20

ps

41

48

55

63

73

84

97

112

130

DK, DK# Differential Slew Rate: 1.0 V/ns

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

60

65

-40

60

63

10

ps

71

66

78

69

85

73

93

77

103

114

127

142

160

82

87

94

101

110

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 41 of 52

μPD48576209, μPD48576218, μPD48576236

Figure 2-32. Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate

VDDQ

V

IH(AC) MIN.

IH(DC) MIN.

V

VRFE(DC)

V

IL(DC) MAX.

IL(AC) MAX.

V

VSSQ

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 42 of 52

μPD48576209, μPD48576218, μPD48576236

3. JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Table 3-1. Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

Description

Test Clock Input. All input are captured on the rising edge of TCK and all

outputs propagate from the falling edge of TCK.

12A

Test Mode Select. This is the command input for the TAP controller state

TMS

TDI

11A

12V

Test Data Input. This is the input side of the serial registers placed between

TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP controller state machine and the instruction that is currently

TDO

11V

Test Data Output. This is the output side of the serial registers placed between

TDI and TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the POWER-UP.

Table 3-2. JTAG DC Characteristics (0°C ≤ TC ≤ 95°C, 1.7 V ≤ VDD ≤ 1.9 V, unless otherwise noted)

Parameter

Symbol

Conditions

0 V ≤ V_IN≤ V_DD

MIN.

−5.0

MAX.

+5.0

Unit Notes

JTAG Input leakage

current

I_LI

μA

JTAG I/O leakage current

I_LO

0 V ≤ V_IN≤ V_DDQ ,

Outputs disabled

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

V_IH

V_IL

V_REF+ 0.15

V_DD+ 0.3

V

1, 2

V

_SSQ − 0.3

V_DDQ − 0.2

_DDQ − 0.4

V_REF− 0.15

V_OH1

V_OH2

V_OL1

V_OL2

| I_OHC| = 100 μA

| I_OHT| = 2 mA

I_OLC= 100 μA

I_OLT= 2 mA

V

JTAG output LOW voltage

0.2

0.4

1

Note 1. All voltages referenced to VSS (GND).

2. Overshoot: V^{IH (AC)}≤ VDD + 0.7 V for t ≤ tCK/2.

Undershoot: V^{IL (AC)}≥ –0.5 V for t ≤ tCK/2.

During normal operation, V^DDQ must not exceed VDD.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 43 of 52

μPD48576209, μPD48576218, μPD48576236

JTAG AC Test Conditions

Input waveform

V

DDQ

V

IH(AC) MIN.

IL(AC) MAX.

V

SS

Rise Time:

2 V/ns

Fall Time:

2 V/ns

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

VTT

50Ω

Test point

10pF

TDO

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 44 of 52

μPD48576209, μPD48576218, μPD48576236

Table 3-3. JTAG AC Characteristics (0°C ≤ T^C≤ 95°C)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Note

Clock

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

t_THTH

f_TF

t_THTL

t_TLTH

20

ns

MHz

ns

50

10

ns

Output time

TCK LOW to TDO

t_TLOX

t_TLOV

0

ns

TCK LOW to TDO valid

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

t_MVTH

t_DVTH

t_CSJ

5

ns

1

Hold time

TMS hold time

t_THMX

t_THDX

t_CHJ

5

ns

TCK HIGH to TDI invalid

Capture hold time

Note 1. tCSJ and tCHJ refer to the setup and hold time requirements of latching data from the boundary scan register.

JTAG Timing Diagram

t

THTH

TCK

TMS

TDI

t

MVTH

t

THTL

t

TLTH

t

THMX

t

DVTH

t

THDX

t

TLOV

t

TLOX

TDO

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 45 of 52

μPD48576209, μPD48576218, μPD48576236

Table 3-4. Scan Register Definition (1)

Register name

Description

Instruction register

The 8 bit instruction registers hold the instructions that are executed by the TAP

controller. The register can be loaded when it is placed between the TDI and TDO pins.

The instruction register is automatically preloaded with the IDCODE instruction at power-

up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It

allows serial test data to be passed through the RAMs TAP to another device in the scan

chain with as little delay as possible. The bypass register is set LOW (VSS) when the

bypass instruction is executed.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit

code when the controller is put in capture-DR state with the IDCODE command loaded in

the instruction register. The register is then placed between the TDI and TDO pins when

the controller is moved into shift-DR state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents

of the RAMs I/O ring when the controller is in capture-DR state and then is placed

between the TDI and TDO pins when the controller is moved to shift-DR state. Several

TAP instructions can be used to activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary

register location. The first column defines the bit’s position in the boundary register. The

second column is the name of the input or I/O at the bump and the third column is the

bump number.

Table 3-5. Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

8

1

bit

32

113

bit

Boundary register

bit

Table 3-6. ID Register Definition

ID [31:28] vendor

ID [0]

fix bit

Part number

Organization

ID [27:12] part no.

ID [11:1] vendor ID no.

revision no.

μPD48576209

μPD48576218

μPD48576236

64M x 9

32M x 18

16M x 36

0000

0001 0001 1010 0111

00000010000

1

0001

0010

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 46 of 52

μPD48576209, μPD48576218, μPD48576236

Table 3-7. SCAN Exit Order

Bit

Signal name

x18

Bump

ID

Bit

Signal name

x18

Bump

ID

Bit

Signal name

x18

Bump

ID

no.

x9

x36

no.

x9

x36

no.

x9

x36

1

DK

DK#

CS#

REF#

WE#

A17

DK

DK1

DK1#

CS#

K1

K2

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

DNU

DQ5

DNU

DQ4

DM

DNU

DQ10

DNU

DQ9

DM

DQ30

DQ32

DQ33

DQ34

DQ35

DM

R11

P11

P10

N11

N10

P12

N12

M11

M10

M12

L12

L11

K11

K12

J12

77

78

DNU

DQ1

DNU

DQ0

DNU

A21

DNU

DQ1

DNU

DQ0

DQ4

DNU

DQ5

DNU

DQ6

DNU

DQ7

DNU

DQ8

(A21)

A5

DQ2

DQ3

DQ0

DQ1

DQ9

DQ8

DQ11

DQ10

DQ13

DQ12

DQ14

DQ15

DQ16

DQ17

(A21)

A5

C11

C10

B11

B10

B3

2

DK#

3

CS#

L2

79

4

REF#

WE#

A17

REF#

WE#

L1

80

5

M1

M3

M2

N1

P1

81

6

A17

82

7

A16

83

8

A18

84

9

A15

85

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

DNU

ZQ

DQ14

DNU

DQ15

DNU

QK1

DQ25

DQ24

DQ23

DQ22

QK1

N3

N2

P3

86

B3

87

B2

A19

A11

A12

A10

A13

A14

BA1

CK#

CK

A19

A11

A12

A10

A13

A14

BA1

CK#

CK

A19

88

B2

A11

89

C3

C2

D3

D2

E2

A12

90

P3

A10

91

P2

A13

92

P2

A14

93

R2

R3

T2

BA1

CK#

CK

94

QK1#

DNU

DQ16

DNU

DQ17

ZQ

QK1#

DQ20

DQ21

DQ18

DQ19

ZQ

95

96

T2

BA0

A4

BA0

A4

BA0

A4

J11

97

T3

H11

H12

G12

G10

G11

E12

F12

F10

F11

E10

E11

D11

D10

98

E2

T3

A3

99

E3

U2

U3

V2

A0

100

101

102

103

104

105

106

107

108

109

110

111

112

113

E3

A2

F2

A1

F2

A20

QVLD

DQ3

DNU

DQ2

DNU

QK0

QK0#

A20

QVLD

DQ3

DNU

DQ2

DNU

QK0

QK0#

(A20)

QVLD

DQ7

DQ6

DQ5

DQ4

QK0

QK0#

F3

DQ8

DNU

DQ7

DNU

DQ6

DQ13

DNU

DQ12

DNU

DQ11

DQ27

DQ26

DQ29

DQ28

DQ31

U10

U11

T10

T11

R10

E1

A5

F1

A6

G2

G3

G1

H1

H2

J2

A7

A8

BA2

A9

BA2

A9

BA2

A9

NF

DK0#

DK0

NF

J1

Note Any unused balls that are in the order will read as a logic “0”.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 47 of 52

μPD48576209, μPD48576218, μPD48576236

JTAG Instructions

Many different instructions (2⁸) are possible with the 8-bit instruction register. All used combinations are listed in

Table 3-8, Instruction Codes. These six instructions are described in detail below. The remaining instructions are

reserved and should not be used.

The TAP controller used in this RAM is fully compliant to the 1149.1 convention. Instructions are loaded into the

TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state,

instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once

it is shifted in, the TAP controller needs to be moved into the Update-IR state.

Table 3-8

Instructions

Instruction

Code [7:0]

Description

EXTEST

0000 0000

The EXTEST instruction allows circuitry external to the component package to be

tested. Boundary-scan register cells at output pins are used to apply test vectors, while

those at input pins capture test results. Typically, the first test vector to be applied

using the EXTEST instruction will be shifted into the boundary scan register using the

PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output drive is

turned on and the PRELOAD data is driven onto the output pins.

IDCODE

0010 0001

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the

controller is in capture-DR mode and places the ID register between the TDI and TDO

pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at

power up and any time the controller is placed in the test-logic-reset state.

SAMPLE / PRELOAD 0000 0101

SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the

SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP

controller into the capture-DR state loads the data in the RAMs input and DQ pins into

the boundary scan register. Because the RAM clock(s) are independent from the TAP

clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while

the input buffers are in transition (i.e., in a metastable state). Although allowing the

TAP to sample metastable input will not harm the device, repeatable results cannot be

expected. RAM input signals must be stabilized for long enough to meet the TAPs

input data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not

be paused for any other TAP operation except capturing the I/O ring contents into the

boundary scan register. Moving the controller to shift-DR state then places the

boundary scan register between the TDI and TDO pins.

CLAMP

0000 0111

0000 0011

1111 1111

−

When the CLAMP instruction is loaded into the instruction register, the data driven by

the output balls are determined from the values held in the boundary scan register.

Selects the bypass register to be connected between TDI and TDO. Data driven by

output balls are determined from values held in the boundary scan register.

High-Z

The High-z instruction causes the boundary scan register to be connected between the

TDI and TDO. This places all RAMs outputs into a High-Z state.

Selects the bypass register to be connected between TDI and TDO. All outputs are

forced into high impedance state.

BYPASS

When the BYPASS instruction is loaded in the instruction register, the bypass register

is placed between TDI and TDO. This occurs when the TAP controller is moved to the

shift-DR state. This allows the board level scan path to be shortened to facilitate

testing of other devices in the scan path.

Reserved for Future Use

The remaining instructions are not implemented but are reserved for future use. Do not

use these instructions.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 48 of 52

μPD48576209, μPD48576218, μPD48576236

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 49 of 52

μPD48576209, μPD48576218, μPD48576236

4. Package Dimension

144-PIN TAPE FBGA ( μBGA) (18.5x11)

D

w

S

A

ZE

B

DD1

eD

ZD

SD

12

11

10

9

A

E2

8

7

6

5

4

E1

E

SE

3

2

1

eE

S

V U T R P

L K J H

N M

G F E D C B A

4xC0.2

INDEX MARK

w

B

INDEX MARK

D2

(UNIT:mm)

ITEM DIMENSIONS

Detail of A pa rt

A

D

18.50 0.10

17.90

y1

S

A2

D1

D2

E

A3

S

14.52

11.00 0.10

10.70

E1

y

S

A1

2.184

E2

w

0.20

M

b

x

S A B

A

1.07 0.10

0.39 0.05

0.68

A1

A2

A3

eD

eE

SD

SE

b

0.08 MAX.

1.00

0.80

0.50

2.00

0.51 0.05

0.15

x

y

0.10

y1

ZD

ZE

0.20

0.75

1.10

P144FF-80-DW1

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 50 of 52

μPD48576209, μPD48576218, μPD48576236

5. Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD48576209FF-DW1

μPD48576218FF-DW1

μPD48576236FF-DW1

: 144-pin TAPE FBGA (18.5 x 11)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to

the ground and so forth.

R10DS0063EJ0300 Rev.3.00

Oct 01, 2012

Page 51 of 52

Revision History

μPD48576209, μPD48576218, μPD48576236

Description

Summary

Rev.

Date

Page

-

Rev.0.01

Rev.1.00

’10.11.08

’11.09.27

New Preliminary Data Sheet

New Data Sheet

-

P12

P16

Update DC Characteristics

Update Thermal Impedance

Rev.2.00

Rev.3.00

’12.05.10

’12.10.01

P39, P40

P41, P42

P18,P19

P35

Update Input Slew Rate Derating

Update Power-On Sequence

All trademarks and registered trademarks are the property of their respective owners.

C - 52

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1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

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others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics

assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific":

Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and

malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the

possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics

products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes

no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Tel: +1-905-898-5441, Fax: +1-905-898-3220

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-65030, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China

Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

13F, No. 363, Fu Shing North Road, Taipei, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632

Tel: +65-6213-0200, Fax: +65-6278-8001

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141

Colophon 1.1


型号：	UPD48576236FF-E24-DW1-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	Low Latency DRAM, T-TFBGA, /Tray 时钟动态存储器双倍数据速率内存集成电路
文件：	总53页 (文件大小：1118K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD48576236FF-E24-DW1-A [RENESAS]

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