UPD6134MC-XXX-5A4-E1 [RENESAS]
UPD6134MC-XXX-5A4-E1;
| 型号： | UPD6134MC-XXX-5A4-E1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | UPD6134MC-XXX-5A4-E1 光电二极管 |
| 文件： | 总66页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6133, 6134
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
Equipped with low-voltage 1.8V operation, a carrier generation circuit for infrared remote control transmission,
a standby release function through key entry, and a programmable timer, the µPD6133 and 6134 are suitable for
infrared remote control transmitters.
For the µPD6133 and 6134, we have made available the one-time PROM product µPD61P34B for program
evaluation or small-quantity production.
FEATURES
• Program memory (ROM)
· µPD6133: 512 × 10 bits
· µPD6134: 1002 × 10 bits
• Data memory (RAM): 32 × 4 bits
• Built-in carrier generation circuit for infrared remote control
• 9-bit programmable timer
• Command execution time
• Stack level
: 1 channel
: 8 µs (when operating at fX = 1 MHz: ceramic oscillation)
: 1 level (Stack RAM is for data memory RF as well.)
• I/O pins (KI/O)
: 8 units
: 4 units
: 1 unit
• Input pins (KI)
• Sense input pin (S0)
• S1/LED pin (I/O)
:
1 unit (When in output mode, this is the remore control transmission
display pin.)
• Power supply voltage
: VDD = 1.8 to 3.6 V (when operating at fX = 500 kHz)
VDD = 2.2 to 3.6 V (when operating at fX = 1 MHz)
• Operating ambient temperature : TA = –40 to +85 ˚C
• Oscillation frequency
: fX = 300 kHz to 1 MHz
• POC circuit (Mask option)
APPLICATION
Infrared remote control transmitter (for AV and household electric appliances)
Unless otherwise stated, the µPD6133 is taken as a representative product in this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U10454EJ6V0DS00 (6th edition)
Date Published June 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
1995, 1999
©
µPD6133, 6134
ORDERING INFORMATION
Part Number
Package
µPD6133GS-×××
µPD6134GS-×××
µPD6134MC-×××-5A4
20-pin plastic SOP (300 mil)
20-pin plastic SOP (300 mil)
20-pin plastic SSOP (300 mil)
Remark ××× indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
20-pin Plastic SOP (300 mil)
• µPD6133GS-×××
• µPD6134GS-×××
20-pin Plastic SSOP (300 mil)
• µPD6134MC-×××-5A4
KI/O6
KI/O7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
KI3
S0
S1/LED
REM
VDD
XOUT
XIN
KI2
GND
RESET
KI1
KI0
Caution The pin numbers of KI and KI/O are in the reverse order of the µPD6600A and 6124A.
Data Sheet U10454EJ6V0DS00
2
µPD6133, 6134
BLOCK DIAGRAM
4
8
2
4
8
2
PORT K
I
K
K
S
I0-KI3
CARRIER
GENERATOR
REM
/LED
CPU
CORE
ROM
PORT KI/O
PORT S
I/O0-KI/O7
9-bit
TIMER
S
1
0
, S /LED
1
RESET
RAM
SYSTEM
CONTROL
X
X
IN
OUT
V
DD
GND
LIST OF FUNCTIONS
Item
µPD6133
µPD6134
1002 × 10 bit
µPD61P34B
ROM capacity
512 × 10 bit
Mask ROM
32 × 4 bits
1002 × 10 bits
One-time PROM
RAM capacity
Stack
1 level (multiplexed with RF of RAM)
I/O pins
• Key input (KI)
• Key I/O (KI/O)
: 4
: 8
: 2
• Key extended input (S0, S1)
• Remote control transmission display output (LED) : 1 (multiplexed with S1 pin)
Number of keys
Clock frequency
• 32 keys
• 48 keys (when extended by key extension input)
• 96 keys (when extended by key extension input and diode)
Ceramic oscillation
• fX = 300 kHz to 1 MHz
• fX = 300 to 500 kHz (with POC circuit)
Instruction execution time
Carrier frequency
Timer
8 µs (fx = 1 MHz)
fX, fX/2, fX/8, fX/12, fX/16, fX/24, no carrier (high level)
9-bit programmable timer: 1 channel
POC circuit
Mask option
Internal
Supply voltage
VDD = 1.8 to 3.6 V
VDD = 2.2 to 3.6 V
Operating ambient temperature
• TA = –40 to +85 °C
• TA = –20 to +70 °C (with POC circuit)
Package
• 20-pin plastic SOP
(300 mil)
• 20-pin plastic SOP (300 mil)
• 20-pin plastic SSOP (300 mil)
Data Sheet U10454EJ6V0DS00
3
µPD6133, 6134
TABLE OF CONTENTS
1. PIN FUNCTIONS.........................................................................................................................
1.1 List of Pin Functions.........................................................................................................................
1.2 INPUT/OUTPUT Circuits of Pins ......................................................................................................
1.3 Dealing with Unused Pins ................................................................................................................
6
6
7
8
2. INTERNAL CPU FUNCTIONS ....................................................................................................
2.1 Program Counter (PC) ......................................................................................................................
2.2 Stack Pointer (SP) .............................................................................................................................
2.3 Address Stack Register (ASR (RF)).................................................................................................
9
9
9
9
2.4 Program Memory (ROM) ................................................................................................................... 10
2.5 Data Memory (RAM) .......................................................................................................................... 10
2.6 Data Pointer (DP)............................................................................................................................... 11
2.7 Accumulator (A) ................................................................................................................................ 11
2.8 Arithmetic and Logic Unit (ALU) ...................................................................................................... 12
2.9 Flags ................................................................................................................................................... 12
2.9.1 Status flag (F).......................................................................................................................... 12
2.9.2 Carry flag (CY) ........................................................................................................................ 13
3. PORT REGISTERS (PX)............................................................................................................. 14
3.1 KI/O Port (P0)....................................................................................................................................... 15
3.2 KI Port/Special Ports (P1) ................................................................................................................. 16
3.2.1 KI port (P11: bits 4-7 of P1) ..................................................................................................... 16
3.2.2 S0 port (bit 2 of P1).................................................................................................................. 16
3.2.3 S1/LED (bit 3 of P1) ................................................................................................................. 16
3.3 Control Register 0 (P3) ..................................................................................................................... 17
3.4 Control Register 1 (P4) ..................................................................................................................... 18
4. TIMER ......................................................................................................................................... 19
4.1 Timer Configuration .......................................................................................................................... 19
4.2 Timer Operation................................................................................................................................. 20
4.3 Carrier Output .................................................................................................................................... 21
4.4 Software Control of Timer Output ................................................................................................... 21
5. STANDBY FUNCTION................................................................................................................ 22
5.1 Outline of Standby Function ............................................................................................................ 22
5.2 Standby Mode Setup and Release................................................................................................... 23
5.3 Standby Mode Release Timing ........................................................................................................ 24
6. RESET PIN.................................................................................................................................. 26
7. POC CIRCUIT (MASK OPTION) ................................................................................................ 27
7.1 Functions of POC Circuit.................................................................................................................. 28
7.2 Oscillation Check at Low Supply Voltage....................................................................................... 28
8. SYSTEM CLOCK OSCILLATOR................................................................................................ 29
Data Sheet U10454EJ6V0DS00
4
µPD6133, 6134
9. INSTRUCTION SET .................................................................................................................... 30
9.1 Machine Language Output by Assembler....................................................................................... 30
9.2 Circuit Symbol Description .............................................................................................................. 31
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ............................... 32
9.4 Accumulator Operation Instructions ............................................................................................... 36
9.5 Input/Output Instructions ................................................................................................................. 39
9.6 Data Transfer Instructions................................................................................................................ 40
9.7 Branch Instructions .......................................................................................................................... 42
9.8 Subroutine Instructions .................................................................................................................... 43
9.9 Timer Operation Instructions ........................................................................................................... 44
9.10 Others................................................................................................................................................. 45
10. ASSEMBLER RESERVED WORDS .......................................................................................... 47
10.1 Mask Option Directives..................................................................................................................... 47
10.1.1 OPTION and ENDOP directives ............................................................................................. 47
10.1.2 Mask option definition directives ............................................................................................. 47
11. ELECTRICAL SPECIFICATIONS............................................................................................... 48
12. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 52
13. APPLIED CIRCUIT EXAMPLE ................................................................................................... 54
14. PACKAGE DRAWINGS.............................................................................................................. 55
15. RECOMMENDED SOLDERING CONDITIONS.......................................................................... 57
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 58
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD6133 SUBSERIES AND
OTHER SUBSERIES ................................................................................................ 59
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case
of NEC transmission format in command one-shot transmission mode) ......... 60
Data Sheet U10454EJ6V0DS00
5
µPD6133, 6134
1. PIN FUNCTIONS
1.1 List of Pin Functions
Pin No.
Symbol
Function
Output Format
CMOS
push-pullNote 1
When Reset
1
KI/O0-KI/O7
These pins refer to the 8-bit I/O ports. I/O switching can
be made in 8-bit units.
High-level output
2
15-20
In INPUT mode, a pull-down resistor is added.
In OUTPUT mode, they can be used as the key scan
output of the key matrix.
3
S0
Refers to the input port.
—
High-impedance
(OFF mode)
Can also be used as the key return input of the key
matrix.
In INPUT mode, the availability of the pull-down resistor
of the S0 and S1 ports can be specified by software in
terms in 2-bit units.
If INPUT mode is canceled by software, this pin is placed
in OFF mode and enters the high-impedance state.
4
S1/LED
Refers to the I/O port.
CMOS push-pull
High-level output
(LED)
In INPUT mode (S1), this pin can also be used as the key
return input of the key matrix.
The availability of the pull-down resistor of the S0 and S1
ports can be specified by software in 2-bit units.
In OUTPUT mode (LED), it becomes the remote control
transmission display output (active low). When the
remote control carrier is output from the REM output, this
pinoutputsthelowlevelfromtheLEDoutputsynchronously
with the REM signal.
5
6
REM
Refers to the infrared remote control transmission output.
The output is active high.
CMOS push-pull
Low-level output
Carrier frequency: fX, fX/8, fX/12, high-level,
fX/2, fX/16, fX/24 (usable on software)
VDD
Refers to the power supply.
—
—
—
7
8
XOUT
These pins are connected to system clock ceramic
resonators.
Low level
XIN
(oscillation stopped)
9
GND
Refers to the ground.
—
—
—
—
10
RESET
Normally, this pin is a system reset input. By inputting
a low level, the CPU can be reset. When resetting with
the POC circuit (mask option) a low level is output. A
pull-up resistor is incorporated.
Note 2
11-14
KI0-KI3
These pins refer to the 4-bit input ports.
They can be used as the key return input of the key
matrix.
—
Input (low-level)
The use of the pull-down resistor can be specified by
software in 4-bit units.
Notes 1. Be careful about this because the drive capability of the low-level output side is held low.
2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when
reset is released (when RESET pin changes from low level to high level, or POC is released due to
supply voltage startup).
Data Sheet U10454EJ6V0DS00
6
µPD6133, 6134
1.2 INPUT/OUTPUT Circuits of Pins
The input/output circuits of the µPD6133 pins are shown in partially simplified forms below.
(1) KI/O0-KI/O7
(4) S0
V
DD
Input buffer
OFF mode
Output
Data
latch
P-ch
N-chNote
Output
disable
Standby
release
N-ch
Pull-down flag
Input buffer
N-ch
(5) S1/LED
VDD
Note The drive capability is held low.
REM
output latch
P-ch
(2) KI0-KI3
Output
disable
N-ch
Standby
release
Standby
release
Input buffer
Input buffer
Pull-down flag
N-ch
N-ch
Pull-down flag
(3) REM
(6) RESET
VDD
VDD
P-ch
P-ch
Output
latch
Data
N-ch
Carrier
generator
Input buffer
Internal reset signal
other than POC
N-ch
Mask option
POC circuit
Data Sheet U10454EJ6V0DS00
7
µPD6133, 6134
1.3 Dealing with Unused Pins
The following connections are recommended for unused pins.
Table 1-1. Connections for Unused Pins
Connection
Inside the microcontroller Outside the microcontroller
Pin
KI/O
INPUT mode
—
High-level output
—
Open
OUTPUT mode
REM
S1/LED
S0
OUTPUT mode (LED) setting
OFF mode setting
—
Directly connected to GND
Open
KI
RESETNote
Built-in POC circuit
Note If the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the RESET
signal is entered externally.
Caution The I/O mode and the terminal output level are recommended to be fixed by setting them
repeatedly in each loop of the program.
Data Sheet U10454EJ6V0DS00
8
µPD6133, 6134
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 10 Bits
Refers to the binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Organization
PC PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
The program counter contains the address of the instruction that should be executed next. Normally, the counter
contents are automatically incremented in accordance with the instruction length (byte count) each time an
instruction is executed.
However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump
destination address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
When reset, the value of the program counter becomes “000H”.
2.2 Stack Pointer (SP): 1 Bit
Refers to the 1-bit register which holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented
when the return instruction (RET) is executed.
When reset, the stack pointer contents are cleared to “0”.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up thus a system reset
signal is generated and the PC becoming “000H”.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 10 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The low-order 8 bits are arranged in the RF of the data memory as a dual-function RAM. The register holds
the ASR value even after the RET is executed.
When reset, it holds the previous data (undefined when turning on the power).
Caution If the RF is accessed as the data memory, the high-order 2 bits of the ASR become undefined.
Figure 2-2. Address Stack Register Organization
RF
ASR ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
Data Sheet U10454EJ6V0DS00
9
µPD6133, 6134
2.4 Program Memory (ROM): 512 steps × 10 bits (µPD6133)
1002 steps × 10 bits (µPD6134)
The ROM consists of 10 bits per step, and is addressed by the program counter.
The program memory stores programs and table data, etc.
The 22 steps from 3EAH to 3FFH cannot be used in the test program area.
Figure 2-3. Program Memory Map
(a) µPD6133
(b) µPD6134
10 bits
10 bits
000H
000H
0FFH
100H
0FFH
100H
1FFH
1FFH
200H
Unmounted areaNote
2FFH
300H
3E9H
3EAH
3FFH
3E9H
3EAH
Test
Test
program areaNote
program areaNote
3FFH
Note The unmounted area and the test program area are so designed that a program or data placed in either
of them by mistake is returned to the 000H address.
2.5 Data Memory (RAM): 32 × 4 Bits
The data memory, which is a static RAM consisting of 32 × 4 bits, is used to retain processed data. The data
memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer.
RF is also used as the ASR.
When reset, R0 is cleared to “00H” and R1 to RF retain the previous data (undefined when turning on the power).
Data Sheet U10454EJ6V0DS00
10
µPD6133, 6134
Figure 2-4. Data Memory Organization
R1n (high-order 4 bits) R0n (low-order 4 bits)
→DP (Refer to 2.6 Data Pointer.)
R0
R
R
R
R
R
R
R
R
R
R
R
R
10
11
12
13
14
15
16
17
18
19
1A
1B
R
R
R
R
R
R
R
R
R
R
R
R
00
01
02
03
04
05
06
07
08
09
0A
0B
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF
R1C
R1D
R1E
R1F
R0C
R0D
R0E
R0F
→ASR (Refer to 2.3 Address Stack Register.)
2.6 Data Pointer (DP): 10 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.
The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 2 bits by
bits 4 and 5 of the P3 register (CR0).
When reset, the pointer contents become “000H”.
Figure 2-5. Data Pointer Organization
P3 Register
b5
b
4
R10
R00
P3
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP0
R0
2.7 Accumulator (A): 4 Bits
The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various
operations.
When reset, the accumulator contents are left undefined.
Figure 2-6. Accumulator Organization
A
3
A
2
A
1
A
0
A
Data Sheet U10454EJ6V0DS00
11
µPD6133, 6134
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple
manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (to 1) in the following cases.
• If the condition specified with the operand is met when the STTS instruction has been executed
• When STANDBY mode is canceled.
• When the cancelation condition is met at the point of executing the HALT instruction. (In this case, the system
is not placed in STANDBY mode.)
Conversely, the status flag is cleared (to 0) in the following cases:
• If the condition specified with the operand is not met when the STTS instruction has been executed.
• When the status flag has been set (to 1), the HALT instruction executed, but the cancelation condition is not
met at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.)
Table 2-1. Conditions for Status Flag (F) to be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) to be Set
b3
b2
b1
b0
0
0
0
0
High level is input to at least one of KI pins.
High level is input to at least one of KI pins.
High level is input to at least one of KI pins.
The down counter of the timer is 0.
0
1
1
1
1
0
1
0
1
1
Either of the combinations
of b2, b1, and b0 above.
[The following condition is added in addition to the above.]
High level is input to at least one of S0 and S1 pins.
Data Sheet U10454EJ6V0DS00
12
µPD6133, 6134
2.9.2 Carry flag (CY)
The carry flag is set (to 1) in the following cases:
• If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is “1” and bit 3 of the
operand is “1”.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “1”.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH.
The carry flag is cleared (to 0) in the following cases:
• If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit
3 of the operand is “0”.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “0”.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH.
• If the ORL instruction is executed.
• When Data is written to the accumulator by the MOV instruction or the IN instruction.
Data Sheet U10454EJ6V0DS00
13
µPD6133, 6134
3. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED), and the control register are treated as port registers.
At reset, port register values are shown below.
Figure 3-1. Port Register Organization
Port Register
P0
At Reset
FFH
P10
P11
P13
P14
P00
P01
P03
P04
K
I/O7
K
I/O6
K
I/O5
K
I/O4
K
I/O3
K
I/O2
K
I/O1
K
I/O0
P1
× FHNote
K
I3
K
I2
K
I1
K
I0
S
1
/LED
S
0
1
1
P3 (Control register 0)
03H
0
0
DP
9
DP
8
TCTL
CARY
MOD
1
MOD
0
P4 (Control register 1)
26H
K
I
S
0
/S
1
0
0
0
S1
/LEDmode
KI/O mode
S0 mode
pull-down pull-down
Note ×: Refers to the value based on the KI pin state.
Table 3-1. Relationship between Ports and their Read/Write
INPUT Mode
OUTPUT Mode
Port Name
Read
Write
Read
Write
KI/O
Pin state
Pin state
Pin state
Pin state
Output latch
Output latch
—
Output latch
KI
—
—
—
—
—
—
S0
Note
S1/LED
Pin state
Note When in OFF mode, “1” is normally read.
Data Sheet U10454EJ6V0DS00
14
µPD6133, 6134
3.1 KI/O Port (P0)
The KI/O port is an 8-bit input/output port for key scan output.
INPUT/OUTPUT mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in INPUT mode, whereas the output latch contents
can be read in OUTPUT mode.
If the write instruction is executed, data can be written to the output latch regardless of INPUT or OUTPUT mode.
When reset, the port is placed in OUTPUT mode; and the value of the output latch (P0) becomes 1111 1111B.
The KI/O port contains the pull-down resistor, allowing pull-down in INPUT mode only.
Caution During double pressing of a key, a high-level output and a low-level output may coincide with
each other at the KI/O port. To avoid this, the low-level output current of the KI/O port is held
low. Therefore, be careful when using the KI/O port for purposes other than key scan output.
The KI/O port is so designed that, even when connected directly to VDD within the normal supply
voltage range (VDD = 1.8 to 3.6 V), no problem may occur.
Table 3-2. KI/O Port (P0)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
b0-b7 : In reading : In INPUT mode, the KI/O pin’s state is read.
In OUTPUT mode, the KI/O pin’s output latch contents are read.
In writing : Data is written to the KI/O pin’s output latch regardless of INPUT or OUTPUT mode.
Data Sheet U10454EJ6V0DS00
15
µPD6133, 6134
3.2 KI Port/Special Ports (P1)
3.2.1 KI port (P11: bits 4-7 of P1)
The KI port is to the 4-bit input port for key entry.
The pin state can be read.
Software can be used to set the availability of the pull-down resistor of the KI port in 4-bit units by means of bit
5 of the P4 register.
When reset, the pull-down resistor is connected.
Table 3-3. KI/Special Port Register (P1)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
KI3
KI2
KI1
KI0
S1/LED S0
(Fixed to “1”)
b2
: In INPUT mode, state of the S0 pin is read (Read only).
In OFF mode, this bit is fixed to “1”.
b3
: The state of the S1/LED pin is read regardless of INPUT/OUTPUT mode (Read only).
b4-b7 : The state of the KI pin is read (Read only).
Caution In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3
when reset is released (when RESET pin changes from low level to high level, or POC is released
due to supply voltage startup).
3.2.2 S0 port (bit 2 of P1)
The S0 port is the INPUT/OFF mode port.
The pin state can be read by setting this port to INPUT mode with bit 0 of the P4 register.
In INPUT mode, software can be used to set the availability of the pull-down resistor of the S0 and S1/LED port
in 2-bit units by means of bit 4 of the P4 register.
If INPUT mode is canceled (thus set to OFF mode), the pin becomes high-impedance but it also makes that the
through current does not flow internally. In OFF mode, “1” can be read regardless of the pin state.
When reset, it is set to OFF mode, thus becoming high-impedance.
3.2.3 S1/LED (bit 3 of P1)
The S1/LED port is the input/output port.
It uses bit 2 of the P4 register to set INPUT or OUTPUT mode. The pin state can be read in both INPUT mode
and OUTPUT mode.
When in INPUT mode, software can be used to set the availability of the pull-down resistor of the S0 and
S1/LED ports in 2-bit units by means of bit 4 of the P4 register.
When in OUTPUT mode, the pull-down resistor is automatically disconnected thus becoming the remote
transmission display pin (refer to 4. TIMER).
When reset, it is placed in OUTPUT mode, and high level is output.
Data Sheet U10454EJ6V0DS00
16
µPD6133, 6134
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0000 0011B.
Table 3-4. Control Register 0 (P3)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
—
—
DP (Data pointer) TCTL
CARY
MOD1
MOD0
DP9
0
DP8
0
Set
0
1
Fixed
to “0”
0
Fixed
to “0”
0
1/1
1/2
0
ON
OFF
0
Refer to
Table 3-5.
value
1
1
When reset
0
0
1
1
b0, b1 : These bits specify the carrier frequency and duty ratio of the REM output.
b2
: This bit specifies the availability of the carrier of the frequency specified by b0 and b1.
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
b3
: This bit changes the carrier frequency and the timer clock’s frequency division ratio.
“0” = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: fX/8)
“1” = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/16)
Table 3-5. Timer Clock and Carrier Frequency Setup
b3
b2
b1
b0
Timer Clock
Carrier Frequency (Duty Ratio)
fX (Duty 1/2)
0
1
0
0
0
1
1
×
0
0
1
1
×
0
1
0
1
×
0
1
0
1
×
fX/8
fX/8 (Duty 1/2)
fX/12 (Duty 1/2)
fX/12 (Duty 1/3)
1
0
Without carrier (high level)
fX/2 (Duty 1/2)
fX/16
fX/16 (Duty 1/2)
fX/24 (Duty 1/2)
fX/24 (Duty 1/3)
1
Without carrier (high level)
b4 and b5 : These bits specify the high-order 2 bits (DP8 and DP9) of ROM’s data pointer.
Remark ×: don’t care
Data Sheet U10454EJ6V0DS00
17
µPD6133, 6134
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0010 0110B.
Table 3-6. Control Register 1 (P4)
Bit
b7
b6
b5
KI
b4
b3
b2
b1
b0
Name
—
—
S0/S1
—
S1/LED KI/O
S0
Pull-down Pull-down
mode
S1
mode
mode
OFF
IN
Set
0
1
Fixed
to “0”
0
Fixed
to “0”
0
OFF
ON
1
OFF
ON
0
Fixed
to “0”
0
IN
value
LED
1
OUT
1
When reset
0
b0 : Specifies the input mode of the S0 port. “0” = OFF mode (high impedance); “1” = IN (INPUT mode).
b1 : Specifies the I/O mode of the KI/O port.
“0” = IN (INPUT mode); “1” = OUT (OUTPUT mode).
b2 : Specifies the I/O mode of the S1/LED port. “0” = S1 (INPUT mode); “1” = LED (output mode).
b4 : Specifies the availability of the pull-down resistor in S0/S1 port INPUT mode. “0” = OFF (unavailable);
“1” = ON (available)
b5 : Specifies the availability of the pull-down resistor in KI port. “0” = OFF (unavailable);
“1” = ON (available).
Remark In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected.
Data Sheet U10454EJ6V0DS00
18
µPD6133, 6134
4. TIMER
4.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists
of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detecting circuit.
Figure 4-1. Timer Configuration
Bit 3 of control register 0 (P3)
T
Count
clock
T1
T0
f
X
/8
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
f
X
/16
9-bit down counter
Timer operation end signal
(HALT # ×101B release
signal)
S
1/LED
Zero detecting circuit
Carrier
synchronous
circuit
REM
Bit 2 of control register 0 (P3)
Carrier signal
Data Sheet U10454EJ6V0DS00
19
µPD6133, 6134
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation
instruction. The timer operation instructions for making the timer start operation are shown below:
MOV T0, A
MOV T1, A
MOV T, #data10
MOV T, @R0
The down counter is decremented (–1) in the cycle of 8/fX or 16/fXNote. If the value of the down counter becomes
0, the zero detecting circuit generates the timer operation end signal to stop the timer operation. At this time, if
the timer is in HALT mode (HALT # × 101B) waiting for the timer to stop its operation, the HALT mode is canceled
and the instruction following the HALT instruction is executed. The output of the timer operation end signal is
continued while the down counter is 0 and the timer is stopped. There is the following relational expression between
the timer’s time and the down counter’s set value.
Note
Timer time = (Set value + 1) × 8/fX (or 16/fX
)
Note This becomes 16/fX if bit 3 of the control register is set (to 1).
By setting 1 for the flag (t9) which enables the timer output, the timer can output its operation status from the
S1/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation.
Table 4-1. Timer Output (at t9 = 1)
S1/LED Pin
REM Pin
Timer operating
Timer halting
L
H (or carrier outputNote
)
H
L
Note The carrier output results if bit 2 of the control register 0 is cleared (to 0).
Figure 4-2. Timer Output (When Carrier Is Not Output)
Timer value: (Set value + 1) × 8 f/
X
(or 16/f )
X
LED
REM
Data Sheet U10454EJ6V0DS00
20
µPD6133, 6134
4.3 Carrier Output
The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of the control
register 0.
As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues
to be output until its next fall and then stops due to the function of the carrier synchronous circuit . When the timer
starts operation, however, the high-level width of the first carrier may become shorter than the specified width.
Figure 4-3. Timer Output (When Carrier Is Output)
Timer value: (Set value+1) × 8/f
X
(or 16/f )
X
LED
REM (at low-level start)
REM (at high-level start)
Note 1
Note 2
Notes 1. Error when the REM output ends: Lead by “the carrier’s low-level width” to lag by “the carrier’s high-
level width”
2. Error of the carrier’s high-level width: 0 to “the carrier’s high-level width”
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-4, the pulse with a minimum width of 1-
instruction cycle (8/fX) can be output.
Figure 4-4. Pulse Output of 1-Instruction Cycle Width
MOV T, #0000000000B; low-level output from the REM pin
MOV T, #1000000000B; high-level output from the REM pin
MOV T, #0000000000B; low-level output from the REM pin
8/f
X
LED
REM
Data Sheet U10454EJ6V0DS00
21
µPD6133, 6134
5. STANDBY FUNCTION
5.1 Outline of Standby Function
To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, are made available.
In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed at a low level.
In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the
timer (including REM output and LED output) operates.
In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc.
immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system
so that the current consumption of the whole system is suppressed before the standby mode is set.
Table 5-1. Statuses During Standby Mode
STOP Mode
HALT instruction
HALT Mode
Setting instruction
Clock oscillator
Oscillation stopped
Oscillation continued
CPU
• Operation halted
Data memory
Accumulator
Flag
• Immediately preceding status retained
• Immediately preceding status retained
Operation
statuses
F
• 0 (When 1, the flag is not placed in the standby mode.)
• Immediately preceding status retained
CY
Port register
Timer
• Immediately preceding status retained
• Operation halted
• Operable
(The count value is reset to “0”)
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is canceled.
2. When standby mode is canceled, the status flag (F) is set (to 1).
3. If, at the point the standby mode has been set, its cancelation condition is met, then the
system is not placed in the standby mode. However, the status flag (F) is set (1).
Data Sheet U10454EJ6V0DS00
22
µPD6133, 6134
5.2 Standby Mode Setup and Cancelation
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the
standby mode to be set, the status flag (F) is required to have been cleared (to 0).
The standby mode is canceled by the cancelation condition specified with the RESET (RESET input; POC) or
the operand of HALT instruction. If the standby mode is canceled, the status flag (F) is set (to 1).
Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby
mode is not set. If the cancelation condition is not met at this time, the status flag is cleared (to 0). If the cancelation
condition is met, the status flag remains set (to 1).
Even in the case when the cancelation condition has been already met at the point that the HALT instruction
is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1).
Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be
careful about this. For example, when setting HALT mode after checking the key status with
the STTS instruction, the system does not enter HALT mode as long as the status flag (F)
remains set (to 1) thus sometimes performing an unintended operation. In this case, the
intended operation can be realized by executing the STTS instruction immediately after timer
setting to clear (to 0) the status flag.
Example STTS
#03H
;To check the KI pin status.
MOV
T, #0xxH ;To set the timer
STTS
#05H
;To clear the status flag
(During this time, be sure not to execute an instruction that may set the status flag.)
HALT
#05H
;To set HALT mode
Table 5-2. Addresses Executed After Standby Mode Release
Cancelation Condition
Address Executed After Cancelation
0 address
The address following the HALT instruction
Reset
Cancelation condition shown in Table 5-3
Data Sheet U10454EJ6V0DS00
23
µPD6133, 6134
Table 5-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b3
b2
b1
b0
0
0
0
0
STOP
All KI/O pins are high-level output.
All KI/O pins are high-level output.
The KI/O0 pin is high-level output.
High level is input to at least one
of KI pins.
0
1
1
1
1
0
STOP
High level is input to at least one
of KI pins.
STOPNote 1
High level is input to at least one
of KI pins.
1
Any of the
STOP
or
[The following condition is added in addition to the above.]
combinations of
b2b1b0 above
—
High level is input to at least one
of S0 and S1 pinsNote 2
When the timer’s down counter is 0
HALT
HALT
.
0/1
1
0
1
—
Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an
internal reset takes effect at the time of program hang-up.
2. At least one of the S0 and S1 pins (the pin used for releasing the standby) must be in INPUT mode.
(The internal reset does not take effect even when both pins are in OUTPUT mode.)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
5.3 Standby Mode Release Timing
(1) STOP Mode Release Timing
Figure 5-1. STOP Mode Cancelation by Release Condition
Wait
(36/fX + α)
HALT instruction
(STOP mode)
Standby
release signal
OPERATING
OPERATING
mode
STOP mode
HALT mode
mode
Oscillation
stopped
Oscillation
Oscillation
Clock
α : Oscillation growth time
Caution When a release condition is established in the STOP mode, the device is released from the STOP
mode and goes into a wait status. At this time, if the release condition is not held, the device
mode and goes into the STOP mode again after the wait time has elapsed. Therefore, when
releasing the STOP mode, it is necessary to hold the release condition longer than the wait time.
Data Sheet U10454EJ6V0DS00
24
µPD6133, 6134
Figure 5-2. STOP Mode Release by RESET Input
HALT instruction
(STOP mode)
Wait
(60 to 116)/fX + α
0 address start
RESET
Clock
OPERATING
mode
OPERATING
STOP
mode
Reset
HALT mode
mode
Oscillation
Oscillation stopped
Oscillation
α : Oscillation growth time
(2) HALT Mode Release Timing
Figure 5-3. HALT Mode Release by Cancelation Condition
HALT instruction
(HALT mode)
Standby
release signal
OPERATING
HALT mode
OPERATING mode
mode
Oscillation
Clock
Figure 5-4. HALT Mode Release by RESET Input
HALT instruction
(HALT mode)
Wait
(60 to 116)/f + α
0 address start
X
RESET
OPERATING
OPERATING
mode
HALT mode
Reset
HALT mode
mode
Oscillation
stopped
Oscillation
Oscillation
α : Oscillation growth time
Clock
Data Sheet U10454EJ6V0DS00
25
µPD6133, 6134
6. RESET PIN
The system reset takes effect by inputting low level to the RESET pin.
While the RESET pin is at low level, the system clock oscillator is stopped and the XIN and XOUT pins are fixed
to the GND.
If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting
60 to 116 of the system clock (fX).
Figure 6-1. Reset Operation by RESET Input
Wait
(60 to 116)/f + α
0 address start
X
RESET
OPERATING mode or Oscillation
STANDBY mode stopped
OPERATING
mode
HALT mode
α : Oscillation growth time
The RESET pin outputs low level when the POC circuit (mask option) is in operation.
Caution When connecting a reset IC to the RESET pin, ensure that the IC is of the N-ch open drain output
type.
Table 6-1. Hardware Statuses After Reset
• RESET Input in Operation
• RESET Input During STANDBY Mode
Hardware
• Resetting by Internal POC Circuit in Operation • Resetting by the Internal POC Circuit During
• Resetting by Other FactorsNote 1
STANDBY Mode
PC (10 bits)
000H
0B
SP (1 bit)
Data
R0 = DP 000H
memory
R1-RF
Undefined
Undefined
0B
Previous status retained
Accumulator (A)
Status flag (F)
Carry flag (CY)
Timer (10 bits)
Port register
0B
000H
P0 FFH
P1 ×FHNote 2
Control register P3 03H
P4 26H
Notes 1. The following resets are available.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer’s overflow or underflow
2. Refers to the value by the KI pin status.
In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when
reset is released (when RESET pin changes from low level to high level, or POC is released due to
supply voltage startup).
Data Sheet U10454EJ6V0DS00
26
µPD6133, 6134
7. POC CIRCUIT (MASK OPTION)
The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller at the
time of battery replacement. If the applied circuit satisfies the following conditions, the POC circuit can be
incorporated by the mask option.
• High reliability is not required.
• Clock frequency fX = 300 to 500 kHz
• Operating ambient temperature TA = –20 to +70 ˚C
Cautions 1. The one-time PROM product (µPD61P34B) originally contains the POC circuit.
2. There are cases in which the POC circuit cannot detect a low power supply voltage of less
than 1 ms. Therefore, if the power supply voltage has become low for a period of less than
1 ms, the POC circuit may malfunction because it does not generate an internal reset signal.
3. Clock oscillation is stopped by the resonator due to low power supply voltage before the
POC circuit generates the internal reset signal. In this case, malfunction may result, for
example when the power supply voltage is recovered after the oscillation is stopped. This
type of phenomenon takes place because the POC circuit does not generate an internal reset
signal (because the power supply voltage recovers before the low power supply voltage is
detected) even though the clock has stopped. If, by any chance, a malfunction has taken
place, remove the battery for a short time and put it back. In most cases, normal operation
will be resumed.
4. If the applied circuit does not satisfy the conditions above, design the applied circuit in such
a manner that the reset takes effect without failure within the power supply voltage range
by means of an external reset circuit.
5. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to
KI3 when reset is released (when RESET pin changes from low level to high level, or POC
is released due to supply voltage startup).
Remarks 1. It is recommended that a POC circuit should be incorporated if applied circuits are infrared remote-
control transmitters for household appliances.
2. Even when a POC circuit is incorporated, the externally entered RESET input is valid with the OR
condition; therefore, the POC circuit and the RESET input can be used at the same time. However,
if the POC circuit detects a low power supply voltage, the RESET pin will be forced to low level;
therefore, use an N-ch open drain output or NPN open collector output for the external reset circuit.
Data Sheet U10454EJ6V0DS00
27
µPD6133, 6134
7.1 Functions of POC Circuit
The POC circuit has the following functions:
• Generates an internal reset signal when VDD ≤ VPOC.
• Cancels an internal reset signal when VDD > VPOC.
Here, VDD: power supply voltage, VPOC: POC-detected voltage.
V
DD
Operating ambient temperature T
A
= –20 to + 70°C
3.6 V
2.2 V
Clock frequency f = 300 to 500 kHz
X
V
POC
←POC-detected voltage VPOC = 0.9 to 2.2 VNote 3
0.8 V
0 V
→ t
Internal reset signal
Reset
OPERATING mode
↑
↑ Reset
Note 1
Note 2
Notes 1. In reality, there is the oscillation stabilization wait time until the circuit is switched to OPERATING
mode. The oscillation stabilization wait time is about 60/fX to 116/fX (when about 130 to 250 µs; fX
= 455 kHz).
2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen,
it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or
more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect.
3. The POC-detected voltage (VPOC) varies between 0.9 to 2.2 V; thus, the resetting may be canceled
at a power supply voltage smaller than the assured range (VDD = 1.8 to 3.6 V). However, as long as
the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage
becomes lower than the POC-detected voltage. Therefore, there is no malfunction occurring due to
the shortage of power supply voltage. However, malfunction for such reasons as the clock not
oscillating due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT).
7.2 Oscillation Check at Low Supply Voltage
A reliable resetting operation can be expected of the POC circuit if it satisfies the condition that the clock can
oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the
POC-detected voltage). Whether this condition is being met or not can be checked by measuring the oscillation
status on a product which actually contains a POC circuit, as follows.
<1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured.
<2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply
voltage VDD from 0 V (making sure to avoid VDD > 3.6V).
At first (during VDD < 0.9 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches
the POC-detected voltage (voltage somewhere between VPOC = 0.9 to 2.2 V), the voltage of the XOUT pin jumps to
about 0.5 VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If, by any
chance, the oscillation start voltage of the resonator is lower than the POC-detected voltage, the growing oscillation
of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC.
Data Sheet U10454EJ6V0DS00
28
µPD6133, 6134
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator consists of oscillators for ceramic resonators (fX = 300 kHz to 1 MHz).
Figure 8-1. System Clock
µ
PD6133, 6134
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops its oscillation when reset or in STOP mode.
Caution When using the system clock oscillator, wire area indicated by the dotted-line in the diagram
as follows to reduce the effects of the wiring capacitance, etc.
•
•
Make the wiring as short as possible.
Do not allow the wiring to intersect other signal lines. Do not wire close to lines through
which large fluctuating currents flow.
•
•
Make sure that the point where the oscillator capacitor is installed is always at the same
electric potential as the ground. Never earth with a ground pattern through which large
currents flow.
Do not extract signals from the oscillator.
Data Sheet U10454EJ6V0DS00
29
µPD6133, 6134
9. INSTRUCTION SET
9.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word.However, the machine language that
is output by the assembler is extended to 16 bits per word. As shown in the example below, the expansion is made
by inserting 3-bit extended bits (111) in two locations.
Figure 9-1. Example of Assembler Output (10 bits extended to 16 bits)
<1> In the case of “ANL A, @R0H”
1
1 0 1 0
1
0 0 0 0
1 1 1
1 0 1 0
1 1 1
1
0 0 0 0 = FAF0
1
Extended bits
Extended bits
<2> In the case of “OUT P0, #data8”
0
0 1 1 0
1
1 0 0 0
1 1 1
0 1 1 0
1 1 1
1
1 0 0 0 = E6F8
0
Extended bits
Extended bits
Data Sheet U10454EJ6V0DS00
30
µPD6133, 6134
9.2 Circuit Symbol Description
A
: Accumulator
ASR
addr
CY
: Address Stack Register
: Program memory address
: Carry flag
data4
data8
data10
F
: 4-bit immediate data
: 8-bit immediate data
: 10-bit immediate data
: Status flag
PC
: Program Counter
Pn
: Port register pair (n = 0, 1, 3, 4)
: Port register (low-order 4 bits)
: Port register (high-order 4 bits)
: Bit n of the program memory’s (n = 0-9)
: Register pair
P0n
P1n
ROMn
Rn
R0n
R1n
SP
: Data memory (General-purpose register; n = 0-F)
: Data memory (General-purpose register; n = 0-F)
: Stack Pointer
T
: Timer register
T0
: Timer register (low-order 4 bits)
: Timer register (high-order 4 bits)
: Content addressed with ×
T1
(×)
Data Sheet U10454EJ6V0DS00
31
µPD6133, 6134
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Operation Instructions
Instruction Code
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
1st Word 2nd Word 3rd Word
ANL
ORL
XRL
INC
A, R0n
FBEn
FAEn
FAF0
(A) ← (A) (Rmn) m = 0, 1 n = 0-F
CY ← A3 • Rmn3
1
1
A, R1n
A, @R0H
(A) ← (A) ((P13), (R0))7-4
CY ← A3 • ROM7
A, @R0L
FBF0
(A) ← (A) ((P13), (R0))3-0
CY ← A3 • ROM3
A, #data4 FBF1
data4
data4
data4
(A) ← (A) data4
2
1
CY ← A3 • data43
A, R0n
FDEn
FCEn
FCF0
(A) ← (A) (Rmn) m = 0, 1 n = 0-F
CY ← 0
A, R1n
A, @R0H
(A) ← (A) ((P13), (R0))7-4
CY ← 0
A, @R0L
FDF0
(A) ← (A) ((P13), (R0))3-0
CY ← 0
A, #data4 FDF1
(A) ← (A) data4
2
1
CY ← 0
A, R0n
F5En
F4En
F4F0
(A) ← (A) (Rmn) m = 0, 1 n = 0-F
CY ← A3 • Rmn3
A, R1n
A, @R0H
(A) ← (A) ((P13), (R0))7-4
CY ← A3 • ROM7
A, @R0L
F5F0
(A) ← (A) ((P13), (R0))3-0
CY ← A3 • ROM3
A, #data4 F5F1
(A) ← (A) data4
2
1
CY ← A3 • data43
A
F4F3
(A) ← (A) + 1
if (A) = 0 CY ← 1
else CY ← 1
RL
A
A
FCF3
FEF3
(An+1) ← (An), (A0) ← (A3)
CY ← A3
RLZ
if A = 0 reset
else (An+1) ← (An), (A0) ← (A3)
CY ← A3
Data Sheet U10454EJ6V0DS00
32
µPD6133, 6134
Input/output Instructions
Instruction Code
1st Word 2nd Word 3rd Word
Instruction Instruction
Mnemonic Operand
Operation
Length
Cycle
IN
A, P0n
A, P1n
P0n, A
P1n, A
A, P0n
A, P1n
A, P0n
A, P1n
A, P0n
A, P1n
FFF8 + n
FEF8 + n
E5F8 + n
E4F8 + n
FBF8 + n
FAF8 + n
FDF8 + n
FCF8 + n
F5F8 + n
F4F8 + n
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
1
1
OUT
ANL
ORL
XRL
(Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4
(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn3
(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn3
Instruction Code
1st Word 2nd Word 3rd Word
Pn, #data8 E6F8 + n data8
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
OUT
(Pn) ← data8
n = 0, 1, 3, 4
2
1
Remark Pn: P1n-P0n are dealt with in pairs.
Data Transfer Instruction
Instruction Code
Mnemonic Operand
Instruction Instruction
Length Cycle
Operation
m = 0, 1 n = 0-F
1st Word 2nd Word 3rd Word
MOV
A, R0n
FFEn
FEEn
FEF0
(A) ← (Rmn)
CY ← 0
1
1
A, R1n
A, @R0H
(A) ← ((P13), (R0))7-4
CY ← 0
A, @R0L
FFF0
(A) ← ((P13), (R0))7-4
CY ← 0
A, #data4 FFF1
data4
(A) ← data4
CY ← 0
2
1
R0n, A
R1n, A
E5En
E4En
(Rmn) ← (A)
m = 0, 1 n = 0-F
Instruction Code
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
1st Word 2nd Word 3rd Word
MOV
Rn, #data8 E6En
Rn, @R0 E7En
data8
—
—
—
(R1n-R0n) ← data8
n = 0-F
n = 1-F
2
1
1
(R1n-R0n) ← ((P13), (R0))
Remark Rn: R1n-R0n are dealt with in pairs.
Data Sheet U10454EJ6V0DS00
33
µPD6133, 6134
Branch Instructions
Instruction Code
1st Word 2nd Word 3rd Word
addr
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
JMP
JC
addr (Page 0) E8F1
addr (Page 1) E9F1
PC ← addr
2
1
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr (Page 0) ECF1
addr (Page 1) EAF1
addr (Page 0) EDF1
addr (Page 1) EBF1
addr (Page 0) EEF1
addr (Page 1) F0F1
addr (Page 0) EFF1
addr (Page 1) F1F1
if CY = 1 PC ← addr
else PC ← PC + 2
if CY = 0 PC ← addr
else PC ← PC + 2
if F = 1 PC ← addr
else PC ← PC + 2
if F = 0 PC ← addr
else PC ← PC + 2
JNC
JF
JNF
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Subroutine Instructions
Instruction Code
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
1st Word 2nd Word 3rd Word
CALL
RET
addr (Page 0) E6F2
E8F1
E9F1
addr
addr
SP ← SP + 1, ASR ← PC, PC ← addr
3
2
addr (Page 1) E6F2
E8F2
PC ← ASR, SP ← SP – 1
1
1
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Timer Operation Instructions
Instruction Code
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
1st Word 2nd Word 3rd Word
MOV
A, T0
A, T1
T0, A
T1, A
FFFF
FEFF
E5FF
F4FF
(A) ← (Tn)
CY ← 0
n = 0, 1
n = 0, 1
1
1
(Tn) ← (A)
(T) n ← 0
Instruction Code
Instruction Instruction
Length Cycle
Mnemonic Operand
Operation
1st Word 2nd Word 3rd Word
MOV
T, #data10 E6FF
data10
(T) ← data10
1
1
T, @R0
F4FF
(T) ← ((P13), (R0))
Data Sheet U10454EJ6V0DS00
34
µPD6133, 6134
Others
Instruction Code
Instruction Instruction
Mnemonic Operand
Operation
Standby mode
1st Word 2nd Word 3rd Word
Length
Cycle
HALT
STTS
#data4
#data4
E2F1
E3F1
data4
data4
2
1
1
if statuses match F ← 1
else F ← 0
R0n
E3En
FAF3
E0E0
if statuses match F ← 1
else F ← 0
n = 0-F
SCAF
NOP
if A = 0FH CY ← 1
else CY ← 0
PC ← PC + 1
Data Sheet U10454EJ6V0DS00
35
µPD6133, 6134
9.4 Accumulator Operation Instructions
ANL A, R0n
ANL A, R1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1
1
0
1 R
4
0 R
3
R
2
R
1
R
0
: 1
: (A) ← (A) (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the
accumulator.
ANL A, @R0H
ANL A, @R0L
<1> Instruction code
:
1 1 0 1 0/1 1 0 0 0 0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) ((P13), (R0))7-4 (in the case of ANL A, @R0H)
CY ← A3 • ROM7
(A) ← (A) ((P13), (R0))3-0 (in the case of ANL A, @R0L)
CY ← A3 • ROM3
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are ANDed and the results are entered in the accumulator.
If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect.
• Program memory (ROM) organization
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
H↓
L↓
Valid bits at the time of accumulator operation
ANL A, #data4
<1> Instruction code
:
1
0
1
0
0
0
1
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) data4
CY ← A3 • data43
The accumulator contents and the immediate data are ANDed and the results are entered in the
accumulator.
Data Sheet U10454EJ6V0DS00
36
µPD6133, 6134
ORL A, R0n
ORL A, R1n
<1> Instruction code
:
1
1
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (Rmn) m = 0, 1 n = 0 to F
CY ← 0
The accumulator contents and the register Rmn contents are ORed and the results are entered in the
accumulator.
ORL A, @R0H
ORL A, @R0L
<1> Instruction code
:
1 1 1 0 0/1 1 0 0 0 0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (P13), (R0))7-4 (in the case of ORL A, @R0H)
(A) ← (A) (P13), (R0))3-0 (in the case of ORL A, @R0L)
CY ← 0
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect.
ORL A, #data4
<1> Instruction code
:
1
0
1
0
1
0
0
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) data4
CY ← 0
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in
the accumulator.
XRL A, R0n
XRL A, R1n
<1> Instruction code
:
1
0
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
The accumulator contents and the register Rmn contents are ORed and the results are entered in the
accumulator.
Data Sheet U10454EJ6V0DS00
37
µPD6133, 6134
XRL A, @R0H
XRL A, @R0L
<1> Instruction code
: 1 0 1 0 0/1 1 0 0 0 0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (P13), (R0))7-4 (in the case of XRL A, @R0H)
CY ← A3 • ROM7
(A) ← (A) (P13), (R0))3-0 (in the case of XRL A, @R0L)
CY ← A3 • ROM3
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.
XRL A, #data4
<1> Instruction code
:
1
0
0
0
1
0
0
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) data4
CY ← A3 • data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in
the accumulator.
INC A
<1> Instruction code
:
1 0 1 0 0 1 0 0 1 1
<2> Cycle count
<3> Function
: 1
: (A) ← (A) + 1
if A = 0 CY ← 1
else CY ← 0
The accumulator contents are incremented (+1).
RL A
<1> Instruction code
:
1 1 1 0 0 1 0 0 1 1
<2> Cycle count
<3> Function
: 1
: (An + 1) ← (An), (A0) ← (A3)
CY ← A3
The accumulator contents are rotated anticlockwise bit by bit.
RLZ A
<1> Instruction code
:
1 1 1 1 0 1 0 0 1 1
<2> Cycle count
<3> Function
: 1
: if A = 0 reset
else (An + 1) ← (An), (A0) ←(A3)
CY ← A3
The accumulator contents are rotated anticlockwise bit by bit.
If A = 0H at the time of command execution, an internal reset takes effect.
Data Sheet U10454EJ6V0DS00
38
µPD6133, 6134
9.5 Input/Output Instructions
IN A, P0n
IN A, P1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1
1
1
1 P
4
1
1 P
2
P
1
P
0
: 1
: (A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
The port Pmn data is loaded (read) onto the accumulator.
OUT P0n, A
OUT P1n, A
<1> Instruction code
:
0
0
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count
<3> Function
: 1
: (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched.
ANL A, P0n
ANL A, P1n
<1> Instruction code
:
1
1
0
1 P
4
1
1 P
2
P1
P0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the
accumulator.
ORL A, P0n
ORL A, P1n
<1> Instruction code
:
1
1
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
The accumulator contents and the port Pmn contents are ORed and the results are entered in the
accumulator.
XRL A, P0n
XRL A, P1n
<1> Instruction code
:
1
0
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count
<3> Function
: 1
: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered
in the accumulator.
Data Sheet U10454EJ6V0DS00
39
µPD6133, 6134
OUT Pn, #data8
<1> Instruction code
:
:
0
0
0
1
1
0
1
1 P
2
P
1
P
0
d7
d6
d5
d4
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: (Pn) ← data8 n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n-P0n operating in pairs.
9.6 Data Transfer Instructions
MOV A, R0n
MOV A, R1n
<1> Instruction code
:
1
1
1
1 R
4
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: (A) ← (Rmn) m = 0, 1 n = 0 to F
CY ← 0
The register Rmn contents are transferred to the accumulator.
MOV A, @R0H
<1> Instruction code
:
1 1 1 1 0 1 0 0 0 0
<2> Cycle count
<3> Function
: 1
: (A) ← ((P13), (R0))7-4
CY ← 0
The high-order 4 bits (b7 b6 b5 b4) of the program memory specified with control register P13 and register
pair R10-R00 are transferred to the accumulator. b9 is ignored.
MOV A, @R0L
<1> Instruction code
:
1 1 1 1 1 1 0 0 0 0
<2> Cycle count
<3> Function
: 1
: (A) ← ((P13), (R0))3-0
CY ← 0
The low-order 4 bits (b3 b2 b1 b0) of the program memory specified with control register P13 and register
pair R10-R00 are transferred to the accumulator. b8 is ignored.
• Program memory (ROM) contents
@R
0
H
@R L
0
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
MOV A, #data4
<1> Instruction code
:
:
1
0
1
1
0
1
0
1
0
1
0
0 0 1
0
0 d
3
d
2
d1
d0
<2> Cycle count
<3> Function
: 1
: (A) ← data4
CY ← 0
The immediate data is transferred to the accumulator.
Data Sheet U10454EJ6V0DS00
40
µPD6133, 6134
MOV R0n, A
MOV R1n, A
<1> Instruction code
:
0
0
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: (Rmn) ← (A) m = 0, 1 n = 0 to F
The accumulator contents are transferred to register Rmn.
MOV Rn, #data8
<1> Instruction code
:
:
0
0
0
1
1
0
0 R
3
R
2
R
1
R
0
d7
d6
d5
d4
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: (R1n-R0n) ← data8 n = 0-F
The immediate data is transferred to the register. Using this instruction, registers operate as register
pairs.
The pair combinations are as follows:
R0 : R10 - R00
R1 : R11 - R01
:
RE : R1E - R0E
RF : R1F - R0F
Lower column
Higher column
MOV Rn, @R0
<1> Instruction code
:
0
0
1
1
1
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: (R1n-R0n) ← ((P13), R0)) n = 1 to F
The program memory contents specified with control register P13 and register pair R10-R00 are
transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following
state after the transfer to the register.
Program memory
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
→
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
@R0
R1n
R0n
The high-order 2 bits of the program memory address is specified with the control register (P13).
Data Sheet U10454EJ6V0DS00
41
µPD6133, 6134
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD6133 (ROM: 0.5K steps) : page 0
µPD6134 (ROM: 1K steps) : page 0
µPD61P34B (ROM: 1K steps): page 0
JMP addr
<1> Instruction code : page 0
0
1
0
0
0
1
0
0
0
1
; page 1 0 1 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 1
: PC ← addr
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
a0).
JC addr
<1> Instruction code : page 0
0
1
1
0
0
1
0
0
0
1
; page 1 0 1 0 1 0 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 1
: if CY = 1 PC ← addr
else PC ← PC + 2
If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a9 to a0).
JNC addr
<1> Instruction code : page 0
0
1
1
0
1
1
0
0
0
1
; page 1 0 1 0 1 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 1
: if CY = 0 PC ← addr
else PC ← PC + 2
If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a9 to a0).
JF addr
<1> Instruction code : page 0
0
1
1
1
0
1
0
0
0
1
; page 1 1 0 0 0 0 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 1
: if F = 1 PC ← addr
else PC ← PC + 2
If the status flag F is set (to 1), a jump is made to the address specified with addr (a9 to a0).
JNF addr
<1> Instruction code : page 0
0
1
1
1
1
1
0
0
0
1
; page 1 1 0 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 1
: if F = 0 PC ← addr
else PC ← PC + 2
If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a9 to a0).
Data Sheet U10454EJ6V0DS00
42
µPD6133, 6134
9.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD6133 (ROM: 0.5K steps) : page 0
µPD6134 (ROM: 1K steps) : page 0
µPD61P34B (ROM: 1K steps): page 0
CALL addr
<1> Instruction code
:
0
0
1
1
0
0
1
1
0
0
0
0
1 0
page 0
0
1
0
0
0
1
; page 1 0 1 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count
<3> Function
: 2
: SP ← SP + 1
ASR ← PC
PC ← addr
Increments (+1) the stack pointer value and saves the program counter value in the address stack
register. Then, enters the address specified with the operand addr (a9 to a0) into the program counter.
If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect.
RET
<1> Instruction code
<2> Cycle count
<3> Function
: 0 1 0 0 0 1 0 0 1 0
: 1
: PC ← ASR
SP ← SP – 1
Restores the value saved in the address stack register to the program counter. Then, decrements
(–1) the stack pointer.
If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect.
Data Sheet U10454EJ6V0DS00
43
µPD6133, 6134
9.9 Timer Operation Instructions
MOV A, T0
MOV A, T1
<1> Instruction code
<2> Cycle count
<3> Function
: 1 1 1 1 0/1 1 1 1 1 1
: 1
: (A) ← (Tn) n = 0, 1
CY ← 0
The timer Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds
to (t5, t4, t3, t2).
T
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
T1
T0
Can be set with
↓
MOV T, #data10
MOV T, @R0
MOV T0, A
MOV T1, A
<1> Instruction code
<2> Cycle count
<3> Function
: 0 0 1 0 0/1 1 1 1 1 1
: 1
: (Tn) ← (A) n = 0, 1
The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0
corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0;
if data is transferred to T0, t0 becomes 0.
MOV T, #data10
<1> Instruction code
:
0 0 1 1 0 1 1 1 1 1
t1
t9
t8
t7
t6
t0
t5
t4
t3
t2
<2> Cycle count
<3> Function
: 1
: (T) ← data10
The immediate data is transferred to the timer register T (t9-t0).
Remark The timer time is set with
(set value + 1) × 8/fX (or 16/fX).
Data Sheet U10454EJ6V0DS00
44
µPD6133, 6134
MOV T, @R0
<1> Instruction code
:
0 0 1 1 1 1 1 1 1 1
<2> Cycle count
<3> Function
: 1
: (T) ← ((P13), (R0))
Transfers the program memory contents to the timer register T (t9 to t0) specified with the control register
P13 and the register pair R10-R00.
The program memory, which consists of 10 bits, is placed in the following state after the transfer to the
register.
Timer
Program memory
T
t
1
t
9
t
8
t
7
t
6
t
0
t
5
t
4
t
3
t
2
→
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
@R
0
T1
T0
The high-order 2 bits of the program memory address are specified with the control register (P13).
Caution When setting a timer value in the program memory, ensure to use the DT directive.
9.10 Others
HALT #data4
<1> Instruction code
:
:
0
0
0
0
0
0
1
0
0
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: Sandby mode
Places the CPU in standby mode.
The condition for having the standby mode (HALT/STOP mode) canceled is specified with the immediate
data.
STTS R0n
<1> Instruction code :
0
0
0
1
1
0 R
3
R2
R1
R0
<2> Cycle count
<3> Function
: 1
: if statuses match F ← 1
else F ← 0 n = 0 to F
Compares the S0, S1, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one of the
statuses coincides with the bits that have been set, the status flag F is set (to 1).
If none of them coincide, the status flag F is cleared (to 0).
Data Sheet U10454EJ6V0DS00
45
µPD6133, 6134
STTS #data4
<1> Instruction code
:
:
0
0
0
0
0
0
1
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count
<3> Function
: 1
: if statuses match F ← 1
else F ← 0
Compares the S0, S1, KI/O, KI, and TIMER statuses with the immediate data contents. If at least one
of the statuses coincides with the bits that have been set, the status flag F is set (to 1).
If none of them coincide, the status flag F is cleared (to 0).
SCAF (Set Carry If ACC = FH)
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 0 1 0 1 0 0 1 1
: 1
: if A = 0FH CY ← 1
else CY ← 0
Sets the carry flag CY (to 1) if the accumulator contents are FH.
The accumulator values after executing the SCAF instruction are as follows:
Accumulator Value
Carry Flag
Before execution
After execution
×××0
××01
×011
0111
1111
0000
0 (clear)
0 (clear)
0 (clear)
0 (clear)
1 (set)
0001
0011
0111
1111
Remark ×: don’t care
NOP
<1> Instruction code
:
0 0 0 0 0 0 0 0 0 0
<2> Cycle count
<3> Function
No operation
: 1
: PC ← PC + 1
Data Sheet U10454EJ6V0DS00
46
µPD6133, 6134
10. ASSEMBLER RESERVED WORDS
10.1 Mask Option Directives
When creating the µPD6133 program, it is necessary to use a mask option directive in the assembler’s source
program to specify a mask option.
10.1.1 OPTION and ENDOP directives
From the OPTION directive on to the ENDOP directive are called the mask option definition block. The format
of the mask option definition block is as follows:
Format
Symbol field
[Label:]
Mnemonic field
Operand field
Comment field
[; Comment]
OPTION
:
:
ENDOP
10.1.2 Mask option definition directives
The directives that can be used in the mask option definition block are listed in Table 10-1.
An example of the mask option definition is shown below.
Example
Symbol field
Mnemonic field
OPTION
Operand field
Comment field
USEPOC
ENDOP
; POC circuit incorporated
Table 10-1. List of Mask Option Definition Directives
PRO File
Name
POC
Mask Option Definition Directive
Address value
2044H
Data value
USEPOC
01
(POC circuit incorporated)
NOUSEPOC
00
(Without POC circuit)
Data Sheet U10454EJ6V0DS00
47
µPD6133, 6134
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 ˚C)
Parameter
Power supply voltage
Input voltage
Symbol
VDD
Test Conditions
Rating
Unit
V
–0.3 to +5.0
VI
KI/O, KI, S0, S1, RESET
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Note
High-level output current
IOH
REM
Peak value
rms
–30
–20
–7.5
–5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
˚C
LED
Peak value
rms
One KI/O pin
Peak value
rms
–13.5
–9
Total of LED and KI/O pins
Peak value
rms
–18
–12
7.5
Note
Low-level output current
IOL
REM
LED
Peak value
rms
5
Peak value
rms
7.5
5
Operating ambient
temperature
TA
–40 to +85
Storage temperature
Tstg
–65 to +150
˚C
Note Work out the rms with: [rms] = [Peak value] × √Duty.
Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momen-
tarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical
damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the
these ratings are not exceeded during use of the product.
Recommended Power Supply Voltage Range (TA = –40 to +85 ˚C)
Parameter
Symbol
Test Conditions
fX = 300 to 500 kHz
MIN.
1.8
TYP.
3.0
MAX.
3.6
Unit
V
Power supply voltage
VDD
fX = 500 kHz to 1 MHz
2.2
3.0
3.6
V
When using the POC circuit (mask option)
TA = –20 to +70 ˚C
2.2
3.0
3.6
V
fX = 300 to 500 kHz
Data Sheet U10454EJ6V0DS00
48
µPD6133, 6134
DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 3.6 V)
Parameter
Symbol
VIH1
Test Conditions
MIN.
TYP.
MAX.
VDD
Unit
V
High-level input voltage
RESET
KI/O
0.8 VDD
VIH2
0.65 VDD
VDD
V
VIH3
KI, S0, S1
RESET
KI/O
0.65 VDD
VDD
V
Low-level input voltage
VIL1
0
0
0
0.2 VDD
0.3 VDD
0.15 VDD
3
V
VIL2
V
VIL3
KI, S0, S1
KI
V
High-level input
leakage current
ILIH1
µA
VI = VDD, pull-down resistor not incorporated
ILIH2
S0, S1
3
µA
VI = VDD, pull-down resistor not incorporated
Low-level input leakage
current
ILIL1
ILIL2
ILIL3
KI
VI = 0 V
VI = 0 V
–3
–3
–3
µA
µA
µA
V
KI/O
S0, S1 VI = 0 V
High-level output voltage VOH1
REM, LED, KI/O
IOH = –0.3 mA
0.8 VDD
Low-level output voltage
VOL1
VOL2
REM, LED
KI/O
IOL = 0.3 mA
0.3
0.4
V
IOL = 15 µA
V
High-level output current IOH1
REM
KI/O
VDD = 3.0 V, VOH = 1.0 V
VDD = 3.0 V, VOH = 2.2 V
VDD = 3.0 V, VOL = 0.4 V
VDD = 3.0 V, VOL = 2.2 V
–5
–2.5
30
–9
–5
mA
mA
µA
µA
kΩ
kΩ
kΩ
kΩ
V
IOH2
Low-level output current
Built-in pull-up resistor
IOL1
R1
KI/O
70
100
25
220
50
RESET
100
15
Built-in pull-down resistor R2
RESET
2.5
75
5
R3
R4
KI, S0, S1
KI/O
150
250
300
500
3.6
130
0.9
Data hold power supply
voltage
VDDDR
In STOP mode
Supply currentNote
IDD1
IDD2
IDD3
OPERATING fX = 1.0 MHz, VDD = 3 V ± 10 %
0.4
0.35
0.35
0.3
0.8
0.7
0.7
0.6
8.0
1.0
mA
mA
mA
mA
µA
mode
fX = 455 kHz, VDD = 3 V ± 10 %
fX = 1.0 MHz, VDD = 3 V ± 10 %
fX = 455 kHz, VDD = 3 V ± 10 %
VDD = 3 V ± 10 %
HALT mode
STOP mode
1.0
VDD = 3 V ± 10 %, TA = 25 ˚C
0.1
µA
Note The POC circuit current and the current flowing in the built-in pull-up resistor are not included.
Data Sheet U10454EJ6V0DS00
49
µPD6133, 6134
AC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 3.6 V)
Parameter
Symbol
Test Conditions
VDD = 2.2 to 3.6 V
MIN.
7.9
TYP.
MAX.
27
Unit
µs
µs
µs
µs
µs
µs
Command execution time tCY
15.9
10
27
KI, S0, S1 high-level width tH
When releasing
Standby mode
in HALT mode
in STOP mode
10
Note
10
RESET low-level width
tRSL
Note 10 + 36/fX + oscillation growth time
Remark tCY = 8/fX (fX: System clock oscillator frequency)
POC Circuit (mask optionNote 1) (TA = –20 to +70 ˚C)
Parameter
POC-detected voltageNote 2 VPOC
POC circuit current
Symbol
Test Conditions
MIN.
0.9
TYP.
1.6
MAX.
2.2
Unit
V
IPOC
0.9
1.0
µA
Notes 1. Operates effectively under the conditions of fX = 300 to 500 kHz.
2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal
reset is released.
From the time of VPOC ≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the
period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.
Data Sheet U10454EJ6V0DS00
50
µPD6133, 6134
System Clock Oscillator Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 3.6 V)
Parameter
Oscillator frequency
(ceramic resonator)
Symbol
Test Conditions
MIN.
300
300
TYP.
455
MAX.
500
Unit
kHz
kHz
fX
VDD = 2.2 to 3.6 V
455
1000
Recommended Ceramic Resonator (TA = –40 to +85 ˚C)
Power Supply
Voltage [V]Note
Manufacturer
Recommended Constant
Part Number
Remark
(Order Disregarded)
C1 [pF] C1 [pF] Rd [kΩ]
MIN.
1.8
MAX.
3.6
Murata Mfg. Co., Ltd CSB455E
CSB600P
150
150
100
220
220
100
100
220
220
220
470
470
470
150
150
100
220
220
100
100
220
220
220
470
470
470
0
0
0
0
0
0
0
0
0
0
0
0
0
2.2
2.2
1.8
1.8
2.2
2.2
1.8
1.8
1.8
1.8
1.8
1.8
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
CSB910J
Kyocera Corp.
KBR-455BK
KBR-455BY
KBR-1000F
KBR-1000Y
FCR400K3
TDK Corp.
FCR455K3
FCR500K3
Matsushita
Electronics
EFOA440K06B
EFOA455K06B
Components Co., Ltd. EFOA480K06B
Note When a POC circuit (mask option) is not incorporated
An external circuit example
X
IN
X
OUT
Rd
C1
C2
Data Sheet U10454EJ6V0DS00
51
µPD6133, 6134
12. CHARACTERISTIC CURVE (REFERENCE VALUES) (common to µPD6133 and 6134)
I
DD vs VDD
(
f
X
= 455 kHz)
I
DD vs VDD
(fX = 1 MHz)
(TA
= 25 °C , VDD = 1.8 to 3.6 V)
(TA = 25 °C , VDD = 2.2 to 3.6 V)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
OPERATING mode
OPERATING mode
HALT mode
HALT mode
0.1
0
0.1
0
1
1.8 2
3
3.6
4
1
2 2.2
3
3.6
4
Power supply voltage VDD [V]
Power supply voltage VDD [V]
I
OL vs VOL (REM, LED)
(T = 25 °C, VDD = 3.0 V)
I
OH vs VOH (REM)
(T = 25 °C , VDD = 3.0 V)
A
A
10
9
8
7
6
5
4
3
2
1
– 20
– 18
– 16
– 14
– 12
– 10
– 8
– 6
– 4
– 2
0
0
0.6
1.2
1.8
2.4
3
V
DD
V
DD
–
0.6 VDD
–
1.2 VDD
–
1.8 VDD
–
2.4
V
DD
– 3
Low-level output voltage VOL [V]
High-level output voltage VOH [V]
I
OH vs VOH (LED)
(T = 25 °C , VDD = 3.0 V)
A
– 10
– 9
– 8
– 7
– 6
– 5
– 4
– 3
– 2
– 1
0
V
DD
V
DD
–
0.6 VDD
–
1.2 VDD
–
1.8 VDD
–
2.4
V
DD
– 3
High-level output voltage VOH [V]
Data Sheet U10454EJ6V0DS00
52
µPD6133, 6134
I
OL vs VOL
(
KI/O
)
I
OH vs VOH
(KI/O)
(T
A
= 25 °C, VDD = 3.0 V)
(TA = 25 °C, VDD = 3.0 V)
– 15
– 14
– 13
– 12
– 11
– 10
– 9
– 8
– 7
– 6
– 5
320
280
240
200
160
120
80
µ
– 4
– 3
– 2
– 1
0
40
0
0.6
1.2
1.8
2.4
3
VDD
V
DD
–
0.6 VDD
–
1.2 VDD
–
1.8 VDD
–
2.4
V
DD
– 3
Low-level output voltage VOL [V]
High-level output voltage VOH [V]
Data Sheet U10454EJ6V0DS00
53
µPD6133, 6134
13. APPLIED CIRCUIT EXAMPLE
Example of Application to System
· Remote-control transmitter (40 keys; mode selection switch accommodated)
K
K
S
S
I/O6
I/O7
0
K
K
K
K
K
K
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
+
1/LED
REM
VDD
XOUT
XIN
Mode selection switch
K
K
K
K
I3
I2
I1
I0
+
GND
RESET
Key matrix
8 × 5 = 40 keys
· Remote-control transmitter (48 keys accommodated)
K
K
S
S
I/O6
I/O7
0
K
K
K
K
K
K
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
+
1/LED
REM
V
X
X
DD
OUT
IN
K
K
K
K
I3
I2
I1
I0
+
GND
RESET
Key matrix
8 × 6 = 48 keys
Remark When the POC circuit of the mask option is used effectively, it is not necessary to connect the capacitor
enclosed in the dotted lines.
Data Sheet U10454EJ6V0DS00
54
µPD6133, 6134
14. PACKAGE DRAWINGS
20 PIN PLASTIC SOP (300 mil)
20
11
detail of lead end
P
1
10
A
H
I
J
G
L
C
B
K
D
M
N
M
E
F
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
12.7±0.3
0.500±0.012
0.031 MAX.
0.050 (T.P.)
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
+0.003
0.017
D
–0.07
–0.004
E
F
0.1±0.1
0.004±0.004
0.071 MAX.
0.061±0.002
0.303±0.012
1.8 MAX.
1.55±0.05
7.7±0.3
G
H
+0.009
0.220
I
5.6±0.2
1.1
–0.008
J
K
0.043
+0.003
0.009
+0.08
0.22
–0.004
–0.07
+0.008
0.024
L
0.6±0.2
–0.009
M
N
0.12
0.10
0.005
0.004
+7°
3°
+7°
3°
P
–3°
–3°
P20GM-50-300B, C-5
Remark The dimensions and materials of the ES model are the same as those of mass production model.
Data Sheet U10454EJ6V0DS00
55
µPD6133, 6134
20 PIN PLASTIC SSOP (300 mil)
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
I
J
S
N
S
K
C
B
M
D
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
A
B
C
6.65±0.15
0.475 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1±0.05
1.3±0.1
1.2
8.1±0.2
6.1±0.2
1.0±0.2
J
K
L
0.17±0.03
0.5
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6±0.15
S20MC-65-5A4-1
Remark The dimensions and materials of the ES model are the same as those of mass production model.
Data Sheet U10454EJ6V0DS00
56
µPD6133, 6134
15. RECOMMENDED SOLDERING CONDITIONS
Carry out the soldered packaging of this product under the following recommended conditions.
For details of the soldering conditions, refer to information material Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than the recommended conditions, please consult one of our NEC
sales representatives.
Table 15-1. Soldering Conditions for Surface-Mount Type
(1) µPD6133GS-×××: 20-pin plastic SOP (300 mil)
µPD6134GS-×××: 20-pin plastic SOP (300 mil)
Recommended
Soldering Method
Infrared reflow
Soldering Condition
Condition Symbol
IR35-00-2
Package peak temperature: 235 °C; time: 30 secs. max. (210 °C min.);
count: twice max.
VPS
Package peak temperature: 215 °C; time: 40 secs. max. (200 °C min.);
VP15-00-2
WS60-00-1
—
count: twice max.
Wave soldering
Partial heating
Solder bath temperature: 260 °C max.; time: 10 secs. max.; count: once;
Preliminary heat temperature: 120 °C max. (Package surface temperature)
Pin temperature: 300 ˚C or less ; time: 3 secs. max. (for each side of the device)
Caution Using more than one soldering method should be avoided (except in the case of partial heating).
(2) µPD6134MC-×××-5A4: 20-pin plastic SSOP (300 mil)
Recommended
Soldering Method
Infrared reflow
Soldering Condition
Condition Symbol
IR35-00-3
Package peak temperature: 235 °C; time: 30 secs. max. (210 °C min.);
count: three times max.
VPS
Package peak temperature: 215 °C; time: 40 secs. max. (200 °C min.);
VP15-00-3
WS60-00-1
—
count: three times max.
Wave soldering
Partial heating
Solder bath temperature: 260 °C max.; time: 10 secs. max.; count: once;
Preliminary heat temperature: 120 °C max. (Package surface temperature)
Pin temperature: 300 ˚C or less ; time: 3 secs. max. (for each side of the device)
Caution Using more than one soldering method should be avoided (except in the case of partial heating).
Data Sheet U10454EJ6V0DS00
57
µPD6133, 6134
APPENDIX A. DEVELOPMENT TOOLS
An emulator is provided for the µPD6133.
Hardware
• Emulator (EB-6133Note
It is used to emulate the µPD6133.
)
Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg.
Co., Ltd. (044-822-3813).
Software
• Assembler (AS6133)
• This is a development tool for remote control transmitter software.
Part Number List of AS6133
Host Machine
PC-9800 series
OS
Supply Medium
3.5-inch 2HD
Part Number
MS-DOSTM (Ver. 5.0 to Ver. 6.2)
µS5A13AS6133
(CPU: 80386 or more)
IBM PC/ATTM compatible
MS-DOS (Ver. 6.0 to Ver. 6.22)
PC DOSTM (Ver. 6.1 to Ver. 6.3)
3.5-inch 2HC
µS7B13AS6133
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this
software.
Data Sheet U10454EJ6V0DS00
58
µPD6133, 6134
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD6133 SUBSERIES AND OTHER
SUBSERIES
Item
µPD6133
512 × 10 bits
32 × 4 bits
µPD6134
µPD6600A
512 × 10 bits
32 × 5 bits
µPD6124A
ROM capacity
RAM capacity
Stack
1002 × 10 bits
1002 × 10 bits
1 level (multiplexed with RF of RAM)
3 levels (multiplexed with RAM)
8 × 4 = 32 keys
Key matrix
8 × 6 = 48 keys
S0 (S-IN) input
Read by P01 register (with function to
release standby mode)
Read by left shift instruction
S1/LED (S-OUT)
Clock frequency
I/O (with function to release standby mode) Output
Ceramic oscillation
Ceramic oscillation
• fX = 300 kHz to 1 MHz
• fX = 300 to 500 kHz
(with POC circuit)
• fX = 400 to 500 kHz
Timer
Clock
fX/8, fX/16
fX/8
Count start
Frequency
Writing count value
Writing count value and P1 register value
• fX/8, fX/12
Carrier
• fX, fX/8, fX/12 (timer clock: fX/8)
• fX/2, fX/16, fX/24 (timer clock: fX/16)
• No carrier
Output start
Synchronized with timer
8 µs (fX = 1 MHz)
None
Not synchronized with timer
16 µs (fX = 500 kHz)
Provided
Instruction execution time
Relative branch instruction
Left shift instrucion
None
Provided
“MOV Rn, @R0” instrucion
n = 1 to F
n = 0 to F
Standby mode
HALT mode for timer only.
STOP mode for only releasing KI
(KI/O high-level output or KI/O0 high-level
output)
HALT/STOP mode set by P1 register
value
(HALT instruction)
Relation between HALT
instruction execution and
status flag (F)
HALT instruction not executed when F = 1 HALT instrucion executed regardless of
status of F
Reset function by charging/
discharging capacitor
None
Provided
POC circuit
Mask option
Provided (low-voltage detection circuit)
Low level output to RESET pin on detection Low level ouput to S-OUT pin on detection
Mask option
POC circuit only
• Pull-down resistor
• Variable duty
(Circuits other than POC circuit are set
by software.)
• Hang-up detection
Supply voltage
VDD = 1.8 to 3.6 V
• VDD = 2.2 to 3.6 V
• VDD = 2.2 to 5.5 V
Operating temperature
• TA = –40 to +85 °C
• TA = –20 to +70 °C
• TA = –20 to +70 °C (with POC circuit)
Package
• 20-pin plastic
SOP
• 20-pin plastic SOP • 20-pin plastic SOC
• 20-pin plastic SSOP • 20-pin plastic shrink DIP
One-time PROM product
µPD61P34B
µPD61P24
Data Sheet U10454EJ6V0DS00
59
µPD6133, 6134
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT
(in the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC.
(1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)
REM output
58.5 to 76.5 ms
< 1 >
< 2 >
108 ms
108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can
be reduced by sending the reader code and the stop bit from the second time.
(2) Enlarged waveform of <1>
< 3 >
REM output
9 ms
4.5 ms
Custom code
8 bits
Custom code'
8 bits
Data code
8 bits
Data code
8 bits
Stop bit
1 bit
13.5 ms
Leader code
18 to 36 ms
58.5 to 76.5 ms
27 ms
(3) Enlarged waveform of <3>
REM output
9 ms
4.5 ms
0.56 ms
13.5 ms
1.125 ms 2.25 ms
0
1
1
0
0
(4) Enlarged waveform of <2>
REM output
9 ms
2.25 ms
11.25 ms
Leader code
0.56 ms
Stop bit
Data Sheet U10454EJ6V0DS00
60
µPD6133, 6134
(5) Carrier waveform (Enlarged waveform of each code’s high period)
REM output
8.77 µs
26.3 µs
9 ms or 0.56 ms
Carrier frequency : 38 kHz
(6) Bit array of each code
C0
C1
C2
C3
C4
C5
C6
C7
C0' C1' C2' C3' C4' C5' C6' C7' D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
or or or or or or or or
Co
C1
C2
C3
C4
C5
C6
C7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission
format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the
16-bit custom codes (Custom Code, Custom Code’) and the 16-bit data codes (Data Code,
Data Code) but also check to make sure that no signals are present.
Data Sheet U10454EJ6V0DS00
61
µPD6133, 6134
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Data Sheet U10454EJ6V0DS00
62
µPD6133, 6134
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U10454EJ6V0DS00
63
µPD6133, 6134
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corp.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
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