UPD703102GJ-33-XXX-UEN-A [RENESAS]
IC,MICROCONTROLLER,32-BIT,V850 CPU,CMOS,QFP,144PIN,PLASTIC;
| 型号： | UPD703102GJ-33-XXX-UEN-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,MICROCONTROLLER,32-BIT,V850 CPU,CMOS,QFP,144PIN,PLASTIC 时钟 微控制器 外围集成电路 |
| 文件： | 总82页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD703100-33, 703100-40, 703101-33, 703102-33
V850E/MS1
32-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703101-33 and µPD703102-33 are members of the V850 Series of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU
core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
The µPD703100-33 and µPD703100-40 are ROMless versions of the µPD703101-33 and µPD703102-33 products.
The µPD703100A-33, µPD703100A-40, µPD703101A-33, and µPD703102A-33 are also available as products
having a 3.3 V power supply for external pins.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS1 User’s Manual Hardware:
U12688E
V850E/MS1, V850E/MS2 User’s Manual Architecture: U12197E
FEATURES
•
•
Number of instructions: 81
Minimum instruction execution time 25 ns (@ 40 MHz operation) ····· µPD703100-40
30 ns (@ 33 MHz operation) ····· µPD703100-33, 703101-33, 703102-33
•
•
•
General-purpose registers 32 bits × 32
Instruction set optimized for control applications
Internal memory ROM: None (µPD703100-33, 703100-40),
96 KB (µPD703101-33),
128 KB (µPD703102-33)
RAM : 4 KB
•
•
•
•
•
•
•
Advanced on-chip interrupt controller
Real-time pulse unit suitable for control operations
Powerful serial interface (on-chip dedicated baud rate generator)
On-chip clock generator
10-bit resolution A/D converter: 8 channels
DMA controller: 4 channels
Power saving functions
APPLICATIONS
•
•
•
•
Office automation equipment: printers, facsimile machines, PPCs, etc.
Multimedia equipment: digital still cameras, video printers, etc.
Consumer equipment: single-lens reflex cameras, etc.
Industrial equipment: motor controllers, NC machine tools, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U13995EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark shows major revised points.
1999
µPD703100-33, 703100-40, 703101-33, 703102-33
ORDERING INFORMATION
Maximum Operating
Part Number
Package
Internal ROM
Frequency
µPD703100GJ-33-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
33 MHz
None
None
µPD703100GJ-33-UEN-A
µPD703100GJ-40-UEN
33 MHz
40 MHz
40 MHz
33 MHz
33 MHz
33 MHz
33 MHz
None
µPD703100GJ-40-UEN-A
µPD703101GJ-33-xxx-UEN
µPD703101GJ-33-xxx-UEN-A
µPD703102GJ-33-xxx-UEN
µPD703102GJ-33-xxx-UEN-A
None
96 KB
96 KB
128 KB
128 KB
Remarks 1. xxx indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
2
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
PIN CONFIGURATION (TOP VIEW)
144-pin plastic LQFP (fine pitch) (20 × 20)
•
•
•
•
µPD703100GJ-33-UEN
µPD703100GJ-33-UEN-A
µPD703100GJ-40-UEN
µPD703100GJ-40-UEN-A
•
•
•
•
µPD703101GJ-33-xxx-UEN
µPD703101GJ-33-xxx-UEN-A
µPD703102GJ-33-xxx-UEN
µPD703102GJ-33-xxx-UEN-A
INTP103/ DMARQ3/ P07
INTP102/ DMARQ2/ P06
INTP101/ DMARQ1/ P05
INTP100/ DMARQ0/ P04
TI10/ P03
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
A16/ P60
A17/ P61
A18/ P62
A19/ P63
A20/ P64
A21/ P65
A22/ P66
A23/ P67
TCLR10/ P02
TO101/ P01
TO100/ P00
VSS
9
HVDD
INTP113/ DMAAK3/ P17
INTP112/ DMAAK2/ P16
INTP111/ DMAAK1/ P15
INTP110/ DMAAK0/ P14
TI11/ P13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CS0/ RAS0/ P80
CS1/ RAS1/ P81
CS2/ RAS2/ P82
CS3/ RAS3/ P83
CS4/ RAS4/ IOWR/ P84
CS5/ RAS5/ IORD/ P85
CS6/ RAS6/ P86
CS7/ RAS7/ P87
LCAS/ LWR/ P90
UCAS/ UWR/ P91
RD/ P92
WE/ P93
BCYST/ P94
OE/ P95
HLDAK/ P96
HLDRQ/ P97
VSS
REFRQ/ PX5
WAIT/ PX6
CLKOUT/ PX7
TO150/ P120
TO151/ P121
TCLR15/ P122
TI15/ P123
INTP150/ P124
INTP151/ P125
INTP152/ P126
TCLR11/ P12
TO111/ P11
TO110/ P10
INTP123/ TC3/ P107
INTP122/ TC2/ P106
INTP121/ TC1/ P105
INTP120/ TC0/ P104
TI12/ P103
TCLR12/ P102
TO121/ P101
TO120/ P100
ANI7/ P77
ANI6/ P76
ANI5/ P75
ANI4/ P74
ANI3/ P73
ANI2/ P72
ANI1/ P71
ANI0/ P70
AVDD
AVSS
AVREF
74
73
3
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
PIN NAMES
A0 to A23:
ADTRG:
ANI0 to ANI7:
AVDD:
Address Bus
P50 to P57:
P60 to P67:
P70 to P77:
P80 to P87:
P90 to P97:
P100 to P107:
P110 to P117:
Port 5
AD Trigger Input
Port 6
Analog Input
Port 7
Analog Power Supply
Analog Reference Voltage
Analog Ground
Port 8
AVREF:
Port 9
AVSS:
Port 10
BCYST:
Bus Cycle Start Timing
Port 11
CKSEL
:
Clock Generator Operating Mode Select P120 to P127:
Port 12
CLKOUT:
CS0 to CS7:
CVDD:
Clock Output
PA0 to PA7:
PB0 to PB7:
PX5 to PX7:
RAS0 to RAS7:
RD:
Port A
Chip Select
Port B
Clock Generator Power Supply
Clock Generator Ground
Data Bus
Port X
CVSS:
Row Address Strobe
Read
D0 to D15:
DMAAK0 to DMAAK3: DMA Acknowledge
DMARQ0 to DMARQ3: DMA Request
REFRQ:
Refresh Request
Reset
RESET:
HLDAK:
HLDRQ:
HVDD:
Hold Acknowledge
RXD0, RXD1:
SCK0 to SCK3:
SI0 to SI3:
SO0 to SO3:
TC0 to TC3:
Receive Data
Serial Clock
Serial Input
Serial Output
Terminal Count Signal
Hold Request
Power Supply for External Pins
INTP100 to INTP103, : Interrupt Request from Peripherals
INTP110 to INTP113,
INTP120 to INTP123,
TCLR10 to TCLR15: Timer Clear
INTP130 to INTP133,
TI10 to TI15:
TO100, TO101, :
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
TXD0, TXD1:
UCAS:
Timer Input
INTP140 to INTP143,
Timer Output
INTP150 to INTP153
IORD:
IOWR:
LCAS:
LWR:
I/O Read Strobe
I/O Write Strobe
Lower Column Address Strobe
Lower Write Strobe
MODE0 to MODE3: Mode
Transmit Data
NMI:
Non-Maskable Interrupt Request
Upper Column Address Strobe
Upper Write Strobe
Power Supply for Internal Unit
Ground
OE:
Output Enable
Port 0
UWR:
P00 to P07:
P10 to P17:
P20 to P27:
P30 to P37:
P40 to P47:
VDD:
Port 1
VSS:
Port 2
WAIT:
Wait
Port 3
WE:
Write Enable
Port 4
X1, X2:
Crystal
4
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
INTERNAL BLOCK DIAGRAM
NMI
HLDRQ
CPU
BCU
ROM
HLDAK
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153
INTC
CS0 to CS7/RAS0 to RAS7
IOWR
Instruction queue
PC
IORD
Multiplier
(32 × 32 → 64)
Note
DRAMC
REFRQ
BCYST
WE
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
RD
Barrel
shifter
OE
Page ROM
controller
RPU
RAM
4 KB
System registers
UWR/UCAS
LWR/LCAS
WAIT
General-purpose
registers
(32 bits × 32)
TCLR10 to TCLR15
TI10 to TI15
ALU
A0 to A23
D0 to D15
DMARQ0 to DMARQ3
DMAAK0 to DMARQ3
TC0 to TC3
DMAC
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
UART1/CSI1
BRG1
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
CLKOUT
X1
Port
CG
X2
CVDD
CVSS
SO2
SI2
CSI2
SCK2
MODE0 to MODE3
RESET
BRG2
System
controller
SO3
SI3
CSI3
SCK3
V
DD
SS
ANI0 to ANI7
V
AVREF
AVSS
ADC
AVDD
ADTRG
Note µPD703100-33, 703100-40: None
µPD703101-33: 96 KB (mask ROM)
µPD703102-33: 128 KB (mask ROM)
5
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
CONTENTS
1. DIFFERENCES AMONG PRODUCTS ..........................................................................................
7
2. PIN FUNCTIONS.............................................................................................................................
2.1 Port Pins .................................................................................................................................
8
8
2.2 Non-Port Pins......................................................................................................................... 11
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 15
3. ELECTRICAL SPECIFICATIONS................................................................................................... 18
4. PACKAGE DRAWING .................................................................................................................... 76
5. RECOMMENDED SOLDERING CONDITIONS............................................................................. 77
6
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
1. DIFFERENCES AMONG PRODUCTS
µPD703100
-40 A-33
µPD703101
-33 A-33
µPD703102
-33 A-33
µPD70F3102
Product Name
Item
-33
A-40
-33
A-33
Internal ROM
None
96 KB
128 KB
(mask ROM)
128 KB
(mask ROM)
(flash memory)
Maximum operating
frequency
33 MHz 40 MHz 33 MHz 40 MHz
33 MHz
HVDD
4.5 to 5.5 V
3.0 to 3.6 V
4.5 to
5.5 V
3.0 to
3.6 V
4.5 to
5.5 V
3.0 to
3.6 V
4.5 to
5.5 V
3.0 to
3.6 V
Operation mode
Single-chip
mode 0, 1
None
None
Provided
Flash memory
programming
mode
Provided
Flash memory
None
Provided (VPP)
programming pin
Electrical
Power consumptions differ (refer to the data sheet of each product).
specifications
Package
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
Others
Noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout.
Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20 × 20)
157FBGA: 157-pin plastic FBGA (14 × 14)
7
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
2. PIN FUNCTIONS
2.1 Port Pins
(1/3)
Pin Name
P00
I/O
I/O
Function
Alternate Function
Port 0
TO100
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
TO101
Input/output can be specified in 1-bit units
TCLR10
TI10
INTP100/DMARQ0
INTP101/DMARQ1
INTP102/DMARQ2
INTP103/DMARQ3
TO110
I/O
Port 1
8-bit I/O port
TO111
Input/output can be specified in 1-bit units
TCLR11
TI11
INTP110/DMAAK0
INTP111/DMAAK1
INTP112/DMAAK2
INTP113/DMAAK3
NMI
Input
I/O
Port 2
P20 is an input only port.
–
When a valid edge is input, this pin operates as NMI input. Also, bit 0
of the P2 register indicates the NMI input status.
P21 to P27 are 7-bit I/O port.
TXD0/SO0
RXD0/SI0
SCK0
Input/output can be specified in 1-bit units
TXD1/SO1
RXD1/SI1
SCK1
I/O
Port 3
TO130
8-bit I/O port
TO131
Input/output can be specified in 1-bit units
TCLR13
TI13
INTP130
INTP131/SO2
INTP132/SI2
INTP133/SCK2
D0 to D7
I/O
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units
8
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/3)
Pin Name
I/O
I/O
Function
Alternate Function
D8 to D15
P50 to P57
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units
P60 to P67
P70 to P77
I/O
Port 6
A16 to A23
8-bit I/O port
Input/output can be specified in 1-bit units
Input
I/O
Port 7
ANI0 to ANI7
8-bit input only port
P80
Port 8
CS0/RAS0
CS1/RAS1
CS2/RAS2
CS3/RAS3
CS4/RAS4/IOWR
CS5/RAS5/IORD
CS6/RAS6
CS7/RAS7
LCAS/LWR
UCAS/UWR
RD
8-bit I/O port
P81
Input/output can be specified in 1-bit units
P82
P83
P84
P85
P86
P87
P90
I/O
I/O
I/O
Port 9
8-bit I/O port
P91
Input/output can be specified in 1-bit units
P92
P93
WE
P94
BCYST
P95
OE
P96
HLDAK
P97
HLDRQ
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P114
P115
P116
P117
Port 10
TO120
8-bit I/O port
TO121
Input/output can be specified in 1-bit units
TCLR12
TI12
INTP120/TC0
INTP121/TC1
INTP122/TC2
INTP123/TC3
TO140
Port 11
8-bit I/O port
TO141
Input/output can be specified in 1-bit units
TCLR14
TI14
INTP140
INTP141/SO3
INTP142/SI3
INTP143/SCK3
9
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/3)
Pin Name
P120
I/O
I/O
Function
Alternate Function
Port 12
TO150
TO151
TCLR15
TI15
8-bit I/O port
P121
P122
P123
P124
P125
P126
P127
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PX5
PX6
PX7
Input/output can be specified in 1-bit units
INTP150
INTP151
INTP152
INTP153/ADTRG
A0
I/O
I/O
I/O
Port A
8-bit I/O port
A1
Input/output can be specified in 1-bit units
A2
A3
A4
A5
A6
A7
Port B
A8
8-bit I/O port
A9
Input/output can be specified in 1-bit units
A10
A11
A12
A13
A14
A15
Port X
REFRQ
WAIT
CLKOUT
3-bit I/O port
Input/output can be specified in 1-bit units
10
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
2.2 Non-Port Pins
(1/4)
Pin Name
TO100
I/O
Function
Pulse signal output for timers 10 to 15
Alternate Function
Output
P00
TO101
TO110
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TO150
TO151
TCLR10
TCLR11
TCLR12
TCLR13
TCLR14
TCLR15
TI10
P01
P10
P11
P100
P101
P30
P31
P110
P111
P120
P121
Input
External clear signal input for timers 10 to 15
P02
P12
P102
P32
P112
P122
Input
External count clock input for timers 10 to 15
P03
TI11
P13
TI12
P103
TI13
P33
TI14
P113
TI15
P123
INTP100
INTP101
INTP102
INTP103
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
Input
Input
Input
External maskable interrupt request input, shared as external capture
trigger input for timer 10
P04/DMARQ0
P05/DMARQ1
P06/DMARQ2
P07/DMARQ3
P14/DMAAK0
P15/DMAAK1
P16/DMAAK2
P17/DMAAK3
P104/TC0
P105/TC1
P106/TC2
P107/TC3
External maskable interrupt request input, shared as external capture
trigger input for timer 11
External maskable interrupt request input, shared as external capture
trigger input for timer 12
11
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/4)
Pin Name
INTP130
I/O
Function
Alternate Function
Input
External maskable interrupt request input, shared as external capture
trigger input for timer 13
P34
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
INTP150
INTP151
INTP152
INTP153
SO0
P35/SO2
P36/SI2
P37/SCK2
P114
Input
Input
Output
Input
I/O
External maskable interrupt request input, shared as external capture
trigger input for timer 14
P115/SO3
P116/SI3
P117/SCK3
P124
External maskable interrupt request input, shared as external capture
trigger input for timer 15
P125
P126
P127/ADTRG
P22/TXD0
P25/TXD1
P35/INTP131
P115/INTP141
P23/RXD0
P26/RXD1
P36/INTP132
P116/INTP142
P24
Serial transmit data output (3-wire) for CSI0 to CSI3
Serial receive data input (3-wire) for CSI0 to CSI3
Serial clock I/O (3-wire) for CSI0 to CSI3
SO1
SO2
SO3
SI0
SI1
SI2
SI3
SCK0
SCK1
P27
SCK2
P37/INTP133
P117/INTP143
P22/SO0
P25/SO1
P23/SI0
SCK3
TXD0
Output
Input
I/O
Serial transmit data output for UART0 and UART1
Serial receive data input for UART0 and UART1
16-bit data bus for external memory
TXD1
RXD0
RXD1
P26/SI1
D0 to D7
D8 to D15
A0 to A7
A8 to A15
A16 to A23
LWR
P40 to P47
P50 to P57
PA0 to PA7
PB0 to PB7
P60 to P67
P90/LCAS
P91/UCAS
P92
Output
24-bit address bus for external memory
Output
Output
Output
Output
Output
Lower byte write-enable signal output for external data bus
Higher byte write-enable signal output for external data bus
Read strobe signal output for external data bus
Write enable signal output for DRAM
UWR
RD
WE
P93
OE
Output enable signal output for DRAM
P95
12
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/4)
Pin Name
LCAS
I/O
Function
Alternate Function
Output
Output
Output
Column address strobe signal output for DRAM’s lower data
Column address strobe signal output for DRAM’s higher data
Low address strobe signal output for DRAM
P90/LWR
UCAS
P91/UWR
RAS0 to RAS3
RAS4
P80/CS0 to P83/CS3
P84/CS4/IOWR
P85/CS5/IORD
P86/CS6
RAS5
RAS6
RAS7
P87/CS7
BCYST
CS0 to CS3
Output
Output
Strobe signal output indicating start of bus cycle
Chip select signal output
P94
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
P85/RAS5/IORD
P86/RAS6
CS5
CS6
CS7
P87/RAS7
WAIT
REFRQ
IOWR
IORD
Input
Output
Output
Output
Input
Control signal input for inserting waits in bus cycle
Refresh request signal output for DRAM
DMA write strobe signal output
PX6
PX5
P84/RAS4/CS4
P85/RAS5/CS5
DMA read strobe signal output
DMARQ0 to
DMARQ3
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
Output
Output
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
DMA end (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
HLDRQ
ANI0 to ANI7
NMI
Output
Input
Input
Input
Output
Input
Input
Bus hold acknowledge output
Bus hold request input
P96
P97
Analog input to A/D converter
Non-maskable interrupt request input
System clock output
P70 to P77
P20
PX7
–
CLKOUT
CKSEL
Input for specifying clock generator’s operation mode
Specify operation modes
MODE0 to
MODE3
–
RESET
X1
Input
Input
–
System reset input
–
Oscillator connection for system clock. Input is via X1 when using an
external clock.
–
X2
–
ADTRG
AVREF
AVDD
AVSS
Input
Input
–
A/D converter external trigger input
Reference voltage input for A/D converter
Positive power supply for A/D converter
Ground potential for A/D converter
P127/INTP153
–
–
–
–
13
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(4/4)
Pin Name
I/O
–
Function
Positive power supply for dedicated clock generator
Ground potential for dedicated clock generator
Positive power supply (power supply for internal units)
Positive power supply (power supply for external pins)
Ground potential
Alternate Function
CVDD
–
–
–
–
–
CVSS
VDD
–
–
HVDD
VSS
–
–
14
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
Recommended Connection of Unused Pins
P00/TO100, P01/TO101
P02/TCLR10, P03/TI10
5
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
5-K
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110, P11/TO111
P12/TCLR11, P13/TI11
5
5-K
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P20/NMI
2
5
Connect directly to VSS
P21
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P22/TXD0/SO0
P23/RXD0/SI0
5-K
P24/SCK0
P25/TXD1/SO1
5
P26/RXD1/SI1
5-K
P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13, P33/TI13
P34/INTP130
5
5-K
P35/INTP131/SO2
P36/INTP132/SI2
P37/INTP133/SCK2
P40/D0 to P47/D7
P50/D8 to P57/D15
P60/A16 to P67/A23
P70/ANI0 to P77/ANI7
P80/CS0/RAS0 to P83/CS3/RAS3
5
9
5
Connect directly to VSS
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P86/CS6/RAS6, P87/CS7/RAS7
P90/LCAS/LWR
P91/UCAS/UWR
15
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin
I/O Circuit Type
5
Recommended Connection of Unused Pins
P92/RD
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120, P101/TO121
P102/TCLR12, P103/TI12
5-K
P104/INTP120/TC0 to
P107/INTP123/TC3
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
P114/INTP140
5
5-K
P115/INTP141/SO3
P116/INTP142/SI3
P117/INTP143/SCK3
P120/TO150, P121/TO151
P122/TCLR15, P123/TI15
P124/INTP150 to P126/INTP152
P127/INTP153/ADTRG
PA0/A0 to PA7/A7
PB0/A8 to PB7/A15
PX5/REFRQ
5
5-K
5
PX6/WAIT
PX7/CLKOUT
CKSEL
1
2
Connect directly to HVDD
RESET
–
MODE0 to MODE2
MODE3
Connect to VSS via a resistor (RVPP)
Connect directly to VSS
AVREF, AVSS
–
–
AVDD
Connect directly to HVDD
16
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 2-1. Pin I/O Circuits
Type 1
Type 5-K
VDD
VDD
data
P-ch
IN/OUT
P-ch
IN
output
N-ch
disable
N-ch
input
enable
Type 2
Type 9
P-ch
N-ch
Comparator
IN
+
–
IN
VREF (threshold voltage)
input enable
Schmitt-triggered input with hysteresis characteristics
Type 5
VDD
data
P-ch
IN/OUT
output
disable
N-ch
input
enable
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
17
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Condition
Rating
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +4.6
−0.5 to +0.5
−0.5 to HVDD + 0.5
−0.5 to +0.5
−0.5 to HVDD + 0.5
−0.5 to VDD + 0.5
−0.5 to VDD + 1.0
4.0
Unit
Power supply voltage
VDD pin
V
V
HVDD pin, HVDD ≥ VDD
CVDD pin
HVDD
CVDD
CVSS
AVDD
AVSS
VI
V
CVSS pin
V
AVDD pin
V
AVSS pin
V
Input voltage
X1 pin, except MODE3 pin
MODE3 pin
V
V
Clock input voltage
Output current, low
VK
IOL
X1, VDD = 3.0 to 3.6 V
1 pin
V
mA
mA
mA
mA
V
Total of all pins
1 pin
100
−4.0
Output current, high
IOH
−100
Total of all pins
HVDD = 5.0 V 10 %
−0.5 to HVDD + 0.5
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
−40 to +70
Output voltage
VO
Analog input voltage
VIAN
P70/ANI0 to
AVDD > HVDD
HVDD ≥ AVDD
V
P77/ANI7 pins
V
A/D converter reference input
voltage
AVREF
TA
AVDD > HVDD
HVDD ≥ AVDD
µPD703100-40
V
V
°C
°C
°C
Operating ambient temperature
Storage temperature
µPD703100-33, 703101-33, 703102-33
−40 to +85
−60 to +150
Tstg
Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected with each other. A direct
connection can also be made for an external circuit designed with timing specifications that
prevent conflicting output from pins subject to high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
18
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Capacitance (TA = 25°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP.
MAX.
15
Unit
pF
fc = 1 MHz
Unmeasured pins returned to 0 V.
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Operation
Mode
Operating Ambient
Temperature (TA)
Power Supply Voltage
(VDD, HVDD)
Internal Operating Clock Frequency (φ)
µPD703100-40
−40 to +70°C
−40 to +85°C
−40 to +70°C
−40 to +85°C
Direct
mode
2 to 40 MHz
VDD = 3.0 to 3.6 V,
HVDD = 5.0 V 10%
µPD703100-33, 703101-33, 703102-33
µPD703100-40Note 2
2 to 33 MHz
20 to 40 MHz
20 to 33 MHz
PLL
modeNote 1
µPD703100-33, 703101-33, 703102-33Note 3
Notes 1. The internal operating clock frequency in PLL mode is the value for 5× operation. When used for 1× or
1/2× operation as set by the CKDIVn (n = 0, 1) bit of the CKC register, operation at a frequency of 20
MHz or less is possible.
2. Set the input clock frequency used in PLL mode to 4.0 to 8.0 MHz.
3. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
19
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Recommended Oscillator
(a) Ceramic resonator (TA = −40 to +70°C … µPD703100-40,
TA = −40 to +85°C … µPD703100-33, 703101-33, 703102-33)
(i) Murata Mfg. Co., Ltd. (TA = −40 to +85°C)
X1
X2
Rd
C1
C2
Oscillation
Stabilization
Time (MAX.)
TOST (ms)
Type
Part Number
Oscillation Recommended Circuit Constant
Oscillation Voltage
Range
Frequency
fXX (MHz)
Rd (kΩ)
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
Surface
CSAC4.00MGC040
CSTCC4.00MG0H6
CSAC5.00MGC040
CSTCC5.00MG0H6
CSAC6.60MT
4.0
4.0
5.0
5.0
6.6
6.6
8.0
8.0
4.0
4.0
5.0
5.0
6.6
6.6
8.0
8.0
100
On-chip
100
100
On-chip
100
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.5
0.3
0.4
0.2
0.2
0.1
0.2
0.3
0.5
0.5
0.5
0.5
0.1
0.1
0.1
0.1
mounting
On-chip
30
On-chip
30
CSTCC6.60MG0H6
CSAC8.00MT
On-chip
30
On-chip
30
CSTCC8.00MG0H6
CSA4.00MG040
CST4.00MGW040
CSA5.00MG040
CST5.00MGW040
CSA6.60MTZ
On-chip
100
On-chip
100
Lead
On-chip
100
On-chip
100
On-chip
30
On-chip
30
CST6.60MTW
On-chip
30
On-chip
30
CSA8.00MTZ
CST8.00MTW
On-chip
On-chip
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703100-33, 703100-40, 703101-33, 703102-
33 and the resonator.
20
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(ii) TDK (TA = −40 to +85°C)
X1
X2
Rd
C1
C2
Oscillation
Manufac-
turer
Part Number
Recommended Circuit Constant
Oscillation
Oscillation
Frequency
fXX (MHz)
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
Rd (kΩ)
C1 (pF)
On-chip
On-chip
On-chip
C2 (pF)
On-chip
On-chip
On-chip
MIN. (V) MAX. (V)
TDK
CCR4.0MC3
CCR5.0MC3
CCR8.0MC5
4.0
5.0
8.0
0
0
0
3.0
3.0
3.0
3.6
3.6
3.6
0.17
0.15
0.11
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703100-33, 703100-40, 703101-33, 703102-
33 and the resonator.
(iii) Kyocera Corporation (TA = −20 to +80°C)
X1
X2
Rd
C1
C2
Oscillation
Frequency
fXX (MHz)
Manufac-
turer
Part Number
Recommended Circuit Constant
Oscillation
Oscillation
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
Rd (kΩ)
C1 (pF)
On-chip
On-chip
On-chip
C2 (pF)
On-chip
On-chip
On-chip
MIN. (V) MAX. (V)
Kyocera
PBRC5.00BR-A
PBRC6.00BR-A
PBRC6.60BR-A
5.0
6.0
6.6
0
0
0
3.0
3.0
3.0
3.6
3.6
3.6
0.06
0.06
0.06
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703100-33, 703100-40, 703101-33, 703102-
33 and the resonator.
21
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) External clock input (TA = –40 to +70°C ... µPD703100-40,
TA = –40 to +85°C ... µPD703100-33, µPD703101-33, µPD703102-33)
X1
X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
22
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V)
Parameter
Symbol
Condition
Except Note 1
MIN.
TYP.
MAX.
HVDD + 0.3
HVDD + 0.3
+0.8
Unit
V
Input voltage, high
VIH
2.2
0.8HVDD
−0.5
Note 1
V
Input voltage, low
VIL
VXH
VXL
Except Note 1 and Note 2
V
−0.5
Note 1
0.2HVDD
VDD + 0.3
VDD + 0.3
0.15VDD
0.15VDD
V
Clock input voltage, high
Clock input voltage, low
X1 pin
X1 pin
Direct mode
PLL mode
Direct mode
PLL mode
0.8VDD
0.8VDD
−0.3
V
V
V
−0.3
V
Schmitt-triggered input
threshold voltage
HVT+
HVT−
Note 1, rising edge
Note 1, falling edge
Note 1
3.0
2.0
V
V
Schmitt-triggered input
hysteresis width
HVT+
–HVT−
0.5
V
IOH = −2.5 mA
Output voltage, high
VOH
0.7HVDD
V
V
IOH = −100 µA
HVDD − 0.4
Output voltage, low
VOL
ILIH
IOL = 2.5 mA
0.45
10
V
µA
µA
µA
µA
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
Except VI = HVDD or Note 2
Except VI = 0 V or Note 2
VO = HVDD
−10
10
ILIL
ILOH
ILOL
−10
VO = 0 V
Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,
RESET
2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.
Remark TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
23
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V)
Parameter
Symbol
IDD1
Condition
MIN.
TYP.
2.0 × fx
1.8 × fx
1.4 × fx
0.8 × fx
1.5
MAX.
3.6 × fx
3.0 × fx
2.5 × fx
1.6 × fx
3.0
Unit
Power supply
current
Normal
mode
VDD + CVDD
mA
mA
mA
mA
mA
µA
HVDD
HALT mode
IDLE mode
STOP mode
IDD2
IDD3
IDD4
VDD + CVDD
HVDD
VDD + CVDD
HVDD
10
50
µPD703100-40
VDD + CVDD
HVDD
1.0
3.0
mA
µA
10
50
µPD703100-33,
703101-33,
µA
VDD + CVDD
HVDD
20
100
µA
10
50
703102-33
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode:
fX = 2 to 40 MHz (µPD703100-40)
fX = 2 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
PLL mode:
fX = 20 to 40 MHz (µPD703100-40)
fX = 20 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
3. The unit for fX is MHz.
24
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Data Hold Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-
33, µPD703102-33)
Parameter
Data hold voltage
Symbol
VDDDR
Condition
MIN.
1.5
TYP.
MAX.
3.6
Unit
V
STOP mode, VDD = VDDDR
HVDDDR
STOP mode,
VDDDR
5.5
V
HVDD = HVDDDR
µPD703100-40
Data hold current
IDDDR
VDD = VDDDR
VDD = VDDDR
1.0
30
3.0
mA
µPD703100-33,
703101-33,
µA
150
703102-33
µs
Power supply voltage rise
time
tRVD
200
µs
Power supply voltage fall time
tFVD
tHVD
200
0
Power supply voltage hold
time (to STOP mode setting)
ms
STOP mode release signal
input time
tDREL
VIHDR
VILDR
0
ns
V
Data hold high-level input
voltage
Note
Note
0.8HVDDDR
0
HVDDDR
Data hold low-level input
voltage
0.2HVDDDR
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, Pl16/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
Remark TYP. values are reference values for when TA = 25°C.
25
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
STOP mode setting
VDDDR
VDD
t
FVD
tRVD
tHVD
tDREL
HVDD
V
IHDR
RESET (input)
NMI (input)
VIHDR
(Released by falling edge)
NMI (input)
(Released by rising edge)
VILDR
26
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
AC Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Waveform
(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/
INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/
TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/
INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14,
P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/
SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HVDD
0.8HVDD
0.2HVDD
0.8HVDD
0.2HVDD
Test
points
Input signal
0 V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
0.8 V
2.2 V
0.8 V
Test
points
Input signal
0.4 V
AC Test Output Test Points
2.4 V
0.8 V
2.4 V
0.8 V
Test
points
Output signal
27
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Load Condition
DUT
(Device under test)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device's load capacitance 50 pF.
(1) Clock timing
Parameter
X1 input cycle
Symbol
Condition
µPD703100-40
MIN.
12.5
15
MAX.
250
Unit
ns
<1>
tCYX
Direct
mode
µPD703100-33,
703101-33,
250
ns
703102-33
µPD703100-40
PLL mode
125
150
250
250
ns
ns
µPD703100-33,
703101-33,
703102-33
X1 input high-level width
X1 input low-level width
X1 input rise time
<2>
<3>
<4>
<5>
<6>
tWXH
tWXL
tXR
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
5
50
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
4
10
4
X1 input fall time
tXF
10
500
500
µPD703100-40
CLKOUT output cycle
tCYK
25
30
µPD703100-33, 703101-33,
703102-33
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<7>
<8>
tWKH
tWKL
tKR
0.5T – 7
0.5T – 4
ns
ns
ns
ns
<9>
5
5
CLKOUT fall time
<10>
tKF
Remark T = tCYK
28
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<3>
<2>
<4>
X1
(Direct mode)
<5>
CLKOUT (output)
<9>
<10>
<7>
<8>
<6>
(2) Output waveform (other than X1, CLKOUT)
Parameter
Output rise time
Output fall time
Symbol
<12>
<13>
Condition
MIN.
MAX.
10
Unit
ns
tOR
tOF
10
ns
<12>
<13>
Signals other than X1, CLKOUT
29
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(3) Reset timing
Parameter
RESET high-level width
RESET low-level width
Symbol
Condition
MIN.
500
MAX.
Unit
ns
<14>
<15>
tWRSH
tWRSL
When power supply is on, and
STOP mode has been released
500 + TOS
ns
Other than when power supply is
on, and STOP mode has been
released
500
ns
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (input)
30
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
31
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<16>
Condition
Unit
ns
MIN.
2
MAX.
10
Address, CSn output delay time (from
tDKA
CLKOUT ↓)
Address, CSn output hold time (from
<17>
<18>
<19>
<20>
<21>
tHKA
2
2
2
2
2
10
14
14
10
10
ns
ns
ns
ns
ns
CLKOUT ↓)
RD, IORD ↓ delay time
(from CLKOUT ↑)
tDKRDL
tHKRDH
tDKWRL
tHKWRH
RD, IORD ↑ delay time
(from CLKOUT ↑)
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
BCYST ↓ delay time (from CLKOUT ↓)
BCYST ↑ delay time (from CLKOUT ↓)
WAIT setup time (to CLKOUT ↓)
<22>
<23>
<24>
<25>
<26>
tDKBSL
tHKBSH
tSWK
2
2
10
10
ns
ns
ns
ns
ns
15
2
WAIT hold time (from CLKOUT ↓)
tHKW
Data input setup time
tSKID
18
(to CLKOUT ↑)
Data input hold time
<27>
<28>
<29>
tHKID
tDKOD
tHKOD
2
2
2
ns
ns
ns
(from CLKOUT ↑)
Data output delay time
10
10
(from CLKOUT ↓)
Data output hold time
(from CLKOUT ↓)
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0 to 7
32
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<22>
<17>
A0 to A23 (Output)
CSn (Output)
<23>
BCYST (Output)
<18>
<20>
<19>
RD, IORD (Output)
[Read time]
<21>
UWR, LWR, IOWR (Output)
[Write time]
<26>
<27>
D0 to D15 (I/O)
[Read time]
<28>
<29>
D0 to D15 (I/O)
[Write time]
<25>
<24>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
33
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<30>
Condition
MIN.
MAX.
Unit
ns
Data input setup time (to address)
Data input setup time (to RD)
RD, IORD low-level width
RD, IORD high-level width
tSAID
tSRDID
tWRDL
tWRDH
tDARD
(1.5 + wD + w)T – 28
(1 + wD + w)T – 32
<31>
<32>
<33>
<34>
ns
(1 + wD + w)T – 10
T – 10
ns
ns
Delay time from address, CSn to RD,
0.5T – 10
ns
IORD ↓
Delay time from RD, IORD ↑ to
<35>
tDRDA
(0.5 + i)T – 10
ns
address
Data input hold time (from RD, IORD ↑)
<36>
<37>
tHRDID
0
ns
ns
Delay time from RD, IORD ↑ to data
tDRDOD
(0.5 + i)T – 10
output
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
<38>
<39>
<40>
tSAW
tSBSW
tHBSW
Note
Note
Note
T – 25
T – 25
ns
ns
ns
0
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
5. Maintain at least one of the data input hold times tHKID and tHRDID.
6. n = 0 to 7
34
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
UWR, LWR, IOWR (Output)
RD, IORD (Output)
D0 to D15 (I/O)
<33>
<32>
<35>
<37>
<34>
<31>
<30>
<36>
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
35
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<38>
Condition
Note
MIN.
MAX.
T – 25
T – 25
Unit
ns
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
tSAW
tSBSW
tHBSW
tDAWR
<39>
<40>
<41>
Note
ns
Note
0
ns
Delay time from address, CSn to
0.5T – 10
ns
UWR, LWR, IOWR ↓
Address setup time (to UWR, LWR,
<42>
<43>
tSAWR
(1.5 + wD + w)T – 10
0.5T – 10
ns
ns
IOWR ↑)
Delay time from UWR, LWR, IOWR ↑
tDWRA
to address
UWR, LWR, IOWR high-level width
UWR, LWR, IOWR low-level width
<44>
<45>
<46>
tWWRH
tWWRL
T – 10
ns
ns
ns
(1 + wD + w)T – 10
(1.5 + wD + w)T – 10
Data output setup time
tSODWR
(to UWR, LWR, IOWR ↑)
Data output hold time
<47>
tHWROD
0.5T – 10
ns
(from UWR, LWR, IOWR ↑)
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. n = 0 to 7
36
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
UWR, LWR, IOWR (Output)
D0 to D15 (I/O)
<42>
<43>
<41>
<45>
<44>
<46>
<47>
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
37
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
Condition
Unit
ns
MIN.
15
MAX.
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
RD low-level width
<24>
tSWK
tHKW
<25>
<32>
2
ns
tWRDL
(1 + w
D
+ w
F
+ w)
T
ns
–
10
RD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
<44>
<45>
<48>
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from address, CSn to RD ↓
Delay time from RD ↑ to address
Delay time from RD ↑ to data output
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
Delay time from address to IOWR ↓
Address setup time (to IOWR ↑)
Delay time from IOWR ↑ to address
IOWR high-level width
0.5T – 10
(0.5 + i)T – 10
(0.5 + i)T – 10
Note
Note
Note
T – 25
T – 25
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
tWWRH
tWWRL
tDWRRD
0
0.5T – 10
(1.5 + wD + w)T – 10
0.5T – 10
T – 10
IOWR low-level width
(1 + wD + w)T – 10
0
Delay time from IOWR ↑ to RD ↑
wF = 0
wF = 1
T – 10
Delay time from DMAAKm ↓ to IOWR ↓
Delay time from IOWR ↑ to DMAAKm ↑
<49>
<50>
tDDAWR
tDWRDA
0.5T – 10
(0.5 + wF)T – 10
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
38
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<33>
<32>
<35>
RD (Output)
UWR, LWR (Output)
DMAAKm (Output)
IORD (Output)
<34>
<48>
<49>
<41>
<50>
<43>
<42>
<45>
<44>
IOWR (Output)
<37>
D0 to D15 (I/O)
WAIT (Input)
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
39
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
<24>
tSWK
tHKW
<25>
<32>
2
ns
tWRDL
(1 + wD + wF + w)T
– 10
ns
IORD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from address, CSn to IORD ↓
Delay time from IORD ↑ to address
Delay time from IORD ↑ to data output
WAIT setup time (to address)
0.5T – 10
(0.5 + i)T – 10
(0.5 + i)T – 10
Note
Note
Note
T – 25
T – 25
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
tSBSW
tHBSW
tDAWR
0
Delay time from address to UWR,
0.5T – 10
LWR ↓
Address setup time (to UWR, LWR ↑)
<42>
<43>
tSAWR
(1.5 + wD + w)T – 10
0.5T – 10
ns
ns
Delay time from UWR, LWR to
address
tDWRA
UWR, LWR high-level width
<44>
<45>
<48>
tWWRH
tWWRL
T – 10
(1 + wD + w)T – 10
0
ns
ns
ns
ns
ns
ns
UWR, LWR low-level width
Delay time from UWR, LWR↑ to IORD ↑
tDWRRD
wF = 0
wF = 1
T – 10
Delay time from DMAAKm ↓ to IORD ↓
Delay time from IORD ↑ to DMAAKm ↑
<51>
<52>
tDDARD
tDRDDA
0.5T – 10
0.5T – 10
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
40
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<42>
<45>
<43>
<41>
<44>
UWR, LWR (Output)
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
<34>
<33>
<32>
<35>
<37>
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
41
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (1/2)
Parameter
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
tSWK
tHKW
tSKID
<25>
<26>
2
ns
Data input setup time
18
ns
(to CLKOUT ↑)
Data input hold time
<27>
<30>
tHKID
tSAID
2
ns
ns
(from CLKOUT ↑)
Off-page data input setup time (to
address)
(1.5 + wD + w)T – 28
(1 + wD + w)T – 32
Off-page data input setup time (to RD)
Off-page RD low-level width
RD high-level width
<31>
<32>
<33>
<36>
<37>
<53>
tSRDID
tWRDL
ns
ns
ns
ns
ns
ns
(1 + wD + w)T – 10
0.5T – 10
tWRDH
tHRDID
tDRDOD
tWORDL
Data input hold time (from RD)
Delay time from RD ↑ to data output
On-page RD low-level width
0
(0.5 + i)T – 10
(1.5 + wPR + w)T
– 10
On-page data input setup time
(to address)
<54>
<55>
tSOAID
(1.5 + wPR + w)T – 28
(1.5 + wPR + w)T – 32
ns
ns
On-page data input setup time (to RD)
tSORDID
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wPR: the number of waits due to the PRC register.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times tHKID and tHRDID.
42
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1 TPRW
TW
TO2
CLKOUT (Output)
Off-page addressNote
CSn (Output)
On-page addressNote
UWR, LWR (Output)
RD (Output)
<26>
<30>
<31>
<54>
<33>
<53>
<55>
<32>
<37>
<36>
<27>
<36>
<27>
<26>
<25>
D0 to D15 (I/O)
WAIT (Input)
<25>
<24>
<24>
<25>
<24>
<25>
<24>
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC Register
On-page Addresses
Off-page Addresses
MA5
MA4
MA3
0
0
0
1
0
0
1
1
0
1
1
1
A0, A1
A0 to A2
A0 to A3
A0 to A4
A2 to A23
A3 to A23
A4 to A23
A5 to A23
Remarks 1. This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
43
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Row address setup time
tSWK
tHKW
tSKID
tHKID
tDRDOD
tASR
15
<25>
<26>
<27>
<37>
<56>
<57>
<58>
<59>
<60>
2
18
2
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
tRAH
tASC
Column address setup time
Column address hold time
tCAH
tRC
(1.5 + wDA + w)T – 10
Read/write cycle time
(3 + wRP + wRH + wDA + w)
T
–
10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wRP)T – 10
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T
– 10
WE setup time
<68>
<69>
<70>
<71>
<72>
tRCS
tRRH
tRCH
tCPN
tOEA
(2 + wRP + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
ns
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
T – 10
(2 + wRP + wRH)T – 10
Output enable access time
(2 + wRP + wRH + wDA + w)T
–
28
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)
T
ns
–
28
Access time from column address
CAS access time
<74>
<75>
tAA
(1.5 + wDA + w)T – 28
(1 + wDA + w)T – 28
ns
ns
tCAC
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
44
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
RAS column address delay time
RAS-CAS delay time
Symbol
<76>
Condition
Unit
ns
MIN.
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
MAX.
tRAD
tRCD
tOEZ
<77>
<78>
ns
Output buffer turn-off delay time (from
ns
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
ns
CAS ↑)
Remarks 1. T = tCYK
2. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
45
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
<57>
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<69>
<70>
<71>
<68>
<73>
<75>
WE (Output)
OE (Output)
<79>
<74>
<27>
<72>
<37>
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
46
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
47
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Column address setup time
Column address hold time
RAS hold time
tSKID
tHKID
tDRDOD
tASC
tCAH
tRSH
tRAL
<27>
<37>
<58>
<59>
<63>
<64>
<65>
<68>
<69>
<70>
<72>
<74>
<75>
<78>
2
(0.5 + i)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
(1 + wCP)T – 10
0.5T – 10
Column address read time for RAS
CAS pulse width
tCAS
tRCS
tRRH
tRCH
tOEA
tAA
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
Output enable access time
Access time from column address
CAS access time
T – 10
(1 + wCP + wDA)T – 28
(1.5 + wCP + wDA)T – 28
tCAC
tOEZ
(1 + wDA)T – 28
Output buffer turn-off delay time (from
0
0
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
ns
CAS ↑)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<82>
<83>
tACP
tCP
(2 + wCP + wDA)T – 28
ns
ns
ns
ns
(1 + wCP)T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
tPC
(2 + wCP + wDA)T – 10
tRHCP
(2.5 + wCP + wDA)T – 10
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
48
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
<82>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
WE (Output)
OE (Output)
<75>
<79>
<37>
<72>
<26>
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
49
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Row address setup time
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tASR
tRAH
tASC
tCAH
tRC
<25>
<56>
<57>
<58>
<59>
<60>
2
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w)T – 10
(3 + wRP + wRH + wDA
w)T – 10
+
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wRH)T – 10
ns
ns
ns
ns
ns
Column address read time (from RAS
CAS pulse width
↑)
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T
– 10
CAS precharge time
<71>
<76>
<77>
<84>
tCPN
tRAD
tRCD
tWCS
(2 + wRP + wRH)T – 10
(0.5 + wRH)T – 10
(1 + wRH)T – 10
ns
ns
ns
ns
RAS column address delay time
RAS-CAS delay time
WE setup time (to CAS ↓)
(1 + wRP + wRH )T
– 10
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
<85>
<86>
<87>
tWCH
tDS
(1 + wDA + w)T – 10
ns
ns
ns
(1.5 + wRP + wRH
)T – 10
tDH
(1.5 + wDA + w)T – 10
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
50
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
<57>
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<71>
OE (Output)
WE (Output)
<84>
<85>
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
51
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<58>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Column address setup time
Column address hold time
RAS hold time
tASC
tCAH
tRSH
tRAL
tCAS
tCP
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
(1 + wCP)T – 10
<59>
<63>
<64>
<65>
<81>
<83>
Column address read time (from RAS
CAS pulse width
↑)
CAS precharge time
RAS hold time for CAS precharge
tRHCP
(2.5 + wCP + wDA)T
– 10
WE setup time (to CAS ↓)
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
Data setup time (to WE ↓)
Data hold time (from WE ↓)
WE pulse width
wCP ≥ 1
<84>
<85>
<86>
<87>
<88>
<89>
<90>
<91>
<92>
tWCS
tWCH
tDS
wCPT – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(1 + wDA)T – 10
0.5T – 10
tDH
tRWL
tCWL
tDSWE
tDHWE
tWP
wCP = 0
wCP = 0
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA)T – 10
(1 + wDA)T – 10
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
52
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
WE (Output)
<84>
<85>
<92>
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
53
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Row address setup time
tSKID
tHKID
tDRDOD
tASR
tRAH
tASC
tCAH
tRP
<27>
<37>
<56>
<57>
<58>
<59>
<61>
<64>
<66>
<67>
<68>
<69>
<70>
<73>
<74>
<75>
2
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
(0.5 + wDA)T – 10
(0.5 + wRP)T – 10
(2 + wCP + wDA)T – 10
(1 + wRP)T – 10
Column address read time (from RAS
CAS-RAS precharge time
CAS hold time
↑)
tRAL
tCRP
tCSH
tRCS
tRRH
tRCH
tRAC
tAA
(1.5 + wRH + wDA)T – 10
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
RAS access time
(2 + wRP + wRH)T – 10
0.5T – 10
1.5T – 10
(2 + wRH + wDA)T – 28
Access time from column address
CAS access time
(1.5 + wDA)T – 28
(1 + wDA)T – 28
tCAC
tRAD
tRCD
tOEZ
Delay time from RAS to column address <76>
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
RAS-CAS delay time
<77>
<78>
Output buffer turn-off delay time (from
OE)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<83>
<93>
<94>
<95>
<96>
<97>
<98>
tACP
tCP
(1.5 + wCP + wDA
)T – 28
ns
ns
ns
ns
ns
ns
ns
ns
ns
(0.5 + wCP)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA + wCP)T – 10
RAS hold time for CAS precharge
Read cycle time
tRHCP
tHPC
RAS pulse width
tRASP
tHCAS
tOCH1
tOCH2
tDHC
(2.5 + wRH + wDA)T – 10
CAS pulse width
(0.5 + wDA)T – 10
(2 + wRH + wDA)T – 10
(0.5 + wDA)T – 10
0
CAS hold time from OE
Off-page
On-page
Data input hold time (from CAS ↓)
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
54
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
Output enable access
time
Off-page
On-page
<99>
tOEA1
(2 + wRP + wRH + wDA)T
– 28
<100>
tOEA2
(1 + wCP + wDA
)
T – 28
ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
55
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<57>
<56>
<59>
A0 to A23 (Output)
RASn (Output)
Row address
<76>
Column address
Column address
<64>
<74>
<61>
<94>
<67>
<77>
<83>
<75>
<66>
<95>
<93>
<81>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
<95>
<80>
WE (Output)
OE (Output)
<97>
<96>
<100> <26>
<37>
Note
<75>
<98>
<27>
<27>
<78>
<74>
<26>
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
Data
Data
<73>
<99>
Note For on-page access from another cycle during the RASn low-level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
56
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
57
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (1/2)
Parameter
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
Symbol
<56>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tASR
tRAH
tASC
tCAH
tRP
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
<57>
<58>
<59>
<61>
<63>
<64>
(0.5 + wDA)T – 10
(0.5 + wRP)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
RAS hold time
tRSH
tRAL
Column address read time
(from RAS ↑)
CAS-RAS precharge time
CAS hold time
<66>
<67>
<76>
<77>
<81>
<83>
<85>
<87>
<88>
tCRP
tCSH
tRAD
tRCD
tCP
(1 + wRP)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1.5 + wRH + wDA)T – 10
Delay time from RAS to column address
RAS-CAS delay time
(0.5 + wRH)T – 10
(1 + wRH)T – 10
CAS precharge time
(0.5 + wCP)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
Data hold time (from CAS ↓)
tRHCP
tWCH
tDH
(0.5 + wDA)T – 10
(1.5 + wDA)T – 10
WE read time
On-page
On-page
On-page
tRWL
wCP = 0
wCP = 0
wCP = 0
(from RAS ↑)
WE read time
<89>
tCWL
(0.5 + wDA)T – 10
ns
(from CAS ↑)
WE pulse width
Write cycle time
RAS pulse width
CAS pulse width
<92>
<93>
tWP
tHPC
(1 + wDA)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA + wCP)T – 10
<94>
tRASP
tHCAS
tWCS1
tWCS2
tDS1
(2.5 + wRH + wDA
)T – 10
<95>
(0.5 + wDA)T – 10
WE setup time
Off-page
On-page
Off-page
On-page
<101>
<102>
<103>
<104>
(1 + wRP + wRH
)T – 10
(to CAS ↓)
wCP ≥ 1
wCPT – 10
Data setup time
(1.5 + wRP + wRH
)T – 10
(to CAS ↓)
tDS2
(0.5 + wCP)T – 10
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
58
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
<58>
<59>
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<67>
<77>
<83>
<66>
<95>
<89>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<88>
<95>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
<103>
<87>
<104>
<87>
Data
Data
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
59
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Delay time from OE ↑ to data output
Delay time from address to IOWR ↓
Address setup time (to IOWR ↑)
<24>
tSWK
tHKW
15
2
<25>
<37>
<41>
<42>
ns
tDRDOD
tDAWR
tSAWR
(0.5 + i)T – 10
(0.5 + wRP)T – 10
ns
ns
(2 + wRP + wRH + wDA +
w)T – 10
ns
Delay time from IOWR ↑ to address
Delay time from IOWR ↑ to RD ↑
<43>
<48>
tDWRA
0.5T – 10
0
ns
ns
ns
ns
tDWRRD
wF = 0
wF = 1
T – 10
IOWR low-level width
<50>
tWWRL
(2 + wRH + wDA + w)T
– 10
Row address setup time
Row address hold time
Column address setup time
Column address hold time
<56>
<57>
<58>
<59>
tASR
tRAH
tASC
tCAH
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
(1.5 + wDA + wF + w)T
– 10
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF + w)T – 10
ns
RAS precharge time
RAS hold time
<61>
<63>
tRP
(0.5 + wRP)T – 10
ns
ns
tRSH
(1.5 + wDA + wF + w)T
– 10
Column address read time for RAS
CAS pulse width
<64>
<65>
tRAL
tCAS
(2 + wCP + wDA + w
w)T – 10
F
+
ns
ns
(1 + wDA + wF + w)T
– 10
CAS-RAS precharge time
CAS hold time
<66>
<67>
tCRP
tCSH
(1 + wRP)T – 10
ns
ns
(2 + wRH + wDA + w
w)T – 10
F +
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
60
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3)
Parameter
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
Symbol
<68>
Condition
MIN.
(2 + wRP + wRH)T – 10
0.5T – 10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tRCS
tRRH
tRCH
tCPN
tRAD
tRCD
tOEZ
<69>
<70>
<71>
1.5T – 10
(2 + wRP + wRH)T – 10
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
Delay time from RAS to column address <76>
RAS-CAS delay time
<77>
<78>
Output buffer turn-off delay time (from
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
ns
CAS ↑)
CAS precharge time
<81>
<82>
tCP
tPC
(0.5 + wCP)T – 10
ns
ns
High-speed page mode cycle time
(2 + wCP + wDA + w
10
F
+ w)T
–
RAS hold time for CAS precharge
RAS pulse width
<83>
<94>
<96>
<97>
tRHCP
tRASP
tOCH1
tOCH2
(2.5 + wCP + wDA + w
F
+ w)
T
ns
ns
ns
ns
–
10
(2.5 + wRH + wDA + w
F
+ w)T
– 10
CAS hold time from OE
Off-page
On-page
(2.5 + wRP + wRH + wDA +
wF + w)T – 10
(from CAS ↑)
(1.5 + wCP + wDA + w
F
+ w)T
–
10
Delay time from DMAAKm ↓ to CAS ↓
Delay time from IOWR ↓ to CAS ↓
<105>
<106>
tDDACS
tDRDCS
(1.5 + wRH)T – 10
(1 + wRH)T – 10
ns
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
61
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW T1 TRHW T2 TDAW TW
T3 TCPW TO1 TDAW TW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
Column address
<94>
Row address
<76>
Column address
<64>
<61>
<60>
<69>
<77>
<65>
<83>
<63>
<66>
<67>
<81>
UCAS (Output)
LCAS (Output)
<70>
<71>
<82>
<48>
<96>
<79>
RD (Output)
OE (Output)
<105>
<97>
DMAAKm (Output)
WE (Output)
<68>
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<42>
<43>
<78>
<37>
<41>
<50>
<24>
Data
Data
<25>
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
62
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tWRDL
tWRDH
tDARD
tDRDA
tASR
<25>
<32>
<33>
<34>
<35>
<56>
<57>
<58>
<59>
<60>
2
(2 + wRH + wDA + wF + w)T – 10
T – 10
IORD high-level width
Delay time from address to IORD ↑
Delay time from IORD ↑ to address
Row address setup time
0.5T – 10
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
tRAH
Column address setup time
Column address hold time
Read/write cycle time
tASC
tCAH
(1.5 + wDA + wF)T – 10
tRC
(3 + wRP + wRH + wDA + wF + w)T
– 10
RAS precharge time
RAS hold time
<61>
<63>
<64>
<65>
<66>
<67>
<71>
tRP
tRSH
tRAL
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tCP
(0.5 + wRP)T – 10
(1.5 + wDA + wF)T – 10
(2 + wCP + wDA + wF + w)T – 10
(1 + wDA + wF)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(1 + wRP)T – 10
(2 + wRH + wDA + wF + w)T – 10
(2 + wRP + wRH + w)T – 10
(0.5 + wRH)T – 10
CAS precharge time
Delay time from RAS to column address <76>
RAS-CAS delay time
<77>
<81>
<82>
<83>
<85>
<88>
(1 + wRH + w)T – 10
CAS precharge time
(0.5 + wCP + w)T – 10
(2 + wCP + wDA + wF + w)T – 10
(2.5 + wCP + wDA + w)T – 10
(1 + wDA)T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
WE read time (from RAS ↑)
tPC
tRHCP
tWCH
tRWL
wCP = 0
(1.5 + wDA + w)T – 10
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
9. n = 0 to 7
63
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
WE read time (from CAS ↑)
WE pulse width
Symbol
Condition
wCP = 0
wCP = 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
(1 + wDA + w)T – 10
(1 + wDA + w)T – 10
(2.5 + wRH + wDA + wF + w)T – 10
(1 + wRH + wRP + w)T – 10
wCPT – 10
MAX.
<89>
tCWL
tWP
<92>
<94>
RAS pulse width
tRASP
tWCS1
tWCS2
tDDACS
tDRDCS
tDWERD
WE setup time
Off-page
On-page
<101>
<102>
<105>
<106>
<107>
wCP = 0
(to CAS ↓)
wCP ≥ 1
Delay time from DMAAKm ↓ to CAS ↓
Delay time from IORD ↓ to CAS ↓
Delay time from WE ↑ to IORD ↑
(1.5 + wRH + w)T – 10
(1 + wRH + w)T – 10
0
wF = 0
wF = 1
T – 10
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
64
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW T1 TRHW TW
T2 TDAW T3 TCPW TW
TO1 TDAW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<56>
<61>
<57>
<58>
<59>
Row address
Column address
Column address
<64>
<76>
<94>
<60>
<77>
<65>
<66>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<82>
<83>
RD (Output)
OE (Output)
<102>
<88>
<89>
<101>
<105>
<85>
WE (Output)
<92>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<107>
<35>
<34>
<32>
<24>
<25>
<33>
Data
Data
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
65
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(i) CBR refresh timing
Parameter
RAS precharge time
RAS pulse width
Symbol
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
<61>
tRP
tRAS
(1.5 + wRRW)T – 10
(1.5 + wRCWNote)T – 10
(1.5 + wRCWNote)T – 10
(3 + wRRW + wRCWNote)T – 10
(0.5 + wRRW)T – 10
2
<62>
<108>
<109>
<110>
<111>
CAS hold time
tCHR
tWRFL
tRPC
tDKRF
REFRQ pulse width
RAS precharge CAS hold time
REFRQ active delay time
10
10
(from CLKOUT ↓)
REFRQ inactive delay time
<112>
<113>
tHKRF
tCSR
2
ns
ns
(from CLKOUT ↓)
CAS setup time
T – 10
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits
of the RWC register.
Remarks 1. T = tCYK
2. wRRW: the number of waits due to the RRW0 and RRW1 bits of the RWC register.
3. wRCW: the number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW
T1
T2
TRCWNote
TRCW
T3
TI
CLKOUT (Output)
REFRQ (Output)
RASn (Output)
<111>
<112>
<109>
<61>
<62>
<110>
<110>
<113>
<108>
UCAS (Output)
LCAS (Output)
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 0 to 7
66
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(j) CBR self-refresh timing
Parameter
Symbol
Condition
MIN.
2
MAX.
10
Unit
ns
REFRQ active delay time
<111>
tDKRF
(from CLKOUT ↓)
REFRQ inactive delay time
<112>
tHKRF
2
10
ns
(from CLKOUT ↓)
−5
CAS hold time
<114>
<115>
tCHS
tRPS
ns
ns
RAS precharge time
(1 + 2wSRW)T – 10
Remarks 1. T = tCYK
2. wSRW: the number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (Output)
REFRQ (Output)
RASn (Output)
<111>
<112>
<115>
<114>
UCAS (Output)
LCAS (Output)
Output signals
other than above
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
2. The broken lines indicate high impedance.
3. n = 0 to 7
67
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(7) DMAC timing
Parameter
Symbol
<116>
Condition
Unit
ns
MIN.
MAX.
DMARQn setup time (to CLKOUT ↑)
DMARQn hold time (from CLKOUT ↑)
tSDRK
tHKDR1
tHKDR2
tDKDA
15
<117>
<118>
<119>
2
ns
Until DMAAKn ↓
ns
DMAAKn output delay time
2
10
10
10
10
ns
(from CLKOUT ↓)
DMAAKn output hold time
<120>
<121>
<122>
tHKDA
tDKTC
tHKTC
2
2
2
ns
ns
ns
(from CLKOUT ↓)
TCn output delay time
(from CLKOUT ↓)
TCn output hold time
(from CLKOUT ↓)
Remark n = 0 to 3
CLKOUT (Output)
<117>
<116>
<118>
DMARQn (Input)
DMAAKn (Output)
<116>
<119>
<120>
<122>
<121>
TCn (Output)
Remark n = 0 to 3
68
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
69
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
15
MAX.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ setup time (to CLKOUT ↑)
HLDRQ hold time (from CLKOUT ↑)
Delay time from CLKOUT ↓ to HLDAK
HLDRQ high-level width
<123>
tSHRK
tHKHR
<124>
<125>
<126>
<127>
<128>
<129>
<130>
<131>
2
tDKHA
2
tWHQH
tWHAL
T + 17
T – 8
HLDAK low-level width
Delay time from CLKOUT ↓ to bus float
Delay time from HLDAK ↑ to bus output
Delay time from HLDRQ ↓ to HLDAK ↓
Delay time from HLDRQ ↑ to HLDAK ↑
tDKCF
10
tDHAC
0
tDHQHA1
tDHQHA2
2.5T
0.5T
1.5T
Remark T = tCYK
70
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (Output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
HLDRQ (Input)
HLDAK (Output)
A0 to A23 (Output)
D0 to D15 (I/O)
CSn/RASn (Output)
BCYST (Output)
RD (Output)
<125>
<128>
<125>
<131>
<130>
<127>
<129>
Address
Undefined
Data
WE (Output)
UCAS (Output)
LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 7
71
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(9) Interrupt timing
Parameter
Symbol
<132>
Condition
MIN.
500
MAX.
Unit
ns
NMI high-level width
NMI low-level width
INTPn high-level width
INTPn low-level width
tWNIH
tWNIL
tWITH
tWITL
<133>
<134>
<135>
500
ns
4T + 10
4T + 10
ns
ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
2. T = tCYK
<132>
<134>
<133>
NMI (Input)
<135>
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
(10) RPU timing
Parameter
TI1n high-level width
Symbol
Condition
MIN.
MAX.
Unit
ns
<136>
tWTIH
tWTIL
3T + 18
3T + 18
3T + 18
3T + 18
TI1n low-level width
<137>
<138>
<139>
ns
TCLR1n high-level width
TCLR1n low-level width
tWTCH
tWTCL
ns
ns
Remarks 1. n = 0 to 5
2. T = tCYK
<136>
<137>
TI1n (Input)
<138>
<139>
TCLR1n (Input)
Remark n = 0 to 5
72
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter
Symbol
<140>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
tCYSK0
tWSK0H
tWSK0L
tSRXSK
tHSKRX
tDSKTX
tHSKTX
250
SCKn high-level width
<141>
<142>
<143>
<144>
<145>
<146>
Output
0.5tCYSK0 – 20
SCKn low-level width
Output
0.5tCYSK0 – 20
RXDn setup time (to SCKn ↑)
RXDn hold time (from SCKn ↑)
TXDn output delay time (from SCKn ↓)
TXDn output hold time (from SCKn ↑)
30
0
20
0.5tCYSK0 – 5
Remark n = 0, 1
<140>
<142>
<141>
SCKn (I/O)
<143>
<144>
RXDn (Input)
Input data
<145>
<146>
TXDn (Output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
73
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
Symbol
<147>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
tCYSK1
tWSK1H
tWSK1L
tSSISK
100
SCKn high-level width
<148>
<149>
<150>
<151>
<152>
<153>
Output
0.5tCYSK1 – 20
SCKn low-level width
Output
0.5tCYSK1 – 20
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
30
0
tHSKSI
tDSKSO
tHSKSO
20
0.5tCYSK1 – 5
Remark n = 0 to 3
(b) Slave mode
Parameter
Symbol
Condition
Input
MIN.
100
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
<147>
<148>
<149>
<150>
<151>
<152>
<153>
tCYSK1
tWSK1H
tWSK1L
tSSISK
SCKn high-level width
Input
SCKn low-level width
Input
30
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
10
tHSKSI
tDSKSO
tHSKSO
10
30
tWSK1H
Remark n = 0 to 3
<147>
<149>
<148>
SCKn (I/O)
<150>
<151>
Sln (Input)
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
74
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
A/D Converter Characteristics (TA = –40 to +70°C ... µPD703100-40,
TA = –40 to +85°C ... µPD703100-33, 703101-33, 703102-33,
VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V,
HVDD – 0.5 V ≤ AVDD ≤ HVDD, output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Condition
MIN.
10
TYP.
MAX.
Unit
Resolution
Total error
–
–
bit
LSB
LSB
µs
4
1/2
10
Quantization error
Conversion time
Sampling time
–
tCONV
tSAMP
5
Conversion
clockNote/6
ns
4
Zero scale error
Scale error
–
–
LSB
LSB
LSB
V
4
3
Linearity error
–
−0.3
Analog input voltage
Analog input resistance
AVREF input voltage
AVREF input current
AVDD current
VIAN
RAN
AVREF
AIREF
AIDD
AVREF + 0.3
MΩ
V
2
AVREF = AVDD
4.5
5.5
2.0
6
mA
mA
Note Conversion clock is the number of clocks set by the ADM1 register.
75
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
4. PACKAGE DRAWING
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
M
G
H
J
I
K
P
S
L
S
N
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
20.0 0.2
22.0 0.2
1.25
G
H
1.25
0.22 0.05
I
0.08
J
0.5 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.4
0.10 0.05
+4°
3°
R
S
−3°
1.5 0.1
S144GJ-50-UEN
76
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
5. RECOMMENDED SOLDERING CONDITIONS
The µPD703100-33, 703100-40, 703101-33, and 703102-33 should be soldered and mounted under the following
recommended conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 5-1. Surface Mounting Type Soldering Conditions (1/2)
µPD703100GJ-40-UEN:
µPD703100GJ-33-UEN:
µPD703101GJ-33-xxx-UEN:
µPD703102GJ-33-xxx-UEN:
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
(1)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count:
two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
Infrared reflow
VPS
IR35-103-2
Package peak temperature: 215°C, Time: 25 to 40 seconds max. (at 200°C or higher),
Count: two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10
hours)
VP15-103-2
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Partial heating
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, consult an NEC
Electronics sales representative.
µPD703100GJ-33-UEN-A:
144-pin plastic LQFP (fine pitch) (20 × 20)
(2)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
20 to 72 hours)
Infrared reflow
IR60-203-3
−
−
Wave soldering
Partial heating
For details, consult an NEC Electronics sales representative.
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products with -A at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, consult an NEC
Electronics sales representative.
77
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 5-1. Surface Mounting Type Soldering Conditions (2/2)
µPD703100GJ-40-UEN-A:
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703101GJ-33-xxx-UEN-A: 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703102GJ-33-xxx-UEN-A: 144-pin plastic LQFP (fine pitch) (20 × 20)
(3)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
20 to 72 hours)
Infrared reflow
IR60-207-3
−
−
Wave soldering
Partial heating
For details, consult an NEC Electronics sales representative.
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products with -A at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, consult an NEC
Electronics sales representative.
78
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
79
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Related documents µPD70F3102-33 Data Sheet (U13844E)
µPD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E)
µPD70F3102A-33 Data Sheet (U13845E)
Reference materials Electrical Characteristics for Microcomputer (U15170JNote
Note This document number is that of Japanese version.
)
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
80
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
81
Data Sheet U13995EJ2V1DS
µPD703100-33, 703100-40, 703101-33, 703102-33
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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defined above).
M8E 02. 11-1
相关型号：
UPD703103AGJ-UEN-A
Microcontroller, 32-Bit, 50MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144
NEC
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