UPD70F3040YGM-UEU-A_技术文档

DATA SHEET

PRELIMINADRAYTAPRSOHDEUECTT INFORMATION

MOS INTEGRATED CIRCUIT

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

V850/SV1^TM

32-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD70F3038, µPD70F3038Y, µPD70F3040, and µPD70F3040Y are products that substitute flash memory

for the mask ROM of the µPD703038, µPD703038Y, µPD703039, 703040, and 703041, and µPD703039Y, 703040Y,

and 703041Y, respectively. Since the µPD70F3038, µPD70F3038Y, µPD70F3040, and µPD70F3040Y can be read

and written while mounted on the board, these products are ideal for evaluation during system development, multiple-

version small-scale production or quick product release.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

V850/SV1 User’s Manual Hardware:

U14462E

V850 Family^TMUser’s Manual Architecture: U10243E

FEATURES

Pin compatible with µPD703038, 703039, 703040, 703041, 703038Y, 703039Y, 703040Y, and 703041Y

{

•

For mass production, these can be replaced by a mask ROM version.

µPD70F3038F1-EN2→ µPD703038F1-×××-EN2

µPD70F3038YF1-EN2→ µPD703038YF1-×××-EN2

µPD70F3040GM-UEU→ µPD703039GM-×××-UEU, 703040GM-×××-UEU, 703041GM-×××-UEU

µPD70F3040F1-EN2→ µPD703039F1-×××-EN2, 703040F1-×××-EN2

µPD70F3040YGM-UEU→ µPD703039YGM-×××-UEU, 703040YGM-×××-UEU, 703041YGM-×××-UEU

µPD70F3040YF1-EN2→ µPD703039YF1-×××-EN2, 703040YF1-×××-EN2

APPLICATIONS

{

Camcorders (including DVC)

ORDERING INFORMATION

Part Number

Package

µPD70F3038F1-EN2

µPD70F3038YF1-EN2

µPD70F3040GM-UEU

µPD70F3040F1-EN2

µPD70F3040YGM-UEU

µPD70F3040YF1-EN2

180-pin plastic FBGA (13 × 13)

176-pin plastic LQFP (fine pitch) (24 × 24)

180-pin plastic FBGA (13 × 13)

176-pin plastic LQFP (fine pitch) (24 × 24)

180-pin plastic FBGA (13 × 13)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. U14622EJ2V0DS00 (2nd edition)

Date Published July 2001 N CP(K)

Printed in Japan

2000

©

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

DIFFERENCES BETWEEN V850/SV1 PRODUCTS

Internal ROM

Internal RAM

I²C

V^PPPin

Provided

µPD70F3038

µPD70F3038Y

µPD70F3040

µPD70F3040Y

µPD703038

384 KB (flash memory)

16 KB

8 KB

None

Provided

None

256 KB (flash memory)

384 KB (mask ROM)

256 KB (mask ROM)

Provided

None

µPD703038Y

µPD703039

Provided

None

µPD703039Y

µPD703040

Provided

None

16 KB

8 KB

µPD703040Y

µPD703041

Provided

None

192 KB (mask ROM)

µPD703041Y

Provided

2

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

PIN CONFIGURATION

176-pin plastic LQFP (fine pitch) (24 × 24)

µPD70F3040GM-UEU

µPD70F3040YGM-UEU

P12/SCK0/SCL0^{Note 2}

P13/SI1/RXD0

P14/SO1/TXD0

P15/SCK1/ASCK0

P20/SI2/SDA1^{Note 2}

P21/SO2

1

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

P87/ANI15

2

P86/ANI14

3

P85/ANI13

4

P84/ANI12

5

P83/ANI11

6

P82/ANI10

P22/SCK2/SCL1^{Note 2}

P23/SI3/RXD1

P24/SO3/TXD1

P25/SCK3/ASCK1

P26/TI2/TO2

7

P81/ANI9

8

P80/ANI8

9

P77/ANI7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P76/ANI6

P75/ANI5

P27/TI3/TO3

P74/ANI4

V

DD

SS

P73/ANI3

V

P72/ANI2

P30/TI000

P31/TI001

P32/TI010

P33/TI011

P34/TO0

P35/TO1

P36/TI4/TO4

P37/TI5/TO5

P120/SI4

P121/SO4

P122/SCK4

P123/CLO

P124/TI6/TO6

P125/TI7/TO7

P126/TI10/TO10

P127/TI11/TO11

P180

P71/ANI1

P70/ANI0

P147

P146

P145/RTPTRG1

P144/TI9/INTTI9

P143/INTCP93

P142/INTCP92

P141/INTCP91

P140/INTCP90

P137/TO81

P136/TO80

P135/TCLR8/INTTCLR8

P134/TI8/INTTI8

P133/INTCP83

P132/INTCP82

P131/INTCP81

P130/INTCP80

P181

P182

V

SS

DD

P183

P184

98

P07/INTP6

P185

97

P06/INTP5/RTPTRG0

P05/INTP4/ADTRG

P04/INTP3

P186

96

P187

95

V

DD

94

P03/INTP2

V

SS

93

P02/INTP1

P190

P191

P192

P193

92

P01/INTP0

91

P00/NMI

90

P157/RTP17

P156/RTP16

89

Notes 1. Connect to V^SSin the normal operation mode.

2. SCL0, SCL1, SDA0, and SDA1 are valid only for the µPD70F3040Y.

3

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

180-pin plastic FBGA (13 × 13)

µ PD70F3038F1-EN2

µ PD70F3038YF1-EN2

µ PD70F3040F1-EN2

µ PD70F3040YF1-EN2

Top View

Bottom View

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A B C D E F G H J K L M N P R

R P N M L K J H G F E D C B A

Name

Number

A1

A2

NC^{Note 1}

B1

B2

P13/SI1/RXD0

P12/SCK0/SCL0^Note

2

C1

C2

P15/SCK1/ASCK0

P20/SI2/SDA1^{Note 2}

D1

D2

P23/SI3/RXD1

P21/SO2

P11/SO0

A3

A4

P10/SI0/SDA0^{Note 2}

P112

B3

B4

P113

C3

C4

P14/SO1/TXD0

P111

D3

D4

P22/SCK2/SCL1 ^{Note 2}

P24/SO3/TXD1

WAIT

P110

A5

CLKOUT

P62/A18

P57/AD15

P53/AD11

BV^SS

B5

P64/A20

P60/A16

P54/AD12

P50/AD8

P46/AD6

P42/AD2

P94/ASTB

P91/UBEN

AV^DD

C5

P65/A21

D5

A6

B6

C6

P63/A19

D6

P61/A17

A7

B7

C7

P56/AD14

P52/AD10

BV^DD

D7

P55/AD13

A8

B8

C8

D8

P51/AD9

A9

B9

C9

D9

P47/AD7

A10

A11

A12

A13

A14

A15

P45/AD5

P41/AD1

V^SS

B10

B11

B12

B13

B14

B15

C10

C11

C12

C13

C14

C15

P44/AD4

P40/AD0

P93/DSTB/RD

P82/ANI10

P86/ANI14

P85/ANI13

D10

D11

D12

D13

D14

D15

P43/AD3

P96/HLDRQ

P90/LBEN/WRL

P81/ANI9

AV^SS

AV^REF

NC^{Note 1}

V^DD

P84/ANI12

P83/ANI11

P87/ANI15

Notes 1. Leave the NC pin open.

2. SCL0, SCL1, SDA0, and SDA1 are valid only for the µPD70F3038Y and 70F3040Y.

4

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Name

Number

E1

E2

P27/TI3/TO3

P25/SCK3/ASCK1

P26/TI2/TO2

V^SS

H12

H13

H14

H15

J1

P144/TI9/INTTI9

P143/INTCP93

P146

M1

M2

V^DD

P1

P2

P193

P195

P196

P186

E3

M3

P170/KR0

P174/KR4

P177/KR7

P163/PWM3

P167/HSOUT1

RESET

P3

E4

P141/INTCP91

P125/TI7/TO7

P124/TI6/TO6

P126/TI10/TO10

P127/TI11/TO11

P140/INTCP90

P137/TO81

P142/INTCP92

P135/TCLR8/INTTCLR8

P181

M4

P4

P176/KR6

E5

V^DD

M5

P5

P160/PWM0

P164/CSYNCIN

E11

E12

E13

E14

E15

F1

P95/HLDAK

P92/R/W/WRH

P76/ANI6

P77/ANI7

P80/ANI8

P30/TI000

P31/TI001

P32/TI010

P33/TI011

P74/ANI4

P72/ANI2

P75/ANI5

P70/ANI0

P35/TO1

J2

M6

P6

Note 1

J3

M7

P7

V^PP

J4

M8

P8

X2

J12

J13

J14

J15

K1

M9

V^SS

P9

P100/RTP00

P104/RTP04

P107/RTP07

P150/RTP10

P152/RTP12

P153/RTP13

P156/RTP16

NC^{Note 2}

M10

M11

M12

M13

M14

M15

N1

P103/RTP03

P01/INTP0

P04/INTP3

P05/INTP4/ADTRG

P03/INTP2

P06/INTP5/RTPTRG0

P191

P10

P11

P12

P13

P14

P15

R1

F2

F3

F4

K2

P180

F12

F13

F14

F15

G1

K3

P182

K4

P183

K12

K13

K14

K15

L1

P134/TI8/INTTI8

P133/INTCP83

P136/TO80

P132/INTCP82

P185

N2

P192

R2

P194

N3

P197

R3

P171/KR1

P172/KR2

P161/PWM1

P165/VSOUT

XT1

N4

P173/KR3

P175/KR5

P162/PWM2

P166/HSOUT0

V^DD

R4

G2

P34/TO0

N5

R5

G3

P36/TI4/TO4

P37/TI5/TO5

P73/ANI3

P147

N6

R6

G4

L2

P184

N7

R7

G12

G13

G14

G15

H1

L3

P187

N8

R8

XT2

L4

V^SS

N9

X1

R9

P101/RTP01

P105/RTP05

V^SS

P71/ANI1

P145/RTPTRG1

P121/SO4

P120/SI4

L5

P190

N10

N11

N12

N13

N14

N15

P102/RTP02

P106/RTP06

V^DD

R10

R11

R12

R13

R14

R15

L11

L12

L13

L14

L15

V^DD

V^SS

P151/RTP11

P154/RTP14

P155/RTP15

NC ^{Note 2}

H2

P07/INTP6

P131/INTCP81

P130/INTCP80

P157/RTP17

P00/NMI

H3

P122/SCK4

P123/CLO

H4

P02/INTP1

Notes 1. Connect this pin to V^SSduring normal operation mode.

2. Leave the NC pin open.

5

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

PIN IDENTIFICATION

A16 to A21:

AD0 to AD15:

ADTRG:

ANI0 to ANI15:

ASCK0, ASCK1:

ASTB:

Address bus

P120 to P127:

P130 to P137:

P140 to P147:

P150 to P157:

P160 to P167:

P170 to P177:

P180 to P187:

P190 to P197:

PWM0 to PWM3:

RD:

Port 12

Address/data bus

AD trigger input

Port 13

Port 14

Analog input

Port 15

Asynchronous serial clock

Address strobe

Port 16

Port 17

AV^DD:

Analog power supply

Analog reference voltage

Analog ground

Port 18

AV^REF:

Port 19

AV^SS:

Pulse width modulation

Read

BV^DD:

Bus interface power supply

Bus interface ground

Clock output

BV^SS:

RESET:

Reset

CLKOUT:

CLO:

RTP00 to RTP07,:

RTP10 to RTP17

Real-time output port

Clock output (divided)

Csync input

CSYNCIN:

DSTB:

RTPTRG0, RTPTRG1: RTP trigger input

Data strobe

R/W:

Read/write status

Receive data

Serial clock

Serial data

HLDAK:

HLDRQ:

Hold acknowledge

Hold request

RXD0, RXD1:

SCK0 to SCK4:

SCL0, SCL1:

SDA0, SDA1:

SI0 to SI4:

SO0 to SO4:

TCLR8:

HSOUT0, HSOUT1: Hsync output

INTCP80 to INTCP83,: Interrupt request from peripherals

INTCP90 to INTCP93,

Serial input

INTP0 to INTP6,

Serial output

Timer clear

INTTCLR8,

INTTI8, INTTI9

TI000, TI001, TI010,: Timer input

TI011, TI2 to TI11

KR0 to KR7:

LBEN:

Key return

Lower byte enable

TO0 to TO7, TO80,: Timer output

TO81, TO10, TO11

NMI:

Non-maskable interrupt request

P00 to P07:

P10 to P15:

P20 to P27:

P30 to P37:

P40 to P47:

P50 to P57:

P60 to P65:

P70 to P77:

P80 to P87:

P90 to P96:

P100 to P107:

P110 to P113:

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

TXD0, TXD1:

UBEN:

V^DD:

Transmit data

Upper byte enable

Power supply

V^PP:

Programming power supply

Vsync output

VSOUT:

V^SS:

Ground

WAIT:

Wait

WRH:

Write strobe high level data

Write strobe low level data

Crystal for main system clock

Crystal for subsystem clock

WRL:

X1, X2:

XT1, XT2:

6

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

INTERNAL BLOCK DIAGRAM

NMI

INTP0 to INTP6

ROM

CPU

INTC

HLDRQ

HLDAK

INTCP80 to INTCP83,

INTCP90 to INTCP93

INTTCLR8

Instruction

queue

ROM correction

PC

Note 1

ASTB

INTTI8, INTTI9

TI000, TI001,

32-bit barrel

shifter

Timer/counter

16-bit timers:

TM0, TM1

DSTB/RD

R/W/WRH

UBEN

LBEN/WRL

WAIT

A16 to A21

AD0 to AD15

Multiplier

16 × 16 → 32

TI010, TI011

TO0, TO1

System

registers

8-bit timers

TM2 to TM7,

TM10, TM11

:

BCU

RAM

TO80, TO81

TI8, TI9

ALU

General registers

32 bits × 32

24-bit timers:

TM8, TM9

TCLR8

16 KB

TI2/TO2, TI3/TO3

TI4/TO4, TI5/TO5

TI6/TO6, TI7/TO7

TI10/TO10, TI11/TO11

CSYNCIN

Vsync/Hsync

SIO

HSOUT0, HSOUT1,

VSOUT

SO0

SI0/SDA0^{Note 2}

SCK0/SCL0^{Note 2}

SO2

CSI0/I²C0^{Note 3}

CSI2/I²C1^{Note 3}

CSI1/UART0

CSI3/UART1

CLKOUT

Ports

A/D

converter

CLO

X1

X2

XT1

XT2

RESET

SI2/SDA1^{Note 2}

SCK2/SCL1^{Note 2}

SO1/TXD0

SI1/RXD0

CG

SCK1/ASCK0

SO3/TXD1

SI3/RXD1

SCK3/ASCK1

SO4

V

BVDD

BVSS

DD

SS

Variable-

length CSI4

SI4

SCK4

Watch timer

KR0 to KR7

Key return function

DMAC: 6 ch

PWM

Watchdog timer

V

PP

RTP00 to RTP07,

RTP10 to RTP17

RTPTRG0,

RTP

PWM0 to PWM3

RTPTRG1

Notes 1. 384 KB: µPD70F3038, 70F3038Y (flash memory)

256 KB: µPD70F3040, 70F3040Y (flash memory)

2. SDA0, SDA1, SCL0, and SCL1 are valid only for the 70F3038Y and µPD70F3040Y.

3. The I²C function is valid only for the µPD703038Y and 70F3040Y.

7

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

CONTENTS

1. PIN FUNCTIONS.................................................................................................................................. 9

1.1 Port Pins ....................................................................................................................................................9

1.2 Non-Port Pins...........................................................................................................................................13

1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins........................17

2. ELECTRICAL SPECIFICATIONS ..................................................................................................... 21

3. PACKAGE DRAWING....................................................................................................................... 44

4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 46

Preliminary Data Sheet U14622EJ1V0DS00

8

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

1. PIN FUNCTIONS

1.1 Port Pins

(1/4)

Pin Name

P00

I/O

PULL

Yes

Function

Alternate Function

NMI

Port 0

8-bit I/O port

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

P40

P41

P42

P43

P44

INTP0

Input/output mode can be specified in 1-bit units.

INTP1

INTP2

INTP3

INTP4/ADTRG

INTP5/RTPTRG0

INTP6

I/O

Yes

Port 1

SI0/SDA0

SO0

6-bit I/O port

Input/output mode can be specified in 1-bit units.

SCK0/SCL0

SI1/RXD0

SO1/TXD0

SCK1/ASCK0

SI2/SDA1

SO2

I/O

Yes

Port 2

8-bit I/O port

Input/output mode can be specified in 1-bit units.

SCK2/SCL1

SI3/RXD1

SO3/TXD1

SCK3/ASCK1

TI2/TO2

TI3/TO3

TI000

I/O

Yes

Port 3

8-bit I/O port

TI001

Input/output mode can be specified in 1-bit units.

TI010

TI011

TO0

TO1

TI4/TO4

TI5/TO5

AD0

I/O

No

Port 4

8-bit I/O port

AD1

Input/output mode can be specified in 1-bit units.

AD2

AD3

AD4

Remark PULL: On-chip pull-up resistor

9

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(2/4)

Pin Name

P45

I/O

PULL

No

Function

Alternate Function

AD5

Port 4

8-bit I/O port

P46

P47

P50

P51

P52

P53

P54

P55

P56

P57

P60

P61

P62

P63

P64

P65

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P82

P83

P84

P85

P86

P87

P90

P91

P92

P93

AD6

Input/output mode can be specified in 1-bit units.

AD7

I/O

No

Port 5

AD8

8-bit I/O port

AD9

Input/output mode can be specified in 1-bit units.

AD10

AD11

AD12

AD13

AD14

AD15

A16

I/O

No

Port 6

6-bit I/O port

A17

Input/output mode can be specified in 1-bit units.

A18

A19

A20

A21

Input

No

Port 7

ANI0

8-bit input port

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Input

No

Port 8

ANI8

8-bit input port

ANI9

ANI10

ANI11

ANI12

ANI13

ANI14

ANI15

LBEN/WRL

UBEN

R/W/WRH

DSTB/RD

I/O

No

Port 9

7-bit I/O port

Input/output mode can be specified in 1-bit units.

Remark PULL: On-chip pull-up resistor

10

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(3/4)

Pin Name

P94

I/O

PULL

No

Function

Alternate Function

ASTB

Port 9

7-bit I/O port

P95

HLDAK

HLDRQ

RTP00

RTP01

RTP02

RTP03

RTP04

RTP05

RTP06

RTP07

Input/output mode can be specified in 1-bit units.

P96

P100

P101

P102

P103

P104

P105

P106

P107

P110

P111

P112

P113

P120

P121

P122

P123

P124

P125

P126

P127

P130

P131

P132

P133

P134

P135

P136

P137

P140

P141

P142

P143

P144

P145

P146

P147

I/O

Yes

Port 10

8-bit I/O port

Input/output mode can be specified in 1-bit units.

I/O

No

Port 11

–

4-bit I/O port

Input/output mode can be specified in 1-bit units.

Port 12

SI4

8-bit I/O port

SO4

Input/output mode can be specified in 1-bit units.

SCK4

CLO

TI6/TO6

TI7/TO7

TI10/TO10

TI11/TO11

INTCP80

INTCP81

INTCP82

INTCP83

TI8/INTTI8

TCLR8/INTTCLR8

TO80

I/O

No

Port 13

8-bit I/O port

Input/output mode can be specified in 1-bit units.

TO81

I/O

No

Port 14

INTCP90

INTCP91

INTCP92

INTCP93

TI9/INTTI9

RTPTRG1

–

8-bit I/O port

Input/output mode can be specified in 1-bit units.

–

Remark PULL: On-chip pull-up resistor

11

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(4/4)

Pin Name

P150

I/O

PULL

No

Function

Alternate Function

RTP10

Port 15

8-bit I/O port

P151

P152

P153

P154

P155

P156

P157

P160

P161

P162

P163

P164

P165

P166

P167

P170

P171

P172

P173

P174

P175

P176

P177

P180

P181

P182

P183

P184

P185

P186

P187

P190

P191

P192

P193

P194

P195

P196

P197

RTP11

RTP12

RTP13

RTP14

RTP15

RTP16

RTP17

PWM0

PWM1

PWM2

PWM3

CSYNCIN

VSOUT

HSOUT0

HSOUT1

KR0

Input/output mode can be specified in 1-bit units.

I/O

No

Yes

No

Port 16

8-bit I/O port

Input/output mode can be specified in 1-bit units.

Port 17

8-bit I/O port

KR1

Input/output mode can be specified in 1-bit units.

KR2

KR3

KR4

KR5

KR6

KR7

Port 18

–

8-bit I/O port

Input/output mode can be specified in 1-bit units.

No

Port 19

8-bit I/O port

Input/output mode can be specified in 1-bit units.

Remark PULL: On-chip pull-up resistor

12

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

1.2 Non-Port Pins

(1/4)

Pin Name

A16 to A21

AD0 to AD7

AD8 to AD15

ADTRG

I/O

PULL

No

Function

Alternate Function

P60 to P65

P40 to P47

P50 to P57

P05/INTP4

P70 to P77

P80 to P87

P15/SCK1

P25/SCK3

P94

Output

I/O

Address bus 16 to 21

No

Address/data multiplexed bus 0 to 15

Input

Yes

No

A/D converter external trigger input

Analog input to A/D converter

ANI0 to ANI7

ANI8 to ANI15

ASCK0

No

Yes

Baud rate clock input for UART0 and UART1

External address strobe signal output

ASCK1

ASTB

Output

–

No

–

AV^''

Positive power supply for A/D converter and ports used for

alternate functions

–

AV⁵⁽⁾

AV⁶⁶

Input

–

Reference voltage input for A/D converter

–

Ground potential for A/D converter and ports used for alternate

functions

BV^''

BV⁶⁶

–

Positive power supply for bus interface and ports used for

alternate functions

–

Ground potential for bus interface and ports used for alternate

functions

CLKOUT

CLO

Output

Input

–

Internal system clock output

CLO output signal

–

P123

No

CSYNCIN

DSTB

Csync signal input

P164

Output

Input

External data strobe signal output

Bus hold acknowledge output

Bus hold request input

P93/RD

P95

HLDAK

HLDRQ

HSOUT0

HSOUT1

P96

Output

Hsync signal output before compensation

Hsync signal output after compensation

External capture input for CC80 to CC83

P166

P167

INTCP80 to

INTCP83

Input

No

P130 to P133

INTCP90 to

INTCP93

External capture input for CP90 to CP93

P140 to P143

INTP0 to INTP3

INTP4

Yes

External interrupt request input (analog noise elimination)

External interrupt request input (digital noise elimination)

P01 to P04

P05/ADTRG

P06/RTPTRG0

P07

INTP5

INTP6

External interrupt request input (digital noise elimination

supporting remote controller)

Remark PULL: On-chip pull-up resistor

13

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(2/4)

Pin Name

INTTCLR8

INTTI8

I/O

PULL

No

Function

Alternate Function

P135/TCLR8

P134/TI8

P144/TI9

P170 to P177

P90/WRL

P00

Input

External interrupt request input (digital noise elimination)

No

INTTI9

KR0 to KR7

LBEN

Input

Output

Input

Yes

No

Yes

No

–

Key return input

Lower byte enable signal output for external data bus

Non-maskable interrupt request input

Output of PWM channels 0 to 3

Bus read strobe signal output

System reset input

NMI

PWM0 to PWM3 Output

P160 to P163

P93/DSTB

–

RD

Output

Input

RESET

RTP00 to RTP07 Output

RTP10 to RTP17

Yes

No

Real-time output port

P100 to P107

P150 to P157

P06

RTPTRG0

RTPTRG1

R/W

Input

Yes

No

RTP external trigger input

P145

Output

Input

No

External read/write status output

P92/WRH

P13/SI1

RXD0

RXD1

SCK0

SCK1

SCK2

SCK3

SCK4

SCL0

SCL1

SDA0

SDA1

SI0

Yes

Serial receive data input for UART0 and UART1

P23/SI3

I/O

Yes

Serial clock I/O for CSI0 to CSI3 (3-wire mode)

P12/SCL0

P15/ASCK0

P22/SCL1

P25/ASCK1

P122

No

Variable-length CSI4 serial clock I/O

ꢀ

I/O

Yes

Serial clock I/O for I C0 and I C1

P12/SCK0

P22/SCK2

P10/SI0

(µPD70F3038Y, 70F3040Y)

ꢀ

Yes

Serial transmit/receive data I/O for I C0 and I C1

(µPD70F3038Y, 70F3040Y)

P20/SI2

Input

Serial receive data input for CSI0 to CSI3 (3-wire mode)

P10/SDA0

P13/RXD0

P20/SDA1

P23/RXD1

P120

SI1

SI2

SI3

SI4

No

Variable-length CSI4 serial receive data input

Serial transmit data output for CSI0 to CSI3

SO0

Output

Yes

P11

SO1

P14/TXD0

P21

SO2

SO3

P24/TXD1

P121

SO4

No

Variable-length CSI4 serial transmit data output

External clear input for TM8

TCLR8

Input

P135/INTTCLR8

Remark PULL: On-chip pull-up resistor

14

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(3/4)

Pin Name

TI000

I/O

PULL

Yes

Function

External count clock input/external capture trigger input for TM0

External capture trigger input for TM0

External count clock input/external capture trigger input for TM1

External capture trigger input for TM1

External count clock input for TM2

External count clock input for TM3

External count clock input for TM4

External count clock input for TM5

External count clock input for TM6

External count clock input for TM7

External count clock input for TM8

External count clock input for TM9

External count clock input for TM10

External count clock input for TM11

Pulse signal output for TM0

Alternate Function

P30

Input

TI001

TI010

TI011

TI2

P31

P32

P33

P26/TO2

P27/TO3

P36/TO4

P37/TO5

P124/TO6

P125/TO7

P134/INTTI8

P144/INTTI9

P126/TO10

P127/TO11

P34

TI3

TI4

TI5

TI6

No

TI7

TI8

TI9

TI10

TI11

TO0

TO1

TO2

TO3

TO4

TO5

TO6

TO7

TO80

TO81

TO10

TO11

TXD0

TXD1

UBEN

V^''

Output

Yes

Pulse signal output for TM1

P35

Pulse signal output for TM2

P26/TI2

P27/TI3

P36/TI4

P37/TI5

P124/TI6

P125/TI7

P136

Pulse signal output for TM3

Pulse signal output for TM4

Pulse signal output for TM5

No

Pulse signal output for TM6

Pulse signal output for TM7

Pulse signal output 0 for TM8

Pulse signal output 1 for TM8

P137

Pulse signal output for TM10

P126/TI10

P127/TI11

P14/SO1

P24/SO3

P91

Pulse signal output for TM11

Output

Yes

Serial transmit data output for UART0 and UART1

Output

–

No

–

Higher byte enable signal output for external data bus

Positive power supply pin

–

V³³

–

High voltage application pin for program write/verify

Vsync signal output

–

VSOUT

V⁶⁶

Output

–

No

–

P165

Ground potential

–

WAIT

WRH

WRL

Input

Output

–

External WAIT signal input

–

No

Higher byte write strobe signal output for external data bus

Lower byte write strobe signal output for external data bus

P92/R/W

P90/LBEN

Remark PULL: On-chip pull-up resistor

15

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(4/4)

Pin Name

I/O

Input

–

PULL

–

Function

Alternate Function

X1

X2

Resonator connection for main system clock

–

XT1

XT2

Input

–

Resonator connection for subsystem clock

Remark PULL: On-chip pull-up resistor

16

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins

Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins.

For the I/O configuration of each circuit type, refer to Figure 1-1.

Table 1-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)

Alternate Function

I/O Circuit

Type

I/O Buffer

Power Supply

Recommended Connection Method

P00

NMI

5-W

V^DD

Input:

Independently connect to V^DDor V^SS

via a resistor

P01 to P04

P05

INTP0 to INTP3

INTP4/ADTRG

INTP5/RTPTRG0

INTP6

Output: Leave open

P06

P07

P10

SI0/SDA0

SO0

10-F

10-E

10-F

5-W

10-E

10-F

10-E

10-F

5-W

10-E

10-F

5-W

V^DD

P11

P12

SCK0/SCL0

SI1/RXD0

SO1/TXD0

SCK1/ASCK0

SI2/SDA1

SO2

P13

P14

P15

P20

V^DD

P21

P22

SCK2/SCL1

SI3/RXD1

SO3/TXD1

SCK3/ASCK1

TI2/TO2, TI3/TO3

TI000, TI001

TI010, TI011

TO0, TO1

TI4/TO4

P23

P24

P25

P26, P27

P30, P31

P32, P33

P34, P35

P36

V^DD

5-A

5-W

P37

TI5/TO5

P40 to P47

P50 to P57

P60 to P65

P70 to P77

P80 to P87

P90

AD0 to AD7

AD8 to AD15

A16 to A21

ANI0 to ANI7

ANI8 to ANI15

LBEN/WRL

UBEN

5

9

5

BV^DD

AV^DD

BV^DD

Input:

Independently connect to BVDD or BVSS

via a resistor

Output: Leave open

Connect to AV^SS

Input:

Independently connect to BVDD or BVSS

via a resistor

Output: Leave open

P91

P92

R/W/WRH

DSTB/RD

ASTB

P93

P94

P95

HLDAK

P96

HLDRQ

P100 to P107

P110 to P113

P120

RTP00 to RTP07

–

10-E

5

V^DD

Input:

Independently connect to VDD or VSS

via a resistor

Output: Leave open

SI4

5-K

17

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Table 1-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)

Alternate Function

I/O Circuit

Type

I/O Buffer

Power Supply

Recommended Connection Method

P121

P122

P123

P124

P125

P126

P127

SO4

10-G

10-H

5

V^DD

Input:

Independently connect to V^DDor V^SS

via a resistor

SCK4

Output: Leave open

CLO

TI6/TO6

5-K

TI7/TO7

TI10/TO10

TI11/TO11

P130 to P133

P134

INTCP80 to INTCP83

5-K

V^DD

TI8/INTTI8

P135

TCLR8/INTTCLR8

P136, P137

P140 to P143

P144

TO80, TO81

5

INTCP90 to INTCP93

5-K

V^DD

TI9/INTTI9

P145

RTPTRG1

P146, P147

P150 to P157

P160 to P163

P164

–

5

RTP10 to RTP17

5

V^DD

PWM0 to PWM3

5

CSYNCIN

5-K

5

P165

VSOUT

P166

HSOUT0

P167

HSOUT1

P170 to P177

P180 to P187

P190 to P197

CLKOUT

WAIT

KR0 to KR7

5-K

V^DD

BV^DD

V^DD

–

5

4

Leave open

Connect to V^DDvia a resistor

–

1

RESET

X1

2

–

X2

–

Leave open

Connect to V^SS

Leave open

Connect to AV^SS

Connect to V^SS

–

XT1

16-A

XT2

16-A

AV^REF

–

V^PP

–

V^DD

–

V^SS

–

AV^DD

–

Connect to V^DD

Connect to V^SS

Connect to V^DD

Connect to V^SS

AV^SS

–

BV^DD

–

BV^SS

–

18

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Figure 1-1. Pin I/O Circuits (1/2)

Type 1

Type 5

V

DD

V

DD

Data

P-ch

IN/OUT

IN

Output

disable

N-ch

Input

enable

Type 2

Type 5-A

V

DD

Pullup

enable

P-ch

VDD

Data

P-ch

N-ch

IN

IN/OUT

Output

disable

Input

Schmitt-triggered input with hysteresis characteristics

Type 4

enable

Type 5-K

V

DD

V

DD

Data

P-ch

N-ch

Data

P-ch

IN/OUT

OUT

Output

disable

Output

disable

N-ch

Input

enable

Push-pull output that can be set to high impedance output

(both P-ch and N-ch are off)

19

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Figure 1-1. Pin I/O Circuits (2/2)

Type 5-W

Type 10-G

V

DD

V

DD

Pull-up

enable

Data

P-ch

V

DD

IN/OUT

Data

P-ch

Open drain

N-ch

IN/OUT

Output

disable

Output

disable

N-ch

Input

enable

Input

enable

Type 9

Type 10-H

V

DD

P-ch

N-ch

Data

P-ch

N-ch

Comparator

+

–

IN

IN/OUT

Open drain

Output

V

REF (Threshold voltage)

disable

Input enable

Input

enable

Type 10-E

Type 16-A

V

DD

Pull-up

enable

P-ch

V

DD

Data

P-ch

IN/OUT

Open

Output

disable

N-ch

XT1

XT2

Input

enable

Type 10-F

V

DD

Pull-up

enable

P-ch

V

DD

Data

P-ch

N-ch

IN/OUT

Open

Output

disable

Input

enable

20

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25°C, V^SS= 0 V)

Parameter

Supply voltage

Symbol

V^DD

Conditions

Ratings

Unit

V

–0.5 to +4.6

V^PP

–1.5 to +8.5

V

AV^DD

BV^DD

V^SS

–0.5 to +4.6

–0.5 to +0.5

V

AV^SS

BV^SS

V^I1

V^I2

V^K

V^IAN

AV^REF

I^OL

–0.5 to +0.5

V

–0.5 to +0.5

V

mA

Input voltage

Note 1 (V^DD)

Note 2 (BV^DD)

X1, V^DD= 2.7 to 3.6 V

Note 3 (AV^DD)

AV^REFpin

Per pin

Total for P00 to P07 and P150 to P157

Total for P100 to P107 and P160 to P167

Total for P170 to P177 and P190 to P197

Total for P124 to P127 and P180 to P187

Total for P30 to P37 and P120 to P123

–0.5 to V^DD+ 0.5^{Note 4}

–0.5 to BV^DD+ 0.5^{Note 4}

Clock input voltage

–0.5 to V^DD+ 1.0^{Note 4}

Analog input voltage

Analog reference input voltage

Output current, low

–0.5 to AV^DD+ 0.5^{Note 4}

4.0

25

Total for P12 to P15, P20 to 27, and P110

to P113

Total for P50 to P57, P60 to P65, and

CLKOUT

25

mA

Total for P40 to P47 and P90 to P96

Total for P130 to P137 and P140 to P147

Per pin

Total for P00 to P07 and P150 to P157

Total for P100 to P107 and P160 to P167

Total for P170 to P177 and P190 to P197

Total for P124 to P127 and P180 to P187

Total for P30 to P37 and P120 to P123

25

mA

Output current, high

I^OH

–4.0

–25

Total for P12 to P15, P20 to 27, and P110

to P113

Total for P50 to P57, P60 to P65, and

CLKOUT

–25

mA

Total for P40 to P47 and P90 to P96

Total for P130 to P137 and P140 to P147

Note 1, V^DD= 2.7 to 3.6V

Note 2, CLKOUT, BV^DD= 2.7 to 3.6V

Normal operation mode

–25

mA

V

Output voltage

V^O1

V^O2

T^A

–0.5 to V^DD+ 0.5^{Note 4}

–0.5 to BV^DD+ 0.5^{Note 4}

–40 to +85

V

Operating ambient temperature

Storage temperature

°C

Flash programming mode

+10 to +40

–40 to +125

T^stg

Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 (includes alternate function pins)

2. Ports 4, 5, 6, and 9 (includes alternate function pins)

3. Ports 7 and 8 (includes alternate function pins)

4. Be sure not to exceed each absolute maximum rating (MAX.).

21

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between V^DDor V^CC

and GND. However, direct connections among open-drain and open-connector pins are

possible, as are direct connections to external circuits that have timing designed to prevent

output contention with pins that become high-impedance.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions indicated for DC characteristics and AC characteristics represent

the quality assurance range during normal operation.

Capacitance (T^A= 25°C, V^DD= AV^DD= BV^DD= V^SS= 0 V = AV^SS= BV^SS)

Parameter

Input capacitance

Symbol

C^I

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f^C= 1 MHz

Unmeasured pins returned to 0 V

I/O capacitance

C^IO

15

pF

Output capacitance

C^O

15

pF

Operating Conditions

(1) CPU operating frequency

Parameter

Symbol

Conditions

V^DD= 2.7 to 3.6 V

MIN.

0.5

TYP.

MAX.

16

20

Unit

CPU operating

frequency

f^CPU

MHz

V^DD= 3.1 to 3.6 V

(2) Operating frequency for each supply voltage

Operating Frequency

4 MHz ≤ f^XX≤ 16 MHz

Supply Voltage (V^DD= AV^DD= BV^DD)

2.7 to 3.6 V

3.1 to 3.6 V

2.7 to 3.6 V

4 MHz ≤ f^XX≤ 20 MHz

f^XT= 32.768 kHz (only watch operation)

22

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Recommended Oscillator

(1) Main clock oscillator (T^A= −40 to +85°C)

(a) Ceramic or crystal resonator connection

X2

X1

Parameter

Symbol

f^XX

Conditions

V^DD= 2.7 to 3.6 V

V^DD= 3.1 to 3.6 V

After reset release

MIN.

TYP.

MAX.

16

Unit

MHz

s

Oscillation frequency

4

20

Oscillation stabilization

time

2¹⁹/f^XX

After STOP mode release

Note

s

Note Values vary depending on the settings of the oscillation stabilization selection register (OSTS).

Remarks 1. Place the oscillator as close as possible to X1 and X2.

2. Do not wire other signal lines within the broken lines.

3. For resonator selection and oscillation constants, customers are advised to either evaluate the

oscillation themselves, or apply to the resonator manufacturer for evaluation.

(b) External clock input

X1

X2

Open

High-speed CMOS inverter

External clock

Parameter

Symbol

f^XX

Conditions

MIN.

TYP.

MAX.

16

Unit

MHz

Input frequency

V^DD= 2.7 to 3.6 V

V^DD= 3.1 to 3.6 V

4

20

Cautions 1. Place the high-speed CMOS inverter as close as possible to the X1 pin.

2. Perform sufficient evaluation to determine whether the µPD70F3038, 70F3038Y, 70F3040, or

70F3040Y matches the high-speed inverter.

23

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(2) Subclock oscillator (T^A= −40 to +85°C)

XT1

XT2

Parameter

Symbol

f^XT

Conditions

MIN.

32

TYP.

32.768

10

MAX.

35

Unit

kHz

s

Oscillation frequency

Oscillation stabilization time

V^DD= 2.7 to 3.6 V

Remarks 1. Place the oscillator as close as possible to XT1 and XT2.

2. Do not wire other signal lines within the broken lines.

3. For resonator selection and oscillation constants, customers are advised to either evaluate the

oscillation themselves, or apply to the resonator manufacturer for evaluation.

24

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

DC Characteristics

(1) 16 MHz operation (T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V)

Parameter

Symbol

V^IH1

V^IH2

V^IH3

V^IH4

V^IH5

V^IL1

Conditions

Pins in Note 1, WAIT

MIN.

0.7BV^DD

0.7V^DD

0.75V^DD

0.7AV^DD

0.8V^DD

BV^SS

TYP.

MAX.

BV^DD

Unit

V

Input voltage, high

Pins in Note 2

Pins in Note 3, RESET

Pins in Note 4

X1

V^DD

V

V^DD

V

AV^DD

V

V^DD

V

Input voltage, low

Pins in Note 1, WAIT

Pins in Note 2

Pins in Note 3, RESET

Pins in Note 4

X1

0.3BV^DD

0.3V^DD

0.2V^DD

0.3AV^DD

0.2V^DD

V

V^IL2

V^SS

V

V^IL3

V^SS

V

V^IL4

AV^SS

V

V^IL5

V^SS

V

V^PPsupply current

V^PP1

V^OH1

VOH2

V^OL1

V^OL2

During normal operation

Note 1, CLKOUT

Notes 2, 3

0

V

Output voltage, high

I^OH= –3 mA

I^OH= –1 mA

0.8BV^DD

0.8V^DD

V

Output voltage, low

Note 1, CLKOUT

0.4

V

Notes 2, 3 (excluding

V

P10, P12, P20, P22)

V^OL3

I^LIH1

I^LIH2

I^LIL1

ILIL2

I^LOH

I^LOL

I^DD1

I^DD2

I^DD3

I^DD4

P10, P12, P20, P22

0.4

5

V

Input leakage current, high

Input leakage current, low

V^I= V^DD= AV^DD= BV^DD

Other than X1

µA

mA

µA

X1

20

–5

–20

5

V^I= 0 V

Other than X1

X1

Output leakage current, high

Output leakage current, low

Supply current

V^O= V^DD= AV^DD= BV^DD

V^O= 0 V

–5

58

32

9

Normal operation (f^XX= 16 MHz)

HALT mode (f^XX= 16 MHz)

IDLE mode (f^XX= 16 MHz)

40

19

6

STOP mode (subclock operation: f^XT=

32.768 kHz, watch timer operation

13

115

STOP mode (subclock stopped, XT1 = V^SS)

V^IN= 0V

5

100

µA

kΩ

Pull-up resistor

R^L

10

30

Notes 1. Ports 4, 5, 6, and 9 (includes alternate function pins)

2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147, P150 to

P157, P160 to P163, P165 to P167, P180 to P187, and P190 to P197 (includes alternate function pins)

3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124

to P127, P130 to P135, P140 to P145, P164, and P170 to P177 (includes alternate function pins)

4. Ports 7, and 8 (includes alternate function pins)

Caution The TYP. value of VDD is 3.3 V. The current that is consumed at output buffers is not included.

25

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(2) 20 MHz operation

(T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 3.1 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, high

V^IH1

V^IH2

V^IH3

V^IH4

V^IH5

V^IL1

V^IL2

V^IL3

V^IL4

V^IL5

V^PP1

V^OH1

V^OH2

V^OL1

V^OL2

Pins in Note 1, WAIT

0.7 BV^DD

0.7 V^DD

0.75 V^DD

0.7 AV^DD

0.8 V^DD

BV^SS

BV^DD

V^DD

V

Pins in Note 2

Pins in Note 3, RESET

Pins in Note 4

X1

V^DD

AV^DD

V^DD

Input voltage, low

Pins in Note 1, WAIT

Pins in Note 2

Pins in Note 3, RESET

Pins in Note 4

X1

0.3 BV^DD

0.3 V^DD

0.2 V^DD

0.3 AV^DD

0.2 V^DD

V^SS

AV^SS

V^SS

V^PPsupply voltage

Output voltage, high

Normal operation

Note 1, CLKOUT

Notes 2, 3

0

I^OH= −3 mA

I^OH= −1 mA

I^OL= 1.6 mA

0.8 BV^DD

0.8 V^DD

Output voltage, low

Note 1, CLKOUT

0.4

Notes 2, 3 (excluding I^OL= 1.6 mA

P10, P12, P20, P22)

V^OL3

I^LIH1

I^LIH2

I^LIL1

I^LIL2

I^LOH

P10, P12, P20, P22

I^OL= 3 mA

0.4

5

V

Input leakage current,

high

V^I= V^DD= AV^DD= Other than X1

µA

BV^DD

X1

20

−5

−20

5

Input leakage current, low

V^I= 0 V

Other than X1

X1

Output leakage current,

high

V^O= V^DD= AV^DD= BV^DD

Output leakage current,

Supply current

I^LOL

I^DD1

I^DD2

I^DD3

I^DD4

V^O= 0 V

−5

64

µA

mA

µA

Normal operation (f^XX= 20 MHz)

HALT mode (f^XX= 20 MHz)

45

20

6.5

13

35

IDLE mode (f^XX= 20 MHz)

10

STOP mode (subclock operation: f^XT=

32.768 kHz, watch timer operation)

115

STOP mode (subclock stopped, XT1 = V^SS

)

5

100

µA

kΩ

Pull-up resistor

R^L

V^IN= 0 V

10

30

Notes 1. Ports 4, 5, 6, and 9 (includes alternate function pins)

2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,

P150 to P157, P160 to P163, P165 to P167, P180 to P187, and P190 to P197 (includes alternate function

pins)

3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124

to P127, P130 to P135, P140 to P145, P164, and P170 to P177 (includes alternate function pins)

5. Ports 7 and 8 (includes alternate function pins)

Caution The TYP. value of V^DDis 3.3 V. The current that is consumed at output buffers is not included.

26

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Data Retention Characteristics

(T^A= –40 to +85°C, V^SS= AV^SS= BV^SS= 0 V, C^L= 50pF)

Parameter

Data retention voltage

Data retention current

Supply voltage rise time

Supply voltage fall time

Symbol

V^DDDR

I^DDDR

t^RVD

Conditions

STOP mode

MIN.

1.8

TYP.

5

MAX.

3.6

Unit

V

V^DDDR[V], XT1 = V^SS

100

µA

µs

200

0

t^FVD

µs

Supply voltage hold time

(from STOP mode setting)

t^HVD

ms

STOP release signal input time

t^DREL

V^IHDR

V^ILDR

0

V^IHn

0

ms

V

Data retention high-level input voltage

Data retention low-level input voltage

All input ports

V^DDDR

V^ILn

V

Remark n = 1 to 5

Setting STOP mode

2.7 V

t

FVD

t

RVD

V

DD

V

DDDR

t

HVD

t

DREL

V

IHDR

RESET (input)

IHDR

STOP release interrupt (NMI, etc.)

(when STOP mode is released

at falling edge)

STOP release interrupt (NMI, etc.)

(when STOP mode is released

at rising edge)

V

ILDR

Cautions 1. Be sure to shift to and return from STOP mode when V^DDis 2.7 V or higher (when fxx = 16

MHz) and V^DD= 3.1 V or higher (when fxx = 20 MHz).

2. V^DD= 2.7 V is the lowest operating voltage (when fxx = 16 MHz) of the V850/SV1.

27

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

AC Characteristics

AC Test Input Measurement points (V^DD, BVDD, AVDD)

V

DD

V

IH

IL

V

IH

Measurement

points

V

IL

0 V

AC Test Output Measurement points (BV^DD, VDD)

BVDD

V

OH

OL

V

OH

Measurement

points

V

OL

0 V

Load Conditions

DUT

(Device Under Test)

CL = 50 pF

Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load

capacitance of the device to 50 pF or less by inserting a buffer or by some other means.

28

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Clock Timing

(1) 16 MHz operation

(T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter

X1 input cycle

Symbol

Conditions

MIN.

62.5

28.2

MAX.

250

Unit

ns

t^CYX

<1>

<2>

<3>

<4>

<5>

<6>

<7>

<8>

<9>

<10>

X1 input high-level width

X1 input low-level width

X1 input rise time

t^WXH

t^WXL

t^XR

ns

0.5 (<1>−<2>−<3>)

2 µs

ns

X1 input fall time

t^XF

ns

CLKOUT output cycle

CLKOUT high-level width

CLKOUT low-level width

CLKOUT rise time

t^CYK

t^WKH

t^WKL

t^KR

62.5 ns

0.4t^CYK−10

ns

10

CLKOUT fall time

t^KF

(2) 20 MHz operation

(T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 3.1 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter

X1 input cycle

Symbol

<1>

Conditions

MIN.

50.0

22.5

MAX.

250

Unit

ns

t^CYX

t^WXH

t^WXL

t^XR

<2>

<3>

<4>

<5>

<6>

<7>

<8>

<9>

<10>

X1 input high-level width

X1 input low-level width

X1 input rise time

ns

0.5 (<1>−<2>−<3>)

2µs

ns

X1 input fall time

t^XF

ns

CLKOUT output cycle

CLKOUT high-level width

CLKOUT low-level width

CLKOUT rise time

t^CYK

t^WKH

t^WKL

t^KR

50 ns

0.4t^CYK−10

ns

10

CLKOUT fall time

t^KF

29

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Clock Timing

<1>

<2>

<3>

X1 (input)

<4>

<5>

<6>

<7>

<8>

CLKOUT (output)

<9>

<10>

Timing of Pins Other Than CLKOUT, P4, P5, P6, and P9 Pins

(T^A= –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

20

Unit

ns

Output rise time

Output fall time

t^OR

t^OF

<11>

<12>

20

ns

<11>

<12>

Output signal

30

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Bus Timing (CLKOUT Asynchronous)

(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

ns

Address setup time (to ASTB↓)

Address hold time (from ASTB↓)

Delay time from DSTB↓ to address float

Setup time from address to data input

Setup time from DSTB↓ to data input

Delay time from ASTB↓ to DSTB↓

Data input hold time (from DSTB↑)

Address output time from DSTB↑

Delay time from DSTB↑ to ASTB↑

Delay time from DSTB↑ to ASTB↓

DSTB low-level width

t^SAST

t^HSTA

t^FDA

<13>

<14>

<15>

<16>

<17>

<18>

<19>

<20>

<21>

<22>

<23>

<24>

<25>

<26>

<27>

<28>

<29>

<30>

<31>

<32>

<33>

<34>

<35>

<36>

<37>

<38>

<39>

<40>

0.5T – 20

0.5T – 15

2

t^SAID

(2 + n)T – 30

(1 + n)T – 30

t^SDID

t^DSTD

0.5T – 15

0

t^HDID

t^DDA

(1 + i)T – 15

0.5T – 15

(1.5 + i)T – 15

(1 + n)T – 15

T – 15

t^DDST1

t^DDST2

t^WDL

ASTB high-level width

t^WSTH

t^DDOD

t^SODD

t^HDOD

t^SAWT1

t^SAWT2

t^HAWT1

t^HAWT2

t^SSTWT1

t^SSTWT2

t^HSTWT1

t^HSTWT2

t^WHQH

t^WHAL

t^DHAC

Data output time from DSTB↓

Data output setup time (to DSTB↑)

Data output hold time (from DSTB↑)

WAIT setup time (to address)

15

(1 + n)T – 20

T – 15

n ≥ 1

1.5T – 30

(1.5 + n)T – 30

WAIT hold time (from address)

WAIT setup time (to ASTB↓)

WAIT hold time (from ASTB↓)

(0.5 + n)T

(1.5 + n)T

T – 25

(1 + n)T – 25

nT + 5

(1 + n)T + 5

T + 10

T – 15

0

HLDRQ high-level width

HLDAK low-level width

Delay time from HLDAK↑ to bus output

Delay time from HLDRQ↓ to HLDAK↓

Delay time from HLDRQ↑ to HLDAK↑

t^DHQHA1

t^DHQHA2

(2n + 7.5)T + 25

1.5T + 25

0.5T

Remarks 1. T = 1/f^CPU(f^CPU: CPU operation clock frequency)

2. n: Number of wait clocks inserted in the bus cycle.

Sampling timing changes when a programmable wait is inserted.

3. i: Number of idle states inserted after the read cycle (0 or 1).

4. The specifications described above are the values for when a clock with a duty ratio of 1:1 is input

from X1.

31

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Bus Timing (CLKOUT Synchronous)

(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

Symbol

Conditions

MIN.

0

MAX.

19

Unit

ns

Delay time from CLKOUT↑ to address

t^DKA

<41>

<42>

Delay time from CLKOUT↑ to address

t^FKA

–12

7

ns

float

Delay time from CLKOUT↓ to ASTB

Delay time from CLKOUT↑ to DSTB

Data input setup time (to CLKOUT↑)

Data input hold time (from CLKOUT↑)

t^DKST

t^DKD

<43>

<44>

<45>

<46>

<47>

–12

–5

15

5

7

ns

14

t^SIDK

t^HKID

t^DKOD

Delay time from CLKOUT↑ to data

19

output

WAIT setup time (to CLKOUT↓)

t^SWTK

t^HKWT

t^SHQK

t^HKHQ

t^DKF

<48>

<49>

<50>

<51>

<52>

<53>

15

5

ns

WAIT hold time (from CLKOUT↓)

HLDRQ setup time (to CLKOUT↓)

HLDRQ hold time (from CLKOUT↓)

Delay time from CLKOUT↑ to bus float

Delay time from CLKOUT↑ to HLDAK

15

5

19

t^DKHA

Remark The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from

X1.

32

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)

T1

T2

TW

T3

CLKOUT (output)

<41>

A16 to A21 (output), Note

<16>

<45> <46>

Data

<42>

Hi-Z

AD0 to AD15 (I/O)

ASTB (output)

Address

<43>

<14>

<13>

<19>

<24>

<44>

<18>

<21>

<15>

<17>

<20>

<22>

<44>

DSTB (output),

RD (output)

<23>

<48> <49>

<32> <48> <49>

<34>

<33>

<35>

WAIT (input)

<28>

<30>

<29>

<31>

Note R/W (output), UBEN (output), LBEN (output)

Remark WRL and WRH are high level.

33

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)

T1

T2

TW

T3

CLKOUT (output)

<41>

A16 to A21 (output), Note

<47>

AD0 to AD15 (I/O)

ASTB (output)

Address

<43>

Data

<43>

<13>

<14>

<24>

<21>

<44>

<18>

<44>

<25>

<26>

<27>

DSTB (output),

WRL (output),

WRH (output)

<23>

<48> <49>

<32> <48> <49>

<34>

<33>

<35>

WAIT (input)

<28>

<30>

<29>

<31>

Note R/W (output), UBEN (output), LBEN (output)

Remark RD is high level.

34

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Bus Hold

TH

TI

CLKOUT (output)

HLDRQ (input)

<50>

<50> <51>

<36>

<53>

<39>

<40>

HLDAK (output)

<52>

<37>

<38>

Hi-Z

A16 to A21 (output), Note

AD0 to AD15 (I/O)

ASTB (output)

Data

Hi-Z

DSTB (output), RD (output),

WRL (output), WRH (output)

Note R/W (output), UBEN (output), LBEN (output)

35

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Reset/Interrupt Timing

(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

RESET high-level width

RESET low-level width

NMI high-level width

NMI low-level width

Symbol

t^WRSH

Conditions

MIN.

500

MAX.

Unit

ns

<54>

<55>

<56>

<57>

<58>

t^WRSL

t^WNIH

t^WNIL

t^WITH

500

INTPn high-level width

n = 0 to 3, analog noise elimination

n = 4, 5, digital noise elimination

n = 6, digital noise elimination

n = 0 to 3, analog noise elimination

n = 4, 5, digital noise elimination

n = 6, digital noise elimination

500

3T + 20

3Tsmp + 20

500

INTPn low-level width

t^WITL

<59>

3T + 20

3Tsmp + 20

Remarks 1. T = 1/fXX

2. Tsmp = Noise elimination sampling clock frequency

Reset

<54>

<55>

RESET (input)

Interrupt

<56>

<57>

<59>

NMI (input)

<58>

INTPn (input)

Remark n = 0 to 6

36

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

TIn Input Timing

(T^A= –40 to +85°C, V^DD= AV^DD=BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter

Tl0n0, Tl0n1 (n = 0, 1)

Symbol

Conditions

MIN.

2T^sam+ 20^Note

MAX.

Unit

ns

t^TIIH

<60>

<61>

High-level width

Tln (n = 2 to 7, 10, 11)

High-level width

3T + 20

2T^sam+ 20^Note

3T + 20

ns

Tl0n0, Tl0n1 (n = 0, 1)

Low-level width

t^TIL

Tln (n = 2 to 7, 10, 11)

Low-level width

Note

T^samcan be selected by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,

PRMn1) (n = 0, 1).

TM0 (PRM00, PRM01 registers): T^sam= 2T, 4T, 16T, 64T, 256T, 1/INTWTN period

TM1 (PRM10, PRM11 registers): T^sam= 2T, 4T, 16T, 32T, 128T, 256T

However, when the TIn0 valid edge is selected as the count clock, T^sam= 2T (n = 0, 1).

Remark T: I/fXX

<61>

<60>

TIn

Remark n = 000, 001, 010, 011, 10, 11, 2 to 7

37

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

3-Wire SIO Timing

(1) Master mode (T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter

SCKn cycle time

Symbol

Conditions

MIN.

400

140

50

MAX.

Unit

ns

t^KCY1

<62>

<63>

<64>

<65>

<66>

<67>

SCKn high-level width

t^KH1

t^KL1

SCKn low-level width

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↓)

Delay time from SCKn↓ to SOn output

t^SIK1

t^KSI1

t^KSO1

50

60

Remark n = 0 to 3

(2) Slave mode (T^A= –40 to +85°C, V^DD= AV^DD= BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter

SCKn cycle time

Symbol

Conditions

MIN.

400

180

50

MAX.

Unit

ns

t^KCY2

<62>

<63>

<64>

<65>

<66>

<67>

SCKn high-level width

t^KH2

t^KL2

SCKn low-level width

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↓)

Delay time from SCKn↓ to SOn output

t^SIK2

t^KSI2

t^KSO2

50

60

Remark n = 0 to 3

<62>

<63>

<64>

<65>

SCKn (I/O)

SIn (input)

<66>

<67>

SOn (output)

Remark n = 0 to 3

38

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

3-Wire Variable-Length CSI Timing

(1) Master mode (T^A= –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

SCK4 cycle time

Symbol

Conditions

MIN.

400

140

50

MAX.

Unit

ns

t^KCY1

t^KH1

t^KL1

<68>

<69>

<70>

<71>

<72>

<73>

SCK4 high-level width

SCK4 low-level width

SI4 setup time (to SCK4↑)

SI4 hold time (from SCK4↑)

Delay time from SCK4↓ to SO4 output

t^SIK1

t^KSI1

t^KSO1

50

60

(2) Slave mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

SCK4 cycle time

Symbol

Conditions

MIN.

400

180

50

MAX.

Unit

ns

t^KCY2

t^KH2

t^KL2

<68>

<69>

<70>

<71>

<72>

<73>

SCK4 high-level width

SCK4 low-level width

SI4 setup time (to SCK4↑)

SI4 hold time (from SCK4↑)

Delay time from SCK4↓ to SO4 output

t^SIK2

t^KSI2

t^KSO2

50

60

<68>

<69>

<70>

SCK4 (I/O)

SI4 (input)

<72>

<71>

<73>

SO4 (output)

39

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

UART Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)

Parameter

ASCKn cycle time

Symbol

Conditions

MIN.

200

80

MAX.

Unit

ns

t^KCY13

t^KH13

t^KL13

<74>

<75>

<76>

ASCKn high-level width

ASCKn low-level width

ns

80

ns

Remark n = 0, 1

<74>

<76>

<75>

ASCKn (input)

Remark n = 0, 1

40

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

I²C Bus Mode (Only for µPD70F3038Y and 70F3040Y)

(T^A= −40 to +85°C, V^DD= AV^DD= BV^DD= 2.7 to 3.6 V, V^SS= AV^SS= BV^SS= 0 V, C^L= 50 pF)

Parameter Symbol Standard Mode High-Speed Mode

MIN. MAX.

400

Unit

MIN.

MAX.

100

SCLn clock frequency

f^CLK

t^BUF

0

kHz

Bus free time

<77>

4.7

1.3

µs

(between stop/start conditions)

Hold time^{Note 1}

t^{HD : STA}

t^LOW

<78>

<79>

<80>

<81>

<82>

4.0

4.7

0.6

1.3

0.6

µs

ns

µs

ns

SCLn clock low-level width

SCLn clock high-level width

Setup time of start/restart conditions

t^HIGH

4.0

t^{SU : STA}

4.7

Data hold

time

CBUS-compatible master t^{HD : DAT}

I²C bus mode

5.0

0^{Note 2}

100^{Note 4}

20 + 0.1Cb^{Note 5}

0.6

0.9^{Note 3}

Data setup time

t^{SU : DAT}

<83>

<84>

<85>

<86>

<87>

250

Rising time of SDAn and SCLn signals

t^R

1000

300

Falling time of SDAn and SCLn signals t^F

Setup time of stop condition

t^{SU : STO}

4.0

Pulse width of spike suppressed by

input filter

t^SP

0

50

Load capacitance of bus line

Cb

400

pF

Notes 1. The first clock pulse in the start condition is generated after the hold time.

2. The system must internally provide at least 300 ns hold time for the SDAn signal (at V^IHmin.of the SCLn

signal) in order to fill the undefined period that appears at the SCLn falling edge.

3. If the system does not extend the low-state hold time (t^LOW), only the maximum data hold time (t^HD: ^DAT)

has to be satisfied.

4. The high-speed I²C bus is available in a standard mode I²C bus system. In this case, the following

conditions should be satisfied.

•

When the system does not extend the low-state hold time of the SCLn signal

t^SU: ^DAT≥ 250 ns

•

When the system extends the low-state hold time of the SCLn signal

Send the next data bit to the SDAn line before the SCLn line is released (t^Rmax.+ t^SU: ^DAT= 1000 +

250 = 1250 ns: Standard mode I²C bus specification).

5. Cb: Total capacitance of one bus line (Unit: pF)

Remarks 1. n = 0, 1

2. The maximum operating frequency of I²C is f^XX= 17 MHz.

However, when 16 MHz < f^XX≤ 17 MHz, use the system with V^DD= 3.1 V to 3.6 V.

41

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

I²C Bus Mode (Only for µPD70F3038Y and 70F3040Y)

<80>

<84>

<79>

<85>

SCLn

SDAn

<82>

<81>

<86>

<87>

<83>

<78>

Start

<78>

<77>

<85>

<84>

Stop

Restart

condition

Stop

condition

condition condition

Remark n = 0, 1

A/D Converter (T^A= –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, AVSS = VSS = 0 V, CL = 50 pF)

Parameter

Resolution

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Overall error^{Note 1}

0.8

100

0.4

4.0

3.6

%FSR

µs

Conversion time

t^CONV

5

Zero-scale error^{Note 1}

Full-scale error^{Note 1}

%FSR

LSB

V

Integral linearity error^{Note 2}

Differential linearity error^{Note 2}

Analog reference voltage

Analog input voltage

AV^REFcurrent

AV^REF

V^IAN

AV^REF= AV^DD

2.7

AV^SS

AV^REF

500

3

V

AI^REF

AI^DD

360

1

µA

A/D converter supply current

During normal operation

During STOP mode

mA

AI^DDS

1

10

µA

Notes 1. Excluding quantization error ( 0.05%FSR)

2. Excluding quantization error ( 0.5LSB)

Remark LSB: Least Significant Bit

FSR: Full Scale Range

42

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

Flash Memory Programming Mode

Basic Characteristics (TA = 10 to 40 °C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter

V^PPsupply voltage

Symbol

V^PP2

Conditions

In flash memory programming

mode

MIN.

7.5

TYP.

7.8

MAX.

8.1

Unit

V

V^DDsupply current

I^DD

µPD70F3038,

µPD70F3038Y

V^PP= V^PP2

f^XX= 16 MHz,

V^DD= 3.0 to 3.6 V

f^XX= 20 MHz,

V^DD= 3.1 to 3.6 V

f^XX= 16 MHz,

V^DD= 3.0 to 3.6 V

f^XX= 20 MHz,

66

72

mA

µPD70F3040,

µPD70F3040Y

V^PP= V^PP2

61

67

V^DD= 3.1 to 3.6 V

V^PPsupply voltage

Step erase time

Total erase time per area

Writeback time

I^PP

t^ER

t^ERA

t^WB

V^PP= V^PP2

Note 1

Step erase time = 0.2 s, Note 2

Note 3

200

20

mA

s

s/area

ms

0.2

1

Number of writebacks per C^WB

writeback command

Writeback time = 1 ms, Note 4

300

16

Times/

Writeback command

Time

µs

Number of erases – writebacks

Step write time

C^ERWB

t^WR

Note 5

20

Total write time per word

t^WRW

When step write time is set to 20 µ s

(1 word = 4 bytes), Note 6

One erase + one write after erase

= One rewrite, Note 7

20

200

µs/

word

Times/

area

Number of rewrites per area

C^ERWR

Notes 1. The recommended set value of the step erase time is 0.2 s.

2. The value does not include the prewrite and erase verify (writeback) time prior to erase.

3. The recommended set value of the writeback time is 1 ms.

4. Issuing a writeback command performs one writeback. Therefore, subtract the number of times a

command is issued from this value to set the number of retries.

5. The recommended set value of the step write time is 20 µ s.

6. The actual write time per word is the total of this value and 20 µs. It does not include the internal verify

time during and after writing.

7. When a product is written for the first time, both erase → write and write only is considered as one

rewrite.

Example (P: Write, E: Erase)

Product

→ P → E → P → E → P: 3 rewrites

Product → E → P → E → P → E → P: 3 rewrites

Remarks 1. The operation clock range in the flash memory programming mode is the same as that during

normal operation.

••

2. When the PG-FP3 is used, time parameters required for write/erase are automatically set by

downloading a parameter file. Unless otherwise specified, do not change the set values.

3. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH, area 2 = 040000 to 05FFFFH (µ

PD70F3038, 70F3038Y)

Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH (µ PD70F3040, 70F3040Y)

43

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

3. PACKAGE DRAWING

176-PIN PLASTIC LQFP (FINE PITCH) (24x24)

A

B

132

133

89

88

detail of lead end

S

P

T

C

D

R

L

U

Q

176

1

45

44

F

M

J

G

H

I

K

S

M

N

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

G

H

I

26.0 0.2

24.0 0.2

26.0 0.2

1.25

0.22 0.05

0.08

J

0.5 (T.P.)

1.0 0.2

0.5

K

L

+0.03

M

0.17

−0.07

0.08

N

P

Q

1.4

0.1 0.05

+4°

3°

R

−3°

1.5 0.1

S

T

0.25

U

0.60 0.15

S176GM-50-UEU-1

44

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

180-PIN PLASTIC FBGA (13x13)

D

w

S

B

ZD

B

15

14

13

12

11

10

9

ZE

A

8

E

7

6

5

4

3

2

1

R P N M L K J H G F E D C B A

w

S

A

INDEX MARK

A

y1

A2

S

ITEM MILLIMETERS

13.00 0.10

0.2

D

E

y

e

A1

B

w

S

A

1.48 0.10

0.35 0.06

1.13

A1

A2

e

φ

b

φ

x

M

S

A

0.80

b

0.50 0.05

0.08

x

y

0.10

0.20

y1

ZD

ZE

0.90

P180F1-80-EN2

45

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

4. RECOMMENDED SOLDERING CONDITIONS

The µPD70F3038, 70F3038Y, 70F3040, and 70F3040Y should be soldered and mounted under the following

recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 4-1. Surface Mounting Type Soldering Conditions

(a) µPD70F3040GM-×××-UEU: 176-pin plastic LQFP (fine pitch) (24 × 24)

µPD70F3040YGM-×××-UEU: 176-pin plastic LQFP (fine pitch) (24 × 24)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or

higher), Count: Twice or less, Exposure limit: 3 days^Note(after that, prebake at

125°C for 10 hours)

IR35-103-2

VP15-103-2



VPS

Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or

higher), Count: Twice or less, Exposure limit: 3 days^Note(after that, prebake at

125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

46

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

(b) µ PD70F3038F1-EN2: 180-pin plastic FBGA (13 × 13)

µ PD70F3038YF1-EN2: 180-pin plastic FBGA (13 × 13)

µ PD70F3040F1-EN2: 180-pin plastic FBGA (13 × 13)

µ PD70F3040YF1-EN2: 180-pin plastic FBGA (13 × 13)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

VPS

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Twice or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

10 hours)

IR35-107-2

VP15-107-2



Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),

Count: Twice or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

10 hours)

Partial heating

Pin temperature: 300°C max., Time 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

47

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

[MEMO]

48

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

[MEMO]

49

Data Sheet U14622EJ2V0DS

µPD70F3038, 70F3038Y, 70F3040, 70F3040Y

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Purchase of NEC I²C components conveys a license under the Philips I²C Patent Rights to use these components in an I²C

system, provided that the system conforms to the I²C Standard Specification as defined by Philips.


型号：	UPD70F3040YGM-UEU-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	IC,MICROCONTROLLER,32-BIT,V850 CPU,CMOS,QFP,176PIN,PLASTIC 微控制器
文件：	总52页 (文件大小：1225K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD70F3040YGM-UEU-A [RENESAS]

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