UPD753204GT-XXX-T2 [RENESAS]
IC,MICROCONTROLLER,4-BIT,UPD75000 CPU,CMOS,SSOP,48PIN,PLASTIC;
| 型号： | UPD753204GT-XXX-T2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,MICROCONTROLLER,4-BIT,UPD75000 CPU,CMOS,SSOP,48PIN,PLASTIC 光电二极管 |
| 文件： | 总83页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD753204, 753206, 753208
4-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing
capability comparable to that of an 8-bit microcontroller.
The µPD753208 has an on-chip LCD controller/driver and is based on the µPD75308B of the 75X Series.
However, the µPD75308B is supplied in an 80-pin package, whereas the µPD753208 is supplied in a 48-
pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In
addition, the µPD753208 features expanded CPU functions and performs high-speed operations at a low
voltage of 1.8 V.
Detailed information about functions can be found in the following user’s manual. Be sure to read it
before designing. µPD753208 User’s Manual: U10158E
Features
•
Variable instruction execution time for high-speed
operation and power saving operation
•
Low-voltage operation: VDD = 1.8 to 5.5 V
– Can be driven by two 1.5-V batteries
Internal memory
– 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation)
– 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation)
Internal programmable LCD controller/driver
Small package:
•
– Program memory (ROM):
4096 × 8 bits (µPD753204)
6144 × 8 bits (µPD753206)
8192 × 8 bits (µPD753208)
– Data memory (RAM):
•
•
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
One-time PROM version: µPD75P3216
•
512 × 4 bits
Applications
Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems,
gas meters, etc.
Unless otherwise specified, references in this data sheet to the µPD753208 mean the
µPD753204 and the µPD753206.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U10166EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1996
µPD753204, 753206, 753208
Ordering Information
Part number
Package
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
ROM (× 8 bits)
µPD753204GT-×××
4096
4096
6144
6144
8192
8192
µPD753204GT-×××-A 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753206GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753206GT-×××-A 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753208GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753208GT-×××-A 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
Remarks 1. Products with “-A” at the end of the part number are lead-free products.
2. ××× indicates ROM code suffix.
2
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Function Outline
Parameter
Function
Instruction execution time
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)
ROM 4096 × 8 bits (µPD753204)
6144 × 8 bits (µPD753206)
Internal memory
8192 × 8 bits (µPD753208)
RAM 512 × 4 bits
General-purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
CMOS input
6
Connecting on-chip pull-up resistors can be specified by software: 5
CMOS input/output
20 Connecting on-chip pull-up resistors can be specified by software: 20
Also used for segment pins: 8
N-ch open-drain
input/output
4
On-chip pull-up resistors can be specified by mask option
13-V withstand voltage
Total
30
LCD controller/driver
• Segment selection:
4/8/12 segments (can be changed to CMOS input/
output port in 4-time units; max. 8)
• Display mode selection: Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
• On-chip split resistor for LCD drive can be specified by mask option
Timer
5 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier
generator, and timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
Clock output (PCL)
16 bits
•
•
Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)
Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)
Buzzer output (BUZ)
• 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)
Vectored interrupts
Test input
External: 2, Internal: 5
External: 1, Internal: 1
System clock oscillator
Standby function
Power supply voltage
Package
Ceramic or crystal oscillator for system clock oscillation
STOP/HALT mode
VDD = 1.8 to 5.5 V
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
Data Sheet U10166EJ2V1DS
3
µPD753204, 753206, 753208
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................6
2. BLOCK DIAGRAM................................................................................................................................7
3. PIN FUNCTIONS ....................................................................................................................................8
3.1 Port Pins ......................................................................................................................................8
3.2 Non-Port Pins ............................................................................................................................10
3.3 Pin Input/Output Circuits .........................................................................................................12
3.4 Recommended Connections for Unused Pins .......................................................................14
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................15
4.1 Difference Between Mk I and Mk II Modes ..............................................................................15
4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................16
5. MEMORY CONFIGURATION .............................................................................................................17
6. PERIPHERAL HARDWARE FUNCTION ...........................................................................................22
6.1 Digital I/O Port ...........................................................................................................................22
6.2 Clock Generator ........................................................................................................................23
6.3 Clock Output Circuit .................................................................................................................24
6.4 Basic Interval Timer/Watchdog Timer.....................................................................................25
6.5 Watch Timer ..............................................................................................................................26
6.6 Timer/Event Counter.................................................................................................................27
6.7 Serial Interface ..........................................................................................................................31
6.8 LCD Controller/Driver ...............................................................................................................33
6.9 Bit Sequential Buffer ................................................................................................................35
7. INTERRUPT FUNCTION AND TEST FUNCTION ..............................................................................36
8. STANDBY FUNCTION........................................................................................................................38
9. RESET FUNCTION .............................................................................................................................39
10. MASK OPTION ...................................................................................................................................42
11. INSTRUCTION SET ............................................................................................................................43
12. ELECTRICAL SPECIFICATIONS.......................................................................................................57
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ...................................................................69
14. PACKAGE DRAWINGS .....................................................................................................................71
15. RECOMMENDED SOLDERING CONDITIONS .................................................................................72
4
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST .............................................73
APPENDIX B DEVELOPMENT TOOLS .................................................................................................75
APPENDIX C RELATED DOCUMENTS ................................................................................................78
Data Sheet U10166EJ2V1DS
5
µPD753204, 753206, 753208
1. PIN CONFIGURATION (TOP VIEW)
• 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753204GT-×××, µPD753204GT-×××-A, µPD753206GT-×××, µPD753206GT-×××-A,
µPD753208GT-×××, µPD753208GT-×××-A
COM0
COM1
COM2
COM3
BIAS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
VLC0
VLC1
VLC2
P30/LCDCL
P31/SYNC
P32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P33
VSS
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
VDD
X1
X2
IC Note
Note Connect IC (Internally Connected) pin directly to VDD.
Pin Identification
P00 to P03
P10, P13
: Port0
S12 to S23
VLC0 to VLC2
BIAS
: Segment Output 12 to 23
: LCD Power Supply 0 to 2
: LCD Power Supply Bias Control
: LCD Clock
: Port1
P20 to P23
P30 to P33
P50 to P53
P60 to P63
P80 to P83
P90 to P93
KR0 to KR3
: Port2
: Port3
LCDCL
SYNC
: Port5
: LCD Synchronization
: Timer Input 0
: Port6
TI0
: Port8
PTO0 to PTO2 : Programmable Timer Output 0 to 2
: Port9
BUZ
: Buzzer Clock
: Key Return 0 to 3
PCL
: Programmable Clock
: External Vectored Interrupt 0, 4
: System Clock Oscillation 1, 2
: Reset
COM0 to COM3 : Common Output 0 to 3
INT0, INT4
X1, X2
RESET
IC
SCK
SI
: Serial Clock
: Serial Input
SO
: Serial Output
: Serial Data Bus 0, 1
: Internally Connected
: Positive Power Supply
: Ground
SB0, SB1
VDD
VSS
6
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
2. BLOCK DIAGRAM
WATCH
BUZ/P23
TIMER
4
2
4
4
4
4
4
4
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT8
PORT9
P00 to P03
P10,P13
f
LCD
INTW
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
P20 to P23
P30 to P33
P50 to P53
P60 to P63
P80 to P83
P90 to P93
SP (8)
SBS
PROGRAM
COUNTER
CY
INTBT
8-BIT
TIMER/EVENT
COUNTER #0
ALU
TI0/P13
BANK
TPO0/P20
INTT0 TOUT
INTT1
GENERAL REG.
8-BIT
TIMER
CASCADED
16-BIT
COUNTER #1
PTO1/P21
TOUT
PROGRAM
MEMORYNote
(ROM)
DECODE
AND
CONTROL
TIMER
8-BIT
COUNTER
TIMER
COUNTER #2
DATA
MEMORY
(RAM)
PTO2/PCL/P22
4
4
4
4
S12 to S15
INTT2
S16/P93 to
S19/P90
512 × 4 BITS
SI/SB1/P03
CLOCKED
SERIAL
INTERFACE
S20/P83 to
S23/P80
SO/SB0/P02
SCK/P01
LCD
CONTROLLER/
DRIVER
INTCSI TOUT
COM0 to COM3
INT0/P10
INT4/P00
V
V
V
LC0
LC1
LC2
CPU CLOCK
fX
/2N
Φ
fLCD
INTERRUPT
CONTROL
CLOCK
OUTPUT
CONTROL
SYSTEM
CLOCK
GENERATOR
KR0/P60 to
KR3/P63
CLOCK
DIVIDER
STANDBY
CONTROL
BIAS
LCDCL/P30
SYNC/P31
4
BIT SEQ
BUFFER (16)
PCL/PTO2/P22
X1 X2
IC
VDD VSS
RESET
Note The ROM capacity depends on the product.
Data Sheet U10166EJ2V1DS
7
µPD753204, 753206, 753208
3. PIN FUNCTION
3.1 Port Pins (1/2)
Alternate
Function
8-bit
I/O
I/O Circuit
Pin Name
P00
Input/Output
Function
After Reset
Input
Note 1
TYPE
Input
INT4
SCK
No
No
No
(B)
4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors can
be specified by software in 3-bit units.
P01
P02
P03
P10
Input/Output
Input/Output
Input/Output
Input
(F)-A
(F)-B
(M)-C
(B)-C
SO/SB0
SI/SB1
INT0
Input port in 1 bit unit (PORT1).
On-chip pull-up resistors can be specified by
software in 2-bit units.
Input
Input
Input
P13
TI0
Noise elimination circuit can be specified with
P10/INT0.
P20
P21
P22
P23
P30
P31
P32
P33
Input/Output
Input/Output
Input/Output
PTO0
PTO1
PCL/PTO2
BUZ
E-B
E-B
M-D
4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified by
software in 4-bit units.
LCDCL
SYNC
–
Programmable4-bitinput/outputport(PORT3). No
This port can be specified input/output bit-
wise. On-chip pull-up resistor can be speci-
fied by software in 4-bit units.
–
High level
(when pull-
up resistors
are
P50 to
P53 Note 2
–
No
N-chopen-drain4-bitinput/outputport(PORT5).
A pull-up resistor can be contained bit-wise
(mask option).
provided) or
high-
Withstand voltage is 13 V in open-drain mode.
impedance
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low level input leakage current increases when input or bit manipulation instruction is executed.
8
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
3.1 Port Pins (2/2)
Alternate
Function
8-bit
I/O
I/O Circuit
Pin Name
P60
Input/Output
Function
After Reset
Input
Note 1
TYPE
Programmable4-bitinput/outputport(PORT6).
This port can be specified for input/output bit-
wise.
Input/Output
Input/Output
Input/Output
KR0
KR1
KR2
KR3
S23
S22
S21
S20
S19
S18
S17
S16
No
(F)-A
P61
P62
P63
P80
P81
P82
P83
P90
P91
P92
P93
On-chip pull-up resistors can be specified by
software in 4-bit units.
Yes
Input
Input
H
4-bit input/output port (PORT8).
On-chip pull-up resistors can be specified by
Note 2
software in 4-bit units.
H
4-bit input/output port (PORT9).
On-chip pull-up resistors can be specified by
Note 2
software in 4-bit units.
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output
pins.
Data Sheet U10166EJ2V1DS
9
µPD753204, 753206, 753208
3.2 Non-Port Pins (1/2)
Alternate
Function
I/O Circuit
Pin Name
TI0
Input/Output
Input
Function
After Reset
Note 1
TYPE
P13
Inputs external event pulses to the timer/event
counter.
Input
Input
(B)-C
E-B
PTO0
PTO1
PTO2
PCL
Output
P20
P21
Timer/event counter output
Timer counter output
P22/PCL
P22/PTO2
P23
Clock output
BUZ
Optional frequency output (for buzzer output
or system clock trimming)
SCK
Input/Output
P01
P02
Serial clock input/output
Input
(F)-A
(F)-B
SO/SB0
Serial data output
Serial data bus input/output
SI/SB1
INT4
P03
P00
P10
Serial data input
(M)-C
(B)
Serial data bus input/output
Input
Input
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Input
Input
Edge detection vectored
interrupt input (detection
edge can be selected).
Noise elimination circuit
can be specified.
With clock elimination
circuit/asynchronous
selectable
INT0
(B)-C
KR0 to KR3
S12 to S15
S16 to S19
S20 to S23
COM0 to COM3
VLC0 to VLC2
Input/Output
Output
Output
Output
Output
–
P60 to P63 Falling edge detection testable input
Segment signal output
Input
Note 2
Input
Input
Note 2
–
(F)-A
G-A
H
–
P93 to P90 Segment signal output
P83 to P80 Segment signal output
H
–
–
Common signal output
G-B
–
LCD drive power
On-chip split resistor is enable (mask option).
BIAS
Output
–
Output for external split resistor disconnect
Clock output for externally expanded driver
Clock output for externally expanded driver sync
Note 3
Input
–
LCDCL Note 4
SYNC Note 4
Input/Output
Input/Output
P30
P31
E-B
E-B
Input
Notes 1. Characters in parentheses indicate the Schmitt trigger input.
2. Each display output selects the following VLCX as input source.
S12 to S15: VLC1, COM0 to COM2: VLC2, COM3: VLC0.
3. When a split resistor is contained ....... Low level
When no split resistor is contained ......High-impedance
4. These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.
10
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
3.2 Non-Port Pins (2/2)
Alternate
Function
I/O Circuit
Pin Name
X1
Input/Output
Input
Function
After Reset
–
Note 1
TYPE
–
Crystal/ceramic connection pin for the system
clock oscillator. When inputting the external
clock, input the external clock to pin X1, and
the reverse phase of the external clock to pin
X2.
–
X2
–
RESET
IC
Input
–
–
–
–
System reset input (low-level active)
Internally connected. Connect directly to VDD.
Positive power supply
–
–
–
–
(B)
–
–
–
–
VDD
–
VSS
Ground potential
–
Note Characters in parentheses indicate the Schmitt-trigger input.
Data Sheet U10166EJ2V1DS
11
µPD753204, 753206, 753208
3.3 Pin Input/Output Circuits
The µPD753208 pin input/output circuits are shown schematically.
(1/2)
TYPE A
TYPE D
V
DD
V
DD
data
P-ch
OUT
P-ch
IN
N-ch
output
disable
N-ch
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
CMOS specification input buffer.
TYPE B
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
data
IN/OUT
Type D
output
disable
Type A
Schmitt trigger input having hysteresis characteristic.
P.U.R. : Pull-Up Resistor
TYPE F-A
TYPE B-C
VDD
V
DD
P.U.R.
P-ch
P.U.R.
enable
P.U.R.
P.U.R.
enable
P-ch
data
IN/OUT
Type D
output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
12
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
(2/2)
TYPE F-B
TYPE H
V
DD
P.U.R
P-ch
P.U.R
enable
output
disable
(P)
IN/OUT
SEG
data
V
DD
P-ch
N-ch
TYPE G-A
P-ch
IN/OUT
data
data
output
disable
N-ch
TYPE E-B
output
disable
output
disable
(N)
P.U.R : Pull-Up Resistor
TYPE M-C
TYPE G-A
VDD
P-ch
N-ch
V
V
LC0
LC1
P.U.R
P-ch
N-ch
P.U.R.
enable
P-ch
IN/OUT
P-ch N-ch
data
N-ch
OUT
output
SEG
data
disable
N-ch
P-ch
N-ch
VLC2
N-ch
P.U.R : Pull-Up Resistor
TYPE G-B
TYPE M-D
VDD
P-ch
N-ch
P.U.R.
(Mask Option)
V
LC0
IN/OUT
N-ch
(+13-V
withstand)
data
V
LC1
output
disable
V
DD
P-ch N-ch
input
instruction
P-ch
P.U.R.Note
OUT
Voltage
control
circuit
COM
data
N-ch P-ch
P-ch
N-ch
V
LC2
P.U.R. : Pull-Up Resistor
Pull-up resistor that only operates upon the execution
of an input instruction when the pull-up resistor is not
connected via the mask option (it is available during
low-voltage).
Note
N-ch
Data Sheet U10166EJ2V1DS
13
µPD753204, 753206, 753208
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin
Recommended Connection
Connect to VSS or VDD
P00/INT4
P01/SCK
Connect individually to VSS or VDD via a resistor
P02/SO/SB0
P03/SI/SB1
P10/INT0
P13/TI0
Connect to VSS
Connect to VSS or VDD
P20/PTO0
P21/PTO1
P22/PCL/PTO2
P23/BUZ
P30/LCDCL
P31/SYNC
P32
Input state: Connect individually to VSS or VDD via a resistor
Output state: No connection
P33
P50 to P53
Input state
: Connect to VSS
Output state : Connect to VSS (Do not connect pull-up
resistor in the mask option)
P60/KR0 to P63/KR3
Input state
: Connect individually to VSS or VDD via a
resistor
Output state : No connection
S0 to S15
No connection
COM0 to COM3
S16/P93 to S19/P90
S20/P83 to S23/P80
VLC0 to VLC2
Input state: Connect individually to VSS or VDD via a resistor
Output state: No connection
Connect to VSS
BIAS
Only if all of VLC0 to VLC2 are unused, connect to VSS.
In other cases, no connection.
IC
Connect to VDD directly
14
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference Between Mk I and Mk II Modes
The CPU of the µPD753208 has the following two modes: Mk I and Mk II, either of which can be selected.
The mode can be switched by bit 3 of the Stack Bank Select register (SBS).
•
•
Mk I mode: Upward compatible with the µPD75308B. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
Mk II mode: Incompatible with µPD75308B. Can be used in all the 75XL CPU including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Mk II mode
Number of stack bytes
2 bytes
3 bytes
for subroutine instructions
BRA ! addr1 instruction
Not available
Available
CALLA ! addr1 instruction
CALL ! addr instruction
CALLF ! faddr instruction
3 machine cycles
2 machine cycles
4 machine cycles
3 machine cycles
Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Software compatibility with products whose program memory exceeds 16 Kbytes can be raised
by using this mode.
When the MkII mode is selected, the number of stack bytes increases by one byte per stack
during subroutine call instruction execution compared with the MkI mode. When the !faddr
instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,
if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI
mode is recommended.
Data Sheet U10166EJ2V1DS
15
µPD753204, 753206, 753208
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be
initialized to 100×BNote at the beginning of a program. When using the Mk II mode, it must be initialized to 000×BNote
.
Note The desired numbers must be set in the × positions.
Figure 4-1. Stack Bank Select Register Format
3
2
1
0
Address
F84H
Symbol
SBS
SBS3 SBS2 SBS1 SBS0
Stack area specification
0
0
Memory bank 0
Memory bank 1
Setting prohibited
0
1
Other than
above
0 must be set in the bit 2 position.
0
Mode switching specification
0
1
Mk II mode
Mk I mode
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.
When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.
16
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
5. MEMORY CONFIGURATION
• Program Memory (ROM) .... 4096 × 8 bits (µPD753204)
.... 6144 × 8 bits (µPD753206)
.... 8192 × 8 bits (µPD753208)
– Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
– Addresses 0002H to 000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.
– Addresses 0020H to 007FH
Table area referenced by the GETI instruction Note
.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
•
Data Memory (RAM)
– Data area ... 512 words × 4 bits (000H to 1FFH)
– Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH)
Data Sheet U10166EJ2V1DS
17
µPD753204, 753206, 753208
Figure 5-1. Program Memory Map (1/3)
(a) µPD753204
Address
7
6
5
0
4
0
0
0 0 0 H MBE RBE
0 0 2 H MBE RBE
0 0 4 H MBE RBE
Internal reset start address
Internal reset start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
0
0
0
0
INTBT/INT4
INTBT/INT4
start address
start address
INT0
INT0
start address
start address
CALLF
! faddr
instruction
entry
address
0 0 6 H
Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1Note or
CALLA !addr1Note
0 0 8 H MBE RBE
0 0 A H MBE RBE
0 0 C H MBE RBE
0
0
0
0
0
0
INTCSI
start address
start address
start address
start address
start address
start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
instructions
CALL !addr instruction
subroutine entry address
INTCSI
INTT0
BR $addr instruction
relative branch address
INTT0
–15 to –1,
+2 to +16
INTT1/INTT2
INTT1/INTT2
BRCB
! caddr instruction
branch address
0 2 0 H
GETI instruction reference table
0 7 F H
0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
7 F F H
8 0 0 H
F F F H
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
18
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Figure 5-1. Program Memory Map (2/3)
(b) µPD753206
Address
7
6
5
0
0
0 0 0 0 H
MBE RBE
Internal reset start address
Internal reset start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0
0
INTBT/INT4
INTBT/INT4
INT0
start address
start address
start address
start address
(low-order 8 bits)
(high-order 5 bits)
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
instructions
INT0
(low-order 8 bits)
CALLF
! faddr
instruction
entry
0 0 0 6 H
address
CALL ! addr
instruction
0 0 0 8 H MBE RBE
0
INTCSI
start address
start address
start address
(high-order 5 bits)
subroutine entry
address
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
INTCSI
INTT0
BR $ addr
instruction relative
branch address
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
–15 to –1,
+2 to +16
start address
start address
INTT0
INTT1/INTT2
start address
INTT1/INTT2
(low-order 8 bits)
BRCB ! caddr
instruction
branch
address
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 7 F F H
0 8 0 0 H
0 F F F H
1 0 0 0 H
BRCB ! caddr
instruction
branch
address
1 7 F F H
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
Data Sheet U10166EJ2V1DS
19
µPD753204, 753206, 753208
Figure 5-1. Program Memory Map (3/3)
(c) µPD753208
Address
7
6
5
0
0
0 0 0 0 H
MBE RBE
Internal reset start address
Internal reset start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0
0
INTBT/INT4
INTBT/INT4
INT0
start address
start address
start address
(low-order 8 bits)
(high-order 5 bits)
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
instructions
(low-order 8 bits)
INT0
start address
CALLF
! faddr
instruction
entry
0 0 0 6 H
address
CALL ! addr
instruction
subroutine entry
address
0 0 0 8 H MBE RBE
0
INTCSI
start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
INTCSI
INTT0
start address
start address
BR $ addr
instruction relative
branch address
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
–15 to –1,
+2 to +16
INTT0
start address
start address
INTT1/INTT2
(low-order 8 bits)
INTT1/INTT2
BRCB ! caddr
start address
instruction
branch
address
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 7 F F H
0 8 0 0 H
0 F F F H
1 0 0 0 H
BRCB ! caddr
instruction
branch
address
1 F F F H
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
20
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Figure 5-2. Data Memory Map
Data memory
Memory bank
0 0 0 H
General-purpose
register area
(32 × 4)
0 1 F H
0 2 0 H
0
256 × 4
(224 × 4)
Stack area Note
Data area
static RAM
(512×4)
0 F F H
1 0 0 H
256 × 4
(236 × 4)
1
1 E B H
1 E C H
Display data
memory area
(12 × 4)
(8 × 4)
1 F 7 H
1 F 8 H
1 F F H
Not incorporated
F 8 0 H
128 × 4
15
Peripheral hardware area
F F F H
Note As a stack area, either memory bank 0 or 1 can be selected.
Data Sheet U10166EJ2V1DS
21
µPD753204, 753206, 753208
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
There are three kinds of I/O ports.
•
•
•
CMOS input ports (Ports 0, 1)
: 6
CMOS input/output ports (Ports 2, 3, 6, 8, 9) : 20
N-ch open-drain input/output ports (Port 5)
Total
: 4
30
Table 6-1. Types and Features of Digital Ports
Port
PORT0
Function
Operation and features
Remarks
4-bit input
The alternate function pins have an output function
with operation mode when using the serial interface
function.
Also used for the INT4, SCK,
SO/SB0, and SI/SB1 pins.
PORT1
PORT2
PORT3
PORT5
1-bit input
4-bit I/O
2-bit input dedicated port
Also used for the INT0 and
TI0.
Can be set to input mode or output mode in 4-bit
units.
Also used for the PTO0 to
PTO2, PCL, and BUZ pins.
Can be set to input mode or output mode bit-wise.
Also used for the LCDCL
and SYNC pins.
4-bit I/O (N-
Can be set to input mode or output mode in 4-bit
—
channel open- units. On-chip pull-up resistor can be specified
drain, 13-V
by mask option bit-wise.
withstand)
PORT6
PORT8
PORT9
4-bit I/O
Can be set to input mode or output mode bit-wise.
Can be set to input mode Ports 8 and 9 are paired
Also used for the KR0 to
KR3 pins.
Also used for the S20 to
S23 pins.
or output mode in 4-bit
units.
and data can be input/
output in 8-bit units.
Also used for the S16 to
S19 pins.
22
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is
shown in Figure 6-1.
The operation of the clock generator is determined by the Processor Clock Control Register (PCC).
The instruction execution time can also be changed.
•
•
0.95, 1.91, 3.81, 15.3 µs (system clock: @ 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7 µs (system clock: @ 6.0-MHz operation)
Figure 6-1. Clock Generator Block Diagram
· Basic interval timer (BT)
· Timer/event counter 0
· Timer counter 1, 2
· Watch timer
· LCD controller/driver
· Serial interface
· INT0 noise eliminator
· Clock output circuit
X1
VDD
fX
1/1 to 1/4096
Divider
System clock
oscillator
X2
1/2 1/4 1/16
Oscillation stop
Divider
Selector
1/4
Φ
· CPU
· INT0 noise eliminator
PCC
· Clock output circuit
PCC0
PCC1
PCC2
PCC3
HALT F/F
S
4
HALTNote
STOPNote
R
Q
PCC2,
PCC3
Clear
STOP F/F
Wait release signal from BT
RESET Signal
Q
S
R
Standby release signal from
interrupt control circuit
Note Instruction execution
Data Sheet U10166EJ2V1DS
23
µPD753204, 753206, 753208
Remarks 1. fX = System clock frequency
2. Φ = CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
6.3 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2)
to the remote control wave outputs and peripheral LSIs.
•
Clock Output (PCL) : Φ, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)
Figure 6-2. Clock Output Circuit Block Diagram
From clock
generator
From timer counter
(channel 2)
Φ
/23
/24
Output buffer
f
f
X
X
Selector
PCL/PTO2/P22
f
X
/26
PORT2.2
Bit 2 of PMGB
P22
output latch
Port 2 I/O mode
specification bit
CLOM3
0
CLOM1 CLOM0 CLOM
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when
switching clock output enable/disable.
24
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
6.4 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
•
•
•
•
Interval timer operation to generate a reference time interrupt
Watchdog timer operation to detect program runaway and reset the CPU
Selects and counts the wait time when the standby mode is released
Reads the contents of counting
Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
Clear
Clear
fX
fX
fX
/25
/27
/29
BT
Basic interval timer
(8-bit frequency divider)
Set
MPX
interrupt
request flag
Vectored
interrupt
IRQBT request signal
BT
f
/212
X
3
Wait release signal
when standby is
released.
Internal reset
signal
WDTM
1
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1Note
8
SET1Note
Internal bus
Note Instruction execution
Data Sheet U10166EJ2V1DS
25
µPD753204, 753206, 753208
6.5 Watch Timer
The µPD753208 has one watch timer channel, whose functions are as follows.
•
•
•
Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW.
0.5 sec interval can be created with the system clock (4.194304 MHz)
Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the
fast feed mode.
•
•
Outputs a frequency (2.048, 4.096, or 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming
of system clock frequencies.
Clears the frequency divider to make the clock start with zero seconds.
Figure 6-4. Watch Timer Block Diagram
f
W
26
(512 Hz : 1.95 ms)
(256 Hz : 3.91 ms)
f
LCD
f
W
27
f
X
From
clock
generator
Selector
128
f
W
214
f
W
INTW
IRQW
(32.768 kHz)
(32.768 kHz)
Selector
Divider
set signal
2 Hz
4 kHz 2 kHz
0.5 sec
f
W
f
W
24
Clear
23
Selector
Output buffer
P23/BUZ
WM
PORT2.3
PMGB bit 2
Port 2 input/
Note 1
Note 2
P23
output-latch
WM7
0
WM5 WM4 WM3 WM2 WM1 WM0
output mode
8
Internal bus
Notes 1. WM3 is undefined while reading data.
2. Be sure to set WM0 to 0.
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz.
26
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
6.6 Timer/Event Counter
The µPD753208 provides one channel for timer/event counters and two channels for timer counters. Figures
6-5 to 6-7 show the block diagrams. Timer/event counter functions are as follows.
•
•
•
•
Programmable interval timer operation
Square wave output of any frequency to the PTO0 pin (n = 0 to 2).
Event counter operation (Channel 0 only)
Divides the frequency of signal input via the TI0 pin to 1-nth of the original signal and outputs the divided
frequency to the PTO0 pin (frequency divider operation).
Supplies the shift clock to the serial interface circuit.
Reads the counting status.
•
•
The timer/event counter operates in the following four modes as set by the mode register.
Table 6-2. Operation Modes of Timer/Event Counter
Channel
Channel 0 Channel 1 Channel 2
Mode
8-bit timer/event counter mode Note 1
Gate control function
A
A
A
A
A
N/ANote 2
N/A
N/A
N/A
PWM pulse generator mode
16-bit timer counter mode
Gate control function
N/A
A
A
A
N/ANote 2
N/A
Carrier generator mode
Notes 1. Channel 0 only. 8-bit timer counter mode for channel 1 and channel 2
2. Used for gate control signal generation
Remark A:
Available
N/A: Not available
Data Sheet U10166EJ2V1DS
27
Figure 6-5. Timer/Event Counter Block Diagram (channel 0)
Internal bus
SET1Note
8
8
8
TOE0
PORT2.0
PMGB bit 2
TMOD0
TM0
–
Port 2
input/output
mode
T0
P20
output latch
–
TM06 TM05 TM04 TM03 TM02
–
Modulo register (8)
8
enable flag
To serial interface
PORT1.3
TOUT0
Match
TOUT
F/F
Comparator (8)
8
PTO0/P20
Output buffer
Input
Reset
buffer
T0
TI0/P13
INTT0
IRQT0
set signal
Count register (8)
Clear
f
f
f
X
/24
/26
/28
MPX
CP
From
clock
generator
X
X
µ
f
X
/210
Timer operation start
RESET
IRQT0
clear signal
To timer counter (channel 2)
Note Execution of instruction
Caution When data is set to TM0, always set bit 1 to 0.
Figure 6-6. Timer/Event Counter Block Diagram (channel 1)
Internal bus
SET1Note
8
TOE1
PORT2.1
PMGB bit 2
TM1
Port 2
input/output
mode
8
T1
enable flag
P21
output latch
–
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Decoder
TMOD1
Modulo register (8)
8
P21/PTO1
Match
TOUT
F/F
Comparator (8)
8
Timer counter
(channel 2) output
Output buffer
Reset
f
f
f
X
/25
T1
X
/26
Count register (8)
Clear
MPX
From clock
generator
CP
X
/28
f
f
X
/210
/212
X
µ
RESET
Timer operation start
16 bit timer counter mode
IRQT1 clear signal
Selector
INTT1
IRQT1
set signal
Timer counter match signal (channel 2)
(During 16-bit timer counter mode)
Timer counter reload signal (channel 2)
Timer counter comparator (channel 2)
(During 16-bit timer counter mode)
Note Execution of instruction
Figure 6-7. Timer Counter Block Diagram (channel 2)
Internal bus
SET1Note
8
8
8
8
TMOD2H
TMOD2
TC2
PORT2.2 PMGB bit 2
TM2
High-level period setting
modulo register (8)
P22
Port 2
Modulo register (8)
8
TM26 TM25 TM24 TM23 TM22 TM21 TM20
TGCE
TOE2 REMC NRZB NRZ
Reload
output latch input/output
8
Decoder
MPX (8)
P22/PCL/PTO2
8
Match
Output buffer
TOUT
F/F
Comparator (8)
f
X
/2
/22
/24
Reset
8
Timer clock
input (channel 1)
T2
f
f
f
f
X
X
X
Overflow
Carrier generator mode
From clock
generator
Count register (8)
Clear
MPX
CP
/26
/28
X
f
X
/210
INTT2
IRQT2
16-bit timer counter mode
Timer operation start
set signal
IRQT2 clear signal
µ
RESET
Timer counter
Timer event counter
TOUT F/F (channel 0)
clear signal (channel 1)
(During 16-bit timer
counter mode)
From clock generator
Timer counter
Timer counter
match signal (channel 1)
(When carrier generator mode)
match signal (channel 1)
(During 16-bit timer
counter mode)
Note Execution of instruction
µPD753204, 753206, 753208
6.7 Serial Interface
The µPD753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four
modes.
•
Operation stop mode
•
•
•
3-wire serial I/O mode
2-wire serial I/O mode
SBI mode (serial bus interface mode)
Data Sheet U10166EJ2V1DS
31
Figure 6-8. Serial Interface Block Diagram
Internal bus
Bit test
8
Bit manipulation
RELT
Bit test
8/4
8
8
Slave address register (SVA) (8)
Match signal
SBIC
CSIM
CMDT
Address comparator
(8)
SO latch
P03/SI/SB1
P02/SO/SB0
SET CLR
Selector
Shift register (SIO)
(8)
D
Q
Busy/
acknowledge
output circuit
Selector
RELD
CMDD
ACKD
Bus release/
command/
acknowledge
detection circuit
µ
INTCSI
P01/SCK
INTCSI
control circuit
IRQCSI
set signal
Serial clock counter
f
f
f
X
X
X
/23
/24
/26
P01
output Iatch
Serial clock
selector
Serial clock control
circuit
TOUT0
(from timer/event counter
(channel 0))
External SCK
µPD753204, 753206, 753208
6.8 LCD Controller/Driver
The µPD753208 incorporates a display controller which generates segment and common signals according
to the display data memory contents and incorporates segment and common drivers which can drive the panel
directly.
The µPD753208 LCD controller/driver functions are as follows:
•
•
Display data memory is read automatically by DMA operation and segment and common signals are
generated.
Display mode can be selected from among the following five:
<1> Static
<2> 1/2 duty (time multiplexing by 2), 1/2 bias
<3> 1/3 duty (time multiplexing by 3), 1/2 bias
<4> 1/3 duty (time multiplexing by 3), 1/3 bias
<5> 1/4 duty (time multiplexing by 4), 1/3 bias
•
•
A frame frequency can be selected from among four in each display mode.
A maximum of 12 segment signal output pins (S12 to S23) and four common signal output pins (COM0 to
COM3).
•
•
The segment signal output pins (S16 to S23) can be changed to the I/O ports (PORT8 and PORT9).
Split-resistor can be incorporated to supply LCD drive power. (Mask option)
–
–
Various bias methods and LCD drive voltages can be applicable.
When display is off, current flowing through the split resistor is cut.
•
Display data memory not used for display can be used for normal data memory.
Data Sheet U10166EJ2V1DS
33
Figure 6-9. LCD Controller/Driver Block Diagram
Internal bus
4
4
4
4
4
8
4
8
4
4
4
Port 8
output latch
3 2 1 0
Port 9
Port mode
LCD/port
selection
register
1F7H
1F0H
1EFH
1ECH
Display
control
register
Port 3
Port mode
register group A
Display mode register
output latch register group C
output latch
3 2 1 0
0
1
3
3
2
1
0
0
3
3
2
1
0
3
2
1
0
0
3
3
2
1
0
0
1
0
1
0
Decoder
2
1
2
1
0
3
2
1
2
1
Timing
controller
fLCD
LCD drive
mode
switching
Port 8
Port 9
Input/Output buffer
LCD drive
voltage control
Segment driver
Segment driver
Common driver
µ
Input/Output buffer
0
1
2
3
0
1
2
3
S23/P80
S16/P93
S15
S0
COM3 COM2 COM1 COM0
VLC2
VLC1
VLC0
P31/SYNC P30/LCDCL
µPD753204, 753206, 753208
6.9 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing large data bit-wise.
Figure 6-10. Bit Sequential Buffer Format
Address
Bit
FC3H
FC2H
FC1H
FC0H
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Symbol
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H L = 7H
L = 4H L = 3H
DECS L
L = 0H
INCS L
Remarks 1. In pmem.@L addressing, the specified bit moves corresponding to the L register.
2. In pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.
Data Sheet U10166EJ2V1DS
35
µPD753204, 753206, 753208
7. INTERRUPT FUNCTION AND TEST FUNCTION
There are seven interrupt sources and two test sources in the µPD753208.
The interrupt control circuit of the µPD753208 has the following functions.
(1) Interrupt function
•
Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IE×××) and interrupt master enable flag (IME).
Can set any interrupt start address.
•
•
Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).
•
•
Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.
Release the standby mode. A release interrupt can be selected by the interrupt enable flag.
(2) Test function
•
•
Test request flag (IRQ×××) generation can be checked by software.
Release the standby mode. The test source to be released can be selected by the test enable flag.
36
Data Sheet U10166EJ2V1DS
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus
2
4
IME IPS
IST1 IST0
Interruput enable flag (IE×××
)
IM2
IM0
Decoder
IRQBT
IRQ4
INTBT
VRQn
Both edge
detector
INT4/P00
INT0/P10
Edge
detector
Selec-
tor
Note
IRQ0
INTCSI
IRQCSI
IRQT0
IRQT1
IRQT2
IRQW
IRQ2
Vector table
address
generator
Priority control
circuit
INTT0
INTT1
INTT2
INTW
µ
Selec-
tor
Standby release
signal
KR0/P60
KR3/P63
Falling edge
detector
IM2
Note Noise eliminator (Standby release is disabled when noise eliminator is selected.)
µPD753204, 753206, 753208
8. STANDBY FUNCTION
In order to save power dissipation while a program is in standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the µPD753208.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP mode
STOP instruction
HALT mode
HALT instruction
Set instruction
Operation Clock generator
status
The system clock stops oscillation.
Only the CPU clock Φ halts (oscillation
continues).
Basic interval timer/
Watchdog timer
Operation stops.
Operable only when the system clock
is oscillated. (The IRQBT is set in the
reference interval).
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable
Timer/event counter
Operable only when a signal input to
the TI0 pin is specified as the count
clock.
Operable
Watch timer
Operation stops.
Operation stops.
Operable
Operable
LCD controller/driver
External interrupt
The INT4 is operable.
Note
Only the INT0 is not operated
.
CPU
Operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag or RESET signal input.
Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register
(IM0).
38
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
9. RESET FUNCTION
There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/
watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure
9-1 shows the circuit diagram of the above two inputs.
Figure 9-1. Configuration of Reset Function
RESET
Internal RESET signal
RESET signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Each hardware is initialized by the RESET signal generation as listed in Table 9-1. Figure 9-2 shows the
timing chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET
signal
generated
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Note The following two times can be selected by the mask option.
217/fX (21.8 ms: @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation)
215/fX (5.46 ms: @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation)
Data Sheet U10166EJ2V1DS
39
µPD753204, 753206, 753208
Table 9-1. Status of Each Device After Reset (1/2)
RESET signal generation
in the standby mode
RESET signal generation
during operation
Hardware
Program counter (PC)
µPD753204 Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
µPD753206, Sets the low-order 5 bits of
µPD753208 program memory's address
0000H to PC12 to PC8 and
Sets the low-order 5 bits of
program memory's address
0000H to PC12 to PC8 and
the contents of address 0001H
to PC7 to PC0.
the contents of address 0001H
to PC7 to PC0.
PSW
Carry flag (CY)
Skip flag (SK0-SK2)
Held
0
Undefined
0
0
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
0
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
Data memory (RAM)
1000B
1000B
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Bank select register (MBS, RBS)
Held
Undefined
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog Mode register (BTM)
0
0
0
0
timer
Watchdog timer enable flag (WDTM)
Timer/event
counter (T0)
Counter (T0)
0
0
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
FFH
0
FFH
0
0, 0
0
0, 0
0
Timer
Counter (T1)
counter (T1)
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT F/F
FFH
0
FFH
0
0, 0
0
0, 0
0
Timer
Counter (T2)
counter (T2)
Modulo register (TMOD2)
FFH
FFH
FFH
FFH
High-level period setting modulo
register (TMOD2H)
Mode register (TM2)
TOE2, TOUT F/F
REMC, NRZ, NRZB
TGCE
0
0, 0
0, 0, 0
0
0
0, 0
0, 0, 0
0
Watch timer
Mode register (WM)
0
0
40
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Table 9-1. Status of Each Device After Reset (2/2)
RESET signal generation
in the standby mode
RESET signal generation
during operation
Hardware
Serial interface
Clock generator,
Shift register (SIO)
Held
Undefined
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register (PCC)
0
0
0
0
Held
Undefined
0
0
clock output circuit Clock output mode register (CLOM)
0
0
LCD controller/
driver
Display mode register (LCDM)
Display control register (LCDC)
LCD/port selection register (LPS)
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Interrupt priority selection register (IPS)
INT0, 2 mode registers (IM0, IM2)
Output buffer
0
0
0
0
0
0
Interrupt
function
Reset (0)
Reset (0)
0
0
0
0
0, 0
0, 0
Digital port
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, B, C)
Pull-up resistor setting register (POGA, B)
0
0
0
0
Bit sequential buffer (BSB0 to BSB3)
Held
Undefined
Data Sheet U10166EJ2V1DS
41
µPD753204, 753206, 753208
10. MASK OPTION
The µPD753208 has the following mask options.
•
•
P50 to P53 mask options
Selects whether or not to connect an internal pull-up resistor.
<1> Connect pull-up resistor internally bit-wise.
<2> Do not connect pull-up resistor internally.
VLC0 to VLC2 pins, BIAS pins mask option
Selects whether or not to internally connect LCD-driving split resistors.
<1> Do not connect split resistor internally.
<2> Connect four 10-kΩ (typ.) split resistors simultaneously internally.
<3> Connect four 100-kΩ (typ.) split resistors simultaneously internally.
Standby function mask option
•
Selects the wait time with the RESET signal.
<1> 217/fx (21.8 ms: When fX = 6.0 MHz, 31.3 ms: When fX = 4.19 MHz)
<2> 215/fx (5.46 ms: When fX = 6.0 MHz, 7.81 ms: When fX = 4.19 MHz)
42
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
11. INSTRUCTION SET
(1) Expression formats and description methods of operands
The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER
PACKAGE USERS’ MANUAL—LANGUAGE (EEU-1363)". If there are several elements, one of them
is selected. Capital letters and the + and – symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.
However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
the user's manual.
Representation
Description method
format
reg
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
reg1
rp
XA, BC, DE, HL
rp1
rp2
rp'
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rp'1
rpa
HL, HL+, HL–, DE, DL
DE, DL
rpa1
n4
n8
4-bit immediate data or label
8-bit immediate data or label
Note
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
pmem
addr
000H-FFFH immediate data or label (µPD753204)
0000H-17FFH immediate data or label (µPD753206)
0000H-1FFFH immediate data or label (µPD753208)
000H-FFFH immediate data or label (µPD753204)
0000H-17FFH immediate data or label (µPD753206)
0000H-1FFFH immediate data or label (µPD753208)
12-bit immediate data or label
addr1
(Only in the
MKII mode)
caddr
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit 0 = 0) or label
PORTn
IE×××
RBn
PORT0-PORT3, PORT5, PORT6, PORT8, PORT9
IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW
RB0-RB3
MBn
MB0, MB1, MB15
Note mem can be only used for even address in 8-bit data processing.
Data Sheet U10166EJ2V1DS
43
µPD753204, 753206, 753208
(2) Legend in explanation of operation
A
: A register, 4-bit accumulator
: B register
B
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
BC
DE
HL
XA’
BC’
DE’
HL’
PC
SP
CY
PSW
MBE
RBE
: XA register pair; 8-bit accumulator
: BC register pair
: DE register pair
: HL register pair
: XA’ expanded register pair
: BC’ expanded register pair
: DE’ expanded register pair
: HL’ expanded register pair
: Program counter
: Stack pointer
: Carry flag, bit accumulator
: Program status word
: Memory bank enable flag
: Register bank enable flag
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
IME
IPS
: Interrupt master enable flag
: Interrupt priority selection register
: Interrupt enable flag
IE×××
RBS
MBS
PCC
.
: Register bank selection register
: Memory bank selection register
: Processor clock control register
: Separation between address and bit
: Contents addressed by ××
: Hexadecimal data
(××)
××H
44
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
(3) Explanation of symbols under addressing area column
*1
MB = MBE•MBS
(MBS = 0, 1, 15)
*2
*3
MB = 0
MBE = 0 : MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
Data memory addressing
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
*5
*6
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
MB = 15, pmem = FC0H-FFFH
µPD753204
µPD753206
µPD753208
addr = 000H-FFFH
addr = 0000H-17FFH
addr = 0000H-1FFFH
*7
*8
addr, addr1 = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
µPD753204
µPD753206
caddr = 000H-FFFH
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-17FFH(PC12 = 1)
Program memory addressing
µPD753208
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-1FFFH(PC12 = 1)
*9
faddr = 0000H-07FFH
taddr = 0020H-007FH
*10
*11
µPD753204
µPD753206
µPD753208
addr1 = 000H-FFFH
addr1 = 0000H-17FFH
addr1 = 0000H-1FFFH
Remarks 1. MB indicates memory bank that can be accessed.
2. In *2, MB = 0 independently of how MBE and MBS are set.
3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4. *6 to *11 indicate the areas that can be addressed.
(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.
•
•
•
When no skip is made: S = 0
When the skipped instruction is a 1- or 2-byte instruction: S = 1
When the skipped instruction is a 3-byte instruction Note: S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types
by setting PCC.
Data Sheet U10166EJ2V1DS
45
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
MOV
Operand
Operation
Skip condition
String effect A
area
Transfer
instruction
A, #n4
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
2
A ← n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
reg1 ← n4
2
XA ← n8
String effect A
String effect B
2
HL ← n8
2
rp2 ← n8
1
A ← (HL)
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
2+S
2+S
1
A ← (HL), then L ← L+1
A ← (HL), then L ← L–1
A ← (rpa1)
L = 0
L = FH
2
XA ← (HL)
1
(HL) ← A
2
(HL) ← XA
2
A ← (mem)
XA ← (mem)
(mem) ← A
(mem) ← XA
A ← reg
2
2
2
2
XA, rp'
2
XA ← rp'
reg1, A
2
reg1 ← A
rp'1, XA
A, @HL
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
A, mem
XA, mem
A, reg1
2
rp'1 ← XA
XCH
1
A ↔ (HL)
*1
*1
*1
*2
*1
*3
*3
2+S
2+S
1
A ↔ (HL), then L ← L+1
A ↔ (HL), then L ← L–1
A ↔ (rpa1)
XA ↔ (HL)
L = 0
L = FH
2
2
A ↔ (mem)
XA ↔ (mem)
A ↔ reg1
2
1
XA, rp'
2
XA ↔ rp'
46
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
MOVT
Operand
Operation
Skip condition
area
Table
reference
XA, @PCDE
1
3
● µPD753204
XA ← (PC11–8+DE)ROM
● µPD753206, 753208
XA ← (PC12–8+DE)ROM
XA, @PCXA
1
3
● µPD753204
XA ← (PC11–8+XA)ROM
● µPD753206, 753208
XA ← (PC12–8+XA)ROM
Note
XA, @BCDE
XA, @BCXA
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
1
1
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
3
3
XA ← (BCDE)ROM
*6
*6
*4
*5
*1
*4
*5
*1
Note
XA ← (BCXA)ROM
Bit transfer
MOV1
2
CY ← (fmem.bit)
2
CY ← (pmem7–2+L3–2.bit(L1–0))
CY ← (H+mem3–0.bit)
(fmem.bit) ← CY
2
2
2
(pmem7–2+L3–2.bit(L1–0)) ← CY
(H+mem3–0.bit) ← CY
A ← A+n4
2
Operation
ADDS
1+S
2+S
1+S
2+S
2+S
1
carry
carry
carry
carry
carry
XA, #n8
XA ← XA+n8
A, @HL
A ← A+(HL)
*1
*1
*1
*1
XA, rp'
XA ← XA+rp'
rp'1, XA
rp'1 ← rp'1+XA
ADDC
SUBS
SUBC
A, @HL
A, CY ← A+(HL)+CY
XA, CY ← XA+rp'+CY
rp'1, CY ← rp'1+XA+CY
A ← A–(HL)
XA, rp'
2
rp'1, XA
2
A, @HL
1+S
2+S
2+S
1
borrow
borrow
borrow
XA, rp'
XA ← XA–rp'
rp'1, XA
rp'1 ← rp'1–XA
A, @HL
A, CY ← A–(HL)–CY
XA, CY ← XA–rp'–CY
rp'1, CY ← rp'1–XA–CY
XA, rp'
2
rp'1, XA
2
Note Set "0" to register B if the µPD753204 is used. Only the low-order one bit of register B will be valid if the
µPD753206 or 753208 is used.
Data Sheet U10166EJ2V1DS
47
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
AND
Operand
Operation
Skip condition
area
Operation
A, #n4
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
2
1
A ← A ∧ n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A
A ← A ∧ (HL)
XA ← XA ∧ rp'
rp'1 ← rp'1 ∧ XA
A ← A ∨ n4
*1
2
2
OR
2
1
A ← A ∨ (HL)
XA ← XA ∨ rp'
rp'1 ← rp'1 ∨ XA
A ← A v n4
*1
*1
2
2
XOR
2
1
A ← A v (HL)
XA ← XA v rp'
rp'1 ← rp'1 v XA
2
2
Accumulator RORC
manipulation
instructions
1
CY ← A
A ← A
0, A
3
← CY, An–1 ← A
n
NOT
A
2
Increment
and
Decrement
instructions
INCS
reg
1+S
1+S
2+S
2+S
1+S
2+S
2+S
2+S
1+S
2+S
2+S
2+S
1
reg ← reg+1
rp1 ← rp1+1
reg=0
rp1
rp1=00H
(HL)=0
@HL
(HL) ← (HL)+1
(mem) ← (mem)+1
reg ← reg–1
rp' ← rp'–1
*1
*3
mem
(mem)=0
reg=FH
rp'=FFH
reg=n4
DECS
reg
rp'
Comparison SKE
instruction
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY ← 1
*1
*1
*1
(HL) = n4
A = (HL)
XA = (HL)
A=reg
XA=rp'
Carry flag
manipulation
instruction
SET1
CLR1
SKT
CY
1
CY ← 0
CY
1+S
1
Skip if CY = 1
CY ← CY
CY=1
NOT1
CY
48
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
SET1
Operand
Operation
Skip condition
area
Memory bit
manipulation
instructions
mem.bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
(mem.bit) ← 1
(fmem.bit) ← 1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
fmem.bit
pmem.@L
2
(pmem7–2+L3–2.bit(L1–0)) ← 1
(H+mem3–0.bit) ← 1
@H+mem.bit
mem.bit
2
CLR1
2
(mem.bit) ← 0
fmem.bit
2
(fmem.bit) ← 0
pmem.@L
2
(pmem7–2+L3–2.bit(L1–0)) ← 0
(H+mem3–0.bit) ← 0
@H+mem.bit
mem.bit
2
SKT
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2
Skip if (mem.bit)=1
(mem.bit)=1
fmem.bit
Skip if (fmem.bit)=1
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
(mem.bit)=0
pmem.@L
Skip if (pmem7–2+L3–2.bit(L1–0))=1
Skip if (H+mem3–0.bit)=1
Skip if (mem.bit)=0
@H+mem.bit
mem.bit
SKF
fmem.bit
Skip if (fmem.bit)=0
(fmem.bit)=0
(pmem.@L)=0
(@H+mem.bit)=0
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
pmem.@L
Skip if (pmem7–2+L3–2.bit(L1–0))=0
Skip if (H+mem3–0.bit)=0
Skip if (fmem.bit)=1 and clear
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
Skip if (H+mem3–0.bit)=1 and clear
CY ← CY ∧ (fmem.bit)
@H+mem.bit
fmem.bit
SKTCLR
AND1
OR1
pmem.@L
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
2
CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0))
CY ← CY ∧ (H+mem3–0.bit)
CY ← CY ∨ (fmem.bit)
2
2
2
CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0))
CY ← CY ∨ (H+mem3–0.bit)
CY ← CY v (fmem.bit)
2
XOR1
2
2
CY ← CY v (pmem7–2+L3–2.bit(L1–0))
CY ← CY v (H+mem3–0.bit)
2
Data Sheet U10166EJ2V1DS
49
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
BR Note
Operand
Operation
Skip condition
area
Branch
instructions
addr
–
–
• µPD753204
*6
PC11–0 ← addr
Select the most appropriate instruction from
among BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.
• µPD753206, 753208
PC12–0 ← addr
Select the most appropriate instruction
from among BR !addr, BRCB !caddr
and BR $addr according to the
assembler being used.
addr1
–
–
• µPD753204
*11
PC11-0 ← addr1
Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.
• µPD753206, 753208
PC12–0 ← addr1
Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.
! addr
$addr
3
1
3
2
• µPD753204
PC11–0 ← addr
*6
*7
• µPD753206, 753208
PC12–0 ← addr
• µPD753204
PC11–0 ← addr
• µPD753206, 753208
PC12–0 ← addr
$addr1
1
2
• µPD753204
PC11–0 ← addr1
• µPD753206, 753208
PC12–0 ← addr1
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
50
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
BR
Operand
Operation
Skip condition
area
Branch
instruction
PCDE
2
2
2
2
3
2
3
3
3
3
3
3
2
3
• µPD753204
PC11–0 ← PC11-8+DE
• µPD753206, 753208
PC12–0 ← PC12-8+DE
PCXA
BCDE
BCXA
!addr1
!caddr
• µPD753204
PC11–0 ← PC11-8+XA
• µPD753206, 753208
PC12–0 ← PC12-8+XA
• µPD753204
*6
*6
PC11–0 ← BCDE Note 1
• µPD753206, 753208
PC12–0 ← BCDE Note 2
• µPD753204
PC11–0 ← BCXA Note 1
• µPD753206, 753208
PC12–0 ← BCXA Note 2
BRA Note 3
• µPD753204
*6
PC11–0 ← addr1
• µPD753206, 753208
PC12–0 ← addr1
BRCB
• µPD753204
*8
PC11–0 ← caddr11–0
• µPD753206, 753208
PC12–0 ← PC12+caddr11–0
Subroutine
stack control
instructions
CALLA Note 3 !addr1
• µPD753204
*11
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr1, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr1, SP ← SP–6
Notes 1. "0" must be set to the B register.
2. Only the low-order one bit is valid in the B register.
3. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
Data Sheet U10166EJ2V1DS
51
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
CALL Note
Operand
Operation
Skip condition
area
Subroutine
stack control
instructions
!addr
3
3
• µPD753204
*6
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← addr, SP ← SP–4
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← addr, SP ← SP–4
4
• µPD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr, SP ← SP–6
CALLF Note !faddr
2
2
• µPD753204
*9
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← 0+faddr, SP ← SP–4
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← 00+faddr, SP ← SP–4
3
• µPD753204
←
(SP–2)
×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← 0+faddr, SP ← SP–6
• µPD753206, 753208
←
(SP–2)
×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← 00+faddr, SP ← SP–6
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
52
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
RET Note
Operand
Operation
Skip condition
area
Subroutine
stack control
instructions
1
3
• µPD753204
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4
• µPD753206, 753208
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, PC12 ← (SP+1), SP ← SP+4
• µPD753204
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0, ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
• µPD753206, 753208
×, ×, MBE, RBE ← (SP+4)
MBE, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
RETS Note
1
3+S
• µPD753204
Unconditional
MBE, RBE, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD753206, 753208
MBE, RBE, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+4
then skip unconditionally
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
Data Sheet U10166EJ2V1DS
53
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
RETI Note 1
Operand
Operation
Skip condition
area
Subroutine
stack control
instructions
1
3
• µPD753204
MBE, RBE, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
MBE, RBE, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
PUSH
rp
1
1
(SP–1)(SP–2) ← rp, SP ← SP–2
BS
rp
2
1
2
2
2
1
2
2
(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2
rp ← (SP+1) (SP), SP ← SP+2
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
IME (IPS.3) ← 1
POP
EI
BS
Interrupt
control
instructions
IE×××
2
2
2
2
IE××× ← 1
DI
IME (IPS.3) ← 0
IE××× ← 0
IE×××
2
2
2
2
2
2
Input/output
instructions
IN Note 2
A, PORTn
XA, PORTn
A ← PORTn
(n = 0-3, 5, 6, 8, 9)
(n = 8)
XA ← PORTn+1, PORTn
OUT Note 2
PORTn, A
2
2
2
2
2
2
PORTn ← A
(n = 3, 5, 6, 8, 9)
(n = 8)
PORTn, XA
PORTn+1, PORTn ← XA
CPU control HALT
instructions
Set HALT Mode (PCC.2 ← 1)
STOP
2
1
2
2
2
1
2
2
Set STOP Mode (PCC.3 ← 1)
No Operation
NOP
Special
SEL
RBn
MBn
RBS ← n
(n = 0-3)
instructions
MBS ← n
(n = 0, 1, 15)
Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and
MBS must be set to 15.
54
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
Operand
Operation
Skip condition
area
Special
instructions
GET Notes 1, 2 taddr
1
3
• µPD753204
*10
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP–3) ← MBE, RBE, 0, 0
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
Depending on
the reference
instruction
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
• µPD753206, 753208
• When TBR instruction
PC12–0 ← (taddr)4–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP–3) ← MBE, RBE, 0, PC12
PC12–0 ← (taddr)4–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
Depending on
the reference
instruction
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
3
• µPD753204
*10
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – -
– – – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – -
– – – – – – – – – – – – –
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
Data Sheet U10166EJ2V1DS
55
µPD753204, 753206, 753208
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
Mnemonic
Operand
Operation
Skip condition
area
Special
instructions
GETI Notes 1, 2 taddr
1
3
• µPD753206, 753208
*10
• When TBR instruction
PC12–0 ← (taddr)4–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
(SP–2) ← ×, ×, MBE, RBE
PC12–0 ← (taddr)4–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – –
Depending on
the reference
instruction
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode.
56
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25˚C)
Parameter
Supply voltage
Input voltage
Symbol
VDD
Test Conditions
Rating
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +14
–0.3 to VDD + 0.3
–10
Unit
V
VI1
Except port 5
V
VI2
Port 5
On-chip pull-up resistor
When N-ch open-drain
V
V
Output voltage
VO
IOH
V
Output current high
Per pin
mA
mA
mA
mA
˚C
Total for all pins
Per pin
–30
Output current low
IOL
30
Total for all pins
220
Note
Operating ambient
temperature
TA
–40 to +85
Storage temperature
Tstg
–65 to +150
˚C
Note When LCD is driven in normal mode: TA = –10 to +85˚C
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter or even momentarily. That is, the absolute ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used
under conditions which ensure that the absolute maximum ratings are not exceeded.
CAPACITANCE (TA = 25˚C, VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CIN
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V.
COUT
CIO
15
pF
15
pF
Data Sheet U10166EJ2V1DS
57
µPD753204, 753206, 753208
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Parameter
Test conditions
MIN. TYP. MAX. Unit
Note
2
2
2
Ceramic
Oscillator
frequency (fX) Note 1
1.0
6.0
MHz
X2
X1
resonator
C1
C2
Oscillation
stabilization time Note 3
After VDD reaches oscil-
lation voltage range MIN.
4
ms
V
DD
Note
Crystal
Oscillator
frequency (fX) Note 1
1.0
6.0
MHz
ms
X2
X1
resonator
C1
C2
Oscillation
stabilization time Note 3
VDD = 4.5 to 5.5 V
10
30
V
DD
Note
External
clock
X1 input
frequency (fX) Note 1
1.0
6.0
MHz
ns
X1
X2
X1 input
83.3
500
high/low level width
(tXH, tXL)
Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to the AC characteristics.
2. When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95 µs. Therefore, set PCC
to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing
the STOP mode.
Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VDD.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
58
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
RECOMMENDED OSCILLATOR CONSTANTS
Ceramic resonator (TA = –40 to 85°C)
Oscillator constant (pF)
Oscillation voltage range (VDD)
Remark
Frequency
(MHz)
Manufacturer
TDK
Part number
C1
100
—
C2
100
—
MIN. (V)
MAX. (V)
CCR1000K2
CCR2.0MC33
CCR3.58MC3
CCR4.19MC3
FCR4.19MC5
CCR6.0MC3
FCR6.0MC5
1.0
2.0
1.8
5.5
—
2.0
On-chip
capacitor
3.58
4.19
2.2
2.5
6.0
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillaiton frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
Data Sheet U10166EJ2V1DS
59
µPD753204, 753206, 753208
DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IOL
Test conditions
MIN. TYP. MAX. Unit
Output voltage low
Per pin
15
150
mA
mA
V
Sum of the all pins
Ports 2, 3, 8, and 9
Input voltage high
VIH1
VIH2
VIH3
2.7 ≤ VDD ≤ 5.5 V 0.7VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
2.7 ≤ VDD ≤ 5.5 V 0.8VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
VDD
VDD
V
Ports 0, 1, 6, RESET
VDD
V
VDD
V
Port 5
When a pull-up register 2.7 ≤ VDD ≤ 5.5 V 0.7VDD
VDD
V
is incorporated
1.8 ≤ VDD < 2.7 V 0.9VDD
VDD
V
When N-ch open-drain 2.7 ≤ VDD ≤ 5.5 V 0.7VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
VDD – 0.1
13
V
13
V
VIH4
VIL1
X1
VDD
V
Input voltage low
Ports 2, 3, 5, 8, and 9
Ports 0, 1, 6, RESET
X1
2.7 ≤ VDD ≤ 5.5 V
1.8 ≤ VDD < 2.7 V
2.7 ≤ VDD ≤ 5.5 V
1.8 ≤ VDD < 2.7 V
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
0
V
0
0
V
VIL3
VOH
VOL1
V
Output voltage high
Output voltage low
SCK, SO, ports 2, 3, 6, 8, and 9 IOH = –1.0 mA
VDD – 0.5
V
SCK, SO, ports 2, 3, 5, 6, 8,
and 9
IOL = 15 mA,
0.2
2.0
V
VDD = 4.5 to 5.5 V
IOL = 1.6 mA
0.4
V
V
VOL2
SB0, SB1
N-ch open-drain
pull-up resistor ≥ 1 kΩ
0.2VDD
Input leakage
current high
ILIH1
ILIH2
ILIH3
ILIL1
ILIL2
ILIL3
VIN = VDD
Other pins than X1
3
20
20
–3
–20
–3
µA
µA
µA
µA
µA
µA
X1
VIN = 13 V
VIN = 0 V
Port 5 (When N-ch open-drain)
Other pins than port 5 and X1
X1
Input leakage
current low
Port 5 (When N-ch open drain)
Other than when an input instruction
is executed
Port 5 (When N-ch open-drain)
–30
–27
–8
µA
µA
µA
µA
When an input instruction
VDD = 5.0 V
is executed
–10
–3
VDD = 3.0 V
Output leakage
current high
ILOH1
VOUT = VDD
SCK, SO/SB0, SB1, ports 2, 3, 6, 8
and 9
3
Port 5 (When a pull-up resistor
is incorporated.)
ILOH2
ILOL
VOUT = 13 V
VOUT = 0 V
Port 5 (When N-ch open-drain)
20
–3
µA
µA
Output leakage
current low
On-chip pull-up resistor
RL1
RL2
VIN = 0 V
Ports 0 to 3, 6, 8, and 9
(Excluding P00 pin)
50
15
100
30
200
60
kΩ
kΩ
Port 5 (Mask option)
60
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
VLCD
Test conditions
TA = –40 to +85˚C
TA = –10 to +85˚C
MIN. TYP. MAX. Unit
LCD drive voltage
VAC0 = 0
VAC0 = 1
2.7
2.2
1.8
VDD
VDD
VDD
4
V
V
V
VAC current Note 1
IVAC
VAC0 = 1, VDD = 2.0 V 10%
1
µA
kΩ
kΩ
V
LCD split resistor Note 2
RLCD1
RLCD2
VODC
50
5
100
10
200
20
LCD output voltage
deviation Note 3 (common)
lO = 1.0 µA
lO = 0.5 µA
VLCD0 = VLCD
0
0.2
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
1.8 V ≤ VLCD ≤ VDD
LCD output voltage
deviation Note 3 (segment)
VODS
0
0.2
V
Note 5
Note 6
Supply current Note 4
IDD1
6.0 MHz
VDD = 5.0 V 10%
VDD = 3.0 V 10%
1.9
0.4
6.0
1.3
2.1
0.8
4.0
0.75
2.0
0.7
10
mA
mA
mA
mA
mA
mA
mA
mA
µA
Crystal oscillation
C1 = C2 = 22 pF
IDD2
IDD1
IDD2
IDD3
HALT mode VDD = 5.0 V 10%
VDD = 3.0 V 10%
0.72
0.27
1.5
4.19 MHz
VDD = 5.0 V 10% Note 5
VDD = 3.0 V 10% Note 6
HALT mode VDD = 5.0 V 10%
VDD = 3.0 V 10%
Crystal oscillation
C1 = C2 = 22 pF
0.25
0.7
0.23
0.05
0.02
0.02
STOP mode
VDD = 5.0 V 10%
VDD = 3.0 V
5
µA
10%
TA = 25˚C
3
µA
Notes 1. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1
µA.
2. Either RLCD1 or RLCD2 can be selected by the mask option.
3. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
6. When PCC is set to 0000 and the device is operated in the low-speed mode.
Data Sheet U10166EJ2V1DS
61
µPD753204, 753206, 753208
AC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
tCY
Test conditions
MIN. TYP. MAX. Unit
CPU clock cycle
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
INT0
0.67
0.95
0
64
64
µs
µs
Note 1
time
TI0 input frequency
fTI
1.0
275
MHz
kHz
µs
0
TI0 input
tTIH, tTIL
0.48
1.8
Note 2
10
high/low-level width
µs
Interrupt input high/
low-level width
tINTH,
tINTL
IM02 = 0
IM02 = 1
µs
µs
INT4
10
µs
KR0 to KR3
10
µs
RESET low level width
tRSL
10
µs
Notes 1. The cycle time (minimum instruc-
tion execution time) of the CPU
clock (Φ) is determined by the
oscillation frequency of the con-
nected resonator (and external
clock) and the processor clock
control register (PCC). The figure
at the right indicates the cycle
time tCY versus supply voltage
VDD characteristic.
t
CY vs VDD
64
30
6
5
Guaranteed Operation
Range
µ
4
3
2. 2tCY or 128/fX is set by setting the
interrupt mode register (IM0).
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
62
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
tKCY1
Test conditions
MIN.
TYP. MAX. Unit
SCK cycle time
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
1300
ns
ns
ns
ns
ns
ns
ns
ns
3800
SCK high/low-level
width
tKL1, tKH1
tKCY1/2 – 50
tKCY1/2 – 150
SINote 1 setup time
tSIK1
150
500
400
600
0
(to SCK↑)
SINote 1 hold time
tKSI1
(from SCK↑)
SONote 1 output delay
tKSO1
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
250
ns
ns
Note 2
time from SCK↓
CL = 100 pF
0
1000
Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
800
3200
400
1600
100
150
400
600
0
TYP. MAX. Unit
SCK cycle time
tKCY2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
ns
ns
SCK high/low-level
width
tKL2, tKH2
SINote 1 setup time
tSIK2
(to SCK↑)
SINote 1 hold time
tKSI2
(from SCK↑)
SONote 1 output delay
tKSO2
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
300
ns
ns
Note 2
time from SCK↓
CL = 100 pF
0
1000
Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines.
Data Sheet U10166EJ2V1DS
63
µPD753204, 753206, 753208
SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
tKCY3
Test conditions
MIN.
1300
TYP. MAX. Unit
SCK cycle time
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
ns
3800
SCK high/low-level
width
tKL3, tKH3
tKCY3/2 – 50
tKCY3/2 – 150
150
SB0, 1 setup time
tSIK3
(to SCK↑)
500
SB0, 1 hold time
tKSI3
tKCY3/2
(from SCK↑)
Note
SB0, 1 output delay
tKSO3
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
0
250
ns
ns
ns
ns
ns
ns
time from SCK↓
0
1000
SB0, 1↓ from SCK↑
SCK↓ from SB0, 1↑
SB0, 1 low-level width
SB0, 1 high-level width
tKSB
tSBK
tSBL
tSBH
tKCY3
tKCY3
tKCY3
tKCY3
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.
SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
800
TYP. MAX. Unit
SCK cycle time
tKCY4
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
ns
3200
400
SCK high/low-level
width
tKL4, tKH4
1600
100
SB0, 1 setup time
tSIK4
(to SCK↑)
150
SB0, 1 hold time
tKSI4
tKCY4/2
(from SCK↑)
Note
SB0, 1 output delay
tKSO4
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
0
300
ns
ns
ns
ns
ns
ns
time from SCK↓
0
1000
SB0, 1↓ from SCK↑
SCK↓ from SB0, 1↑
SB0, 1 low-level width
SB0, 1 high-level width
tKSB
tSBK
tSBL
tSBH
tKCY4
tKCY4
tKCY4
tKCY4
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.
64
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
AC Timing Test Point (Excluding X1 Input)
V
IH (MIN.)
IL (MAX.)
V
IH (MIN.)
IL (MAX.)
V
V
V
OH (MIN.)
OL (MAX.)
V
OH (MIN.)
OL (MAX.)
V
V
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
TI0 Timing
1/fTI
t
TIL
t
TIH
TI0
Data Sheet U10166EJ2V1DS
65
µPD753204, 753206, 753208
Serial Transfer Timing
3-wire serial I/O mode
t
KCY1, 2
tKL1, 2
t
KH1, 2
SCK
t
SIK1, 2
t
KSI1, 2
SI
Input Data
t
KSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
66
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tSIK3, 4
tKSI3, 4
tKSB
tSBL
tSBH
tSBK
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
t
KL3, 4
t
KH3, 4
SCK
tSIK3, 4
tKSB
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INTP0, 4
KR0 to 3
RESET input timing
t
RSL
RESET
Data Sheet U10166EJ2V1DS
67
µPD753204, 753206, 753208
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85˚C)
Parameter
Symbol
tSREL
Test conditions
MIN. TYP. MAX. Unit
Release signal set time
0
µs
ms
ms
Oscillation stabilization
wait time Note 1
tWAIT
Release by RESET
Release by interrupt
Note 2
Note 3
Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2. Either 217/fX or 215/fX can be selected by the mask option.
3. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait time
When fx = 4.19-MHz operation When fx = 6.0-MHz operation
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
220/fX (approx. 250 ms)
217/fX (approx. 31.3 ms)
215/fX (approx. 7.81 ms)
213/fX (approx. 1.95 ms)
220/fX (approx. 175 ms)
217/fX (approx. 21.8 ms)
215/fX (approx. 5.46 ms)
213/fX (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
Halt mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Halt mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
68
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
13. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (System Clock : 6.0-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
0.5
PCC = 0000
System clock
HALT mode
0.1
0.05
X1
X2
Crystal
resonator
6.0 MHz
22 pF
22 pF
VDD
0.01
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
Data Sheet U10166EJ2V1DS
69
µPD753204, 753206, 753208
IDD vs VDD (System Clock : 4.19-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
1.0
0.5
PCC = 0001
PCC = 0000
System clock
HALT mode
0.1
0.05
X1
X2
Crystal
resonator
4.19 MHz
22 pF
22 pF
VDD
0.01
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
70
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
14. PACKAGE DRAWINGS
48 PIN PLASTIC SHRINK SOP (375 mil)
48
25
detail of lead end
1
24
A
H
I
J
N
C
L
B
D
M
M
P48GT-65-375B-1
NOTE
ITEM
MILLIMETERS
16.21 MAX.
0.63 MAX.
0.65 (T.P.)
0.30 0.10
0.125 0.075
2.0 MAX.
INCHES
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
A
B
C
D
E
F
0.639 MAX.
0.025 MAX.
0.026 (T.P.)
+0.004
–0.005
0.012
0.005 0.003
0.079 MAX.
G
H
I
1.7 0.1
0.067 0.004
+0.012
–0.013
10.0 0.3
0.394
8.0 0.2
0.315 0.008
+0.009
–0.008
0.039
J
1.0 0.2
+0.10
+0.004
0.15
0.006
K
L
–0.05
–0.002
+0.008
–0.009
0.5 0.2
0.10
0.020
M
N
0.004
0.004
0.10
Data Sheet U10166EJ2V1DS
71
µPD753204, 753206, 753208
15. RECOMMENDED SOLDERING CONDITIONS
The µPD753204, µPD753206, and µPD753208 should be soldered and mounted under the following
recommended conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 15-1. Surface Mounting Type Soldering Conditions
(1) µPD753204GT-xxx: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
µPD753206GT-xxx: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
µPD753208GT-xxx: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-2
Count: Twice or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-2
Count: Twice or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
(2) µPD753204GT-xxx-A: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
µPD753206GT-xxx-A: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
µPD753208GT-xxx-A: 48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
Undefined
Remark Products with “-A” at the end of the part number are lead-free products.
72
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST
Parameter
Program memory
µPD753108
µPD753208
µPD75P3216
Mask ROM
0000H-1FFFH
(8192 × 8 bits)
One-time PROM
0000H-3FFFH
(16384 × 8 bits)
Data memory
CPU
000H-1FFH
(512 × 4 bits)
75XL CPU
Instruction
execution
time
When main system
clock is selected
•
•
0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation)
When subsystem
clock is selected
122 µs (@ 32.768-kHz
operation)
None
I/O port
CMOS input
8 (on-chip pull-up resistors can
be specified by software: 7)
6 (on-chip pull-up resistors can be specified by software: 5)
CMOS input/output
20 (on-chip pull-up resistors can be specified by software)
N-ch open drain
input/output
4 (on-chip pull-up resistors can be specified by software,
withstand voltage is 13 V)
4 (no mask option, withstand
voltage is 13 V)
Total
32
30
LCD controller/driver
Segment selection: 16/20/24
(can be changed to CMOS
input/output port in 4 time-
unit; max. 8)
Segment selection: 4/8/12 segments
(can be changed to CMOS input/output port in 4 time-unit;
max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by
using mask option.
No on-chip split resistor for
LCD driver
Timer
5 channels
5 channels
• 8-bit timer/event
• 8-bit timer counter: 2 channels (can be used as the 16-bit
timer counter, carrier generator, and timer with gate)
• 8-bit timer/event counter: 1 channel
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
counter: 3 channels
• Basic interval timer/
watchdog timer: 1 channel
• Watch timer: 1 channel
Clock output (PCL)
Buzzer output (BUZ)
• Φ, 524, 262, 65.5 kHz
(Main system clock: @ 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock: @ 6.0-MHz operation)
• 2, 4, 32 kHz
• 2, 4, 32 kHz
(Main system clock: @
4.19-MHz operation or sub-
(Main system clock: @ 4.19-MHz operation)
• 2.93, 5.86, 46.9 kHz
system clock: @ 32.768-kHz (Main system clock: @ 6.0-MHz operation)
operation)
• 2.86, 5.72, 45.8 kHz
(Main system clock: @
6.0-MHz operation)
Serial interface
3 modes are available
• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
• 2-wire serial I/O mode
• SBI mode
SCC register
Contained
None
SOS register
Vectored interrupt
External: 3, internal: 5
External: 2, internal: 5
Data Sheet U10166EJ2V1DS
73
µPD753204, 753206, 753208
Parameter
µPD753108
External: 1, internal: 1
VDD = 1.8 to 5.5 V
µPD753208
µPD75P3216
Test input
Operation supply voltage
Operating ambient temperature
Package
TA = –40 to +85°C
• 64-pin plastic QFP
(14 × 14 mm)
• 48-pin plastic shrink SOP
(375 mils, 0.65-mm pitch)
• 64-pin plastic QFP
(12 × 12 mm)
74
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD753208.
In 75XL series, the relocatable assembler which is common to the µPD753208 Subseries is used in combination
with the device file of each product.
Language processor
RA75X relocatable assembler
Part number
Host machine
(product name)
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOSTM
Ver. 3.30 to
µS5A13RA75X
µS5A10RA75X
Note
Ver. 6.2
IBM PC/ATTM and
compatible machines
Refer to section
“OS for IBM PC”
3.5-inch 2HC
5-inch 2HC
µS7B13RA75X
µS7B10RA75X
Device file
Part number
(product name)
Host machine
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOS
Ver. 3.30 to
µS5A13DF753208
µS5A10DF753208
Note
Ver. 6.2
3.5-inch 2HC
5-inch 2HC
µS7B13DF753208
µS7B10DF753208
IBM PC/AT and
compatible machines
Refer to section
“OS for IBM PC”
PROM write tools
Hardware
PG-1500
PG-1500 is a PROM programmer which enables you to program single chip microcomputers
including PROM by stand-alone or host machine operation by connecting an attached board
and optional programmer adapter to PG-1500. It also enables you to program typical PROM
devices of 256 Kbits to 4 Mbits.
PA-75P3216GT
PROM programmer adapter for the µPD75P3216GT. Connect the programmer adapter to
PG-1500 for use.
Software
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500
is controlled on the host machine.
Part number
(product name)
Host machine
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOS
Ver. 3.30 to
Ver. 6.2Note
µS5A13PG1500
µS5A10PG1500
3.5-inch 2HD
5-inch 2HC
µS7B13PG1500
µS7B10PG1500
IBM PC/AT and
compatible machines
Refer to section
“OS for IBM PC”
Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the assembler and device file is guaranteed only on the above host machine and OSs.
2. Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.
Data Sheet U10166EJ2V1DS
75
µPD753204, 753206, 753208
Debugging tool
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
µPD753208.
The system configurations are described as follows.
Note 1
Hardware
IE-75000-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-
753208GT-R that are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging
can be made.
It contains the emulation board IE-75000-R-EM which is connected.
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-
753208GT-R which are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM
programmer.
IE-75300-R-EM
EP-753208GT-R
Emulation board for evaluating the application systems that use a µPD753208
subseries.
It must be used with the IE-75000-R or IE-75001-R.
Emulation probe for the µPD753208GT.
It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 48-pin conversion adapter EV-9500GF-48 which facilitates
connection to a target system.
EV-9500GF-48
Software
IE control program
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix
I/F and controls the above hardware on a host machine.
Part No.
(product name)
Host machine
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOS
µS5A13IE75X
µS5A10IE75X
Ver. 3.30 to
Ver. 6.2 Note 2
3.5-inch 2HC
5-inch 2HC
µS7B13IE75X
µS7B10IE75X
IBM PC/AT and its
compatible machine
Refer to section
“OS for IBM PC”
Notes 1. Maintenance parts.
2. Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.
2. The µPD753204, 753206, 753208, and 75P3216 are commonly referred to as the µPD753208
Subseries.
76
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
OS for IBM PC
The following IBM PC OS’s are supported.
OS
Version
PC DOSTM
Ver. 5.02 to Ver. 6.3
Note
Note
J6.1/V
to J6.3/V
MS-DOS
Ver. 5.0 to Ver. 6.22
Note
Note
5.0/V
to 6.2/V
Note
IBM DOSTM
J5.02/V
Note English version is supported.
Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software.
Data Sheet U10166EJ2V1DS
77
µPD753204, 753206, 753208
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to device
Document No.
Japanese English
Document Name
µPD753204, 753206, 753208 Data Sheet
µPD75P3216 Data Sheet
U10166J
U10241J
U10158J
U10453J
This manual
U10241E
U10158E
U10453E
µPD753208 User’s Manual
75XL Series Selection Guide
Documents related to development tool
Document No.
Document Name
Japanese
EEU-846
U11354J
U10739J
U11940J
EEU-731
EEU-730
EEU-704
English
Hardware
Software
IE-75000-R/IE-75001-R User‘s Manual
EEU-1416
U11354E
U10739E
EEU-1335
EEU-1346
EEU-1363
EEU-1291
IE-75300-R-EM User’s Manual
EP-753208GT-R User’s Manual
PG-1500 User’s Manual
RA75X Assembler Package User’s Manual
Operation
Language
PG-1500 Controller User’s Manual
PC-9800 Series
(MS-DOS) Base
IBM PC Series
(PC DOS) Base
EEU-5008
U10540E
Other related documents
Document No.
Document Name
Japanese
C10943X
C10535J
C11531J
C10983J
MEM-539
C11893J
C11416J
English
Semiconductor Device Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
C10535E
C11531E
C10983E
IEI-1201
MEI-1202
–
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
Guide to Quality Assurance for Semiconductor Devices
Microcontroller – Related Product Guide – Third Party Products –
Caution The contents of the documents listed above are subject to change without prior notice to users.
Make sure to use the latest edition when starting design.
78
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet U10166EJ2V1DS
79
µPD753204, 753206, 753208
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
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Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
80
Data Sheet U10166EJ2V1DS
µPD753204, 753206, 753208
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
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"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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