UPD754302GS-XXX-A [RENESAS]
UPD754302GS-XXX-A;
| 型号： | UPD754302GS-XXX-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | UPD754302GS-XXX-A 光电二极管 |
| 文件： | 总75页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD754302,754304,754302(A),754304(A)
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD754304 is one of the “75XL Series” 4-bit single-chip microcontrollers with data processing capability
comparable to that of 8-bit microcontrollers. The µPD754303(A) has a higher reliability than the µPD754304.
The microcontrollers in the 75XL Series have expanded CPU functions than those of the 75X Series and can operate
at a voltage of as low as 1.8 V; therefore, they are ideal for battery-driven application systems.
As the one-time PROM version of the µPD754304, the µPD75P4308 is ideal for evaluation of a system under
development or for small-scale production of application systems.
Detailed information about functions can be found in the following document. Be sure to read the following
document before designing.
µPD754304 User’s Manual: U10123E
FEATURES
•
Variable instruction execution time effective for high-
speed operation and power saving
•
•
Low-voltage operation: VDD = 1.8 to 5.5 V
Internal memory
0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz)
0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz)
Internal serial interface (1 channel)
Powerful timer function (3 channels)
Inherits instruction set of existing 75X Series for easy
replacement
Program memory (ROM):
2048 × 8 bits (µPD754302, 754302(A))
4096 × 8 bits (µPD754304, 754304(A))
Data memory (RAM): 256 × 4 bits
•
•
•
APPLICATIONS
•
µPD754302, 754302(A)
Cordless telephones, TVs, VCRs, audio systems, household appliances, office machines, etc.
•
µPD754304, 754304(A)
Automotive appliance, etc.
The µPD754302 and 754304 differ from the µPD754302(A) and 754304(A) only in terms of their quality grade.
Unless otherwise specified, the µPD754304 is treated as a representative model in this Data Sheet.
For the models other than the µPD754304, µPD754304 can be read as the other model name.
If different descriptions are made for the µPD754302 and 754304, the (A) models correspond as follows:
µPD754302 → µPD754302(A), µPD754304 → µPD754304(A)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U10797EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1996
µPD754302, 754304, 754302(A), 754304(A)
ORDERING INFORMATION
Parts Number
Package
Quality Grade
µPD754302GS-×××
µPD754302GS-×××-A
µPD754304GS-×××
µPD754304GS-×××-A
µPD754302GS(A)-×××
µPD754304GS(A)-×××
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
Standard
Standard
Standard
Standard
Special
Special
Remarks 1. Products with “-A” at the end of the part number are lead-free products.
2. ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications.
Difference between µPD75430× and µPD75430×(A)
Parts Number
µPD754302
µPD754304
µPD754302(A)
µPD754304(A)
Item
Quality grade
Standard
Special
2
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Functional Outline
Parameter
Function
Instruction execution time
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with system clock)
On-chip memory
ROM 2048 × 8 bits (µPD754302)
4096 × 8 bits (µPD754304)
RAM 256 × 4 bits
General-purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
CMOS input
8
On-chip pull-up resistors can be specified by software: 7
CMOS input/output
18 On-chip pull-up resistors can be specified by software: 18
N-ch open-drain
input/output pins
4
13 V withstand voltage. On-chip pull-up resistors can be specified by
mask option.
Total
30
Timer
3 channels
• 8-bit timer/event counter: 2 channels (16-bit timer/event counter)
• Basic interval timer/watchdog timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit
• 2-wire serial I/O mode
Bit sequential buffer
Clock output (PCL)
16 bits
•
•
Φ, 524, 262, 65.5 kHz (@ 4.19 MHz with system clock)
Φ, 750, 375, 93.8 kHz (@ 6.0 MHz with system clock)
Vectored interrupts
Test input
External: 3, Internal: 4
External: 1
System clock oscillator
Standby function
Ceramic or crystal oscillator
STOP/HALT mode
TA = –40 to +85 ˚C
Operating ambient
temperature
Power supply voltage
Package
VDD = 1.8 to 5.5 V
36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)
Data Sheet U10797EJ2V1DS
3
µPD754302, 754304, 754302(A), 754304(A)
CONTENTS
1. PIN CONFIGURATION (Top View) ······································································································6
2. BLOCK DIAGRAM································································································································8
3. PIN FUNCTION ·····································································································································9
3.1 Port Pins ······································································································································9
3.2 Non-port Pins ····························································································································10
3.3 Pin Input/Output Circuits ·········································································································11
3.4 Recommended Connections for Unused Pins ·······································································13
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ················································14
4.1 Difference between Mk I and Mk II Modes ··············································································14
4.2 Setting Method of Stack Bank Select Register (SBS) ···························································15
5. MEMORY CONFIGURATION ·············································································································16
6. PERIPHERAL HARDWARE FUNCTIONS ·························································································20
6.1 Digital Input Ports ·····················································································································20
6.2 Clock Generator ························································································································21
6.3 Clock Output Circuit ·················································································································22
6.4 Basic Interval Timer/Watchdog Timer·····················································································23
6.5 Timer/Event Counter·················································································································24
6.6 Serial Interface ··························································································································27
6.7 Bit Sequential Buffer ················································································································29
7. INTERRUPT FUNCTION AND TEST FUNCTION ··············································································30
8. STANDBY FUNCTION························································································································32
9. RESET FUNCTION ·····························································································································33
10. MASK OPTION ···································································································································36
11. INSTRUCTION SETS··························································································································37
12. ELECTRICAL SPECIFICATIONS·······································································································49
13. CHARACTERISTICS CURVES (REFERENCE VALUES) ·································································61
14. PACKAGE DRAWING ························································································································63
15. RECOMMENDED SOLDERING CONDITIONS··················································································64
4
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
APPENDIX A. COMPARISON OF FUNCTIONS AMONG µPD750004, 754304, AND 75P4308 ···········65
APPENDIX B. DEVELOPMENT TOOLS ·································································································67
APPENDIX C. RELATED DOCUMENTS ·································································································70
Data Sheet U10797EJ2V1DS
5
µPD754302, 754304, 754302(A), 754304(A)
1. PIN CONFIGURATION (Top View)
36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)
µPD754302GS-×××, µPD754302GS-×××-A, µPD754302GS(A)-×××
µPD754304GS-×××, µPD754304GS-×××-A, µPD754304GS(A)-×××
V
SS
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P50
X1
X2
2
P51
3
P52
RESET
P33
4
P53
5
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P13/TI0/TI1
P12/INT2
P11/INT1
P10/INT0
P32
6
P31
7
P30
8
P81
9
P80
10
11
12
13
14
15
16
17
18
P23
P22/PCL
P21/PTO1
P20/PTO0
P03/SI
P02/SO/SB0
P01/SCK
P00/INT4
VDD
IC
IC: Internally Connected (Connect directly this pin to VDD.)
6
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
PIN IDENTIFICATION
P00-P03 : PORT0
P10-P13 : PORT1
P20-P23 : PORT2
P30-P33 : PORT3
P50-P53 : PORT5
P60-P63 : PORT6
P70-P73 : PORT7
P80, P81 : PORT8
KR0-KR7: Key Return 0-7
RESET
TI0, TI1
:
:
Reset Input
Timer Input 0, 1
PTO0, PTO1: Programmable Timer Output 0, 1
PCL
:
:
:
:
:
:
:
Programmable Clock
External Vectored Interrupt 0, 1, 4
External Test Input 2
GND
INT0, 1, 4
INT2
VSS
X1, X2
IC
System Clock Oscillation 1, 2
Internally Connected
Positive Power Supply
SCK
SI
:
:
:
:
Serial Clock
VDD
Serial Input
SO
Serial Output
Serial data Bus 0
SB0
Data Sheet U10797EJ2V1DS
7
BASIC
INTERVAL
TIMER/
BIT SEQ.
BUFFER (16)
WATCHDOG TIMER
INTBT
INTT0
4
4
4
4
4
4
4
2
4
4
4
4
4
4
4
2
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT7
PORT8
P00-P03
P10-P13
P20-P23
P30-P33
P50-P53
P60-P63
P70-P73
P80, P81
TOUT0
SP (8)
SBS
PROGRAM
CY
COUNTER Note1
TI0/TI1/P13
PTO0/P20
8-BIT
ALU
CASCADED
16-BIT
TIMER/
TIMER/EVENT
COUNTER#0
8-BIT
EVENT
COUNTER
BANK
TIMER/EVENT
COUNTER#1
PTO1/P21
INTT1
ROM Note2
PROGRAM
MEMORY
GENERAL REG.
SI/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
DECODE
AND
CONTROL
RAM
DATA
TOUT0
INTCSI
µ
MEMORY
256 × 4 BITS
INT0/P10
INT1/P11
INT2/P12
INT4/P00
INTERRUPT
CONTROL
CPU CLOCK
Φ
KR0-KR3/P60-P63
KR4-KR7/P70-P73
fX/2N
8
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
STAND BY
CONTROL
CLOCK GENERATOR
PCL/P22
X1
X2
IC
VDD VSS RESET
Notes 1. The µPD754302 and µPD754304 program counters are 11 and 12 bits, respectively.
2. The ROM capacity of the µPD754302 is 2048 × 8 bits, and that of the µPD754304 is 4096 × 8 bits.
µPD754302, 754304, 754302(A), 754304(A)
3. PIN FUNCTION
3.1 Port Pins
Alternate
Function
8-bit
I/O
I/O Circuit
TYPE Note 1
Function
Pin Name
P00
Input/Output
After Reset
Input
Input
Input/Output
Input/Output
Input
INT4
SCK
SO/SB0
SI
4-bit input port (PORT0).
×
×
×
×
B
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30
P31
P32
P33
For P01 to P03, on-chip pull-up resistors
can be specified by software in 3-bit units.
F -A
F -B
B -C
B -C
Input
INT0
INT1
INT2
TI0/TI1
PTO0
PTO1
PCL
–
Input
Input
Input
4-bit input port (PORT1).
On-chip pull-up resistors can be specified
by software in 4-bit units.
Noise elimination circuit can be selected
(Only P10/INT0)
Input/Output
Input/Output
4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified
by software in 4-bit units.
E-B
E-B
–
Programmable 4-bit input/output port
(PORT3).
–
This port can be specified for input/output
bit-wise. On-chip pull-up resistor can be
specified by software in 4-bit units.
–
–
Note 2
High level
(when pull-up
resistors are
provided) or
high-
N-ch open-drain 4-bit input/output port
(PORT5).
P50-P53
Input/Output
Input/Output
–
×
√
M-D
F -A
A pull-up resistor can be contained bit-wise
(mask option).
impedance
Withstand voltage is 13 V in open-drain mode.
Programmable 4-bit input/output port
(PORT6).
This port can be specified for input/output
bit-wise.
On-chip pull-up resistors can be specified
by software in 4-bit units.
P60
P61
P62
P63
P70
P71
P72
P73
P80
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
–
Input
Input
Input
Input/Output
Input/Output
F -A
E-B
4-bit input/output port (PORT7).
On-chip pull-up resistors can be specified
by software in 4-bit units.
2-bit input/output port (PORT8).
On-chip pull-up resistors can be specified
by software in 2-bit units.
×
P81
–
Notes 1. Circled characters indicate the Schmitt-trigger input.
2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input
port), low level input leakage current increases when input or bit manipulation instruction is executed.
Data Sheet U10797EJ2V1DS
9
µPD754302, 754304, 754302(A), 754304(A)
3.2 Non-port Pins
Alternate
Function
I/O Circuit
Pin Name
TI0/TI1
Input/Output
Function
After Reset
Input
Note
TYPE
Input
P13
Inputs external event pulses to the timer/event
counter.
B -C
PTO0
PTO1
PCL
Output
P20
P21
P22
P01
P02
Timer/event counter output
Input
Input
E-B
Clock output
SCK
Input/Output
Serial clock input/output
F -A
F -B
SO/SB0
Serial data output
Serial data bus input/output
SI
Input
Input
P03
P00
Serial data input
B -C
B
INT4
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Input
Input
Edge detection vectored
interrupt input (detection
edge can be selected).
INT0/P10 can select a
noise elimination circuit.
Asynchronous with
noise elimination
INT0
Input
P10
B -C
circuit can be selected
Asynchronous
Asynchronous
INT1
INT2
P11
P12
Edge detection testable
input
Input
Input
B -C
(rising edge detection)
KR0-KR3
KR4-KR7
X1
Input
Input
P60-P63
P70-P73
–
Testable input (falling edge detection)
Input
–
F -A
–
Crystal/ceramic connection pin for the system
clock oscillator. When inputting the external
clock, input the external clock to pin X1, and
the inverted phase of the external clock to
pin X2.
X2
–
RESET
IC
Input
–
–
–
–
System reset input (low-level active)
Internally connected. Connect directly to VDD.
Positive power supply
–
–
–
–
B
–
–
–
–
–
–
VDD
VSS
Ground potential
Note Circled characters indicate the Schmitt-trigger input.
10
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
3.3 Pin Input/Output Circuits
The µPD754304 pin input/output circuits are shown schematically.
TYPE A
TYPE D
VDD
VDD
data
P-ch
OUT
P-ch
IN
N-ch
output
disable
N-ch
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
CMOS specification input buffer.
TYPE E-B
TYPE B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
data
IN/OUT
Type D
output
disable
Type A
Schmitt trigger input having hysteresis characteristic.
P.U.R. : Pull-Up Resistor
TYPE F-A
TYPE B-C
VDD
V
DD
P.U.R.
P-ch
P.U.R.
enable
P.U.R.
P.U.R.
enable
P-ch
data
IN/OUT
Type D
output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Data Sheet U10797EJ2V1DS
11
µPD754302, 754304, 754302(A), 754304(A)
TYPE F-B
TYPE M-D
V
DD
V
DD
P.U.R.
(Mask Option)
P.U.R.
IN/OUT
P.U.R.
enable
P-ch
N-ch
(+13 V)
data
output
V
DD
disable
(P)
output
disable
V
DD
P-ch
Input
instruction
IN/OUT
P-ch
data
P.U.R.Note
output
disable
Voltage
limiting
circuit
N-ch
output
disable
(N)
(+13 V)
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Note If this pull-up resistor is not connected using the mask
option it operates only when the input instruction is
executed (if the pin is low, current flows from VDD to the
pin).
12
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin
Recommended Connection
Connect to VSS or VDD
P00/INT4
P01/SCK
Connect to VSS or VDD through the resistor individually
P02/SO/SB0
P03/SI
Connect to VSS
P10/INT0-P12/INT2
P13/TI0/TI1
P20/PTO0
P21/PTO1
P22/PCL
Connect to VSS or VDD
Input state : Connect to VSS or VDD through the resistor
individually
Output state : Leave open
P23
P30-P33
P50-P53
Input state : Connect to VSS
Output state : Connect to VSS (Pull-up resistor by mask
option should not be connected)
Input state : Connect to VSS or VDD through the resistor
individually
P60/KR0-P63/KR3
P70/KR4-P73/KR7
P80, P81
Output state : Leave open
IC
Connect to VDD directly
Data Sheet U10797EJ2V1DS
13
µPD754302, 754304, 754302(A), 754304(A)
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference between Mk I and Mk II Modes
The CPU of µPD754304 has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by the bit 3 of the stack bank select register (SBS).
•
•
Mk I mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.
Mk II mode: Can be used in all the 75XL CPU’s including those products whose ROM capacity is more
than 16K bytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Mk II mode
Number of stack bytes
2 bytes
3 bytes
for subroutine instructions
BRA !addr1 instruction
Not available
Available
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
3 machine cycles
2 machine cycles
4 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area exceeding 16K bytes in the 75X and 75XL
series. This mode can improve software compatibility with products with a program
area of more than 16K bytes.
When Mk II mode is selected, the number of stack bytes when a subroutine call
instruction is executed is greater by 1 byte per stack compared with the Mk I mode.
When the CALL !addr or CALLF !faddr instruction is used, one more machine cycle is
required. To emphasize the efficiency of the RAM and processing speed rather than
software compatibility, therefore, use the Mk I mode.
14
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
3
2
1
0
Address
F84H
Symbol
SBS
SBS3 SBS2 SBS1 SBS0
Stack area specification
0
0
Memory bank 0
Other than above setting prohibited
0 must be set in the bit 2 position.
0
Mode switching specification
0
1
Mk II mode
Mk I mode
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk
I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the
Mk II mode.
Data Sheet U10797EJ2V1DS
15
µPD754302, 754304, 754302(A), 754304(A)
5. MEMORY CONFIGURATION
•
Program Memory (ROM) .... 2048 × 8 bits (µPD754302)
.... 4096 × 8 bits (µPD754304)
•
•
•
Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
Addresses 0002H-000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.
Addresses 0020H-007FH
Table area referenced by the GETI instruction Note
.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
•
Data Memory (RAM)
•
•
Data area .... 256 words × 4 bits (000H-0FFH)
Peripheral hardware area .... 128 words × 4 bits (F80H-FFFH)
16
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Figure 5-1. Program Memory Map (1/2)
(a) µPD754302
Address
7
6
5
0
4
0
0
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
Internal reset start address
Internal reset start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
0
0
0
0
INTBT/INT4
INTBT/INT4
start address
start address
INT0
INT0
start address
start address
CALLF
! faddr
instruction
entry
0 0 0 6 H MBE RBE
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
0
0
0
0
0
0
INT1
start address
start address
start address
start address
start address
start address
start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
address
Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1Note or
CALLA !addr1Note instruction
INT1
INTCSI
INTCSI
INTT0
INTT0
INTT1
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
_
_
15 to 1,
+2 to +16
INTT1
(low-order 8 bits)
start address
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
0 7 F F H
Note Can be used in the Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
Data Sheet U10797EJ2V1DS
17
µPD754302, 754304, 754302(A), 754304(A)
Figure 5-1. Program Memory Map (2/2)
(b) µPD754304
Address
7
6
5
0
4
0
0
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
Internal reset start address
Internal reset start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
0
0
0
0
INTBT/INT4
INTBT/INT4
start address
start address
INT0
INT0
start address
start address
CALLF
! faddr
instruction
entry
0 0 0 6 H MBE RBE
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
0
0
0
0
0
0
INT1
start address
start address
start address
start address
start address
start address
start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
address
Branch address of
BR BCXA, BR BCDE,
INT1
BR !addr, BRA !addr1Note or
CALLA !addr1Note instruction
INTCSI
INTCSI
INTT0
INTT0
INTT1
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
_
_
15 to 1,
+2 to +16
(low-order 8 bits)
INTT1
start address
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 7 F F H
0 8 0 0 H
0 F F F H
Note Can be used in the Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
18
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Figure 5-2. Data Memory Map
Data memory
Memory bank
0 0 0 H
General-purpose
register area
(32
×
4)
0 1 F H
Data area
static RAM
(256 × 4)
0
Stack area
256
×
4
×
(224 4)
0 F F H
F 8 0 H
Not incorporated
×
128
4
15
Peripheral hardware area
F F F H
Data Sheet U10797EJ2V1DS
19
µPD754302, 754304, 754302(A), 754304(A)
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 Digital Input Ports
The following three types of I/O ports are provided.
• CMOS input (Ports 0, 1)
:
8
• CMOS I/O (Ports 2, 3, 6 to 8)
• N-ch open-drain I/O (Port 5)
: 18
:
4
Total
30
Table 6-1. Types and Features of Digital Ports
Port Name
PORT0
Function
Operation, Features
Remark
4-bit input
When serial interface function is used, multiplexed pin
has output function depending on operation mode.
Multiplexed with INT4, SCK,
SO/SB0, and SI pins
PORT1
PORT2
Input port.
Multiplexed with INT0
through INT2 and TI0/TI1 pins.
4-bit I/O
Can be set in input or output mode in 4-bit units.
Can be set in input or output mode in 1-bit units.
Multiplexed with PTO0, PTO1,
and PCL pins.
PORT3
PORT5
—
4-bit I/O
Can be set in input or output mode in 4-bit units. Pull-up
resistor can be connected in 1-bit units by mask option.
(N-ch open-
drain, 13 V)
PORT6
PORT7
PORT8
4-bit I/O
Can be set in input or
Ports 6 and 7 are used in
pairs and can input or
Multiplexed with KR0 through
KR3 pins.
output mode in 1-bit units.
output data in 8-bit units.
Can be set in input or
Multiplexed with KR4 through
KR7 pins.
output mode in 4-bit units.
2-bit I/O
Can be set in input or output mode in 2-bit units.
—
20
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
6.2 Clock Generator
•
Clock generator configuration
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration
is shown in Figure 6-1.
The operation of the clock generator is set with the processor clock control register (PCC).
The instruction execution time can be changed.
• 0.95, 1.91, 3.81, 15.3 µs (system clock operating at 4.19 MHz)
• 0.67, 1.33, 2.67, 10.7 µs (system clock operating at 6.0 MHz)
Figure 6-1. Clock Generator Block Diagram
· Basic interval timer (BT)
· Timer/event counters 0, 1
· Serial interface
· INT0 noise eliminator
· Clock output circuit
X1
1/1 to 1/4096
fX
System
clock oscillator
Divider
X2
1/2 1/4 1/16
Oscillation
stop
Divider
1/4
Φ
· CPU
Selector
· INT0 noise eliminator
· Clock output circuit
PCC
PCC0
PCC1
4
HALT F/F
PCC2
PCC3
S
HALTNote
STOPNote
R
Q
PCC2,
PCC3
Clear
STOP F/F
Wait signal from BT
RESET signal
S
Q
R
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks 1. fX = System clock frequency
2. Φ = CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
Data Sheet U10797EJ2V1DS
21
µPD754302, 754304, 754302(A), 754304(A)
6.3 Clock Output Circuit
The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to apply for remote controller
waveform output or to supply clock pulse peripheral LSIs.
• Clock output (PCL) : Φ, 524, 262, 65.5 kHz (during 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (during 6.0-MHz operation)
Figure 6-2. Clock Output Circuit Block Diagram
From clock
generator
Φ
/23
/24
Output buffer
f
X
Selector
fX
PCL/P22
fX
/26
PORT2.2
Bit 2 of PMGB
P22
output latch
Port 2 I/O mode
specification bit
CLOM3
0
CLOM1 CLOM0 CLOM
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output
when switching clock output enable/disable.
22
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
6.4 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
• Interval timer operation to generate a reference time interrupt
• Watchdog timer operation to detect a runaway of program and reset the CPU
• Selects and counts the wait time when the standby mode is released
• Reads the contents of counting
Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
Clear
Clear
fX/25
fX/27
fX/29
BT
interrupt
request flag
Basic interval timer
(8-bit frequency divider)
Set
MPX
Vectored
interrupt
IRQBT request signal
BT
fX/212
3
Wait release signal
when standby is
released.
Internal reset
signal
WDTM
1
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1 Note
8
SET1 Note
Internal bus
Note Instruction execution
Data Sheet U10797EJ2V1DS
23
µPD754302, 754304, 754302(A), 754304(A)
6.5 Timer/Event Counter
The µPD754304 has two channels of timer/event counters. Its configuration is shown in Figures
6-4 and 6-5.
The timer/event counter has the following functions.
• Programmable interval timer operation
• Square wave output of any frequency to the PTOn pin (n = 0, 1)
• Event counter operation
• Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided
frequency to the PTOn pin (frequency divider operation).
• Supplies the shift clock to the serial interface circuit.
• Reads the count value.
The timer/event counter operates in the following two modes as set by the mode register.
Table 6-2. Operation Modes of Timer/Event Counter
Channel
Channel 0 Channel 1
Mode
8-bit timer/event counter mode
16-bit timer/event counter mode
√
√
√
24
Data Sheet U10797EJ2V1DS
Figure 6-4. Timer/Event Counter (Channel 0) Block Diagram
Internal bus
8
TM0
TOE0
PORT 2.0 Bit 2 of PMGB
8
TM06 TM05 TM04 TM03 TM02 TM01 TM00
T0
P20
output latch
Port 2
I/O mode
PORT1.3
TMOD0
enable flag
Decoder
Modulo register (8)
P20/PTO0
8
Match
TOUT
F/F
Output buffer
Comparator (8)
Input buffer
To serial interface
TI0/TI1/P13
Reset
8
/22
/24
T0
f
X
Timer/event counter
(channel 1) clock input
Overflow
fX
Count register (8)
Clear
µ
From clock
generator
MPX
/26
/28
CP
fX
f
X
f
X
/210
INTT0
IRQT0
set signal
16-bit timer/event counter mode
IRQT0 clear signal
Timer operation start
RESET
Timer/event counter
(channel 1) TM12 signal
(When 16-bit timer/event
counter mode)
Timer/event counter
(channel 1) match signal
(When 16-bit timer/event
counter mode)
Timer/event counter
(channel 1) clear signal
(When 16-bit timer/event
counter mode)
Figure 6-5. Timer/Event Counter (Channel 1) Block Diagram
Internal bus
8
TOE1
PORT2.1
Bit 2 of PMGB
TM1
Port 2
input/output
mode
8
T1
enable flag
P21
output latch
—
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Decoder
TMOD1
Modulo register (8)
PORT1.3
8
Match
P21/PTO1
TOUT
F/F
Comparator (8)
8
Input buffer
Output buffer
TI0/TI1/P13
Reset
T1
Timer/event counter (channel 0) output
/22
f
X
Count register (8)
Clear
MPX
CP
f
X
/26
µ
From clock
generator
fX
/28
/210
/212
f
X
f
X
RESET
Timer operation start
IRQT1 clear signal
16 bit timer/event counter mode
Selector
Timer/event counter (channel 0) TM02 signal
(When 16 bit timer/event counter mode)
INTT1
IRQT1
set signal
Timer/event counter (channel 0)
match signal/operation start
(When 16-bit timer/event counter mode)
Timer/event counter (channel 0) comparator
(When 16-bit timer/event counter mode)
µPD754302, 754304, 754302(A), 754304(A)
6.6 Serial Interface
The µPD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
Data Sheet U10797EJ2V1DS
27
Figure 6-6. Serial Interface Block Diagram
Internal bus
8/4
Bit test
Bit manipulation
8
8
8
SBIC
CSIM
Slave address register (SVA)
(8)
Matching
signal
(8)
RELT
CMDT
Address comparator
P03/SI
SO latch
SET CLR
Selector
D
Q
Shift register (SIO)
(8)
µ
P02/SO/SB0
INTCSI
IRQCSI
set signal
P01/SCK
INTCSI
control circuit
Serial clock counter
f
f
f
X
X
X
/23
P01
output Iatch
/24
/26
Serial clock control
circuit
Serial clock
selector
TOUT F/F
(from timer/event counter 0)
External SCK
µPD754302, 754304, 754302(A), 754304(A)
6.7 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing a long data bit-wise.
The data memory is composed of 16 bits and the pmem.@L addressing of a bit manipulation instruction is
possible. The bit can be specified indirectly by the L register. In this case, processing can be done by moving the
specified bit in sequence by incrementing and decrementing the L register in the program loop.
Figure 6-7. Bit Sequential Buffer Format
Address
Bit
FC3H
FC2H
FC1H
FC0H
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Symbol
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H L = 7H
L = 4H L = 3H
DECS L
L = 0H
INCS L
Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register.
2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.
Data Sheet U10797EJ2V1DS
29
µPD754302, 754304, 754302(A), 754304(A)
7. INTERRUPT FUNCTION AND TEST FUNCTION
The µPD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection
testable inputs are provided for INT2 of the test source.
The interrupt control circuit of the µPD754304 has the following functions.
(1) Interrupt function
•
Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IE×××) and interrupt master enable flag (IME).
Can set any interrupt start address.
•
•
Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).
•
•
Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.
Release the standby mode. A release interrupt can be selected by the interrupt enable flag.
(2) Test function
•
•
Test request flag (IRQxxx) generation can be checked by software.
Release the standby mode. The test source to be released can be selected by the test enable flag.
30
Data Sheet U10797EJ2V1DS
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus
2
1
4
IME IPS
IST1
IST0
Interrupt enable flag (IE
)
×××
IM2
IM1
IM0
Decoder
IRQBT
IRQ4
INTBT
VRQn
Both edge
detector
INT4/P00
INT0/P10
Edge
detector
Selec-
tor
Note
IRQ0
µ
Edge
detector
IRQ1
INT1/P11
Vector table
address
generator
Priority control
circuit
INTCSI
INTT0
INTT1
IRQCSI
IRQT0
IRQT1
Rising edge
detector
INT2/P12
Selec-
tor
IRQ2
KR0/P60
KR7/P73
Falling edge
detector
Standby release
signal
IM2
Note Noise eliminator (Standby release is disabled when noise eliminator is selected.)
µPD754302, 754304, 754302(A), 754304(A)
8. STANDBY FUNCTION
In order to save dissipation power while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the µPD754304.
Table 8-1. Operation Status in Standby Mode
Mode
Item
STOP mode
STOP instruction
HALT mode
HALT instruction
Set instruction
Operation Clock generator
status
The system clock stops oscillation.
Only the CPU clock Φ halts (oscillation
continues).
Basic interval timer/
Watchdog timer
Operation stops.
Operable (The IRQBT is set in the
reference interval).
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable
Timer/event counter
Operable only when a signal input to
the TI0 and TI1 pins are specified as
the count clock.
Operable
External interrupt
The INT1, 2, and 4 are operable.
Note
Only the INT0 is not operated
.
CPU
The operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag or RESET signal input.
Note Operable only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register
(IM0).
32
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
9. RESET FUNCTION
There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/
watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure
9-1 shows the circuit diagram of the above two inputs.
Figure 9-1. Configuration of Reset Function
RESET
Internal RESET signal
RESET signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing
chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET
signal
generated
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Note The following two times can be selected by the mask option.
217/fX (21.8 ms : @ 6.0 MHz, 31.3 ms: @ 4.19 MHz)
215/fX (5.46 ms : @ 6.0 MHz, 7.81 ms: @ 4.19 MHz)
Data Sheet U10797EJ2V1DS
33
µPD754302, 754304, 754302(A), 754304(A)
Table 9-1. Status of Each Hardware After Reset (1/2)
RESET signal generation
RESET signal generation
in operation
Hardware
Program counter (PC)
in the standby mode
µPD754302 Sets the low-order 3 bits of
Sets the low-order 3 bits of
program memory’s address
program memory’s address
0000H to the PC10-PC8 and the 0000H to the PC10-PC8 and the
contents of address 0001H to
the PC7-PC0.
contents of address 0001H to
the PC7-PC0.
µPD754304 Sets the low-order 4 bits of
Sets the low-order 4 bits of
program memory's address
program memory's address
0000H to the PC11-PC8 and the 0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
contents of address 0001H to
the PC7-PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
0
0
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
Data memory (RAM)
1000B
1000B
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Bank select register (MBS, RBS)
Held
Undefined
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog Mode register (BTM)
0
0
0
timer
Watchdog timer enable flag (WDTM)
0
Timer/event
counter (T0)
Counter (T0)
0
0
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
FFH
0
FFH
0
0, 0
0
0, 0
Timer/event
counter (T1)
Counter (T1)
0
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT F/F
FFH
0
FFH
0
0, 0
Held
0
0, 0
Serial
Shift register (SIO)
Undefined
interface
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
0
0
0
Held
0
Undefined
Clock generator, Processor clock control register (PCC)
0
0
clock output
circuit
Clock output mode register (CLOM)
0
34
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Table 9-1. Status of Each Hardware After Reset (2/2)
RESET signal generation
RESET signal generation
in operation
Hardware
in the standby mode
Interrupt
function
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Interrupt priority select register (IPS)
INT0, 1, 2 mode registers (IM0, IM1, IM2)
Output buffer
Reset (0)
Reset (0)
0
0
0
0
0, 0, 0
0, 0, 0
Digital port
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, B, C)
Pull-up resistor setting registers (POGA, B)
0
0
0
0
Bit sequential buffers (BSB0-BSB3)
Held
Undefined
Data Sheet U10797EJ2V1DS
35
µPD754302, 754304, 754302(A), 754304(A)
10. MASK OPTION
The µPD754304 has the following mask options:
•
Mask option of P50 through P53
Pull-up resistors can be connected to these pins.
(1) Specify connection of a pull-up resistor in 1-bit units.
(2) Do not specify connection of a pull-up resistor.
•
Standby function mask option
The wait time when the RESET signal is input can be selected.
(1) 217/fX (21.8 ms: fX = 6.0 MHz, 31.3 ms: fX = 4.19 MHz)
(2) 215/fX (5.46 ms: fX = 6.0 MHz, 7.81 ms: fX = 4.19 MHz)
36
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
11. INSTRUCTION SETS
(1) Expression formats and description methods of operands
The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to RA75X ASSEMBLER
PACKAGE USERS’ MANUAL——LANGUAGE (EEU-1363). If there are several elements, one of them
is selected. Capital letters and the + and – symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be
described. However, there are restrictions in the labels that can be described for fmem and pmem.
For details, refer to the µPD754304 USER’S MANUAL (U10123E).
Representation
Description method
format
reg
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
reg1
rp
XA, BC, DE, HL
rp1
rp2
rp'
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rp'1
rpa
HL, HL+, HL–, DE, DL
DE, DL
rpa1
n4
n8
4-bit immediate data or label
8-bit immediate data or label
Note
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
pmem
addr
0000H-07FFH immediate data or label (µPD754302)
0000H-0FFFH immediate data or label (µPD754304)
0000H-07FFH immediate data or label (µPD754302)
0000H-0FFFH immediate data or label (µPD754304)
12-bit immediate data or label
addr1
caddr
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit 0 = 0) or label
PORTn
IE×××
RBn
PORT0-PORT3, PORT5-PORT8
IEBT, IET0, IET1, IE0-IE2, IE4, IECSI
RB0-RB3
MBn
MB0, MB15
Note mem can be only used for even address in 8-bit data processing.
Data Sheet U10797EJ2V1DS
37
µPD754302, 754304, 754302(A), 754304(A)
(2) Legend in explanation of operation
A
: A register; 4-bit accumulator
: B register
B
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
BC
DE
HL
XA’
BC’
DE’
HL’
PC
SP
CY
PSW
MBE
RBE
: XA register pair; 8-bit accumulator
: BC register pair
: DE register pair
: HL register pair
: XA’ expanded register pair
: BC’ expanded register pair
: DE’ expanded register pair
: HL’ expanded register pair
: Program counter
: Stack pointer
: Carry flag; bit accumulator
: Program status word
: Memory bank enable flag
: Register bank enable flag
PORTn : Port n (n = 0-3, 5-8)
IME
IPS
: Interrupt master enable flag
: Interrupt priority select register
: Interrupt enable flag
IExxx
RBS
MBS
PCC
.
: Register bank select register
: Memory bank select register
: Processor clock control register
: Separation between address and bit
: The contents addressed by ××
: Hexadecimal data
(××)
××H
38
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
(3) Explanation of symbols under addressing area column
*1
MB = MBE•MBS
(MBS = 0, 15)
*2
*3
MB = 0
MBE = 0 : MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
Data memory addressing
MBE = 1 : MB = MBS (MBS = 0, 15)
*4
*5
*6
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
MB = 15, pmem = FC0H-FFFH
µPD754302
µPD754304
addr = 0000H-07FFH
addr = 0000H-0FFFH
*7
*8
addr = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
µPD754302
µPD754304
caddr = 0000H-07FFH
Program memory addressing
caddr = 0000H-0FFFH (PC12 = 0)
*9
faddr = 0000H-07FFH
taddr = 0020H-007FH
*10
*11
µPD754302
µPD754304
addr1 = 0000H-07FFH
addr1 = 0000H-0FFFH
Remarks 1. MB indicates memory bank that can be accessed.
2. In *2, MB = 0 independently of how MBE and MBS are set.
3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4. *6 to *11 indicate the areas that can be addressed.
(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.
• When no skip is made: S = 0
• When the skipped instruction is a 1- or 2-byte instruction: S = 1
• When the skipped instruction is a 3-byte instruction Note: S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types
by setting PCC.
Data Sheet U10797EJ2V1DS
39
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
area
Mnemonic
MOV
Operand
Operation
Skip condition
String effect A
Transfer
A, #n4
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
2
A ← n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL–
A, @rpa
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg1
reg1 ← n4
XA ← n8
HL ← n8
rp2 ← n8
A ← (HL)
2
String effect A
String effect B
2
2
1
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
2+S
2+S
1
A ← (HL), then L ← L+1
A ← (HL), then L ← L–1
A ← (rpa)
L = 0
L = FH
2
XA ← (HL)
1
(HL) ← A
2
(HL) ← XA
2
A ← (mem)
2
XA ← (mem)
(mem) ← A
2
2
(mem) ← XA
A ← reg1
2
XA, rp'
2
XA ← rp'
reg1, A
2
reg1 ← A
rp'1, XA
A, @HL
A, @HL+
A, @HL–
A, @rpa
XA, @HL
A, mem
XA, mem
A, reg1
2
rp'1 ← XA
XCH
1
A ↔ (HL)
*1
*1
*1
*2
*1
*3
*3
2+S
2+S
1
A ↔ (HL), then L ← L+1
A ↔ (HL), then L ← L–1
A ↔ (rpa)
L = 0
L = FH
2
XA ↔ (HL)
2
A ↔ (mem)
2
XA ↔ (mem)
A ↔ reg1
1
XA, rp'
2
XA ↔ rp'
Table
MOVT
XA, @PCDE
3
● µPD754302
reference
XA ← (PC10–8+DE)ROM
● µPD754304
XA ← (PC11–8+DE)ROM
XA, @PCXA
1
3
● µPD754302
XA ← (PC10–8+XA)ROM
● µPD754304
XA ← (PC11–8+XA)ROM
Note
XA, @BCDE
XA, @BCXA
1
1
3
3
XA ← (BCDE)ROM
*6
*6
Note
XA ← (BCXA)ROM
Note To use the µPD754302, clear the most significant bit of the register C and register B to “0”. To use
the µPD754304, clear the register B to “0”.
40
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
Addressing
area
Mnemonic
MOV1
Operand
Operation
Skip condition
of bytes
Bit transfer
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
2
2
CY ← (fmem.bit)
*4
*5
*1
*4
*5
*1
CY ← (pmem7–2+L3–2.bit(L1–0))
CY ← (H+mem3–0.bit)
(fmem.bit) ← CY
(pmem7–2+L3–2.bit(L1–0)) ← CY
(H+mem3–0.bit) ← CY
A ← A+n4
2
2
2
2
Operation
ADDS
1+S
2+S
1+S
2+S
2+S
1
carry
carry
carry
carry
carry
XA, #n8
A, @HL
XA, rp'
XA ← XA+n8
A ← A+(HL)
*1
*1
*1
*1
XA ← XA+rp'
rp'1, XA
A, @HL
XA, rp'
rp'1 ← rp'1+XA
ADDC
SUBS
SUBC
AND
A, CY ← A+(HL)+CY
XA, CY ← XA+rp'+CY
rp'1, CY ← rp'1+XA+CY
A ← A–(HL)
2
rp'1, XA
A, @HL
XA, rp'
2
1+S
2+S
2+S
1
borrow
borrow
borrow
XA ← XA–rp'
rp'1, XA
A, @HL
XA, rp'
rp'1 ← rp'1–XA
A, CY ← A–(HL)–CY
XA, CY ← XA–rp'–CY
rp'1, CY ← rp'1–XA–CY
A ← A ∧ n4
2
rp'1, XA
A, #n4
2
2
A, @HL
XA, rp'
1
A ← A ∧ (HL)
*1
*1
*1
2
XA ← XA ∧ rp'
rp'1, XA
A, #n4
2
rp'1 ← rp'1 ∧ XA
A ← A ∨ n4
OR
2
A, @HL
XA, rp'
1
A ← A ∨ (HL)
2
XA ← XA ∨ rp'
rp'1, XA
A, #n4
2
rp'1 ← rp'1 ∨ XA
A ← A v n4
XOR
2
A, @HL
XA, rp'
1
A ← A v (HL)
2
XA ← XA v rp'
rp'1, XA
A
2
rp'1 ← rp'1 v XA
Accumulator RORC
1
CY ← A
A ← A
0
, A3
← CY, An–1 ← A
n
manipulation
NOT
A
2
Increment
and
INCS
reg
1+S
1+S
2+S
2+S
1+S
2+S
reg ← reg+1
rp1 ← rp1+1
reg=0
rp1
rp1=00H
(HL)=0
decrement
@HL
(HL) ← (HL)+1
(mem) ← (mem)+1
reg ← reg–1
*1
*3
mem
(mem)=0
reg=FH
rp'=FFH
DECS
reg
rp'
rp' ← rp'–1
Data Sheet U10797EJ2V1DS
41
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
area
Mnemonic
Operand
Operation
Skip condition
Comparison SKE
reg, #n4
2
2
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2+S
2+S
1+S
2+S
2+S
2+S
1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY ← 1
reg=n4
@HL, #n4
A, @HL
*1
*1
*1
(HL) = n4
A = (HL)
XA = (HL)
A=reg
XA, @HL
A, reg
XA, rp'
XA=rp'
Carry flag
SET1
CLR1
SKT
CY
manipulation
CY
1
CY ← 0
CY
1+S
1
Skip if CY = 1
CY ← CY
CY=1
NOT1
SET1
CY
Memory bit
mem.bit
2
(mem.bit) ← 1
(fmem.bit) ← 1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
manipulation
fmem.bit
2
pmem.@L
@H+mem.bit
mem.bit
2
(pmem7–2+L3–2.bit(L1–0)) ← 1
(H+mem3–0.bit) ← 1
2
CLR1
2
(mem.bit) ← 0
fmem.bit
2
(fmem.bit) ← 0
pmem.@L
@H+mem.bit
mem.bit
2
(pmem7–2+L3–2.bit(L1–0)) ← 0
(H+mem3–0.bit) ← 0
2
SKT
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2
Skip if (mem.bit)=1
(mem.bit)=1
fmem.bit
Skip if (fmem.bit)=1
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
(mem.bit)=0
pmem.@L
@H+mem.bit
mem.bit
Skip if (pmem7–2+L3–2.bit(L1–0))=1
Skip if (H+mem3–0.bit)=1
Skip if (mem.bit)=0
SKF
fmem.bit
Skip if (fmem.bit)=0
(fmem.bit)=0
(pmem.@L)=0
(@H+mem.bit)=0
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
pmem.@L
@H+mem.bit
fmem.bit
Skip if (pmem7–2+L3–2.bit(L1–0))=0
Skip if (H+mem3–0.bit)=0
Skip if (fmem.bit)=1 and clear
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
Skip if (H+mem3–0.bit)=1 and clear
CY ← CY ∧ (fmem.bit)
SKTCLR
AND1
OR1
pmem.@L
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
2
CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0))
CY ← CY ∧ (H+mem3–0.bit)
CY ← CY ∨ (fmem.bit)
2
2
2
CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0))
CY ← CY ∨ (H+mem3–0.bit)
CY ← CY v (fmem.bit)
2
XOR1
2
2
CY ← CY v (pmem7–2+L3–2.bit(L1–0))
CY ← CY v (H+mem3–0.bit)
2
42
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
Addressing
area
Mnemonic
BR Note
Operand
Operation
Skip condition
of bytes
Branch
addr
–
–
µPD754302
*6
•
PC10–0 ← addr
Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler being
used.
µPD754304
•
PC11–0 ← addr
Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler being
used.
addr1
–
–
µPD754302
*11
•
PC10-0 ← addr
Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.
µPD754304
•
PC11–0 ← addr1
Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.
!addr
3
1
1
2
2
3
2
2
3
3
µPD754302
*6
*7
•
PC10–0 ← addr
µPD754304
•
PC11–0 ← addr
$addr
$addr1
PCDE
PCXA
µPD754302
•
PC10–0 ← addr
µPD754304
•
PC11–0 ← addr
µPD754302
•
PC10–0 ← addr1
µPD754304
•
PC11–0 ← addr1
µPD754302
•
PC10–0 ← PC10-8+DE
µPD754304
•
PC11–0 ← PC11-8+DE
µPD754302
•
PC10–0 ← PC10-8+XA
µPD754304
•
PC11–0 ← PC11-8+XA
Note The above operations in the double boxes can be performed only in the Mk II mode.
Data Sheet U10797EJ2V1DS
43
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
area
Mnemonic
BR
Operand
Operation
Skip condition
Branch
BCDE
2
2
3
2
3
3
3
3
2
3
µPD754302
*6
*6
•
PC10–0 ← BCDE Note1
µPD754304
•
PC11–0 ← BCDE Note2
BCXA
!addr1
!caddr
µPD754302
•
PC10–0 ← BCXA Note1
µPD754304
•
PC11–0 ← BCXA Note2
BRA Note3
µPD754302
*11
*8
•
PC10–0 ← addr1
µPD754304
•
PC11–0 ← addr1
BRCB
µPD754302
•
PC10–0 ← caddr10–0
µPD754304
•
PC11–0 ← caddr11–0
Subroutine
CALLANote3 !addr1
µPD754302
*11
•
stack control
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC10–0
(SP–5) ← 0, 0, 0, 0
PC10–0 ← addr1, SP ← SP–6
µPD754304
•
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr1, SP ← SP–6
CALL Note3 !addr
3
3
µPD754302
*6
•
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC10–0
PC10–0 ← addr, SP ← SP–4
µPD754304
•
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← addr, SP ← SP–4
4
µPD754302
•
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC10–0
(SP–5) ← 0, 0, 0, 0
PC10–0 ← addr, SP ← SP–6
µPD754304
•
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr, SP ← SP–6
Notes 1. “0” must be set to the most significant bit of the register C and register B.
2. “0” must be set to register B.
3. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
44
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
Addressing
area
Mnemonic
Operand
Operation
Skip condition
of bytes
Subroutine
CALLF Note !faddr
2
2
µPD754302
*9
•
stack control
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC10–0
PC10–0 ← faddr, SP ← SP–4
µPD754304
•
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← 0+faddr, SP ← SP–4
3
µPD754302
•
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC10–0
(SP–5) ← 0, 0, 0, 0
PC10–0 ← faddr, SP ← SP–6
µPD754304
•
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← 0+faddr, SP ← SP–6
RET Note
1
3
µPD754302
•
PC10–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4
µPD754304
•
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4
µPD754302
•
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0, ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
µPD754304
•
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0 ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
RETS Note
1
3+S
µPD754302
Unconditional
•
MBE, RBE, 0, 0 ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
µPD754304
•
MBE, RBE, 0, 0← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
Data Sheet U10797EJ2V1DS
45
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
area
Mnemonic
RETS Note1
Operand
Operation
Skip condition
Unconditional
Subroutine
1
3+S
µPD754302
•
stack control
0, 0, 0, 0 ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
µPD754304
•
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
RETI Note1
1
3
µPD754302
•
MBE, RBE, 0, 0 ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
µPD754304
•
MBE, RBE, 0, 0← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
µPD754302
•
0, 0, 0, 0 ← (SP+1)
PC10–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
µPD754304
•
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
PUSH
POP
rp
1
2
1
2
2
2
2
2
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
(SP–1)(SP–2) ← rp, SP ← SP–2
(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2
rp ← (SP+1) (SP), SP ← SP+2
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
IME (IPS.3) ← 1
BS
rp
BS
Interrupt
control
EI
IE×××
IE××× ← 1
DI
IME (IPS.3) ← 0
IE×××
IE××× ← 0
Input/output
IN Note2
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
A ← PORTn
(n = 0-3, 5-8)
(n = 6)
XA ← PORTn+1, PORTn
PORTn ← A
OUT Note2
(n = 2, 3, 5-8)
(n = 6)
PORTn+1, PORTn ← XA
Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and
MBS must be set to 15.
46
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
Addressing
area
Mnemonic
Operand
Operation
Skip condition
of bytes
CPU control HALT
2
2
1
2
2
1
2
2
1
2
2
3
Set HALT Mode (PCC.2 ← 1)
Set STOP Mode (PCC.3 ← 1)
No Operation
STOP
NOP
Special
SEL
RBn
MBn
RBS ← n
(n = 0-3)
MBS ← n
(n = 0, 15)
GETI Notes 1, 2 taddr
µPD754302
*10
•
• When TBR instruction
PC10–0 ← (taddr)2–0 + (taddr+1)
– – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC10–0
(SP–3) ← MBE, RBE, 0, 0
PC10–0 ← (taddr)2–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When instruction other than TBR and
TCALL instructions
Depending on
the reference
instruction
(taddr) (taddr+1) instruction is executed.
µPD754304
•
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP–3) ← MBE, RBE, 0, 0
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When instruction other than TBR and
TCALL instructions
Depending on
the reference
instruction
(taddr) (taddr+1) instruction is executed.
3
µPD754302
*10
•
• When TBR instruction
PC10–0 ← (taddr)2–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC10–0
(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC10–0 ← (taddr)2–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
3
• When instruction other than TBR and
TCALL instructions
Depending on
the reference
instruction
(taddr) (taddr+1) instruction is executed.
Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
Data Sheet U10797EJ2V1DS
47
µPD754302, 754304, 754302(A), 754304(A)
Number
of machine
cycles
Instruction
group
Number
of bytes
Addressing
area
Mnemonic
Operand
Operation
Skip condition
Special
GETI Notes 1, 2 taddr
1
3
µPD754304
*10
•
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
3
• When instruction other than TBR and
TCALL instructions
Depending on
the reference
instruction
(taddr) (taddr+1) instruction is executed.
Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode.
48
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Input voltage
Symbol
VDD
Test Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +14
–0.3 to VDD + 0.3
–10
Unit
V
VI1
Except port 5
Port 5
V
VI2
Pull-up resistor incorporated
N-ch open-drain
V
V
Output voltage
VO
IOH
V
Output current, high
Per pin
mA
mA
mA
mA
°C
For all pins
Per pin
–30
Note
Output current, low
IOL
30
For all pins
220
Operating ambient
temperature
TA
–40 to +85
Storage temperature
Tstg
–65 to +150
°C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the products. Be sure to use the products within the ratings.
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CIN
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V
COUT
CIO
15
pF
15
pF
Data Sheet U10797EJ2V1DS
49
µPD754302, 754304, 754302(A), 754304(A)
System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Constant
Parameter
Oscillation
Testing Conditions
MIN.
1.0
TYP. MAX.
Unit
Ceramic
resonator
6.0Note2 MHz
Note1
frequency (fX)
X1
X2
Oscillation
After VDD reaches MIN.
value of oscillation
voltage range
4
ms
C1
C2
stabilization
Note 3
time
Crystal
Oscillation
1.0
6.0Note2 MHz
Note1
resonator
frequency(fX)
X1
X2
Oscillation
stabilization time Note3
VDD = 4.5 to 5.5 V
10
30
ms
ms
C1
C2
External
clock
X1 input
1.0
6.0Note2 MHz
Note1
frequency (fX)
X1
X2
X1 input high- and
low-level widths
(tXH, tXL)
83.3
500
ns
Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Charac-
teristics.
2. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, set the processor control
register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated cycle time of 0.95 µs
is not satisfied.
3. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD,
or after the STOP mode has been released.
Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted
lines in the figures as follows to avoid adverse influences on the wiring capacitance:
• Keep the wire length as short as possible.
• Do not cross other signal lines.
• Do not route the wiring in the vicinity of lines though which a high fluctuating current flows.
• Always keep the ground point of the capacitor of the oscillation circuit as the same potential
as VSS.
• Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
50
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Recommended Oscillation Circuit Constants
Ceramic Resonator (TA = –40 to +85 °C)
Manufacturer
Product
Frequency Recommended Circuit Constants (pF) Oscillation Voltage Range (VDD
)
Remarks
(MHz)
1.0
C1
100
30
–
C2
100
30
–
MIN.
2.7
MAX.
5.5
Note
Murata
CSB1000J
Rd = 5.6 kΩ
Mfg. Co., Ltd CSA2.00MG
CST2.00MG
2.0
1.8
5.5
Capacitor incorporated
Capacitor incorporated
Capacitor incorporated
Capacitor incorporated
Capacitor incorporated
Capacitor incorporated
CSA3.58MG
3.58
4.0
30
–
30
–
1.8
5.5
5.5
5.5
CST3.58MGW
CSA3.58MGU
CST3.58MGWU
CSA4.00MG
30
–
30
–
30
–
30
–
2.0
1.8
2.9
1.8
CST4.00MGW
CSA4.00MGU
CST4.00MGWU
CSA6.00MG
30
–
30
–
6.0
30
–
30
–
CST6.00MGW
CSA6.00MGU
CST6.00MGWU
Kyocera Corp. KBR-1000F/Y
KBR-2.0MS
30
–
30
–
Capacitor incorporated
1.0
2.0
4.0
100
47
33
–
100
47
33
–
1.8
2.0
1.8
5.5
5.5
5.5
TA = –20 to +80 °C
KBR-4.0MSA
KBR-4.0MKS
Capacitor incorporated, T
A
= –20 to +80 °C
PBRC 4.00A
33
–
33
–
TA = –20 to +80 °C
PBRC 4.00B
Capacitor incorporated, T
A
= –20 to +80 °C
KBR-6.0MSA
6.0
33
33
1.8
1.8
5.5
5.5
TA = –20 to +80 °C
PBRC 6.00A
PBRC 6.00B
–
100
–
–
100
–
Capacitor incorporated, T
A
= –20 to +80 °C
TDK
CCR1000K2
CCR2.0MC33
CCR4.19MC3
FCR4.19MC5
CCR6.0MC3
1.0
2.0
Capacitor incorporated
4.19
6.0
Data Sheet U10797EJ2V1DS
51
µPD754302, 754304, 754302(A), 754304(A)
Note If using Murata’s CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 5.6 kΩ) is required
(see figure below). If using any other recommended resonator, no limited resistor is needed.
X1
X2
CSB1000J
Rd
C2
C1
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accu-
racy is required for actual circuits, it is necessary to adjust the oscillation frequency of the
resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed.
52
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
DC Characteristics (TA = –40 to + 85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
mA
mA
V
Output current, low
IOL
Per pin
For all pins
Ports 2, 3, 8
150
VDD
VDD
VDD
Input voltage, high
VIH1
VIH2
VIH3
2.7 V≤VDD≤5.5 V 0.7 VDD
1.8 V≤VDD<2.7 V 0.9 VDD
2.7 V≤VDD≤5.5 V 0.8 VDD
1.8 V≤VDD<2.7 V 0.9 VDD
2.7 V≤VDD≤5.5 V 0.7 VDD
1.8 V≤VDD<2.7 V 0.9 VDD
V
Ports 0, 1, 6, 7, RESET
V
V
V
V
DD
DD
DD
V
Port 5
Pull-up resistor
incorporated
V
V
N-ch open drain 2.7 V≤VDD≤5.5 V 0.7 VDD
1.8 V≤VDD<2.7 V 0.9 VDD
VDD–0.1
13
V
13
V
VIH4
VIL1
X1
VDD
V
Input voltage, low
Ports 2, 3, 5, 8
2.7 V≤VDD≤5.5 V
1.8 V≤VDD<2.7 V
2.7 V≤VDD≤5.5 V
1.8 V≤VDD<2.7 V
0
0.3 VDD
0.1 VDD
0.2 VDD
0.1 VDD
0.1
V
0
V
VIL2
Ports 0, 1, 6, 7, RESET
0
V
0
0
V
VIL3
VOH
VOL1
X1
V
Output voltage, high
Output voltage, low
SCK, SO, ports 2, 3, 6, 7, 8 IOH = –1 mA
SCK, SO, ports 2, 3, 5, 6, 7, 8 IOL = 15 mA
VDD = 5 V 10%
VDD–0.5
V
0.2
2.0
V
IOL = 1.6 mA
0.4
0.2 VDD
3
V
VOL2
SB0
N-ch open-drain pull-up resistor≥1 kΩ
Pins other than X1
X1
V
Input leak current, high
I
LIH1
V
I
= VDD
µA
µA
µA
µA
µA
µA
ILIH2
ILIH3
20
VI = 13 V
VI = 0 V
Port 5 (N-ch open drain)
Pins other than X1 and port 5
X1
20
Input leak current, low ILIL1
–3
ILIL2
ILIL3
–20
–3
Port 5 (N-ch open drain)
Other than input instruction
execution time
–30
–27
–8
µA
µA
µA
µA
Port 5 (N-ch
open drain)
VDD = 5.0 V
–10
–3
Input instruction
execution time
VDD = 3.0 V
Output leak current, high
ILOH1
ILOH2
VO = VDD
SCK, SO/SB0, ports 2, 3, 6, 7, 8,
port 5 (with on-chip pull-up resistor)
3
VO = 13 V
VO = 0 V
VI = 0 V
Port 5 (N-ch open drain)
20
–3
µA
µA
kΩ
kΩ
Output leak current, low ILOL
On-chip pull-up resistor RL1
RL2
Ports 0 to 3 and 6 to 8 (except P00 pin)
Port 5
50
15
100
30
200
60
Data Sheet U10797EJ2V1DS
53
µPD754302, 754304, 754302(A), 754304(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
1.50
0.33
0.61
0.24
1.20
0.17
0.40
0.13
0.05
0.02
0.02
MAX.
5.00
1.00
1.85
0.75
3.50
0.55
1.50
0.50
10.0
5.00
3.00
Unit
mA
mA
mA
mA
mA
mA
mA
mA
µA
Note1
Note2
Note3
Supply current
IDD1
6.00 MHz
VDD = 5.0 V 10%
Crystal resonator VDD = 3.0 V 10%
IDD2
IDD1
IDD2
IDD5
C1 = C2 = 22 pF HALT mode
VDD = 5.0 V 10%
VDD = 3.0 V 10%
Note2
4.19 MHz
Crystal resonator VDD = 3.0 V 10%
C1 = C2 = 22 pF HALT mode
VDD = 5.0 V 10%
Note3
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
STOP mode
µA
TA = 25 °C
µA
Notes 1. Does not include current fed to on-chip pull-up resistor.
2. When processor clock control register (PCC) is set to 0011, during high-speed mode.
3. When PCC is set to 0000, during low-speed mode.
54
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
AC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
0.67
TYP.
MAX.
64
Unit
Note1
CPU clock cycle time
tCY
When system
VDD = 2.7 to 5.5 V
µs
(Minimum instruction execution
time = 1 machine cycle)
TI0, TI1 input frequency
clock is used
0.95
64
µs
fTI
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0
0
1
MHz
kHz
µs
275
TI0, TI1 input high- and
low-level width
t
TIH, tTIL
0.48
1.8
Note 2
10
µs
Interrupt input high- and
low-level width
tINTH, tINTL INT0
IM02 = 0
IM02 = 1
µs
µs
INT1, 2, 4
KR0-7
10
µs
10
µs
RESET low-level width
tRSL
10
µs
t
CY vs VDD
Notes 1. The CPU clock (Φ) cycle time (minimum
instruction execution time) is determined
by the ocillation frequency of the con-
nected resonator and the processor
clock control register (PCC). The figure
on the right shows the cycle time tCY
characteristics against the supply voltage
VDD when the system clock is used.
(During system clock operation)
64
60
6
5
Operation
guaranteed range
4
3
2. 2tCY or 128/fx depending on the setting of
the interrupt mode register (IM0).
µ
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
Data Sheet U10797EJ2V1DS
55
µPD754302, 754304, 754302(A), 754304(A)
Serial Transfer Operation
2-wire and 3-wire Serial I/O Mode (SCK...Internal clock output) (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
1300
3800
tKCY1/2–50
tKCY1/2–150
150
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY1
SCK high- and
low-level width
SINote1 setup time
(to SCK↑)
tKL1,
tKH1
tSIK1
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
R = 1 kΩ, C = 100 pF
500
SINote1 hold time
tKSI1
400
(from SCK↑)
600
SCK↓→SONote1
output delay time
tKSO1
VDD = 2.7 to 5.5 V
0
250
Note2
0
1000
Notes 1. SB0 in the 2-wire serial I/O mode.
2. R and C are the load resistance and load capacitance of the SO output line.
2-wire and 3-wire Serial I/O Mode (SCK...External clock input) (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY2
SCK high- and
low-level width
SINote1 setup time
(to SCK↑)
tKL2,
tKH2
tSIK2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
R = 1 kΩ, C = 100 pF
SINote1 hold time
tKSI2
(from SCK↑)
SCK↓→SONote1
output delay time
tKSO2
VDD = 2.7 to 5.5 V
300
Note2
0
1000
Notes 1. SB0 in the 2-wire serial I/O mode.
2. R and C are the load resistance and load capacitance of the SO output line.
56
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
AC Timing Test Points (Excluding X1 Input)
V
V
IH (MIN.)
IL (MAX.)
V
V
IH (MIN.)
IL (MAX.)
V
V
OH (MIN.)
OL (MAX.)
V
V
OH (MIN.)
OL (MAX.)
Note For the values, refer to the DC Characteristics.
Clock Timing
1/fX
tXL
tXH
X1 input
VDD – 0.1 V
0.1 V
TI0, TI1 Timing
1/fTI
tTIL
tTIH
TI0, TI1
Data Sheet U10797EJ2V1DS
57
µPD754302, 754304, 754302(A), 754304(A)
Serial Transfer Timing
3-wire Serial I/O Mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SI
Input data
tKSO1, 2
SO
Output data
2-wire Serial I/O Mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0
tKSO1, 2
58
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4
KR0-7
RESET Input Timing
tRSL
RESET
Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Symbol
Test Conditions
MIN.
0
TYP.
MAX.
Unit
µs
Release signal set time tSREL
Oscillation stabilization tWAIT
Release by RESET
Release by interrupt request
Note2
Note3
ms
ms
Note1
wait time
Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to
avoid unstable operation at oscillation start.
2. 217/fx and 215/fx can be selected with mask option.
3. Depends on setting of basic interval timer mode register (BTM) (see table below).
BTM3
BTM2
BTM1
BTM0
Wait Time
When fX = 4.19 MHz
220/fX (Approx. 250 ms)
217/fX (Approx. 31.3 ms)
215/fX (Approx. 7.81 ms)
213/fX (Approx. 1.95 ms)
When fX = 6.0 MHz
–
–
–
–
0
0
1
1
0
1
0
1
0
1
1
1
220/fX (Approx. 175 ms)
217/fX (Approx. 21.8 ms)
215/fX (Approx. 5.46 ms)
213/fX (Approx. 1.37 ms)
Data Sheet U10797EJ2V1DS
59
µPD754302, 754304, 754302(A), 754304(A)
Data Retention Timing (on releasing STOP mode by RESET)
Internal reset operation
HALT mode
Operation mode
STOP mode
Data retention mode
V
DD
VDDDR
tSREL
Execution of STOP instruction
RESET
tWAIT
Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal)
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
VDDDR
tSREL
Execution of STOP instruction
Standby release signal
(interrupt request)
tWAIT
60
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
13. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD VS VDD (System Clock: 6.0-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
0.5
PCC = 0000
System clock
HALT Mode
0.1
0.05
0.01
0.005
X1
X2
Crystal
resonator
6.0 MHz
22 pF
22 pF
0.001
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
Data Sheet U10797EJ2V1DS
61
µPD754302, 754304, 754302(A), 754304(A)
IDD VS VDD (System Clock: 4.19-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
1.0
0.5
PCC = 0010
PCC = 0001
PCC = 0000
System clock
HALT mode
0.1
0.05
0.01
0.005
X1
X2
Crystal
resonator
4.19 MHz
22 pF
22 pF
0.001
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
62
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
14. PACKAGE DRAWING
36 PIN PLASTIC SHRINK SOP (300 mil)
36
19
detail of lead end
1
18
A
H
I
J
L
B
C
N
M
M
D
P36GM-80-300B-3
NOTE
ITEM
MILLIMETERS
15.54 MAX.
0.97 MAX.
INCHES
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
A
B
C
D
E
F
0.612 MAX.
0.039 MAX.
0.8 (T.P.)
0.031 (T.P.)
+0.10
–0.05
+0.004
–0.003
0.014
0.35
0.125 0.075
1.8 MAX.
1.55
0.005 0.003
0.071 MAX.
0.061
G
H
I
7.7 0.3
5.6
0.303 0.012
0.220
J
1.1
0.043
+0.004
+0.10
0.008
K
L
0.20
–0.002
–0.05
+0.008
0.6 0.2
0.10
0.024
–0.009
M
N
0.004
0.004
0.10
Data Sheet U10797EJ2V1DS
63
µPD754302, 754304, 754302(A), 754304(A)
15.
RECOMMENDED SOLDERING CONDITIONS
The µPD754302 and µPD754304 should be soldered and mounted under the following recommended
conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 15-1. Surface Mounting Type Soldering Conditions
(1) µPD754302GS-xxx:
µPD754304GS-xxx:
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
µPD754302GS(A)-xxx: 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
µPD754304GS(A)-xxx: 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-2
Count: Twice or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-2
Count: Twice or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
(2) µPD754302GS-xxx-A: 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
µPD754304GS-xxx-A: 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), IR60-207-3
Count: Three times or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 to 72 hours)
Wave soldering
Partial heating
For details, contact an NEC Electronics sales representative.
–
–
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products with “-A” at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
64
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
APPENDIX A. COMPARISON OF FUNCTIONS AMONG µPD750004, 754304, AND 75P4308
Item
Program memory
µPD750004
Mask ROM
µPD754304
Mask ROM
µPD75P4308
One-time PROM
0000H-1FFFH
(8192 × 8 bits)
0000H-0FFFH
0000H-0FFFH
(4096 × 8 bits)
(4096 × 8 bits)
Data memory
CPU
000H-1FFH (512 × 4 bits) 000H-0FFH (256 × 4 bits)
75XL CPU
Instruction w/main system clock
execution
• 0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz)
• 0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz)
time
w/subsystem clock
• 122 µs (at 32.768 kHz)
No subsystem clock
I/O port
CMOS input
CMOS I/O
8 (of which 7 can be connected with on-chip pull-up resistor via software)
18 (on-chip pull-up resistor can be connected via software)
N-ch open-drain I/O
(withstand 13 V)
8 (pull-up resistor can be
connected by mask option)
4 (pull-up resistor can be
connected by mask option)
4 (no mask option)
Total
34
30 (no port 4 pins)
3 channels
Timer
4 channels
• Basic interval timer/
watchdog timer
• Basic interval timer/watchdog timer
2
• 8-bit timer/event counter 0 (fX/2 added)
2
•
8-bit timer/event counter
• 8-bit timer/event counter 1 (TI1, fX/2 added)
• 8-bit timer
(can be used as 16-bit timer/event counter)
• Watch timer
Clock output (PCL)
• Φ, 524, 262, or 65.5 kHz
(main system clock: 4.19 MHz)
• Φ, 750, 375, or 93.8 kHz
(main system clock: 6.0 MHz)
BUZ output
Provided
None
Serial interface
3 modes are supported
• 3-wire serial I/O mode
··· MSB/LSB first
selectable
2 modes are supported
• 3-wire serial I/O mode ··· MSB/LSB first selectable
• 2-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode
Watch mode register (WM)
Provided
None
System clock control register
(SCC)
Suboscillation circuit control
register (SOS)
MBS register
MB0, 1
MB0 only
Stack area (SBS1, 0)
Data Sheet U10797EJ2V1DS
65
µPD754302, 754304, 754302(A), 754304(A)
Item
TM0, 1 registers
µPD750004
µPD754304
µPD75P4308
Bits 0, 1, and 7 are
fixed to 0
–
Vectored interrupt
Test input
External: 3, internal: 4
External: 1, internal: 1
Provided
External: 1
Test enable flag (IEW)
Test request flag (IRQW)
Supply voltage
None
VDD = 2.2 to 5.5 V
TA = –40 to +85 ˚C
VDD = 1.8 to 5.5 V
Operating ambient temperature
Package
• 42-pin plastic
• 36-pin plastic shrink SOP
(300 mil, 0.8-mm pitch)
shrink DIP (600 mil)
• 44-pin plastic QFP
(10 × 10 mm)
66
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for development of application systems using the µPD754304.
In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each
model.
Language processor
RA75X relocatable assembler
Order code
Host machine
(part number)
OS
Supply media
3.5” 2HD
TM
PC-9800 series
MS-DOS
µS5A13RA75X
µS5A10RA75X
Ver. 3.30 to
5” 2HD
Note
Ver. 6.2
TM
3.5” 2HC
5” 2HC
µS7B13RA75X
µS7B10RA75X
IBM PC/AT
or
Refer to
“OS for IBM PC”
compatible machine
Device file
Order code
(part number)
Host machine
OS
Supply media
PC-9800 series
MS-DOS
Ver. 3.30 to
3.5” 2HD
5” 2HD
µS5A13DF754304
µS5A10DF754304
Note
Ver. 6.2
3.5” 2HC
5” 2HC
µS7B13DF754304
µS7B10DF754304
IBM PC/AT or
compatible machine
Refer to
“OS for IBM PC”
PROM writing tools
Hardware
PG-1500
The PG-1500 is a PROM programmer that can program PROM-contained single-chip
microcontrollers in the standalone mode or under control of a host machine, when
connected with an accessory board and an optional programmer adapter.
It can also program representative PROMs including 256K-bit to 4M-bit models.
PA-75P4308GS
This is a PROM programmer adapter dedicated to the µPD75P4308GS and connected
to the PG-1500.
Software
PG-1500 controller
This connects the PG-1500 and a host machine with a serial or parallel interface to
control the PG-1500 from the host machine.
Order code
(part number)
Host machine
OS
Supply media
3.5” 2HD
PC-9800 series
MS-DOS
Ver. 3.30 to
µS5A13PG1500
µS5A10PG1500
5” 2HD
Note
Ver. 6.2
3.5” 2HD
5” 2HC
µS7B13PG1500
µS7B10PG1500
IBM PC/AT or
compatible machine
Refer to
“OS for IBM PC”
Note Although Ver.5.00 and later have a task swap function, this function cannot be used with this software.
Remark The operation of the assembler, device file and PG-1500 controller is guaranteed only on the above
host machine and OS.
Data Sheet U10797EJ2V1DS
67
µPD754302, 754304, 754302(A), 754304(A)
Debugging tools
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
µPD754304.
The system configurations are described as follows.
Note 1
Hardware
IE-75000-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD754304 subseries, the emulation board IE-75300-R-EM and emulation probe that
are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging
can be made.
It contains the emulation board IE-75000-R-EM which is connected.
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD754304 subseries, the emulation board IE-75300-R-EM and emulation probe which
are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM program-
mer.
IE-75300-R-EM
EP-754304GS-R
Emulation board for evaluating the application systems that use a µPD754304
subseries.
It must be used with the IE-75000-R or IE-75001-R.
Emulation probe for the µPD754304GS.
It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the flexible board EV-9500GS-36 which facilitates connection to a
target system.
EV-9500GS-36
Software
IE control program
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix
I/F and controls the IE-75000-R or IE-75001-R on a host machine.
Order code
(Part number)
Host machine
OS
Supply media
3.5” 2HD
PC-9800 series
MS-DOS
µS5A13IE75X
µS5A10IE75X
Ver. 3.30 to
Ver. 6.2 Note 2
5” 2HD
3.5” 2HC
5” 2HC
µS7B13IE75X
µS7B10IE75X
IBM PC/AT or
compatible machine
Refer to
“OS for IBM PC”
Notes 1. Maintenance parts
2. Although Ver.5.00 and later have a task swap function, this function cannot be used with this software.
Remark Operation of the IE control program is guaranteed only on the above host machines and OSs.
68
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
OS for IBM PC
The following IBM PC OS’s are supported.
OS
Version
PC DOSTM
Ver. 5.02 to Ver. 6.3
Note
Note
J6.1/V
to J6.3/V
MS-DOS
Ver. 5.0 to Ver. 6.22
Note
Note
5.0/V
to 6.2/V
Note
IBM DOSTM
J5.02/V
Note Only English version is supported.
Caution Ver. 5.0 and later have the task swap function, but this function cannot be used for this
software.
Data Sheet U10797EJ2V1DS
69
µPD754302, 754304, 754302(A), 754304(A)
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device related documents
Document Number
Document Name
Japanese
English
This document
U10909E
U10123E
—
µPD754302, 754304 Data Sheet
µPD75P4308 Data Sheet
U10797J
U10909J
U10123J
IEM-5605
U10453J
µPD754304 User’s Manual
µPD754304 Instruction Table
75XL Series Selection Guide
U10453E
Development tool related documents
Document Number
Document Name
Japanese
English
EEU-1416
EEU-1493
U10677E
Hardware IE-75000-R/IE-75001-R User's Manual
IE-75300-R-EM User's Manual
EEU-846
U11354J
U10677J
EEU-651
EEU-731
EEU-730
EEU-704
EP-754304GS-R User's Manual
PG-1500 User's Manual
EEU-1335
EEU-1346
EEU-1363
EEU-1291
Software
RA75X Assembler Package User's Manual
Operation
Language
PG-1500 Controller User's Manual
PC-9800 series
(MS-DOS) base
PC-9800 series
(PC DOS) base
EEU-5008
U10540E
Other related documents
Document Number
Japanese English
Document Name
IC Package Manual
C10943X
C10535J
C11531J
C10983J
MEM-539
MEI-603
MEI-604
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
C10535E
IEI-1209
NEC Semiconductor Device Reliability/Quality Control System
Static Electricity Discharge (ESD) Test
C10983E
–
MEI-1202
–
Guide to Quality Assurance for Semiconductor Devices
Microcomputer Related Product Guide - Other Manufacturers
Caution These documents are subject to change without notice. Be sure to read the latest documents.
70
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet U10797EJ2V1DS
71
µPD754302, 754304, 754302(A), 754304(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
72
Data Sheet U10797EJ2V1DS
µPD754302, 754304, 754302(A), 754304(A)
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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