UPD75P3216GT [RENESAS]
4-BIT, OTPROM, 6MHz, MICROCONTROLLER, PDSO48, 0.375 INCH, 0.65 MM PITCH, PLASTIC, SSOP-48;
| 型号： | UPD75P3216GT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4-BIT, OTPROM, 6MHz, MICROCONTROLLER, PDSO48, 0.375 INCH, 0.65 MM PITCH, PLASTIC, SSOP-48 可编程只读存储器 时钟 光电二极管 外围集成电路 |
| 文件： | 总435页 (文件大小：1633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
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of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
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of Renesas Electronics or others.
3.
4.
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Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
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you or third parties arising from the use of these circuits, software, or information.
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7.
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User’s Manual
µPD753208
4-bit Single-chip Microcontrollers
µPD753204
µPD753206
µPD753208
µPD75P3216
Document No. U10158EJ2V1UM00 (2nd edition)
Date Published November 1999 N CP(K)
1995
©
Printed in Japan
[MEMO]
2
User’s Manual U10158EJ2V1UM00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
QTOP is a trademark of NEC Corporation.
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
3
User’s Manual U10158EJ2V1UM00
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7D 98.12
4
User’s Manual U10158EJ2V1UM00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
5
User’s Manual U10158EJ2V1UM00
MAJOR REVISIONS IN THIS EDITION
Page
Contents
Throughout
Change of µPD753204, 753206, 753208, and 75P3216 from “under development” to “have been
developed”.
Change of input withstand voltage of ports 4 and 5 at N-ch open drain from 12 V to 13 V.
Addition of data bus pins (D0-D7).
p.45
Change of Table 2-3. List of Recommended Connections for Unused Pins.
Change of Table 4-1. Differences between Mk I Mode and Mk II Mode.
Addition of Caution to 5.6.7 (a) Bus release signal (REL) and 5.6.7 (b) Command signal (CMD).
Addition of 7.4 Mask Option Selection.
p.75
p.232
p.334
p.343
P.344
p.374
p.423
p.431
Change of 9.2 Writing Program Memory.
Change of 9.3 Reading Program Memory.
Modification of the instruction list in 11.3 Op Code of Each Instruction.
Change of ordering media in APPENDIX C ORDERING MASK ROMS.
Addition of APPENDIX F REVISION HISTORY.
The mark
shows major revised points.
6
User’s Manual U10158EJ2V1UM00
INTRODUCTION
Readers:
Purpose:
This manual is intended for user engineers who understand the functions of the µPD753204,
753206, 753208, and 75P3216, and wish to design application systems using any of these
microcontrollers.
This manual describes the hardware functions of the µPD753204, 753206, 753208, and 75P3216
in the organization described below.
Organization: This manual contains the following information:
•
•
•
•
•
•
•
•
•
•
•
General
Pin Functions
Features of Architecture and Memory Map
Internal CPU Functions
Peripheral Hardware Functions
Interrupt Functions and Test Functions
Standby Functions
Reset Function
Writing and Verifying PROM
Mask Option
Instruction Set
How to Read This Manual:
It is assumed that readers for this manual have general knowledge on electricity, logic circuits, and
microcontrollers.
•
If you have experience of using the µPD753108,
→ ReadAPPENDIXA µPD753108, 753208AND75P3216FUNCTIONLISTtocheckdifferences
described in this manual.
•
If you use this manual as the manual for the µPD753204, 753206, and 75P3216,
→ Unless otherwise specified, the µPD753208 is regarded as the representative model, and
description throughout this manual is focused on this model. Refer to 1.3 Differences among
µPD753208 Subseries Products to check the differences among the respective models.
•
•
•
To check the functions of an instruction whose mnemonic is known,
→ Refer to APPENDIX D INSTRUCTION INDEX.
To check the functions of a specific internal circuit,
→ Refer to APPENDIX E HARDWARE INDEX.
To understand the overall functions of the µPD753204, 753206, 753208, and 75P3216,
→ Read this manual in the order of TABLE OF CONTENTS.
7
User’s Manual U10158EJ2V1UM00
Legend
Data significance
Active low
: Left: high-order, right: low-order
××× (top bar over pin or signal name)
:
Address of memory map
Note
: Top: low, Bottom: high
: Description of an item withNote in the text
: Important information
Caution
Remark
: Supplement
Important point and emphasis : Bold letters
Numeric notation : Binary ················×××× or ××××B
Decimal··············××××
Hexadecimal······××××H
8
User’s Manual U10158EJ2V1UM00
Related documents Some documents are preliminary editions, but they are not so specified in the tables below.
Documents related to devices
Document Number
Document Name
Japanese
English
µPD753204, 753206, 753208 Data Sheet
µPD75P3216 Data Sheet
U10166J
U10166E
U10241J
U10158J
U10453J
U10241E
µPD753208 User’s Manual
This manual
U10453E
75XL Series Selection Guide
Documents related to development tools
Document Number
Japanese
Document Name
English
Hardware
Software
IE-75000-R/IE-75001-R User’s Manual
IE-75300-R-EM User’s Manual
EP-753208GT-R User’s Manual
PG-1500 User’s Manual
EEU-846
U11354J
U10739J
U11940J
U12622J
U12385J
EEU-1416
U11354E
U10739E
U11940E
EEU-1346
EEU-1363
EEU-1291
U10540E
RA75X Assembler Package User’s Manual Operation
Language
PG-1500 Controller
User’s Manual
PC-9800 Series (MS-DOS) Based EEU-704
IBM PC Series (PC DOS) Based EEU-5008
Other documents
Document Number
Document Name
Japanese
English
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
C10535J
C11531J
C10983J
C11892J
C10535E
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability and Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic
Discharge (ESD)
Microcontroller-Related Products Guide - by third parties
U11416J
–
Caution The above related documents are subject to change without notice. Be sure to use the latest edition
when you design your system.
9
User’s Manual U10158EJ2V1UM00
[MEMO]
10
User’s Manual U10158EJ2V1UM00
TABLE OF CONTENTS
CHAPTER 1 GENERAL .........................................................................................................................23
1.1 Function Outline .....................................................................................................................24
1.2 Ordering Information ..............................................................................................................26
1.3 Differences among µPD753208 Subseries Products...........................................................26
1.4 Block Diagram.........................................................................................................................27
1.5 Pin Configuration (Top View) .................................................................................................28
CHAPTER 2 PIN FUNCTIONS..............................................................................................................31
2.1 Pin Functions of µPD753208..................................................................................................31
2.2 Pin Functions ..........................................................................................................................35
2.2.1
2.2.2
P00-P03 (PORT0), P10, P13 (PORT1) ...................................................................................... 35
P20-P23 (PORT2), P30-P33 (PORT3)
P50-P53 (PORT5), P60-P63 (PORT6)
P80-P83 (PORT8) and P90-P93 (PORT9) ................................................................................. 36
TI0 .............................................................................................................................................. 37
PTO0-PTO2 ................................................................................................................................ 37
PCL ............................................................................................................................................ 37
BUZ ............................................................................................................................................ 37
SCK, SO/SB0, and SI/SB1 ......................................................................................................... 37
INT4............................................................................................................................................ 38
INT0............................................................................................................................................ 38
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10 KR0-KR3 .................................................................................................................................... 38
2.2.11 S12-S23...................................................................................................................................... 38
2.2.12 COM0-COM3.............................................................................................................................. 39
2.2.13 VLC0-VLC2 ................................................................................................................................ 39
2.2.14 BIAS ........................................................................................................................................... 39
2.2.15 LCDCL........................................................................................................................................ 39
2.2.16 SYNC.......................................................................................................................................... 39
2.2.17 X1 and X2 ................................................................................................................................... 39
2.2.18 RESET........................................................................................................................................ 40
2.2.19 MD0-MD3 (µPD75P3216 only)................................................................................................... 40
2.2.20 D0-D7 (µPD75P3216 only)......................................................................................................... 40
2.2.21 IC (µPD753204, 753206, and 753208 only) ............................................................................... 40
2.2.22 VPP (µPD75P3216 only) ............................................................................................................. 40
2.2.23 VDD .............................................................................................................................................. 41
2.2.24 VSS .............................................................................................................................................. 41
2.3 Pin Input/Output Circuits .......................................................................................................42
2.4 Recommended Connections for Unused Pins .....................................................................45
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP ............................................47
3.1 Bank Configuration and Addressing Mode of Data Memory ..............................................47
User’s Manual U10158EJ2V1UM00
11
3.1.1
3.1.2
Bank configuration of data memory............................................................................................ 47
Addressing mode of data memory ............................................................................................. 49
3.2 Bank Configuration of General-Purpose Registers.............................................................63
3.3 Memory-Mapped I/O ...............................................................................................................68
CHAPTER 4 INTERNAL CPU FUNCTIONS ........................................................................................75
4.1 Switching Function between Mk I Mode and Mk II Mode ....................................................75
4.1.1
4.1.2
Difference between Mk I and Mk II modes ................................................................................. 75
Setting method of stack bank select register (SBS) ................................................................... 76
4.2 Program Counter (PC) ............................................................................................................77
4.3 Program Memory (ROM) .........................................................................................................78
4.4 Data Memory (RAM) ................................................................................................................83
4.4.1
4.4.2
Configuration of data memory .................................................................................................... 83
Specifying bank of data memory ................................................................................................ 84
4.5 General-Purpose Registers....................................................................................................88
4.6 Accumulators ..........................................................................................................................89
4.7 Stack Pointer (SP) and Stack Bank Selection Register (SBS) ............................................89
4.8 Program Status Word (PSW) ..................................................................................................93
4.9 Bank Selection Register (BS) ................................................................................................97
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS......................................................................99
5.1 Digital I/O Port .........................................................................................................................99
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
Types, features, configuration of digital I/O ports ..................................................................... 100
Setting I/O mode ...................................................................................................................... 105
Digital I/O port manipulation instruction ................................................................................... 107
Operation of digital I/O port ...................................................................................................... 110
Connecting pull-up resistors ..................................................................................................... 112
I/O timing of digital I/O port....................................................................................................... 114
5.2 Clock Generator.....................................................................................................................116
5.2.1
5.2.2
5.2.3
5.2.4
Clock generator configuration................................................................................................... 116
Clock generator function and operation.................................................................................... 117
Setting of CPU clock................................................................................................................. 123
Clock output circuit ................................................................................................................... 125
5.3 Basic Interval Timer/Watchdog Timer .................................................................................128
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Basic interval timer/watchdog timer configuration .................................................................... 128
Basic interval timer mode register (BTM) ................................................................................. 129
Watchdog timer enable flag (WDTM) ....................................................................................... 131
Basic interval timer (BT) operations ......................................................................................... 132
Watchdog timer operations....................................................................................................... 133
Other functions ......................................................................................................................... 135
5.4 Watch Timer ...........................................................................................................................137
5.4.1
5.4.2
Configuration of watch timer ..................................................................................................... 137
Watch mode register ................................................................................................................ 138
User’s Manual U10158EJ2V1UM00
12
5.5 Timer/Event Counter .............................................................................................................140
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Configuration of timer/event counter......................................................................................... 140
8-bit timer/event counter mode operation ................................................................................. 150
PWM pulse generator mode (PWM mode) operation............................................................... 162
16-bit timer counter mode operation......................................................................................... 168
Carrier generator mode (CG Mode) operation ......................................................................... 178
Notes on using the timer/event counter .................................................................................... 190
5.6 Serial Interface ......................................................................................................................197
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
Serial interface function ............................................................................................................ 197
Configuration of serial interface ................................................................................................ 198
Register function ...................................................................................................................... 202
Operation stop mode ................................................................................................................ 210
Operation in 3-wire serial I/O mode.......................................................................................... 212
Operation in 2-wire serial I/O mode.......................................................................................... 222
SBI mode operation.................................................................................................................. 229
SCK pin output manipulation .................................................................................................... 262
5.7 LCD Controller/Driver............................................................................................................263
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.9
LCD controller/driver configuration ........................................................................................... 263
LCD controller/driver functions ................................................................................................. 265
Display mode register (LCDM) ................................................................................................. 265
Display control register (LCDC) ................................................................................................ 267
LCD/Port Selection Register (LPS) .......................................................................................... 269
Display data memory ................................................................................................................ 270
Common signal and segment signal ........................................................................................ 272
Supply of LCD drive power VLC0, VLC1, and VLC2 ................................................................ 276
Display mode ............................................................................................................................ 279
5.8 Bit Sequential Buffer ............................................................................................................292
CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS..................................................295
6.1 Configuration of Interrupt Control Circuit ..........................................................................295
6.2 Types of Interrupt Sources and Vector Tables ...................................................................297
6.3 Hardware Controlling Interrupt Functions .........................................................................299
6.4 Interrupt Sequence ...............................................................................................................307
6.5 Nesting processing Control .................................................................................................308
6.6 Vector Address Share Interrupt Processing ......................................................................310
6.7 Machine Cycles until Interrupt Processing ........................................................................312
6.8 Effective Usage of Interrupt .................................................................................................314
6.9 Application of Interrupt ........................................................................................................314
6.10 Test Function ........................................................................................................................322
6.10.1 Types of test sources ................................................................................................................ 322
6.10.2 Hardware devices controlling the test function ......................................................................... 322
CHAPTER 7 STANDBY FUNCTIONS.................................................................................................327
7.1 Standby Mode Setting and Operation Status.....................................................................329
7.2 Standby Mode Release.........................................................................................................331
7.3 Operation After Releasing the Standby Mode....................................................................333
7.4 Mask Option Selection .........................................................................................................334
7.5 Application of Standby Mode ..............................................................................................334
User’s Manual U10158EJ2V1UM00
13
CHAPTER 8 RESET FUNCTIONS......................................................................................................337
CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY).....................................341
9.1 Operation Mode for Writing/Verifying Program Memory ...................................................342
9.2 Writing Program Memory .....................................................................................................343
9.3 Reading Program Memory ...................................................................................................344
9.4 Screening of One-Time PROM.............................................................................................345
CHAPTER 10 MASK OPTION .............................................................................................................347
10.1 Pin ..........................................................................................................................................347
10.1.1 Mask option of P50 through P53 .............................................................................................. 347
10.1.2 Mask option of VLC0 through VLC2 ......................................................................................... 347
10.2 Mask Option of Standby Function.......................................................................................348
CHAPTER 11 INSTRUCTION SET .....................................................................................................349
11.1 Unique Instructions ..............................................................................................................349
11.1.1 GETI instruction........................................................................................................................ 349
11.1.2 Bit manipulation instruction ...................................................................................................... 350
11.1.3 String-effect instruction ............................................................................................................. 350
11.1.4 Base number adjustment instruction ........................................................................................ 351
11.1.5 Skip instruction and number of machine cycles required for skipping ...................................... 352
11.2 Instruction Sets and their Operations ................................................................................353
11.3 Op Code of Each Instruction ...............................................................................................369
11.4 Instruction Function and Application .................................................................................375
11.4.1 Transfer instructions ................................................................................................................. 376
11.4.2 Table reference instructions...................................................................................................... 382
11.4.3 Bit transfer instructions ............................................................................................................. 386
11.4.4 Operation instructions .............................................................................................................. 387
11.4.5 Accumulator manipulation instructions ..................................................................................... 393
11.4.6 Increment/decrement instructions ............................................................................................ 394
11.4.7 Compare instructions ............................................................................................................... 395
11.4.8 Carry flag manipulation instructions ......................................................................................... 396
11.4.9 Memory bit manipulation instructions ....................................................................................... 397
11.4.10 Branch instructions ................................................................................................................... 400
11.4.11 Subroutine/stack control instructions........................................................................................ 404
11.4.12 Interrupt control instructions ..................................................................................................... 409
11.4.13 Input/output instructions ........................................................................................................... 410
11.4.14 CPU control instructions ........................................................................................................... 411
11.4.15 Special instructions .................................................................................................................. 412
APPENDIX A µPD753108, 753208 AND 75P3216 FUNCTION LIST.............................................415
APPENDIX B DEVELOPMENT TOOLS ..............................................................................................417
APPENDIX C ORDERING MASK ROMS ..........................................................................................423
User’s Manual U10158EJ2V1UM00
14
APPENDIX D INSTRUCTION INDEX..................................................................................................425
D.1 Instruction Index (by function) ............................................................................................425
D.2 Instruction Index (alphabetical order).................................................................................427
APPENDIX E HARDWARE INDEX .....................................................................................................429
APPENDIX F REVISION HISTORY......................................................................................................431
User’s Manual U10158EJ2V1UM00
15
LIST OF FIGURES (1/4)
Figure No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Selecting MBE = 0 Mode and MBE = 1 Mode ..................................................................................... 48
Data Memory Configuration and Addressing Range for Each Addressing Mode ................................ 50
Static RAM Address Update Method ................................................................................................... 56
Example of Using Register Banks ....................................................................................................... 64
General-Purpose Register Configuration (for 4-bit operation) ............................................................. 66
General-Purpose Register Configuration (for 8-bit operation) ............................................................. 67
µPD753208 I/O Map ............................................................................................................................ 70
4-1
Stack Bank Select Register Format ..................................................................................................... 76
Program Counter Structure .................................................................................................................. 77
Program Memory Map (1/4) ................................................................................................................. 79
Data Memory Map ............................................................................................................................... 85
Configuration of Display Data Memory ................................................................................................ 87
General-Purpose Register Configuration ............................................................................................. 88
Register Pair Configuration .................................................................................................................. 88
Accumulators ....................................................................................................................................... 89
Stack Pointer and Stack Bank Selection Register Configuration ......................................................... 90
Data Saved in Stack Memory (Mk I mode) .......................................................................................... 91
Data Restored from Stack Memory (Mk I mode) ................................................................................. 91
Data Saved in Stack Memory (Mk II mode) ......................................................................................... 92
Data Restored from Stack Memory (MkII mode) ................................................................................. 92
Program Status Word Format .............................................................................................................. 93
Bank Selection Register Format .......................................................................................................... 97
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
Digital Ports Data Memory Addresses ................................................................................................. 99
Port 0, 1 Configuration ....................................................................................................................... 101
Port 3, 6 Configuration ....................................................................................................................... 102
Port 2 Configuration ........................................................................................................................... 102
Port 5 Configuration ........................................................................................................................... 103
Port 8, 9 Configuration ....................................................................................................................... 104
Port Mode Register Formats .............................................................................................................. 106
Pull-Up Resistor Register Format ...................................................................................................... 113
I/O Timing of Digital I/O Port .............................................................................................................. 114
ON Timing of Internal Pull-up Resistor Connected via Software ....................................................... 115
Clock Generator Block Diagram ......................................................................................................... 116
Format of Processor Clock Control Register...................................................................................... 119
System Clock Oscillator External Circuit ............................................................................................ 120
Example of Connecting Oscillator Incorrectly .................................................................................... 121
Switching to/from CPU Clock ............................................................................................................. 124
Clock Output Circuit Block Diagram ................................................................................................... 125
Clock Output Mode Register Format.................................................................................................. 126
Application Example of Remote Control Waveform Output................................................................ 127
Basic Interval Timer/Watchdog Timer Block Diagram ........................................................................ 128
Basic Interval Timer Mode Register Format....................................................................................... 130
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
User’s Manual U10158EJ2V1UM00
16
LIST OF FIGURES (2/4)
Figure No.
Title
Page
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-33
5-34
5-35
5-36
5-3
Watchdog Timer Enable Flag (WDTM) Format .................................................................................. 131
Watch Timer Block Diagram ............................................................................................................... 138
Format of Watch Mode Register ........................................................................................................ 139
Timer/Event Counter Block Diagram (channel 0) ............................................................................... 141
Timer Counter Block Diagram (channel 1) ......................................................................................... 142
Timer Counter Block Diagram (channel 2) ......................................................................................... 143
Timer/Event Counter Mode Register (channel 0) Format .................................................................. 145
Timer Counter Mode Register (channel 1) Format ............................................................................ 146
Timer Counter Mode Register (channel 2) Format ............................................................................ 147
Timer/Event Counter Output Enable Flag Format.............................................................................. 148
Timer Counter Control Register Format ............................................................................................. 149
Timer/Event Counter Mode Register Setup (1/3) ............................................................................... 151
Timer Counter Control Register Setup............................................................................................... 152
Timer Counter Control Register Setup............................................................................................... 154
Timer/Event Counter Output Enable Flag Setup................................................................................ 154
Configuration of Timer/Event Counter ................................................................................................ 157
Count Operation Timing ..................................................................................................................... 157
Configuration of Event Count ............................................................................................................. 159
Count Operation Timing ..................................................................................................................... 160
Timer Counter Mode Register Setup ................................................................................................. 163
Timer Counter Control Register Setup............................................................................................... 164
Configuration of PWM Pulse Generator ............................................................................................. 166
PWM Pulse Generator Operation Timing ........................................................................................... 166
Timer Counter Mode Register Setup ................................................................................................. 169
Timer Counter Control Register Setup............................................................................................... 170
Timer Counter Operation Configuration ............................................................................................. 173
Count Operation Timing ..................................................................................................................... 173
Count Operation Configuration .......................................................................................................... 175
Count Operation Timing ..................................................................................................................... 176
Timer Counter Mode Register Setup (n = 1, 2) .................................................................................. 179
Timer Counter Output Enable Flag Setup .......................................................................................... 180
Timer Counter Control Register Setup............................................................................................... 180
Carrier Generator Operation Configuration ........................................................................................ 183
Carrier Generator Operation Timing .................................................................................................. 184
Example of SBI System Configuration ............................................................................................... 198
Serial Interface Block Diagram........................................................................................................... 199
Serial Operation Mode Register (CSIM) Format ................................................................................ 202
Serial Bus Interface Control Register (SBIC) Format......................................................................... 205
System Comprising Shift Register and Peripheral Devices Configuration ........................................ 208
Example of System Configuration in 3-Wire Serial I/O Mode ............................................................ 212
3-Wire Serial I/O Mode Timing ........................................................................................................... 215
Operation of RELT and CMDT ........................................................................................................... 216
Transfer Bit Change Circuit ................................................................................................................ 217
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
User’s Manual U10158EJ2V1UM00
17
LIST OF FIGURES (3/4)
Figure No.
Title
Page
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5-71
5-72
5-73
5-74
5-75
5-76
5-77
5-78
5-79
5-80
5-81
5-82
5-83
5-84
5-85
5-86
5-87
5-88
5-89
5-90
5-91
5-92
5-93
5-94
5-95
5-96
5-97
5-98
5-99
5-100
5-101
5-102
5-103
5-104
5-105
5-106
Example of System Configuration in 2-Wire Serial I/O Mode ............................................................ 222
2-Wire Serial I/O Mode Timing ........................................................................................................... 225
Operation of RELT and CMDT ........................................................................................................... 226
SBI System Configuration Example ................................................................................................... 229
SBI Transfer Timings .......................................................................................................................... 231
Bus Release Signal............................................................................................................................ 232
Command Signal ............................................................................................................................... 232
Address .............................................................................................................................................. 233
Selecting Slave by Address................................................................................................................ 233
Command........................................................................................................................................... 234
Data.................................................................................................................................................... 234
Acknowledge Signal ........................................................................................................................... 235
Busy and Ready Signals .................................................................................................................... 236
RELT, CMDT, RELD, CMDD Operation (master) ............................................................................... 242
RELT, CMDT, RELD, CMDD Operation (slave) .................................................................................. 242
ACKT Operation ................................................................................................................................. 242
ACKE Operation................................................................................................................................. 243
ACKD Operation ................................................................................................................................ 244
BSYE Operation ................................................................................................................................. 244
Pin Configuration................................................................................................................................ 247
Address Transmission Operation from Master Device to Slave Device (when WUP = 1) .................. 249
Command Transmission Operation from Master Device to Slave Device .......................................... 250
Data Transmission Operation from Master Device to Slave Device ................................................... 251
Data Transmission Operation from Slave Device to Master Device ................................................... 252
Example of Serial Bus Configuration ................................................................................................. 255
Transfer Format of READ Command ................................................................................................. 257
Transfer Formats of WRITE and END Commands............................................................................. 258
Transfer Format of STOP Command.................................................................................................. 258
Transfer Format of STATUS Command .............................................................................................. 259
Status Format of STATUS Command................................................................................................. 259
Transfer Format of RESET Command ............................................................................................... 260
Transfer Format of CHGMST Command ............................................................................................ 260
Operations of Master and Slave in Case of Error .............................................................................. 261
SCK/P01 Pin Configuration ................................................................................................................ 262
LCD Controller/Driver Block Diagram ................................................................................................ 264
Display Mode Register Format........................................................................................................... 266
Format of Display Control Register .................................................................................................... 267
LCD/Port Selection Register Format .................................................................................................. 269
Data Memory Map ............................................................................................................................. 270
Relationship between Display Data Memory and Common Segments.............................................. 271
Common Signal Waveform (Static) .................................................................................................... 274
Common Signal Waveform (1/2 bias method).................................................................................... 274
Common Signal Waveform (1/3 bias method).................................................................................... 274
Common and Segment Signal Electric Potentials and Phases.......................................................... 275
User’s Manual U10158EJ2V1UM00
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LIST OF FIGURES (4/4)
Figure No.
Title
Page
5-107
5-108
5-109
5-110
5-111
5-112
5-113
5-114
5-115
5-116
5-117
5-118
5-119
5-120
5-121
5-122
LCD Drive Power Connection Examples (when split resistor is incorporated)................................... 277
LCD Drive Power Supply Connection Examples................................................................................ 278
Static Mode LCD Display Pattern and Electrode Connection ............................................................ 279
Static LCD Panel Connection Example.............................................................................................. 280
Static LCD Drive Waveform Example................................................................................................. 281
Division by 2 Mode LCD Display Pattern and Electrode Connection ................................................. 282
Division by 2 LCD Panel Connection Example .................................................................................. 283
Division by 2 LCD Drive Waveform Example (1/2 bias method) ........................................................ 284
Division by 3 Mode LCD Display Pattern and Electrode Connection ................................................. 285
Division by 3 LCD Panel Connection Example .................................................................................. 286
Division by 3 LCD Drive Waveform Example (1/2 bias method) ........................................................ 287
Division by 3 LCD Drive Waveform Example (1/3 bias method) ........................................................ 288
Division by 4 Mode LCD Display Pattern and Electrode Connection ................................................. 289
Division by 4 LCD Panel Connection Example .................................................................................. 290
Division by 4 LCD Drive Waveform Example (1/3 bias method) ........................................................ 291
Bit Sequential Buffer Format .............................................................................................................. 292
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
Interrupt Control Circuit Block Diagram.............................................................................................. 296
Interrupt Vector Table ......................................................................................................................... 298
Interrupt Priority Selection Register ................................................................................................... 301
Configurations of INT0, and INT4 ...................................................................................................... 303
Noise Detection Circuit Input/Output Timing ...................................................................................... 304
INT0 Edge Detection Mode Register (IM0) Format............................................................................ 305
Interrupt Processing Sequence.......................................................................................................... 307
Nestings by High-Order Priority Interrupts ......................................................................................... 308
Nestings by Changing Interrupt Status Flag ...................................................................................... 309
KR0-KR3 Block Diagram.................................................................................................................... 324
Format of INT2 Edge Detection Mode Register (IM2)........................................................................ 347
7-1
7-2
Standby Mode Release Operation ..................................................................................................... 332
Wait Time When STOP Mode Is Released ........................................................................................ 333
8-1
8-2
Configuration of Reset Function......................................................................................................... 337
Reset Operation by RESET Signal Generation ................................................................................. 337
User’s Manual U10158EJ2V1UM00
19
LIST OF TABLES (1/2)
Table No.
Title
Page
2-1
2-2
2-3
Pin Functions of Digital I/O Ports ......................................................................................................... 31
Pin Function of Pins Other Than Port Pins .......................................................................................... 33
List of Recommended Connections for Unused Pins........................................................................... 45
3-1
3-2
3-3
3-4
Addressing Mode ................................................................................................................................. 51
Register Bank Selected by RBE and RBS ........................................................................................... 63
Example of Using Different Register Banks for Normal Routine and Interrupt Routine ....................... 64
Addressing Modes Applicable to Operating the Peripheral Hardware ................................................. 68
4-1
4-2
4-3
4-4
4-5
4-6
Differences between Mk I Mode and Mk II Mode ................................................................................. 75
Stack Area Selected by SBS................................................................................................................ 89
PSW Flags Saved and Restored during Stack Operation.................................................................... 93
Carry Flag Manipulation Instructions ................................................................................................... 94
Interrupt Status Flag Indication ............................................................................................................ 95
RBE, RBS, and Selected Register Bank .............................................................................................. 97
5-1
Types and Features of Digital Ports ................................................................................................... 100
I/O Pin Manipulation Instructions ....................................................................................................... 109
Operation When an I/O Port Is Manipulated ...................................................................................... 111
Pull-Up Resistor Incorporation Specification Method......................................................................... 112
Maximum Time Required to Switch to/from CPU Clock ..................................................................... 123
Operation Modes of Timer/Event Counter.......................................................................................... 140
Selection of Serial Clock and Applications (in 3-wire serial I/O mode) .............................................. 216
Selection of Serial Clock and Applications (in 2-wire serial I/O mode) .............................................. 226
Selection of Serial Clock and Applications (in SBI mode).................................................................. 241
Signal in SBI Mode (1/2) .................................................................................................................... 245
Maximum Number of Displayed Picture Elements ............................................................................. 265
Common Signal ................................................................................................................................. 272
LCD Drive Voltage (Static) ................................................................................................................. 273
LCD Drive Voltage (1/2 Bias method) ................................................................................................ 273
LCD Drive Voltage (1/3 Bias method) ................................................................................................ 273
LCD Drive Power Supply Values ........................................................................................................ 276
S12-S19 Pin Selection and Non-selection Voltage (Static Display Example) .................................... 279
S12-S15 Pin Selection and Non-selection Voltage (Division by 2 Display Example) ......................... 282
S12-S14 Pin Selection and Non-selection Voltage (Division by 3 Display Example) ......................... 285
S14, S15 Selection and Non-selection Voltage (Division by 4 Display Example) .............................. 289
5-2
5-3
5-4
5-5
5-6
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
6-1
6-2
6-3
6-4
6-5
6-6
Types of Interrupt Sources ................................................................................................................. 297
Set Signals for Interrupt Request Flags ............................................................................................. 300
IST1 and IST0 and Interrupt Processing Status ................................................................................ 306
Identifying Interrupt Sharing Vector Table Address ............................................................................ 310
Types of Test Sources ........................................................................................................................ 325
Set Signal for Test Request Flag ........................................................................................................ 325
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LIST OF TABLES (2/2)
Table No.
Title
Page
7-1
7-2
Operation Status in Standby Mode .................................................................................................... 329
Wait Time Selection by Using BTM .................................................................................................... 333
8-1
Status of Each Device After Reset ..................................................................................................... 338
9-1
9-2
Pins Used to Write or Verify Program Memory................................................................................... 341
Operation Mode ................................................................................................................................. 342
10-1
11-1
Selecting Mask Option of Pin ............................................................................................................. 347
Types of Bit Manipulation Addressing Modes and Specification Range ............................................ 350
User’s Manual U10158EJ2V1UM00
21
[MEMO]
User’s Manual U10158EJ2V1UM00
22
CHAPTER 1 GENERAL
The µPD753204, 753206, 753208, and 75P3216 are 4-bit single-chip microcontrollers in the NEC’s 75XL series,
a successor to the 75X series that boasts a wealth of variations. TheseµPD753204, 753206, 753208, and 75P3216
are collectively called µPD753208 subseries.
The µPD753208 is based on the existing µPD75308B, but has a high-order ROM capacity and more sophisticated
CPU functions, and can operate at high speeds at a voltage of as low as 1.8 V. In addition, the µPD753208 is also
provided with an LCD controller/driver.
This model is available in a small plastic shrink SOP (375 mil, 0.65 mm pitch) and is ideal for small application
set that uses an LCD panel.
The features of the µPD753208 are as follows:
•
•
Low-voltage operation: VDD = 1.8 to 5.5 V
Variable instruction execution time useful for high-speed operation and power saving
0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (4.19 MHz operation)
0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (6.0 MHz operation)
Five timer channels
•
•
•
Programmable LCD controller/driver
Small package (48-pin plastic shrink SOP (375 mil, 0.65 mm pitch))
The µPD75P3216 is provided with a one-time PROM that can be electrically written and is pin-compatible with
the µPD753204, 753206, and 753208. This one-time PROM model is convenient for experimental development of
an application system or small-scale production of the application system.
Application Field
•
•
•
•
•
Remote controllers
CD/cassette players with radio
Cameras
Sphygmomanometers
Gas meters, etc.
Remark Unless otherwise specified, the µPD753208 is regarded as the representative model, and description
throughout this manual is focused on this model.
User’s Manual U10158EJ2V1UM00
23
CHAPTER 1 GENERAL
1.1 Function Outline
(1/2)
Parameter
Function
Instruction execution time
• 0.95, 1.91, 3.81, 15.3 µs (System clock: 4.19 MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (System clock: 6.0 MHz operation)
On-chip memory
ROM 4096 × 8 bits (µPD753204)
6144 × 8 bits (µPD753206)
8192 × 8 bits (µPD753208)
16384 × 8 bits (µPD75P3216)
RAM 512 × 4 bits
General-purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
CMOS input
6
Internal pull-up resistors can be connected by software: 5
CMOS input/output
20 Internal pull-up resistors can be connected by software: 20
Also used for segment pins: 8
N-ch open-drain
input/output
4
13 V withstand voltage. Internal pull-up resistors can be specified by mask optionNote 1
Total
30
LCD controller/driver
• Segment selection:
4/8/12 segments (can be changed to CMOS input/
output port in 4 time-unit; max. 8)
• Display mode selection: Static 1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
Note 2
Internal split resistor for LCD driver can be specified by mask option
Timer
5 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels
(can be used as 16-bit timer counter, carrier generator, timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
Clock output (PCL)
16 bits
•
•
Φ, 524, 262, 65.5 kHz (System clock: 4.19 MHz operation)
Φ, 750, 375, 93.8 kHz (System clock: 6.0 MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz (System clock: 4.19 MHz operation)
• 2.93, 5.86, 46.9 kHz (System clock: 6.0 MHz operation)
Notes 1. The µPD75P3216 does not incorporate pull-up resistors by mask option.
2. The µPD75P3216 is not provided with a split resistor by mask option.
User’s Manual U10158EJ2V1UM00
24
CHAPTER 1 GENERAL
(2/2)
Parameter
Vectored interrupts
Test input
Function
External: 2, internal: 5
External: 1, internal: 1
System clock oscillator
Standby function
Power supply voltage
Package
Ceramic or crystal oscillator for system clock oscillation
STOP/HALT modes
VDD = 1.8 to 5.5 V
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
User’s Manual U10158EJ2V1UM00
25
CHAPTER 1 GENERAL
1.2 Ordering Information
Part Number
Package
Internal ROM
µPD753204GT-×××
µPD753206GT-×××
µPD753208GT-×××
µPD75P3216GT
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
Mask ROM
Mask ROM
Mask ROM
One-time PROM
Remark ××× indicates a ROM code suffix.
1.3 Differences among µPD753208 Subseries Products
Item
Program counter
µPD753204
12 bits
µPD753206
13 bits
µPD753208
µPD75P3216
14 bits
Program memory (byte)
Mask ROM
4096
Mask ROM
6144
Mask ROM
8192
One-time PROM
16384
Data memory ( × 4 bits)
512
Mask option
Pull-up
Provided (Incorporated/not incorporated specifiable)
None (Cannot be
incorporated)
resistor of
port 5
17
15
Note
Wait time
at RESET
Provided (2 /fX or 2 /fX selectable)
None (Fixed
15
Note
to 2 /fX)
Split resistor Provided (Incorporated/not incorporated specifiable)
for LCD drive
None (Cannot be
incorporated)
Pin connection
Pins 9-12
Pins 14-17
Pins 18-21
P30-P33
P30/MD0-P33/MD3
P50/D4-P53/D7
P50-P53
P60/KR0-P63/KR3
P60/KR0/D0-P63/
KR3/D3
Pin 25
IC
VPP
Others
Noise immunity and noise radiation differ depending on circuit scale and mask layout.
Note 217/fX: 21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz
215/fX: 5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz
Caution The noise immunity and noise radiation of the PROM model differ from those of the mask ROM
model. If you replace the PROM model with the mask ROM model in the course of experimental
production to mass production, perform thorough evaluation by using the CS model (not ES
model) of the mask ROM model.
User’s Manual U10158EJ2V1UM00
26
4
4
Port0
Port1
Port2
Port3
Port5
Port6
Port8
Port9
4
4
P00-P03
P10-P13
P20-P23
Watch timer
BUZ/P23
CY
SP(8)
SBS
INTW
f
LCD
Program counter
ALU
Basic
interval
timer/
watchdog
timer
4
4
4
4
Bank
4
4
4
4
4
P30-P33
(P30/MD0-P33/MD3)Note 2
INTBT
P50-P53
(P50/D4-P53/D7)Note 2
General reg.
8-bit
timer/event
counter #0
TI0/P13
P60-P63
4
4
PTO0/P20
(P60-D0-P63/D3)Note 2
Program
memoryNote 1
(ROM)
P80-P83
P90-P93
Decode
and
control
INTT0 TOUT
INTT1
Data memory
(RAM)
512×4 bits
4
8-bit timer
Cascaded
16-bit
counter #1
PTO1/P21
LCD
controller/
driver
timer
4
S12-S15
TOUT
8-bit timer
counter #2
counter
PTO2/PCL/P22
S16/P93-
S19/P90
4
4
INTT2
S20/P83-
S23/P80
SI/SB1/P03
Clocked
serial
interface
SO/SB0/P02
SCK/P01
CPU
f
/2N
x
clockΦ
4
COM0-COM3
BIAS
Clock
output
control
INTCSI TOUT0
INT1
Clock
divider
System clock
generator
Standby
control
V
V
V
LC0
LC1
LC2
f
LCD
INT0/P10
INT4/P00
LCDCL/P30
SYNC/P31
Interrupt
control
KR0/P60
-KR3/P63
4
X1
X2
PCL/PTO2/P22
IC
VDD
VSS RESET
Note 2
(VPP
)
Bit seq.
buffer (16)
Notes 1. Capacity of the ROM differs depending on the product.
µ
2. ( ): PD75P3216
CHAPTER 1 GENERAL
1.5 Pin Configuration (Top View)
•
48-pin plastic shrink SOP (375 mil, 0.65 mm pitch)
µPD753204GT-×××, µPD753206GT-×××,
µPD753208GT-×××, µPD75P3216GT
COM0
COM1
COM2
COM3
BAIS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
V
LC0
VLC1
VLC2
P30/LCDCL (/MD0)
P31/SYNC (/MD1)
P32 (/MD2)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P33 (/MD3)
VSS
P50 (/D4)
P51 (/D5)
P52 (/D6)
P53 (/D7)
P60/KR0 (/D0)
P61/KR1 (/D1)
P62/KR2 (/D2)
P63/KR3 (/D3)
V
DD
X1
X2
ICNote (VPP
)
Note Directly connect the IC (Internally Connected) pin to VDD.
Remark ( ): µPD75P3216
User’s Manual U10158EJ2V1UM00
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CHAPTER 1 GENERAL
Pin Names
BIAS
P90-P93
PCL
: Port9
: LCD Power Supply Bias Control
: Buzzer Clock
: Programmable Clock
BUZ
PTO0-PTO2 : Programmable Timer Output 0-2
COM0-COM3 : Common Output 0-3
RESET
S12-S23
SB0, SB1
SCK
: Reset
D0-D7
: Data Bus 0-7
: Internally Connected
: External Vectored Interrupt 0, 4
: Key Return 0-3
: LCD Clock
: Mode selection 0-3
: Port0
: Segment Output 12-23
: Serial Data Bus 0, 1
: Serial Clock
IC
INT0, INT4
KR0-KR3
LCDCL
SI
: Serial Input
SO
: Serial Output
MD0-MD3
P00-P03
P10, P13
P20-P23
P30-P33
P50-P53
P60-P63
P80-P83
SYNC
TI0
: LCD Synchronization
: Timer Input 0
: Port1
VDD
: Positive Power Supply
: LCD Power Supply 0-2
: Programmable Power Supply
: Ground
: Port2
VLC0-VLC2
VPP
: Port3
: Port5
VSS
: Port6
X1, X2
: System Clock Oscillation 1, 2
: Port8
User’s Manual U10158EJ2V1UM00
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[MEMO]
User’s Manual U10158EJ2V1UM00
30
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Functions of µPD753208
Table 2-1. Pin Functions of Digital I/O Ports (1/2)
Alternate
Function
8-bit
I/O
I/O Circuit
TYPE
Pin Name
P00
Input/Output
On Reset
Input
Note 1
Function
Input
INT4
SCK
×
×
×
×
B
4-bit input port (PORT0).
For P01 to P03, internal pull-up
resistors can be connected by
software in 3-bit units.
P01
P02
P03
P10
Input/output
Input/output
Input/output
Input
F -A
F -B
M -C
B -C
SO/SB0
SI/SB1
INT0
Input
Input
Input
2-bit input port (PORT1).
This port can be manipulated bit-wise only.
Internal pull-up resistors can be
connected by software in 2-bit units.
Noise eliminating circuit selectable (P10/INT0).
P13
TI0
P20
P21
P22
P23
P30
Input/output
PTO0
PTO1
E-B
E-B
4-bit input/output port (PORT2).
Internal pull-up resistors can be
connected by software in 4-bit units.
PCL/PTO2
BUZ
Input/output LCDCL (/MD0)Note 2
Programmable 4-bit input/output port
(PORT3).
Note 2
P31
SYNC (/MD1)
This port can be specified input/output
bit-wise.
Note 2
P32
(MD2)
Internal pull-up resistor can be
connected by software in 4-bit units.
Note 2
P33
(MD3)
P50Note 3
P51Note 3
P52Note 3
P53Note 3
Input/output
(D4)Note 2
(D5)Note 2
(D6)Note 2
(D7)Note 2
×
M-D
High level
(when pull-
up resistors
are provided)
or high-
N-ch open-drain 4-bit input/output port
(PORT5). Withstand voltage is 13 V in
open-drain mode.
(M-E)Note 2
A pull-up resistor can be provided bit-
Note 4
wise (mask option)
.
impedance
Notes 1. Circled characters indicate the Schmitt-trigger input.
2. ( ): µPD75P3216
3. If internal pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low level input leakage current increases when input or bit manipulation instruction is executed.
4. The µPD75P3216 does not incorporate pull-up resistors by mask option.
User’s Manual U10158EJ2V1UM00
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CHAPTER 2 PIN FUNCTIONS
Table 2-1. Pin Functions of Digital I/O Ports (2/2)
Alternate
Function
8-bit
I/O
I/O Circuit
Pin Name
P60
Input/Output
Input/output
On Reset
Input
Note 1
Function
TYPE
Note 2
Programmable 4-bit input/output port
(PORT6).
This port can be specified for input/
output bit-wise.
Internal pull-up resistors can be
connected by software in 4-bit units.
KR0(/D0)
KR1(/D1)
KR2(/D2)
KR3(/D3)
S23
×
F -A
Note 2
Note 2
Note 2
P61
P62
P63
P80
P81
P82
P83
P90
P91
P92
P93
Input/output
Input/output
4-bit input/output port (PORT8).
Internal pull-up resistors can be
connected by software in 4-bit
●
Input
Input
H
S22
S21
unitsNote 3
.
S20
S19
H
4-bit input/output port (PORT9).
Internal pull-up resistors can be
connected by software in 4-bit
S18
S17
unitsNote 3
.
S16
Notes 1. Circled characters indicate the Schmitt-trigger input.
2. ( ): µPD75P3216
3. When using these pins to output segment signals, do not connect the internal pull-up resistor to these
pins by software.
User’s Manual U10158EJ2V1UM00
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CHAPTER 2 PIN FUNCTIONS
Table 2-2. Pin Function of Pins Other Than Port Pins (1/2)
Alternate
I/O Circuit
Pin Name
TI0
Input/Output
Function
On Reset
Input
Note 1
Function
TYPE
Input
P13
Inputs external event pulses to the timer/
event counter
B -C
E-B
PTO0
PTO1
PTO2
PCL
Output
P20
P21
Timer/event counter output
Timer counter output
Input
P22/PCL
P22/PTO2
P23
Clock output
BUZ
Optional frequency output (for buzzer or
system clock trimming)
SCK
Input/output
P01
P02
Serial clock input/output
Input
F -A
F -B
SO/SB0
Serial data output
Serial data bus input/output
SI/SB1
INT4
P03
P00
P10
Serial data input
M -C
B
Serial data bus input/output
Input
Input
Edge detection vectored interrupt input (both
rising and falling edge detection)
Input
Input
Edge detection vectored
interrupt input (detection
edge can be selected).
Noise eliminating circuit
selectable.
INT0
With noise
eliminating
circuit/
B -C
asynchronous
selectable
KR0-KR3
S12-S15
Input
P60-P63
–
Falling edge detection testable input
Segment signal output
Input
Note 2
Input
F -A
G-A
H
Output
Output
Output
Output
S16-S19
P93-P90
P83-P80
–
Segment signal output
S20-S23
Segment signal output
Input
H
COM0-COM3
Common signal output
Note 2
G-B
Notes 1. Circled characters indicate the Schmitt trigger input.
2. Each display output selects the following VLCX as input source.
S12-S15: VLC1, COM0-COM2: VLC2, COM3: VLC0.
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CHAPTER 2 PIN FUNCTIONS
Table 2-2. Pin Function of Pins Other Than Port Pins (2/2)
Alternate
I/O Circuit
Pin Name
Input/Output
Function
Power for LCD driver
On Reset
–
Note 1
Function
TYPE
VLC0-VLC2
–
–
–
Internal split resistor is enabled (mask
Note 2
option)
.
BIAS
Output
Output
Output
Input
–
–
Output for external split resistor disconnection
Clock output for externally expanded driver
Clock output for externally expanded driver sync
Note 3
Input
Input
–
–
Note 4
LCDCL
P30
P31
–
E-B
E-B
–
Note 4
SYNC
X1
X2
Crystal/ceramic connection pin for the system
clock oscillator. When inputting the external
clock, input the clock to pin X1, and the
reverse phase of the clock to pin X2.
RESET
Input
Input
–
System reset input (low-level active)
–
B
MD0-MD3
P30-P33
Provided only to µPD75P3216.
Input
E-B
Select modes for writing/verifying program
memory (PROM).
D0-D3
D4-D7
Input/output P60/KR0-P63/KR3 Provided only to µPD75P3216.
Data bus pins when the program memory
(PROM) is written/verified
Input
F -A
M-E
P50-P53
High
impedance
IC
–
–
–
–
Internally connected. Connect directly to VDD.
–
–
–
–
VPP
Provided only to µPD75P3216.
Supplies voltage necessary for writing/
verifying program memory (PROM).
Connect directly to VDD for normal operation.
Apply +12.5 V to this pin to write/verify
PROM.
VDD
VSS
–
–
–
–
Positive power supply
Ground potential
–
–
–
–
Notes 1. Circled characters indicate the Schmitt trigger input.
2. A split resistor is not provided by mask option in the µPD75P3216.
3. When a split resistor is provided ············· Low level
When no split resistor is provided ··········· High impedance
4. These pins are provided for future system expansion. At present, these pins are used only as pins P30
and P31.
User’s Manual U10158EJ2V1UM00
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CHAPTER 2 PIN FUNCTIONS
2.2 Pin Functions
2.2.1 P00-P03 (PORT0) ··· input shared with INT4, SCK, SO/SB0, and SI/SB1
P10, P13 (PORT1) ··· input shared with INT0, and TI0
Port 0 is a 4-bit input port, and port 1 is a 2-bit input port.
Ports 0 and 1 are shared with the following functions, in addition to the input port function:
•
•
Port 0 : Vectored interrupt input (INT4)
Serial interface I/Os (SCK, SO/SB0, SI/SB1)
Port 1 : Vectored interrupt input (INT0)
External event pulse input to timer/event counter (TI0)
Port 0 has an output function depending on the operation mode of the shared pins when using the serial interface
function.
Port 0 can be manipulated in 1- or 4-bit units, and port 1 can be manipulated in 1-bit units only.
Each pin of port 0 and port 1 are Schmitt trigger input pins to prevent malfunctioning due to noise. In addition,
the P10 pin can be selected a noise eliminating circuit (for details, refer to 6.3 (3) Hardware of INT0, and INT4).
Port 0 can be connected with pull-up resistors in 3-bit units (P01-P03) by software. Port 1 can be connected with
on-chip pull-up resistors in 2-bit units (P10, P13). The pull-up resistors can be connected by using pull-up resistor
select register group A (POGA).
When the RESET signal is asserted, all the pins are set in the input mode.
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CHAPTER 2 PIN FUNCTIONS
2.2.2 P20-P23 (PORT2) ··· I/O shared with PTO0-PTO2, PCL, and BUZ
P30-P33 (PORT3) ··· I/O shared with LCDCL , SYNC, and MD0-MD3Note
P50-P53 (PORT5) ··· N-ch open-drain, medium-voltage withstanding (13 V), I/O shared with D4-D7
P60-P63 (PORT6) ··· I/O shared with KR0-KR3 and D0-D3Note
Note
P80-P83 (PORT8) and P90-P93 (PORT9) ··· I/O shared with S23-S20 and S19-S16
4-bit I/O ports with output latch.
In addition to the I/O port function, the following functions are available.
•
•
Port 2
Port 3
: Timer/event counter outputs (PTO0-PTO2)
Clock output (PCL)
Any frequency output (BUZ)
: Clock for driving external expansion LCD driver (LCDCL)
Clock for synchronizing external expansion LCD driver (SYNC)
Mode selection (MD0-MD3)Note when the program memory (PROM) is written/verified
: Data bus (D4-D7)Note when the program memory (PROM) is written/verified
: Key interrupt inputs (KR0-KR3)
•
•
Port 5
Port 6
Data bus (D0-D3)Note when the program memory (PROM) is written/verified
•
Ports 8 and 9 : Segment signal outputs (S23-S20 and S19-S16)
Note µPD75P3216 only
Port 5 is an N-ch open-drain, medium-voltage withstanding (13 V) port.
The input/output mode selection of each port is set by port mode register. Ports 2, 5, 8, and 9 can be set in input
or output mode in 4-bit units, and ports 3 and 6 can be set in input or output mode in 1-bit units.
Ports 2, 3, 6, 8, and 9 can be connected with a internal pull-up resistor in 4-bit units by software, by manipulating
the pull-up resistor specification registers, groups A and B (POGA and POGB). Port 5 can be connected with a pull-
up resistor in 1-bit units by mask option. However, the ports of the µPD75P3216 cannot be connected with a pull-
up resistor by mask option.
Ports 8 and 9 can be set in input or output mode in pairs in 8-bit units. When the RESET signal is asserted, ports
2, 3, 6, 8, and 9 are set in input mode (high-impedance), and port 5 is set at the high-level (when the pull-up resistor
is connected by mask option) or high-impedance state.
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CHAPTER 2 PIN FUNCTIONS
2.2.3 TI0 ··· input shared with port 1
This is the external event pulse input pin of timer/event counter 0.
This pin can be used by selecting the external event pulse input to the count pulse (CP) in the timer/event counter
mode register (TM0).
TI0 is a Schmitt trigger input pin.
For details, refer to 5.5.1 (1) Timer/event counter mode register (TM0, TM1, TM2).
2.2.4 PTO0-PTO2 ··· outputs shared with port 2
These are the output pins of timers/event counter 0 and timer counters 1, 2, and output square wave pulses. To
output the signal of a timer/event counter or timer counter, clear the output latch to “0”, and set the bit corresponding
to port 2 of the port mode register to “1” to set the output mode.
The outputs of these pins are cleared to “0” by the timer start instruction.
For details, refer to 5.5.2 (3) Timer/event counter operation.
2.2.5 PCL ··· output shared with port 2
This is a programmable clock output pin and is used to supply the clock to a peripheral LSI (such as a slave
microcontroller). When the RESET signal is asserted, the contents of the clock output mode register (CLOM) are
cleared to “0”, disabling the output of the clock. In this case, the PCL pin can be used as an ordinary port pin.
For details, refer to 5.2.4 Clock output circuit.
2.2.6 BUZ ··· output shared with port 2
This is a frequency output pin and is used to issue a buzzer sound or trim the system clock frequency by outputting
a specified frequency (2, 4, or 32 kHz). This pin is shared with P23 pin, and is valid only when the bit 7 (WM7) of
the watch mode register (WM) is set to “1”.
When the RESET signal is asserted, WM7 is cleared to “0”, so that the BUZ pin is used as an ordinary port pin.
For details, refer to 5.4.2 Watch mode register.
2.2.7 SCK, SO/SB0, and SI/SB1 ··· 3-state I/Os shared with port 0
These are serial interface I/O pins and operate in accordance with the setting of the serial operation mode register
(CSIM). When the 3-wire serial I/O mode is selected, SCK functions as CMOS I/O, SO, as CMOS output, and SI,
as CMOS input. When the 2-wire serial I/O mode or SBI mode is selected, SCK functions as CMOS I/O, and SB1
(SB0), as N-ch open-drain I/O.
When the RESET signal is asserted, the serial interface operation is stopped, and these pins serve as input port
pins.
All these pins are Schmitt trigger input pins.
For details, 5.6 Serial Interface.
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CHAPTER 2 PIN FUNCTIONS
2.2.8 INT4 ··· input shared with port 0
This is an external vectored interrupt input pin and becomes active at both the rising and falling edges. At the
positive transition of the signal input to this pin, the interrupt request flag is set.
INT4 is an asynchronous input pin and the interrupt is acknowledged when a high- or low-level signal is input to
this pin for a fixed time, regardless of the operating clock of the CPU.
INT4 can also be used to release the STOP and HALT modes. This pin is a Schmitt trigger input pin.
2.2.9 INT0 ··· input shared with port 1
This pin input vectored interrupt signals that are detected by the edge, and can select a noise eliminating circuit.
The edge to be detected can be specified by using the edge detection mode register (IM0).
•
INT0 (bits 0 and 1 of IM0)
(a) Active at rising edge
(b) Active at falling edge
(c) Active at both rising and falling edges
(d) External interrupt signal input disabled
INT0 is an asynchronous input and is accepted regardless of the operating clock of the CPU, if it has a fixed high-
level width. In addition, a noise rejection circuit can be activated by software, and the sampling clock used for noise
rejection can be changed in two steps. In this case, the width of the signal to be accepted differs depending on the
CPU operating clock.
When the RESET signal is asserted, IM0 is cleared to “0”, and the rising edge is selected as the active edge.
INT0 can be used to release the STOP and HALT modes. However, when the noise eliminating circuit is selected,
INT0 cannot be used to release the STOP and HALT modes.
INT0 is a Schmitt trigger input pin.
2.2.10 KR0-KR3 ··· inputs shared with port 6
These are key interrupt input pins, which input interrupt signals that are detected in parallel at falling edge.
The interrupt source can be selected from “KR2 and KR3” or “KR0-KR3” by using the edge detection mode register
(IM2).
When the RESET signal is asserted, these pins serve as port 6 pins and set in input mode.
2.2.11 S12-S23 ··· outputs
These are segment signal output pins that can directly drive the segment pins (front panel electrodes) of an LCD
and perform static and 2- or 3-time division drive of the 1/2 bias method or 3- or 4-time division drive of the 1/3 bias
method.
S16 through S19 and S20 through S23 are shared with ports 9 and 8, respectively, and the modes of these pins
can be selected by using display mode register (LCDM).
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CHAPTER 2 PIN FUNCTIONS
2.2.12 COM0-COM3 ··· outputs
These are common signal output pins that can directly drive the common pins (rear panel electrodes) of an LCD.
They output common signals at static (COM0, 1, 2, and 3 outputs), 2-time division drive of the 1/2 bias method (COM0
and 1 outputs) or 3-time division drive (COM0, 1, and 2 outputs), or 3-time division drive of the 1/3 bias method (COM0,
1, and 2 outputs) or 4-time division drive (COM0, 1, 2, and 3 outputs).
2.2.13 VLC0-VLC2
These are power supply pins to drive an LCD. With the µPD753208, a split resistor can be internally connected
to the VLC0 through VLC2 pins by mask option, so that power to drive the LCD in accordance with each bias method
can be supplied without an external resistor. The µPD75P3216 does not have a mask option and is not provided
with a split resistor.
2.2.14 BIAS
This is an output pin for split resistor cutting. It is connected to the VLC0 pin to supply various types of LCD driving
voltages and is used to change a resistance division ratio, connect an external resistor along with the VLC0 through
VLC2 pins and VSS pin, and fine-tune the LCD driving supply voltage.
2.2.15 LCDCL
This is a clock output pin for driving an external LCD expansion driver.
2.2.16 SYNC
This is a clock output pin to synchronize an external LCD expansion driver.
2.2.17 X1 and X2
These pins connect with a crystal/ceramic oscillator for system clock oscillation.
An external clock can also be input to these pins.
(a) Crystal/ceramic oscillation
(b) External clock
µPD753208
V
DD
µPD753208
External
clock
V
X1
DD
X1
X2
X2
Crystal oscillator
or ceramic oscillator
(4.194304 MHz TYP.)
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CHAPTER 2 PIN FUNCTIONS
2.2.18 RESET
This pin inputs a low-active reset signal.
The RESET signal is an asynchronous input signal and is asserted when a signal with a specific low-level width
is input to this pin regardless of the operating clock. The RESET signal takes precedence over all the other operations.
This pin can not only be used to initialize and start the CPU, but also to release the STOP and HALT modes.
The RESET pin is a Schmitt trigger input pin.
2.2.19 MD0-MD3 (µPD75P3216 only)
These pins are provided to the µPD75P3216 only, and are used to select a mode when the program memory (one-
time PROM) is written or verified.
2.2.20 D0-D7 (µPD75P3216 only)
These pins are provided on the µPD75P3216 only, and are data bus pins when the program memory (one-time
PROM) is written or verified.
2.2.21 IC (µPD753204, 753206, and 753208 only)
The IC (Internally Connected) pin sets a test mode in which theµPD753208 is tested before shipment. It is usually
best to connect the IC pin directly to the VDD pin with as short a wiring length as possible.
If a voltage difference is generated between the IC and VDD pins because the wiring length between the IC and
VDD pins is too long, or because external noise is superimposed on the IC pin, your program may not be correctly
executed.
• Directly connect the IC pin to the VDD pin.
Keep as short as
possible.
V
DD
V
DD
IC
(VPP
)
2.2.22 VPP (µPD75P3216 only)
This pin inputs a program voltage when the program memory (one-time PROM) is written or verified.
It is usually best to connect this pin directly to the VDD (refer to the figure above). Apply 12.5 V to this pin when
the PROM is written or verified.
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CHAPTER 2 PIN FUNCTIONS
2.2.23 VDD
Positive power supply pin.
2.2.24 VSS
GND.
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin Input/Output Circuits
The µPD753208 pin input/output circuits are shown schematically.
(1/3)
TYPE A
TYPE D
VDD
V
DD
Data
P-ch
OUT
P-ch
IN
N-ch
Output
disable
N-ch
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
CMOS specification input buffer.
TYPE E-B
TYPE B
V
DD
P.U.R.
P.U.R.
enable
P-ch
IN
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input having hysteresis characteristic.
P.U.R. : Pull-Up Resistor
TYPE F-A
TYPE B-C
V
DD
VDD
P.U.R.
P-ch
P.U.R.
P.U.R.
enable
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
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CHAPTER 2 PIN FUNCTIONS
(2/3)
TYPE F-B
TYPE H
VDD
P.U.R
P-ch
P.U.R
enable
Output
disable
(P)
IN/OUT
SEG
data
V
DD
TYPE G-A
TYPE E-B
P-ch
IN/OUT
Data
Data
Output
disable
N-ch
Output
disable
Output
disable
(N)
P.U.R : Pull-Up Resistor
TYPE G-A
TYPE M-C
VDD
VLC0
P.U.R
P.U.R.
enable
VLC1
P-ch
IN/OUT
P-ch N-ch
Data
N-ch
OUT
Output
disable
SEG
data
N-ch
VLC2
N-ch
P.U.R : Pull-Up Resistor
TYPE G-B
TYPE M-D
V
DD
P.U.R.
(Mask option)
IN/OUT
V
LC0
LC1
N-ch
(+13 V
Data
V
withstand
voltage)
Output
disable
VDD
P-ch N-ch
Input instruction
P-ch
P.U.R.Note
OUT
Voltage
Iimitation
circuit
COM data
N-ch P-ch
(+13 V withstand voltage)
P.U.R. : Pull-Up Resistor
VLC2
Note Pull-up resistor that operates only when an input
instruction is executed if internal pull-up resistors
are not specified by mask option (When the pin is
at low level, current flows from VDD to the pin).
N-ch
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CHAPTER 2 PIN FUNCTIONS
(3/3)
TYPE M-E
Data
IN/OUT
N-ch
(+13 V
withstand
voltage)
Output
disable
VDD
Input
P-ch
instruction
P.U.R.Note
Voltage
Iimitation
circuit
(+13 V withstand voltage)
Note Pull-up resistor that operates only when an input
instruction is executed (When the pin is at low level,
current flows from VDD to the pin).
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CHAPTER 2 PIN FUNCTIONS
2.4 Recommended Connections for Unused Pins
Table 2-3. List of Recommended Connections for Unused Pins
Pin
Recommended Connection
Connect to VSS or VDD
P00/INT4
P01/SCK
Connect to VSS or VDD individually via resistor
P02/SO/SB0
P03/SI/SB1
P10/INT0
Connect to VSS
Connect to VSS or VDD
P13/TI0
P20/PTO0
Input state : Connect to VSS or VDD individually via
resistor
P21/PTO1
Output state : Leave unconnected
P22/PCL/PTO2
P23/BUZ
Note
P30/LCDCL (/MD0)
Note
P31/SYNC (/MD1)
Note
P32 (/MD2)
Note
P33 (/MD3)
Note
P50 (/D4)
Connect to VSS (Do not connect to pull-up resistor by
mask option.)
Note
P51 (/D5)
Note
P52 (/D6)
Note
P53 (/D7)
Note
P60/KR0 (/D0)
Input state : Connect to VSS or VDD individually via
resistor
Note
P61/KR1 (/D1)
Output state : Leave unconnected
Note
P62/KR2 (/D2)
Note
P63/KR3 (/D3)
S12-S15
Leave unconnected
COM0-COM3
S16/P93-S19/P90
S20/P83-S23/P80
VLC0-VLC2
Input state: Connect to VSS or VDD individually via resistor
Output state: Leave unconnected
Connect to VSS
BIAS
Only if all of VLC0-VLC2 are unused, connect to VSS.
In other cases, leave unconnected.
Note
IC (VPP)
Connect directly to VDD
Note ( ): µPD75P3216 only
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[MEMO]
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
The 75XL architecture employed for the µPD753208 has the following features:
•
•
Internal RAM: 4K words × 4 bits MAX. (12-bit address)
Expandability of peripheral hardware
To realize these superb features, the following methods are employed:
(1) Bank configuration of data memory
(2) Bank configuration of general-purpose registers
(3) Memory-mapped I/O
This chapter describes each of these features.
3.1 Bank Configuration and Addressing Mode of Data Memory
3.1.1 Bank configuration of data memory
The µPD753208 is provided with static RAM at the addresses 000H through 1FFH of the data memory space, of
which a 12 × 4 bit area of addresses 1ECH through 1F7H can also be used as a display data memory. Peripheral
hardware units (such as I/O ports and timers) are allocated to addresses F80H through FFFH.
The µPD753208 employs memory bank configuration that directly or indirectly specifies the low-order 8 bits of an
address by an instruction and the high-order 4 bits of the address by a memory bank when the data memory space
of 12-bit address (4K words × 4 bits) is addressed.
To specify a memory bank (MB), the following hardware units are provided:
•
•
Memory bank enable flag (MBE)
Memory bank select register (MBS)
MBS is a register that selects a memory bank. Memory banks 0, 1, or 15 can be selected. MBE is a flag that
enables or disables the memory bank selected by MBS. When MBE is 0, the specified memory bank (MB) is fixed,
regardless of MBS, as shown in Figure 3-1. When MBE is 1, however, a memory bank is selected according to the
setting of MBS, so that the data memory space can be expanded.
To address the data memory space, MBE is usually set to 1 and the data memory of the memory bank specified
by MBS is manipulated. By selecting a mode of MBE = 0 or a mode of MBE = 1 for each processing of the program,
programming can be efficiently carried out.
Adapted Program Processing
• Interrupt processing
Effect
MBE = 0 mode
MBE = 1 mode
Saving/restoring MBS unnecessary
Changing MBS unnecessary
• Processing repeating internal hardware manipulation
and static RAM manipulation
• Subroutine processing
Saving/restoring MBS unnecessary
• Normal program processing
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-1. Selecting MBE = 0 Mode and MBE = 1 Mode
(Main program)
SET1 MBE
(Subroutine)
CLR1 MBE
MBE
= 1
MBE = 0
CLR1 MBE
Internal hardware
and static RAM
manipulation repeated
RET (Interrupt processing)
MBE
= 0
; MBE = 0 by vector table
SET1 MBE
MBE = 0
MBE
= 1
RETI
Remark Solid line: MBE = 1, dotted line: MBE = 0
Because MBE is automatically saved or restored during subroutine processing, it can be changed even while
subroutine processing is under execution. MBE can also be saved or restored automatically during interrupt
processing, so that during interrupt processing MBE can be specified as soon as the interrupt processing is started,
by setting the interrupt vector table. This feature is useful for high-speed interrupt processing.
To change by using subroutine processing or interrupt processing, save or restore it to stack by using the PUSH
or POP instruction.
MBE is set by using the SET1 or CLR1 instruction. Use the SEL instruction to set MBS.
Examples 1. To clear MBE and fix memory bank
CLR1
MBE
; MBE ← 0
2. To select memory bank 1
SET1
SEL
MBE
MB1
; MBE ← 1
; MBS ← 1
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3.1.2 Addressing mode of data memory
The 75XL architecture employed for the µPD753208 provides the seven types of addressing modes as shown in
Table 3-1, so that the data memory space can be efficiently addressed by the bit length of the data to be processed,
and so that programming can be carried out efficiently.
(1) 1-bit direct addressing (mem.bit)
This mode is for directly addressing each bit of the entire data memory space by using the operand of an
instruction.
The memory bank (MB) to be specified is fixed to 0 in the mode of MBE = 0 if the address specified by the operand
ranges from 00H to 7FH, and to 15 if the address specified by the operand is 80H to FFH. In the mode of MBE
= 0, therefore, both the data area of addresses 000H through 07FH and the peripheral hardware area of F80H
through FFFH can be addressed.
In the mode of MBE = 1, MB = MBS; therefore, the entire data memory space can be addressed.
This addressing mode can be used with four instructions: bit set and reset (SET1 and CLR1) instructions, and
bit test instructions (SKT and SKF).
Example To set FLAG1, reset FLAG2, and test whether FLAG3 is 0
FLAG1
FLAG2
FLAG3
EQU
EQU
EQU
03FH.1
087H.2
0A7H.0
; Bit 1 of address 3FH
; Bit 2 of address 87H
; Bit 3 of address A7H
SET1
SEL
MBE
; MBE ← 1
MB0
; MBS ← 0
SET1
CLR1
SKF
FLAG1
FLAG2
FLAG3
; FLAG1 ← 1
; FLAG2 ← 0
; FLAG3 = 0?
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Figure 3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode
mem
mem. bit
@HL
@H+mem. bit
@DE
Stack
fmem. bit pmem. @L
Addressing Mode
@DL Addressing
Memory bank enable flag
MBE=0 MBE=1 MBE=0 MBE=1
—
—
—
—
0 0 0 H
General-purpose
register area
0 1 F H
0 2 0 H
Data area
0 7 F H
0 8 0 H
MBS
=0
MBS
=0
SBS
=0
Static RAM
(memory bank 0)
0 F F H
1 0 0 H
Data area
Static RAM
(memory bank 1)
1 E B H
1 E C H
MBS
=1
MBS
=1
SBS
=1
Display data
memory
1 F 7 H
1 F 8 H
1 F F H
Not contained
F 8 0 H
F B 0 H
Peripheral hardware area
(memory bank 15)
MBS
=15
MBS
=15
F B F H
F C 0 H
F F 0 H
F F F H
Remark –: don’t care
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Table 3-1. Addressing Mode
Addressing Mode
Identifier
mem.bit
Specified Address
1-bit direct
addressing
Bit of address indicated by MB and mem. The bit is addressed by “bit”.
• When MBE = 0
when mem = 00H-7FH : MB = 0
when mem = 80H-FFH : MB = 15
• When MBE = 1
: MB = MBS
4-bit direct
addressing
mem
Address indicated by MB and mem.
• When MBE = 0
when mem = 00H-7FH : MB = 0
when mem = 80H-FFH : MB = 15
• When MBE = 1
: MB = MBS
8-bit direct
addressing
Address indicated by MB and mem (mem is an even address).
• When MBE = 0
when mem = 00H-7FH : MB = 0
when mem = 80H-FFH : MB = 15
• When MBE = 1
: MB = MBS
4-bit register
@HL
Address indicated by MB and HL. MB = MBE•MBS
indirect addressing
@HL+
@HL–
Address indicated by MB and HL. MB = MBE•MBS
When HL+ is given, L register is automatically incremented after addressing.
When HL– is given, L register is automatically decremented after addressing.
@DE
@DL
@HL
Memory bank 0 address indicated by DE.
Memory bank 0 address indicated by DL.
8-bit register
Address indicated by MB and HL (L register contents are even).
MB = MBE•MBS.
indirect addressing
Bit manipulation
addressing
fmem.bit
pmem.@L
@H+mem.bit
–
Bit of address indicated by fmem. The bit is addressed by “bit”.
fmem = FB0H-FBFH (hardware related to interrupt)
FF0H-FFFH (I/O port)
Bit of address indicated by high-order 10-bit of pmem and high-order 2-bit of
L register. The bit is addressed by low-order 2-bit of L register.
pmem = FC0H-FFFH
Bit of address indicated by MB, H, and low-order 4-bit of mem. The bit is
addressed by “bit”.
MB = MBE•MBS
Stack addressing
The address indicated by SP of memory banks 0 and 1 selected by setting SBS.
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(2) 4-bit direct addressing (mem)
This addressing mode is to directly address the entire memory space in 4-bit units by using the operand of an
instruction.
Like the 1-bit direct addressing mode, the area that can be addressed is fixed to the data area of addresses 000H
through 07FH and the peripheral hardware area of F80H through FFFH in the mode of MBE = 0. In the mode
of MBE = 1, MB = MBS, and the entire data memory space can be addressed.
This addressing mode is applicable to the MOV, XCH, INCS, IN, and OUT instructions.
Caution If data related to I/O ports is stored to the stack RAM in bank 1 as shown in Example 1 below,
the program efficiency is degraded. To program without changing MBS as shown in Example
2, store the data related to I/O ports to the addresses 00H through 7FH of bank 0.
Examples 1. To output data of “BUFF” to port 5
BUFF
EQU
11AH
; “BUFF” is at address 11AH
; MBE ← 1
SET1 MBE
SEL
MOV
SEL
OUT
MB1
; MBS ← 1
A, BUFF
MB15
; A ← (BUFF)
; MBS ← 15
PORT5, A
; PORT5 ← A
2. To input data from port 5 and store it to “DATA1”
DATA1 EQU
5FH
; “DATA1” is at address 5FH
; MBE ← 0
CLR1 MBE
IN
A, PORT5
DATA1, A
; A ← PORT5
MOV
; (DATA1) ← A
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(3) 8-bit direct addressing (mem)
This addressing mode is for directly addressing the entire data memory space in 8-bit units by using the operand
of an instruction.
The address that can be specified by the operand is an even address. The 4-bit data of the address specified
by the operand and the 4-bit data of the the address high-order than the specified address are used in pairs and
processed in 8-bit units by the 8-bit accumulator (XA register pair).
The memory bank that is addressed is the same as that addressed in the 4-bit direct addressing mode.
This addressing mode is applicable to the MOV, XCH, IN, and OUT instructions.
Examples 1. To transfer the 8-bit data of ports 8 and 9 to addresses 20H and 21
DATA
EQU
020H
CLR1 MBE
; MBE ← 0
XA, PORT8 ; X ← port 9, A ← port 8
DATA, XA ; (21H) ← X, (20H) ← A
IN
MOV
2. To load the 8-bit data input to the shift register (SIO) of the serial interface and, at the same
time, set transfer data to instruct the start of transfer
SEL
MB15
; MBS ← 15
; XA ↔ (SIO)
XCH
XA, SIO
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(4) 4-bit register indirect addressing (@rpa)
This addressing mode is for indirectly addressing the data memory space in 4-bit units by using a data pointer
(a pair of general-purpose registers) specified by the operand of an instruction.
As the data pointer, three register pairs can be specified: HL that can address the entire data memory space
by using MBE and MBS, and DE and DL that always address memory bank 0, regardless of the specification
by MBE and MBS. By selecting a register pair depending on the data memory bank to be used, programming
can be carried out efficiently.
Example To transfer data 50H through 57H to addresses 110H through 117H
DATA1
DATA2
EQU
EQU
SET1
SEL
57H
117H
MBE
MB1
MOV
MOV
MOV
XCH
DECS
BR
D, #DATA1 SHR 4
HL, #DATA2 AND 0FFH ; HL ← 17H
LOOP:
A, @DL
A, @HL
L
; A ← (DL)
; A ← (HL)
; L ← L – 1
LOOP
The addressing mode that uses register pair HL as the data pointer is widely used to transfer, operate, compare,
and input/output data. The addressing mode using register pair DE or DL is used with the MOV and XCH
instructions.
By using this addressing mode in combination with the increment/decrement instruction of a general-purpose
register or a register pair, the addresses of the data memory can be updated as shown in Figure 3-3.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Examples 1. To compare data 50H through 57H with data 110H through 117H
DATA1 EQU
DATA2 EQU
57H
117H
SET1 MBE
SEL
MOV
MB1
D, #DATA1 SHR 4
HL, #DATA2 AND 0FFH
A, @DL
MOV
LOOP: MOV
SKE
A, @HL
NO
; A = (HL)?
; NO
BR
DECS
L
; YES, L ← L – 1
BR
LOOP
2. To clear data memory of 00H through FFH
CLR1 RBE
CLR1 MBE
MOV
XA, #00H
HL, #04H
@HL, A
L
MOV
LOOP: MOV
; (HL) ← A
; L ← L+1
INCS
BR
LOOP
H
INCS
BR
; H ← H+1
LOOP
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-3. Static RAM Address Update Method
X0H
XFH
0XH
DECS D
DECS D
DECS E
INCS E
@DL
4-bit transfer
@DE
4-bit transfer
DECS L
INCS L
DECS DE
INCS DE
INCS D
INCS D
Direct
addressing bit
manipulation
4-bit transfer
8-bit transfer
DECS H
DECS H
Auto decrement
DECS L
Auto increment
INCS L
@HL
4-bit manipulation
8-bit manipulation
@H+mem. bit
Bit manipulation
DECS HL
INCS HL
INCS H
INCS H
FXH
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(5) 8-bit register indirect addressing (@HL)
This addressing mode is to indirectly address the entire data memory space in 8-bit units by using a data pointer
(HL register pair).
In this addressing mode, data is processed in 8-bit units, that is, the 4-bit data at an address specified by the
data pointer with bit 0 (bit 0 of the L register) cleared to 0 and the 4-bit data at the address high-order are used
in pairs and processed with the data of the 8-bit accumulator (XA register).
The memory bank is specified in the same manner as when the HL register is specified in the 4-bit register indirect
addressing mode, by using MBE and MBS. This addressing mode is applicable to the MOV, XCH, and SKE
instructions.
Examples 1. To compare whether the count register (T0) value of timer/event counter 0 is equal to the data
at addresses 30H and 31H
DATA
EQU
30H
CLR1 MBE
MOV
MOV
SKE
BR
HL, #DATA
XA, T0
A, @HL
NO
; XA ← count register 0
; A = (HL)?
INCS
MOV
SKE
L
A, X
; A ← X
A, @HL
; A = (HL)?
2. To clear data memory at 00H through FFH
CLR1 RBE
CLR1 MBE
MOV
XA, #00H
HL, #04H
@HL, XA
L
MOV
LOOP: MOV
; (HL) ← XA
INCS
BR
LOOP
H
INCS
BR
LOOP
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(6) Bit manipulation addressing
This addressing mode is used to manipulate the entire memory space in bit units (such as Boolean processing
and bit transfer).
While the 1-bit direct addressing mode can be only used with the instructions that set, reset, or test a bit, this
addressing mode can be used in various ways, such as Boolean processing by the AND1, OR1, and XOR1
instructions, and test and reset by the SKTCLR instruction.
Bit manipulation addressing can be implemented in the following three ways, which can be selected depending
on the data memory address to be used.
(a) Specific address bit direct addressing (fmem.bit)
This addressing mode is to manipulate the hardware units that use bit manipulation especially often, such
as I/O ports and interrupt-related flags, regardless of the setting of the memory bank. Therefore, the data
memory addresses to which this addressing mode is applicable are FF0H through FF9H, to which the I/O
ports are mapped, and FB0H through FBH, to which the interrupt-related hardware units are mapped. The
hardware units in these two data memory areas can be manipulated in bit units at any time in the direct
addressing mode, regardless of the setting of MBS and MBE.
Example 1. To test timer 0 interrupt request flag (IRQT0) and, if it is set, clear the flag and reset P63
SKTCLR
BR
IRQT0
NO
; IRQT0 = 1?
; NO
CLR1
PORT6.3
; YES
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Example 2. To reset P53 if both P30 and P51 pins are 1
P30
P53
P31
(i)
SET1
AND1
AND1
SKT
CY
; CY ← 1
CY, PORT3.0 ; CY ^ P30
CY, PORT5.1 ; CY ^ P51
CY
; CY = 1?
; P53 ← 0
; P53 ← 1
BR
STEP
PORT5.3
CLR1
.
.
.
SETP: SET1
PORT5.3
.
.
.
(ii)
SKT
BR
PORT3.0
SETP
; P30 = 1?
; P51 = 1?
; P53 ← 0
; P53 ←1
SKT
BR
PORT5.1
SETP
CLR1
PORT5.3
.
.
.
SETP: SET1
PORT5.3
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(b) Specific address bit register indirect addressing (pmem, @L)
This addressing mode is used to indirectly specify and successively manipulate the bits of the peripheral
hardware units, such as I/O ports. The data memory addresses to which this addressing mode can be applied
are FC0H through FFFH.
This addressing mode specifies the high-order 10 bits of a data memory address directly by using an operand,
and the low-order 2 bits by using the L register. Therefore, 16 bits (4 ports) can be successively manipulated
depending on the specification of the L register.
This addressing mode can also be used independently of the setting of MBE and MBS.
Example To output pulses to the respective bits of ports 8 and 9
P80
P81
to
P93
LOOP2: MOV
L, #0
LOOP1: SET1
PORT8.@L
PORT8.@L
L
; Bits of ports 8 and 9 (L1-0) ← 1
; Bits of ports 8 and 9 (L1-0) ← 0
CLR1
INCS
NOP
SKE
BR
L, #08H
LOOP1
LOOP2
BR
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(c) Special 1-bit direct addressing (@H+mem, bit)
This addressing mode enables bit manipulation in the entire memory space.
The high-order 4 bits of the data memory address of the memory bank specified by MBE and MBS are
indirectly specified by the H register, and the low-order 4 bits and the bit address are directly specified by
the operand. This addressing mode can be used to manipulate the respective bits of the entire data memory
area in various ways.
Example To reset bit 2 (FLAG3) at address 32H if both bits 3 (FLAG1) at address 30H and bit 0 (FLAG2)
at address 31H are 0 or 1
FLAG1
FLAG3
FLAG2
FLAG1
FLAG2
FLAG3
EQU
EQU
EQU
SEL
30H.3
31H.0
32H.2
MB0
MOV
CLR1
OR1
H, #FLAG1 SHR 6
CY
; CY ← 0
CY, @H+FLAG1
CY, @H+FLAG2
@H+FLAG3
CY
; CY ← CY v FLAG1
; CY ← CY v FLAG2
; FLAG3 ← 1
XOR1
SET1
SKT
; CY = 1?
CLR1
@H+FLAG3
; FLAG3 ← 0
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(7) Stack addressing
This addressing mode is used to save or restore data when interrupt processing or subroutine processing is
executed.
The address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode.
This addressing is also used to save or restore register contents by using the PUSH or POP instruction, in addition
to during interrupt processing or subroutine processing.
Examples 1. To save or restore register contents during subroutine processing
SUB:
PUSH XA
PUSH HL
PUSH BS
; Saves MBS and RBS
.
.
.
POP
POP
POP
RET
BS
HL
XA
2. To transfer contents of register pair HL to register pair DE
PUSH HL
POP
DE
; DE ← HL
3. To branch to address specified by registers [XABC]
PUSH BC
PUSH XA
RET
; To branch address XABC
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3.2 Bank Configuration of General-Purpose Registers
The µPD753208 is provided with four register banks with each bank consisting of eight general-purpose registers:
X, A, B, C, D, E, H, and L. The general-purpose register area consisting of these registers is mapped to the addresses
00H through 1FH of memory bank 0 (refer to Figure 3-5). To specify a general-purpose register bank, a register bank
enable flag (RBE) and a register bank select register (RBS) are provided. RBS selects a register bank, and RBE
determines whether the register bank selected by RBS is valid or not. The register bank (RB) that is enabled when
an instruction is executed is as follows:
RB = RBE·RBS
Table 3-2. Register Bank Selected by RBE and RBS
RBS
RBE
Register Bank
3
0
0
2
0
0
1
×
0
0
1
1
0
×
0
1
0
1
0
1
Fixed to bank 0
Bank 0 selection
Bank 1 selection
Bank 2 selection
Bank 3 selection
Fixed to 0
Remark × = don’t care
RBE is automatically saved or restored during subroutine processing, and therefore can be set while subroutine
processing is under execution. When interrupt processing is executed, RBE is automatically saved or restored, and
RBE can be set during interrupt processing depending on the setting of the interrupt vector table as soon as the
interrupt processing is started. Consequently, if different register banks are used for normal processing and interrupt
processing as shown in Table 3-3, it is not necessary to save or restore general-purpose registers when an interrupt
is processed, and only RBS needs to be saved or restored if two interrupts are nested, so that the interrupt processing
speed can be increased.
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Table 3-3. Example of Using Different Register Banks for Normal Routine and Interrupt Routine
Normal processing
Uses register banks 2 or 3 with RBE = 1
Uses register bank 0 with RBE = 0
Single interrupt processing
Nesting processing of two interrupts
Uses register bank 1 with RBE = 1 (at this time, RBS must be saved or
restored)
Nesting processing of three or more interrupts
Registers must be saved or restored by PUSH or POP instructions
Figure 3-4. Example of Using Register Banks
<Main program>
SET1 RBE
SEL RB2
<Single interrupt> <Nesting of two interrupts> <Nesting of three interrupts>
; RBE = 0
; RBE = 1
; RBE = 0
in vector table
in vector table
in vector table
PUSH BS
PUSH rp
SEL RB1
RB = 2
RB = 0
RB = 1
RB = 0
POP BS
RETI
POP rp
RETI
RETI
If RBS is to be changed in the course of subroutine processing or interrupt processing, it must be saved or restored
by using the PUSH or POP instruction.
RBE is set by using the SET1 or CLR1 instruction. RBS is set by using the SEL instruction.
Example SET1
RBE
RBE
RB0
RB3
; RBE ← 1
; RBE ← 0
; RBS ← 0
; RBS ← 3
CLR1
SEL
SEL
The general-purpose register area provided to the µPD753208 can be used not only as 4-bit registers, but also
as 8-bit register pairs. This feature allows the µPD753208 to provide transfer, operation, comparison, and increment/
decrement instructions comparable to those of 8-bit microcomputers and allows you to program mainly with general-
purpose registers.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
(1) To use as 4-bit registers
When the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers,
X, A, B, C, D, E, H, and L, specified by RBE and RBS can be used as shown in Figure 3-5. Of these registers,
A plays a central role in transferring, operating, and comparing 4-bit data as a 4-bit accumulator. The other
registers can transfer, compare, and increment or decrement data with the accumulator.
(2) To use as 8-bit registers
When the general-purpose register area is used as an 8-bit register area, a total of eight 8-bit register pairs can
be used as shown in Figure 3-6: register pairs XA, BC, DE, and HL of a register bank specified by RBE and RBS,
and register pairs XA’, BC’, DE’, and HL’ of the register bank whose bit 0 is complemented in respect to the register
bank (RB). Of these register pairs, XA serves as an 8-bit accumulator, playing the central role in transferring,
operating, and comparing 8-bit data. The other register pairs can transfer, compare, and increment or decrement
data with the accumulator. The HL register pair is mainly used as a data pointer. The DE and DL register pairs
are also used as auxiliary data pointers.
Examples 1. INCS
HL
; Skips if HL ← HL+1, HL=00H
; Skips if XA ← XA+BC, carry
; DE’ ← DE’ – XA – CY
; XA ← XA’
ADDS
SUBC
MOV
XA, BC
DE’, XA
XA, XA’
XA, @PCDE
XA, BC
MOVT
SKE
; XA ← (PC12-8+DE)ROM, table reference
; Skips if XA = BC
2. To test whether the value of the count register (T0) of timer/event counter is greater than the
value of register pair BC’ and, if not, wait until it becomes greater
CLR
MBE
NO: MOV
XA, T0
; Reads count register
; XA ≥ BC, ?
; YES
SUBS XA, BC’
BR
BR
YES
NO
; NO
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-5. General-Purpose Register Configuration (for 4-bit operation)
X
A
01H
03H
05H
07H
09H
0BH
0DH
0FH
00H
02H
04H
06H
08H
0AH
0CH
0EH
H
D
L
Register bank 0
(RBE · RBS = 0)
E
B
X
H
D
C
A
L
Register bank 1
(RBE · RBS = 1)
E
B
X
C
A
11H
13H
15H
17H
10H
12H
14H
16H
H
D
B
L
E
C
Register bank 2
(RBE · RBS = 2)
X
H
D
B
A
L
19H
1BH
1DH
1FH
18H
1AH
1CH
1EH
Register bank 3
(RBE · RBS = 3)
E
C
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-6. General-Purpose Register Configuration (for 8-bit operation)
XA
XA'
00H
02H
00H
02H
HL
DE
BC
HL'
DE'
BC'
04H
06H
04H
06H
When
When
RBE · RBS = 0
RBE · RBS = 1
XA'
HL'
DE'
XA
HL
DE
08H
0AH
08H
0AH
0CH
0EH
0CH
0EH
BC'
BC
XA
HL
XA'
HL'
DE'
BC'
XA
HL
10H
12H
10H
12H
DE
BC
XA'
HL'
DE'
BC'
14H
16H
14H
16H
When
RBE · RBS = 2
When
RBE · RBS = 3
18H
1AH
18H
1AH
DE
BC
1CH
1EH
1CH
1EH
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
3.3 Memory-Mapped I/O
The µPD753208 employs memory-mapped I/O where peripheral hardware such as the input/output ports and
timers are mapped in data memory space addresses F80H-FFFH, as shown in Figure 3-2. Thus, special instructions
to control the peripheral hardware are not provided and memory manipulation instructions are all used to control the
peripheral hardware (Some hardware control mnemonics are provided for easy understanding of programs).
To manipulate the peripheral hardware, the addressing modes listed in Table 3-4 can be used.
The display data memory mapped in addresses 1ECH-1F7H is manipulated by specifying memory bank 1.
Table 3-4. Addressing Modes Applicable to Operating the Peripheral Hardware
Applicable Addressing Mode
Applicable Hardware
Bit manipulation
Specified by a direct addressing mem.bit with
MBE = 0 or (MBE = 1, MBS = 15).
All the hardware for which bit
manipulation is possible
Specified by direct addressing fmem.bit regardless
of MBE and MBS.
IST1, IST0, MBE, RBE
IEXXX, IRQXXX, PORTn.X
Specified by indirect addressing pmem.@L
regardless of MBE and MBS.
BSBn.X
PORTn.X
4-bit manipulation
8-bit manipulation
Specified by direct addressing mem with MBE = 0
or (MBE = 1, MBS = 15).
All the hardware for which 4-bit
manipulation is possible
Specified by register indirect addressing @HL with
(MBE = 1, MBS = 15).
Specified by direct addressing mem with MBE = 0
or (MBE = 1, MBS = 15). Note that mem must be an
even-number address.
All the hardware for which 8-bit
manipulation is possible
Specified by register indirect addressing @HL with
(MBE = 1, MBS = 15). Note that the contents of
the L register are an even number.
Example CLR1
MBE
TM0.3
IE0
; MBE = 0
SET1
EI
; Starts timer 0
; Enables INT0
DI
IET1
IRQ2
; Disables INTT1
SKTCLR
SET1
; Tests and clears INT2 request flag
PORT5.@L ; Sets port 5
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
The I/O map of the µPD753208 is shown in Figure 3-7.
The meanings of the items in Figure 3-7 are as follows.
•
•
Hardware name ····· A name indicating the address of on-chip hardware. Can be written in the operand
(symbol) column of instruction.
R/W ························ Indicates whether the given hardware is read/write enabled or not.
R/W : read/write enabled
R
: read only
: write only
W
•
Number of bits ············ Indicates the number of bits in which the hardware device can be manipulated.
that can be mani-
pulated
● : Bit manipulation is possible in the unit (1/4/8 bits) used in the column.
▲ : A part of bits can be manipulated. Refer to “Remarks” for the bits that can be
manipulated.
–
: Bit manipulation is impossible in the unit (1/4/8 bits) used in the column.
•
Bit manipulation ·········· Indicates the usable bit manipulation addressing when bit manipulation is performed
addressing on the hardware.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD753208 I/O Map (1/5)
Number of Bits that
Can Be Manipulated
Hardware Name (Symbol)
Bit
Address
F80H
R/W
R/W
Manipulation
Addressing
Remarks
b3
b2
b1
b0
1-bit 4-bit 8-bit
Stack pointer (SP)
–
–
●
●
–
–
Bit 0 is fixed to 0
Register bank selection register (RBS)
F82H
F83H
F84H
F85H
F86H
R
–
–
●
●
●
●
–
Note 1
................................................................................
Bank selection register (BS)
................................................................................
Memory bank selection register (MBS)
Stack bank selection register (SBS)
R/W
W
–
–
–
–
mem.bit
–
Basic interval timer mode register (BTM)
Basic interval timer (BT)
▲
–
Bit manipulation can be performed only on bit 3
R
●
F88H
Modulo register for setting timer counter high R/W
level (TMOD2H)
–
–
●
–
F8BH
F8CH
WDTMNote 2
W
▲
–
–
–
mem.bit
mem.bit
Bit manipulation can be performed only on bit 3
Bit manipulation can be performed only on bit 3
Display mode register (LCDM)
R/W ▲ (W)
●
–
–
F8EH
F8FH
Display control register (LCDC)
LCD/port selection register (LPS)
R/W
R/W
–
–
●
●
–
–
–
–
Notes 1. The manipulation is possible separately with RBS and MBS in the 4-bit manipulation.
The manipulation is possible with BS in the 8-bit manipulation.
Write data in the MBS and RBS with the SEL MBn and SEL RBn instructions.
2. WDTM: Watchdog Timer Enable flag (W); Cannot be cleared, once set, by an instruction.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD753208 I/O Map (2/5)
Number of Bits that
Can Be Manipulated
Hardware Name (Symbol)
Bit
Address
F90H
R/W
Manipulation
Addressing
Remarks
b3
b2
b1
b0
1-bit 4-bit 8-bit
Timer counter 2 mode register (TM2)
R/W ▲ (W)
–
–
●
●
●
●
●
–
–
–
Bit manipulation can be performed only on bit 3
–
TOE2
REMC
NRZB
NRZ
F92H
F94H
F96H
F98H
R/W
R
●
▲
–
●
–
Bit 3 can be written only
................................................................................
Timer counter 2 control register (TC2)
................................................................................
Bit manipulation can be performed only on bit 3
TGCE
–
–
–
Timer counter 2 count register (T2)
–
–
–
–
Timer counter 2 modulo register (TMOD2)
Watch mode register (WM)
R/W
R/W
–
–
–
–
–
–
Bit 6 is fixed to 0.
FA0H
Timer/event counter 0 mode register (TM0)
R/W ▲ (W)
–
–
–
–
●
mem.bit
Bit manipulation can be performed only on bit 3
–
–
mem.bit
–
Note 1
FA2H
FA4H
TOE0
W
R
●
–
Timer/event counter 0 count register (T0)
–
●
FA6H
FA8H
Timer/event counter 0 modulo register
(TMOD0)
R/W
–
–
●
●
–
Timer counter 1 mode register (TM1)
R/W ▲ (W)
–
–
–
–
mem.bit
Bit manipulation can be performed only on bit 3
–
–
mem.bit
–
Note 2
FAAH
FACH
TOE1
W
R
●
–
Timer counter 1 count register (T1)
–
●
FAEH
Timer counter 1 modulo register (TMOD1)
R/W
–
–
●
–
Notes 1. TOE0: Timer/event counter output enable flag (channel 0) (W)
2. TOE1: Timer counter output enable flag (channel 1) (W)
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD753208 I/O Map (3/5)
Number of Bits that
Can Be Manipulated
Hardware Name (Symbol)
Bit
Address
FB0H
R/W
R/W
Manipulation
Addressing
Remarks
b3
b2
b1
b0
1-bit 4-bit 8-bit
IST1
IST0
MBE
RBE
●
(R/W)
●
(R/W)
●
(R)
–
fmem.bit
8-bit manipulation is read only
................................................................................
Program status word (PSW)
................................................................................
Note 2
▲
–
CYNote 1 SK2Note 1 SK1Note 1 SK0Note 1
FB2H
FB3H
FB4H
FB6H
Interrupt priority selection register (IPS)
R/W
R/W
R/W
R/W
–
–
●
●
●
●
●
●
●
●
●
●
Note 3
Note 4
Processor clock control register (PCC)
INT0 edge detection mode register (IM0)
–
–
–
–
INT2 edge deection mode register (IM2)
INTA register (INTA)
–
Bit manipulation can be performed only on bits 0, 1
FB8H ................................................................................ R/W
●
●
●
●
●
●
–
–
–
fmem.bit
IE4
IRQ4
IEBT
IRQBT
INTC register (INTC)
................................................................................
FBAH
FBCH
FBDH
FBEH
FBFH
R/W
R/W
R/W
R/W
R/W
IEW
IRQW
INTE register (INTE)
................................................................................
IET1
IRQT1
IET0
IRQT0
INTF register (INTF)
................................................................................
IET2
IRQT2
IECSI
IRQCSI
INTG register (INTG)
................................................................................
IE0
IRQ0
INTH register (INTH)
................................................................................
IE2
IRQ2
FC0H
FC1H
FC2H
FC3H
Bit sequential buffer 0 (BSB0)
Bit sequential buffer 1 (BSB1)
Bit sequential buffer 2 (BSB2)
Bit sequential buffer 3 (BSB3)
R/W
R/W
R/W
R/W
●
●
●
●
●
●
●
●
●
●
mem.bit
pmem.@L
Remarks 1. IEXXX : Interrupt enable flag
2. IRQXXX: Interrupt request flag
Notes 1. These are not registered as reserved words.
2. Write data in the CY with the CY manipulation instruction.
3. Manipulation can be performed by the EI/DI instruction only for bit 3
4. Bit manipulation can be performed on bits 3 and 2 when the STOP/HALT instructions are executed.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD753208 I/O Map (4/5)
Number of Bits that
Can Be Manipulated
Hardware Name (Symbol)
Bit
Address
R/W
Manipulation
Addressing
Remarks
b3
b2
b1
b0
1-bit 4-bit 8-bit
FD0H
FDCH
Clock output mode register (CLOM)
R/W
R/W
–
–
●
–
–
–
Pull-up resistor specification register
group A (POGA)
–
●
FDEH
Pull-up resistor specification register
group B (POGB)
R/W
–
–
●
–
FE0H
FE2H
FE4H
FE6H
FE8H
FECH
FEEH
Serial operation mode register (CSIM)
...........................................................
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
–
–
–
●
–
–
Note
▲
(R)(W)
CSIE
COI
WUP
mem.bit
mem.bit
CMDD
RELD
CMDT
RELT
................................................................................
●
–
–
–
–
–
R/W depends on the bit number
SBI control register (SBIC)
................................................................................
BSYE
ACKD
ACKE
ACKT
Serial I/O shift register (SIO)
–
–
–
–
–
●
●
●
●
●
–
–
–
–
–
Slave address register (SVA)
Note 2
Note 2
Note 2
Note 2
PM33
PM32
PM31
PM30
................................................................................
Port mode register group A (PMGA)
................................................................................
Note 2
Note 2
Note 2
Note 2
PM63
PM62
PM61
PM60
Note 2
PM2
–
–
–
................................................................................
Port mode register group B (PMGB)
................................................................................
Note 2
–
–
–
–
PM5
–
Note 2
Note 2
PM8
PM9
................................................................................
Port mode register group C (PMGC)
................................................................................
–
–
–
–
Notes 1. For the 1-bit manipulation, R/W depends on the bit number.
2. These are not registered as reserved words.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD753208 I/O Map (5/5)
Number of Bits that
Can Be Manipulated
Hardware Name (Symbol)
Bit
Address
R/W
Manipulation
Addressing
Remarks
b3
b2
b1
b0
1-bit 4-bit 8-bit
FF0H
FF1H
FF2H
FF3H
FF5H
Port 0
Port 1
Port 2
Port 3
Port 5
KR3
(PORT0)
(PORT1)
R
R
●
●
●
●
●
●
–
–
–
–
(PORT2) R/W
(PORT3) R/W
(PORT5) R/W
KR0
●
●
●
–
–
KR2
KR1
................................................................................
FF6H
R/W
●
●
Port 6
Port 8
Port 9
(PORT6)
FF8H
FF9H
(PORT8) R/W
(PORT9) R/W
●
●
●
●
●
fmem.bit
pmem.@L
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CHAPTER 4 INTERNAL CPU FUNCTIONS
4.1 Switching Function between Mk I Mode and Mk II Mode
4.1.1 Difference between Mk I and Mk II modes
The CPU of µPD753208 has the following two modes: Mk I and Mk II, either of which can be selected. The mode
can be switched by the bit 3 of the Stack Bank Select register (SBS).
•
•
Mk I mode : Upward compatible with µPD75308B.
Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.
Mk II mode : Incompatible with µPD75308B.
Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than
16K bytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode
Mk II Mode
Number of stack bytes
2 bytes
3 bytes
for subroutine instructions
BRA !addr1 instruction
Not available
Available
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
3 machine cycles
2 machine cycles
4 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area of the 75X and 75XL series exceeding 16K bytes.
This mode improves the software compatibility with products with a program area of
more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes (area used) increases 1 byte,
as compared with the Mk I mode, when a subroutine call instruction is executed. When
the CALL !addr or CALLF !faddr instruction is used, the machine cycle is extended by
1 machine cycle. Therefore, use the Mk I mode when the emphasis is placed on the use
efficiency of the RAM and processing capability more than software compatibility.
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CHAPTER 4 INTERNAL CPU FUNCTIONS
4.1.2 Setting method of stack bank select register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 100XBNote at the beginning of a program. When using
the Mk II mode, it must be initialized to 000XBNote
Note The desired numbers must be set in the X positions.
Figure 4-1. Stack Bank Select Register Format
.
3
2
1
0
Address
F84H
Symbol
SBS
SBS3 SBS2 SBS1 SBS0
Stack area specification
0
0
0
1
Memory bank 0
Memory bank 1
Other than above setting prohibited
0 must be set in the bit 2 position.
0
Mode switching specification
0
1
Mk II mode
Mk I mode
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.
When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.
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CHAPTER 4 INTERNAL CPU FUNCTIONS
4.2 Program Counter (PC) ····· 12-bit (µPD753204)
13-bit (µPD753206, 753208)
14-bit (µPD75P3216)
This is a binary counter that holds an address of the program memory.
Figure 4-2. Program Counter Structure
(a) µPD753204
PC11 PC10
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC9
(b) µPD753206, 753208
PC12 PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(c) µPD75P3216
PC13 PC12 PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
The value of the program counter (PC) is usually automatically incremented by the number of bytes of an instruction
each time an instruction has been executed.
When a branch instruction (BR, BRA, or BRCB) is executed, immediate data indicating the branch destination
address or the contents of a register pair are loaded to all or some bits of the PC.
When a subroutine call instruction (CALL, CALLA, or CALLF) is executed or when a vector interrupt occurs, the
contents of the PC (a return address already incremented to fetch the next instruction) are saved to the stack memory
(data memory specified by the stack pointer) and then the jump destination address is loaded to the PC.
When the return instruction (RET, RETS, or RETI) instruction is executed, the contents of the stack memory are
set to the PC.
With the µPD753204, the contents of the low-order 4 bits of address 0000H of the program memory are loaded
to bits PC11 through PC8, and the contents of address 0001H are loaded to PC7 through PC0 when the RESET signal
is asserted. Therefore, the program can be started from any address.
With the µPD753206 and 753208, the contents of the low-order 5 bits of program memory address 0000H are
loaded to PC12 through PC8, and the contents of address 0001H are loaded to PC7 through PC0 when the RESET
signal is asserted.
With the µPD75P3216, the contents of the low-order 6 bits of program memory address 0000H are loaded to PC13
through PC8 and the contents of address 0001H are loaded to PC7 through PC0 when the RESET signal is asserted.
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CHAPTER 4 INTERNAL CPU FUNCTIONS
4.3 Program Memory (ROM) ····· 4096 × 8 bits (µPD753204)
6144 × 8 bits (µPD753206)
8192 × 8 bits (µPD753208)
16384 × 8 bits (µPD75P3216)
The program memory is provided to store the programs, interrupt vector table, reference table of the GETI
instruction, and table data.
It is addressed by the program counter. Table data can be referenced by the Table Reference instruction (MOVT).
The range of addresses to which branches can be taken by a Branch instruction and Subroutine Call instruction
is shown in Figure 4-3. A branch can take place to address (contents of PC–15 to –1, +2 to +16) by a Relative Branch
instruction (BR $addr instruction).
The address range of the program memory of each model is as follows:
•
•
•
•
000H-FFFH : µPD753204
0000H-17FFH : µPD753206
0000H-1FFFH: µPD753208
0000H-3FFFH: µPD75P3216
Special functions are assigned to the following addresses. All the addresses other than 0000H and 0001H can
be usually used as program memory addresses.
•
•
•
Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
Addresses 0002H-000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts
are written. Interrupt execution can be started at an arbitrary address.
Addresses 0020H-007FH
Table area referenced by the GETI instructionNote
.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps (11.1.1 GETI
instruction).
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CHAPTER 4 INTERNAL CPU FUNCTIONS
Figure 4-3. Program Memory Map (1/4)
(a) µPD753204
Address
7
6
5
0
4
0
0
0 0 0 H MBE RBE
0 0 2 H MBE RBE
0 0 4 H MBE RBE
Internal reset start address
Internal reset start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
0
0
0
0
INTBT/INT4
INTBT/INT4
start address
start address
INT0
INT0
start address
start address
CALLF
! faddr
instruction
entry
address
0 0 6 H
Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1 Note
or CALLA !addr1 Note
instruction
0 0 8 H MBE RBE
0 0 A H MBE RBE
0 0 C H MBE RBE
0
0
0
0
0
0
INTCSI
start address
start address
start address
start address
start address
start address
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
CALL !addr instruction
subroutine entry address
INTCSI
INTT0
BR $addr instruction
relative branch address
INTT0
–15 to –1,
+2 to +16
INTT1/INTT2
INTT1/INTT2
BRCB
!caddr instruction
branch address
0 2 0 H
GETI instruction reference table
0 7 F H
0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
7 F F H
8 0 0 H
F F F H
Note Can be used only in the MkII mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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Figure 4-3. Program Memory Map (2/4)
(b) µPD753206
Address
7
6
5
0
0
0 0 0 0 H
MBE RBE
Internal reset start address
Internal reset start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0
0
INTBT/INT4
INTBT/INT4
INT0
start address
start address
start address
start address
(low-order 8 bits)
(high-order 5 bits)
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
instruction
INT0
(low-order 8 bits)
CALLF
! faddr
instruction
entry
0 0 0 6 H
address
CALL ! addr
instruction
0 0 0 8 H MBE RBE
0
INTCSI
start address
start address
start address
(high-order 5 bits)
subroutine entry
address
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
INTCSI
INTT0
BR $ addr
instruction relative
branch address
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
–15 to –1,
+2 to +16
start address
start address
INTT0
INTT1/INTT2
start address
INTT1/INTT2
(low-order 8 bits)
BRCB ! caddr
instruction
branch
address
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 7 F F H
0 8 0 0 H
0 F F F H
1 0 0 0 H
BRCB ! caddr
instruction
branch
address
1 7 F F H
Note Can be used only in the MkII mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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Figure 4-3. Program Memory Map (3/4)
(c) µPD753208
Address
7
6
5
0
0
0 0 0 0 H
MBE RBE
Internal reset start address
Internal reset start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0
0
INTBT/INT4
INTBT/INT4
INT0
start address
start address
start address
(low-order 8 bits)
(high-order 5 bits)
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
(low-order 8 bits)
INT0
start address
CALLF
! faddr
instruction
entry
0 0 0 6 H
address
CALL ! addr
instruction
subroutine entry
address
0 0 0 8 H MBE RBE
0
INTCSI
start address
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
INTCSI
INTT0
start address
start address
BR $ addr
instruction relative
branch address
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
–15 to –1,
+2 to +16
INTT0
start address
start address
INTT1/INTT2
(low-order 8 bits)
INTT1/INTT2
BRCB ! caddr
start address
instruction
branch
address
0 0 2 0 H
GETI instruction reference table
0 0 7 F H
0 0 8 0 H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0 7 F F H
0 8 0 0 H
0 F F F H
1 0 0 0 H
BRCB ! caddr
instruction
branch
address
1 F F F H
Note Can be used only in the MkII mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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Figure 4-3. Program Memory Map (4/4)
(d) µPD75P3216
Address
7
6
5
0
0000H MBE
0002H MBE
0004H MBE
0006H
Internal reset start address (high-order 6 bits)
Internal reset start address (low-order 8 bits)
RBE
CALLF !faddr
instruction
entry address
RBE INTBT/INT4 start address (high-order 6 bits)
INTBT/INT4 start address (low-order 8 bits)
INT0 start address (high-order 6 bits)
RBE
BRCB !caddr
instruction
branch address
INT0 start address (low-order 8 bits)
RBE
MBE
0008H
INTCSI start address (high-order 6 bits)
Branch address
of the following
instructions:
· BR !addr
· CALL !addr
· BRA !addr1Note
· CALLA !add1Note
· BR BCDE
INTCSI start address (low-order 8 bits)
RBE INTT0 start address (high-order 6 bits)
INTT0 start address (low-order 8 bits)
000AH MBE
INTT1/INTT2 start address (high-order 6 bits)
INTT1/INTT2 start address (low-order 8 bits)
000CH MBE RBE
· BR BCXA
Branch/call
address by GETI
0020H
GETI instruction reference table
007FH
0080H
BR $addr instruction
relative branch
address
07FFH
0800H
(–15 to –1, +2 to +16)
0FFFH
1000H
BRCB !caddr
instruction
branch address
1FFFH
2000H
BRCB !caddr
instruction
branch address
2FFFH
3000H
BRCB !caddr
instruction
branch address
3FFFH
Note Can be used only in the MkII mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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4.4 Data Memory (RAM) ··· 512 words × 4 bits
The data memory consists of data areas and a peripheral hardware area as shown in Figure 4-4.
The data memory consists of the following banks, with each bank made up of 256 words × 4 bits:
•
•
Memory banks 0 and 1 (data areas)
Memory bank 15 (peripheral hardware area)
4.4.1 Configuration of data memory
(1) Data area
A data area consists of static RAM, and is used to store data and as a stack memory when a subroutine or interrupt
is executed. The contents of this area can be backed up for a long time by batteries even when the CPU is stopped
in the standby mode. The data area is manipulated by using memory manipulation instructions.
Static RAM is mapped to memory banks 0 and 1 in units of 256 × 4 bits each. Although bank 0 is mapped as
a data area, it can also be used as a general-purpose register area (000H through 01FH) and as a stack area
(000H through 1FFH: Refer to Note 1 below.). Bank 1 can be used as a display data memory (1ECH through
1F7H). One address of the static RAM consists of 4 bits. However, it can be manipulated in 8-bit units by using
an 8-bit memory manipulation instruction, or in 1-bit units by using a bit manipulation instruction (refer to Note
2 below). To use an 8-bit manipulation instruction, specify an even address.
Notes 1. One stack area can be selected from memory bank 0 or 1.
2. The display data memory cannot be manipulated in 8-bit units.
•
General-purpose register area
This area can be manipulated by using a general-purpose register manipulation instruction or memory
manipulation instruction. Up to eight 4-bit registers can be used. The registers not used by the program
can be used as part of the data area or stack area.
•
•
Stack area
The stack area is set by an instruction and is used as a saving area when a subroutine or interrupt processing
is executed.
Display data memory
The display data of an LCD are written to this area. The data written to this display data memory are
automatically read and displayed by hardware when the LCD is driven. The addresses of this area not
used for display can be used as data area addresses.
(2) Peripheral hardware area
The peripheral hardware area is mapped to addresses F80H through FFFH of memory bank 15.
This area is manipulated by using a memory manipulation instruction, in the same manner as the static area.
Note, however, that the bit units in which the peripheral hardware units can be manipulated differ depending on
the address. The addresses to which no peripheral hardware unit is allocated cannot be accessed because these
addresses are not provided to the data memory.
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4.4.2 Specifying bank of data memory
A memory bank is specified by a 4-bit memory bank select register (MBS) when bank specification is enabled by
setting a memory bank enable flag (MBE) to 1 (MBS = 0, 1, or 15). When bank specification is disabled (MBE = 0),
bank 0 or 15 is automatically specified depending on the addressing mode selected at that time. The addresses in
the bank are specified by 8-bit immediate data or a register pair.
For the details of memory bank selection and addressing, refer to3.1 Bank Configuration and Addressing Mode
of Data Memory.
For how to use a specific area of the data memory, refer to the following:
•
•
•
•
General-purpose register area··········· 4.5 General-Purpose Registers
Stack area··········································· 4.7 Stack Pointer (SP) and Stack Bank Selection Register (SBS)
Display data memory ························· 5.7.6 Display data memory
Peripheral hardware area ·················· CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
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Figure 4-4. Data Memory Map
Data Memory
0 0 0 H
Memory Bank
General-purpose
register area
(32 × 4)
0 1 F H
0
256 × 4
(224 × 4)
Stack areaNote
Data area
Static RAM
(512 × 4)
0 F F H
1 0 0 H
256 × 4
(236 × 4)
1
1 E B H
1 E C H
Display data
(12 × 4)
memory area
1 F 7 H
1 F 8 H
1 F F H
(8 × 4)
Not incorporated
F 8 0 H
128 × 4
15
Peripheral hardware area
F F F H
Note Memory bank 0 or 1 can be selected as the stack area.
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The contents of the data memory are undefined at reset. Therefore, they must be initialized at the beginning of
program execution (RAM clear). Otherwise, unexpected bugs may occur.
Example To clear RAM at addresses 000H through 1FFH
SET1
SEL
MOV
MOV
MOV
INCS
BR
MBE
MB0
XA, #00H
HL, #04H
@HL, A
L
RAMC0:
RAMC1:
; Clears 04H-FFHNote
; L ← L+1
RAMC
H
INCS
BR
; H ← H+1
RAMC0
MB1
SEL
MOV
INCS
BR
@HL, A
L
; Clears 100H-1FFH
; L ← L+1
RAMC1
H
INCS
BR
; H ← H+1
RAMC1
Note Data memory addresses 000H through 003H are not cleared because they are used as general-purpose
register pairs XA and HL.
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Figure 4-5. Configuration of Display Data Memory
Address
1ECH
b3
b2
b1
b0
S12
S13
1EDH
1EEH
1EFH
1F0H
1F1H
1F2H
1F3H
1F4H
1F5H
1F6H
1F7H
S14
S15
S16/P93
S17/P92
S18/P91
S19/P90
S20/P83
S21/P82
Display
data
memory
Segment
output
S22/P81
S23/P80
COM3
COM2
COM1
COM0
Common signal
The display data memory is manipulated in 1- or 4-bit units.
Caution The display data memory cannot be manipulated in 8-bit units.
Example To clear display data memory at addresses 1ECH-1F7H
SET1
SEL
MBE
MB1
MOV
MOV
MOV
INCS
SKE
SKE
BR
HL, #0ECH
A, #00H
@HL, A
HL
LOOP:
; Clears display data memory in 4-bit units at once
H, #0EH
L, #08H
LOOP
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4.5 General-Purpose Registers ··· 8 × 4 bits × 4 banks
The general-purpose registers are mapped in specific addresses of the data memory. There are four registers
banks each consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A).
The register bank (RB) which becomes valid during instruction execution is determined by the following expression:
RB = RBE•RBS (RBS = 0-3)
Each general-purpose register is manipulated in 4-bit units. In addition, register pairs BC, DE, HL, and XA can
also be used for 8-bit manipulation. The DL register can also be paired as well as DE and HL; these three register
pairs can be used as data pointers.
When two general-purpose registers are manipulated in 8-bit units, register pairs BC’, DE’, HL’, and XA’ of the
register bank (0 ↔ 1, 2 ↔ 3) specified by the complement of bit 0 of the register bank (RB) can be used, in addition
to BC, DE, HL, and XA (refer to 3.2 Bank Configuration of General-Purpose Registers).
The general purpose register area can be addressed as normal RAM for an access regardless of whether or not
the area is used as registers.
Figure 4-6. General-Purpose Register Configuration
Figure 4-7. Register Pair Configuration
3
0
3
0
Data memory
B
D
H
X
C
E
L
Address
3
0
3
3
3
0
0
0
3
3
3
0
0
0
000H
001H
A register
X register
1 bank
L register
H register
E register
D register
C register
B register
002H
003H
004H
005H
006H
Register bank 0
A
007H
008H
Same configuration
as bank 0
Register bank 1
00FH
010H
Same configuration
as bank 0
Register bank 2
Register bank 3
017H
018H
Same configuration
as bank 0
01FH
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4.6 Accumulators
The µPD753208 uses the A register and XA register pair as accumulators. The A register is used as the main
register during execution of 4-bit data processing instructions; the XA register pair is used as the main register pair
during execution of 8-bit data processing instructions.
The carry flag (CY) is used for a bit accumulator during execution of bit manipulation instructions.
Figure 4-8. Accumulators
CY
Bit accumulator
4-bit accumulator
8-bit accumulator
A
A
X
4.7 Stack Pointer (SP) and Stack Bank Selection Register (SBS)
The µPD753208 uses static RAM for stack memory (LIFO). The stack pointer (SP) is an 8-bit register which holds
top address information of the stack area.
The stack area is addresses 000H-1FFH of memory bank 0 or 1. Specify one memory bank using 2-bit SBS. (Refer
to Table 4-2.)
Table 4-2. Stack Area Selected by SBS
SBS
Stack Area
SBS1
SBS0
0
0
0
1
Memory bank 0
Memory bank 1
Setting prohibited
Other than above
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The SP decrements before a write (save) operation in the stack memory and increments after a read (restore)
operation from it.
Figures 4-10 to 4-13 show the data saved and restored by the stack operations.
The initial value of the SP is set by an 8-bit memory manipulation instruction and the initial value of the SBS is
set by a 4-bit memory manipulation instruction to determine a stack area. Its contents can also be read.
When 00H is set in the SP as the initial value, data is stacked first in the highest-order address (nFFH) in the memory
bank (n) specified by the SBS.
The stack area is limited to the memory bank specified by the SBS, and data is returned to nFFH in the same bank
when further stacking operation is performed in addresses starting with n00H. Data cannot be stacked over the
boundary of memory bank without rewriting the SBS.
Since the contents of the SP becomes uncertain and the contents of the SBS becomes 1000B when a RESET
signal is generated, they must be initialized to the desired values at the start of programs.
Figure 4-9. Stack Pointer and Stack Bank Selection Register Configuration
Address
Symbol
SP
F 8 0 H
SP7
SP6
SP5
SP4
SP3
SP2
0
SP1
0
SBS3Note
SBS1 SBS0 SBS
F 8 4 H
0 0 0 H
SP
SP
Memory bank 0
Memory bank 1
SBS
0 F F H
1 0 0 H
1 F F H
Note Switching between the Mk I mode and Mk II mode can be done by a SBS3. The stack bank select function
can be used in both the Mk I mode and Mk II mode (Refer to 4.1 Switching Function between Mk I Mode
and Mk II Mode).
Example SP Initialization
Memory bank 1 is assigned to the stack area and data is stacked in addresses starting with 1FFH.
SEL
MB15
; or CLR1 MBE
MOV
MOV
MOV
MOV
A, #1
SBS, A
XA, #00H
SP, XA
; Assign memory bank 1 as the stack area.
; SP ← 00H
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Figure 4-10. Data Saved in Stack Memory (Mk I mode)
PUSH instruction
CALL, CALLF instruction
Interrupt
Stack
Stack
Stack
SP – 6
SP – 5
SP – 4
SP – 3
SP – 2
SP – 1
PC11 - PC8
PC11 - PC8
SP – 4
Note 2
Note 2
MBE RBE 0Note 1 PC12
PC3 - PC0
MBE RBE 0Note 1 PC12
PC3 - PC0
SP – 3
SP – 2
SP – 1
Register pair low order
SP – 2
SP – 1 Register pair high order
SP
PC7 - PC4
PC7 - PC4
IST1 IST0 MBE RBE
PSW
SP
CY SK2 SK1 SK0
SP
Figure 4-11. Data Restored from Stack Memory (Mk I mode)
POP instruction
RET, RETS instruction
RETI instruction
Stack
Stack
Stack
PC11 - PC8
PC11 - PC8
Register pair low order
Register pair high order
SP
SP
SP
Note 2
Note 2
MBE RBE 0Note 1 PC12
MBE RBE 0Note 1 PC12
PC3 - PC0
SP+1
SP+2
SP+1
SP+2
SP+ 3
SP+4
SP+1
SP+2
SP+3
SP+4
PC3 - PC0
PC7 - PC4
PC7 - PC4
IST1 IST0 MBE RBE
PSW
CY SK2 SK1 SK0
SP+5
SP+6
Notes 1. For the µPD75P3216, PC13 is saved to this position.
2. For the µPD753204, PC12 is set to 0.
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Figure 4-12. Data Saved in Stack Memory (Mk II mode)
PUSH instruction
CALL, CALLA, CALLF instruction
Interrupt
Stack
Stack
Stack
SP – 6
PC11 - PC8
SP – 6
PC11 - PC8
Note 2
Note 2
0
0
0Note 1 PC12
0
0
0Note 1 PC12
SP – 5
SP – 4
SP – 3
SP – 2
SP – 1
SP – 5
SP – 4
SP – 3
SP – 2
SP – 1
PC3 - PC0
PC7 - PC4
PC3 - PC0
PC7 - PC4
SP – 2
SP – 1
Register pair low order
Register pair high order
MBE RBE
IST1 IST0 MBE RBE
PSW
SP
*
*
*
*
Note 3
CY SK2 SK1 SK0
*
*
SP
SP
Figure 4-13. Data Restored from Stack Memory (MkII mode)
POP instruction
RET, RETS instruction
RETI instruction
Stack
Stack
Stack
PC11 - PC8
0
PC11 - PC8
Register pair low order
Register pair high order
SP
SP
SP
Note 2
Note 2
0Note 1 PC12
0Note 1 PC12
0
0
0
SP+ 1
SP+ 2
SP+ 1
SP+ 2
SP+ 3
SP+ 4
SP+ 5
SP+ 1
SP+ 2
SP+ 3
SP+ 4
PC3 - PC0
PC7 - PC4
PC3 - PC0
PC7 - PC4
MBE RBE
IST1 IST0 MBE RBE
PSW
*
*
*
*
Note 3
CY SK2 SK1 SK0
SP+ 5
SP+ 6
*
*
SP+ 6
Notes 1. For the µPD75P3216, PC13 is saved to this position.
2. For the µPD753204, PC12 is set to 0.
3. PSW other than MBE and RBE is not saved/restored.
Remark * means undefined.
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4.8 Program Status Word (PSW) ··· 8 bits
The program status word (PSW) consists of flags closely related to processor operation.
PSW is mapped in memory space addresses FB0H and FB1H, and four bits of address FB0H can be manipulated
by executing a memory manipulation instruction.
Figure 4-14. Program Status Word Format
Address
FB0H
Symbol
PSW
FB1H
FB0H
CY
SK2
SK1
SK0
IST1 IST0
MBE RBE
Cannot be manipulated
Can be manipulated
Can be manipulated by
executing a dedicated
instruction
Table 4-3. PSW Flags Saved and Restored during Stack Operation
Flags Saved and Restored
Save
When CALL, CALLA or CALLF instruction is executed
When hardware interrupt is executed
MBE and RBE are saved
All PSW bits are saved
MBE and RBE are restored
All PSW bits are restored
Restore
When RET or RETS instruction is executed
When RETI instruction is executed
(1) Carry flag (CY)
The carry flag (CY) is a 1-bit flag which stores overflow or underflow occurrence information when an operation
instruction with carry (ADDC or SUBC) is executed. The carry flag also serves as a bit accumulator.
Boolean algebra operation is performed between the bit accumulator and the data memory specified by bit
address, and the result can be stored in the accumulator.
The carry flag is manipulated by executing a dedicated instruction independently of other PSW bits.
When a RESET is input, the carry flag becomes undefined.
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Table 4-4. Carry Flag Manipulation Instructions
Instruction (Mnemonics)
Carry Flag Manipulation and Processing
Carry flag manipulation
dedicated instruction
SET1
CY
CY
CY
CY
Set CY to 1
CLR1
NOT1
SKT
Reset CY to 0
Reverses the CY status
Skip if CY contains 1
Bit transfer instruction
Bit Boolean instruction
MOV1
MOV1
mem*.bit, CY
CY,mem*.bit
Transfer CY contents to the specified bit
Transfer the specified bit contents to CY
AND1
OR1
CY,mem*.bit
CY,mem*.bit
CY,mem*.bit
AND, OR, and XOR in the specified bit contents and CY contents
and set the result in CY
XOR1
Interrupt processing
When interrupt is executed
Save CY and other PSW bits in stack memory in parallel
.............................................................................................................................................................................................................................
RETI
Restore CY and other PSW bits in parallel from stack memory
Remark mem*.bit indicates following three bit manipulation addressing
•
•
•
fmem.bit
pmem.@L
@H+mem.bit
Example AND address 3FH bit 3 and P33 and output the result to P50.
MOV
H, #3H
;
;
;
;
Set high-order 4-bit address in H register
CY ← 3FH BIT 3
MOV1
AND1
MOV1
CY, @H+0FH.3
CY, PORT3.3
PORT5.0, CY
CY ← CY ^ P33
P50 ← CY
(2) Skip flag (SK2, SK1, SK0)
The skip flag stores the skip state. It is automatically set or reset when the CPU executes an instruction.
The user cannot directly manipulate the flag as an operand.
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(3) Interrupt status flag (IST1, IST0)
The interrupt status flag is a 2-bit flag which stores the status of the current processing being performed (For
details, refer to Table 6-3. IST1 and IST0 and Interrupt Processing Status).
Table 4-5. Interrupt Status Flag Indication
IST1
0
IST0
0
Status of Processing Being Performed
Status 0
Processing Indication and Interrupt Control
During normal program processing.
Acknowledgment of all interrupts is enabled.
0
1
1
1
0
1
Status 1
Status 2
–
During low-priority or high-priority interrupt processing.
High-priority interrupt acknowledgment is enabled.
During high-priority interrupt processing.
Acknowledgment of all interrupt is disabled.
Setting prohibited
The interrupt priority control circuit (refer to Figure 6-1. Interrupt Control Circuit Block Diagram) judges the
interrupt status flag contents to control nesting.
If an interrupt is acknowledged, the IST1 and IST0 contents are saved in the stack memory as a part of PSW,
then automatically changed to the upper status. When the RETI instruction is executed, the value before the
interrupt processing routine is entered is restored.
The interrupt status flag can be manipulated by executing a memory manipulating instruction. The status of
processing being performed can also be changed under the program control.
Caution To manipulate the flag, be sure to execute a DI instruction to disable interrupts before
manipulation and execute an EI instruction to enable interrupts after manipulation.
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(4) Memory bank enable flag (MBE)
The memory bank enable flag (MBE) is a 1-bit flag to specify the address information generation mode of the
high-order four bits of a 12-bit data memory address.
MBE can be set or reset at any time, regardless of the setting of the memory bank.
When MBE is set to 1, the data memory address space is expanded and all the data memory space can be
addressed.
When MBE is reset to 0, the data memory address space is fixed regardless of the MBS contents (Refer toFigure
3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode).
When a RESET signal is input, the contents of bit 7 of program memory address 0 is set in MBE for automatic
initialization.
When vectored interrupt processing is performed, the bit 7 contents of the corresponding vector address table
are set and the MBE state during the interrupt processing is automatically set.
Normally, in interrupt processing, MBE is set to 0 for use of static RAM of memory bank 0.
(5) Register bank enable flag (RBE)
The register bank enable flag (RBE) is a 1-bit flag to control whether or not the register bank configuration of
the general-purpose registers is expanded.
RBE can be set or reset at any time, regardless of the setting of the memory bank.
When RBE is set to 1, general-purpose registers of one bank can be selected among register banks 0-3 according
to the register bank selection register (RBS) contents.
When RBE is reset to 0, register bank 0 is always selected for general-purpose registers regardless of the register
bank selection register (RBS) contents.
When a RESET signal is input, the bit 6 contents of program memory address 0 are set in RBE for automatic
initialization.
When a vectored interrupt occurs, the bit 6 contents of the corresponding vector address table are set and the
RBE state during the interrupt processing is automatically set. Normally, in interrupt processing, RBE is set to
0 for use of register bank 0 for 4-bit operation or register bank 0 and 1 for 8-bit operation.
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4.9 Bank Selection Register (BS)
The bank selection register (BS) consists of the register bank selection register (RBS) and memory bank selection
register (MBS) to specify the register bank and memory bank to be used.
RBS and MBS are set by executing SEL RBn and SEL MBn instructions, respectively.
BS can be saved in and restored from the stack memory in 8-bit units by executing the PUSH BS and POP BS
instructions.
Figure 4-15. Bank Selection Register Format
Address
F82H
Symbol
BS
F83H
F82H
MBS3 MBS2 MBS1 MBS0
0
0
RBS1 RBS0
(1) Memory bank selection register (MBS)
The memory bank selection register (MBS) is a 4-bit register which stores high-order 4-bit address information
of a 12-bit data memory address. The memory bank to be accessed is specified by the register contents (For
the µPD753208, only banks 0, 1, and 15 can be specified).
MBS is set by executing the SEL MBn instruction (n = 0, 1, or 15).
The address range for MBE and MBS setting is as shown in Figure 3-2.
When a RESET signal is input, MBS is initialized to 0.
(2) Register bank selection register (RBS)
The register bank selection register (RBS) is a register to specify the register bank used as general- purpose
registers. One of banks 0-3 can be selected.
RBS is set by executing the SEL RBn instruction (n = 0-3).
When a RESET signal is input, RBS is initialized to 0.
Table 4-6. RBE, RBS, and Selected Register Bank
RBS
RBE
Register Bank
3
0
0
2
0
0
1
×
0
0
1
1
0
×
0
1
0
1
0
1
Fixed to bank 0
Bank 0 selection
Bank 1 selection
Bank 2 selection
Bank 3 selection
Fixed to 0
× : Don't care
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[MEMO]
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
5.1 Digital I/O Port
Memory mapped I/O is employed for the µPD753208. All the I/O ports are mapped in the data memory space.
Figure 5-1. Digital Ports Data Memory Addresses
Address
F F 0 H
3
2
1
0
P03
P02
P01
P00 PORT0
F F 1 H
F F 2 H
F F 3 H
F F 5 H
F F 6 H
F F 8 H
F F 9 H
P13
P23
P33
P53
P63
P83
P93
–
–
P10 PORT1
P20 PORT2
P30 PORT3
P50 PORT5
P60 PORT6
P80 PORT8
P90 PORT9
P22
P32
P52
P62
P82
P92
P21
P31
P51
P61
P81
P91
Table 5-2 lists the input/output ports manipulation instructions for Port 8 and Port 9 in addition to 4-bit input/output,
8-bit input/output and bit manipulation can be performed. These enable many types of control.
Examples 1. The status shown on P13 is tested and the values depending on the results of test are output to
ports 8 and 9.
SKT
PORT1.3
; Skip if bit 3 of port 1 is 1.
MOV XA, #18H
MOV XA, #14H
; XA ← 18H
; XA ← 14H
; or CLR1 MBE
String effect
String effect
SEL
MB15
OUT
PORT8, XA ; ports 9, 8 ← XA
2. SET1 PORT8. @L ; The bit (in ports 8 and 9) specified by the L register is set to 1.
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5.1.1 Types, features, configuration of digital I/O ports
Table 5-1 lists the types of digital I/O ports.
The configurations of the ports are shown in Figures 5-2 to 5-6.
Table 5-1. Types and Features of Digital Ports
Port (Pin name)
Function
Operation & Features
Remarks
PORT0
(P00-P03)
4-bit input
Shared with output function depending on operation
mode of the shared pins when the serial interface
function is used.
Also used for the INT4, SCK,
SO/SB0, and SI/SB1 pins
PORT1
(P10, P13)
2-bit input
4-bit I/O
Dedicated 2-bit input port.
Also used for the INT0 and
TI0 pins.
PORT2
(P20-P23)
Can be set to input mode or output mode in 4-bit units.
Can be set to input mode or output mode in 1-bit units.
Also used for the PTO0-
PTO2, PCL, and BUZ pins
PORT3
(P30-P33)
Also used for the LCDCL,
SYNC, and MD0-MD3Note 1
pins
PORT5
(P50-P53)
4-bit I/O
Can be set to input mode or output mode in 4-bit units.
Also used for the D4-D7Note 1
pins
(N-ch open-drain, On-chip pull-up resistor can be specified by mask
13 V withstand optionNote 2 bit-wise.
voltage)
PORT6
(P60-P63)
4-bit I/O
Can be set to input mode or output mode in 1-bit units.
Also used for the KR0-KR3,
D0-D3Note 1 pins
PORT8
(P80-P83)
Can be set to input mode or output mode in 4-bit units.
Input/output of data can be executed in pairs of 4-bit
units (8-bit units).
Also used for the S20-S23
pins
PORT9
(P90-P93)
Also used for the S16-S19
pins
Notes 1. Shared with only in the µPD75P3216.
2. The µPD75P3216 does not incorporate pull-up resistors by mask option.
P10 is also used for an external vectored interrupt input pin and has a noise eliminating circuit (Refer to 6.3
Hardware Controlling Interrupt Functions).
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-2. Port 0, 1 Configuration
SI
SCK INT4
SO
Internal
SCK
V
DD
P01
output latch
Pull-up
resistor
Selector
Selector
8
CSIM
P-ch
POGA
bit 0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
Output buffer where push-pull
output and N-ch open-drain
output can be changed.
N-ch open-drain
output buffer
Input buffer
V
DD
Pull-up resistor
P-ch
POGA
bit 1
Φ or f /64
X
Input buffer
Noise
eliminating
circuit
P10/INT0
P13/TI0
Input buffer having
hysteresis characteristic
TI0
INT0
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Figure 5-3. Port 3, 6 Configuration
Key interrupt (Port 6 only)
Input buffer having hysteresis
characteristic (Port 6 only)
VDD
Pull-up resistor
PMmn = 0
Input buffer
M
P
PMmn = 1
X
POGA
bit m
P-ch
Output latch
PMmn
Output buffer
Pmn
Corresponding bit of port
mode register group A
m = 3, 6
n = 0-3
Figure 5-4. Port 2 Configuration
V
DD
Pull-up resistor
P-ch
POGA
bit 2
Input buffer
PM2=0
M
P
X
PM2=1
P20
P21
P22
P23
Output
latch
Output buffer
PM2
Corresponding bit of
port mode register group B
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-5. Port 5 Configuration
V
DD
Pull-up
resistor
(Mask option)
Input buffer
PM5 = 0
M
P
PM5 = 1
X
P50
P51
Output
latch
P52
P53
N-ch open-drain
output buffer
PM5
Corresponding bit of
port mode register group B
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Figure 5-6. Port 8, 9 Configuration
VDD
Pull-up resistor
P-ch
POGB
bits 0,1
Input buffer
PMm=0
M
P
X
PMm=1
Output
buffer
Pm0
Pm1
Pm2
Pm3
Output
latch
Decoder
LPS
PMm
Corresponding bit of
port mode register group C
(m=8, 9)
LCD controller/driver
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5.1.2 Setting I/O mode
The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 5-
7. Ports 3 and 6 can be set in the input or output mode in 1-bit units by using port mode register group A (PMGA).
Ports 2 and 5 are set in the input or output mode in 4-bit units by using port mode register group B (PMGB). Port
mode group register group C (PMGC) is used to set the input or output mode of ports 8 and 9 in 4-bit units.
Each port is set in the input mode when the corresponding port mode register bit is “0” and in the output mode
when the corresponding register bit is “1”.
When a port is set in the output mode by the corresponding port mode register, the contents of the output latch
are output to the output pin(s). Before setting the output mode, therefore, the necessary value must be written to
the output latch.
Port mode register groups A, B, and C are set by using an 8-bit memory manipulation instruction.
When the RESET signal is asserted, all the bits of each port mode register are cleared to 0, turning off the output
buffer and setting the corresponding port in the input mode.
Example To use P30, 31, 62, and 63 as input pins and P32, 33, 60, and 61 as output pins
CLR1
MOV
MOV
MBE
; or SEL MB15
XA, #3CH
PMGA, XA
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Figure 5-7. Port Mode Register Formats
Specification
0
1
Input mode (output buffer off)
Output mode (output buffer on)
Port mode register group A
Address
Symbol
PMGA
7
6
5
4
3
2
1
0
FE8H
PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30
P30 input/output specification
P31 input/output specification
P32 input/output specification
P33 input/output specification
P60 input/output specification
P61 input/output specification
P62 input/output specification
P63 input/output specification
Port mode register group B
Address
Symbol
PMGB
7
6
5
4
3
2
1
0
FECH
PM5
PM2
Port 2 (P20-P23) input/output specification
Port 5 (P50-P53) input/output specification
Port mode register group C
Address
Symbol
PMGC
7
6
5
4
3
2
1
0
FEEH
PM9
PM8
Port 8 (P80-P83) input/output specification
Port 9 (P90-P93) input/output specification
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5.1.3 Digital I/O port manipulation instruction
Because all the I/O ports of the µPD753208 are mapped to the data memory space, they can be manipulated by
using data memory manipulation instructions. Of these data memory manipulation instructions, those considered
to be especially useful for manipulating the I/O pins and their range of applications are shown in Table 5-2.
(1) Bit manipulation instruction
Because the specific address bit direct addressing (fmem.bit) and specific address bit register indirect addressing
(pmem.@L) are applicable to digital I/O ports 0 through 3, 5, 6, 8, and 9, the bits of these ports can be manipulated
regardless of the specifications by MBE and MBS.
Example To OR P50 and P51 and set P61 in output mode
MOV1
OR1
CY, PORT5.0
CY, PORT5.1
PORT6.1, CY
; CY ← P50
; CY ← CY v P51
; P61 ← CY
MOV1
(2) 4-bit manipulation instruction
In addition to the IN and OUT instructions, all the 4-bit memory manipulation instructions such as MOV, XCH,
ADDS, and INCS can be used to manipulate the ports in 4-bit units. Before executing these instructions, however,
memory bank 15 must be selected.
Examples 1. To output the contents of the accumulator to port 3
SET1
SEL
MBE
MB15
; or CLR1 MBE
OUT
PORT3, A
2. To add the value of the accumulator to the data output to port 5
SET1
SEL
MBE
MB15
MOV
ADDS
NOP
MOV
HL, #PORT5
A, @HL
; A ← A+PORT5
; PORT5 ← A
@HL, A
3. To test whether the data of port 5 is greater than the value of the accumulator
SET1
SEL
MBE
MB15
MOV
SUBS
BR
HL, #PORT5
A, @HL
NO
; A<PORT5
; NO
; YES
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(3) 8-bit manipulation instruction
In addition to the IN and OUT instructions, the MOV, XCH, and SKE instructions can be used to manipulate ports
8 and 9, which can be manipulated in 8-bit units. In this case also, memory bank 15 must be selected, just as
when 4-bit manipulation instructions are used to manipulate ports.
Example To output the data of register pair BC to the output port specified by the 8-bit data input from ports
8 and 9
SET1
SEL
IN
MBE
MB15
XA, PORT8
HL, XA
XA, BC
@HL, XA
; XA ← ports 9 and 8
; HL ← XA
MOV
MOV
MOV
; XA ← BC
; Port (L) ← XA
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Table 5-2. I/O Pin Manipulation Instructions
Port
Port
0
Port
1
Port
2
Port
3
Port
5
Port
6
Port
8
Port
9
Instruction
Note 1
IN
A, PORTn
●
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
IN
XA, PORTn
PORTn, A
PORTn, XA
–
–
–
–
–
–
–
–
–
●
–
●
●
●
●
●
OUT
OUT
MOV A, PORTn
MOV XA, PORTn
MOV PORTn, A
MOV PORTn, XA
●
●
●
–
–
–
–
–
–
XCH
XCH
A, PORTn
XA, PORTn
MOV1 CY, PORTn.bit
MOV1 CY, PORTn.@L
MOV1 PORTn.bit, CY
MOV1 PORTn.@L, CY
INCS PORTn
●
●
Note 2
–
–
–
–
●
●
Note 2
Note 1
●
SET1 PORTn.bit
–
–
–
–
●
●
●
●
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
SET1 PORTn.@L
CLR1 PORTn.bit
CLR1 PORTn.@L
SKT
SKT
SKF
SKF
PORTn.bit
PORTn.@L
PORTn.bit
PORTn.@L
●
●
●
●
●
●
●
●
●
●
●
●
SKTCLR PORTn.bit
SKTCLR PORTn.@L
AND1 CY, PORTn. bit
AND1 CY, PORTn. @L
OR1
OR1
CY, PORTn. bit
CY, PORTn. @L
XOR1 CY, PORTn. bit
XOR1 CY, PORTn. @L
Notes 1. Must be MBE = 0 or (MBE = 1, MBS = 15) before execution.
2. The low-order 2 bits and the bit addresses of the address must be indirectly specified by the L register.
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5.1.4 Operation of digital I/O port
The operations of each port and port pin when a data memory manipulation instruction is executed to manipulate
a digital I/O port differs depending on whether the port is set in the input or output mode (refer to Table 5-3). This
is because, as can be seen from the configuration of the I/O port, the data of each pin is loaded to the internal bus
in the input mode, and the data of the output latch is loaded to the internal bus in the output mode.
(1) Operation in input mode
When a test instruction such as SKT, a bit input instruction such as MOV1, or an instruction that loads port data
to the internal bus, such as IN, MOV, an operation, or a comparison instruction, is executed, the data of each
pin is manipulated.
When an instruction that transfers the contents of the accumulator in 4- or 8-bit units, such as OUT or MOV, is
executed, the data of the accumulator is latched to the output latch. The output buffer remains off.
When the XCH instruction is executed, the data of each pin is input to the accumulator, and the data of the
accumulator is latched to the output latch. The output buffer remains off.
When the INCS instruction is executed, the data which 1 is added to the data of each pin (4 bits) is latched to
the output latch. The output buffer remains off.
When an instruction that rewrites the data memory contents in 1-bit units, such as SET1, CLR1, MOV1, or
SKTCLR, is executed, the contents of the output latch of the specified bit can be rewritten as specified by the
instruction, but the contents of the output latches of the other bits are undefined.
(2) Operation in output mode
When a test instruction, bit input instruction, or an instruction that loads port data to the internal bus is executed,
the contents of the output latch are manipulated.
When an instruction that transfers the contents of the accumulator in 4- or 8-bit units is executed, the data of
the output latch is rewritten and at the same time output from the port pins.
When the XCH instruction is executed, the contents of the output latch are transferred to the accumulator, and
the contents of the accumulator are latched to the output latches of the specified port and output from the port
pins.
When the INCS instruction is executed, the contents of the output latches of the specified port are incremented
by 1 and output from the port pins.
When a bit output instruction is executed, the specified bit of the output latch is rewritten and output from the
pin.
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Table 5-3. Operation When an I/O Port Is Manipulated
Operation of Port and Pins
Input Mode
Instruction Executed
Output Mode
SKT
1
1
Tests pin data
Tests output latch data
SKF
MOV1
AND1
OR1
CY,
CY,
CY,
CY,
Transfers pin data to CY
Transfers output latch data to CY
1
1
1
1
Performs operation between pin data and CY
Performs operation between output latch
data and CY
XOR1
IN
A, PORTn
XA, PORTn
A, PORTn
XA, PORTn
A, @HL
XA, @HL
A, @HL
A, @HL
A, @HL
A, @HL
A, @HL
A, @HL
A, @HL
A, @HL
XA, @HL
PORTn, A
PORTn, XA
PORTn, A
PORTn, XA
@HL, A
@HL, XA
A, PORTn
XA, PORTn
A, @HL
XA, @HL
PORTn
Transfers pin data to accumulator
Transfers output latch data to accumulator
IN
MOV
MOV
MOV
MOV
ADDS
ADDC
SUBS
SUBC
AND
OR
Performs operation between pin data and
accumulator
Performs operation between output latch
data and accumulator
XOR
SKE
Compares pin data with accumulator
Compares output latch data with accumulator
SKE
OUT
OUT
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
INCS
INCS
SET1
CLR1
MOV1
SKTCLR
Transfers accumulator data to output latch
(output buffer remains off)
Transfers accumulator data to output latch
and outputs data from pins
Transfers pin data to accumulator and
accumulator data to output latch (output
buffer remains off)
Exchanges data between output latch and
accumulator
Increments pin data by 1 and latches it to
output latch
Increments output latch contents by 1
@HL
1
Rewrites output latch contents of specified bit
as specified by instruction but output latch
contents of other bits are undefined
Changes status of output pin as specified by
instruction
1
1
1
, CY
Remark
: Indicates two addressing modes: PORTn. bit and PORTn.@L.
1
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5.1.5 Connecting pull-up resistors
Each port pin of the µPD753208 can be connected to an internal pull-up resistor (except the P00 pin). Some pins
can be connected with a pull-up resistor via software and the others can be connected by mask option.
Table 5-4 shows how to specify connection of a pull-up resistor to each port pin. The internal pull-up resistor is
connected by software in the format shown in Figure 5-8.
Internal pull-up resistors can be connected only to the pins of ports 3 and 6 in the input mode. To the pins set
in the output mode, the internal pull-up resistor cannot be connected regardless of the setting of POGA, POGB.
Table 5-4. Pull-Up Resistor Incorporation Specification Method
Port (Pin Name)
Pull-up Resistor Incorporation Specification Method
Specified Bit
POGA.0
POGA.1
POGA.2
POGA.3
–
PORT0 (P01-P03)Note 1 Connection specification by software in 3-bit units
PORT1 (P10, P13)
PORT2 (P20-P23)
PORT3 (P30-P33)
PORT5 (P50-P53)
PORT6 (P60-P63)
PORT8 (P80-P83)Note 2
PORT9 (P90-P93)Note 2
Connection specification by software in 2-bit units
Connection specification by software in 4-bit units
Incorporation specification by mask option in 1-bit units
Connection specification by software in 4-bit units
POGA.6
POGB.0
POGB.1
Notes 1. The P00 pin cannot specify connection of an internal pull-up resistor.
2. When these pins are used to output segment signals, do not connect the internal pull-up
resistor by software.
Rem ark The µPD75P3216 does not incorporate pull-up resistors by mask option.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-8. Pull-Up Resistor Register Format
Specification
0
1
Internal pull-up resistor not connected
Internal pull-up resistor connected
Pull-up resistor register group A
Address
Symbol
POGA
7
6
5
4
3
2
1
0
FDCH
PO6
PO3
PO2 PO1 PO0
Port 0 (P01-P03)
Port 1 (P10, P13)
Port 2 (P20-P23)
Port 3 (P30-P33)
Port 6 (P60-P63)
Pull-up resistor register group B
Address
Symbol
POGB
7
6
5
4
3
2
1
0
FDEH
PO9 PO8
Port 8 (P80-P83)
Port 9 (P90-P93)
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5.1.6 I/O timing of digital I/O port
Figure 5-9 shows the timing by which data is output to the output latch and the timing by which the pin data or
the data of the output latch is loaded to the internal bus.
Figure 5-10 shows the ON timing when an internal pull-up resistor is connected to a port pin via software.
Figure 5-9. I/O Timing of Digital I/O Port
(a) When data is loaded by 1-machine cycle instruction
1 machine cycle
Φ
0
Φ
1
Φ
2
Φ
3
Instruction
execution
Manipulation instruction
Input timing
(b) When data is loaded by 2-machine cycle instruction
2 machine cycle
Φ
0
Φ
1
Φ
2
Φ
3
Instruction
execution
Manipulation instruction
Input timing
(c) When data is latched by 1-machine cycle instruction
Φ
3
Φ
0
Φ
1
Instruction
execution
Manipulation instruction
Output latch
(output pin)
(d) When data is latched by 2-machine cycle instruction
Φ
0
Φ
1
Instruction
execution
Manipulation instruction
Output latch
(output pin)
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Figure 5-10. ON Timing of Internal Pull-up Resistor Connected via Software
2 machine cycles
Φ0
Φ1
Instruction
execution
Internal pull-up resistor setting instruction
Pull-up
resistor register
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5.2 Clock Generator
The clock generator supplies various clocks to the CPU and peripheral hardware units and controls the operation
mode of the CPU.
5.2.1 Clock generator configuration
The configuration of the clock generator is shown in Figure 5-11.
Figure 5-11. Clock Generator Block Diagram
• Basic interval timer (BT)
• Timer/event counter 0
• Timer counter 1, 2
• Watch timer
• LCD controller/driver
• Serial interface
• INT0 noise eliminating circuit
• Clock output circuit
X1
V
DD
System clock
oscillator
fX
1/1 1/4096
Divider
X2
1/2 1/4 1/16
Oscillation stop
Divider
1/4
Φ
• CPU
• INT0 noise eliminating circuit
• Clock output circuit
PCC
PCC0
PCC1
PCC2
PCC3
4
HALT F/F
S
HALTNote
STOPNote
R
Q
PCC2,
PCC3
clear
STOP F/F
Wait release signal from BT
Q
S
RESET signal
R
Standby release signal
from interrupt control
circuit
Note Instruction execution
Remarks 1. fX = System clock frequency
2. Φ = CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
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5.2.2 Clock generator function and operation
The clock generator provides the following clock signals and controls the operating mode of the CPU such as
standby mode.
•
•
•
System clock
CPU clock
fX
Φ
Clock to peripheral hardware
The clock generator operates according to how the processor clock control register (PCC) is set, as described
below:
(a) When the RESET signal is generated, the minimum speed mode of the system clock (10.7 µs at 6.00 MHz
operation) is selected. (PCC = 0)
(b) One of four CPU clock frequencies can be selected (0.67 µs, 1.33 µs, 2.67 µs, and 10.7 µs @ 6.00 MHz operation)
by setting PCC.
(c) The standby mode (STOP or HALT) can be used.
(d) The clock supplied to the peripheral hardware is generated by dividing the sytem clock.
(e) The serial interface, timer/event counter, and timer counter can continue operation when an external clock is
selected as the clock. The other hardware units, however, operate on the system clock and therefore cannot
be used when the system clock is stopped.
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(1) Processor clock control register (PCC)
The PCC is a 4-bit register whereof the low-order 2 bits select the CPU clock F and high-order 2 bits control the
CPU operating mode. (Refer to Figure 5-12.)
When bit 2 or bit 3 is set to “1” exclusively, the PCC is set in the standby mode. When it is released from the
mode by a Standby Release signal, both bits 2 and 3 are automatically cleared for normal operations (Refer to
CHAPTER 7 STANDBY FUNCTIONS).
The low-order 2 bits of the PCC are set by a 4-bit memory manipulation instruction. (The high-order 2 bits must
be set to “0”.)
Bits 2 and 3 are set to “1” by a HALT instruction and STOP instruction, respectively.
These instructions can be executed regardless of the contents of MBE.
Examples 1. The machine cycle is set to the fastest mode (0.67 µs: during fx = 6.00 MHz operation).
SEL
MB15
MOV A, #0011B
MOV PCC, A
2. The machine cycle is set to 1.91 µs (during fX = 4.19 MHz).
SEL
MB15
MOV A, #0010B
MOV PCC, A
3. The PCC is set to the STOP mode. (An NOP instruction must be entered following the STOP
instruction or HALT instruction.)
STOP
NOP
The PCC is cleared to “0” by the RESET signal.
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Figure 5-12. Format of Processor Clock Control Register
Address
FB3H
Symbol
0
3
2
1
PCC3 PCC2 PCC1 PCC0
PCC
CPU mode control bits
PCC3
PCC2
Operation mode
0
0
1
1
0
1
0
1
Normal operation mode
HALT mode
STOP mode
Setting prohibited
CPU clock select bits (at fX = 6.0 MHz)
PCC1
PCC0
CPU clock frequency
Φ = fX/64 (93.8 kHz)
Φ = fX/16 (375 kHz)
1 machine cycle
0
0
1
1
0
1
0
1
10.7 µs
2.67 µs
1.33 µs
0.67 µs
Φ = fX/8
Φ = fX/4
(750 kHz)
(1.5 MHz)
(at fX = 4.19 MHz)
PCC1
PCC0
CPU clock frequency
1 machine cycle
0
0
1
1
0
1
0
1
Φ = fX/64 (65.5 kHz)
Φ = fX/16 (262 kHz)
15.3 µs
3.81 µs
1.91 µs
0.95 µs
Φ = fX/8
Φ = fX/4
(524 kHz)
(1.05 MHz)
Remark fX: Output frequency of system clock oscillation circuit
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(2) System clock oscillators
The system clock oscillator oscillates with a crystal resonator or ceramic oscillator connected to the X1 and X2
pins. (4.194304 MHz TYP.)
External clock can also be input.
Figure 5-13. System Clock Oscillator External Circuit
(a) Crystal or ceramic oscillation
(b) External clock
V
DD
µ
PD753208
µ
PD753208
V
DD
External
clock
X1
X1
X2
X2
Crystal resonator or
ceramic oscillator
Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up with VDD on resistance of 50-
kΩ (TYP.).
2. Wire the portion enclosed by the dotted line in Figure 5-13 as follows to prevent adverse
influence by wiring capacitance when using the system clock oscillation circuits.
• Keep the wiring length as short as possible.
• Do not cross the wiring with any other signal lines.
• Do not route the wiring in the vicinity of a line through which a high alternating current flows.
• Always keep the potential at the connecting point of the capacitor of the oscillation circuit
at the same level as VDD. Do not connect the wiring to a power supply pattern through which
a high current flows.
• Do not extract signals from the oscillation circuit.
Figure 5-14 shows examples of connecting the oscillator incorrectly.
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Figure 5-14. Example of Connecting Oscillator Incorrectly (1/2)
(a) Wiring length too long
(b) Crossed signal line
PORTn
( n = 0 - 3,5,6,8,9)
µ
PD753208
µ
PD753208
X1
X2
X1
X2
V
DD
V
DD
V
DD
V
DD
(c) High alternating current
close to signal line
(d) Current flowing through power line
of oscillation circuit
(potential at points A, B, and C changes)
V
DD
µPD753208
µ
PD753208
P
nm
X1
X2
X1
X2
V
DD
V
DD
High
current
V
DD
A
B
C
V
DD
High current
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Figure 5-14. Example of Connecting Oscillator Incorrectly (2/2)
(e) Signal extracted
µPD753208
X1
X2
VDD
V
DD
(3) Divider circuit
The divider circuit divides the output of the system clock oscillation circuit (fX) to generate various clocks.
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5.2.3 Setting of CPU clock
(1) Time required to switch to/from CPU clocks
The CPU clock can be switched by using the low-order two bits of PCC. However, this clock switching is not
immediately made after the registers are rewritten, and the clock before the clock switching is made is used for
operation during given machine cycles. Thus, to stop system clock oscillation, a STOP instruction must be
executed after the switching time elapses.
Table 5-5. Maximum Time Required to Switch to/from CPU Clock
Setup value before switching
Setup value after switching
PCC1
0
PCC0
0
PCC1
0
PCC0
1
PCC1
1
PCC0
0
PCC1
1
PCC0
1
PCC1
PCC0
0
0
1
1
0
1
0
1
1 machine cycle
1 machine cycle
4 machine cycles
1 machine cycle
4 machine cycles
8 machine cycles
4 machine cycles
8 machine cycles
16 machine cycles
8 machine cycles
16 machine cycles
16 machine cycles
Caution The values of fX change depending on the environmental temperature of the oscillator and the
variance of load capacitance characteristics. When fX is high-order than its nominal value, the
machine cycles given in the table are larger than those obtained by the nominal value of fX.
Thus, when setting a wait time necessary for switching to/from CPU clock, it must be longer than
the machine cycle obtained by the nominal values of fX.
Remark The CPU clock Φ is supplied to the internal CPU and its inverse (defined to be 1 machine cycle in this
manual) is the minimum instruction execution time.
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(2) Switching procedure to/from CPU clock
The switching procedure CPU clock is explained according to Figure 5-15.
Figure 5-15. Switching to/from CPU Clock
On
Commercial power
supply
Off
Minimum operating
supply voltage
Voltage at VDD Pin
RESET signal
Wait
Wait Note 1
STOP
mode
System clock,
CPU clock
f
X
f
X
f
X
10.7 µs
Internal reset
operation
0.67 µs
0.67 µs
10.7
10.7
µs
µs
(f
X
= 6.0 MHz)
<1>
<2>
<3>
<4>
<1> After the wait time has elapsed (21.8/5.46 ms: 6.00 MHz) for stable oscillation by the RESET signal, the
CPU starts operation with the slowest speed (10.7 µs at 6.0 MHz or 15.3 µs at 4.19 MHz) of the system
clock.
<2> After a time long enough for the voltage at the VDD pin to rise to a value by which the CPU can operate
in the highest speed has elapsed, the contents of the PCC are written and the CPU starts operation in the
highest speed.
<3> When a power failure in the commercial power supply is detected by an interrupt inputNote 2, the value of
PCC is rewritten, the time necessary for the CPU to operate at the slowest speed elapses, and then the
STOP mode is set.
<4> Restoration of the commercial power supply is detected by an interrupt inputNote2, and the STOP mode is
released. After the wait time (set by BTM) during which the oscillation is stabilized has elapsed, the CPU
starts operation at the slowest speed of the system clock. When the sufficient time during which the voltage
on the VDD pin rises to the level at which the CPU can operate at the highest speed has elapsed, the value
of the PCC is rewritten, and the CPU operates at the highest speed.
Notes 1. The following two times can be selected by mask option:
2
17/fX (21.8 ms: 6.0 MHz, 31.3 ms: 4.19 MHz)
215/fX (5.46 ms: 6.0 MHz, 7.81 ms: 4.19 MHz)
However, the µPD75P3216 does not have a mask option and is fixed to 215/fX.
2. Use INT4 for this purpose.
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5.2.4 Clock output circuit
(1) Clock output circuit configuration
The configuration of the clock output circuit is shown in Figure 5-16.
(2) Clock output circuit function
The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the remote control
waveform outputs and peripheral LSI’s.
The clock pulses must be output in the following steps.
(a) Select a clock output frequency. Prohibit clock output.
(b) Write “0” in the output latch at P22.
(c) Set the I/O mode of the port 2 to output.
(d) Disable timer counter (channel 2) output.
(e) Enable clock output.
Figure 5-16. Clock Output Circuit Block Diagram
From clock
generator
From timer counter (Channel 2)
Φ
/23
/24
Output buffer
f
X
Selector
f
X
PCL/P22/PTO2
f
X
/26
PORT2.2
Bit 2 of PMGB
P22
output latch
Port 2 I/O mode
specification bit
CLOM3
0
CLOM1 CLOM0 CLOM
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output
when switching clock output enable/disable.
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(3) Clock output mode register (CLOM)
The CLOM is a 4-bit register which controls clock output.
It must be set by a 4-bit memory manipulation instruction.
Example The CPU clock Φ is output from the PCL/PTO2/P22 pin.
SEL
MB15
; or CLR1 MBE
MOV
MOV
A, #1000B
CLOM, A
CLOM is cleared to “0” by a RESET signal generation and the clock output is disabled.
Figure 5-17. Clock Output Mode Register Format
Address
FD0H
Symbol
CLOM
3
2
0
1
0
CLOM3
CLOM1 CLOM0
Clock output frequency select bit
When f
X
= 6.00 MHz
0
0
1
0
1
Φ output Note (1.5 MHz, 750 kHz, 375 kHz, 93.8 kHz)
0
1
1
fX/23 output (750 kHz)
fX/24 output (375 kHz)
fX/26 output (93.8 kHz)
When f
X
= 4.19 MHz
0
0
1
0
1
Φ output Note (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)
0
1
1
fX/23 output (524 kHz)
fX/24 output (262 kHz)
fX/26 output (65.5 kHz)
Note Φ is the CPU clock selected by the PCC.
Clock output enable/disable bit
0
1
Output disabled.
Output enabled.
Caution Be sure to set bit 2 of the CLOM to “0”.
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(4) Application example of remote control waveform output
The µPD753208 clock output function can be used for remote control waveform. The carrier frequency of remote
control waveform output is selected by the clock frequency select bit of the clock output mode register. The pulse
output enable/disable is selected by controlling the clock output enable/disable bit by software.
Special attention is paid not to output small-width pulses when switching clock output enable/disable.
Figure 5-18. Application Example of Remote Control Waveform Output
CLOM
bit 3
PCL pin
output
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5.3 Basic Interval Timer/Watchdog Timer
The µPD753208 is provided with the 8-bit basic interval timer/watchdog timer and has the following functions.
(a) Interval timer operation to generate a reference time interrupt
(b) Watchdog timer operation to detect a hung-up of program and reset the CPU
(c) Selects and counts the wait time when the standby mode is released
(d) Reads the contents of counting
5.3.1 Basic interval timer/watchdog timer configuration
The configuration of the basic interval timer/watchdog timer is shown in Figure 5-19.
Figure 5-19. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
Clear
Clear
fX
fX
fX
/25
/27
/29
BT
Basic interval timer
(8-bit frequency divider)
Set
MPX
interrupt
request flag
Vectored
interrupt
IRQBT request signal
BT
f
/212
X
3
Wait release signal
when standby is
released.
Internal reset
signal
WDTM
1
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1 Note
8
SET1 Note
Internal bus
Note Instruction execution
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5.3.2 Basic interval timer mode register (BTM)
The BTM is a 4-bit register which controls the operations of the basic interval timer (BT).
It is set by a 4-bit memory manipulation instruction.
Bit 3 can be set by a bit manipulation instruction.
Example The interrupt generation interval is set to 1.37 ms (6.00 MHz).
SEL
MB15
; or CLR1 MBE
CLR1
MOV
MOV
WDTM
A, #1111B
BTM, A
; BTM ← 1111B
When bit 3 is set to “1”, the contents of BT are cleared and the interrupt request flag of the basic interval timer/
watchdog timer (IRQBT) is also cleared (the start of the basic interval timer/watchdog timer).
Its contents are cleared to “0” by a RESET signal generation and the interrupt request signal generation interval
is set to the longest time.
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Figure 5-20. Basic Interval Timer Mode Register Format
Address
F85H
Symbol
0
3
2
1
BTM3 BTM2 BTM1 BTM0 BTM
When f = 6.00 MHz
X
Interrupt interval time
(wait time when standby is released)
220/fX (175 ms)
Clock input specification
0
0
1
1
0
1
0
1
0
1
1
1
fX/212 (1.46 kHz)
fX/29 (11.7 kHz)
fX/27 (46.9 kHz)
fX/25 (188 kHz)
Setting prohibited.
217/fX (21.8 ms)
215/fX (5.46 ms)
213/fX (1.37 ms)
Other than the
above
–
When f
X
= 4.19 MHz
Interrupt interval time
(wait time when standby is released)
220/fX (250 ms)
Clock input specification
0
0
1
1
0
1
0
1
0
1
1
1
fX/212 (1.02 kHz)
fX/29 (8.19 kHz)
fX/27 (32.768 kHz)
fX/25 (131 kHz)
217/fX (31.3 ms)
215/fX (7.81 ms)
213/fX (1.95 ms)
Other than the
above
Setting prohibited.
–
Start control bit of basic interval timer/watchdog timer
The basic interval timer/watchdog timer starts by writing “1”
(The counter and interrupt request flag are cleared).
Reset to "0" when the operation starts.
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5.3.3 Watchdog timer enable flag (WDTM)
The WDTM is a flag which enables reset signal generation by overflow.
It is set by a bit manipulation instruction. Once it is set, it cannot be cleared by an instruction.
Example Setting of watchdog timer
SEL
MB15
; or CLR1 MBE
SET1
WDTM
.
.
.
SET1
BTM.3
; Bit 3 of BTM is set to “1”.
The contents are cleared to “0” by a RESET signal generation.
Figure 5-21. Watchdog Timer Enable Flag (WDTM) Format
Address
F8BH.3
WDTM
BT mode:
0
1
Sets the IRQBT by the overflow of basic interval
timer (BT).
WT mode:
Generates an internal Reset signal by the overflow
of basic interval timer (BT).
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5.3.4 Basic internal timer (BT) operations
When WDTM is set to “0”, the interrupt request flag (IRQBT) is set by the overflow of the basic interval timer (BT)
and it operates as the interval timer. The basic interval timer (BT) always increments by the clock sent from the clock
generator and the counting operation cannot be stopped.
Four interrupt generation intervals can be set by BTM. (Refer to Figure 5-20.)
By setting bit 3 of the BTM to “1”, the basic interval timer (BT) and IRQBT can be cleared (start specification as
the interval timer).
The counting status can be read out from the basic interval timer (BT) by an 8-bit manipulation instruction. Note
that data cannot be entered.
Perform the timer operations as follows.
<1> Set an interval time to the BTM.
<2> Set bit 3 of the BTM to “1”.
These can be set at the same time.
Example Interrupts are generated every 1.37 ms (at 6.00 MHz operation).
SET1
SEL
MOV
MOV
EI
MBE
MB15
A, #1111B
BTM, A
; Time setting and start
; Interrupt enabled
EI
IEBT
; BT interrupt enabled
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5.3.5 Watchdog timer operations
When WDTM is set to “1” in the basic interval timer/watchdog timer, it performs as the watchdog timer wherein
an internal reset signal is generated by an overflow of the basic interval timer (BT). No reset signal, however, is
generated during the oscillation wait time following the STOP instruction has been released (When the WDTM is set
to “1” once, it can be cleared only by resetting). The basic interval timer (BT) always increments by the clock sent
from the clock generator and its counting operation cannot be stopped.
In the watchdog timer mode, program hung-up is detected by utilizing the interval timer wherein the BT overflows.
Four intervals can be selected by bits 0-2 of the BTM (Refer to Figure 5-20). Select one of them suitable for user’s
system. Set an interval and divide the program so that it can be executed in the interval and execute the instruction
which clears the BT at the ends of the divided program. If the instruction which clears the BT is not reached within
the time set (that is, the program is not executed normally = hung-up), the BT overflows and an internal reset signal
is generated to forcibly terminate the program. Namely, it indicates a program hung-up has occurred and been
detected.
Set the watchdog timer with the following procedure.
<1> Set the interval in the BTM.
<2> Set bit 3 of the BTM to “1”.
<3> Set WDTM to “1”.
Initialization
<4> Then, set bit 3 of the BTM to “1” within the interval.
The above steps <1> and <3> can be set at the same time.
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Example The basic interval timer/watchdog timer is used as the watchdog timer with 5.46 ms (during 6.00 MHz
operation).
The program is divided into several modules which end within the time set for the BTM (5.46 ms) and
the BT is cleared at the ends of the modules. In case a hung-up occurs, the BT is not cleared within
the time set, therefore it overflows and an internal Reset signal is generated.
Initialization :
SET1
SEL
MBE
MB15
MOV
MOV
SET1
A, #1101B
BTM, A
WDTM
: Sets time and starts
: Enables watchdog timer
(Then, the bit 3 of the BTM is set to “1” every 5.46 ms.)
Module 1 :
SET1
SEL
MBE
Processing is completed
within 5.46 ms.
MB15
BTM.3
SET1
Module 2 :
Processing is completed
within 5.46 ms
SET1
SEL
MBE
MB15
BTM.3
SET1
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5.3.6 Other functions
The basic interval timer/watchdog timer has the following functions regardless of the basic interval timer (BT)
operation and watchdog timer operation.
<1> Selects and counts the wait time after the standby mode is released.
<2> Reads the contents of counter.
(1) Selects and counts the wait time after the STOP mode is released
At the time the STOP mode is released, the system clock needs time for stablilizing oscillation. For this purpose,
the wait function is provided for the CPU to halt its operation until the basic interval timer (BT) overflows.
The wait time after a RESET signal generation is fixed by the mask option. However, it can be selected by setting
the BTM when the STOP mode is released by an interrupt generated. In this case, the wait time is the same
as the interval shown in Figure 5-20. The BTM must be set before the STOP mode is set. For details, refer to
CHAPTER 7 STANDBY FUNCTION.
Example The wait time is set to 5.46 ms at the time the STOP mode is released by an interrupt (during 6.00
MHz operation).
SET1
SEL
MBE
MB15
MOV
MOV
STOP
NOP
A, #1101B
BTM, A
; Sets time
; Sets the STOP mode
(2) Reads the counting operation
The basic interval timer (BT) can read the counting status by an 8-bit manipulation instruction. Note that data
cannot be entered.
Caution When reading the counting contents of the BT, execute the read instruction twice in order
not to read uncertain data while counting continues. If the two values read out are reasonable,
take the last one as the count data. If they are completely different, try the operation again.
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Examples 1. The counting contents of the BT is read out.
SET1 MBE
SEL MB15
MOV
LOOP : MOV
MOV
HL, #BT
XA, @HL
BC, XA
XA, @HL
XA, BC
LOOP
; Sets the address of BT to HL.
; First reading
MOV
; Second reading
SKE
BR
2. The high-level width of the pulses which are input to an INT4 interrupt (both edges are detected)
is set. The pulse width is assumed not to exceed the value set for the BT. The value set for
the BTM is assumed to be 5.46 ms or more (at 6.00 MHz operation).
<INT4 interrupt routine (MBE = 0)>
LOOP : MOV
MOV
MOV
SKE
XA, BT
BC, XA
XA, BT
A, C
; First reading
; Stores data
; Second reading
BR
LOOP
A, X
MOV
SKE
A, B
BR
LOOP
PORT0.0
AA
SKT
; P00=1?
BR
; NO
MOV
MOV
CLR1
RETI
XA, BC
BUFF, XA
FLAG
; Stores data in the data memory
; Data exists. Clears the flag.
AA :
MOV
MOV
SUBC
INCS
MOV
MOV
SUBC
MOV
MOV
MOV
SET1
RETI
HL, #BUFF
A, C
A, @HL
L
C, A
A, B
A, @HL
B, A
XA, BC
BUFF, XA
FLAG
; Stores data
; Data exists. Sets the flag.
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5.4 Watch Timer
The µPD753208 is provided with a 1-channel of watch timer. This watch timer has the following functions:
(a) Sets the test flag (IRQW) with 0.5 sec interval.
The standby mode can be released by the IRQW.
(b) 0.5 sec interval can be created by the system clock. Take fX = 4.194304 MHz for the system clock frequency
in this case.
(c) Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast
feed mode.
(d) Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming of
system clock frequencies.
(e) Clears the frequency divider to make the clock start with zero seconds.
5.4.1 Configuration of watch timer
Figure 5-22 shows the configuration of the watch timer.
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Figure 5-22. Watch Timer Block Diagram
f
W
26
(512 Hz : 1.95 ms)
(256 Hz : 3.91 ms)
f
LCD
f
W
27
f
X
Selector
From
clock
generator
128
f
W
214
f
W
INTW
IRQW
(32.768 kHz)
(32.768 kHz)
Selector
Divider
set signal
2 Hz
4 kHz 2 kHz
0.5 sec
fW
f
W
24
Clear
23
VDD
Selector
Output buffer
P23/BUZ
WM
WM7
PORT2.3
PMGB bit 2
Port 2 input/
Note 1
Note 2
P23
output-latch
0
WM5 WM4
WM2 WM1
WM0
WM3
output mode
8
Internal bus
Notes 1. WM3 is undefined when data is read.
2. Be sure to set 0 to WM0.
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz.
5.4.2 Watch mode register
The watch mode register (WM) is an 8-bit register that controls the watch timer. This register is manipulated by
an 8-bit memory manipulation instruction. Figure 5-23 shows the format of this regsiter.
Be sure to set bit 0 of the watch mode register to 0. Bit 6 is fixed to 0. Bit 3 is undefined when data is read from
this bit.
All the bits of the watch mode register, except bit 3, are cleared to “0” at RESET.
Example Make a time by the system clock (4.19 MHz). Enable buzzer output.
CLR1
MOV
MOV
MBE
XA, #84H
WM, XA
; Sets the WM
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-23. Format of Watch Mode Register
Address
F98H
7
6
0
5
4
3
Note 1
2
1
0
Note 2
Symbol
WM
WM7
WM5 WM4
WM2 WM1
WM0
WM3
BUZ output enable/disable bit
WM7
0
1
Disables BUZ output.
Enables BUZ output.
BUZ output frequency select bit
WM5 WM4 BUZ output frequency
f
W
0
0
1
1
0
1
0
1
(2.048 kHz)
(4.096 kHz)
24
W
f
23
Setting prohibited.
f
W
(32.768 kHz)
Watch operation enable/disable bit
WM2
0
1
Stops watch operation (clears the frequency divider).
Watch operation possible.
Operation mode select bit
f
W
214
WM1
0
1
Normal watch mode (
: sets the IRQW in 0.5 sec).
f
W
Fast watch mode (
: sets the IRQW in 3.91 ms).
27
Notes 1. WM3 is undefined when data is read.
2. Be sure to set 0 to WM0.
Remark The function in parentheses is available when fW = 32.768 kHz.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
5.5 Timer/Event Counter
The µPD753208 has one timer/event counter channel (channel 0) and two timer counter channels (channels 1
and 2). Figure 5-24 through 5-26 show the configuration of these channels.
In this section, the timer/event counter and timer counters are referred to as “timer/event counters”. When you
read this section for description of channels 1 and 2, take “timer/event counter” as “timer counter”.
The timer/event counter has the following functions.
(a) Programmable interval timer operation
(b) Square wave output of any frequency to the PTOn pin.
(c) Event counter operation (Channel 0 only)
(d) Divides the frequency of signal input via the TI0 pin to 1-Nth of the original signal and outputs the divided frequency
to the PTO0 pin (frequency divider operation).
(e) Supplies the serial shift clock to the serial interface circuit.
(f) Calls the counting status.
The timer/event counter operates in the following four modes as set by the mode register.
Table 5-6. Operation Modes of Timer/Event Counter
Channel Channel 0 Channel 1 Channel 2 2
Mode
8-bit timer/event counter mode
Note 1
●
●
×
●
●
●
Note 2
Gate control function
×
×
×
×
×
PWM pulse generator mode
16-bit timer counter mode
×
●
●
●
Note 2
Gate control function
Carrier generator mode
Notes 1. This mode is available for channel 0 only. This mode is an 8-bit timer counter mode with
channels 1 and 2.
2. This function is used to generate a gate control signal.
5.5.1 Configuration of timer/event counter
Figure 5-24 to 5-26 shows the configuration of the timer/event counter.
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Figure 5-24. Timer/Event Counter Block Diagram (channel 0)
Internal bus
8
SET1 Note
8
8
TOE0
PORT2.0
PMGB bit 2
TMOD0
TM0
–
Port 2
T0
enable flag
P20
Modulo register (8)
8
input/output
mode
–
TM06 TM05 TM04 TM03 TM02
0
output latch
To serial interface
TOUT0
PORT1.3
Match
TOUT
F/F
Comparator (8)
8
P20/PTO0
Output buffer
Input
Reset
buffer
T0
TI0
INTT0
IRQT0
set signal
Count register (8)
Clear
fX
fX
fX
fX
/24
MPX
CP
/26
/28
/210
From
clock
generator
Timer operation start
RESET
IRQT0
clear signal
Note Instruction execution
To timer counter (channel 2)
Caution When setting data to TM0, be sure to set 0 to bit 1.
Figure 5-25. Timer Counter Block Diagram (channel 1)
Internal bus
SET1 Note
8
TOE1
PORT2.1
PMGB bit 2
TM1
Port 2
input/output
mode
8
T1
enable flag
P21
output latch
–
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Decoder
TMOD1
Modulo register (8)
8
P21/PTO1
Match
TOUT
F/F
Comparator (8)
8
Timer counter
output (channel 2)
Output buffer
Reset
f
f
f
f
f
X
X
X
X
X
/25
T1
/26
Count register (8)
Clear
MPX
From clock
generator
CP
/28
/210
/212
RESET
Timer operation start
16 bit timer counter mode
IRQT1 clear signal
Selector
INTT1
IRQT1
set signal
Timer counter match signal (channel 2)
(When 16-bit timer counter mode)
Timer counter reload signal (channel 2)
Timer counter comparator (channel 2)
(When 16-bit timer counter mode)
Note Instruction execution
Figure 5-26. Timer Counter Block Diagram (channel 2)
Internal bus
SET1 Note
8
8
8
8
TMOD2H
TMOD2
TC2
PORT2.2 PMGB bit 2
TM2
High-level period setting
modulo register (8)
P22
Port 2
Modulo register (8)
8
TM26 TM25 TM24 TM23 TM22 TM21 TM20
TGCE
TOE2 REMC NRZB NRZ
Reload
output latch input/output
8
Decoder
MPX (8)
P22/PCL/PTO2
8
Match
Output buffer
TOUT
F/F
Comparator (8)
f
f
f
f
f
f
X
X
X
X
X
X
Reset
8
/2
Timer counter clock
input (channel 1)
T2
Overflow
Carrier generator mode
/24
/26
/28
/210
From clock
generator
Count register (8)
Clear
MPX
CP
INTT2
IRQT2
set signal
16-bit timer counter mode
IRQT2 clear signal
Timer operation start
RESET
Timer counter clear
signal (channel 1)
(When 16-bit timer
counter mode)
Timer event counter
TOUT F/F (channel 0)
From clock
generator
Timer counter match
Timer counter match
signal (channel 1) (When
carrier generator mode)
signal (channel 1)
(When 16-bit timer
counter mode)
Note Instruction execution
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(1) Timer/event counter mode register (TM0, TM1, TM2)
The mode register (TMn) is an 8-bit register which controls the timer/event counter.
Its format is shown in Figures 5-27 to 5-29.
The timer/event counter mode register is set by an 8-bit memory manipulation instruction.
Bit 3 is a timer start bit and can be operated bit-wise. It is automatically reset to “0” when the timer operation
starts.
All the bits of the timer/event counter mode register are cleared to “0” by a RESET signal generation.
Examples 1. Start the timer in the interval timer mode of CP = 5.86 kHz (during 6.00 MHz operation).
SEL
MB15
; or CLR1 MBE
MOV
MOV
XA, #01001100B
TMn, XA
; TMn ← 4CH
2. Restart the timer according to the setting of the timer/event counter mode register.
SEL
MB15
TMn.3
; or CLR1 MBE
SET1
; TMn.bit3 ← 1
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Figure 5-27. Timer/Event Counter Mode Register (channel 0) Format
Address
FA0H
7
6
5
4
3
2
1
0
0
Symbol
TM0
TM06 TM05 TM04 TM03 TM02
Count pulse (CP) selection bit
When fX = 6.00 MHz
TM06 TM05 TM04
Count pulse (CP)
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
TI0 rising edge
TI0 falling edge
fX/210 (5.86 kHz)
fX/28 (23.4 kHz)
fX/26 (93.8 kHz)
fX/24 (375 kHz)
Setting prohibited.
Other than above
When fX = 4.19 MHz
TM06 TM05 TM04
Count pulse (CP)
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
TI0 rising edge
TI0 falling edge
fX/210 (4.10 kHz)
fX/28 (16.4 kHz)
fX/26 (65.5 kHz)
fX/24 (262 kHz)
Setting prohibited.
Other than above
Timer start indication bit
TM03 When 1 is written into the bit, the counter and IRQT0 flag are cleared.
If bit 2 is set to 1, count operation is started.
Operation mode
TM02
Count operation
Stop (retention of count contents)
Count operation
0
1
Caution When setting data to TM0, be sure to set 0 to bit 1.
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Figure 5-28. Timer Counter Mode Register (channel 1) Format (1/2)
Address
FA8H
7
6
5
4
3
2
1
0
Symbol
TM1
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Count pulse (CP) select bit
When f = 6.00 MHz
X
TM16 TM15 TM14
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
Timer output of timer counter channel 2
fX
fX
fX
fX
fX
/25 (188 kHz)
/212 (1.46 kHz)
/210 (5.86 kHz)
/28 (23.4 kHz)
/26 (93.8 kHz)
When f = 4.19 MHz
X
TM16 TM15 TM14
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
Timer output of timer counter channel 2
f
f
f
f
f
X
X
X
X
X
/25 (131 kHz)
/212 (1.02 kHz)
/210 (4.10 kHz)
/28 (16.4 kHz)
/26 (65.5 kHz)
Timer start indication bit
TM13 When 1 is written into the bit, the counter and IRQT1 flag are cleared.
If bit 2 is set to 1, count operation is started.
Operation mode
TM12
Count operation
Stop (retention of count contents)
Count operation
0
1
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-28. Timer Counter Mode Register (channel 1) Format (2/2)
Operation mode select bit
TM11 TM10
Mode
0
1
0
0
8-bit timer counter modeNote
16-bit timer counter mode
Setting prohibited.
Other than
the above
Note When it is used in combination with the TM20 and TM21 (=11) of the
timer counter mode register (channel 2), it enters the carrier generator mode.
Figure 5-29. Timer Counter Mode Register (channel 2) Format (1/2)
Address
F90H
7
6
5
4
3
2
1
0
Symbol
TM2
TM26 TM25 TM24 TM23 TM22 TM21 TM20
Count pulse (CP) select bit
When f
X
= 6.00 MHz
TM26 TM25 TM24
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
fX
fX
fX
fX
fX
fX
/2 (3.00 MHz)
(6.00 MHz)
/210 (5.86 kHz)
/28 (23.4 kHz)
/26 (93.8 kHz)
/24 (375 kHz)
When f = 4.19 MHz
X
TM26 TM25 TM24
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
fX
fX
fX
fX
fX
fX
/2 (2.10 MHz)
(4.19 MHz)
/210 (4.10 kHz)
/28 (16.4 kHz)
/26 (65.5 kHz)
/24 (262 kHz)
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-29. Timer Counter Mode Register Format (channel 2) (2/2)
Timer start indication bit
TM23 When “1” is written into the bit, the counter and IRQT2 flag are cleared.
If bit 2 is set to 1, count operation is started.
Operation mode
TM22
Count operation
Stop (retention of count contents)
Count operation
0
1
Operation mode select bit
TM21 TM20
Mode
0
0
1
1
0
1
0
1
8-bit timer counter mode
PWM pulse generator mode
16-bit timer counter mode
Carrier generator mode
(2) Timer/event counter output enable flag (TOE0, TOE1)
The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0 and
PTO1 pins in the timer out F/F (TOUT F/F) status.
The timer out F/F flips by the match signal sent from the comparator. When bit 3 of the timer/event counter mode
register (TM0, TM1) is set to “1”, the timer out F/F is cleared to “0”.
TOE0, TOE1, and timer out F/F are cleared to “0” by a RESET signal generation.
Figure 5-30. Timer/Event Counter Output Enable Flag Format
Address
FA2H
FAAH
TOE0
TOE1
Channel 0
Channel 1
Timer/event counter output enable flag (W)
0
1
Disabled.
Enabled.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(3) Timer counter control register (TC2)
The timer counter control register (TC2) is an 8-bit register which controls the timer counter (channel 2). Its format
is shown in Figure 5-31.
The timer/event counter control register (TC2) is set by an 8-bit/4-bit memory manipulation instruction and a bit
manipulation instruction.
All the bits of the timer/event counter control register (TC2) are cleared to “0” by the internal reset signal
generation.
Figure 5-31. Timer Counter Control Register Format
Address
F92H
7
6
5
4
3
2
1
0
Symbol
TC2
TGCE
TOE2 REMC NRZB NRZ
Gate control enable flag
TGCE
Gate control
0
Disabled.
(If bit 2 of the TM2 is set to “1”, the count operation is performed
regardless of the sampling clock status.)
1
Enabled.
(If bit 2 of the TM2 is set to “1”, the count operation is performed when
the sampling clock is high, and is stopped when the sampling clock is low)
Timer output enable flag
TOE2
Timer output
Disabled (outputs the low level).
Enabled.
0
1
Remote control output control flag
REMC
Remote control output
0
1
Outputs the carrier pulse when NRZ = 1.
Output a high-level signal when NRZ = 1.
No return zero buffer flag
NRZB No return zero data to be output next. Transferred to the NRZ when a
timer counter (channal 1) interrupt is generated.
No return zero flag
NRZ
No return zero data
Outputs a low-level signal.
0
1
Outputs the carrier pulse or high-level signal.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
5.5.2 8-bit timer/event counter mode operation
It is used as an 8-bit timer/event counter in this mode. It performs an 8-bit programmable interval timer and event
counter operation (channel 0 only).
(1) Register setting
The following four registers are used in the 8-bit timer/event counter mode.
•
•
•
•
Timer/event counter mode register (TMn)
Timer counter control register (TC2)Note
Timer/event counter count register (Tn)
Timer/event counter modulo register (TMODn)
Note Channels 0 and 1 of the timer/event counter use the timer/event counter output enable flags (TOE0 and
TOE1).
(a) Timer/event counter mode register (TMn)
When the 8-bit timer/event counter mode is used, TMn must be set as shown in Figure 5-32 (For the format
of the TMn, refer to Figures 5-27 to 5-29).
The TMn is manipulated by an 8-bit manipulation instruction. Bit 3 is a timer start indication bit and can be
manipulated bit-wise and is automatically cleared to “0” when the timer starts.
The TMn is cleared to 00H when an internal reset signal is generated.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-32. Timer/Event Counter Mode Register Setup (1/3)
(a) In the case of timer/event counter (channel 0)
Address
FA0H
7
6
5
4
3
2
1
0
0
Symbol
TM0
TM06 TM05 TM04 TM03 TM02
Count pulse (CP) selection bit
TM06 TM05 TM04
Count pulse (CP)
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
TI0 rising edge
TI0 falling edge
f
f
f
f
X
X
X
X
/210
/28
/26
/24
Other than above
Setting prohibited.
Timer start indication bit
TM03
When “1” is written into the bit, the counter and IRQT0 flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TM02
Count operation
Stop (retention of count contents)
Count operation
0
1
Caution When setting data to TM0, be sure to set 0 to bit 1.
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Figure 5-32. Timer/Event Counter Mode Register Setup (2/3)
(b) In the case of timer counter (channel 1)
Address
FA8H
7
6
5
4
3
2
1
0
Symbol
TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM1
Count pulse (CP) selection bit
TM16 TM15 TM14
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
Timer counter channel 2 timer output
f
f
f
f
f
X
X
X
X
X
/25
/212
/210
/28
/26
Timer start indication bit
TM13
When “1” is written to the bit, the counter and IRQT1 flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TM12
Count operation
Stop (retention of count contents)
Count operation
0
1
Operation mode selection bit
TM11 TM10
Mode
0
0
8-bit timer counter mode
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Figure 5-32. Timer/Event Counter Mode Register Setup (3/3)
(c) In the case of timer counter (channel 2)
Address
F90H
7
6
5
4
3
2
1
0
Symbol
TM26 TM25 TM24 TM23 TM22 TM21 TM20 TM2
Count pulse (CP) selection bit
TM26 TM25 TM24
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
f
f
f
f
f
f
X
X
X
X
X
X
/2
/210
/28
/26
/24
Timer start indication bit
TM23
When “1” is written to the bit, the counter and IRQT2 flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TM22
Count operation
Stop (retention of count contents)
Count operation
0
1
Operation mode selection bit
TM21 TM20
Mode
0
0
8-bit timer counter mode
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(b) Timer counter control register (TC2)
Figure 5-33 shows the setting of the timer counter (channel 2) when it is used in an 8-bit timer counter mode
(Refer to Figure 5-35. Timer Counter Control Register Format).
The TC2 is manipulated by an 8-bit/4-bit manipulation instruction and bit manipulation instruction.
The TC2 is cleared to 00H by an internal reset signal.
The flag indicated by the full lines indicates a flag which is used in the 8-bit timer counter mode.
The flag indicated by the broken lines must not be used in the 8-bit timer counter mode. Set 0.
Figure 5-33. Timer Counter Control Register Setup
7
6
5
4
3
2
1
0
Symbol
TC2
TGCE
TOE2 REMC NRZB NRZ
Gate control enable flag
TGCE
Gate control
0
Disabled.
(If bit 2 of the TM2 is set to “1”, the count operation is performed
regardless of the status of the sampling clock.)
Enabled.
1
(If bit 2 of the TM2 is set to “1”, the count operation is performed when
the sampling clock is high, and is stopped when the sampling clock is low.)
Timer output enable flag
TOE2
Timer output
0
1
Disabled (outputs the low-level signal).
Enabled.
Figure 5-34. Timer/Event Counter Output Enable Flag Setup
Address
FA2H
FAAH
TOE0
TOE1
Channel 0
Channel 1
Timer/event counter output enable flag (W)
0
1
Disabled (outputs the low-level signal).
Enabled.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(2) Timer/event counter time setting
[Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency]
selected by setting the mode register.
n+1
fCP
T (sec) =
= (n + 1)·(resolution)
T (sec) : Timer setup time (seconds)
fCP (Hz) : Count pulse frequency (Hz)
n
: Modulo register content (n ≠ 0)
Once the timer is set, interrupt request signal (IRQTn) is generated at the intervals set in the timer.
Table 5-7 lists the resolution and longest setup time (time when FFH is set in the modulo register) for each count
pulse to the timer/event counter.
Table 5-7. Resolution and Longest Setup Time (8-bit timer) (1/2)
(a) When timer/event counter (channel 0)
Mode register
At 6.0 MHz
Longest setup time
At 4.19 MHz
Longest setup time
TM06
TM05
TM04
Resolution
171 µs
Resolution
244 µs
1
1
1
1
0
0
1
1
0
1
0
1
43.7 ms
10.7 ms
2.73 ms
683 µs
62.5 ms
15.6 ms
3.91 ms
977 µs
42.7 µs
10.7 µs
2.67 µs
61.0 µs
15.3 µs
3.81 µs
(b) When timer counter (channel 1)
Mode register
At 6.0 MHz
At 4.19 MHz
TM16
TM15
TM14
Resolution
Longest setup time
1.37 ms
Resolution
7.64 µs
977 µs
Longest setup time
1.95 ms
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
5.33 µs
683 µs
171 µs
42.7 µs
10.7 µs
175 ms
250 ms
43.7 ms
244 µs
62.5 ms
10.9 ms
61.0 µs
15.3 µs
15.6 ms
2.73 ms
3.91 ms
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Table 5-7. Resolution and Longest Setup Time (8-bit timer) (2/2)
(c) When timer counter (channel 2)
Mode register
At 6.0 MHz
Longest setup time
At 4.19 MHz
TM26
TM25
TM24
Resolution
333 ns
Resolution
477 ns
Longest setup time
122 µs
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
85.3 µs
42.7 µs
43.7 ms
10.9 ms
2.73 ms
683 µs
167 ns
239 ns
61.1 µs
171 µs
244 µs
62.5 ms
42.7 µs
10.7 µs
2.67 µs
61.0 µs
15.3 µs
3.81 µs
15.6 ms
3.91 ms
977 µs
(3) Timer/event counter operation
The timer/event counter operates as follows. In the operation with timer counter (channel 2), the gate control
enable flag (TGCE) of the timer counter control register (TC2) must be set to 0.
Figure 5-35 shows the configuration of the timer/event counter.
<1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register
(Tn).
<2> The Tn is compared with the modulo register (TMODn), and if they are equal, a match signal is generated
and the interrupt request flag (IRQTn) is set. At the same time, the timer out flip-flop (TOUT F/F) flips.
Figure 5-36 is a timing chart of the timer/event counter.
The timer/event counter normally begins operation in the following procedure.
<1> Set a count in the TMODn.
<2> Set the operating mode, count pulse, and start indication in the TMn.
Caution Set a value other than 00H in the modulo register (TMODn).
When using the timer/event counter output pin (PTOn), set the dual function pin P2n as follows.
<1> Clear the output latch of P2n.
<2> Set port 2 to the output mode.
<3> Make a status wherein the internal pull-up resistor is not connected in port 2.
<4> Set the timer/event counter output enable flag (TOEn) to 1.
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Figure 5-35. Configuration of Timer/Event Counter
INTTn
(IRQTn set signal)
Modulo register (TMODn)
Comparator
TI0Note
Match
TOUT F/F
PTOn
MPX
Internal
clock
CP
To serial interface Note
Count register (Tn)
Clear
Note Channel 0 of the timer/event counter only.
Figure 5-36. Count Operation Timing
Count pulse(CP)
m
Modulo register
(TMODn)
Count register
(Tn)
0
1
2
m–1
m
0
1
2
m–1
m
0
1
2
3
4
Match
Match
Reset
TOUT F/F
Timer start indication
Remark m: Set value of modulo register
n : 0-2
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(4) Counter operation with gate control function (8-bit)
The timer counter (channel 2) can be used as a counter with a gate control function. Set the gate control enable
flag (TGCE) of the timer counter control register to 1 when using this function.
When timer/event counter channel 0 counts to the specified number, the gate signal is generated.
When the gate signal (output of TOUT F/F of T0) is high, the count pulses of timer counter channel 2 can be
counted as shown in Figure 5-38 (for details, refer to (3) Timer/event counter operation).
<1> The count pulse (CP) is selected by setting the mode register (TM2), and the CP is input to the count register
(T2) when the gate signal is high.
<2> Interrupt is generated at the rising edge and falling edge of the gate signal. Normally, the contents of the
T2 are read out by an interrupt subroutine at the falling edge and the T2 is cleared for the subsequent count
operation.
Figure 5-38 shows the timing chart of the counter.
The counter normally starts operation by the following procedure.
<1> Set the operation mode, count pulse, and counter clear indication in the TM2.
<2> Set the number of count in the TMOD0.
<3> Set the operation mode, and start indication in the TM0.
Caution A value other than 00H must be set in the modulo register (TMOD0, TMOD2).
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Figure 5-37. Configuration of Event Count
INTT0
(IRQT0 set signal)
Modulo register (TMOD0)
Match
TI0
TOUT
F/F
Comparator
PTO0
MPX
Internal
clock
CP
Count register (T0)
Clear
INTT2
(IRQT2 set signal)
Modulo register (TMOD2)
Match
TOUT
F/F
PTO2
Internal
clock
Comparator
MPX
Count register (T2)
Clear
CP
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Figure 5-38. Count Operation Timing
Count pulse
(CP)
Modulo register
(TMOD0)
m
Count register
(T0)
0
1
2
m–1
m
0
1
2
m–1
m
0
1
2
3
4
Match
Match
Reset
Gate signal
(TOUT F/F)
IRQT0 set
IRQT0 set
Count disable
Count enable
Count disable
Event input
(TI0)
Count register
(T2)
0
1
2
m–2 m–1
n
Counter clear indication
Timer start indication
Remark m: Set value of modulo register
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(5) 8-bit timer/event counter mode application
(a) Use as an interval timer which causes an interrupt to occur at 50 ms intervals.
•
Set the high-order four bits of the mode register (TM2) to 0100B to select the longest setup time 62.5
ms (when fX = 4.19 MHz)
•
•
Set the low-order four bits of the TM2 to 1100B.
The value set in the modulo register (TMOD2) is as follows:
50 ms
244 µs
= 205, 205 – 1 = CCH
<Program example>
SEL
MOV
MOV
MOV
MOV
EI
MB15
; or CLR1 MBE
; Set modulo
XA, #0CCH
TMOD2, XA
XA, #01001100B
TM2, XA
; Set mode and start timer
; Enable interrupt
EI
IET2
; Enable timer interrupt
Remark In this example, the TI0 pin can be used as an input pin.
(b) Generate an interrupt when the number of pulses input from the TI0 pin reaches 100. (Channel 2 only. The
pulses are active high.)
•
•
•
Set the high-order four bits of the mode register (TM0) to 0000 to select rising edge.
Set the low-order four bits of the TM0 to 1100B.
The value set in the modulo register (TMOD0) is 99 = 100 – 1.
<Program example>
SEL
MOV
MOV
MOV
MOV
EI
MB15
; or CLR1 MBE
; Set modulo
XA, #100 – 1
TMOD0, XA
XA, #00001100B
TM0, XA
; Set mode, start count
; Enable INTT0
EI
IET0
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5.5.3 PWM pulse generator mode (PWM mode) operation
It performs as an 8-bit PWM pulse generator in this mode.
(1) Register setting
The following five registers are used in the PWM mode.
•
•
•
•
•
Timer counter mode register (TM2)
Timer counter control register (TC2)
Timer counter count register (T2)
Timer counter high-level period setting modulo register (TMOD2H)
Timer counter modulo register (TMOD2)
(a) Timer counter mode register (TM2)
When using the PWM mode, set the TM2 as shown in Figure 5-39. For the format of the TM2, Refer to Figure
5-29. Timer Counter Mode Register Format (channel 2).
The TM2 is manipulated by an 8-bit manipulation instruction. Bit 3 is a timer start indication bit. It can be
manipulated bit-wise and is automatically cleared to 0 when the timer starts.
The TM2 is cleared to 00H when an internal reset signal is generated.
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Figure 5-39. Timer Counter Mode Register Setup
Address
F90H
7
6
5
4
3
2
1
0
Symbol
TM26 TM25 TM24 TM23 TM22 TM21 TM20 TM2
Count pulse (CP) selection bit
TM26 TM25 TM24
Count pulse (CP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Setting prohibited
fX/2
fX
fX/210
fX/28
fX/26
fX/24
Timer start indication bit
TM23
When “1” is written to the bit, the counter and IRQT2 flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TM22
Count operation
Stop (retention of count contents)
Count operation
0
1
Operation mode selection bit
TM21 TM20
Mode
0
1
PWM pulse generator mode
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(b) Timer counter control register (TC2)
When using the PWM mode, set the TC2 as shown in Figure 5-40 (Refer to Figure 5-31. Timer Counter
Control Register Format).
The TC2 is manipulated by an 8-bit/4-bit manipulation instruction and bit operation instruction.
The TC2 is cleared to 00H by an internal reset signal.
The flag indicated by the full lines is used in the PWM mode.
The flag indicated by the broken lines must not be used for the PWM mode. Set 0.
Figure 5-40. Timer Counter Control Register Setup
7
6
5
4
3
2
1
0
Symbol
TC2
TGCE
TOE2 REMC NRZB NRZ
Timer output enable flag
TOE2
Timer output
0
1
Disabled (output the low-level signal).
Enabled.
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(2) PWM pulse generator operation
The PWM pulse generator operates as follows. Figure 5-41 shows its configuration.
<1> When the mode register (TM2) is set, the count pulse (CP) is selected and input to the count register (T2).
<2> The contents of the T2 are compared with those of the high-level period setting modulo register (TMOD2H),
and if they are equal, a match signal is generated and the timer out flip-flop (TOUT F/F) flips.
<3> The contents of the T2 are compared with those of the modulo register (TMOD2), and if they are equal,
a match signal is generated and an interrupt request flag (IRQT2) is set. At the same time, the TOUT F/
F flips.
<4> The above operations <2> and <3> repeat alternatively.
Figure 5-42 shows the timing chart of the PWM pulse generator.
The PWM pulse generator normally starts operation in the following procedure.
<1> Set the number of count in the TMOD2H.
<2> Set the number of low-level count in the TMOD2.
<3> Set the operating mode and count pulse start indication in the TM2.
Caution Set values other than 00H in the modulo register (TMOD2) and high-level period setting
modulo register (TMOD2H).
When using the timer counter output pin PTO2, set the dual function pins P22 and PCL as follows.
<1> Clear the output latch of P22.
<2> Set port 2 to output mode.
<3> Do not connect the internal pull-up resistor to port 2, and disable output of PCL.
<4> Set the timer counter output enable flag (TOE2) to 1.
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Figure 5-41. Configuration of PWM Pulse Generator
High-level period setting modulo register (TMOD2H)
Modulo register (TMOD2)
INTT2
(IRQT2 set signal)
MPX
Match
Internal
clock
TOUT F/F
PTO2
Comparator
MPX
CP
Count register (T2)
Clear
Figure 5-42. PWM Pulse Generator Operation Timing
Count pulse
(CP)
High-level period
setting modulo register
(TMOD2H)
m
n
Modulo register
(TMOD2)
Count register
(T2)
0
1
2
m–1
m
0
1
2
n–1
n
0
1
2
3
4
Match
Match
Set
TOUT F/F
IRQT2 set
Timer start indication
Remark m: Set value of high-level period setting modulo register
n : Set value of modulo register
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(3) PWM mode application
The pulses (frequency is 38.0 kHz (cycle is 26.3 µs) and duty ratio is 1/3) are output to the PTO2 pin.
•
•
Set the high-order 4 bits of the mode register (TM2) to 0011B and select the longest setup time 61.1 µs.
Set the low-order 4-bits of the TM2 to 1101B and select the PWM mode and count operation and indicate timer
start.
•
•
Set the timer output enable flag (TOE2) to “1” and enable the timer output.
The high-level time setting modulo register (TMOD2H) is set as follows.
1
3
26.3 µs
239 ns
.
– 1 = 36.7 – 1 = 36 = 24H
·
.
•
The modulo register (TMOD2) is set as follows.
.
2
3
26.3 µs
239 ns
– 1 = 73.4 – 1 = 72 = 48H
.
·
<Program example>
SEL
MB15
; or CLR1 MBE
SET1
MOV
MOV
MOV
MOV
MOV
MOV
TOE2
; Enables timer output.
XA, #024H
TMOD2H, XA
XA, #48H
TMOD2, XA
XA, #00111101B
TM2, XA
; Sets the modulo (high-level period).
; Sets the modulo (low-level period).
; Sets the mode and timer start.
Remark In this application, TI0 is used as input pins.
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5.5.4 16-bit timer counter mode operation
Used as a 16-bit timer counter in this mode. It performs 16-bit programmable interval timer and count operations.
When it is used in the 16-bit timer counter mode, the channel 1 and channel 2 of the timer counter are used in
combination.
(1) Register setting
The following seven registers are used in the 16-bit timer counter mode.
•
•
•
•
Timer counter mode registers (TM1, TM2)
Timer counter control register (TC2)Note
Timer counter count registers (T1, T2)
Timer counter modulo registers (TMOD1, TMOD2)
Note The timer counter (channel 1) uses the timer counter output enable flag (TOE1).
(a) Timer counter mode registers (TM1, TM2)
When using the 16-bit timer counter mode, set the TM1 and TM2 as shown in Figure 5-43. For the formats
of the TM1 and TM2, refer to Figure 5-28. Timer Counter Mode Register (channel 1) Format and Figure
5-29. Timer Counter Mode Register (channel 2) Format, respectively.
The TM1 and TM2 are manipulated by 8-bit manipulation instructions. Bit 3 is a timer start indication bit and
can be manipulated bit-wise and is automatically cleared to 0 when the timer starts.
The TM1 and TM2 are cleared to 00H by an internal reset signal.
The flag indicated by the full lines expresses a bit used in the 16-bit timer counter mode.
The flag indicated by the broken lines must not be used in the 16-bit timer counter mode. Set 0.
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Figure 5-43. Timer Counter Mode Register Setup
Address
FA8H
7
6
5
4
3
2
1
0
Symbol
TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM1
TM26 TM25 TM24 TM23 TM22 TM21 TM20 TM2
Count pulse (CP) selection bit (n = 1, 2)
F90H
TMn6 TMn5 TMn4
TM1
Setting prohibited
TM2
Setting prohibited
Setting prohibited
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Timer counter (channel 2) timer output
f
f
f
f
f
f
X
X
X
X
X
X
/2
f
f
f
f
f
X
X
X
X
X
/25
/212
/210
/28
/210
/28
/26
/24
/26
Timer start indication bit
TM23
When “1” is written to the bit, the counter and IRQTn flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TM22
Count operation
Stop (retention of count contents)
Count operation
0
1
Operation mode selection bit
TM20 TM11 TM10
TM21
1
Mode
16-bit timer counter mode
0
1
0
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(b) Timer counter control register (TC2)
When using the 16-bit timer counter mode, set the TC2 as shown in Figure 5-44. For the format of the TC2,
refer to Figure 5-31. Timer Counter Control Register Format.
The TC2 is manipulated by an 8-bit/4-bit manipulation instruction and bit manipulation instruction.
The TC2 is cleared to 00H by an internal reset signal.
The flag indicated by the full lines is a flag used in the 16-bit timer counter mode.
The flag indicated by the broken lines must not be used in the 16-bit timer counter mode. Set 0.
Figure 5-44. Timer Counter Control Register Setup
7
6
5
4
3
2
1
0
Symbol
TC2
TGCE
TOE2 REMC NRZB NRZ
Gate control enable flag
TGCE
Gate control
0
Disabled.
(If the bit 2 of the TM2 is set to “1”, the count opration is performed
regardless of the status of sampling clock.)
Enabled.
1
(If the bit 2 of the TM2 is set to “1”, the count opration is performed
when the sampling clock is high and is stopped when the sampling
clock is low.)
Timer output enable flag
TOE2
Timer output
0
1
Disabled (outputs the low level signal).
Enabled.
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(2) Timer/event counter time setting
[Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency]
selected by setting the mode register.
n+1
fCP
T (sec) =
= (n + 1)·(resolution)
T (sec) : Timer setup time (seconds)
fCP (Hz) : Count pulse frequency (Hz)
n
: Modulo register content (n ≠ 0)
Once the timer is set, interrupt request signal (IRQT2) is generated at the intervals set in the timer.
Table 5-8 lists the resolution and longest setup time (time when FFH is set in the modulo register) for each
count pulse to the timer counter.
Table 5-8. Resolution and Longest Setup Time (16-bit timer)
(a) When timer counter (channel 1)
Mode register
At 6.0 MHz
At 4.19 MHz
Longest setup time
TM16
TM15
TM14
Resolution
Longest setup time
350 ms
Resolution
7.63 µs
977 µs
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
5.33 µs
683 µs
171 µs
42.7 µs
10.7 µs
500 ms
64.0 s
16.0 s
4.0 s
44.7 s
11.2 s
244 µs
2.80 s
61.0 µs
15.3 µs
699 ms
1.0 s
(b) When timer counter (channel 2)
Mode register
At 6.0 MHz
At 4.19 MHz
TM26
TM25
TM24
Resolution
Longest setup time
21.8 ms
Resolution
477 ns
Longest setup time
31.3 ms
15.6 ms
16.0 s
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
333 ns
167 ns
171 µs
42.7 µs
10.7 µs
2.67 µs
10.9 ms
238 ns
11.2 s
244 µs
2.80 s
61.0 µs
15.3 µs
3.81 µs
4.0 s
699 ms
1.0 s
175 ms
250 ms
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(3) Timer counter operation
The timer counter operates as follows. In this operation mode, set the gate control enable flag (TGCE) of the
timer counter control register (TC2) to 0.
Figure 5-45 shows the configuration of the timer counter.
<1> The count pulse (CP) is selected by setting the mode registers (TM1 and TM2), and is input to the count
register (T2). The overflow of the T2 is input to the count register (T1).
<2> The contents of the T1 and those of the modulo register (TMOD1) are compared, and if they are equal,
a match signal is generated.
<3> The contents of the T2 are compared with those of the modulo register (TMOD2), and if they are equal,
a match signal is generated.
<4> If the match signals of <2> and <3> above are the same, an interrupt request flag (IRQT2) is set. At the
same time, the timer out flip-flop (TOUT F/F) flips.
Figure 5-46 shows the timing chart of the timer counter operation.
The timer counter normally starts the operation in the following procedure.
<1> Set the high-order 8-bits of the count expressed by a 16-bit width in the TMOD1.
<2> Set the low-order 8-bits of the count expressed by a 16-bit width in the TMOD2.
<3> Set the operating mode and count pulse in the TM1.
<4> Set the operating mode, count pulse, and start indication in the TM2.
Caution Set a value other than 00H to the modulo register (TMOD2).
When using the timer counter output pin (PTO2), set the dual function pins P22 and PCL as follows.
<1> Clear the output latch of P22.
<2> Set port 2 to the output mode.
<3> Do not connect the internal pull-up resistor to port 2, and disable output of PCL.
<4> Set the timer counter output enable flag (TOE2) to 1.
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Figure 5-45. Timer Counter Operation Configuration
Modulo register (TMOD1)
Match
Comparator
MPX
Internal
clock
CP
Clear
Count register (T1)
INTT2
(IRQT2 set signal)
Modulo register (TMOD2)
Comparator
Match
TOUT F/F
PTO2
Internal
clock
MPX
CP
Count register (T2)
Clear
Figure 5-46. Count Operation Timing
Count pulse
(CP)
Modulo register
(TMOD2)
n
Count register
(T2)
0
1
2
n
255
0
1
2
n–1
n
0
1
2
Modulo register
(TMOD1)
m
Match
Match
Count register
(T1)
0
m–1
m
0
TOUT F/F
Set
Timer start indication
Remark m: Set value of modulo register (TMOD1)
n : Set value of modulo register (TMOD2)
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(4) Counter operation with gate control function (16 bits)
The timer counter (channel 1) and timer counter (channel 2) can be used as a counter with gate control function.
Set the gate control enable flag (TGCE) of the timer counter control register to 1 when using this function.
When timer/event counter (channel 0) counts to the specified number, the gate signal is generated.
When the gate signal (output of TOUT F/F of T0) is high, the count pulses of timer counter channels 1, 2 can
be counted as shown in Figure 5-48 (for details, refer to (3) Timer counter operation).
<1> When the mode registers (TM1 and TM2) are set, the count pulse (CP) is selected. When the gate signal
is high, the CP is input to the count register (T2). The overflow of the T2 is input to the count register (T1).
<2> Interrupts are generated at the rising edge and falling edge of the gate signal. Normally, the contents of
the T1 and T2 are read out by an interrupt subroutine of the falling edge and they are then cleared for the
next count operation.
Figure 5-48 shows the timing chart of the counter operation.
The counter normally starts operation in the following procedure.
<1> Set the operation mode and count pulse in the TM1.
<2> Set the operation mode, count pulse, and counter clear indication in the TM2.
<3> Set the number of count in the TMOD0.
<4> Set the operation mode, count pulse, and start specification in the TM0.
Cautions 1. Do not set a value other than 00H in the modulo registers (TMOD0, TMOD1, TMOD2).
2. Do not set 1 to the timer counter interrupt enable flag (IET1).
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Figure 5-47. Count Operation Configuration
INTT0
Modulo register (TMOD0) (IRQT0 set signal)
TI0
Match
TOUT
F/F
Comparator
PTO0
MPX
Internal
clock
CP
Count register (T0)
Clear
INTT2
Modulo register (TMOD2) (IRQT2 set signal)
Match
TOUT
F/F
Internal
clock
PTO2
Comparator
MPX
Count register (T2)
Clear
CP
Modulo register (TMOD1)
Match
Comparator
MPX
Internal
clock
CP
Count register (T1)
Clear
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-48. Count Operation Timing
Count pulse
(CP)
Modulo register
(TMOD0)
n
Count register
(T0)
0
1
2
n–1
n
0
1
2
n–1
n
0
1
2
3
4
Match
Match
Gate signal
(TOUT F/F)
Reset
IRQT0 set
IRQT0 set
Count disable
Count enable
Count disable
Event input
(TI0)
Count register
(T1: upper)
0
i
Count register
(T2: Iower)
0
1
2
j–2 j–1
j
Counter clear indication
Timer start indication
Remark i : Set value of count register (T1: High-order)
j : Set value of count register (T2: Low-order)
n: Set value of modulo register (TMOD0)
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(5) 16-bit timer counter mode application
Example Application used as an interval timer generating interrupts every 5 seconds
•
Set the high-order 4-bits of the mode register (TM1) to 0010B and select the timer counter (channel 2)
timer output.
•
•
•
Set the high-order 4-bits of the TM2 to 0100B and select the longest setup time 16.0 seconds.
Set the low-order 4-bits of the TM1 to 0010B and select the 16-bit timer counter mode.
Set the low-order 4-bits of the TM2 to 1110B and select the 16-bit timer counter mode and count operation
and indicate timer start.
•
Set the modulo registers (TMOD1, TMOD2) as follows.
5 sec
244 µs
= 20491.8 – 1 = 500BH
<Program example>
SEL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DI
MB15
; or CLR1 MBE
XA, #050H
TMOD1, XA
XA, #00BH
TMOD2, XA
XA, #00100010B
TM1, XA
; Sets the modulo (for high-order 8-bits).
; Sets the modulo (for low-order 8-bits).
; Sets the mode.
XA, #01001110B
TM2, XA
; Sets the mode and starts the timer.
; Disables the timer (channel 1) interrupts.
; Enables the interrupts.
IET1
EI
EI
IET2
; Enables the timer (channel 2) interrupts.
Remark In this example TI0 can be used as the input pins.
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5.5.5 Carrier generator mode (CG Mode) operation
It is used as an 8-bit carrier generator in this mode.
When using this mode, it is used in combination with channel 1 and channel 2 of the timer counter.
The timer counter (channel 1) generates remote control signals.
The timer counter (channel 2) generates carrier clocks.
(1) Register setting
In the CG mode, the following eight registers are used.
•
•
•
•
•
Timer counter mode registers (TM1, TM2)
Timer counter control register (TC2)Note
Timer counter count registers (T1, T2)
Timer counter modulo registers (TMOD1, TMOD2)
Timer counter high-level period setting modulo register (TMOD2H)
Note The channel 1 of the timer counter uses the timer counter output enable flag (TOE1).
(a) Timer counter mode register (TM1, TM2)
When using the CG mode, set the TM1 and TM2 as shown in Figure 5-49 (For the format of the TM1, refer
to Figure 5-28. Timer Counter Mode Register (channel 1) Format. For the format of TM2, refer to Figure
5-29. Timer Counter Mode Register (channel 2) Format).
The TM1 and TM2 are manipulated by the 8-bit manipulation instructions. Bit 3 is a timer start indication
bit and can be manipulated bitwise and is automatically cleared to 0 when the timer starts operation.
The TM1 and TM2 are cleared to 00H when the internal reset signals are generated.
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Figure 5-49. Timer Counter Mode Register Setup (n = 1, 2)
Address
FA8H
7
6
5
4
3
2
1
0
Symbol
TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM1
F90H
TM26 TM25 TM24 TM23 TM22 TM21 TM20 TM2
Count pulse (CP) selection bit
TMn6 TMn5 TMn4
TM1
TM2
0
0
0
0
0
1
0
1
0
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Timer counter (channel 2)
timer output
fX
/2
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
f
f
f
f
f
X
X
X
X
X
/25
f
f
f
f
f
X
X
X
X
X
/212
/210
/28
/210
/28
/26
/24
/26
Timer start indication bit
TMn3
When “1” is written into the bit, the counter and IRQTn flag are cleared.
If bit 2 is set to “1”, count operation is started.
Operation mode
TMn2
Count operation
Stop (retention of count contents)
Count operation
0
1
Opetation mode selection bit
TM20 TM11 TM10
TM21
1
Mode
Carrier generator mode
1
0
0
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(b) Timer counter control register (TC2)
When using the CG mode, set the timer output enable flag (TOE1) and TC2 as show in Figures 5-50,
5-51 (For the format of the TC2, refer to Figure 5-31. Timer Counter Control Register Format).
The TOE1 is manipulated by a bit manipulation instruction. The TC2 is manipulated by an 8-bit/4-bit
manipulation instruction and bit manipulation instruction.
The TOE1 and TC2 are cleared to 00H by the internal reset signals.
The flag indicated by the full lines expresses a flag used in the CG mode.
The flag indicated by the broken lines must not be used in the CG mode. Set “0”.
Figure 5-50. Timer Counter Output Enable Flag Setup
Address
Timer counter output enable flag (W)
FAAH
TOE1
0
1
Disabled.
Enabled.
Figure 5-51. Timer Counter Control Register Setup
7
6
5
4
3
2
1
0
Symbol
TC2
TGCE
TOE2 REMC NRZB NRZ
Remote control output control flag
REMC
Remote control output
0
1
Outputs the carrier pulse when NRZ = 1.
Outputs the high-level signal when NRZ = 1.
No return zero buffer flag
NRZB No return zero data to be output next. Transferred to the NRZ when
a timer counter (channel 1) interrupt is generated.
No return zero flag
NRZ
No return zero data
Outputs the low level signal.
0
1
Outputs the carrier pulse or high-level signal.
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(2) Carrier generator operation
The carrier generator operates as follows. Figure 5-52 shows its configuration.
(a) Timer counter (channel 1) operation
The timer counter (channel 1) determines the reloading interval from the no return zero buffer flag (NRZB)
to the no return zero flag (NRZ). The timer counter (channel 1) operates as follows (For details, refer to 5.5.2
8-bit timer/event counter mode operation).
<1> When the mode register (TM1) is set, the count pulse (CP) is set and is input to the count register (T1).
<2> The contents of the T1 and those of the modulo register (TMOD1) are compared, and if they are equal,
a match signal is generated and the interrupt request flag (IRQT1) is set. At the same time, the timer
out flip-flop (TOUT F/F) flips.
(b) Timer counter (channel 2) operation
The timer counter (channel 2) generates the carrier clock and outputs the carrier signal according to the no
return zero data. The timer counter (channel 2) operates as follows (For details, refer to 5.5.3 PWM pulse
generator mode (PWM mode) operation).
<1> When the mode register (TM2) is set, the count pulse (CP) is selected and is input to the count register
(T2).
<2> The contents of the T2 and those of the high-level period setting modulo register (TMOD2H) are
compared, and if they are equal, a match signal is generated and the timer out flip/flop (TOUT F/F)
flips.
<3> The contents of the T2 and those of the modulo register (TMOD2) are compared, and if they are equal,
a match signal is generated and the interrupt request flag (IRQT2) is set. At the same time, the TOUT
F/F flips.
<4> Repeat the above operations <2> and <3>.
<5> The no return zero data is reloaded from the NRZB to the NRZ when an interrupt is generated in the
timer counter (channel 1).
<6> When the remote control output control flag (REMC) is set and NRZ = 1, the carrier clock signal or
high-level signal is output. When NRZ = 0, a low-level signal is output.
Figure 5-53 shows the timing chart of the carrier generator.
The carrier generator normally operates in the following procedure.
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<1> Set the number of count of the carrier clock’s high-level signals in the TMOD2H.
<2> Set the number of count of the carrier clock’s low-level signals in the TMOD2.
<3> Set the style of the output waveform in the REMC.
<4> Set the operation mode, count pulse, and start indication in the TM2.
<5> Set the number of count in the TMOD1.
<6> Set the operation mode, count pulse, and start indication in the TM1.
<7> Set the next no return zero data in the NRZB at any time before an interrupt is generated in the timer
counter (channel 1).
Caution Set the values other than 00H in the modulo registers (TMOD1, TMOD2, TMOD2H).
When using the timer counter output pin (PTO1), set the dual function pin P21 as follows.
<1> Clear the output latch of P21.
<2> Set port 2 to the output mode.
<3> Do not connect the internal pull-up resistor to port 2.
<4> Set the timer counter output enable flag (TOE1) to 1.
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Figure 5-52. Carrier Generator Operation Configuration
INTT1
(IRQT1 set signal)
Modulo register (TMOD1)
Comparator
Match
TOUT F/F
PTO1
MPX
Internal
clock
CP
Clear
Count register (T1)
Carrier clock
PTO2
NRZB
NRZ
Reload
High-level period setting modulo register
(TMOD2H)
Modulo register (TMOD2)
MPX
INTT2
(IRQT2 set signal)
Match
Internal
clock
Comparator
TOUT F/F
MPX
CP
Count register (T2)
Clear
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Figure 5-53. Carrier Generator Operation Timing
Count pulse
(CP)
High-level period
setting modulo register
(TMOD2H)
i
Modulo register
(TMOD2)
k
Count register
(T2)
k
0
1
2
i–1
i
0
1
2
k–1
k
0
1
2
3
4
Carrier clock
Modulo register
(TMOD1)
n
Count register
(T1)
n
0
1
2
n
0
1
2
n
0
1
2
n
0
1
2
n
0
1
Interrupt generation
(channel1)
IRQT1 set
1
IRQT1 set
IRQT1 set
IRQT1 set
IRQT1 set
No return zero buffer flag
(NRZB)
0
1
1
0
Reload
Reload
Reload
Reload
No return zero flag
(NRZ)
0
1
0
1
1
0
PTO2 pin
Remark i : Set value of high-level period setting modulo register (TMOD2H)
k : Set value of modulo register (TMOD2)
n: Set value of modulo register (TMOD1)
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Remark When the PTO2 pin is high (the no return zero flag (NRZ) is “0” and the carrier clock signal is high)
and a timer counter (channel 1) interrupt is generated, the PTO2 pin output does not change
according to the updated contents of NRZ until the carrier clock signal goes high.
When the PTO2 pin is high (the NRZ is “1” and the carrier clock is high) and a timer counter (channel
1) interrupt is generated, the PTO2 pin output does not change according to the updated contents
of NRZ until the carrier clock signal goes low.
This is to keep a certain high-level pulse width of the output carrier (refer to the figure below).
No return zero
(NRZ)
Carrier clock
PTO2 pin
Even if the NRZ is set to “1”,
the PTO2 pin output does not
go high until the next carrier
clock pulse goes high.
Even if the NRZ is set to “0”,
the PTO2 pin output does not
go low until the next carrier
clock pulse goes low.
(3) CG mode applications
It can be used as a carrier generator for remote control transmission.
<1> A carrier clock signal (frequency is 38.0 kHz (period: 26.3 µs) and duty ratio is 1/3) is generated.
•
•
Set the high-order 4-bits of the mode register (TM2) to 0011B and select the longest setup time 61.1
µs.
Set the low-order 4-bits of the TM2 to 1111B and select the CG mode and count operation and indicate
timer start.
•
•
Set the timer output enable flag (TOE2) to “1” and enable timer output.
Set the high-level period setting modulo register (TMOD2H) to the following value.
1
3
26.3 µs
239 ns
.
•
– 1 = 36.7 – 1 = 36 = 24H
.
•
Set the modulo register (TMOD2) to the following value.
2
3
26.3 µs
239 ns
.
•
– 1 = 73.4 – 1 = 72 = 48H
.
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<Program example>
SEL
MB15
; or CLR1 MBE
MOV
MOV
MOV
MOV
MOV
MOV
XA, #024H
TMOD2H, XA
XA, #48H
; Sets the modulo (high-level period).
; Sets the modulo (low-level period).
; Sets the mode and starts the timer.
TMOD2, XA
XA, #00111111B
TM2, XA
<2> A reader code (carrier clock output period is 9 ms and low-level output period is 4.5 ms) is output. Refer
to the figure below.
•
•
•
Set the high-order 4 bits of the mode register (TM1) to 0110B and select the longest setup time 15.6
ms.
Set the low-order 4 bits of the TM1 to 1100B and select the 8-bit timer counter mode and count operation
and indicate timer start.
Set the modulo register (TMOD1) to the following initial value.
9 ms
.
– 1 = 147.5 – 1 = 146 = 92H
.
61 µs
•
Set the TMOD1 as follows when update it.
4.5 ms
.
– 1 = 73.7 – 1 = 73 = 49H
.
61 µs
•
•
Set the high-order 4 bits of the TC2 to 0000B and disable the gate control.
Set the low-order 4 bits of the TC2 to 0000B and output the carrier clock signal when no return zero
data is “1” and set the next no return zero data to “0”.
<Program example>
SEL
MB15
; or CLR1 MBE
MOV
MOV
MOV
MOV
XA, #092H
TMOD1, XA
XA, #00000000B
TC2, XA
; Sets the modulo (carrier clock output time).
SET1 NRZ
; Sets the no return zero data to “1”.
MOV
MOV
EI
XA, #01101100B
TM1, XA
IET1
; Sets the mode and starts the timer.
; Enables the interrupts.
EI
; Enables the timer (channel 1) interrupts.
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; <Subroutine>
MOV
MOV
RETI
XA, #049H
TMOD1, XA
; Updates the modulo (low-level output time).
9 ms
4.5 ms
<3> A custom code (the carrier clock output period is 0.56 ms and low-level output period is 1.69 ms when data
is “1”, and carrier clock output period is 0.56 ms and low-level output period is 0.56 ms when data is “0”)
is output. Refer to the figure below.
•
•
•
Set the high-order 4 bits of the mode register (TM1) to 0011B and select the longest setup time 1.95
ms.
Set the low-order 4 bits of the TM1 to 1100B and select the 8-bit timer counter mode and count operation
and indicate timer start.
Set the modulo register (TMOD1) to the following initial value.
0.56 ms
.
– 1 = 73.3 – 1 = 72 = 48H
.
7.64 µs
•
When data is “0” during the period in which the carrier output is not specified by TMOD1, the processing
is performed for the same duration as the output period. When data is “1”, the processing time is three
times longer than the output period.
•
•
Set the high-order 4 bits of the TC2 to 0000B and disable the gate control.
Set the low-order 4 bits of the TC2 to 0000B, and if no return zero data is “1”, output the carrier clock
and set the next no return zero data to “0”.
•
Put the transmit data (“0” or “1”) in the bit sequential buffer.
Data "1"
Data "0"
0.56 ms
1.69 ms
0.56 ms
0.56 ms
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<Program example>
In this example, it is assumed that the output latch of the PTO2 pin is fixed to “0” and the pin is set in
the output mode. It is also assumed that the carrier clock is being generated by the program in <2>
above.
; SEND_CARIER_DATA_PRO
SEL
MB15
; or CLR1 MBE
MOV
HL, #00H
; Sets pointer of BSB (bit sequential buffer) to L. H is used
to save bit data of BSS temporarily.
; GC_Init & Send_1st_Data
MOV
MOV
MOV
XA, #48H
TMOD1, XA
; Sets modulo register (carrier clock output period).
; Disables gate control, enables output of carrier clock,
and initializes NRZB and NRZ to 0.
XA, #00000000B
MOV
SET1
MOV
MOV
TC2, XA
NRZ
; Sets “1” to no return zero flag.
XA, #01101100B
TM1, XA
; Selects count pulse, and sets 8-bit timer/counter mode.
; Enables timer/count operation, and starts timer.
; Send_1st_Data
CALL
!GET_DAT
; Gets data from BSB
CALL
!SEND_D_0
; Outputs carrier with data 0 and 1, and sets low-output
period once.
SKE
BR
H, #1H
; If bit 0 is 1, adds low-output period twice.
; If bit 0 is 0, searches next data with low output.
; Adds two low-output periods.
SEND_1_F
!SEND_D_1
CALL
Transmitsdataofbits0-FofBSBwithPTO2pinoutputting
low.
SEND_1_F:
SET1
; Transmits data of bits 0-F of BSB.
NRZB
L
; Sets NRZB to 1 during low-output period of previous
data so that carrier of data transmitted next is output one
next generation of IRQT1.
INCS
; Counts transmit data. If L changes from 0FH to 0H, ends
data transmission.
BR
BR
LOOP_C_0
SEND_END
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LOOP_C_0: SKTCLRIRQT1
; Waits low output of previous data (acknowledges end of
previous data).
BR
LOOP_C_0
NRZB
; Starts carrier output.
CLR1
; Clears NRZB to 0 in advance so that first low output is
performed on next generation of IRQT1.
CALL
CALL
SKE
!GET_DAT
!SEND_D_0
H, #1H
; If data gotten is 1, adds low output period twice
(SEND_D_1).
BR
SEND_1_F
; If data is 0, transmits next data with PTO2 pin outputting
low.
CALL
BR
!SEND_D_1
SEND_1_F
SEND_END:
; End of transmitting 16 bits of data.
; <Subroutine>
GET_DAT:
; Searches data of BSB indicated by @L. Sets value to
H register.
SKT
BSB0, @L
A, #0
MOV
MOV
MOV
RET
A, #1
H, A
SEND_D_0:
; Outputs carrier with data 0 and 1 and sets low output
once.
LOOP_1st: SKTCLR IRQT1
BR
LOOP_1st
; Waits carrier output.
; Starts first low output.
RET
SEND_D_1:
CLR1
NRZB
; If data is 1, sets second low output.
LOOP_2nd: SKTCLR IRQT1
BR
LOOP_2nd
; Waits first low output.
; Starts second low output.
; Sets third low output.
CLR1
NRZB
LOOP_3rd: SKTCLR IRQT1
BR
LOOP_3rd
; Waits second low output.
; Starts third low output.
RET
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5.5.6 Notes on using the timer/event counter
(1) Error when starting the timer
During the time from the timer start (bit 3 of the TMn is set) to the match signal generation, an error of one count
pulse (CP) at maximum is produced with respect to the value obtained by the formula: (value set in modulo register
+ 1) × resolution. This is because the count register Tn is cleared asynchronously with the CP as shown below.
Count pulse (CP)
Count register (Tn)
0
1
2
3
0
1
2
Timer start
Timer start
When the frequency of CP is one machine cycle or more, the time from the timer start (bit 3 of the TMn is set
to “1”) to the match signal generation has a discrepancy of two clock pulses at maximum to the value obtained
by the formula: (value set in modulo register + 1) × resolution. This is because the Tn is cleared asynchronously
with the CP based on the CPU clock as shown below.
Count pulse (CP)
Count register (Tn)
0
1
2
0
1
Timer start
Timer start
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(2) Caution on starting the timer
The count register Tn and interrupt request flag IRQTn are always cleared when the timer starts (bit 3 of the TMn
is set to “1”). On the other hand, when the timer is operating and the IRQTn is set and the timer starts at the
same timing, the IRQTn may not be able to be cleared. This does not cause trouble when the IRQTn is used
as a vectored interrupt. However, when the IRQTn is tested, it appears to be set although the timer has started.
Therefore, when the timer starts at the timing when the IRQTn may be set high, the timer must stop (bit 2 of the
TMn is set to “0”) and then restart or the timer start operation must be done twice.
Example Timer start at the timing when the IRQTn may be set high
SEL
MB15
MOV
MOV
MOV
MOV
or
XA, #0
TMn, XA
XA, #4CH
TMn, XA
; Timer stop
; Restart
SEL
MB15
TMn.3
TMn.3
SET1
SET1
; Restart
(3) Error when reading the count register
The count register (Tn) can be read any time by an 8-bit data memory operation instruction. When the instruction
is being executed, the count pulse (CP) does not change and the contents of the Tn are kept unchanged. When
the power supply for the CP is input from the TI0, the CP is cut during the instruction execution time. When the
internal clock is used as the CP, it is synchronous with instructions, and therefore this phenomenon does not
occur.
As stated above, when the TI0 is input as the CP to read the Tn, a signal (which has a pulse width that does
not give rise to incorrect counting even if the CP is cut) must be input. That is, the time during which count is
suspended by a read instruction is one machine cycle, therefore the pulse that is input to the TI0 must be wider
than it.
Read instruction
External clock (TI0)
Instruction
Count pulse (CP)
Count register (Tn)
K – 1
K
K + 1
K + 2
Count pulse change is
held by instruction
Count pulse is deleted by
instruction
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(4) Caution on changing the count pulse
When the count pulse (CP) is changed by rewriting the timer/event counter mode register (TMn), the specification
for the change is valid immediately after the instruction is executed.
Rewrite instruction
Rewrite instruction
Clock A specification
Clock B specification
Clock A specification
Clock A
Clock B
Count pulse (CP)
Depending on the combination of clock pulses at the time the CP is changed, whisker-like clock pulses (<1> or
<2> in the illustration below) may be produced. In this case, incorrect counting may occur and the count register
(Tn) may be disrupted. Therefore, when changing the CP, set bit 3 of the TMn to “1” and restart the timer
simultaneously.
Rewrite instruction
Rewrite instruction
Clock A specification
Clock B specification
Clock A specification
Clock A
Clock B
<1>
<2>
Count pulse (CP)
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(5) Operation after changing the modulo register
The contents of the modulo register (TMODn) and high-level period setting modulo register (TMOD2H) are
rewritten by an 8-bit data memory manipulation instruction.
Count pulse (CP)
Modulo register (TMODn)
n
m
High-level period setting
modulo register
(TMOD2H)
Rewrite instruction
Count register (Tn)
n
0
1
0
m
Match signal
Match signal
If the value of the TMODn after a change is smaller than the value of the count register (Tn), the Tn continues
counting and overflows to restart counting from 0. Therefore, if the value (m) after the TMODn and TMOD2H
are changed is smaller than the value (n) before they are changed, the timer must restart after they are changed.
Count pulse(CP)
Modulo register (TMODn)
n
m
High-level period setting
modulo register
(TMOD2H)
Count register (Tn)
1
x – 1
x
255
0
n > x > m
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(6) Caution on using the carrier generator (at the start)
When a carrier clock is generated, an error of one count pulse (CP) at maximum (two clock pulses at maximum
when the CP frequency is one machine cycle or more) is produced with respect to the value obtained by the
formula ((modulo register value + 1) × resolution) during the high-level period of the initial carrier clock after the
timer starts (the bit 3 of the TM2 is set to “1”). For details, refer to (1) Error when starting the timer.
When no return zero flag (NRZ) is set to “1” and then the timer starts (the bit 3 of the TM2 is set to “1”) in case
a carrier is output as the initial code, the error at the time of timer start is contained during the time the initial
carrier clock is high.
SET1 NRZ
0
1
NRZ
TOUT F/F
PTO2
0
1
0
1
0
Including the error at
the time of timer start
SET1 TM2.3
Therefore, when a carrier is to be output as the initial code, start the timer (set bit 3 of the TM2 to “1”) and then
set NRZ to “1”.
SET1 NRZ
0
1
NRZ
0
1
0
1
0
TOUT F/F
Clock
PTO2
Including the error at
the time of timer start
SET1 TM2.3
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(7) Caution on using the carrier generator (when reloading)
When a carrier is output to the PTO2 pin, a delay of one carrier clock pulse at maximum occurs during the time
from the reloading (the contents of the no return zero buffer flag (NRZB) are transferred to the no return zero
flag (NRZ) by a timer counter (channel 1) interrupt generation and the contents of the NRZ are updated to “1”)
to the initial carrier generation.
This is because reloading is done asynchronously with the carrier clock and for keeping the carrier at the stable
high level.
<Delay after reloading is at minimum>
Reloading by interrupt generation
0
1
NRZB
NRZ
0
1
0
1
0
1
0
1
0
TOUT F/F
Clock
PTO2
<Delay after reloading is at maximum>
Reloading by interrupt generation
0
1
NRZB
NRZ
0
1
0
1
0
1
0
1
0
TOUT F/F
Clock
PTO2
A delay of one carrier clock pulse
maximum occurred
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(8) Caution on using the carrier generator (when restarting)
When the carrier clock is high (TOUT F/F is holding “1”) and reloading is to be done forcibly by directly rewriting
the contents of no return zero flag (NRZ) and the timer is to restart (by setting bit 3 of TM2 to “1”), the carrier
may not be output to the PTO2 pin as shown below.
SET1 NRZ
NRZ
0
1
TOUT F/F
0
1
0
1
1
0
1
0
Clock
PTO2
Carrier is not output
SET1 TM2.3
Similarly to the above, when carrier clock is high (TOUT F/F is holding “1”) and reloading is to be done forcibly
by directly rewriting the contents of NRZ and the timer is to restart (by setting bit 3 of TM2 to “1”), the carrier
output to the PTO2 pin may keep its high level for a longer time as shown below.
CLR1 NRZ
NRZ
0
1
TOUT F/F
Clock
0
1
0
1
1
0
1
0
PTO2
High-level period of
carrier is elongated.
SET1 TM2.3
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5.6 Serial Interface
5.6.1 Serial interface function
The µPD753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four
modes.
The functions of the modes are described as follows.
(1) Operation stop mode
This mode is used when serial data transfer is not done. Power consumption can be reduced.
(2) 3-wire serial I/O mode
By using the 3-wire: serial clock (SCK), serial output (SO), and serial input (SI), data can be transferred in 8-
bit units.
In this mode, data can be transmitted and received simultaneously, therefore data transfer can be done in a high-
order speed.
The top bit of 8-bit data to be transferred is switchable between MSB and LSB, that is, it can be connected to
any devices without paying attention to their top bit, MSB or LSB.
In the mode, it can be connected to 75XL series, 75X series, 78K series, and various types of peripheral I/O
devices.
(3) 2-wire serial I/O mode
By using the 2-wire: serial clock (SCK) and serial data bus (SB0 or SB1), data can be transferred in 8-bit units.
By controlling the signal output levels to the two lines by software, communications links with several devices
can be established.
The levels of signals output to the SCK and SB0 (or SB1) can be controlled by software, therefore they can accept
any data transfer formats. As a result, the lines which are necessary for hand shaking in the conventional systems
of devices are not needed and so the I/O ports can be used more efficiently.
(4) SBI mode (serial bus interface mode)
By using the SBI: serial clock (SCK) and serial data bus (SB0 or SB1), communications links with several devices
can be established in this mode.
The mode complies with NEC’s serial bus format.
In the SBI mode, the transmitter can output an “address” for selecting a destination device of serial communication,
a “command” to be given to the destination device, and “data” to the serial data bus. The receiver can distinguish
the received data items by hardware, “address”, “command”, or “data" from each other. By this function, the I/
O ports can be used efficiently and the serial interface control portion of an application program can be simplified
similarly to the 2-wire serial I/O mode.
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Figure 5-54. Example of SBI System Configuration
VDD
Master CPU
SCK
Slave CPU
Serial clock
SCK
SB0, SB1
#1 Address 1
SB0, SB1
Address
Command
Data
Slave IC
SCK
Address N
#N
SB0, SB1
5.6.2 Configuration of serial interface
Figure 5-55 shows a block diagram of the serial interface.
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Figure 5-55. Serial Interface Block Diagram
Internal bus
Bit test
8
Bit manipulation
RELT
Bit test
8/4
8
8
Slave address register (SVA) (8)
SBIC
CSIM
Match
signal
CMDT
Address comparator
(8)
P03/SI/SB1
P02/SO/SB0
SET CLR SO latch
Selector
Shift register (SIO)
(8)
D
Q
Busy/
acknowledge
output circuit
Selector
RELD
CMDD
ACKD
Bus release/
command/
acknowledge
detection circuit
INTCSI
P01/SCK
INTCSI
control circuit
IRQCSI
set signal
Serial clock counter
f
f
f
X
X
X
/23
/24
/26
P01
output Iatch
Serial clock
selector
Serial clock control
circuit
TOUT F/F
(from timer/event counter)
External SCK
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(1) Serial operation mode register (CSIM)
This 8-bit register specifies the operation mode and serial clock wake-up function of the serial interface. (For
details, refer to 5.6.3 (1) Serial operation mode register (CSIM).)
(2) Serial bus interface control register (SBIC)
This 8-bit register consists of bits that control the status of the serial bus and flags that indicate the various statuses
of the data input from the serial bus. It is mainly used in the SBI mode. (For details, refer to 5.6.3 (2) Serial
bus interface control register (SBIC).)
(3) Shift register (SIO)
This register converts 8-bit serial data into parallel data or 8-bit parallel data into serial data. It performs
transmission or reception (shift operation) in synchronization with the serial clock. Actual transmission or
reception is controlled by writing data to the SIO. (For details, refer to 5.6.3 (3) Shift register (SIO).)
(4) SO latch
This latch holds the levels of the SO/SB0 and SI/SB1 pins. It can also be controlled directly via software. In
the SBI mode, this latch is set when SCK has been asserted eight times. (For details, refer to 5.6.3 (2) Serial
bus interface control register (SBIC).)
(5) Serial clock selector
This selects the serial clock to be used.
(6) Serial clock counter
This counter counts the number of serial clocks output or input when transmission or reception operation is
performed, to check whether 8 bits of data have been transmitted or received.
(7) Slave address register (SVA) and address comparator
•
In SBI mode
This register and comparator are used when the µPD753208 is used as a slave device. The slave places
its specification number (slave address value) in the SVA. The master outputs a slave address to select a
specific slave.
The address comparator of the slave compares the slave address the slave has received from the master with
the value in the SVA. When the address coincides with the SVA value, the slave is selected.
•
In 2-wire serial I/O mode and SBI mode
When the µPD753208 is used as a slave or master, this register and comparator detects an error. (For details,
refer to 5.6.3 (4) Slave address register (SVA).)
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(8) INTCSI control circuit
This circuit controls generation of an interrupt request. The interrupt request (INTCSI) is generated in the following
cases. When the interrupt request is generated, an interrupt request flag (IRQCSI) is set. (Refer to Figure 6-
1. Interrupt Control Circuit Block Diagram.)
•
•
In 3-wire and 2-wire serial I/O modes
An interrupt request is generated each time eight serial clocks have been counted.
In SBI mode
When WUPNote = “0” ······ An interrupt request is generated each time eight serial clocks have been counted.
When WUPNote = “1” ····· An interrupt request is generated when the value of SVA and that of SIO coincide
after an address has been received.
Note WUP ··· Wake-up function specification bit (bit 5 of CSIM)
(9) Serial clock control circuit
This circuit controls the supply of the serial clock to the shift register. It also controls the clock output to the SCK
pin when the internal system clock is used.
(10) Busy/acknowledge output circuit and bus release/command/acknowledge circuit
These circuits output and detect control signals in the SBI mode.
They do not operate in the three-wire and two-wire serial I/O modes.
(11) P01 output latch
This latch generates the serial clock via software after eight serial clocks have been generated.
It is set to “1” when the reset signal is input.
To select the internal system clock as the serial clock, set the P01 output latch to “1”.
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5.6.3 Register function
(1) Serial operation mode register (CSIM)
Figure 5-56 shows the format of the serial operation mode register (CSIM).
The CSIM is an 8-bit register which specifies the serial interface operation mode, serial clock, and wake-up
function.
The register is manipulated by an 8-bit memory manipulation instruction. The high-order 3 bits of the register
can be operated bitwise. In this case, the name of each bit is used to manipulate.
Whether the read/write operation can be performed or not depends on the bit (Refer to Figure 5-56). Bit 6 can
be used only as a bit test and data written in the bit position is invalid.
All the bits are cleared to 0, when a RESET signal is generated.
Figure 5-56. Serial Operation Mode Register (CSIM) Format (1/4)
Address
FE0H
7
6
5
4
3
2
1
0
Symbol
CSIE
COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM
Serial clock selection bit (W)
Serial interface operation mode selection bit (W)
Wake-up function specification bit (W)
Signal sent from address comparator (R)
Serial interface operation enable/disable specification bit (W)
Remarks 1. (R) Read only.
2. (W) Write only.
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Figure 5-56. Serial Operation Mode Register (CSIM) Format (2/4)
Serial interface operation enable/disable specification bit (W)
Shift register operation
Serial clock counter
Clear
IRQCSI flag
Hold
SO/SB0, SI/SB1 pins
CSIE
0
1
Disable the shift operation.
Enables the shift operation.
Dedicated to port 0 function
Count operation
Enable setting
Both for the function in each mode and port 0
Remarks 1. Each mode can be selected by setting the CSIE, CSIM3, and CSIM2.
CSIE
CSIM3 CSIM2
Operation mode
Operation halt mode
3-wire serial I/O mode
SBI mode
0
1
1
1
×
0
1
1
×
×
0
1
2-wire serial I/O mode
2. The P01/SCK pin enters the following status by setting the CSIE, CSIM1, and CSIM0.
CSIE
CSIM1 CSIM0
Status of P01/SCK pin
Input port (P01)
0
1
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
High-impedance (SCK input)
High-level output
Serial clock output
(high-level output: at the end
of serial transfer)
3. During serial data transfer, follow the procedure (<1> to <3>) to clear the CSIE.
<1> Clear the interrupt enable flag (IECSI) and disable the interrupts.
<2> Clear the CSIE.
<3> Clear the interrupt request flag (IRQCSI).
Examples 1. fX/24 is selected for the serial clock. A serial interrupt IRQCSI is generated at the
end of serial data transfer. Serial data transfer is done in the SBI mode with the
SB0 pin as the serial data bus.
SEL
MB15
; or CLR1 MBE
MOV
MOV
XA, #10001010B
CSIM, XA
; CSIM ← 10001010B
2. Serial data transfer complying with the contents of the CSIM is enabled.
SEL MB15 ; or CLR1 MBE
SET1 CSIE
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Figure 5-56. Serial Operation Mode Register (CSIM) Format (3/4)
Signal from address comparator (R)
COINote
Condition to be cleared (COI = 0)
Condition to be set (COI = 1)
The contents of the slave address register (SVA)
are not the same as those of the shift register.
The contents of the slave address register (SVA)
are the same as those of the shift register.
Note The reading of the COI is valid only before and after serial data transfer. Uncertain data is read out during
transfer. The COI data written by an 8-bit manipulation instruction is ignored.
Wake-up function specification bit (W)
WUP
0
1
Sets the IRQCSI at each time serial data transfer ends in each mode.
Used only in the SBI mode. Sets the IRQCSI only when an address received after a bus release is equal
to the data of the slave address register (wake-up status). SB0 and SB1 are high-impedance buses.
Caution If WUP = 1 while a BUSY signal is output, BUSY is not released. The BUSY signal is output during
the time from the release of BUSY to the falling edge of serial clock (SCK) in the SBI. When making
WUP = 1, be sure to release the BUSY status and then assure the SB0 (or SB1) pin is high.
Serial interface operating mode selection bit (W)
CSIM4 CSIM3 CSIM2
Operation mode
Shift register bit order
SO/SB0/P02 pin function SI/SB1/P03 pin function
×
0
0
1
0
3-wire serial
I/O mode
SIO7-0 ↔ XA
SO (CMOS output)
SI (CMOS input)
(transferred at MSB top)
SIO0-7 ↔ XA
(transferred at LSB top)
0
1
SBI mode
SIO7-0 ↔ XA
(transferred at MSB
top)
SB0
P03 (CMOS input)
(N-ch open-drain I/O)
1
0
1
P02 (CMOS input)
SB1
(N-ch open-drain I/O)
1
1
2-wire serial
I/O mode
SIO7-0 ↔ XA
SB0
P03 (CMOS input)
(transferred at MSB top)
(N-ch open-drain I/O)
P02 (CMOS input)
SB1
(N-ch open-drain I/O)
Remark × : don’t care
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Figure 5-56. Serial Operation Mode Register (CSIM) Format (4/4)
Serial clock selection bit (W)
Serial clock
SBI mode
SCK pin
mode
CSIM1 CSIM0
3-wire serial I/O mode
2-wire serial I/O mode
0
0
1
0
1
0
Clock input from outside to SCK pin
Input
Timer/event counter output (T0)
Output
4
6
fX/2 (during 375 kHz: 6.00 MHz operation,
262 kHz: 4.19 MHz operation)
fX/2
during
3
1
1
fX/2 (during 750 kHz: 6.00 MHz operation,
93.8 kHz: 6.00 MHz operation,
65.5 kHz: 4.19 MHz operation
524 kHz: 4.19 MHz operation)
(2) Serial bus interface control register (SBIC)
Figure 5-57 shows the format of the serial bus interface control register (SBIC).
The SBIC is an 8-bit register which is composed of the bits controlling the serial bus and the flags indicating the
status of input data. It is used mainly in the SBI mode.
It is manipulated by a bit manipulation instruction. It can not be manipulated by an 8-bit/4-bit manipulation
instruction.
Whether the read/write operation can be performed or not depends on the bit (Refer to Figure 5-57).
All the bits are cleared to 0 when RESET signal is generated.
Caution Only the following bits can be used in the 3-wire/2-wire serial I/O mode.
•
•
Bus release trigger bit (RELT)·················· sets the SO latch.
Command trigger bit (CMDT)···················· clears the SO latch.
Figure 5-57. Serial Bus Interface Control Register (SBIC) Format (1/3)
Address
FE2H
7
6
5
4
3
2
1
0
Symbol
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SBIC
Bus release trigger bit (W)
Command trigger bit (W)
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Acknowledge enable bit (R/W)
Acknowledge detection flag (R)
Busy enable bit (R/W)
Remarks 1. (R)
: Read only.
2. (W) : Write only.
3. (R/W) : Both read/write.
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Figure 5-57. Serial Bus Interface Control Register (SBIC) Format (2/3)
Busy enable bit (R/W)
BSYE
0
1
<1> Disables the automatic output of a busy signal.
<2> Stops the output of a busy signal in synchronization with the falling edge of the SCK immediately after
a clear instruction is executed.
Outputs a busy signal in synchronization with the falling edge of the SCK following an acknowledge signal.
Examples 1. A command signal is output.
SEL
MB15
; or CLR1 MBE
SET1
CMDT
2. The RELD and CMDD are tested to identify the received data for an appropriate operation.
The interrupt routine sets the WUP to 1 and is executed only when the address is matched.
SEL
SKF
BR
MB15
RELD
!ADRS
CMDD
!DATA
!CMD
; Tests the RELD.
;Tests the CMDD.
SKT
BR
BR
CMD ; ·································· ; Interprets the command.
DATA ; ·································· ; Processes the data.
ADRS ; ·································· ; Decodes the address.
Acknowledge detection flag (R)
ACKD
Condition to be cleared (ACKD = 0)
<1> At the start of data transfer
<2> When the RESET signal is generated.
Condition to be set (ACKD = 1)
When acknowledge signal (ACK) is detected
(in synchronization with the rising edge of the SCK).
Acknowledge enable bit (R/W)
ACKE
0
1
Disables the automatic output of the acknowledge signal (ACK). Output by the ACKT is enabled.
When it is set before data transfer terminates
The ACK is output in synchronization with the 9th clock
pulse of SCK.
When it is set after data transfer terminates
The ACK is output in synchronization with the SCK
immediately after a set instruction is executed.
Acknowledge trigger bit (W)
ACKT
When it is set at the end of data transfer, the ACK is output in synchronization with the next SCK. It is automati-
cally cleared to 0 after the ACK is output.
Cautions 1. Do not set to 1 during serial data transfer.
2. The ACKT cannot be cleared by software.
3. When setting the ACKT, set the ACKE to 0.
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Figure 5-57. Serial Bus Interface Control Register (SBIC) Format (3/3)
Command detection flag (R)
CMDD
Condition to be cleared (CMDD = 0)
Condition to be set (CMDD = 1)
<1> When Transfer Start instruction is being executed.
<2> When bus release signal (REL) is detected.
<3> When the RESET signal is generated.
<4> CSIE = 0 (refer to Figure 5-56)
When command signal (CMD) is detected.
Bus release detection flag (R)
RELD
Condition to be cleared (RELD = 0)
Condition to be set (RELD = 1)
<1> When Transfer Start instruction is being executed.
<2> When the RESET signal is generated.
When bus release signal (REL) is detected.
<3> CSIE = 0 (refer to Figure 5-56)
<4> SVA is not equal to SIO when an address is received.
Command trigger bit (W)
CMDT
Trigger output control bit for the command signal (CMD). When it is set (CMDT = 1), the SO latch is cleared to 0
and then CMDT bit is automatically cleared to 0.
Caution The SB0 (or SB1) must not be cleared during serial data transfer, but before or after it.
Bus release trigger bit (W)
RELT
Trigger output control bit for the bus release signal (REL). When it is set (RELT = 1), the SO latch is set to 1
and then RELT bit is automatically cleared to 0.
Caution The SB0 (or SB1) must not be cleared during serial data transfer, but before or after it.
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(3) Shift register (SIO)
Figure 5-58 shows the configuration of the system comprising the shift register and peripheral devices. The SIO
is an 8-bit register which performs serial-to-parallel conversion and shift operation in synchronization with the
serial clock.
Serial data transfer starts when data is entered into the SIO.
During data transmission, the data written in the SIO is output to the serial output (SO) or serial data bus (SB0
or SB1). During receiving, data is read from the serial input (SI) or SB0 or SB1 to the SIO.
Data can be read and written by an 8-bit operation instruction.
When a RESET signal is generated during an operation, the contents of the SIO are uncertain. When the RESET
signal is generated in the standby mode, the contents of the SIO are held.
The shift operation stops after data is transmitted or received in an 8-bit unit.
Figure 5-58. System Comprising Shift Register and Peripheral Devices Configuration
Address
comparator
RELT
Internal bus
CMDT
Shift
register
SO latch
SET
CLR
D
Q
CLK
CSIM
Shift clock
BUSY/ACK
N-ch open-drain output
Data can be written and read to/from the SIO in the following timings.
•
The serial interface operation enable/disable bit (CSIE) is set to 1 except when the CSIE is set to 1 after data
is written in the shift register.
•
•
The serial clock is masked after the 8-bit serial data transfer ends.
The SCK is high.
Be sure to write or read data to or from the SIO when SCK is high.
The input pin of the data bus is shared with the output pin in the two-wire serial I/O mode and SBI mode. The
output pin is of the N-ch open-drain configuration. Therefore, put FFH in the SIO of the device that is to receive
data.
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(4) Slave address register (SVA)
SVA is an 8-bit register that sets a slave address (specification number).
It is operated by an 8-bit manipulation instruction.
The contents of the SVA becomes uncertain when a RESET signal is generated. However, when the RESET
signal is generated in the standby mode, the contents of the SVA are held.
(a) Detection of slave address (in SBI mode)
When the µPD753208 is connected to the serial bus as a slave device, SVA is used to set the slave address
(specification number) of the µPD753208. The master outputs a slave address to the slaves connected to
the bus, to select a specific slave. The slave address output from the master is compared with the value
of the SVA of the slave by the address comparator of the slave. When the two addresses coincide, the slave
is selected.
At this time, the bit 6 (COI) of the serial operation mode register (CSIM) is set to “1”. When an address is
received from the master and coincidence between the received address and the address set to the SVA
is not detected, the bus release detection flag (RELD) is cleared to 0. IRQCSI is set only when coincidence
is detected when WUP = 1. This interrupt function allows the slave (µPD753208) to learn that the master
has issued a request for communication.
(b) Detection of errors (in 2-wire serial I/O mode and SBI mode)
The SVA detects an error in the following cases:
•
•
When the µPD753208 operates as the master and transmits addresses, commands, and data
When the µPD753208 transmits data as a slave device
For details, refer to 5.6.6 (6) Error detection or 5.6.7 (8) Error detection.
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5.6.4 Operation stop mode
The operation stop mode is used when serial transfer is not performed, to reduce the power dissipation.
In this mode, the shift register does not perform shift operations. Therefore, it can be used as an ordinary 8-bit
register.
When the reset signal is input, operation stop mode is set. The P02/SO/SB0 and P03/SI/SB1 pins are set to the
input port mode. The P01/SCK pin can be used as an input port pin if so specified by the serial operation mode register.
[Register setting]
Operation stop mode is set by using the serial operation mode register (CSIM). (For the format of the CSIM, refer
to 5.6.3 (1) Serial operation mode register (CSIM).)
The CSIM is manipulated in 8-bit units. However, the CSIE bit of this register can be manipulated in 1-bit units.
The name of the bit can be used for manipulation.
The CSIM is set to 00H at reset.
The shaded portions in the figure below indicate the bits used in operation stop mode.
Address
FE0H
Symbol
CSIM
7
6
5
4
3
2
1
0
CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
Serial clock select bits (W)Note
Serial interface operation mode select bits (W)
Wake-up function specification bit (W)
Coincidence signal from address comparator (R)
Serial interface operation enable/disable bit (W)
Note This bit can select the status of the P01/SCK pin.
Remark (R) : read only
(W) : write only
Serial interface operation enable/disable bit (W)
Operation of shift register
Shift operation disabled
Serial clock counter
Cleared
IRQCSI flag
Retained
SO/SB0 and SI/SB1 pins
CSIE
0
Dedicated to port 0
function
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Serial clock select bit (W)
The P01/SCK pin is set to the following status according to the setting of the CSIM0 and CSIM1 bits.
CSIM1 CSIM0
Status of P01/SCK pin
High impedance
High level
0
0
1
1
0
1
0
1
Clear the CSIE bit using the following procedure during serial transfer:
<1> Clear the interrupt enable flag (IECSI) to disable the interrupt.
<2> Clear CSIE.
<3> Clear the interrupt request flag (IRQCSI).
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5.6.5 Operation in 3-wire serial I/O mode
In the three-wire operation mode, the µPD753208 can be connected to microcomputers in the 75XL series, 75X
series, and 78K series, and to various peripheral I/O devices.
In this mode, communication is established by using three lines: serial clock (SCK), serial output (SO), and serial
input (SI).
Figure 5-59. Example of System Configuration in 3-Wire Serial I/O Mode
3-wire serial I/O ↔ 3-wire serial I/O
Master CPU
PD753208
Slave CPU
µ
SCK
SCK
SO
SI
SI
SO
Remark The µPD753208 can be also used as a slave CPU.
(1) Register setting
When 3-wire serial I/O mode is used, the following two registers must be set:
•
•
Serial operation mode register (CSIM)
Serial bus interface control register (SBIC)
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(a) Serial operation mode register (CSIM)
When three-wire serial I/O mode is used, set CSIM as shown below. (For the format of CSIM, refer to 5.6.3
(1) Serial operation mode register (CSIM).)
CSIM is manipulated by using 8-bit manipulation instructions. Bits 7, 6, and 5 can also be manipulated in
1-bit units.
The contents of the CSIM are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in three-wire serial I/O mode.
Address
FE0H
Symbol
CSIM
7
6
5
4
3
2
1
0
CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
Serial clock select bits (W)
Serial interface operation mode select bits (W)
Wake-up function specification bit (W)
Coincidence signal from address comparator (R)
Serial interface operation enable/disable bit (W)
Remark (R) : read only
(W) : write only
Serial interface operation enable/disable bit (W)
Operation of shift register
Shift operation enabled
Serial clock counter
Count operation
IRQCSI flag
Can be set
SO/SB0 and SI/SB1 pins
CSIE
1
Function in each mode
and port 0 function
shared
Signal from address comparator (R)
COINote
Clear condition (COI = 0)
When the slave address register (SVA) data
and shift register data do not coincide
Set condition (COI = 1)
When slave address register (SVA) data and shift register
data coincide
Note COI can be read before the start of serial transfer and after completion of the serial transfer. An undefined
value is obtained if this bit is read during transfer. Data written to COI by an 8-bit manipulation instruction
is ignored.
Wake-up function specification bit (W)
WUP
0
Sets IRQCSI each time serial transfer is completed
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Serial interface operation mode select bit (W)
CSIM4
CSIM3
0
CSIM2
Bit order of shift register
SIO7-0 ↔ XA (MSB first)
SIO0-7 ↔ XA (LSB first)
SO pin function
SI pin function
×
0
1
SO (CMOS output)
SI (CMOS input)
Remark ×: don’t care
Serial clock select bit (W)
CSIM1
CSIM0
Serial clock
SCK pin mode
Input
0
0
1
1
0
1
0
1
External clock input to SCK pin
Timer/event counter output (TO)
Output
4
fX/2 (262 kHz)Note
3
fX/2 (524 kHz)Note
Note ( ): fX = 4.19 MHz operation
(b) Serial bus interface control register (SBIC)
When the three-wire serial I/O mode is used, set SBIC as shown below. (For the format of SBIC, refer to
5.6.3 (2) Serial bus interface control register (SBIC).)
This register is manipulated by using bit manipulation instructions.
The contents of SBIC are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in the three-wire serial I/O mode.
Address
FE2H
Symbol
SBIC
7
6
5
4
3
2
1
0
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Do not use these bits in
3-wire serial I/O mode.
Bus release trigger bit (W)
Command trigger bit (W)
Remark (W): write only
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Command trigger bit
CMDT
This bit controls the output trigger of a command signal (CMD). When this bit is set to 1, the SO latch is
cleared to 0. After that, the CMDT bit is automatically cleared to 0.
Bus release trigger bit (W)
RELT
This bit controls the output trigger of a bus release signal (REL). When this bit is set to 1, the SO latch is
set to 1. After that, the RELT bit is automatically cleared to 0.
Caution Do not use bits in the SBIC register other than CMDT and RELT in the three-wire serial I/O mode.
(2) Communication operation
The 3-wire serial I/O mode transmit/receive data in 8-bit units. Data is transferred one bit at a time in
synchronization with a given serial clock.
Shift register shift operation is performed in synchronization with the serial clock (SCK) falling edge. Transmit
data is retained in the SO latch and output from the SO pin. On the SCK rising edge, receive data input to the
SI pin is latched in the shift register.
When 8-bit transfer terminates, shift register operation automatically stops and the interrupt request flag (IRQCSI)
is set.
Figure 5-60. 3-Wire Serial I/O Mode Timing
SCK
SI
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO
IRQCSI
Transfer termination
Transfer start in synchronization with SCK falling edge.
Execution of data write instruction into SIO (transfer start indication)
When CSIE is set(1), IRQCSI is automatically cleared (0).
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Because the SO pin is a CMOS output pin and outputs the status of the SO latch, the output status of the SO
pin can be manipulated by setting the RELT and CMDT bits.
However, do not perform this manipulation during serial transfer.
The output status of the SCK pin can be controlled by manipulating the P01 latch in the output mode (mode of
the internal system clock). (Refer to 5.6.8 SCK pin output manipulation.)
(3) Selecting the serial clock
The serial clock is selected by using bits 0 and 1 of the serial operation mode register (CSIM). The following
four types of serial clocks can be selected:
Table 5-9. Selection of Serial Clock and Applications (in 3-wire serial I/O mode)
Mode register
Serial clock
Timing at which shift register can be read/
written and serial transfer can be started
Application
CSIM
1
CSIM
0
Masking
Source
serial clock
0
0
External
SCK
Automati-
cally masked
at end of
<1> In operable mode (CSIE = 1)
Slave CPU
<2> If serial clock is masked after 8-bit serial
transfer
0
1
TOUT
F/F
Half duplex start-stop
synchronization transfer
(software control)
transfer of 8-
bit data
<3> When SCK is high
4
1
1
0
1
fX/2
Medium-speed serial
transfer
3
fX/2
High-speed serial transfer
(4) Signals
Figure 5-61 illustrates the operation of RELT and CMDT.
Figure 5-61. Operation of RELT and CMDT
SO latch
RELT
CMDT
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(5) Transfer top bit change between MSB and LSB
The 3-wire serial I/O mode enables selection of the most significant bit (MSB) or least significant bit (LSB) for
the transfer top bit.
Figure 5-62 shows the shift register (SIO) and internal bus configuration. As shown in Figure 5-62, MSB and
LSB can be reversed for read/write.
MSB or LSB can be specified as the transfer top bit by setting serial operation mode register (CSIM) bit 2.
Figure 5-62. Transfer Bit Change Circuit
7
6
Internal bus
1
0
LSB top
MSB top
Read/Write gate
Read/Write gate
SO latch
Shift register (SIO)
D
Q
SI
SO
SCK
The transfer top bit is changed by changing the bit order of data write into the shift register (SIO). The SIO shift
order is always the same.
Change the transfer top bit between MSB and LSB before writing data into the shift register.
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(6) Starting transfer
Serial transfer is started when the transfer data is placed in the shift register (SIO), if the following two conditions
are satisfied:
•
•
Serial interface operation enable/disable bit (CSIE) = 1
The internal serial clock is stopped after 8-bit serial transfer or SCK is high
Caution Transfer is not started even if CSIE is set to “1” after the data has been written to the shift
register.
When an 8-bit transfer has been completed, the serial transfer is automatically stopped, and an interrupt request
flag (IRQCSI) is set.
Example To transfer the RAM data specified by the HL register to SIO and, at the same time, load the data
in SIO to the accumulator and start serial transfer
MOV
SEL
XA, @HL
MB15
; Fetches out transfer data from RAM
; or CLR1 MBE
XCH
XA, SIO
; Exchanges transmit data and receive data, and starts transfer
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(7) Applications using 3-wire serial I/O mode
Example 1. To transfer data, MSB first, with 262-kHz transfer clock (at 4.19 MHz) (master operation)
<Program example>
CLR1 MBE
MOV XA, #10000010B
MOV CSIM, XA
MOV XA, TDATA
MOV SIO, XA
; Sets transfer mode
; TDATA is address storing transfer data
; Sets transfer data and starts transfer
Caution After transfer has been started for the first time, transfer can be started by
writing data to SIO (by using MOV SIO, XA or XCH XA, SIO) the second and
later times.
µPD753208
µPD7225G (LCD controller/driver), etc.
SCK
SO/SB0
SCK
SI
In this example, the SI/SB1 pin of the µPD753208 can be used as an input pin.
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Example 2. To transfer data, LSB first, with an external clock (slave operation)
(In this example, the shift register is read/written using a function that reverses the MSB-LSB
order.)
µPD753208
Other microcontroller
P01/SCK
SI/SB1
SCK
SO
SO/SB0
SI
<Program example>
Main routine
CLR1 MBE
MOV XA, #84H
MOV CSIM, XA
MOV XA, TDATA
MOV SIO, XA
; Stops serial operation, MSB/LSB inverse mode, external clock
; Sets transfer data and starts transfer
EI
EI
IECSI
Interrupt routine (MBE = 0)
MOV XA, TDATA
XCH
XA, SIO
; Receive data ↔ transfer data, starts transfer
MOV RDATA, XA
RETI
; Saves receive data
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Example 3. To transmit or receive data at high speeds using a 524-kHz (at 4.19 MHz) transfer clock
µPD753208 (master)
µPD75206, etc.
SCK
SCK
SI
SO/SB0
SI/SB1
SO
<Program example> ··· Master
CLR1
MOV
MOV
MOV
MOV
MBE
XA, #10000011B
CSIM, XA
XA, TDATA
SIO, XA
; Sets transfer mode
; Sets transfer data and starts transfer
.
.
.
.
.
.
LOOP: SKTCLR
IRQCSI
LOOP
; Test IRQCSI
BR
MOV
XA, SIO
; Receives data
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5.6.6 Operation in 2-wire serial I/O mode
The two-wire serial I/O mode can be used in any communication format if so specified by program.
Basically, communication is established by using two lines: serial clock (SCK) and serial data input/output (SB0
or SB1).
Figure 5-63. Example of System Configuration in 2-Wire Serial I/O Mode
2-wire serial I/O ↔ 2-wire serial I/O
Slave CPU
Master CPU
( µPD753208)
SCK
SCK
V
DD
SB0, SB1
SB0, SB1
Remark The µPD753208 can be also used as a slave CPU.
(1) Register setting
When the two-wire serial I/O mode is used, the following two registers must be set:
•
•
Serial operation mode register (CSIM)
Serial bus interface control register (SBIC)
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(a) Serial operation mode register (CSIM)
When the two-wire serial I/O mode is used, set CSIM as shown below. (For the format of CSIM, refer to
5.6.3 (1) Serial operation mode register (CSIM).)
CSIM is manipulated by using an 8-bit manipulation instructions. Bits 7, 6, and 5 can also be manipulated
in 1-bit units.
The contents of the CSIM are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in the two-wire serial I/O mode.
Address
FE0H
Symbol
CSIM
7
6
5
4
3
2
1
0
CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
Serial clock select bits (W)
Serial interface operation mode select bits (W)
Wake-up function specification bit (W)
Coincidence signal from address comparator (R)
Serial interface operation enable/disable bit (W)
Remark (R) : read only
(W): write only
Serial interface operation enable/disable bit (W)
Operation of shift register
Shift operation enabled
Serial clock counter
IRQCSI flag
Can be set
SO/SB0 or SI/SB1 pin
CSIE
1
Count operation
Function in each mode and
port 0 function shared
Signal from address comparator (R)
COINote
Clear condition (COI = 0)
Set condition (COI = 1)
When slave address register (SVA) data and shift
register data do not coincide
When slave address register (SVA) data and shift
register data coincide
Note COI can be read before the start of a serial transfer and after completion of a serial transfer. An undefined
value is read if this bit is read during transfer. Data written to COI by an 8-bit manipulation instruction is
ignored.
Wake-up function specification bit (W)
WUP
0
Sets IRQCSI each time serial transfer is completed
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Serial interface operation mode select bit (W)
CSIM4
0
CSIM3
1
CSIM2
1
Bit order of shift register
SO pin function
SBO
(N-ch open-drain I/O)
P02 input (CMOS input) SB1
(N-ch open-drain I/O)
SI pin function
SIO7-0 ↔ XA (MSB first)
P03 input (CMOS input)
1
Serial clock select bit (W)
CSIM1
CSIM0
Serial clock
SCK pin mode
Input
Output
0
0
1
1
0
1
0
1
External clock input to SCK pin
Timer/event counter output (TO)
6
Note
fX/2 (65.5 kHz)
Note ( ): fX = 4.19 MHz operation
(b) Serial bus interface control register (SBIC)
When the two-wire serial I/O mode is used, set SBIC as shown below. (For the format of SBIC, refer to 5.6.3
(2) Serial bus interface control register (SBIC).)
This register is manipulated by using bit manipulation instructions.
The contents of SBIC are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in the two-wire serial I/O mode.
Address
FE2H
Symbol
SBIC
7
6
5
4
3
2
1
0
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Do not use these bits in
2-wire serial I/O mode.
Bus release trigger bit (W)
Command trigger bit (W)
Remark (W): write only
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Command trigger bit
CMDT
This bit controls the output trigger of a command signal (CMD). When this bit is set to 1, the SO latch is
cleared to 0. After that, the CMDT bit is automatically cleared to 0.
Bus release trigger bit (W)
RELT
This bit controls the output trigger of a bus release signal (REL). When this bit is set to 1, the SO latch is
set to 1. After that, the RELT bit is automatically cleared to 0.
Caution Do not use bits of the SBIC register other than CMDT and RELT in two-wire serial I/O mode.
(2) Communication operation
The 2-wire serial I/O mode transmits/receives data in 8-bit units. Data is transferred one bit at a time in
synchronization with a given serial clock.
Shift register shift operation is performed in synchronization with the serial clock (SCK) falling edge. Transmit
data is retained in the SO latch and output starting at the MSB from the SB0/P02 (or SB1/P03) pin. On the SCK
rising edge, receive data input from the SB0 (or SB1) pin is latched in the shift register.
When an 8-bit transfer terminates, shift register operation automatically stops and the interrupt request flag
(IRQCSI) is set.
Figure 5-64. 2-Wire Serial I/O Mode Timing
SCK
SB0, SB1
IRQCSI
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
Transfer termination
Transfer start in synchronization with SCK falling edge
Execution of data write instruction into SIO (transfer start indication)
The SB0 (or SB1) pin specified for the serial data bus becomes N-ch open-drain input/output, thus must be pulled
high with an external pull-up resistor. Because it is necessary to turn off the N-ch transistor when data is received,
write FFH to SIO in advance.
Since the SB0 (or SB1) pin outputs the SO latch state, the SB0 (or SB1) pin output state can be manipulated
by setting the RELT and CMDT bits.
However, do not perform this manipulation during serial transfer.
In the output mode (internal system clock mode), the SCK pin output state can be controlled if the P01 output
latch is manipulated (Refer to 5.6.8 SCK pin output manipulation).
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(3) Selecting the serial clock
The serial clock is selected by using the bits 0 and 1 of the serial operation mode register (CSIM). Three types
of serial clocks can be selected:
Table 5-10. Selection of Serial Clock and Applications (in 2-wire serial I/O mode)
Mode Register
Serial Clock
Timing at which shift register can be read/
written and serial transfer can be started
Application
CSIM
1
CSIM
0
Masking
Source
Serial Clock
0
0
External
SCK
Automati-
cally masked
at end of
<1> In operable mode (CSIE = 1)
Slave CPU
<2> If serial clock is masked after 8-bit serial
transfer
0
1
TOUT
F/F
Serial transfer at any
speed
transfer of 8-
bit data
<3> When SCK is high
6
1
1
0
1
fX/2
Low-speed serial transfer
(4) Signals
Figure 5-65 illustrates the operation of RELT and CMDT.
Figure 5-65. Operation of RELT and CMDT
SO latch
RELT
CMDT
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(5) Starting transfer
Serial transfer is started when the transfer data is placed in the shift register (SIO), if the following two conditions
are satisfied:
•
•
Serial interface operation enable/disable bit (CSIE) = 1
The internal serial clock is stopped after 8-bit serial transfer, or SCK is high
Cautions 1. Transfer is not started even if CSIE is set to “1” after the data has been written to the shift
register.
2. Because it is necessary to turn off the N-ch transistor when data is received, write FFH
to SIO in advance.
When an 8-bit transfer has been completed, serial transfer is automatically stopped, and an interrupt request
flag (IRQCSI) is set.
(6) Error detection
In two-wire serial I/O mode, because the status of the serial bus SB0 or SB1 during transmission is also loaded
to the shift register SIO of the device transmitting data, an error can be detected by the following methods:
(a) By comparing SIO data before and after transmission
If the two data differ from each other, it can be assumed that a transmission error has occurred.
(b) By using the slave address register (SVA)
The transmit data is placed in SIO and SVA and transmission is executed. After transmission, the COI bit
(coincidence signal from the address comparator) of the serial operation mode register (CSIM) is tested. If
this bit is “1”, the transmission has been completed normally. If it is “0”, it can be assumed that a transmission
error has occurred.
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(7) Application using 2-wire serial I/O mode
Two-wire serial I/O mode can be used to connect multiple devices by configuring a serial bus.
Example To configure a system by connecting the µPD753208 as the master and µPD75104, µPD75402A,
and µPD7225G as slaves
V
DD
µ PD753208 (master)
µPD7225G
Port
CS
SCK
SCK
SI
SO/SB0
PD75402A
µ
SCK
SI
SO
PD75104
µ
SCK
SI
SO
The SI and SO pins of the µPD75104 are connected together. When serial data is not output, the serial operation
mode register is manipulated so that the output buffer is turned off to release the bus.
Because the SO pin of the µPD75402A cannot go into a high-impedance state, a transistor is connected to the
SO pin as shown in the figure, so that the SO pin can be used as an open-collector output pin. When data is
input to the µPD75402A, the transistor is turned off by writing 00H to the shift register in advance.
The timing of when each microcomputer outputs data is determined in advance.
The serial clock is output by the µPD753208, which is the master. All the slave microcomputers operate on an
external clock.
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5.6.7 SBI mode operation
The SBI (serial bus interface) is a high-speed serial interface system which is compliant with the NEC serial bus
format.
The SBI is a high-speed serial bus of a single master; bus configuration function is added to the clocked serial
I/O system so that the master can communicate with a number of devices by using two signal lines. When
microcomputers and peripheral ICs make up a serial bus, the number of ports and wiring on the printed circuit boards
can be reduced.
The master can output an “address” to select the slave device with which it is to communicate, a “command” to
tell the slave which operation to perform, and actual “data”, via the serial data bus. The slave identifies the data it
has received from the master as an “address”, “command”, or “data” by using hardware. This SBI function simplifies
the portion of the application program that controls the serial interface.
The SBI function is provided in many devices such as the 75XL series, 75X series, and 8- and 16-bit single-chip
microcomputers in the 78K series.
Figure 5-66 shows an example of the configuration of the serial bus with CPUs and peripheral ICs having a serial
interface conforming to SBI.
Figure 5-66. SBI System Configuration Example
VDD
Master CPU
Slave CPU
µ PD753208
µ
PD753208
SB0, SB1
SB0, SB1
Address 1
SCK
SCK
Slave CPU
SB0, SB1
SCK
Address 2
Slave IC
SB0, SB1
SCK
Address N
Cautions 1. Since the serial data bus pin SB0 (or SB1) is open-drain output in the SBI, the serial data bus
line is in the wired-OR status. The serial data bus line needs a pull-up resistor.
2. When master-slave exchange is to be performed, the I/O switching of the serial clock line
(SCK) is done asynchronously between the master and slave, therefore the pull-up resistor
is also necessary for the SCK.
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(1) Function of SBI
If two or more devices are connected to configure a serial bus with the existing serial I/O method, many ports
and much wiring are necessary to distinguish among the chip select signal, command, and data, and to identify
the busy status, because the existing serial I/O method only provides a data transfer function. Moreover, if
software is used to distinguish the signals and identify the status, the workload of the software increases.
In the SBI mode, the serial bus can be configured by using only two lines: serial clock SCK and serial data bus
SB0 or SB1. Therefore, the number of ports can be reduced and the wiring on the printed circuit board can be
shortened.
The functions of the SBI mode are described below.
(a) Address/command/data identification function
Serial data is identified as an address, command, or data.
(b) Chip select function by using address
The master transmits an address to a slave to select the slave (chip select).
(c) Wake-up function
The slave can judge whether it has received an address (whether the slave has received the chip select signal
from the master) by using the wake-up function (which can be set or cleared via software).
When the wake-up function is set, an interrupt (IRQCSI) is generated when the slave has received an address
coinciding with its own address. Therefore, even when the master communicates with two or more slaves,
the slaves other than that selected by the master can operate independently of the serial communication
between the master and selected slave.
(d) Acknowledge signal (ACK) control function
The acknowledge signal is controlled so that confirmation can be made that serial data has been received.
(e) Busy signal (BUSY) control function
The busy signal is controlled so that the master is notified of the busy status of a slave.
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(2) Definition of SBI
This paragraph describes the format of the serial data in the SBI mode and the meanings of the signals used.
The serial data transferred in the SBI mode are classified into “address”, “command”, and “data”.
Figure 5-67. SBI Transfer Timings
Address transfer
SCK
8
9
SB0, SB1
A7
A0
ACK
BUSY
BUSY
BUSY
Bus release
signal
Command
signal
Command transfer
SCK
9
ACK
READY
SB0, SB1
C7
C0
Data transfer
SCK
8
9
SB0, SB1
D7
D0 ACK
READY
The bus release and command signals are output by the master. BUSY is output by the slave. ACK can be output
by both the master and slave (usually, this signal is output by the receiver of 8-bit data).
The master continues outputting the serial clock since the start of 8-bit data transfer until the BUSY signal is
deasserted.
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(a) Bus release signal (REL)
The bus release signal is asserted when the SB0 or SB1 line goes high while the SCK line is high (i.e., when
the serial clock is not output). This signal is output by the master.
Figure 5-68. Bus Release Signal
“H”
SCK
SB0, SB1
The bus release signal indicates that the master is to transmit an address to a slave. The slave has hardware
that detects the bus release signal.
Caution Positive transition of the SB0 (SB1) pin from low to high is recognized as a bus release signal
when the SCK line is high. If the change timing of the bus is shifted due to the influence of
board capacitance, data that is transmitted may be identified as a bus release signal by
mistake. Exercise care in wiring.
(b) Command signal (CMD)
The command signal is asserted when the SB0 or SB1 line goes low while the SCK line is high (i.e., when
the serial clock is not output). This signal is output by the master.
Figure 5-69. Command Signal
“H”
SCK
SB0, SB1
The slave has hardware that detects the command signal.
Caution Positive transition of the SB0 (SB1) pin from low to high is recognized as a bus release signal
when the SCK line is high. If the change timing of the bus is shifted due to the influence of
board capacitance, data that is transmitted may be identified as a bus release signal by
mistake. Exercise care in wiring.
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(c) Address
An address is 8-bit data output by the master to select a specific slave from the slaves connected to the bus
line.
Figure 5-70. Address
1
2
3
4
5
6
7
8
SCK
A7 A6 A5 A4 A3 A2 A1 A0
SB0, SB1
Address
Bus release signal
Command signal
The 8-bit data following the bus release signal and command signal is defined as an address. The slave
detects an address by using hardware, and checks whether the 8-bit data coincides with its own specification
number (slave address). If the 8-bit data coincides with the slave address, the slave is selected. After that,
the slave communicates with the master, until the master later unselects the slave.
Figure 5-71. Selecting Slave by Address
Unselected
Selected
Slave 1
Slave 2
Slave 3
Slave 4
Master
Unselected
Unselected
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(d) Command and data
The master transmits commands to or transmits data to or receives data from the slave it has selected by
transmitting an address.
Figure 5-72. Command
1
2
3
4
5
6
7
8
SCK
C7 C6 C5 C4 C3 C2 C1 C0
SB0, SB1
Command
Command signal
Figure 5-73. Data
1
2
3
4
5
6
7
8
SCK
D7 D6 D5 D4 D3 D2 D1 D0
Data
SB0, SB1
8-bit data following a command signal is defined as a command. 8-bit data that does not follow a command
signal is defined as data. How to use commands and data can be determined arbitrarily, depending on the
communication specifications.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(e) Acknowledge signal (ACK)
The acknowledge signal is used for confirmation of data reception between the transmitter and receiver.
Figure 5-74. Acknowledge Signal
(When output in synchronization with 11th SCK)
SCK
8
9
10
11
SB0, SB1
ACK
(When output in synchronization with 9th SCK)
SCK
8
9
SB0, SB1
ACK
The acknowledge signal is a one-shot pulse synchronized with the falling edge of SCK after 8-bit data has
been transferred, and can be synchronized with arbitrary assertion of SCK.
The transmitter side checks, after it has transmitted 8-bit data, whether the receiver side returns an
acknowledge signal. If the acknowledge signal is not returned in a fixed time period after the data has been
transmitted, it is judged that the data has not been received correctly.
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(f) Busy (BUSY) and ready (READY) signals
A busy signal is output by a slave to inform the master that the slave is preparing for transmission or reception.
A ready signal is also output by a slave to inform the master that the slave is now ready for transmission
or reception.
Figure 5-75. Busy and Ready Signals
SCK
8
9
SB0, SB1
ACK
BUSY
READY
In the SBI mode, the slave makes the SB0 (or SB1) line low to inform the master of the busy status.
The busy signal is output following the acknowledge signal output by the master or slave. The busy signal
is asserted or deasserted in synchronization with the falling edge of SCK. The master automatically ends
output of serial clock SCK when the busy signal is deasserted.
The master can start the next transfer when the busy signal has been deasserted and the ready signal is
asserted.
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(3) Register setting
When the SBI mode is used, the following two registers must be set:
•
•
Serial operation mode register (CSIM)
Serial bus interface control register (SBIC)
(a) Serial operation mode register (CSIM)
When the SBI mode is used, set the CSIM as shown below. (For the format of the CSIM, refer to 5.6.3 (1)
Serial operation mode register (CSIM).)
The CSIM is manipulated by using 8-bit manipulation instructions. Bits 7, 6, and 5 can also be manipulated
in 1-bit units.
The contents of the CSIM are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in SBI mode.
Address
FE0H
Symbol
CSIM
7
6
5
4
3
2
1
0
CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
Serial clock select bits (W)
Serial interface operation mode select bits (W)
Wake-up function specification bit (W)
Coincidence signal from address comparator (R)
Serial interface operation enable/disable bit (W)
Remark (R) : read only
(W): write only
Serial interface operation enable/disable bit (W)
Operation of shift register
Shift operation range
Serial clock counter
IRQCSI flag
Can be set
SO/SB0 or SI/SB1 pin
CSIE
1
Count operation
Function in each mode and
port 0 function shared
Signal from address comparator (R)
COINote
Clear condition (COI = 0)
Set condition (COI = 1)
When slave address register (SVA) data and shift
register data coincide
When slave address register (SVA) data and shift
register data do not coincide
Note COI can be read before the start of serial transfer and after the completion of serial transfer. An undefined
value is read if this bit is read during transfer. Data written to COI by an 8-bit manipulation instruction is
ignored.
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Wake-up function specification bit (W)
WUP
0
1
Sets IRQCSI each time a serial transfer is completed with SBI mode masked
Used only by the slave in SBI mode. When and only when the address received by the slave after the
bus has been released coincides with the data in the slave register of the slave (wake-up status),
IRQCSI is set. SB0 or SB1 goes into a high-impedance state.
Caution BUSY is not deasserted if WUP is set to 1 while the BUSY signal is output. In the SBI mode, after
a command to deassert the BUSY signal has been issued, the BUSY signal is output until the next
serial clock (SCK) falls. Before setting WUP to 1, be sure to deassert the BUSY signal and confirm
that the SB0 (or SB1) pin has gone high.
Serial interface operation mode select bit (W)
CSIM4
0
CSIM3
1
CSIM2
0
Bit order of shift register
SO pin function
SB0
SI pin function
SIO7-0 ↔ XA (MSB first)
P03 (CMOS input)
(N-ch open-drain I/O)
1
P02 (CMOS input)
SB1
(N-ch open-drain I/O)
Serial clock select bit (W)
CSIM1
CSIM0
Serial clock
SCK pin mode
Input
0
0
1
1
0
1
0
1
External clock input to SCK pin
Timer/event counter output (TO)
Output
4
Note
fX/2 (262 kHz)
3
Note
fX/2 (524 kHz)
Note ( ): fX = 4.19 MHz operation
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(b) Serial bus interface control register (SBIC)
When the SBI mode is used, set SBIC as shown below (for the format of SBIC, refer to 5.6.3 (2) Serial bus
interface control register (SBIC).)
This register is manipulated by using bit manipulation instructions.
The contents of SBIC are cleared to 00H at reset.
The shaded portion in the figure indicates the bits used in the three-wire serial I/O mode.
Address
FE2H
Symbol
CSIM
7
6
5
4
3
2
1
0
BSYE ACKD ACKE ACKT CM0D RELD CMDT RELT
Bus release trigger bit (W)
Command trigger bit (W)
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Acknowledge enable bit (R/W)
Acknowledge detection flag (R)
Busy enable bit (R/W)
Remark (R)
: read only
(W) : write only
(R/W) : read/write
Busy enable bit (R/W)
BSYE
0
1
<1> Disables automatic output of busy signal
<2> Stops output of busy signal in synchronization with falling edge of SCK immediately after clear
instruction has been executed
Following acknowledge signal, busy signal is output in synchronization with falling edge of SCK
Acknowledge detection flag (R)
ACKD
Clear condition (ACKD = 0)
Set condition (ACKD = 1)
<1> At start of transfer
<2> At reset input
When acknowledge signal (ACK) is detected
(synchronized with falling edge of SCK)
Acknowledge enable bit (R/W)
ACKE
0
1
Disables automatic output of acknowledge signal (output by ACKT is enabled)
When set before end of transfer
When set after end of transfer
ACK is output in synchronization with 9th SCK
ACK is output in synchronization with SCK immediately after
execution of set instruction
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Acknowledge trigger bit (W)
ACKT
If this bit is set after end of transfer, ACK is output in synchronization with next SCK. This bit is automati-
cally cleared to 0 after ACK signal has been output.
Cautions 1. Do not set this bit to 1 before the end of serial transfer or during transfer.
2. ACKT cannot be cleared by software.
3. To set ACKT, clear ACKE to 0.
Command detection flag (R)
ACKD
Clear condition (CMDD = 0)
Set condition (CMDD = 1)
<1> When transfer start instruction is executed
<2> When bus release signal (REL) is detected
<3> When reset signal is input
When command signal (CMD) is detected
<4> CSIE = 0 (Refer to Figure 5-56.)
Bus release detection flag (R)
ACKD
Clear condition (RELD = 0)
Set condition (RELD = 1)
<1> When transfer start instruction is executed
<2> When reset signal is input
When bus release signal (REL) is detected
<3> CSIE = 0 (Refer to Figure 5-56.)
<4> When SVA and SIO do not coincide at time
address is received
Command trigger bit (W)
CMDT
This bit controls output trigger of command signal (CMD). When this bit is set to 1, SO latch is cleared to
0. After that, the CMDT bit is automatically cleared to 0.
Caution Do not set SB0 (or SB1) during serial transfer. Be sure to set it before the start of or after the
end of transfer.
Bus release trigger bit (W)
RELT
This bit controls output trigger of bus release signal (REL). When this bit is set to 1, SO latch is set to 1.
After that, the RELT bit is automatically cleared to 0.
Caution Do not set SB0 (or SB1) during serial transfer. Be sure to set it before the start of or after the
end of transfer.
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(4) Selecting the serial clock
The serial clock is selected by using the bits 0 and 1 of the serial operation mode register (CSIM). The following
four types of serial clocks can be selected:
Table 5-11. Selection of Serial Clock and Applications (in SBI mode)
Mode Register
Serial Clock
Timing when shift register can be read/
written and serial transfer can be started
Application
CSIM
1
CSIM
0
Masking
Source
Serial Clock
0
0
1
1
0
1
0
1
External
SCK
Automati-
cally masked
at end of
<1> In operable mode (CSIE = 1)
Slave CPU
<2> If serial clock is masked after 8-bit serial
transfer
TOUT
F/F
Serial transfer at any
speed
transfer of 8-
bit data
<3> When SCK is high
4
fX/2
Medium-speed serial
transfer
3
fX/2
High-speed serial transfer
When the internal system clock is selected, SCK is internally stopped when SCK has been asserted and
deasserted eight times. Externally, however, counting SCK continues until the slave enters the ready status.
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(5) Signals
Figures 5-76 through 5-81 illustrate the operation of the signals in the SBI mode. Table 5-12 lists the signals
used in the SBI mode.
Figure 5-76. RELT, CMDT, RELD, CMDD Operation (master)
Transfer start indication
SIO
"H"
SCK
SO latch
RELT
CMDT
RELD
CMDD
Figure 5-77. RELT, CMDT, RELD, CMDD Operation (slave)
Transfer start indication
SIO latch
SIO
SCK
1
2
7
8
SO latch
D7
D6
D1
D0
RELT
(Master)
CMDT
(Master)
When address match is found
RELD
When no address match is found
CMDD
Figure 5-78. ACKT Operation
Set after transfer is complete
SCK
6
7
8
9
ACK signal is output during one
clock period immediately after set
SB0, SB1
ACKT
D2
D1
D0
ACK
When set during this period
Caution Do not set ACKT before transfer terminates.
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Figure 5-79. ACKE Operation
(a) When ACKE = 1 when transfer is complete
SCK
SB0, SB1
ACKE
1
2
7
8
9
D7
D6
D2
D1
D0
ACK
ACK signal is output on
the ninth clock cycle.
When ACKE = 1 at this point of time.
(b) When set after transfer is complete
SCK
SB0, SB1
ACKE
6
7
8
9
ACK signal is output during
one clock period immediately
after set.
D2
D1
D0
ACK
When set during this period and ACKE = 1 on
the next SCK falling edge
(c) When ACKE = 0 when transfer is complete
SCK
SB0, SB1
ACKE
1
2
7
8
9
D7
D6
D2
D1
D0
ACK signal is not output.
When ACKE = 0 at this point of time
(d) When the period during which ACKE = 1 is short
SCK
SB0, SB1
ACKE
ACK signal is not output
When ACKE is set and reset during this
period and remains reset to 0 on the SCK
falling edge
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Figure 5-80. ACKD Operation
(a) When ACK signal is output during the period of the ninth SCK clock
Transfer start indication
SIO
Transfer start
SCK
6
7
8
9
SB0, SB1
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after the ninth SCK clock
Transfer start indication
Transfer start
SIO
6
7
8
9
SCK
ACK
SB0, SB1
D2
D1
D0
ACKD
(c) Reset timing when transfer start indication is given during BUSY
Transfer start indication
SIO
Transfer start
6
7
8
9
SCK
ACK
BUSY
SB0, SB1
D2
D1
D0
D7
D6
ACKD
Figure 5-81. BSYE Operation
6
7
8
9
SCK
SB0, SB1
ACK
BUSY
BSYE
When BSYE = 1 at this point of time
When reset during this period and BSYE = 0
on the SCK falling edge
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Table 5-12. Signal in SBI Mode (1/2)
Output
Device
Output
Signal Name
Definition
Timing Chart
Flag Influence
Explanation
Conditions
Bus release
signal (REL)
Master
SB0, SB1 rising edge
when SCK = 1
• Set RELT
• Set RELD
When this signal is
followed by CMD
signal output, it
• Clear CMDD
SCK
“H”
SB0, SB1
indicates that transmit
data is address.
Command
Master
SB0, SB1 falling edge
when SCK = 1
• Set CMDT
• Set CMDD
(i) After REL signal is
output, transmit
signal (CMD)
SCK
“H”
data is address.
(ii) REL signal is not
output. Transmit
data is command.
SB0, SB1
Acknowledge
signal (ACK)
Master/
slave
Low signal output to
SB0, SB1 during the
period of one clock SCK
after completion of
serial reception
<1> ACKE = 1
<2> ACKT set
• Set ACKD
Completion of
reception.
[Synchronous busy signal]
Busy signal
(BUSY)
Slave
Slave
[Synchronous busy signal]
Low-level output to
• BSYE = 1
–
–
Serial reception
9
SCK
cannot be done
ACK
BUSY
SB0, SB1 following
acknowledge signal
because processing is
being performed.
READY
READY
SB0, SB1
SB0, SB1
D0
D0
ACK
BUSY
Ready signal
(READY)
High-level output to
SB0, SB1 before start or
after completion of serial
transfer
<1> BSYE = 0
<2> Execution of
SIO data write
instruction
Serial reception is
enabled.
(transfer start
indication)
Table 5-12. Signal in SBI Mode (2/2)
Output
Device
Output
Signal Name
Definition
Timing Chart
Flag Influence
Explanation
Conditions
Serial clock
(SCK)
Master
Synchronizing clock for
output of address,
command, data, ACK
signal, synchronous
BUSY signal, etc.
Execution of
data write
IRQCSI is set
(on the rising
edge of ninth
clock)Note 1
Signal output timing
to serial data bus
instruction into
SIO when CSIE
= 1 (serial
SCK
1
2
7
8
9
10
SB0, SB1
Address, command, or
data is transferred on
the first eight.
transfer start
indication)Note 2
Address (A7-A0) Master
8-bit data transferred in
synchronization with
SCK after REL and CMD
signals are output.
Slave device address
value on serial bus
1
2
7
8
SCK
SB0, SB1
REL CMD
Command
(C7-C0)
Master
8-bit data transferred in
synchronization with
SCK after only CMD
signal is output without
REL signal output.
Indication, message,
etc., to slave device.
1
2
7
8
SCK
SB0, SB1
CMD
1
Data (D7-D0)
Master
8-bit data transferred in
synchronization with
Data processed by
slave or master.
2
7
8
SCK
or slave
SCK when neither REL
nor CMD signal is output.
SB0, SB1
Notes 1. When WUP = 0, IRQCSI is always set on the rising edge of the ninth SCK clock.
When WUP = 1, IRQCSI is set on the rising edge of the ninth SCK clock only when address is received and matches the value in the slave address register
(SVA).
2. In the BUSY state for the data transmission and reception (transfer), transfer is started after the READY state is entered.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(6) Pin configuration
The configurations of the serial clock pin (SCK) and serial data bus pin (SB0 or SB1) are as follows:
(a) SCK ··················· Inputs or outputs serial clock
<1> Master ······ CMOS, push-pull output
<2> Slave ········ Schmitt input
(b) SB0, SB1 ·········· Serial data I/O pin
N-ch open-drain output and Schmitt input for both master and slave
Because the serial data bus line is of the N-ch open-drain output configuration, an external pull-up resistor
must be connected to it.
Figure 5-82. Pin Configuration
Slave device
Master device
(Clock output)
SCK
SCK
Clock output
(Clock input)
Clock input
Serial clock
R
L
SB0, SB1
SB0, SB1
N-ch open-drain
SO
N-ch open-drain
Serial data bus
SO
SI
SI
Caution Because it is necessary to turn off the N-ch transistor when data is received, write FFH to SIO
in advance. The transistor can be always turned off during transfer. However, if the wake-up
function specification bit (WUP) = 1, the N-ch transistor is always off. Therefore, it is not
necessary to write FFH to SIO before reception.
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(7) Detection of address coincidence
In the SBI mode, the master transmits an address to select a specific slave and then starts communicating with
the selected slave.
Whether the address transmitted to a slave coincides with the address of the slave is detected by the hardware
of the slave. For this purpose, the slave is provided with a slave address register (SVA). In the wake-up status
(WUP = 1), the slave sets IRQCSI only when the address transmitted from the master coincides with the value
set in the SVA of the slave.
Cautions 1. Whether a slave is selected or not is detected by observing if there is a coincidence
between the address transmitted from the master and the slave address of the slave after
the bus has been released (RELD = 1).
For this coincidence detection, an address coincidence interrupt (IRQCSI) that is gener-
ated when WUP = 1 is usually used. Therefore, detect whether a slave is selected or not
when WUP = 1.
2. To detect whether the slave is selected when WUP = 0 and without using an interrupt, do
not detect the address coincidence, but transmit and receive a command determined by
the program in advance.
(8) Error detection
In the SBI mode, because the status of the serial bus SB0 or SB1 during transmission is also loaded to the shift
register SIO of the device transmitting data, an error can be detected by the following methods:
(a) By comparing SIO data before and after transmission
If the two data differ from each other, it can be assumed that a transmission error has occurred.
(b) By using slave address register (SVA)
The transmit data is placed in SIO and SVA and transmission is executed. After transmission, the COI bit
(coincidence signal from the address comparator) of the serial operation mode register (CSIM) is tested. If
this bit is “1”, the transmission has been completed normally. If it is “0”, it can be assumed that a transmission
error has occurred.
(9) Communication operation
In the SBI mode, the master usually selects one of the slave devices with which it is to communicate, by outputting
an “address” onto the serial bus.
After the master has selected the slave device, commands and data are transmitted and received between the
master and slave. In this way, serial communication is implemented.
Figures 5-83 through 5-86 show the timing charts illustrating each kind of data communication.
In the SBI mode, the shift register performs shift operations in synchronization with the falling edge of the serial
clock (SCK), and the transmit data is latched to the SO latch and output from the SB0/P02 or SB1/P03 pin with
the MSB first. The receive data input to the SB0 (or SB1) pin at the rising edge of SCK is latched to the shift
register.
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Figure 5-83. Address Transmission Operation from Master Device to Slave Device (when WUP = 1)
Master device processing (transmitting party)
Write into
SIO
CMDT RELT CMDT
set set set
Interrupt processing (preparation for the next serial transfer)
Program processing
SCK
stop
IRQCSI
generation
ACKD
set
Hardware operation
Serial transmission operation
Transfer line
SCK pin
1
2
3
4
5
6
7
8
9
SB0, SB1 pin
A7
A6
A5
A4
A3
A2
A1
A0
ACK BUSY
READY
Address
Slave device processing (receiving party)
Program processing
ACKT
set
BUSY
clear
WUP ← 0
IRQCSI
generation
CMDD CMDD CMDD
ACK BUSY
output output
BUSY
clear
Hardware operation
Serial receiving operation
set
clear set
RELD
set
(when SVA = SIO)
Figure 5-84. Command Transmission Operation from Master Device to Slave Device
Master device processing (transmitting party)
CMDT Write into
Program processing
Interrupt processing (preparation for the next serial transfer)
set
SIO
IRQCSI
generation
ACKD
set
SCK
stop
Hardware operation
Serial transmission operation
Transfer line
SCK pin
1
2
3
4
5
6
7
8
9
SB0, SB1 pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command
Slave device processing (receiving party)
Program processing
SIO
read
Command ACKT
BUSY
clear
interpretation
set
CMDD
set
IRQCSI
generation
ACK BUSY
output output
BUSY
clear
Hardware operation
Serial receiving operation
Figure 5-85. Data Transmission Operation from Master Device to Slave Device
Master device processing (transmitting party)
Write into
SIO
Program processing
Interrupt processing (preparation for the next serial transfer)
IRQCSI
generation
ACKD
set
SCK
stop
Hardware operation
Serial transmission operation
Transfer line
SCK pin
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
BUSY
READY
SB0, SB1 pin
Data
Slave device processing (receiving party)
Program processing
ACKT
set
BUSY
clear
SIO read
IRQCSI
generation
BUSY
clear
ACK BUSY
output output
Hardware operation
Serial receiving operation
Figure 5-86. Data Transmission Operation from Slave Device to Master Device
Master device processing (receiving party)
Write FFH
into SIO
Write FFH
into SIO
ACKT
set
Receive data processing
SIO read
Program processing
Serial receiving
operation
SCK
stop
IRQCSI
generation
ACK
output
Hardware operation
Serial receiving operation
Transfer line
SCK pin
1
2
3
4
5
6
7
8
9
1
2
SB0, SB1 pin
BUSY
READY
D7
D6
D5
D4
D3
D2
D1
D0
ACK
BUSY
D7
D6
READY
Data
Slave device processing (transmitting party)
Program processing
Write into
SIO
Write into
SIO
BUSY
clear
IRQCSI
generation
ACKD
set
BUSY BUSY
output
Hardware operation
Serial transmission operation
clear
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(10) Starting transfer
Serial transfer is started when the transfer data is placed in the shift register (SIO), if the following two conditions
are satisfied:
•
•
Serial interface operation enable/disable bit (CSIE) = 1
The internal serial clock is stopped after 8-bit serial transfer or SCK is high
Cautions 1. Transfer is not started even if CSIE is set to “1” after the data has been written to the
shift register.
2. Because it is necessary to turn off the N-ch transistor when data is received, write FFH
to SIO in advance.
When the wake-up function specification bit (WUP) = 1, however, it is not necessary to
write FFH to SIO, because the N-ch transistor is always off.
3. If data is written to SIO while the slave is busy, the data is not lost.
When the SB0 (or SB1) input goes high and the slave becomes ready after the slave has
been released from the busy status, transfer is started.
When an 8-bit transfer has been completed, the serial transfer is automatically stopped, and an interrupt request
flag (IRQCSI) is set.
Example To transfer the RAM data addressed by the HL register and at the same time, load the SIO data
in the accumulator, and start serial transfer
MOV XA,
@HL
SIO
; Takes out transmit data from RAM
; or CLR1 MBE
SEL
MB15
XA,
XCH
; Exchanges transmit data and receive data, and starts transfer
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(11) Notes on SBI mode
(a) Whether a slave is selected or not is detected by observing if there is a coincidence between an address
transmitted from the master after the bus has been released (RELD = 1) and the slave address of the slave.
For this coincidence detection, an address coincidence interrupt (IRQCSI) that is generated when WUP
= 1 is usually used. Therefore, detect whether a slave is selected or not by using the slave address when
WUP = 1.
(b) To detect whether a slave is selected or not when WUP = 0 without using the interrupt, do not detect address
coincidence, but transmit or receive a command set in advance by program.
(c) If WUP is set to 1 while the BUSY signal is output, the BUSY signal is not deasserted. In the SBI mode,
the BUSY signal is output until the next serial clock (SCK) falls after a command that deassert the BUSY
signal has been issued. Before setting WUP to 1, be sure to deassert the BUSY signal and confirm that
the SB0 (or SB1) pin has gone high.
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(12) Application of SBI mode
This paragraph introduces an application example in which serial data communication is executed in the SBI
mode. In this example, the µPD753208 can operate as both the master and slave CPU on the serial bus.
Moreover, the master can be changed by a command.
(a) Serial bus configuration
In the application example presented below, it is assumed that the µPD753208 is connected to the bus
line as one of the devices in the serial bus.
The µPD753208 uses the serial data bus SB0 (or SB1) and serial clock SCK pins.
Figure 5-87 shows an example of serial bus configuration.
Figure 5-87. Example of Serial Bus Configuration
VDD
Master CPU
Slave CPU
µ
µ
PD753208
PD753208
SB0, SB1
SB0, SB1
Address 1
SCK
SCK
Slave CPU
SB0, SB1
SCK
Address 2
Slave IC
SB0, SB1
SCK
Address N
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(b) Command description
<Types of commands>
In this application example, the following commands are used:
<1> READ
: Transfers data from slave to master
<2> WRITE : Transfers data from master to slave
<3> END
: Notifies slave of end of WRITE command
<4> STOP
: Notifies slave that WRITE command has been aborted
<5> STATUS : Reads status of slave
<6> RESET : Unselects slave currently selected
<7> CHGMST : Relinquishes mastership to slave
<Communication procedure>
Communication between the master and a slave is carried out in the following procedure:
<1> The master transmits the address of a slave with which the master is to communicate, to select the
slave (chip select).
The slave that has received the address returns ACK to start communication with the master (the
slave is selected).
<2> Commands and data are transmitted between the master and the slave selected in <1>.
Note that the other slaves must be unselected, because commands and data are transmitted between
the master and a slave on a one-to-one basis.
<3> Communication ends when the slave is unselected. The slave is unselected in the following cases:
•
•
When the master transmits the RESET command, the selected slave is unselected.
When the master is changed to a slave by the CHGMST command, the device changed to a slave
is unselected.
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<Command format>
Here is the transfer format of each command:
<1> READ command
This command reads data from a slave. The number of data to be read varies from 1 to 256 bytes.
The master specifies the number of data as a parameter. If 00H is specified as the number of data,
256 bytes of data is transferred.
Figure 5-88. Transfer Format of READ Command
M
S
M
S
S
S
S
S
Number
READ
ACK
ACK
Data 0
ACK ····· Data N
Data
ACK
of data
Command
Data
Data
Remark M : output by master
S : output by slave
If the slave has more data than the number of data it has received, the slave returns ACK; if not, the
slave does not return ACK, and an error occurs.
The master sends ACK to the slave each time it receives 1 byte.
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<2> WRITE, END, and STOP commands
The WRITE command writes data to a slave. The number of data to be written is variable from 1 to
256 bytes. The master specifies the number of data as a parameter. If 00H is specified as the number
of data, data of 256 bytes is transferred.
Figure 5-89. Transfer Formats of WRITE and END Commands
M
S
M
S
M
S
M
S
M
S
Number
WRITE
ACK
ACK
Data 0
ACK ····· Data N
Data
ACK
END
ACK
of data
Command
Command
Data
Data
Remark M : output by master
S : output by slave
The slave returns ACK after it has received the number of data, if it has an enough area to store the
received data. If the area runs short, the slave does not return ACK, and an error occurs.
The master sends the END command after it has transferred all the data. This command notifies
the slave that all the data have been correctly transferred.
The slave receives the END command even before all the data have been received. In this case,
the data which has been received immediately before receiving the END command is valid.
The master compares the contents of SIO before and after transfer to check to see if the data have
been correctly output onto the bus. If the contents of SIO before and after transfer differ, the master
sends the STOP command to stop data transfer.
Figure 5-90. Transfer Format of STOP Command
M
S
M
S
Data
ACK
STOP
ACK
Data
Command
Stops data
transfer.
Checks data.
Error occurs.
Remark M : output by master
S : output by slave
When the slave receives the READ command, it invalidates 1-byte of the data received immediately
before reception of the READ command.
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<3> STATUS command
This command reads the status of the slave currently selected.
Figure 5-91. Transfer Format of STATUS Command
M
S
S
S
Status
ACK
Status
ACK
Data
Command
Remark M : output by master
S : output by slave
The format of the status returned by the slave is as follows:
Figure 5-92. Status Format of STATUS Command
MSB
Status
LSB
7
6
5
4
3
2
1
0
Bit indicating whether slave has data to transfer
All 0
0: Slave has no data to transfer
1: Slave has data of 1 byte or more to transfer
Bit indicating whether slave is ready to receive data
0: Slave does not have enough area to store received data
1: Slave has area of 1 byte or more to store received data
Bit indicating occurrence of error
0: No error
1: Error occurs during previous transfer
Bit indicating whether master can be changed
0: Master cannot be changed
1: Master can be changed
The master returns ACK when it has received the data from the slave.
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<4> RESET command
This command unselects the slave currently selected. By sending the RESET command, the master
can unselect all the slaves.
Figure 5-93. Transfer Format of RESET Command
M
S
RESET
ACK
Command
Remark M : output by master
S : output by slave
<5> CHGMST command
This command gives the mastership to the slave currently selected.
Figure 5-94. Transfer Format of CHGMST Command
M
S
M
S
CHGMST
ACK
DATA
ACK
Data
Command
Remark M : output by master
S : output by slave
When the slave has received the CHGMST command, it decides whether it can receive mastership,
and returns the following data to the master:
•
•
FFH: Master can be changed
00H: Master cannot be changed
The slave compares the contents of SIO before and after transfer of data. If the SIO contents do
not coincide, the slave does not return ACK, and an error occurs.
The master returns ACK when it has received data. If the received data is FFH, the master starts
operating as a slave. After the slave has sent data FFH and received ACK from the master, it starts
operating as a master.
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<Occurrence of error>
An error may occur during communication between the master and a slave.
If an error occurs, the slave notifies the master of error occurrence by not returning ACK to the master.
If an error occurs only when the slave receives data, the slave sets the bit of the status that indicates
occurrence of an error and cancels the processing of all the commands under execution.
The master checks whether the slave has returned ACK after it has completed transfer of 1 byte. If
the slave does not return ACK in specific time after the master has completed transfer, the master
judges that an error has occurred, and outputs a dummy ACK signal.
Figure 5-95. Operations of Master and Slave in Case of Error
Processing
by slave
Reception completed.
Error occurs. Slave stops processing.
ACK
SB0
Error data
ACK wait time
Processing
by master
Master checks whether
ACK is returned from slave.
Error occurs.
Master outputs ACK.
Transfer completed.
Master starts checking ACK.
The following types of errors may occur:
•
Error occurs in slave
<1> If the transfer format of a command is wrong
<2> If an undefined command is received
<3> If the number of data to be transferred by the slave runs short when READ command is
executed
<4> If the slave does not have an enough area to store data when the WRITE command is
executed
<5> If the data transferred by the READ, STATUS, or CHGMST command changes
If any of the above occurs, the slave does not return ACK.
•
Error occurs in master
When the data to be transferred by the master changes when the WRITE command is executed,
the master sends the STOP command to the slave.
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5.6.8 SCK pin output manipulation
The SCK/P01 pin, which incorporates an output latch, can also produce static output by software control in addition
to a normal serial clock.
The number of SCKs can be set as desired by using software to control the P01 output latch (the SO/SB0/P02,
and SI/SB1/P03 pins are controlled by setting the SBIC RELT and CMDT bits).
The SCK/P01 pin output control method is described below:
<1> The serial operation mode register (CSIM) is set (SCK pin: Output mode). SCK from serial clock control circuit
is set to 1 during serial transfer stops.
<2> The P01 output latch is controlled by using bit manipulation (operation) instructions.
Example To output one clock pulse to SCK/P01 pin by using software.
SEL
MB15
; or CLR1 MBE
MOV
MOV
CLR1
SET1
XA, #10000011B ; SCK (fX/23), output mode
CSIM, XA
0FF0H.1
0FF0H.1
; SCK/P01 ← 0
; SCK/P01 ← 1
Figure 5-96. SCK/P01 Pin Configuration
Address
FF0H.1
To internal
circuit
P01
output latch
P01/SCK
From serial clock
control circuit
SCK
SCK pin output mode
The P01 output latch is mapped in bit 1 of address FF0H. When the RESET signal is generated, the P01 output
latch is set to 1.
Cautions 1. The P01 output latch must be set to 1 during normal serial transfer.
2. Do not use “PORT0.1” to specify the P01 output latch address. Write directly the address
(0FF0H.1) or specify with SCKP in operand. At that time, set MBS to 0, or set MBE to 1 and
MBS to 15.
Do not use
Use
CLR1 0FF0H.1
CLR1 PORT0.1
SET1 PORT0.1
SET1 0FF0H.1
CLR1 SCKP
SET1 SCKP
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5.7 LCD Controller/Driver
5.7.1 LCD controller/driver configuration
The µPD753208 incorporates a display controller which generates segment and common signals according to the
display data memory contents and incorporates segment and common drivers which can drive the panel directly.
Figure 5-97 shows the LCD controller/driver configuration.
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Figure 5-97. LCD Controller/Driver Block Diagram
Internal bus
4
4
4
4
4
8
4
8
4
4
4
Port 8
output latch
3 2 1 0
Port 9
Port mode
LCD/port
selection
register
1F7H
1F0H
1EFH
1ECH
Display
control
register
Port 3
Port mode
register group A
Display mode register
output latch register group C
output latch
3 2 1 0
0
1
3
3
2
1
0
0
3
3
2
1
0
3
2
1
0
0
3
3
2
1
0
0
1
0
1
0
Decoder
2
1
2
1
0
3
2
1
2
1
Timing
controller
f
LCD
Port 8
Port 9
Input/Output buffer
LCD drive
voltage control
Segment driver
Segment driver
Common driver
Input/Output buffer
LCD drive
mode
change
0
1
2
3
0
1
2
3
S23/P80
S16/P93
S15
S12
COM3 COM2 COM1 COM0
VLC2
VLC1
V
LC0
P31/SYNC P30/LCDCL
CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
5.7.2 LCD controller/driver functions
The µPD753208 LCD controller/driver functions are as follows:
(a) Display data memory is read automatically by DMA operation and segment and common signals are generated.
(b) Display mode can be selected from among the following five:
<1> Static
<2> 1/2 duty (time multiplexing by 2), 1/2 bias
<3> 1/3 duty (time multiplexing by 3), 1/2 bias
<4> 1/3 duty (time multiplexing by 3), 1/3 bias
<5> 1/4 duty (time multiplexing by 4), 1/3 bias
(c) A frame frequency can be selected from among four in each display mode.
(d) A maximum of 12 segment signal output pins (S0-S23) and four common signal output pins (COM0-COM3).
(e) The segment signal output pins (S12-S23) can be changed to the I/O ports (PORT8 and PORT9).
(f) Split-resistor can be incorporated to supply LCD drive power. (Mask option)
•
•
Various bias methods and LCD drive voltages can be applicable.
When display is off, current flowing through the split resistor is cut.
(g) Display data memory not used for display can be used for normal data memory.
Table 5-13 lists the maximum number of picture elements that can be displayed in each display mode.
Table 5-13. Maximum Number of Displayed Picture Elements
Bias Method
Time Division Common Signals Used
Maximum Number of Picture Elements
12 (segment 24 × common 1)Note 1
24 (segment 24 × common 2)Note 2
36 (segment 24 × common 3)Note 3
–
Static
COM0 (COM1, 2, 3)
COM0, 1
1/2
2
3
3
4
COM0, 1, 2
1/3
COM0, 1, 2, 3
48 (segment 24 × common 4)Note 4
Notes 1. 1 digits (8 segment signals/digit) on LCD panel (display).
2. 3 digits (4 segment signals/digit) on LDC panel (display).
3. 4 digits (3 segment signals/digit) on LCD panel (display).
4. 6 digits (2 segment signals/digit) on LCD panel (display).
5.7.3 Display mode register (LCDM)
The display mode register (LCDM) consists of eight bits to specify the display mode, LCD clock, frame frequency,
and display output on/off control.
LCDM is set by using an 8-bit memory manipulation instruction. Only bit 3 (LCDM3) can be set and cleared by
using bit operation (manipulation) instructions.
When the RESET signal is generated, all the bits are cleared to “0”.
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Figure 5-98. Display Mode Register Format
Address
F8CH
7
0
6
0
5
4
3
2
1
0
Symbol
LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0 LCDM
LCD Clock Selection
LCDM5
LCDM4
LCDCLNote
fW/29 (64 Hz)
0
0
1
1
0
1
0
1
fW/28 (128 Hz)
fW/27 (256 Hz)
fW/26 (512 Hz)
Note LCDCL is supplied only when the watch timer operates. To use the LCD controller, bit 2 of watch mode
register WM should be set to 1.
Display Mode Selection
Time
LCDM3
LCDM2
LCDM1
LCDM0
division Bias method
value
0
1
1
1
1
1
×
0
0
0
0
1
×
0
0
1
1
0
×
0
1
0
1
0
Display offNote
4
1/3
1/3
1/2
1/2
3
2
3
Static
Prohibited
Other than the above
Note All segment signals are unselected.
Frame Frequency (Hz)
LCDCL
Display duty
fW/29
(64 Hz)
64
fW/28
(128 Hz)
128
fW/27
(256 Hz)
256
fW/26
(512 Hz)
512
Static
1/2
32
64
128
256
1/3
21
43
85
171
1/4
16
32
64
128
When fW = 32.768 kHz
fW : Input clock to watch timer (fX/128)
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5.7.4 Display control register (LCDC)
The display control register controls LCD drive as follows.
•
•
•
Enables/disables the common and segment outputs.
Cuts the current flowing through the split resistors for the LCD driving power supply.
Enables/disables synchronization clock (LCDCL) and synchronization signal (SYNC) outputs to the external
segment signal extending controller/driver.
•
Switching of LCD drive modes (normal mode and low-voltage mode) by supply voltage
Normal mode ·············· Low current consumption.
Low-voltage mode ······ For low voltage operation.
Caution To drive LCD at VDD ≤ 2.2 V, be sure to set the low-voltage mode.
The LCDC is set by a 4-bit memory manipulation instruction.
When the RESET signal is generated, all the bits of the display control register are cleared to “0”.
Figure 5-99. Format of Display Control Register
Address
F8EH
3
0
2
1
0
Symbol
LCDC2 VAC0 LCDC0 LCDC
Output enable/disable specification bit for LCDCL and SYNC signal
LCDC2
0
1
Disables the output of LCDCL and SYNC signal.
Enables the output of LCDCL and SYNC signal.
Caution The LCDCL and SYNC signal are provided for system extension in the future. Currently, disable
the signal output.
Bit for LCD drive mode select
VAC0
0
1
Normal mode (2.2 V ≤ VDD ≤ 5.5 V)
Low-voltage mode (1.8 V ≤ VDD ≤ 5.5 V)
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Display output status by LCDC0 and LCDM3
LCDC0
LCDM3
0
1
×
0
1
COM0-COM3
Outputs “L” (display off).
Outputs a common signal
corresponding to the display
mode.
Outputs a common signal
corresponding to the display
mode.
S12-S15
Outputs “L” (display off).
Outputs a segment signal
corresponding to the display
mode (outputs an unselected
level, display off).
Outputs a segment signal
corresponding to the display
mode (display on).
S16-S23 segments
specification pin
S16-S23 bit ports
I/O ports. Whether the port is used as an input or output port depends on the specification of the
specification pin port mode register group C (PMGC)
Power supply for Off (high-impedance)Note
the split resistors
On (high-level)Note
On (high-level)Note
(BIAS pin output)
Note The descriptions in the parentheses apply to the case where the split resistors are not used.
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5.7.5 LCD/Port Selection Register (LPS)
The LCD/port selection register (LPS) switches the segment signal output (S16-S23) to the input/output port.
Of segment signal outputs, S16 to S19 are also used as PORT9 and S20 to S23, as PORT8. Four outputs each
are switched together as one unit.
By setting the LPS value to “000”, S16 to S23 can be switched to input/output ports (PORT9 and PORT8).
The LPS bits are set by a 4-bit memory manipulation instruction.
All LPS bits can be cleared to “0” by generating the RESET signal.
Figure 5-100. LCD/Port Selection Register Format
Address
F8FH
Symbol
LPS2 LPS1 LPS0 LPS
3
0
2
1
0
Usable pin
Segment output pin
—
Port pin
0
0
0
1
0
1
0
P93-P90, P83-P80
0
0
S16-S19
P83-P80
—
S16-S19, S20-S23
Other than the above Setting prohibited
Cautions 1. All LPS bits are cleared to “0” during resetting, and the LCD cannot be used. Be sure to set
the LPS value to 001 or 010 when using the LCD.
2. Be sure to set bit 3 of LPS to “0”.
3. When using the S16/P93 through S19/P90, and S20/P83 through S23/P80 pins to output
segment signals, do not connect the internal pull-up resistors to these pins by software.
The port set in the segment signal output mode by LPS is not floated even if the input mode
is set by the port mode register group C. It is therefore not necessary to specify connection
of the internal pull-up resistor by software.
If an input instruction is executed to a port set in the segment signal output mode, the contents
of the output latch are input.
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5.7.6 Display data memory
The display data memory is mapped in 1ECH-1F7H.
The display data memory is an area read by the LCD controller/driver, which performs DMA operation independ-
ently of CPU operation. The LCD controller controls the segment signals according to data in the display data memory.
The area not used for LCD display or port can be used for normal data memory.
The display data memory is manipulated in 1- or 4-bit units. It cannot be manipulated in 8-bit units.
Figure 5-102 shows the relationship between the display data memory bits and segment output.
Figure 5-101. Data Memory Map
Data memory
Memory bank
0 0 0 H
256 × 4
0
0 F F H
1 0 0 H
256 × 4
(236 × 4)
1
1 E C H
Display
data memory
(12 × 4)
(8 × 4)
1 F 7 H
1 F 8 H
1 F F H
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Figure 5-102. Relationship between Display Data Memory and Common Segments
b3
b2
b1
b0
S12
1ECH
1EDH
1EEH
1EFH
1F0H
S13
S14
S15
S16/P93
S17/P92
S18/P91
S19/P90
S20/P83
S21/P82
S22/P81
S23/P80
1F1H
1F2H
1F3H
1F4H
1F5H
1F6H
1F7H
COM3
COM2
COM1
COM0
Common signal
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5.7.7 Common signal and segment signal
The individual picture elements of the LCD panel light up when the potential difference between the corresponding
common signal and segment signal is greater than a predetermined value (LCD driving voltage VLCD). When it goes
low-order than the VLCD or is zero, they go out.
The LCD panel is degraded when a DC voltage is applied for the common signal and segment signal, therefore
it is driven by an AC voltage.
(1) Common signal
The common signal is a selection timing in a sequence shown in Table 5-14 in accordance with the time division
number which is set and repeats with that cycle. In the static mode, the same signal is output to the COM0-COM3.
When the time division number is 2, COM2 pin and COM3 pin must be open. When the time division number
is 3, the COM3 pin must be open.
Table 5-14. Common Signal
Common signal
Time
division number
COM0
COM1
COM2
Open
COM3
Static
Open
Open
2
3
4
(2) Segment signal
There are 12 segment signals corresponding to the 12 locations in the display data memory (1ECH-1F7H) of
the data memory. Each location’s bits 0, 1, 2, and 3 are automatically read out in synchronization with the
selection timings of COM0, COM1, COM2, and COM3, respectively. When the contents of each bit is 1, it is
converted to the selection voltage; and if they are 0, it is converted to the non-selection voltage and then output
via the segment pins (S12-S23).
As stated above, what combination of LCD panel’s front panel electrodes (corresponding to the segment signals)
and rear panel electrodes (corresponding to the common signals) forms a display pattern on the display data
memory must be checked and then the bit data which corresponds one-to-one to the pattern to be displayed must
be written.
Bits 1/2/3 in the display data memory in the static method, bits 2/3 in the division number 2 method, and bit 3
in the division number 3 are not accessed, therefore they can be used for purposes other than display.
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(3) Common and segment signal output waveforms
Tables 5-15 to 5-17 list voltages output to the common and segment signals. +VLCD/–VLCD on voltage is applied
only when both signals become selection voltages; otherwise, the off voltage is applied.
Table 5-15. LCD Drive Voltage (Static)
Segment signal Sn
Common signal COM0
Selection
VLC0/VSS
Non-selection
VSS/VLC0
VSS/VLC0
+VLCD/–VLCD
0 V/0 V
Table 5-16. LCD Drive Voltage (1/2 Bias method)
Segment signal Sn
Common signal COMm
Selection
VLC0/VSS
Non-selection
VSS/VLC0
Selection
VSS/VLC0
VLC1 = VLC2
+VLCD/–VLCD
0 V/0 V
1
1
VLCD/– VLCD
2
1
2
1
VLCD/+ VLCD
2
Non-selection
+
–
2
Table 5-17. LCD Drive Voltage (1/3 Bias method)
Segment signal Sn
Common signal COMm
Selection
VLC0/VSS
Non-selection
VLC2/VLC1
1
3
1
3
1
VLCD/– VLCD
3
1
VLCD/– VLCD
3
Selection
VSS/VLC0
VLC1/VLC2
+VLCD/–VLCD
+
+
1
1
VLCD/– VLCD
3
Non-selection
+
3
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Figures 5-103 to 5-105 show the common signal waveforms. Figure 5-106 shows the common and segment signal
electric potentials and phases.
Figure 5-103. Common Signal Waveform (Static)
VLC0
COM0
(Static)
VLCD
VSS
TF = T
T : One cycle of LCDCL
: Frame cycle
TF
Figure 5-104. Common Signal Waveform (1/2 bias method)
VLC0
COMm
VLC1, 2
VLCD
(division by 2)
VSS
TF = 2 × T
VLC0
VLC1, 2
COMm
VLCD
(division by 3)
VSS
TF = 3 × T
T : One cycle of LCDCL
: Frame cycle
TF
Figure 5-105. Common Signal Waveform (1/3 bias method)
V
V
LC0
LC1
V
LCD
V
V
LC2
SS
COMm
(division by 3)
TF = 3 × T
V
V
LC0
LC1
V
LCD
V
V
LC2
SS
COMm
(division by 4)
TF = 4 × T
T : One cycle of LCDCL
: Frame cycle
T
F
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Figure 5-106. Common and Segment Signal Electric Potentials and Phases
(a) 1/3 bias method
Selection Non-selection
(b) 1/2 bias method
Selection Non-selection
V
V
V
LC0
V
V
V
V
LC0
LC1
LC2
SS
V
LCD
V
V
LCD
LC1, 2
SS
Common signal
Segment signal
V
V
V
LC0
V
V
V
V
LC0
LC1
LC2
SS
LC1, 2
SS
V
LCD
LCD
T
T
T
T
T : One cycle of LCDCL
(c) Static display mode
Selection
Non-selection
VLC0
Common signal
Segment signal
VLCD
VSS
VLC0
VLCD
VSS
T
T
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5.7.8 Supply of LCD drive power VLC0, VLC1, and VLC2
In the µPD753208, a split resistor can be incorporated in the VLC0-VLC2 pins for the LCD drive power supply.
According to the bias method, the LCD drive power can be supplied without an external split resistor. The µPD753208
also includes the BIAS pin to deal with various LCD drive voltages. The BIAS and VLC0 pins are connected externally.
Table 5-18 lists proper LCD drive power supply values based on the static, 1/2, and 1/3 bias methods.
Table 5-18. LCD Drive Power Supply Values
Bias Method
No Bias
LCD
1/2
1/3
(Static Mode)
Drive Power
VLC0
VLC1
VLC2
VSS
VLCD
2/3VLCD
1/3VLCD
0 V
VLCD
VLCD
2/3VLCD
1/3VLCD
0 V
1/2VLCDNote
0 V
Note When 1/2 bias is used, the VLC1 and VLC2 pins must be
connected externally.
Remark When the BIAS and VLC0 pins are not connected, VLCD
= 3/5 VDD (internal split resistor must be specified by
using a mask option).
When the BIAS and VLC0 pins are connected, VLCD =
VDD.
Figure 5-107, (a) to (c) show LCD drive power supply examples according to Table 5-18.
Current flow through the split resistor can also be cut by clearing display control register bit 0 (LCDC0).
This LCD power on/off control is also useful to prevent DC voltage from being applied to LCD (if the system clock
subsystem is selected) when the LCD clock is stopped by execution of a STOP instruction, when the watch timer
operates using the system clock. That is, display control register bit 0 (LCDC0) is cleared and all LCD drive power
sources are placed in the same potential VSS immediately before the STOP instruction is executed, thereby
suppressing the potential difference between the LCD electrodes even if the LCD clock is stopped.
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Figure 5-107. LCD Drive Power Connection Examples (when split resistor is incorporated)
(a) 1/3 bias method and static display mode
(In example VDD = 5 V, VLCD = 3 V)
(b) 1/2 bias method
(In example VDD = 5 V, VLCD = 5 V)
µ
PD753208
µPD753208
V
DD
V
DD
LCDC0
LCDC0
BIAS pin
BIAS pin
2R
R
2R
R
V
V
V
V
LC0
LC1
V
V
V
V
LC0
LC1
V
LCD
V
LCD
R
R
LC2
SS
LC2
SS
R
R
V
LCD = 3/5 VDD
VLCD = VDD
(c) 1/3 bias method and static display mode
(In example VDD = 5 V, VLCD = 5 V)
µ
PD753208
VDD
LCDC0
BIAS pin
2R
R
V
V
V
V
LC0
LC1
VLCD
R
LC2
SS
R
VLCD = VDD
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Figure 5-108. LCD Drive Power Supply Connection Examples
(when split resistor is incorporated externally)
(a) Static display modeNote
(In example VDD = 5 V, VLCD = 5 V)
(b) Static display mode
(In example VDD = 5 V, VLCD = 3 V)
µ
PD753208
µ
PD753208
VDD
VDD
LCDC0
LCDC0
BIAS pin
BIAS pin
2R
V
V
V
V
LC0
V
V
V
V
LC0
3R
LC1
LC1
VLCD
VLCD
LC2
SS
LC2
SS
VLCD = VDD
VLCD = 3/5 VDD
(c) 1/2 bias method
(In example VDD = 5 V, VLCD = 2.5 V)
(d) 1/3 bias method
(In example VDD = 5 V, VLCD = 3 V)
µ
PD753208
µ
PD753208
VDD
VDD
LCDC0
LCDC0
BIAS pin
2R
BIAS pin
2R
V
V
V
V
LC0
LC1
V
V
V
V
LC0
LC1
R
R
R
V
LCD
V
LCD
LC2
SS
LC2
SS
R
R
V
LCD= 3/5 VDD
VLCD= 1/2 VDD
Note Set LCDC0 always to 1. (Including the case of standby mode.)
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5.7.9 Display mode
(1) Static display example
Figure 5-110 shows connection of a static 1-digit LCD panel having the display pattern shown in Figure 5-109,
the µPD753208 segment signals (S12-S19), and the common signal (COM0). In this example, “1” is displayed.
The contents of the display data memory (addresses 1ECH-1F3H) correspond to the display pattern.
In the example of Figure 5-110, it is necessary to output selection and no-selection voltages as shown in Table
5-19 to the S12-S19 pins at the COM0 common signal timing according to the display pattern shown in Figure
5-109.
Table 5-19. S12-S19 Pin Selection and Non-selection Voltage (Static Display Example)
Segment
S12
S13
S14
S15
S16
S17
S18
S19
Common
COM0
Non-selection
Selection
Selection
Non-selection Non-selection Non-selection Non-selection Non-selection
This shows that the bit 0 string of display data memory addresses 1ECH-1F3H corresponding to S12-S19 needs
to be set to 01100000.
Figure 5-111 shows the S14, S15, and COM0 LCD drive waveforms. This shows that alternating current square
wave of +VLCD/–VLCD that is LCD on level is generated when S14 becomes the selection voltage at the selection
timing of COM0.
Since the same waveform as COM0 is output to COM1 to COM3, the drive capability can be increased by
connecting COM0, COM1, COM2, and COM3.
Figure 5-109. Static Mode LCD Display Pattern and Electrode Connection
S15
S14
S17
S16
S18
COM0
S13
S12
S19
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Figure 5-110. Static LCD Panel Connection Example
DATA MEMORY ADDRESS
TIMING STROBE
1
F
7
1
F
3
1
F
0
1
E
C
H
…
2
0
1
0
F
0
E
1
D
1
H
H
H
0
0
0
BIT0
× × × × × × × × BIT1
× × × × × × × × BIT2
× × × × × × × × BIT3
µPD753208
Can be shortened
LCD PANEL
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Figure 5-111. Static LCD Drive Waveform Example
T
F
V
LC0
COM0
V
V
SS
LC0
S14
V
V
SS
LC0
S15
V
SS
+ VLCD
COM0 – S14
0
– VLCD
+ VLCD
COM0 – S15
0
– VLCD
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(2) Division by 2 display example
Figure 5-113 shows connection of the division by 2 mode 3-digit LCD panel having the display pattern shown
in Figure 5-112, the µPD753208 segment signals (S12-S23), and the common signals (COM0 and COM1). In
the example, “12.3” is displayed. The contents of the display data memory (addresses 1ECH-1F7H) correspond
to the display pattern.
Here, “3.” at the first digit position is taken as an example. It is necessary to output the selection and no-selection
voltages as shown in Table 5-20 to the S12-S15 pins at the timing of the COM0 and COM1 common signal
according to the display pattern shown in Figure 5-112.
Table 5-20. S12-S15 Pin Selection and Non-selection Voltage (Division by 2 Display Example)
Segment
S12
S13
S14
S15
Common
COM0
Selection
Selection
Selection
Non-selection
Selection
Non-selection
Selection
COM1
Non-selection
This shows that for example, the display data memory address 1EFH bits corresponding to S15 need to be set
to ××10.
Figure 5-114 shows an LCD drive waveform example among S15 and common signals. This shows an alternating
current square wave of +VLCD/–VLCD that is the LCD on level being generated when S15 is the selection voltage
at the COM1 selection timing.
Figure 5-112. Division by 2 Mode LCD Display Pattern and Electrode Connection
COM0
Sn + 1
Sn + 2
Sn + 3
Sn
COM1
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Figure 5-113. Division by 2 LCD Panel Connection Example
DATA MEMORY ADDRESS
TIMING STROBE
1
F
7
1
F
0
1
E
C
H
6
5
4
3
2
1
F
E
D
H
H
0
0
0
0
1
0
1
0
1
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
BIT0
BIT1
BIT2
BIT3
× × × × × × × × × × × ×
× × × × × × × × × × × ×
µPD753208
LCD PANEL
Remark ×: Any data can be stored at any time because of the division by 2 display.
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Figure 5-114. Division by 2 LCD Drive Waveform Example (1/2 bias method)
T
F
V
V
V
LC0
COM0
COM1
LC1, 2
SS
V
V
V
LC0
LC1, 2
SS
V
V
V
LC0
S15
LC1, 2
SS
+VLCD
+1/2 VLCD
0
COM0–S15
–1/2 VLCD
–VLCD
+VLCD
+1/2 VLCD
0
COM1–S15
–1/2 VLCD
–VLCD
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(3) Division by 3 display example
Figure 5-116 shows connection of a division by 3 mode 4-digit LCD panel having the display pattern shown in
Figure 5-115, the µPD753208 segment signals (S12-S23), and the common signals (COM0-COM2). In this
example, “1236.” is displayed. The contents of the display data memory (addresses 1ECH-1F7H) correspond
to the display pattern.
Here, “6.” at the first digit position is taken as an example. It is necessary to output the selection and no-selection
voltages as shown in Table 5-21 to the S12-S14 pins at the COM0-COM2 common signal timings according to
the display pattern shown in Figure 5-115.
Table 5-21. S12-S14 Pin Selection and Non-selection Voltage (Division by 3 Display Example)
Segment
S12
S13
S14
Common
COM0
Non-selection
Selection
Selection
Selection
Selection
Selection
Selection
—
COM1
COM2
Selection
This shows that the bits at display data memory address 1ECH corresponding to S12 need to be set to ×110.
Figure 5-117 (1/2 bias method) and 5-118 (1/3 bias method) show LCD drive waveforms among S12 and common
signals. These show an alternating current square wave of +VLCD/–VLCD that is LCD on level being generated
when S12 is the selection voltage at the COM1 selection timing and S12 is the selection voltage at the COM2
selection timing.
Figure 5-115. Division by 3 Mode LCD Display Pattern and Electrode Connection
S
n
+
1
COM0
Sn
+
2
Sn
COM1
COM2
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Figure 5-116. Division by 3 LCD Panel Connection Example
DATA MEMORY ADDRESS
TIMING STROBE
1
F
7
1
F
0
1
E
C
H
6
5
4
3
2
1
F
E
D
H
H
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
BIT0
BIT1
BIT2
0
1
1
×'
×'
×'
×'
× × × × × × × × × × × × BIT3
µPD753208
LCD PANEL
Remarks ×’: Any data can be stored because the LCD panel does not have a corresponding segment.
× : Any data can be stored at any time because of the division by 3 display.
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Figure 5-117. Division by 3 LCD Drive Waveform Example (1/2 bias method)
T
F
V
V
V
LC0
LC1, 2
SS
COM0
COM1
COM2
V
V
V
LC0
LC1, 2
SS
V
V
V
LC0
LC1, 2
SS
V
V
V
LC0
LC1, 2
SS
S12
+VLCD
+1/2 VLCD
0
COM0 – S12
–1/2 VLCD
–VLCD
+VLCD
+1/2 VLCD
0
COM1 – S12
–1/2 VLCD
–VLCD
+VLCD
+1/2 VLCD
0
COM2 – S12
–1/2 VLCD
–VLCD
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
Figure 5-118. Division by 3 LCD Drive Waveform Example (1/3 bias method)
T
F
VLC0
VLC1
VLC2
VSS
COM0
V
V
V
V
LC0
LC1
LC2
SS
COM1
COM2
S12
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
+VLCD
+1/3 VLCD
0
COM0 – S12
–1/3 VLCD
–VLCD
+VLCD
+1/3 VLCD
0
–1/3 VLCD
COM1 – S12
–VLCD
+VLCD
+1/3 VLCD
0
–1/3 VLCD
COM2 – S12
–VLCD
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
(4) Division by 4 Display Example
Figure 5-120 shows connection of the division by 4 mode 6-digit LCD panel having the display pattern shown
in Figure 5-119, the µPD753208 segment signals (S12-S23), and the common signals (COM0-COM3). In this
example, “12345.6” is displayed. The contents of the display data memory (addresses 1ECH-1F7H) correspond
to the display pattern.
Here, “5.” at the second digit position is taken as an example. It is necessary to output the selection and no-
selection voltages as shown in Table 5-22 to the S14 and S15 pins at the COM0-COM3 common signal timing
according to the display pattern shown in Figure 5-119.
Table 5-22. S14, S15 Selection and Non-selection Voltage (Division by 4 Display Example)
Segment
S14
S15
Common
COM0
COM1
COM2
COM3
Selection
Non-selection
Selection
Selection
Selection
Non-selection
Selection
Selection
This shows that the bits at display data memory address 1EEH corresponding to S14 need to be set to 1101.
Figure 5-121 shows LCD drive waveforms for S14, COM0, and COM1 signals (Waveforms for COM2 and COM3
are omitted because of space limitation). This shows an alternating current square wave of +VLCD/–VLCD that is
the LCD on level being generated when S14 becomes the selection voltage at the COM0 selection timing.
Figure 5-119. Division by 4 Mode LCD Display Pattern and Electrode Connection
S
n
COM0
COM2
COM1
COM3
S
n + 1
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Figure 5-120. Division by 4 LCD Panel Connection Example
DATA MEMORY ADDRESS
TIMING STROBE
1
F
7
1
F
0
1
E
C
H
6
5
4
3
2
1
F
E
D
H
H
0
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
1
1
1
0
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
0
BIT0
BIT1
BIT2
BIT3
1
0
0
µPD753208
LCD PANEL
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Figure 5-121. Division by 4 LCD Drive Waveform Example (1/3 bias method)
T
F
V
V
V
V
LC0
LC1
LC2
SS
COM0
COM1
COM2
COM3
S14
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
+VLCD
+1/3 VLCD
0
COM0 – S14
–1/3 VLCD
–VLCD
+VLCD
+1/3 VLCD
0
COM1 – S14
–1/3 VLCD
–VLCD
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
5.8 Bit Sequential Buffer ··· 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily
performed by changing the address specification and bit specification in sequence, therefore it is useful when
processing a long data bit-wise.
The data memory is composed of 16 bits and the pmem.@L addressing of a bit manipulation instruction is possible.
The bit can be specified indirectly by the L register. In this case, processing can be done by moving the specified
bit in sequence by incrementing and decrementing the L register in the program loop.
Figure 5-122. Bit Sequential Buffer Format
Address
Bit
FC3H
FC2H
FC1H
FC0H
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Symbol
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H L = 7H
L = 3H
L = 0H
L = 4H
DECS L
INCS L
Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register.
2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.
Data can be operated by direct addressing. It can be used for continuous input and output of 1-bit data together
with the 1-bit/4-bit/8-bit direct addressing and pmem.@L addressing. For 8-bit manipulation, the BSB0 and BSB2 must
be specified to manipulate the high-order 8-bits and low-order 8 bits.
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Example The 16-bit data of BUFF 1/2 is output serially starting with the bit 0 of port 3.
CLR1 MBE
MOV
MOV
XA, BUFF1
BSB0, XA
XA, BUFF2
BSB2, XA
L, #0
;
;
;
Sets BSB0,1.
MOV
MOV
Sets BSB2,3.
MOV
LOOP0 : SKT
BR
BSB0, @L
LOOP1
Tests the specification bit of BSB.
NOP
;
;
Dummy (timing adjustment)
Sets the bit 0 of port 3.
SET1 PORT3.0
BR LOOP2
LOOP1 : CLR1 PORT3.0
;
;
Clears the bit 0 of port 3.
Dummy (timing adjustment)
NOP
NOP
LOOP2 : INCS
L
;
L ← L+1
BR
LOOP0
RET
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[MEMO]
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CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
The µPD753208 has seven vectored interrupt sources and two test inputs that can be used for various applications.
The interrupt control circuit of the µPD753208 has unique features and can process interrupts at extremely high
speed.
6.1 Configuration of Interrupt Control Circuit
The interrupt control circuit is configured as shown in Figure 6-1, and each hardware unit is mapped to the data
memory space.
(1) Interrupt function
(a) Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt
enable flag (IE×××) and interrupt master enable flag (IME).
(b) Can set any interrupt start address.
(c) Nestings wherein the order of priority can be specified by the interrupt priority select register (IPS).
(d) Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.
(e) Release the standby mode. A release interrupt can be selected by the interrupt enable flag.
(2) Test function
(a) Test request flag (IRQ×××) generation can be checked by software.
(b) Release the standby mode. The test source to be released can be selected by the test enable flag.
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Figure 6-1. Interrupt Control Circuit Block Diagram
Internal bus
2
4
IME IPS
IST1
IST0
Interruput enable flag (IE×××
)
IM2
IM0
Decoder
IRQBT
IRQ4
INTBT
Both edge
detection
circuit
VRQn
INT4/P00
INT0/P10
Edge
Selec-
tor
Note
IRQ0
detection
circuit
Vector table
address
generator
Priority control
circuit
INTCSI
IRQCSI
IRQT0
IRQT1
IRQT2
IRQW
IRQ2
INTT0
INTT1
INTT2
INTW
Selec-
tor
Standby release
signal
KR0/P60
KR3/P63
Falling
detection
circuit
IM2
Note Noise eliminator (Standby release is disable when noise eliminator is selected.)
CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.2 Types of Interrupt Sources and Vector Tables
The µPD753208 has the following seven types of interrupt sources, and nestings by software control are allowed.
Table 6-1. Types of Interrupt Sources
Internal/
External
Interrupt
Priority Note
Vectored Interrupt Request Signal
(Vector Table Address)
Interrupt Source
INTBT
INT4
(Reference interval timer signal sent from the basic
interval timer/watchdog timer)
Internal
1
VRQ1 (0002H)
(Detection by both rising edge and falling edge
is valid.)
External
INT0
(Selects rising edge or falling edge.)
External
Internal
Internal
2
3
4
VRQ2 (0004H)
VRQ4 (0008H)
VRQ5 (000AH)
INTCSI (Serial data transfer end signal)
INTT0
INTT1
INTT2
(Match signal between the count register and
modulo register of the timer/event counter 0)
(Match signal between the count register and
modulo register of the timer counter 1)
Internal
Internal
5
VRQ6 (000CH)
(Match signal between the count register and
modulo register of the timer counter 2)
Note The priority of interrupts is applied when several interrupt requests are generated simultaneously.
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CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
Figure 6-2. Interrupt Vector Table
Address
0002H
0004H
0006H
0008H
000AH
000CH
MBE
MBE
RBE
RBE
INTBT/INT4 start address (high-order 6 bits)
INTBT/INT4 start address (low-order 8 bits)
INT0 start address (high-order 6 bits)
INT0 start address (low-order 8 bits)
MBE
MBE
MBE
RBE
RBE
RBE
INTCSI start address (high-order 6 bits)
INTCSI start address (low-order 8 bits)
INTT0 start address (high-order 6 bits)
INTT0 start address (low-order 8 bits)
INTT1, INTT2 start address (high-order 6 bits)
INTT1, INTT2 start address (low-order 8 bits)
The priority column in Table 6-1 indicates the priority according to which interrupts are executed if two or more
interrupts occur at the same time, or if two or more interrupt requests are kept pending.
To the vector table, write the start address of interrupt processing, and the set values of MBE and RBE during
interrupt processing. The vector table is set by using an assembler pseudoinstruction (VENTn: n = 1-6).
Example Setting of vector table of INTBT/INT4
VENT1
MBE=0, RBE=0, GOTOBT
↑
↑
↑
↑
<1>
<2>
<3>
<4>
<1> Vector table of address 0002
<2> Setting of MBE in interrupt processing routine
<3> Setting of RBE in interrupt processing routine
<4> Symbol indicating start address of interrupt processing routine
Caution The contents (MBE, RBE, and start address) written in the operand of VENTn (n = 1-6) instruction
is stored to the vector table of address 2n.
Example Setting of vector tables of INTBT/INT4 and INTT0
VENT1
VENT5
MBE=0, RBE=0, GOTOBT; INTBT/INT4 start address
MBE=0, RBE=1, GOTOT0; INTT0 start address
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6.3 Hardware Controlling Interrupt Functions
(1) Interrupt request flag and interrupt enable flag
The µPD753108 has the following seven interrupt request flags (IRQ×××) corresponding to the respective
interrupt sources:
INT0 interrupt request flag (IRQ0)
Serial interface interrupt request flag (IRQCSI)
Timer/event counter 0 interrupt request flag (IRQT0)
INT4 interrupt request flag (IRQ4)
Timer counter 1 interrupt request flag (IRQT1)
Timer counter 2 interrupt request flag (IRQT2)
BT interrupt request flag (IRQBT)
Each interrupt request flag is set to “1” when the corresponding interrupt request is generated, and is automatically
cleared to “0” when the interrupt processing is executed. However, because IRQBT and IRQ4, and IRQT1 and
IRQT2 share the vector address, these flags are cleared differently from the other flags (refer to 6.6 Vector
Address Share Interrupt processing).
The µPD753108 also has seven interrupt enable flags (IE×××) corresponding to the respective interrupt request
flags.
INT0 interrupt enable flag (IE0)
Serial interface interrupt enable flag (IECSI)
Timer/event counter 0 interrupt enable flag (IET0)
INT4 interrupt enable flag (IE4)
Timer counter 1 interrupt enable flag (IET1)
Timer counter 2 interrupt enable flag (IET2)
BT interrupt enable flag (IEBT)
When the interrupt enable flag is “1”, the interrupt is enabled; and when it is “0”, the interrupt is disabled.
When the interrupt request flag is set and interrupt enable flag enables the interrupt, a vectored interrupt request
(VRQn) is generated. It is also used to release the standby mode.
The interrupt request flag and interrupt enable flag are operated by a bit manipulation instruction and 4-bit memory
manipulation instruction. When the bit instruction is used, they can be directly manipulated at any time regardless
of MBE setting. The interrupt enable flag is manipulated by an EI IE××× instruction and DI IE××× instruction. A
SKTCLR instruction is normally used to test the interrupt request flag.
Example EI
IE0
; Enables INT0.
DI
IET1
; Disables INTT1.
SKTCLR IRQCSI ; Skips and clears when IRQCSI is 1.
When the interrupt request flag is set by an instruction, a vectored interrupt is executed as if an interrupt were
generated.
The interrupt request flag and interrupt enable flag are cleared to “0” when a RESET signal is generated and
all the interrupts are inhibited.
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Table 6-2. Set Signals for Interrupt Request Flags
Interrupt
Interrupt
Set Signal for Interrupt Request Flag
Request Flag
Enable Flag
IRQBT
IRQ4
Set by the reference interval signal by the basic interval timer/watchdog timer.
Set by the detection of both rising edge and falling edge of an INT4/P00 pin.
IEBT
IE4
IRQ0
Reset by the edge detection of an INT0/P10 pin input signal. The detection edge is
selected by the INT0 edge detection mode register (IM0).
IE0
IRQCSI
IRQT0
IRQT1
IRQT2
Set by a serial data transfer end signal of the serial interface.
Set by a match signal sent from the timer/event counter 0.
Set by a match signal sent from the timer counter 1.
Set by a match signal sent from the timer counter 2.
IECSI
IET0
IET1
IET2
(2) Interrupt priority selection register (IPS)
The interrupt priority selection register selects the high-order-priority interrupts in a system wherein nestings are
allowed. Its low-order 3 bits are used for specification.
Bit 3 is the interrupt master enable flag (IME) which specifies whether all the interrupts are prohibited or not.
The IPS is set by a 4-bit memory manipulation instruction. Bit 3 is set and reset by an EI/DI instruction.
To change the contents of the low-order 3 bits of IPS, the interrupt must be disabled (IME = 0).
Example DI
CLR1
; Disables interrupt
MBE
A, #1010B
IPS, A ; Gives high-order priority to INT0 and enables interrupt
MOV
MOV
All the bits are cleared to “0” when a RESET signal is generated.
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Figure 6-3. Interrupt Priority Selection Register
Address
FB2H
3
2
1
0
Symbol
IPS
IPS3 IPS2 IPS1 IPS0
Selection of higher-order-priority interrupts
No interrupts are handled as higher-order-priority
0
0
0
0
0
1
interrupts.
The above vectored
interrupts are
VRQ1
(INTBT/INT4)
VRQ2
regarded as
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
higher-order priority
interrupts.
(INT0)
Setting prohibited
VRQ4
(INTCSI)
VRQ5
(INTT0)
VRQ6
(INTT1, INTT2)
Prohibited
Interrupt master enable flag (IME)
Disables all the interrupts and no vectored interrupt is
started.
0
Controls interrupt enable/disable by the corresponding
interrupt enable flag.
1
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(3) Hardware of INT0, and INT4
(a) Figure 6-4(a) shows the configuration of the INT0. An external interrupt is input to select the detection
edge, that is, rising edge or falling edge.
The INT0 has a noise eliminating circuit by means of the sampling clock. (Refer to Figure 6-5. Noise
Detection Circuit Input/Output Timing.) The noise eliminating circuit removes the pulses which are
narrower than the two cycles of the sampling clock Note. However, a pulse which is wider than the one cycle
of the sampling clock may be accepted in some cases as an interrupting signal depending on a sampling
timing. The pulses which are wider than the two cycles of sampling clock are accepted all the time as
interrupting signals. (Refer to Figure 6-5 <2>(a).)
The INT0 has the two sampling clocks: F and fX/64, either of which can be selected. One of them is selected
by the bit 3 (IM03) of the INT0 edge detection mode register (IM0). (Refer to Figure 6-6.)
The detection edge is selected by the bits 0/1 (IM00/IM01) of the INT0 edge detection mode register (IM0).
Figure 6-6(a) shows the format of the IM0. It is set by a 4-bit manipulation instruction. All the bits are cleared
to “0” by a RESET signal generated and the rising edge specification is adopted.
Note 2tCY when the sampling clock is Φ.
128/fX when the sampling clock is fX/64.
Cautions 1. Pulses are input to the INT0/P10 pin via a noise eliminating circuit if it is used as
a port, therefore pulses longer than the two cycles of sampling clock must be
input.
2. When the noise eliminating circuit is selected, that is IM02 is set to 0, the INT0
performs sampling by a clock, therefore it does not operate in the standby mode.
(The noise eliminating circuit does not operate when the CPU clock Φ is not
supplied.) Consequently, if the standby mode is to be released by the INT0, the
noise eliminating circuit must not be selected, that is the IM02 must be set to 1.
(b) Figure 6-4(b) shows the configuration of the INT4. An external interrupt is input so that both the rising edge
and falling edge can be detected.
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Figure 6-4. Configurations of INT0, and INT4
(a) INT0 hardware
INT0
IRQ0
set signal
Edge detection
circuit
Selector
Noise eliminating
circuitNote
INT0/P10
IM02
IM00, IM01
IM03
Selector
Detection edge specification
Sampling clock selection
IM0
4
Φ
f
x/64
Input buffer
Internal bus
Note The HALT mode cannot be cleared by INT0 even if fX/64 is selected.
(b) INT4 hardware
INT4
IRQ4
set signal
Both edge
detection circuit
INT4/P00
Input buffer
Internal bus
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Figure 6-5. Noise Detection Circuit Input/Output Timing
tSMP
tSMP
tSMP
tSMP
tSMP
<1> 1 sampling cycle (tSMP) or less
INT0
L
L
Shaping output
“L”
Detected as noise
H
H
<2> 1-2 times
L
L
L
L
L
INT0
(a)
Shaping output
H
L
INT0
(b)
Detected as noise
H
Shaping output
“L”
<3> 2 times or more
INT0
H
L
Shaping output
Remark tSMP = tCY or 64/fX
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Figure 6-6. INT0 Edge Detection Mode Register (IM0) Format
3
2
1
0
Address
Symbol
IM0
FB4H IM03 IM02 IM01 IM00
IM01
IM00
Detection edge specification
0
0
1
1
0
1
0
1
Rising edge specification
Falling edge specification
Rising edge/falling edge specification
Ignored (The interrupt request flag is not set).
IM02
Noise eliminator select bit
Sampling
Enabled
Disabled
Standby release
Impossible
Possible
0
1
Selects the noise eliminating circuit.
Does not select the noise eliminating circuit.
IM03
Sampling clock
0
1
Φ (0.67 µs, 1.33 µs, 2.67µs, 10.7µs: 6.00 MHz operation)
/64 (10.7 µs : 6.00 MHz operation)
f
x
Caution When the edge detection mode register is changed, the interrupt request flag may be set
in some case, therefore the interrupts must be prohibited beforehand to select the mode
register and the interrupt request flag must be cleared by a CLR1 instruction, and then the
interrupts must be enabled. When fX/64 is selected as the sampling clock by changing the
IM0, the interrupt request flag must be cleared when 16 machine cycles have elapsed since
the mode register was changed.
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(4) Interrupt status flag
The interrupt status flags (IST0 and IST1) indicate the status of the processing currently executed by the CPU
and are included in PSW.
The interrupt priority control circuit controls nesting of interrupts according to the contents of these flags as shown
in Table 6-3.
IST0 and IST1 can be changed by using a 4-bit or bit manipulation instruction, and interrupts can be nested with
the status under execution changed. IST0 and IST1 can be manipulated in 1-bit units regardless of the setting
of MBE.
Before manipulating IST0 and IST1, be sure to execute the DI instruction to disable the interrupt. Execute the
EI instruction after manipulating the flags to enable the interrupt.
IST1 and IST0 are saved to the stack memory along with the other flags of PSW when an interrupt is
acknowledged, and their statuses are automatically changed high-order by one. When the RETI instruction is
executed, the original values of IST1 and IST0 are restored.
The contents of these flags are cleared to “0” when the RESET signal is asserted.
Table 6-3. IST1 and IST0 and Interrupt Processing Status
Status of
After interrupt
acknowledged
Interrupt request that can be
acknowledged
processing under
execution
IST1
IST0
Processing by CPU
IST1
0
IST0
1
0
0
1
1
0
1
0
1
Status 0
Executes normal program
All interrupts can be acknowl-
edged
Status 1
Processes interrupt with low
or high priority
Interrupt with high priority can
be acknowledged
1
–
0
–
Status 2
Processes interrupt with
high priority
Acknowledging all interrupts is
disabled
Setting prohibited
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6.4 Interrupt Sequence
When an interrupt is generated, it is executed in the following procedure.
Figure 6-7. Interrupt Processing Sequence
Interrupt (INT×××) is generated.
IRQ××× is set.
NO
Held until IE×××
IE××× is set?
is set.
YES
Corresponding VRQn is generated.
NO
NO
Held until IME is
set.
IME = 1
YES
Held until the current
operation ends.
VRQn is
higher-order priority
interrupt?
YES
Note 1
Note 1
NO
NO
IST1, 0 = 00 or 01
IST1, 0 = 00
YES
YES
Select one of the several VRQn's generated
simultaneously according to the order of the
interrupts in Table 5-1.
Selected
VRQn
Remaining
VRQn
Save the contents of the PC and PSW in the stack memory and set the
data Note 2 in the vector table corresponding to the started VRQn in the
PC, RBE, and MBE.
Change the contents of IST0,1 to 01 if 00,
or to 10 if 01.
Reset the accepted IRQ×××
.
Refer to 6.6, if the interrupt source shares the
vector address.
Jump to the interrupt service program execution starting address.
Notes 1. IST1, 0: interrupt status flag (bits 2, 3 of PSW; refer to Table 6-3)
2. Each vector table stores the interrupt processing program starting address and values set for the MBE
and RBE at the time the interrupt processing starts.
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6.5 Nesting processing Control
The µPD753208 accepts nestings in the following two methods.
(1) Nestings wherein high-order priority interrupts are specified
This is a standard nestings method of the µPD753208, wherein one of the interrupt sources is selected to enable
the nestings (double interrupts) of the interrupt.
That is, the high-order priority interrupts specified by the interrupt priority select register (IPS) can be accepted
when the status of the current operation is 0 and 1, and the other low-order priority interrupts can be serviced
when the status is 0 (Refer to Figure 6-8 and Table 6-3).
Therefore, if this method is used when you wish to nest only one interrupt, operations such as enabling and
disabling interrupts while the interrupt is processed need not to be performed, and the nesting level can be kept
to 2.
Figure 6-8. Nestings by High-Order Priority Interrupts
Lower-order priority or
higher-order priority
interrupt service (status 1)
Higher-order priority
interrupt service
(status 2)
Normal processing
(status 0)
Interrupt is disabled.
IPS is set.
Interrupt is enabled.
Higher-order
priority interrupt
is generated.
Lower-order priority or
higher-order priority
interrupt is generated.
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(2) Nestings changing the interrupt status flag
If the interrupt status flag is changed by the program, nestings can be accepted. That is, if IST1 and IST0 are
changed to “0, 0” (status 0), nestings can be serviced.
This method is used when nestings (two or more interrupts) are to be accepted.
The IST1 and IST0 must be changed beforehand in a status in which the interrupts are prohibited by a DI
instruction.
Figure 6-9. Nestings by Changing Interrupt Status Flag
Normal processing
(status 0)
Single interrupt
Double interrupts
Interrupts are disabled.
IPS is set.
Status 1
Interrupts
Interrupts are enabled.
are disabled.
IST is changed.
Lower-order priority interrupts
or higher-order priority interrupts
are generated.
Interrupts are enabled.
Status 0
Status 1
Lower-order priority
interrups or higher-
order priority
interrupts are
generated.
Status 0
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6.6 Vector Address Share Interrupt Processing
Since INTBT, INT4 and INTT1, INTT2 interrupt sources share the vector table addresses, interrupt source
selection is made as described below:
(1) To use one interrupt only
Set the interrupt enable flag to 1 for the required one of the two interrupt sources sharing the vector table
addresses, and clear the interrupt enable flag of the other interrupt source. In this case, an interrupt request
is generated from the interrupt source corresponding to the interrupt enable flag that is set to 1 (IE××× = 1). When
the interrupt request is acknowledged, the interrupt request flag is cleared.
(2) To use both interrupts
Set both the interrupt enable flags of the two interrupt sources to 1. In this case, an interrupt request is made
by ORing the interrupt request flags of the two interrupt sources.
Even if an interrupt request is acknowledged when either or both of the interrupt request flags are set to 1, the
interrupt request flags are not reset.
Therefore, the interrupt processing routine must decide which interrupt source the interrupt is generated from.
This is accomplished by executing the DI instruction at the SKTCLR instruction to check the interrupt request
flags.
If both the request flags are set when this request flag is tested or cleared, the interrupt request remains even
if one of the request flags is cleared. If this interrupt is selected as having the high-order priority, nesting
processing is started by the remaining interrupt request.
Consequently, the interrupt request not tested is processed first. If the selected interrupt has the low-order priority,
the remaining interrupt is kept pending and therefore, the interrupt request tested is processed first. Therefore,
an interrupt sharing a vector address with another interrupt is identified differently, depending whether it has the
high-order priority, as shown in Table 6-4.
Table 6-4. Identifying Interrupt Sharing Vector Table Address
With high-order priority Interrupt is disabled and interrupt request flag of interrupt
that takes precedence is tested
With low-order priority Interrupt request flag of interrupt that takes precedence is
tested
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Examples 1. To use both INTBT and INT4 as having the high-order priority and give priority to INT4
DI
SKTCLR
BR
IRQ4
;
IRQ4 = 1 ?
VSUBBT
.
.
.
.
Processing routine
of INT4
EI
RETI
.
.
.
VSUBBT: CLR1
IRQBT
.
.
.
.
.
.
.
.
.
.
Processing routine
of INTBT
EI
RETI
2. To use both INTBT and INT4 as having the low-order priority and give priority to INT4
SKTCLR
BR
IRQ4
;
IRQ4 = 1 ?
VSUBBT
.
.
.
.
.
.
.
.
.
.
Processing routine
of INT4
RETI
.
.
.
VSUBBT: CLR1
IRQBT
.
.
.
.
.
.
.
.
.
Processing routine
of INTBT
RETI
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6.7 Machine Cycles until Interrupt Processing
The number of machine cycles required since an interrupt request flag (IRQ×××) has been set until the interrupt
routine is executed is as follows:
(1) If IRQ××× is set while interrupt control instruction is executed
If IRQ××× is set while an interrupt control instruction is executed, the next one instruction is executed. Then three
machine cycles of interrupt processing is performed and the interrupt routine is executed.
Interrupt control
instruction
A
B
C
D
A: Sets IRQ×××
B: Executes next one instruction (1 to 3 machine cycles; differs depending on instruction)
C: Interrupt processing (3 machine cycles)
D: Executes interrupt routine
Remarks 1. An interrupt control instruction manipulates the hardware units related to interrupt (address
FB×H of the data memory). The DI and EI instructions are interrupt control instructions.
2. The three machine cycles of interrupt processing are the time required to manipulate the stack
which is manipulated when an interrupt is acknowledged.
Cautions 1. If two or more interrupt control instructions are successively executed, the one instruc-
tion following the interrupt control instruction executed last is executed, three machine
cycles of interrupt processing are performed, and finally the interrupt routine is executed.
2. If the DI instruction is executed when or after IRQ××× is set (A in the above figure), the
interrupt request corresponding to IRQ××× that has been set is kept pending until the EI
instruction is executed next time.
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(2) If IRQ××× is set while instruction other than (1) is executed
(a) If IRQ××× is set at the last machine cycle of the instruction under execution
In this case, the one instruction following the instruction under execution is executed, three machine cycles
of interrupt processing are performed, and finally the interrupt routine is executed.
Instruction other than
interrupt control instruction
A
B
C
D
A: Sets IRQ×××
B: Executes next one instruction (1 to 3 machine cycles; differs depending on instruction)
C: Interrupt processing (3 machine cycles)
D: Executes interrupt routine
Caution If the next instruction is an interrupt control instruction, the one instruction following
the interrupt control instruction executed last is executed, three machine cycles of
interrupt processing are performed, and finally the interrupt routine is executed. If the
DI instruction is executed after IRQn has been set, the interrupt request corresponding
to the set IRQn is kept pending.
(b) If IRQ××× is set before the last machine cycle of the instruction under execution
In this case, three machine cycles of processing are performed after execution of the current instruction, and
then the interrupt routine is executed.
Instruction other than
interrupt control instruction
A
C
D
A: Sets IRQ×××
C: Interrupt processing (3 machine cycles)
D: Executes interrupt routine
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6.8 Effective Usage of Interrupt
Use the interrupt function effectively as follows:
(1) Set MBE to 0 in interrupt processing routine.
If the memory used in the interrupt routine is allocated to addresses 00H through 7FH, and MBE is cleared to
0 by the interrupt vector table, you can program without having to consider the memory bank.
If it is necessary to use memory bank 1, save the memory bank select register by using the PUSH BS instruction
and then select memory bank 1.
(2) Use different register banks for the normal routine and interrupt routine.
The normal routine uses register banks 2 and 3 with RBE = 1 and RBS = 2. If the interrupt routine is for one
nested interrupt, use register bank 0 with RBE = 0, so that you do not have to save or restore the registers. When
two or more interrupts are nested, set RBE to 1, save the register bank by using the PUSH BS instruction, and
set RBS to 1 to select register bank 1.
(3) Use the software interrupt for debugging.
Even if an interrupt request flag is set by an instruction, the same operation as when an interrupt occurs is
performed. For debugging of an irregular interrupt or debugging when two or more interrupts occur at the same
time, the efficiency can be enhanced by setting the interrupt flag by an instruction.
6.9 Application of Interrupt
To use the interrupt function, first set as follows by the main routine:
(a) Set the interrupt enable flag of the interrupt used (by using the EI IE××× instruction).
(b) To use INT0, select the active edge (set IM0).
(c) To use nesting (of an interrupt with the high-order priority), set IPS (IME can be set at the same time).
(d) Set the interrupt master enable flag (by using the EI instruction).
In the interrupt routine, MBE and RBE are set by the vector table. However, when the interrupt specified as having
the high-order priority is processed, the register bank must be saved and set.
To return from the interrupt routine, use the RETI instruction.
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(1) Enabling or disabling interrupt
<Main routine>
<1>
Reset
Disables interrupts
<2>
EI IE0
EI IET1
<3> EI
Enables INT0 and INTT1
Enables INTT1
<4>
DI IE0
<5> DI
Disables interrupts
<1> All the interrupts are disabled by the RESET signal.
<2> An interrupt enable flag is set by the EI IE××× instruction.
At this stage, the interrupts are still disabled.
<3> The interrupt master enable flag is set by the EI instruction.
INT0 and INTT1 are enabled at this time.
<4> The interrupt enable flag is cleared by the DI IE××× instruction, and INT0 is disabled.
<5> All the interrupts are disabled by the DI instruction.
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(2) Example of using INTBT, INT0 (falling edge active) INTT0. No nesting (all interrupts have low-order
priority)
<Main routine>
; RBE = 1, MBE = 0
Reset
<1> SEL RB2
<2> MOV A, #1
MOV IM0, A
CLR1 IRQ0
<3> EI
EI
IEBT
IE0
IET0
Status 0
<INT0 processing routine>
; RBE = 0
EI
EI
<4> INT0
Status 1
Status 0
<5> RETI
<1> All the interrupts are disabled by the RESET signal and status 0 is set.
RBE = 1 is specified by the reset vector table. The SEL SB2 instruction uses register banks 2 and 3.
<2> INT0 is specified to be active at the falling edge.
<3> The interrupt is enabled by the EI, EI IE××× instruction.
<4> The INT0 interrupt routine is started at the falling edge of INT0. The status is changed to 1, and all the
interrupts are disabled.
RBE = 0, and register banks 0 and 1 are used.
<5> Execution returns from the interrupt routine when the RETI instruction is executed. The status is returned
to 0 and the interrupt is enabled.
Remark If all the interrupts are used as having the low-order priority as shown in this example, saving
or restoring the register bank is not necessary if RBE = 1 and RBS = 2 for the main routine
and register banks 2 and 3 are used, and RBE = 0 for the interrupt routine and register banks
0 and 1 are used.
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(3) Nesting of interrupts with high-order priority (INTBT has high-order priority and INTT0 and INTCSI have
low-order priority)
Reset
; RBE = 1, MBE = 0
SEL RB2
EI
EI
EI
IEBT
IET0
IECSI
<1> MOV A, #9
MOV IPS, A
Status 0
<INTT0 processing routine>
; RBE = 0
<INTBT processing routine>
; RBE = 1
Status 1
<4> SEL RB1
<2> INTT0
Status 2
<3> INTBT
<5> SEL RB2
RETI
Status 1
Status 0
RETI
<1> INTBT is specified as having the high-order priority by setting of IPS, and the interrupt is enabled at the
same time.
<2> INTT0 processing routine is started when INTT0 with the low-order priority occurs. Status 1 is set and the
other interrupts with the low-order priority are disabled. RBE = 0 to select register bank 0.
<3> INTBT with the high-order priority occurs. The interrupts are nested. The status is changed to 0 and all
the interrupts are disabled.
<4> RBE = 1 and RBS = 1 to select register bank 1 (only the registers used may be saved by the PUSH
instruction).
<5> RBS is returned to 2, and execution returns to the main routine. The status is returned to 1.
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(4) Executing pending interrupt – interrupt input while interrupts are disabled –
<Main routine>
Reset
EI IE0
<INT0 processing routine>
<1> INT0
<2> EI
<3> INTCSI
RETI
<INTCSI processing routine>
<4> EI IECSI
RETI
<1> The request flag is kept pending even if INT0 is set while the interrupts are disabled.
<2> INT0 processing routine is started when the interrupts are enabled by the EI instruction.
<3> Same as <1>.
<4> INTCSI processing routine is started when the pending INTCSI is enabled.
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(5) Executing pending interrupt – two interrupts with low-order priority occur simultaneously –
<Main routine>
Reset
EI IET0
EI IE0
EI
<INT0 processing routine>
INT0
<1>
INTT0
<2> RETI
<INTT0 processing routine>
RETI
<1> If INT0 and INTT0 with the low-order priority occur at the same time (while the same instruction is executed),
INT0 with the high-order priority is executed first (INTT0 is kept pending).
<2> When the INT0 processing routine is terminated by the RETI instruction, the pending INTT0 processing
routine is started.
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CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
(6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has high-order priority
and INTT0 and INTCSI have low-order priority) –
<Main routine>
Reset
EI
EI
EI
IEBT
IET0
IECSI
MOV A, #9
MOV IPS, A
<INTBT processing routine>
PUSH rp
<2> INTCSI
POP rp
<3> RETI
INTT0
INTBT
<1>
<INTCSI processing routine>
<4> RETI
<INTT0 processing routine>
RETI
<1> If INTBT with the high-order priority and INTT0 with the low-order priority occur at the same time, the
processing of the interrupt with the high-order priority is started (if there is no possibility that an interrupt
with the high-order priority occurs while another interrupt with the high-order priority is processed, DI IE××
is not necessary).
<2> If an interrupt with the low-order priority occurs while the interrupt with the high-order priority is executed,
the interrupt with the low-order priority is kept pending.
<3> When the interrupt with the high-order priority has been processed, INTCSI with the high-order priority of
the pending interrupts is executed.
<4> When the processing of INTCSI has been completed, the pending INTT0 is processed.
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(7) Enabling two nesting of interrupts – INTT0 and INT0 are nested doubly and INTCSI and INT4 are nested
singly –
<Main routine>
Reset
EI IET0
EI IE0
EI IECSI
Status 0
<INTCSI processing routine>
EI IE4
EI
<2> DI
CLR1 IST0
Status 1
DI
DI
EI
IECSI
IE4
<1> INTCSI
Status 0
<INTT0 processing routine>
Status 0
<3> INTT0
Status 1
<4> RETI
Status 0
<5> EI
EI
IECSI
IE4
RETI
<1> When INTCSI that does not enable nesting occurs, the INTCSI processing routine is started. The status
is 1.
<2> The status is changed to 0 by clearing IST0. INTCSI and INT4 that do not enable nesting are disabled.
<3> When INTT0 that enables nesting occurs, nesting is executed. The status is changed to 1, and all the
interrupts are disabled.
<4> The status is returned to 1 when INTT0 processing is completed.
<5> The disabled INTCSI and INT4 are enabled, and execution returns to the main routine.
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CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.10 Test Function
6.10.1 Types of test sources
The µPD753208 has two types of test sources. Of these, INT2 is provided with two types of edge-detection testable
inputs.
Table 6-5. Types of Test Sources
Test Source
INT2 (detects falling edge to any of KR0-KR3)
INTW (signal from watch timer)
Internal/External
External
Internal
6.10.2 Hardware devices controlling the test function
(1) Test request flag, test enable flag
The test request flag (IRQXXX) is set to “1” when a test request (INTXXX) is generated. When the test processing
is completed, it must be cleared to “0” by software.
The test enable flag (IEXXX) is annexed to each test request flag. When it is “1”, a standby release signal is
enabled; and when it is “0”, the signal is disabled.
When both the test request flag and test enable flag are set to “1”, a standby release signal is generated.
Table 6-6 lists the set signals for the test request flags.
Table 6-6. Set Signal for Test Request Flag
Test Request Flag
IRQW
Set Signal for Test Request Flag
Set by a signal sent from the watch timer.
Test Enable Flag
IEW
IE2
IRQ2
Set by the falling edge detection of a input to any of KR0/P60-KR3/P63 pins. The
detection edge is selected by the INT2 edge detection mode register (IM2).
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(2) Key interrupt (KR0-KR3) hardware
Figure 6-10 shows the configuration of KR0-KR3.
A pin which is used for the interrupt input is selected among the KR0-KR3 pins by the INT2 edge detection mode
register (IM2). The IRQ2 is set by the falling edge detection of a signal input to a selected pin.
Figure 6-11 shows the format of the IM2. The IM2 is set by a 4-bit manipulation instruction. All the bits are cleared
to “0” by a RESET signal and the rising edge specification by the INT2 is adopted.
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Figure 6-10. KR0-KR3 Block Diagram
Falling edge
detection
circuit
IRQ2
set signal
Selector
KR3/P63
KR2/P62
IM20, IM21
KR1/P61
KR0/P60
IM2
4
Input buffer
Internal bus
CHAPTER 6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
Figure 6-11. Format of INT2 Edge Detection Mode Register (IM2)
Address
FB6H
Symbol
IM21 IM20 IM2
3
0
2
0
1
0
IM21
IM20
INT2 test source
Interrupt input pin
1
1
0
1
KR2-KR3
KR0-KR3
(2)
(4)
Falling edge specification of any KRX pin input
Other setting prohibited
—
Cautions 1. If the edge detection mode register is changed, the test request flag may be set in some
cases; therefore the test input must be disabled beforehand to change the mode register
and the test request flag must be cleared by a CLR1 instruction, and then a test input must
be enabled.
2. When a low level signal is input to a pin among those pins selected for falling edge
detection, the IRQ2 is not set even if falling edges are input to the other pins.
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CHAPTER 7 STANDBY FUNCTIONS
The µPD753208 has a standby function that reduces the power dissipation of the system. This standby function
can be implemented in the following two modes:
• STOP mode
• HALT mode
The functions of the STOP and HALT modes are as follows:
(1) STOP mode
In this mode, the system clock oscillation circuit is stopped and therefore, the entire system is stopped. The power
dissipation of the CPU is substantially reduced.
Moreover, the contents of the data memory can be retained at a low voltage (VDD = 1.8 V MIN.). This mode is
therefore useful for retaining the data memory contents with an extremely low current dissipation.
The STOP mode of the µPD753208 can be released by an interrupt request; therefore, the microcomputer can
operate intermittently. However, because a wait time is required for stabilizing the oscillation of the clock
oscillation circuit when the STOP mode has been released, use the HALT mode if processing must be started
immediately after the standby mode has been released by an interrupt request.
(2) HALT mode
In this mode, the operating clock of the CPU is stopped. Oscillation of the system clock oscillation circuit
continues. This mode does not reduce the power dissipation as much as the STOP mode, but it is useful when
processing must be resumed immediately when an interrupt request is issued, or for an intermittent operation
such as a watch operation.
In either mode, all the contents of the registers, flags, and data memory immediately before the standby mode
is set are retained. Moreover, the contents of the output latches and output buffers of the I/O ports are also retained;
therefore, the statuses of the I/O ports are processed in advance so that the current dissipation of the overall system
can be minimized.
The following page describes the points to be noted in using the standby mode.
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Cautions 1. If the STOP mode is set when the LCD controller/driver and watch timer operate, the
operations of the LCD controller/driver and watch timer are stopped.
To continue the operations of these, therefore, use the HALT mode.
2. Efficient operation with a low current dissipation at a low voltage can be performed by
selecting the standby mode, CPU clock. In any case, however, the time described in 5.2.3
Setting of CPU clock is required until the operation is started with the new clock when the
clock has been changed by manipulating the control register. To use the CPU clock selecting
function and standby mode in combination, therefore, set the standby mode after the time
required for selection has elapsed.
3. To use the standby mode, process so that the current dissipation of the I/O ports is minimized.
Especially, do not open the input port, and be sure to input low or high level to it.
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CHAPTER 7 STANDBY FUNCTIONS
7.1 Standby Mode Setting and Operation Status
Table 7-1. Operation Status in Standby Mode
Mode
Item
STOP Mode
STOP instruction
HALT Mode
HALT instruction
Set instruction
Operation Clock generator
status
Only the system clock stops oscillation.
Only the CPU clock Φ halts (oscillation
continues).
Basic interval timer/
watchdog timer
Operation stops.
Operable only when the system clock is
oscillated.
BT mode: IRQBT is set at reference
time intervals
WT mode: Reset is occured by overflow
of BT
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable.
Timer/event counter
Operable only when a signal input to
Operable.
the TI0 pin is specified as the count clock.
Watch timer
Operation stops.
Operation stops.
Operable.
Operable.
LCD controller/driver
External interrupt
The INT2, and 4 are operable.
Note
Only the INT0 is not operated
.
CPU
Operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag or RESET signal input.
Note Can operate only when the noise eliminating circuit is not used (IM02 = 1) by bit 2 of the edge detection
mode register(IM0).
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CHAPTER 7 STANDBY FUNCTIONS
The STOP mode is set by a STOP instruction and the HALT mode is set by a HALT instruction. The STOP instruction
and HALT instruction set bit 3 and bit 2, respectively, of the PCC.
A NOP instruction must be placed following the STOP instruction and HALT instruction.
When changing the CPU clock by the low-order 2 bits of the PCC, thWere may be a time difference between PCC
updating and CPU clock change as shown in Table 5-5. Maximum Time Required to Switch to/from CPU Clock.
Consequently, when the operating clock before the standby mode and the CPU clock after the standby mode is
released are to be changed, the PCC must be updated and then the standby mode must be set after the machine
cycle necessary to change the CPU clock has elapsed.
In the standby mode, the data items stored in all the registers and data memory such as the general-purpose
register, flags, mode registers, and output latch which stop in the mode are held.
Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up with VDD on resistance of 50-
kΩ (TYP.).
2. Before setting the standby mode, reset all the interrupt request flags.
If there is an interrupt source in which both the test request flag and test enable flag are set,
the standby mode is released at the moment the system enters it (Refer to Figure 6-1 Interrupt
Control Circuit Block Diagram). However, when the STOP mode is set, the system enters the
HALT mode immediately after a STOP instruction is executed and then returns to the operating
mode after waiting for a time which is set in the BTM register.
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CHAPTER 7 STANDBY FUNCTIONS
7.2 Standby Mode Release
The standby mode (STOP or HALT) is released when an interrupt request signal enabled with an interrupt enable
flag occurs or a RESET signal is input. Figure 7-1 shows the standby mode release operation.
Figure 7-1. Standby Mode Release Operation (1/2)
(a) STOP mode release when a RESET signal is generated
Wait Note
STOP instruction
RESET
signal
Operation mode
STOP mode
HALT mode
Oscillation
Operation mode
Oscillation
Oscillation stop
Clock
(b) STOP mode release when an interrupt occurs
Wait
(setup time in BTM)
STOP instruction
Standby
release
signal
Operation mode
STOP mode
HALT mode
Oscillation
Operation mode
Oscillation
Oscillation stop
Clock
Note Following two wait time can be specified by the mask option.
217/fX (21.8 ms : 6.00 MHz operation, 31.3 ms: 4.19 MHz operation)
215/fX (5.46 ms : 6.00 MHz operation, 7.81 ms: 4.19 MHz operation)
However, the µPD75P3216 has no mask option, and wait time is fixed to 215/fX.
Remark Broken line: When the interrupt request to release the standby mode is acknowledged.
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CHAPTER 7 STANDBY FUNCTIONS
Figure 7-1. Standby Mode Release Operation (2/2)
(c) HALT mode release when a RESET signal is generated
Wait Note
HALT instruction
RESET
signal
Operation mode
HALT mode
Oscillation
Operation mode
Clock
(d) HALT mode release when an interrupt occurs
HALT instruction
Standby
release
signal
Operation mode
HALT mode
Operation mode
Oscillation
Clock
Note Following two wait times can be specified by the mask option.
217/fX (21.8 ms : 6.00 MHz operation, 31.3 ms: 4.19 MHz operation)
2
15/fX (5.46 ms : 6.00 MHz operation, 7.81 ms: 4.19 MHz operation)
However, the µPD75P3216 has no mask option, and wait time is fixed to 215/fX.
Remark Broken line: When the interrupt request to release of the standby mode is acknowledged.
When the STOP mode has been released by an interrupt, the wait time is determined by the setting of BTM (refer
to Table 7-2).
The time required for the oscillation to stabilize varies depending on the type of the oscillator used and the supply
voltage when the STOP mode has been released. Therefore, select the appropriate wait time depending on a given
condition, and set BTM before setting the STOP mode.
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CHAPTER 7 STANDBY FUNCTIONS
Table 7-2. Wait Time Selection by Using BTM
Note
Wait Time
BTM3
BTM2
BTM1
BTM0
When fX = 6.00 MHz
When fX = 4.19 MHz
–
–
–
–
0
0
1
1
0
1
0
1
0
1
1
1
About 220/fX (about 175 ms)
About 217/fX (about 21.8 ms)
About 215/fX (about 5.46 ms)
About 213/fX (about 1.37 ms)
Setting prohibited
About 220/fX (about 250 ms)
About 217/fX (about 31.3 ms)
About 215/fX (about 7.81 ms)
About 213/fX (about 1.95 ms)
Other than the above
Note This time does not include the time until oscillation is started after the STOP mode is released.
Caution The wait time that elapses when the STOP mode has been released does not include the time
that elapses until the clock oscillation is started after the STOP mode has been released (a
in Figure 7-2), regardless of whether the STOP mode has been released by the RESET signal
or occurrence of an interrupt.
Figure 7-2. Wait Time When STOP Mode Is Released
STOP mode release
X1 pin voltage
waveform
a
V
SS
7.3 Operation After Releasing the Standby Mode
(1) When the standby mode is released by a RESET signal generation, the normal reset operation is performed.
(2) When the standby mode is released by generation of an interrupt, whether a vectored interrupt is to be serviced
or not at the time the CPU resumes instruction execution is determined by the contents of the interrupt master
enable flag (IME).
(a) When IME = 0
Following the release of the standby mode, the instruction execution resumes starting with the instruction
subsequent to the standby mode setting instruction. The interrupt request flag is held.
(b) When IME = 1
After the standby mode is released, two instructions are executed and then a vectored interrupt is executed.
However, if the standby mode is released by the INTW and KR0 to KR3, a vectored interrupt is not generated;
therefore the operations identical to (a) above are performed.
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CHAPTER 7 STANDBY FUNCTIONS
7.4 Mask Option Selection
In the standby function of the µPD753208, the wait time after releasing the standby function by occurrence of
RESET signal can be selected from the following two by the mask option.
<1>
2
17/fX (21.8 ms: 6.0 MHz, 31.3 ms: 4.19 MHz)
<2> 215/fX (5.46 ms: 6.0 MHz, 7.81 ms: 4.19 MHz)
However, µPD75P3216 has no mask option, and wait time is fixed 215/fX.
7.5 Application of Standby Mode
Use the standby mode in the following procedure:
<1> Detect the cause that sets the standby mode, such as an interrupt input or power failure by port input (use of
INT4 to detect a power failure is recommended).
<2> Process the I/O ports (process so that the current dissipation is minimized).
It is important not to open the input port. Be sure to input a low or high level to it.
<3> Specify an interrupt that releases the standby mode (use of INT4 is effective. Clear the interrupt enable flags
of the interrupts that do not release the standby mode).
<4> Specify the operation to be performed after the standby mode has been released (manipulate IME depending
on whether interrupt processing is performed or not).
<5> Specify the CPU clock to be used after the standby mode has been released.
<6> Select the wait time to elapse after the standby mode has been released.
<7> Set the standby mode (by using the STOP or HALT instruction).
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Example When using the STOP mode under the following conditions
•
•
The STOP mode is set at the falling edge of INT4 and released at the rising edge (INTBT is not used).
All the I/O ports go into a high-impedance state (if the pins are externally processed so that the current
dissipation is reduced in a high-impedance state).
•
Interrupts INT0 and INTT0 are used in the program. However, these interrupts are not used to release the
STOP mode.
•
•
•
•
The interrupts are enabled even after the STOP mode has been released.
After the STOP mode has been released, operation is started with the slowest CPU clock.
The wait time that elapses after the mode has been released is about 21.8 ms.
A wait time of 21.8 ms elapses until the power supply stabilizes after the mode has been released. The P00/
INT4 pin is checked two times to eliminate chattering.
<Timing chart>
V
DD
VDD pin voltage
0 V
P00/INT4
Low-speed High-speed
operation operation
HALT mode
(wait)
Operation mode
STOP mode
CPU operation
21.8 ms
21.8 ms
INT4
STOP instruction
INT4
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CHAPTER 7 STANDBY FUNCTIONS
<Program example>
(INT4 processing program, MBE = 0)
VSUB4:
SKT
BR
PORT0.0
PDOWN
BTM.3
;
;
;
;
P00 = 1 ?
Power down
Power on
SET1
SKT
BR
WAIT:
IRQBT
Waits for 21.8 ms
WAIT
SKT
BR
PORT0.0
PDOWN
A, #0011B
PCC, A
XA, #XXH
PMGm, XA
IE0
;
Checks chattering
MOV
MOV
MOV
MOV
EI
;
;
Sets high-speed mode
Sets port mode register
EI
IET0
RETI
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DI
PDOWN:
A, #0
;
Lowest-speed mode
PCC, A
XA, #00H
LCDM, XA
LCDC, A
PMGA, XA
PMGB, XA
IE0
;
;
;
LCD display off
I/O port in high-impedance state
Disables INT0 and INTT0
DI
IET0
MOV
MOV
NOP
STOP
NOP
RETI
A, #1011B
BTM, A
.
;
;
Wait time =. 21.8 ms
Sets STOP mode
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CHAPTER 8 RESET FUNCTIONS
There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog
timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 8-1 shows the circuit
diagram of the above two inputs.
Figure 8-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Each device is initialized by the RESET signal generated as listed in Table 8-1. Figure 8-2 shows the timing chart
of the reset operation.
Figure 8-2. Reset Operation by RESET Signal Generation
Wait Note
RESET
signal
generated
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Note The following two times can be selected by the mask option.
217/fX (21.8 ms : 6.00 MHz operation, 31.3 ms: 4.19 MHz operation)
215/fX (5.46 ms : 6.00 MHz operation, 7.81 ms: 4.19 MHz operation)
However, the µPD75P3216 has no mask option, and wait time is fixed to 215/fX.
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CHAPTER 8 RESET FUNCTIONS
Table 8-1. Status of Each Device After Reset (1/2)
RESET Signal Generation
in the Standby Mode
RESET Signal Generation
in Operation
Hardware
Program counter (PC)
µPD753204 Sets the low-order 4 bits of
Sets the low-order 4 bits of
program memory’s address
program memory’s address
0000H to the PC11-PC8 and the 0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
contents of address 0001H to
the PC7-PC0.
µPD753206, Sets the low-order 5 bits of
µPD753208 program memory's address
Sets the low-order 5 bits of
program memory's address
0000H to the PC12-PC8 and the 0000H to the PC12-PC8 and the
contents of address 0001H to
the PC7-PC0.
contents of address 0001H to
the PC7-PC0.
µPD75P3216 Sets the low-order 6 bits of
Sets the low-order 6 bits of
program memory address 0000H program memory address 0000H
to PC13-8 and contents of
address 0001H to PC7-PC0
to PC13-8 and contents of
address 0001H to PC7-PC0
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
0
0
Interrupt status flag (IST0, 1)
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
Data memory (RAM)
1000B
1000B
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Bank select register (MBS, RBS)
Held
Undefined
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog Mode register (BTM)
0
0
0
0
timer
Watchdog timer enable flag (WDTM)
Timer/event
counter (T0)
Counter (T0)
0
0
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
FFH
0
FFH
0
0, 0
0
0, 0
0
Timer counter Counter (T1)
(T1) Modulo register (TMOD1)
FFH
0
FFH
0
Mode register (TM1)
TOE1, TOUT F/F
0, 0
0, 0
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CHAPTER 8 RESET FUNCTIONS
Table 8-1. Status of Each Device After Reset (2/2)
RESET Signal Generation
RESET Signal Generation
in Operation
Hardware
in the Standby Mode
Timer counter
(T2)
Counter (T2)
0
0
Modulo register (TMOD2)
FFH
FFH
FFH
FFH
High-level period setting modulo
register (TMOD2H)
Mode register (TM2)
0
0
TOE2, TOUT F/F
0, 0
0, 0
REMC, NRZ, NRZB
0, 0, 0
0, 0, 0
TGCE
0
0
Watch timer
Mode register (WM)
0
0
Serial interface
Shift register (SIO)
Held
Undefined
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register (PCC)
0
0
0
0
Held
Undefined
Clock generator,
0
0
clock output circuit Clock output mode register (CLOM)
0
0
LCD controller/
driver
Display mode register (LCDM)
Display control register (LCDC)
LCD/port selection register (LPS)
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Interrupt master enable flag (IME)
Interrupt priority selection register (IPS)
INT0, 2 mode registers (IM0, IM2)
Output buffer
0
0
0
0
0
0
Interrupt
function
Reset (0)
Reset (0)
0
0
0
0
0
0
0, 0
0, 0
Digital port
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, B, C)
Pull-up resistor setting register (POGA, B)
0
0
0
0
Bit sequential buffer (BSB0-3)
Held
Undefined
339
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CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY)
The program memory of the µPD75P3216 is a one-time PROM. The memory capacity is as follows:
µPD75P3216: 16384 words × 8 bits
To write or verify this one-time PROM, the pins shown in Table 9-1 are used. Note that no address input pins
are used and that the address is updated by inputting a clock from the X1 pin.
Table 9-1. Pins Used to Write or Verify Program Memory
Pin Name
Function
VPP
Applies program voltage for writing or verifying program memory (usually, VDD)
X1, X2
Inputs clock to update address when program memory is written or verified.
Complement of X1 pin is input to X2 pin.
MD0-MD3
Select operation mode when program memory is written or verified
Input or output 8-bit data when program memory is written or verified
D0/P60-D3/P63 (low-order 4)
D4/P50-D7/P53 (high-order 4)
VDD
Supplies power supply voltage. Supplies 1.8 to 5.5 V for normal operation and +6 V when
program memory is written or verified
Cautions 1. The program memory contents of the µPD75P3216 cannot be erased by ultraviolet rays
because the µPD75P3216 is not provided with a window for erasure.
2. Connect the pins not used for writing or verifying the program memory to VSS.
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CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY)
9.1 Operation Mode for Writing/Verifying Program Memory
When +6 V is applied to the VDD pin of the µPD75P3216 and +12.5 V is applied to the VPP pin, the program memory
write/verify mode is set. In this mode, the following operation modes can be selected by using the MD0 through MD3
pins.
Table 9-2. Operation Mode
Specifies Operation Mode
Operation Mode
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
H
L
Clears program memory address to 0
Write mode
L
H
H
L
H
H
Verify mode
H
×
H
H
Program inhibit mode
×: L or H
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CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY)
9.2 Writing Program Memory
The program memory can be written in the following procedure at high speed:
(1) Pull down the pins not used to VSS with a resistor. The X1 pin is low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait for 10 µs.
(4) Set the program memory address 0 clear mode.
(5) Supply 6 V to VDD and 12.5 V to VPP.
(6) Write data in the 1-ms write mode
(7) Set the verify mode. If the data have been correctly written, proceed to (8). If not, repeat (6) and (7).
(8) Additional writing of (number of times data have been written in (6) and (7): X) × 1 ms
(9) Input a pulse four times to the X1 pin to update the program memory address (by one).
(10) Repeat (6) through (9) until the last address is written.
(11) Set the program memory address 0 clear mode.
(12) Change the voltage applied to the VDD and VPP pins to 5 V.
(13) Turn off the power supply.
Steps (2) through (9) above are illustrated below.
Repeat X times
Additional
write
Address
increment
Write
Verify
V
PP
DD
V
PP
DD
V
V
DD+1
DD
V
V
X1
D0/P60 - D3/P63
D4/P50 - D7/P53
Data output
Data input
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
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CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY)
9.3 Reading Program Memory
The contents of the program memory can be read in the following procedure. Reading is executed in the verify
mode.
(1) Pull down the pins not used to VSS with a resistor. The X1 pin is low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait for 10 µs.
(4) Set the program memory address 0 clear mode.
(5) Supply 6 V to VDD and 12.5 V to VPP.
(6) Verify mode. Data of each address is sequentially output at the cycle in which four clock pulses are input to the
X1 pin.
(7) Set the program memory address 0 clear mode.
(8) Change the voltage applied to the VDD and VPP pins to 5 V.
(9) Turn off the power supply.
Steps (2) through (7) above are illustrated below.
V
PP
V
PP
VDD
V
DD + 1
V
DD
VDD
X1
D0/P60-D3/P63
D4/P50-D7/P53
Data output
Data output
MD0/P30
MD1/P31
MD2/P32
“L”
MD3/P33
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CHAPTER 9 WRITING AND VERIFYING PROM (PROGRAM MEMORY)
9.4 Screening of One-Time PROM
Because of its structure, it is difficult for NEC to completely test the one-time PROM product before shipment. It
is therefore recommended that screening be performed to verify the PROM contents after the necessary data has
been written to the PROM and the product has been stored under the following conditions.
Storage Temperature
Storage Time
24 hours
125 °C
NEC provides a fee-based, one-time microprocessor PROM writing, marking, screening, and verifying service
called QTOPTM. For details, consult your NEC distributor.
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[MEMO]
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CHAPTER 10 MASK OPTION
10.1 Pin
The pins of the µPD753208 have the following mask options:
Table 10-1. Selecting Mask Option of Pin
Pin
P50-P53
Mask Option
Pull-up resistor can be connected in 1-bit units.
VLC0-VLC2, BIAS
LCD drive power supplying divider resistors can be connected to four pins at once.
10.1.1 Mask option of P50 through P53
P50 through P53 (port 5) can be connected with pull-up resistors by mask option. The mask option can be specified
in 1-bit units.
If the pull-up resistor is connected by mask option, port 5 goes high on reset. If the pull-up resistor is not connected,
the port goes into a high-impedance state on reset.
The µPD75P3216 does not incorporate pull-up resistors by mask option.
10.1.2 Mask option of VLC0 through VLC2
Divider resistors can be connected to the VLC0 through VLC2 pins (LCD drive power supply) and BIAS pin (external
divider resistor cutting pin) by mask option. Therefore, LCD drive power can be supplied without an external divider
resistor according to each bias (for details, refer to 5.7.8 Supply of LCD drive power VLC0, VLC1, and VLC2).
The following three mask options can be selected.
<1> No divider resistor is connected.
<2> A 10-kΩ (typ.) divider resistor is connected.
<2> A 100-kΩ (typ.) divider resistor is connected.
The mask option is specified for the VLC0 through VLC2 and BIAS pins at once and cannot be specified in 1-pin units.
The BIAS pin goes low on reset when the divider resistor is connected to this pin by mask option. When the divider
resistor is not connected, the BIAS pin goes into a high-impedance state on reset.
The µPD75P3216 does not have a mask option, and cannot be connected with a divider resistor. Connect an
external divider resistor to the µPD75P3216, if necessary.
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CHAPTER 10 MASK OPTION
10.2 Mask Option of Standby Function
The standby function of the µPD753208 allows you to select wait time by using a mask option. The wait time is
required for the CPU to return to the normal operation mode after the standby function has been released by the RESET
signal (for details, refer to 7.2 Standby Mode Release).
The following two wait times can be selected:
<1> 217/fX (21.8 ms: fX = 6.00 MHz operation, 31.3 ms: fX = 4.19 MHz operation)
<2> 215/fX (5.46 ms: fX = 6.00 MHz operation, 7.81 ms: fX = 4.19 MHz operation)
The µPD75P3216 does not have a mask option and its wait time is fixed to 215/fX.
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CHAPTER 11 INSTRUCTION SET
The instruction set of the µPD753208 is based on the instruction set of the 75X series and therefore, maintains
compatibility with the 75X series, but has some improved features. They are:
(1) Bit manipulation instructions for various applications
(2) Efficient 4-bit manipulation instructions
(3) 8-bit manipulation instructions comparable to those of 8-bit microcomputers
(4) GETI instruction reducing program size
(5) String-effect and base number adjustment instructions enhancing program efficiency
(6) Table reference instructions ideal for successive reference
(7) 1-byte relative branch instruction
(8) Easy-to-understand, well-organized NEC’s standard mnemonics
For the addressing modes applicable to data memory manipulation and the register banks valid for instruction
execution, refer to 3.2 Bank Configuration of General-Purpose Registers.
11.1 Unique Instructions
This section describes the unique instructions of the µPD753208’s instruction set.
11.1.1 GETI instruction
The GETI instruction converts the following instructions into 1-byte instructions:
(a) Subroutine call instruction to 16K-byte space (0000H-3FFFH)
(b) Branch instruction to 16K-byte space (0000H-3FFFH)
(c) Any 2-byte, 2-machine cycle instruction (except BRCB and CALLF instructions)
(d) Combination of two 1-byte instructions
The GETI instruction references a table at addresses 0020H through 007FH of the program memory and executes
the referenced 2-byte data as an instruction of (a) to (d). Therefore, 48 types of instructions can be converted into
1-byte instructions.
If instructions that are frequently used are converted into 1-byte instructions by using this GETI instruction, the
number of bytes of the program can be substantially decreased.
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11.1.2 Bit manipulation instruction
The µPD753208 has reinforced bit test, bit transfer, and bit Boolean (AND, OR, and XOR) instructions, in addition
to the ordinary bit manipulation (set and clear) instructions.
The bit to be manipulated is specified in the bit manipulation addressing mode. Three types of bit manipulation
addressing modes can be used. The bits manipulated in each addressing mode are shown in Table 11-1.
Table 11-1. Types of Bit Manipulation Addressing Modes and Specification Range
Addressing
fmem.bit
Peripheral Hardware that Can Be Manipulated
RBE, MBE, IST1, IST0, IE×××, IRQ×××
PORT0-3, 5, 6, 8, 9
Addressing Range of Bit that Can Be Manipulated
FB0H-FBFH
FF0H-FFFH
FC0H-FFFH
pmem.@L
BSB0-3, PORT-3, 5, 6, 8, 9
@H + mem.bit
All peripheral hardware units that can be
manipulated bitwise
All bits of memory bank specified by MB that can
be manipulated bitwise
Remarks 1. ×××: 0, 2, 4, BT, T0, T1, T2, W, CSI
2. MB = MBE and MBS
11.1.3 String-effect instruction
The µPD753208 has the following two types of string-effect instructions:
(a) MOV A, #n4 or MOV XA, #n8
(b) MOV HL, #n8
“String effect” means locating these two types of instructions at contiguous addresses.
Example A0 : MOV A, #0
A1 : MOV A, #1
XA7 : MOV XA, #07
When string-effect instructions are arranged as shown in this example, and if the address executed first is A0, the
two instructions following this address are replaced with the NOP instructions. If the address executed first is A1,
the following one instruction is replaced with the NOP instruction. In other words, only the instruction that is executed
first is valid, and all the string-effect instructions that follow are processed as NOP instructions.
By using these string-effect instructions, constants can be efficiently set to the accumulator (A register or register
pair XA) and data pointer (register pair HL).
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11.1.4 Base number adjustment instruction
Some application requires that the result of addition or subtraction of 4-bit data (which is carried out in binary
number) be converted into a decimal number or into a number with a base of 6, such as time.
Therefore, the µPD753208 is provided with base number adjustment instructions that adjusts the result of addition
or subtraction of 4-bit data into a number with any base.
(a) Base adjustment of result of addition
Where the base number to which the result of addition executed is to be adjusted is m, the contents of the
accumulator and memory (HL) are added in the following combination, and the result is adjusted to a number
with a base of m:
ADDS A, #16–m
ADDC A, @HL ; A, CY ← A + (HL) + CY
ADDS A, #m
Occurrence of an overflow is indicated by the carry flag.
If a carry occurs as a result of executing the ADDC A, @HL instruction, the ADDS A, #n4 instruction is skipped.
If a carry does not occur, the ADDS A, #n4 instruction is executed. At this time, however, the skip function of
the instruction is disabled, and the following instruction is not skipped even if a carry occurs as a result of addition.
Therefore, a program can be written after the ADDS A, #n4 instruction.
Example To add accumulator and memory in decimal
ADDS A, #6
ADDC A, @HL ; A, CY ← A + (HL) + CY
ADDS A, #10
.
.
.
(b) Base adjustment of result of subtraction
Where the base number into which the result of subtraction executed is to be adjusted is m, the contents of memory
(HL) are subtracted from those of the accumulator in the following combination, and the result of subtraction is
adjusted to a number with a base of m:
SUBC A, @HL
ADDS A, #m
Occurrence of an underflow is indicated by the carry flag.
If a borrow does not occur as a result of executing the SUBC A, @HL instruction, the following ADDS A, #n4
instruction is skipped. If a borrow occurs, the ADDS A, #n4 instruction is executed. At this time, the skip function
of this instruction is disabled, and the following instruction is not skipped, even if a carry occurs as a result of
addition. Therefore, a program can be written after the ADDS A, #n4 instruction.
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11.1.5 Skip instruction and number of machine cycles required for skipping
The instruction set of the µPD753208 configures a program where instructions may be or may not be skipped if
a given condition is satisfied.
If a skip condition is satisfied when a skip instruction is executed, the instruction next to the skip instruction is
skipped and the instruction after the next is executed.
When a skip occurs, the number of machine cycles required for skipping is:
(a) If the instruction that follows the skip instruction (i.e., the instruction to be skipped) is a 3-byte instruction (BR
!addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction): 2 machine cycles
(b) Instruction other than (a): 1 machine cycle
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11.2 Instruction Sets and their Operations
(1) Operand identifiers and methods of use
The operands are written in the operand column of each instruction in accordance with the method of use of the
operand identifier. For details, refer to “RA75X ASSEMBLER PACKAGE USER’S MANUAL——LANGUAGE
(U12385E)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols
are key words and are written as they are.
For immediate data, appropriate numbers and labels are written.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers shown in Figure 3-7 can
be written. However, there are restrictions in the labels that can be written for fmem and pmem. For details,
refer to Table 3-1. Addressing Mode and Figure 3-7. µPD753208 I/O Map.
Identifier
Format
reg
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
reg1
rp
XA, BC, DE, HL
BC, DE, HL
BC, DE
rp1
rp2
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rp'1
rpa
HL, HL+, HL–, DE, DL
DE, DL
rpa1
n4
n8
4-bit immediate data or label
8-bit immediate data or label
Note
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
pmem
addr
000H-FFFH immediate data or label (µPD753204)
0000H-17FFH immediate data or label (µPD753206)
0000H-1FFFH immediate data or label (µPD753208)
0000H-3FFFH immediate data or label (µPD7P3216)
000H-FFFH immediate data or label (µPD753204)
0000H-17FFH immediate data or label (µPD753206)
0000H-1FFFH immediate data or label (µPD753208)
0000H-3FFFH immediate data or label (µPD75P3216)
12-bit immediate data or label
addr1
caddr
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit 0 = 0) or label
PORTn
IE×××
RBn
PORT0-PORT3, PORT5, PORT6, PORT8, PORT9
IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW
RB0-RB3
MBn
MB0, MB1, MB15
Note mem can be only used for even address in 8-bit data processing.
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(2) Legend in explanation of operation
A
: A register, 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
BC
DE
HL
XA’
BC’
DE’
HL’
PC
SP
CY
PSW
MBE
RBE
: XA register pair; 8-bit accumulator
: BC register pair
: DE register pair
: HL register pair
: XA’ expanded register pair
: BC’ expanded register pair
: DE’ expanded register pair
: HL’ expanded register pair
: Program counter
: Stack pointer
: Carry flag, bit accumulator
: Program status word
: Memory bank enable flag
: Register bank enable flag
PORTn : Port n (n = 0-3, 5, 6, 8, 9)
IME
IPS
: Interrupt master enable flag
: Interrupt priority selection register
: Interrupt enable flag
IE×××
RBS
MBS
PCC
.
: Register bank selection register
: Memory bank selection register
: Processor clock control register
: Separation between address and bit
: The contents addressed by ××
: Hexadecimal data
(××)
××H
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(3) Explanation of symbols under addressing area column
*1
MB = MBE•MBS
(MBS = 0, 1, 15)
*2
*3
MB = 0
MBE = 0 : MB = 0 (00H-7FH)
MB = 15 (F80H-FFFH)
Data memory addressing
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
MB = 15, pmem = FC0H-FFFH
*4
*5
*6
µPD753204
µPD753206
µPD753208
µPD75P3216
addr = 000H-FFFH
addr = 0000H-17FFH
addr = 0000H-1FFFH
addr = 0000H-3FFFH
*7
*8
addr = (Current PC) – 15 ~ (Current PC) – 1
(Current PC) + 2 ~ (Current PC) + 16
addr1 = (Current PC) – 15 ~ (Current PC) – 1
(Current PC) + 2 ~ (Current PC) + 16
µPD753204
µPD753206
caddr = 000H-FFFH
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-17FFH(PC12 = 1)
Program memory addressing
µPD753208
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-1FFFH(PC12 = 1)
µPD75P3216
caddr = 0000H-0FFFH (PC13, 12 = 00B) or
1000H-1FFFH (PC13, 12 = 01B) or
2000H-2FFFH (PC13, 12 = 10B) or
3000H-3FFFH (PC13, 12 = 11B)
*9
faddr = 0000H-07FFH
taddr = 0020H-007FH
*10
*11
µPD753204
µPD753206
µPD753208
µPD75P3216
addr1 = 000H-FFFH (MKII mode only)
addr1 = 0000H=17FFH (MKII mode only)
addr1 = 0000H-1FFFH (MKII mode only)
addr1 = 0000H-3FFFH (MKII mode only)
Remarks 1. MB indicates memory bank that can be accessed.
2. In *2, MB = 0 independently of how MBE and MBS are set.
3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4. *6 to *11 indicate the areas that can be addressed.
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(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The
value of S varies as follows.
•
•
•
When no skip is made: S = 0
When the skipped instruction is a 1- or 2-byte instruction: S = 1
When the skipped instruction is a 3-byte instructionNote: S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by
setting PCC (Refer to Figure 5-12. Processor Clock Control Register Format).
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
MOV
Operand
of Machine
Cycles
Operation
Skip Condition
String effect A
of Bytes
Transfer
A, #n4
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
2
A ← n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL–
A, @rpa
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
reg1 ← n4
2
XA ← n8
String effect A
String effect B
2
HL ← n8
2
rp2 ← n8
1
A ← (HL)
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
2+S
2+S
1
A ← (HL), then L ← L+1
A ← (HL), then L ← L–1
A ← (rpa1)
L = 0
L = FH
2
XA ← (HL)
1
(HL) ← A
2
(HL) ← XA
2
A ← (mem)
XA ← (mem)
(mem) ← A
(mem) ← XA
A ← reg
2
2
2
2
XA, rp’
2
XA ← rp’
reg1, A
2
reg1 ← A
rp'1, XA
A, @HL
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
A, mem
XA, mem
A, reg1
2
rp’1 ← XA
XCH
1
A ↔ (HL)
*1
*1
*1
*2
*1
*3
*3
2+S
2+S
1
A ↔ (HL), then L ← L+1
A ↔ (HL), then L ← L–1
A ↔ (rpa)
L = 0
L = FH
2
XA ↔ (HL)
2
A ↔ (mem)
XA ↔ (mem)
A ↔ reg1
2
1
XA, rp’
2
XA ↔ rp’
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Number
Number
Instruction
Group
Addressing
Area
Mnemonic
MOVT
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Table
XA, @PCDE
1
3
•
µPD753204
reference
XA ← (PC11–8+DE)ROM
•
µPD753206, 753208
XA ← (PC12–8+DE)ROM
•
µPD75P3216
XA ← (PC13-8+DE)ROM
XA, @PCXA
1
3
•
µPD753204
XA ← (PC11–8+XA)ROM
•
µPD753206, 753208
XA ← (PC12–8+XA)ROM
•
µPD75P3216
XA ← (PC13–8+XA)ROM
ROMNote
XA, @BCDE
XA, @BCXA
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
1
1
2
2
2
2
2
2
1
2
1
2
2
1
2
2
3
3
XA ← (BCDE)
*6
*6
*4
*5
*1
*4
*5
*1
ROMNote
XA ← (BCXA)
Bit transfer
MOV1
2
CY ← (fmem.bit)
2
CY ← (pmem7–2+L3–2.bit(L1–0))
CY ← (H+mem3–0.bit)
(fmem.bit) ← CY
2
2
2
(pmem7–2+L3–2.bit(L1–0)) ← CY
(H+mem3–0.bit) ← CY
A ← A+n4
2
Operation
ADDS
1+S
2+S
1+S
2+S
2+S
1
carry
carry
carry
carry
carry
XA, #n8
XA ← XA+n8
A, @HL
A ← A+(HL)
*1
*1
XA, rp’
XA ← XA+rp’
rp’1, XA
rp’1 ← rp’1+XA
ADDC
A, @HL
A, CY ← A+(HL)+CY
XA, CY ← XA+rp’+CY
rp’1, CY ← rp’1+XA+CY
XA, rp’
2
rp’1, XA
2
Note When using the µPD753204, set “0” to the B register.
When using the µPD753206 and 753208, only the low-order 1 bit of the B register is valid.
When using the µPD75P3216, only the low-order 2 bits are valid.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
SUBS
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Operation
A, @HL
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1+S
2+S
2+S
1
A ← A–(HL)
*1
borrow
borrow
borrow
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A
XA ← XA–rp’
rp’1 ← rp’1–XA
A, CY ← A–(HL)–CY
XA, CY ← XA–rp’–CY
rp’1, CY ← rp’1–XA–CY
A ← A n4
SUBC
AND
*1
2
2
2
1
A ← A (HL)
*1
*1
*1
2
XA ← XA rp’
rp’1 ← rp’1 XA
A ← A n4
2
OR
2
1
A ← A (HL)
2
XA ← XA rp’
rp’1 ← rp’1 XA
A ← A v n4
2
XOR
2
1
A ← A v (HL)
2
XA ← XA v rp’
rp’1 ← rp’1 v XA
2
Accumulator RORC
manipulation
NOT
1
CY ← A
A ← A
0, A
3
← CY, An–1 ← A
n
A
2
Increment
and
decrement
INCS
reg
1+S
1+S
2+S
2+S
1+S
2+S
2+S
2+S
1+S
2+S
2+S
2+S
reg ← reg+1
rp1 ← rp1+1
reg=0
rp1
rp1=00H
(HL)=0
@HL
(HL) ← (HL)+1
(mem) ← (mem)+1
reg ← reg–1
*1
*3
mem
(mem)=0
reg=FH
rp'=FFH
reg=n4
DECS
SKE
reg
rp’
rp’ ← rp’–1
Compare
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp’
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp’
*1
*1
*1
(HL) = n4
A = (HL)
XA = (HL)
A=reg
XA=rp’
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Carry flag
manipulation
SET1
CLR1
SKT
CY
CY
CY
CY
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
CY ← 1
CY ← 0
1+S
1
Skip if CY = 1
CY=1
NOT1
SET1
CY ← CY
Memory bit
manipulation
mem. bit
2
(mem.bit) ← 1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
fmem. bit
2
(fmem.bit) ← 1
pmem. @L
2
(pmem7–2+L3–2.bit(L1–0)) ← 1
(H+mem3–0.bit) ← 1
@H+mem. bit
mem. bit
2
CLR1
2
(mem.bit) ← 0
fmem. bit
2
(fmem.bit) ← 0
pmem. @L
2
(pmem7–2+L3–2.bit(L1–0)) ← 0
(H+mem3–0.bit) ← 0
@H+mem. bit
mem. bit
2
SKT
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2
Skip if (mem.bit)=1
(mem.bit)=1
fmem. bit
Skip if (fmem.bit)=1
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
(mem.bit)=0
pmem. @L
Skip if (pmem7–2+L3–2.bit(L1–0))=1
Skip if (H+mem3–0.bit)=1
Skip if (mem.bit)=0
@H+mem. bit
mem. bit
SKF
fmem. bit
Skip if (fmem.bit)=0
(fmem.bit)=0
(pmem.@L)=0
(@H+mem.bit)=0
(fmem.bit)=1
(pmem.@L)=1
(@H+mem.bit)=1
pmem. @L
Skip if (pmem7–2+L3–2.bit(L1–0))=0
Skip if (H+mem3–0.bit)=0
Skip if (fmem.bit)=1 and clear
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
Skip if (H+mem3–0.bit)=1 and clear
CY ← CY (fmem.bit)
CY ← CY (pmem7–2+L3–2.bit(L1–0))
CY ← CY (H+mem3–0.bit)
CY ← CY (fmem.bit)
CY ← CY (pmem7–2+L3–2.bit(L1–0))
CY ← CY (H+mem3–0.bit)
CY ← CY v (fmem.bit)
CY ← CY v (pmem7–2+L3–2.bit(L1–0))
CY ← CY v (H+mem3–0.bit)
@H+mem. bit
fmem. bit
SKTCLR
AND1
OR1
pmem. @L
@H+mem. bit
CY, fmem. bit
CY, pmem. @L
CY, @H+mem. bit
CY, fmem. bit
CY, pmem. @L
CY, @H+mem. bit
CY, fmem. bit
CY, pmem. @L
CY, @H+mem. bit
2
2
2
2
2
XOR1
2
2
2
User’s Manual U10158EJ2V1UM00
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
BRNote
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Branch
addr
–
–
• µPD753204
*6
PC11–0 ← addr
Select appropriate instruction from
among BRCB !caddr and BR $addr
according to the assembler being used.
• µPD753206, 753208
PC12–0 ← addr
Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler
being used.
• µPD75P3216
PC13–0 ← addr
Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler
being used.
addr1
–
–
• µPD753204
*11
PC11-0 ← addr
Select appropriate instruction from
among BRA !addr1, BRCB !caddr and
BR $addr1 according to the assembler
being used.
• µPD753206, 753208
PC12–0 ← addr1
Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.
• µPD75P3216
PC13–0 ← addr1
Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.
! addr
3
3
• µPD753204
PC11–0 ← addr
*6
• µPD753206, 753208
PC12–0 ← addr
• µPD75P3216
PC13–0 ← addr
$addr
1
2
• µPD753204
PC11–0 ← addr
*7
• µPD753206, 753208
PC12–0 ← addr
• µPD75P3216
PC13–0 ← addr
Note The above operations in the shaded boxes can be performed only in the Mk II mode.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
BRNote 1
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Branch
$addr1
1
2
3
3
3
3
• µPD753204
*7
PC11–0 ← addr1
• µPD753206, 753208
PC12–0 ← addr1
• µPD75P3216
PC13–0 ← addr1
PCDE
PCXA
BCDE
BCXA
2
2
2
2
• µPD753204
PC11–0 ← PC11-8+DE
• µPD753206, 753208
PC12–0 ← PC12-8+DE
• µPD75P3216
PC13–0 ← PC13-8+DE
• µPD753204
PC11–0 ← PC11-8+XA
• µPD753206, 753208
PC12–0 ← PC12-8+XA
• µPD75P3216
PC13–0 ← PC13-8+XA
• µPD753204
PC11–0 ← BCDENote 2
*6
• µPD753206, 753208
PC12–0 ← BCDENote 3
• µPD75P3216
PC13–0 ← BCDENote 4
• µPD753204
PC11–0 ← BCXANote 2
*6
• µPD753206, 753208
PC12–0 ← BCXANote 3
• µPD75P3216
PC13–0 ← BCXANote 4
Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
2. “0” must be set to B register.
3. Only low-order one bit is valid in B register.
4. Only low-order two bits are valid in B register.
User’s Manual U10158EJ2V1UM00
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
BRANote
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Branch
!addr1
3
3
2
3
• µPD753204
*6
PC11–0 ← addr1
• µPD753206, 753208
PC12–0 ← addr1
• µPD75P3216
PC13–0 ← addr1
BRCB
!caddr
2
• µPD753204
PC11–0 ← caddr11–0
*8
• µPD753206, 753208
PC12–0 ← PC12+caddr11–0
• µPD75P3216
PC13–0 ← PC13, 12+caddr11–0
Subroutine
CALLANote !addr1
3
• µPD753204
*11
stack control
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr1, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr1, SP ← SP–6
• µPD75P3216
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, PC13, 12
PC13–0 ← addr1, SP ← SP–6
CALLNote
!addr
3
3
• µPD753204
*6
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← addr, SP ← SP–4
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← addr, SP ← SP–4
• µPD75P3216
(SP–3) ← MBE, RBE, PC13, 12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC13–0 ← addr, SP ← SP–4
4
• µPD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, PC12
PC12–0 ← addr, SP ← SP–6
• µPD75P3216
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, PC13, 12
PC13–0 ← addr, SP ← SP–6
Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Subroutine
CALLFNote !faddr
2
2
• µPD753204
*9
stack control
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← 0+faddr, SP ← SP–4
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← 00+faddr, SP ← SP–4
• µPD75P3216
(SP–3) ← MBE, RBE, PC13, 12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC13–0 ← 000+faddr, SP ← SP–4
3
• µPD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← 0+faddr, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← 00+faddr, SP ← SP–6
• µPD75P3216
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, PC13, 12
PC13–0 ← 000+faddr, SP ← SP–6
RETNote
1
3
• µPD753204
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4
• µPD753206, 753208
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, PC12 ← (SP+1), SP ← SP+4
• µPD75P3216
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, PC13, 12 ← (SP+1)
SP ← SP+4
• µPD753204
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0, ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
• µPD753206, 753208
×, ×, MBE, RBE ← (SP+4)
MBE, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
• µPD75P3216
×, ×, MBE, RBE ← (SP+4)
PC11–0 ← (SP) (SP+3) (SP+2)
MBE, 0, PC13, 12 ← (SP+1)
SP ← SP+6
Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
User’s Manual U10158EJ2V1UM00
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
RETSNote
Operand
of Machine
Cycles
Operation
Skip Condition
Unconditional
of Bytes
Subroutine
1
3+S
• µPD753204
stack control
MBE, RBE, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD753206, 753208
MBE, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD75P3216
MBE, 0, PC13, 12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
• µPD75P3216
×, ×, MBE, RBE ← (SP+4)
PC11–0 ← (SP) (SP+3) (SP+2)
0, 0, PC13, 12 ← (SP+1)
SP ← SP+6
then skip unconditionally
Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
RETINote
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Subroutine
1
3
• µPD753204
stack control
MBE, RBE, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
MBE, RBE, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD75P3216
MBE, RBE, PC13, 12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD75P3216
0, 0, PC13, 12 ← SP+1
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
PUSH
rp
1
1
(SP–1)(SP–2) ← rp, SP ← SP–2
BS
rp
2
1
2
2
2
1
2
2
(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2
rp ← (SP+1) (SP), SP ← SP+2
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
IME (IPS.3) ← 1
POP
EI
BS
Interrupt
control
IE×××
IE×××
2
2
2
2
2
2
IE××× ← 1
DI
IME (IPS.3) ← 0
IE××× ← 0
Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
INNote 1
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Input/output
A, PORTn
XA, PORTn
2
2
2
2
A ← PORTn
(n = 0-3, 5, 6, 8, 9)
(n = 8)
XA ← PORTn+1, PORTn
OUTNote 1 PORTn, A
PORTn, XA
2
2
2
2
2
2
PORTn ← A
(n = 2, 3, 5, 6, 8, 9)
(n = 8)
PORTn+1, PORTn ← XA
CPU control HALT
Set HALT Mode (PCC.2 ← 1)
STOP
NOP
2
1
2
2
1
2
1
2
2
3
Set STOP Mode (PCC.3 ← 1)
No Operation
Special
SEL
RBn
MBn
taddr
RBS ← n
(n = 0-3)
MBS ← n
(n = 0, 1, 15)
Note
2
GETI
• µPD753204
*10
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP–3) ← MBE, RBE, 0, 0
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
• µPD753206, 753208
• When TBR instruction
PC12–0 ← (taddr)4–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP–3) ← MBE, RBE, 0, PC12
PC12–0 ← (taddr)4–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
• µPD75P3216
• When TBR instruction
PC13–0 ← (taddr)5–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC11–0
(SP+1) ← MBE, RBE, 0, PC13, 12
PC13–0 ← (taddr)5–0 + (taddr+1)
SP ← SP–4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
Notes 1. While the IN instruction and OUT instruction are being executed, the MBS must be set to 0 or 1 and
MBS must be set to 15.
2. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
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CHAPTER 11 INSTRUCTION SET
Number
Number
Instruction
Group
Addressing
Area
Mnemonic
Operand
of Machine
Cycles
Operation
Skip Condition
of Bytes
Notes 1, 2
Special
GETI
taddr
1
3
• µPD753204
*10
• When TBR instruction
PC11–0 ← (taddr)3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC11–0 ← (taddr)3–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
Depending on
the reference
instruction
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
3
• µPD753206, 753208
• When TBR instruction
PC12–0 ← (taddr)4–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
(SP–2) ← ×, ×, MBE, RBE
PC12–0 ← (taddr)4–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
3
• µPD75P3216
• When TBR instruction
PC13–0 ← (taddr)5–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
4
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← MBE, RBE, PC13, 12
(SP–2) ← ×, ×, MBE, RBE
PC13–0 ← (taddr)5–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – –
Depending on
the reference
instruction
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Notes 1. The TBR, TCALL instructions are the table definition assembler pseudo instructions of the GETI
instructions.
2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
User’s Manual U10158EJ2V1UM00
368
CHAPTER 11 INSTRUCTION SET
11.3 Op Code of Each Instruction
(1) Description of symbol of op code
reg
A
reg-pair
XA
R
2
R
0
0
1
1
0
0
1
1
1
R
0
P
2
P
1
P
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
XA’
HL
L
H
E
HL’
reg
rp’
reg1
rp’1
DE
D
C
B
DE’
BC
BC’
reg-pair
addressing
@HL
Q
0
0
0
1
1
2
Q
0
1
1
0
0
1
Q
0
0
1
0
1
0
P
2
P
1
0
0
XA
HL
DE
BC
0
1
1
1
0
1
@HL+
@HL –
@DE
rp
rp1
@rpa
@rpa1
rp2
@DL
IE×××
IEBT
IEW
IET0
IECSI
IE0
N
0
0
0
0
0
0
1
1
1
1
5
N
0
0
1
1
1
1
0
1
1
1
2
N
0
1
0
0
1
1
0
0
0
1
1
N
0
0
0
0
1
0
1
0
0
1
0
IE2
IE4
IET1
IET2
IE1
In : immediate data for n4 or n8
Dn : immediate data for mem
Bn : immediate data for bit
Nn : immediate data for n or IE×××
Tn : immediate data for taddr × 1/2
An : immediate data for [relative address distance from branch destination address (2 – 16)] – 1
Sn : immediate data for 1’s complement of [relative address distance from branch destination address (15 –
1)]
369
User’s Manual U10158EJ2V1UM00
CHAPTER 11 INSTRUCTION SET
(2) Op code for bit manipulation addressing
1
•
in the operand field indicates the following three types:
fmem.bit
•
pmem.@L
@H+mem.bit
•
The second byte 2 of the op code corresponding to the above addressing is as follows:
1
2nd Byte of Code
Accessible Bit
fmem. bit
1
1
0
0
0
1
1
0
B1 B0
B1 B0
F3
F3
F2
F2
F1
F1
F0
F0
Bit of FB0H-FBFH that can be manipulated
Bit of FF0H-FFFH that can be manipulated
pmem. @L
0
0
G3 G2 G1 G0 Bit of FC0H-FFFH that can be manipulated
@H+mem. bit
B1 B0 D3 D2 D1 D0 Bit of accessible memory bank that can be manipulated
Bn : immediate data for bit
Fn : immediate data for fmem (indicates low-order 4 bits of address)
Gn : immediate data for pmem (indicates bits 5-2 of address)
Dn : immediate data for mem (indicates low-order 4 bits of address)
User’s Manual U10158EJ2V1UM00
370
CHAPTER 11 INSTRUCTION SET
Op Code
Instruction
Transfer
Mnemonic
MOV
Operand
B
1
B
2
B
3
A, #n4
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
1
1
1
1
1
I
3
I
2
I
1
I
0
reg1, #n4
rp, #n8
1
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
I
I
3
7
I
I
2
6
I
I
1
5
I
I
0
4
1
R
2
R
1
R
0
P
2
P
1
I
3
I
2
I
1
I
0
A, @rpa1
XA, @HL
@HL, A
Q
2
Q
1
Q
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
@HL, XA
A, mem
0
0
0
1
D
D
D
D
7
D
D
D
D
6
D
D
D
D
5
D
D
D
D
4
D
D
D
D
3
3
3
3
D
D
D
D
R
2
D
D
D
D
R
1
D
0
XA, mem
mem, A
7
7
7
6
6
6
5
5
5
4
2
2
2
2
1
1
1
1
0
4
4
D
0
mem, XA
A, reg
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
R
0
XA, rp’
P2
R2
P2
P
1
P
0
reg1, A
R
1
R
0
rp’1, XA
P
1
P
0
XCH
A, @rpa1
XA, @HL
A, mem
Q
0
0
0
2
Q
1
1
1
1
Q
0
1
0
0
0
0
0
1
0
0
0
1
D
D
7
D
D
6
D
D
5
D
D
4
D
D
3
D
D
2
D
D
1
D
0
XA, mem
A, reg1
7
6
5
4
3
2
1
0
R
0
1
0
1
0
1
0
2
R
1
0
0
0
0
0
1
1
R
0
0
0
1
1
1
1
0
XA, rp’
0
1
0
0
0
P
2
P
1
P
0
MOVT
MOV1
XA, @PCDE
XA, @PCXA
XA, @BCDE
XA, @BCXA
CY, *1
Bit transfer
*2
*2
*1 , CY
371
User’s Manual U10158EJ2V1UM00
CHAPTER 11 INSTRUCTION SET
Op Code
Instruction
Operation
Mnemonic
ADDS
Operand
B
1
B
2
B
3
A, #n4
XA, #n8
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
I
3
I
2
I
1
I
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
1
1
1
1
0
0
0
0
1
0
P
P
2
2
P
P
1
1
P
P
0
0
ADDC
SUBS
SUBC
AND
1
1
1
1
0
0
1
1
1
0
P
P
2
2
P
P
1
1
P
P
0
0
1
1
1
1
1
1
0
0
1
0
P
P
2
2
P
P
1
1
P
P
0
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
P
P
2
2
P
P
1
1
P
P
0
0
I
3
I
2
I
1
I
0
1
1
0
0
0
1
0
0
0
1
1
0
1
0
P
P
2
2
P
P
1
1
P
P
0
0
OR
I
3
I
2
I
1
I
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
P
P
2
2
P
P
1
1
P
P
0
0
XOR
I
3
I
2
I
1
I
0
1
1
0
0
1
1
1
1
1
0
P
P
2
2
P
P
1
1
P
P
0
0
Accumulator
manipula-
tion
RORC
NOT
A
0
1
0
1
1
1
1
1
User’s Manual U10158EJ2V1UM00
372
CHAPTER 11 INSTRUCTION SET
Op Code
Instruction
Mnemonic
INCS
Operand
B
1
B
2
B
3
Increment/
decrement
reg
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
R
2
R
1
R
0
rp1
P
2
P
1
0
1
0
@HL
mem
reg
0
0
0
1
0
0
0
0
0
0
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DECS
R
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
R
1
1
0
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
R
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
0
rp’
0
1
1
0
1
0
P
2
P
1
P0
Comparison SKE
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp’
CY
I
3
I
2
I
1
I
0
R
2
R
1
R
0
0
1
1
0
I
3
I
2
I
1
I
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
1
0
0
1
R
P
2
R
1
R
0
2
P
1
P
0
Carry flag
manipulation
SET1
CLR1
SKT
CY
CY
NOT1
SET1
CY
mem. bit
*1
B
1
B
0
D
D
D
D
7
D
D
D
D
6
D
D
D
D
5
D
4
D
D
D
D
3
D
D
D
D
2
2
2
2
D
D
D
D
1
1
1
1
D
D
D
D
0
0
0
0
Memory bit
manipula-
tion
0
1
*2
CLR1
SKT
mem. bit
*1
B
1
B
0
7
7
7
6
6
6
5
5
5
D
4
3
3
3
0
1
*2
mem. bit
*1
B
1
B
0
D
4
1
1
*2
SKF
mem. bit
*1
B
1
0
1
1
1
1
B
1
1
0
0
1
0
D
4
*2
*2
*2
*2
*2
SKTCLR
AND1
OR1
*1
CY, *1
CY, *1
CY, *1
XOR1
373
User’s Manual U10158EJ2V1UM00
CHAPTER 11 INSTRUCTION SET
Op Code
Instruction
Branch
Mnemonic
BR
Operand
B
1
B
2
B
3
addr
! addr
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
(+16) to (+2)
(–1) to (–15)
A
S
3
3
A
S
2
A
S
1
A
S
0
$ addr
2
1
0
PCDE
PCXA
BCDE
BCXA
! addr1
! caddr
! addr1
! addr
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
addr1
BRA
BRCB
CALLA
CALL
CALLF
RET
caddr
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
addr
addr
Subroutine/
stack
faddr
! faddr
1
0
1
1
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
0
0
1
1
0
1
1
RETS
RETI
PUSH
rp
P
2
P
1
BS
0
0
0
0
0
0
0
0
1
1
1
1
1
0
POP
IN
rp
P
0
0
0
0
0
1
1
1
1
1
1
0
0
0
2
P
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
BS
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
I/O
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
N
N
N
N
3
3
3
3
N
N
N
N
2
N
N
N
N
1
N
N
N
N
0
2
2
2
1
1
1
0
0
0
OUT
EI
0
1
0
1
0
0
0
1
0
Interrupt
control
IE×××
IE×××
N
5
N
2
N
1
N
0
DI
1
0
1
0
N
1
1
5
N
0
0
2
N
1
1
1
N
1
1
0
CPU control HALT
STOP
NOP
Special
SEL
RBn
MBn
taddr
0
0
0
0
1
0
0
1
0
0
N
N
1
N
N
0
N
3
N
2
1
0
GETI
T
5
T
4
T
3
T
2
T
1
T
0
User’s Manual U10158EJ2V1UM00
374
CHAPTER 11 INSTRUCTION SET
11.4 Instruction Function and Application
This section describes the functions and applications of the respective instructions. The instructions that can be
used and the functions of the instructions differ between the MkI and Mk2 modes of the µPD753204, 753206, 753208,
and 75P3216. Read the descriptions on the following pages according to the following guidance:
How to read
:
This instruction can be used commonly to all the following:
µPD753204
µPD753206
In MkI and MkII modes
µPD753208
µPD75P3216
:
:
:
This instruction can be used only in the MkI mode of the µPD753204, 753206, 753208, and 75P3216.
This instruction can be used only in the MkII mode of the µPD753204, 753206, 753208, and 75P3216.
I
II
This instruction can be used commonly in the MkI and MkII modes of the µPD753204, 753206, 753208,
and 75P3216, but the function may differ between the MkI and MkII modes.
In the MkI mode, refer to the description under the heading [MkI mode]. In the MkII mode, read the
description under the heading [MkII mode].
I/II
Remark In this section, it is assumed that the 13-bit program counter of the µPD753206 and µPD753208 is used.
Note that the program counter of the µPD753204 is 12 bits wide, and that of the µPD75P3216 is 14 bits
wide.
375
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11.4.1 Transfer instructions
MOV A, #n4
Function: A ← n4
n4 = I3-0: 0-FH
Transfers 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a string effect (group
A), and if the same instruction or MOV XA, #n8 follows this instruction, the string-effect instruction following the
instruction executed is processed as NOP.
Application example
(1) To set 0BH to the accumulator
MOV A, #08H
(2) To select data output to port 3 from 0 to 2
A0: MOV A, #0
A1: MOV A, #1
A2: MOV A, #2
OUT PORT3, A
MOV reg1, #n4
Function: reg1 ← n4
n4 = I3-0 0-FH
Transfers 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, or C).
MOV XA, #n8
Function: XA ← n8 n8 = I7-0: 00H-FFH
Transfers 8-bit immediate data n8 to register pair XA. This instruction has a string effect, and if two or more of
this instruction are executed in succession or if this instruction is followed by the MOV A, #n4 instruction, the instruction
following this instruction is treated as NOP.
MOV HL, #n8
Function: HL ← n8 n8 = I7-0: 00H-FFH
Transfers 8-bit immediate data n8 to register pair HL. This instruction has a string effect. If two or more of this
instructions are executed in succession, those that follow the first instruction are treated as NOP.
MOV rp2, #n8
Function: rp2 ← n8 n8 = I7-0: 00H-FFH
Transfers 8-bit immediate data n8 to register pair rp2 (BC, DE).
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MOV A, @HL
Function: A ← (HL)
Transfers the contents of the data memory addressed by register pair HL to the A register.
MOV A, @HL+
Function: A ← (HL), L ← L + 1
skip if L = 0H
Transfers the contents of the data memory addressed by register pair HL to the A register. After that, automatically
increments the contents of the L register by one. When the value of the L register reaches 0H as a result, skips the
next one instruction.
MOV A, @HL–
Function: A ← (HL), L ← L – 1
skip if L = FH
Transfers the contents of the data memory addressed by register pair HL to the A register. After that, automatically
decrements the contents of the L register by one. When the value of the L register reaches FH as a result, skips
the next one instruction.
MOV A, @rpa1
Function: A ← (rpa)
Where rpa = HL+ : skip if L = 0
Where rpa = HL– : skip if L = FH
Transfers the contents of the data memory addressed by register pair rpa (HL, HL+, HL–, DE, or DL) to the A
register.
If autoincrement (HL+) is specified as rpa, the contents of the L register are automatically incremented by one after
the data has been transferred. If the contents of the L register become 0 as a result, the next one instruction is skipped.
If autodecrement (HL–) is specified as rpa, the contents of the L register are automatically decremented by one
after the data has been transferred. If the contents of the L register become FH as a result, the next one instruction
is skipped.
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MOV XA, @HL
Function: A ← (HL), X ← (HL+1)
Transfers the contents of the data memory addressed by register pair HL to the A register, and the contents of
the next memory address to the X register.
If the contents of the L register are a odd number, an address whose least significant bit is ignored is transferred.
Application example
To transfer the data at addresses 3EH and 3FH to register pair XA
MOV HL, #3EH
MOV XA, @HL
MOV @HL, A
Function: (HL) ← A
Transfers the contents of the A register to the data memory addressed by register pair HL.
MOV @HL, XA
Function: (HL) ← A, (HL+1) ← X
Transfers the contents of the A register to the data memory addressed by register pair HL, and the contents of
the X register to the next memory address.
However, if the contents of the L register are a odd number, an address whose least significant bit is ignored is
transferred.
MOV A, mem
Function: A ← (mem) mem = D7-0: 00H-FFH
Transfers the contents of the data memory addressed by 8-bit immediate data to the A register.
MOV XA, mem
Function: A ← (mem), X ← (mem+1)
mem = D7-0: 00H-FEH
Transfers the contents of the data memory addressed by 8-bit immediate data mem to the A register and the
contents of the next address to the X register.
The address that can be specified by mem is an even address.
Application example
To transfer the data at addresses 40H and 41H to register pair XA
MOV XA, 40H
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MOV mem, A
Function: (mem) ← A mem = D7-0: 00H-FFH
Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem.
MOV mem, XA
Function: (mem) ← A, (mem+1) ← X
mem = D7-0: 00H-FFH
Transfers the contents of the A register to the data memory addressed by 8-bit immediate data and the contents
of the X register to the next memory address.
The address that can be specified by mem is an even address.
MOV A, reg
Function: A ← reg
Transfers the contents of register reg (X, A, H, L, D, E, B, or C) to the A register.
MOV XA, rp’
Function: XA ← rp’
Transfers the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) to register pair XA.
Application example
To transfer the data of register pair XA’ to register pair XA
MOV XA, XA’
MOV reg1, A
Function: reg1 ← A
Transfers the contents of the A register to register reg1 (X, H, L, D, E, B, or C).
MOV rp’1, XA
Function: rp’1 ← XA
Transfers the contents of register pair XA to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’).
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XCH A, @HL
Function: A ↔ (HL)
Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL.
XCH A, @HL+
Function: A ↔ (HL), L ← L + 1
skip if L = 0H
Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL. After
that, automatically increments the contents of the L register by one. If the contents of the L register reaches 0H as
a result, skips the next one instruction.
XCH A, @HL–
Function: A ↔ (HL), L ← L – 1
skip if L = FH
Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL. After
that, automatically decrements the contents of the L register by one.
If the contents of the L register reaches FH as a result, skips the next one instruction.
XCH A, @rpa1
Function: A ↔ (rpa)
Where rpa = HL+: skip if L = 0
Where rpa = HL–: skip if L = FH
Exchanges the contents of the A register with the contents of the data memory addressed by register pair rpa (HL,
HL+, HL–, DE, or DL). If autoincrement (HL+) or autodecrement (HL–) is specified as rpa, the contents of the L register
are automatically incremented or decremented by one after the data have been exchanged. If the result is 0 in the
case of HL+ and FH in the case of HL–, the next one instruction is skipped.
Application example
To exchange the data at data memory addresses 20H through 2FH with the data at addresses 30H through 3FH
SEL MB0
MOV D, #2
MOV HL, #30H
LOOP: XCH A, @HL
XCH A, @DL
; A ↔ (3×)
; A ↔ (2×)
XCH A, @HL+ ; A ↔ (3×)
BR LOOP
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XCH XA, @HL
Function: A ↔ (HL), X ↔ (HL+1)
Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL, and
the contents of the X register with the contents of the next address.
If the contents of the L register are odd numbers, however, an address whose least significant bit is ignored is
specified.
XCH A, mem
Function: A ↔ (mem) mem = D7-0: 00H-FFH
Exchanges the contents of the A register with the contents of the data memory addressed by 8-bit immediate data
mem.
XCH XA, mem
Function: A ↔ (mem), X ↔ (mem+1)
mem = D7-0: 00H-FEH
Exchanges the contents of the A register with the data memory contents addressed by 8-bit immediate data mem,
and the contents of the X register with the contents of the next memory address.
The address that can be specified by mem is an even address.
XCH A, reg1
Function: A ↔ reg1
Exchanges the contents of the A register with the contents of register reg1 (X, H, L, D, E, B, or C).
XCH XA, rp’
Function: XA ↔ rp’
Exchanges the contents of register pair XA with the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’,
or BC’).
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11.4.2 Table reference instructions
MOVT XA, @PCDE
Function: µPD753206 and µPD753208
XA ← ROM (PC12-8+DE)
Transfers the low-order 4 bits of the table data in the program memory addressed to the A resister when the low-
order 8 bits (PC7-0) of the program counter (PC) are replaced with the contents of register pair DE, and the high-order
4 bits to the X register.
The table address is determined by the contents of the program counter (PC) when this instruction is executed.
The necessary data must be programmed to the table area in advance by using an assembler pseudoinstruction
(DB instruction).
The program counter is not affected by execution of this instruction.
This instruction is useful for successively referencing table data.
Example In the case of µPD753206 or 753208
Program memory
7
4 3
0
8 7
4 3
0
Table
address
Table data H Table data L
PC12-8
D3-0
E3-0
3
0
3
0
X
A
Remark The function described here applies to the µPD753206 and 753208 that has a 13-bit program counter.
Note that the program counter of the µPD753204 is 12 bits wide and that of the µPD75P3216 is 14 bits
wide.
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Caution
The MOVT XA, @PCDE instruction usually references the table data in page where the instruction exists. If the
instruction is at address ××FFH, however, the table data in the page where the instruction exists is not referenced,
but the table data in the next page is.
Program memory
7
0
Page 2
02FFH
0300H
a
Page 3
For example, if the MOV XA, @PCDE instruction is located at position a in the above figure, the table data in page
3, not page 2, specified by the contents of register pair DE is transferred to register pair XA.
Application example
To transfer the 16-byte data at program memory addresses ××F0H through ××FFH to data memory addresses 30H
through 4FH
SUB:
SEL
MB0
MOV
MOV
HL, #30H
DE, #0F0H
; HL ← 30H
; DE ← F0H
LOOP: MOVT XA, @PCDE ; XA ← table data
MOV
INCS
INCS
INCS
BR
@HL, XA
HL
; (HL) ← XA
; HL ← HL+2
HL
E
; E ← E+1
LOOP
RET
ORG
DB
××F0H
××H, ××H, ··· ; table data
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MOVT XA, @PCXA
Function: µPD753206 and µPD753208
XA ← ROM (PC12-8+XA)
Transfers the low-order 4 bits of the table data in the program memory addressed to the A resister when the low-
order 8 bits (PC7-0) of the program counter (PC) are replaced with the contents of register pair XA, and the high-order
4 bits to the X register.
The table address is determined by the contents of the PC when this instruction is executed.
The necessary data must be º ogrammed to the table area in advance by using an assembler pseudoinstruction
(DB instruction). The PC is not affected by execution of this instruction.
Caution
If an instruction exists at address ××FFH, the table data of the next page is transferred, in the same manner as
MOVT XA, @PCDE.
Remark The function described here applies to the µPD753206 and 753208 that has a 13-bit program counter.
Note that the program counter of the µPD753204 is 12 bits wide and that of the µPD75P3216 is 14 bits
wide.
MOVT XA, @BCDE
Function: µPD753206 and 753208
XA ← ROM (B0+CDE)
Transfers the low-order 4 bits of the table data (8-bit) in the program memory addressed by the least significant
bit of register B and the contents of registers C, D, and E, to the A register, and the high-order 4 bits to the X register.
The necessary data must be programmed to the table area in advance by using an assembler pseudoinstruction
(DB instruction). The PC is not affected by execution of this instruction.
12
11
8 7
4 3
0
B0
C
D
E
Table data H
Table data L
3
0
3
0
X
A
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MOVT XA, @BCXA
Function: µPD753206 and 753208
XA ← ROM (B0+CXA)
Transfers the low-order 4 bits of the table data (8-bit) in the program memory addressed by the least significant
bit of register B and the contents of registers C, X, and A, to the A register, and the high-order 4 bits to the X register.
The necessary data must be programmed to the table area in advance by using an assembler pseudoinstruction
(DB instruction). The PC is not affected by execution of this instruction.
12
11
8 7
4 3
0
B0
C
X
A
Table data H
Table data L
3
0
3
0
X
A
Remark The function described here applies to the µPD753206 and 753208 that has a 13-bit program counter.
Note that the program counter of the µPD753204 is 12 bits wide and that of the µPD75P3216 is 14 bits
wide.
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11.4.3 Bit transfer instructions
MOV1 CY, fmem. bit
MOV1 CY, pmem. @L
MOV1 CY, @H+mem. bit
Function: CY ← (bit specified by operand)
Transfers the contents of the data memory addressed in the bit manipulating addressing mode (fmem. bit,
pmem. @L, or @H+mem. bit) to the carry flag (CY).
MOV1 fmem. bit, CY
MOV1 pmem. @L, CY
MOV1 @H+mem. bit, CY
Function: (Bit specified by operand) ← CY
Transfers the contents of the carry flag (CY) to the data memory bit addressed in the bit manipulation addressing
mode (fmem. bit, pmem. @L, or @H+mem. bit).
Application example
To output the flag of bit 3 at data memory address 3FH to the bit 2 of port 3
FLAG EQU 3FH.3
SEL
MB0
MOV
H, #FLAG SHR 6; H ← high-order 4 bits of FLAG
MOV1 CY, @H+FLAG ; CY ← FLAG
MOV1 PORT3. 2, CY ; P32 ← CY
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11.4.4 Operation instructions
ADDS A, #n4
Function: A ← A+n4; Skip if carry. n4 = l3-0: 0-FH
Adds 4-bit immediate data n4 to the contents of the A register. If a carry occurs as a result, the next instruction
is skipped. The carry flag is not affected.
If this instruction is used in combination with ADDC A, @HL or SUBC A, @HL instruction, it can be used as a base
number adjustment instruction (refer to 11.1.4 Base number adjustment instruction).
ADDS XA, #n8
Function: XA ← XA+n8; Skip if carry. n8 = I7-0: 00H-FFH
Adds 8-bit immediate data n8 to the contents of register pair XA. If a carry occurs as a result, the next instruction
is skipped. The carry flag is not affected.
ADDS A, @HL
Function: A ← A + (HL); Skip if carry.
Adds the contents of the data memory addressed by register pair HL to the contents of the A register. If a carry
occurs as a result, the next instruction is skipped. The carry flag is not affected.
ADDS XA, rp’
Function: XA ← XA + rp’; Skip if carry.
Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) to the contents of register pair XA.
If a carry occurs as a result, the next instruction is skipped. The carry flag is not affected.
ADDS rp’1, XA
Function: rp’ ← rp’1 + XA; Skip if carry.
Adds the contents of register pair XA to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’). If a carry occurs
as a result, the next instruction is skipped. The carry flag is not affected.
Application example
To shift a register pair to the left
MOV
XA, rp’1
ADDS rp’1, XA
NOP
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ADDC A, @HL
Function: A, CY ← A+ (HL) +CY
Adds the contents of the data memory addressed by register pair HL to the contents of the A register, including
the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset.
If the ADDS A, #n4 instruction is placed following this instruction, and if a carry occurs as a result of executing
this instruction, the ADDS A, #n4 instruction is skipped. If a carry does not occur, the ADDS A, #n4 instruction is
executed, and a function that disables the skip function of the ADDS A, #n4 instruction is effected. Therefore, these
instructions can be used in combination for base number adjustment (refer to 11.1.4 Base number adjustment
instruction).
ADDC XA, rp’
Function: XA, CY ← XA + rp’ + CY
Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) to the contents of register pair XA,
including the carry. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset.
ADDC rp’1, XA
Function: rp’1, CY ← rp’1+XA+CY
Adds the contents of register pair XA to the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), including
the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset.
SUBS A, @HL
Function: A ← A – (HL); Skip if borrow.
Subtracts the contents of the data memory addressed by register pair HL from the contents of the A register, and
sets the result to the A register. If a borrow occurs as a result, the next instruction is skipped.
The carry flag is not affected.
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SUBS XA, rp’
Function: XA ← XA – rp’; Skip if borrow.
Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) from the contents of register
pair XA, and sets the result to register pair XA. If a borrow occurs as a result, the next instruction is skipped.
The carry flag is not affected.
Application example
To compare specified data memory contents with the contents of a register pair
MOV
XA, mem
SUBS XA, rp’
; (mem) ≥ rp’
; (mem) < rp’
SUBS rp’1, XA
Function: rp’ ← rp’1 + XA; Skip if borrow.
Subtracts the contents of register pair XA from register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), and sets the
result to specified register pair rp’1. If a borrow occurs as a result, the next instruction is skipped.
The carry flag is not affected.
SUBC A, @HL
Function: A, CY ← A– (HL) –CY
Subtracts the contents of the data memory addressed by register pair HL to the contents from the A register,
including the carry flag, and sets the result to the A register. If a borrow occurs as a result, the carry flag is set; if
not, the carry flag is reset.
If an ADDS A, #n4 instruction is placed following this instruction, and if a borrow does not occur as a result of
executing this instruction, the ADDS A, #n4 instruction is skipped. If a borrow occurs, the ADDS A, #n4 instruction
is executed, and a function that disables the skip function of the ADDS A, #n4 instruction is effected. Therefore, these
instructions can be used in combination for base number adjustment (refer to 11.1.4 Base number adjustment
instruction).
SUBC XA, rp’
Function: XA, CY ← XA – rp’ – CY
Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) from the contents of register
pair XA, including the carry, and sets the result to register pair XA. If a borrow occurs as a result, the carry flag is
set; if not, the carry flag is reset.
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SUBC rp’1, XA
Function: rp’1, CY ← rp’1–XA–CY
Subtracts the contents of register pair XA from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or
BC’), including the carry flag, and sets the result to specified register pair rp’1. If a borrow occurs as a result, the carry
flag is set; if not, the carry flag is reset.
AND A, #n4
Function: A ← A n4 n4 = l3-0: 0-FH
ANDs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register.
Application example
To clear the high-order 2 bits of the accumulator to 0
AND A, #0011B
AND A, @HL
Function: A ← A (HL)
ANDs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets
the result to the A register.
AND XA, rp’
Function: XA ← XA rp’
ANDs the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) with the contents of register pair
XA, and sets the result to register pair XA.
AND rp’1, XA
Function: rp’ 1 ← rp’1 XA
ANDs the contents of register pair XA with register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), and sets the result
to the specified register pair.
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OR A, #n4
Function: A ← A n4 n4 = l3-0: 0-FH
ORs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register.
Application example
To set the low-order 3 bits of the accumulator to 1
OR A, #0111B
OR A, @HL
Function: A ← A (HL)
ORs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets
the result to the A register.
OR XA, rp’
Function: XA ← XA rp’
ORs the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) with the contents of register pair XA,
and sets the result to register pair XA.
OR rp’1, XA
Function: rp’ 1 ← rp’1 XA
ORs the contents of register pair XA with register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), and sets the result
to the specified register pair rp’1.
XOR A, #n4
Function: A ← A n4 n4 = l3-0: 0-FH
Exclusive-ORs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register.
Application example
To invert the high-order 4 bits of the accumulator
XOR A, #1000B
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XOR A, @HL
Function: A ← A (HL)
Exclusive-ORs the contents of the data memory addressed by register pair HL with the contents of the A register,
and sets the result to the A register.
XOR XA, rp’
Function: XA ← XA rp’
Exclusive-ORs the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) with the contents of register
pair XA, and sets the result to register pair XA.
XOR rp’1, XA
Function: rp’ 1 ← rp’1 XA
Exclusive-ORs the contents of register pair XA with register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), and sets
the result to the specified register pair rp’1.
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11.4.5 Accumulator manipulation instructions
RORC A
Function: CY ← A0, An–1 ← An, A3 ← CY (n = 1-3)
Rotates the contents of the A register (4-bit accumulator) 1 bit to the right with the carry flag.
A
CY
0
3
0
2
1
1
0
0
1
Before
execution
RORC A
After
execution
1
0
0
1
0
NOT A
Function: A ← A
Takes 1’s complement of the A register (4-bit accumulator) (inverts the bits of the accumulator).
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11.4.6 Increment/decrement instructions
INCS reg
Function: reg ← reg+1; Skip if reg = 0
Increments the contents of register reg (X, A, H, L, D, E, B, or C). If reg = 0 as a result, the next instruction is
skipped.
INCS rp1
Function: rp1 ← rp1+1; Skip if rp1 = 00H
Increments the contents of register pair rp1 (HL, DE, or BC). If rp1 = 00H as a result, the next instruction is skipped.
INCS @HL
Function: (HL) ← (HL)+1; Skip if (HL) = 0
Increments the contents of the data memory addressed by pair register HL. If the contents of the data memory
become 0 as a result, the next instruction is skipped.
INCS mem
Function: (mem) ← (mem) + 1; Skip if (mem) = 0, mem = D7-0: 00H-FFH
Increments the contents of the data memory addressed by 8-bit immediate data mem. If the contents of the data
memory become 0 as a result, the next instruction is skipped.
DECS reg
Function: reg ← reg–1; Skip if reg = FH
Decrements the contents of register reg (X, A, H, L, D, E, B, or C). If reg = FH as a result, the next instruction
is skipped.
DECS rp’
Function: rp’ ← rp’–1; Skip if rp’ = 00H
Decrements the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’ or BC’). If rp’ = FFH as a result, the
next instruction is skipped.
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11.4.7 Compare instructions
SKE reg, #n4
Function: Skip if reg = n4
n4 = I3-0: 0-FH
Skips the next instruction if the contents of register reg (X, A, H, L, D, E, B, or C) are equal to 4-bit immediate
data n4.
SKE @HL, #n4
Function: Skip if (HL) = n4
n4 = I3-0: 0-FH
Skips the next instruction if the contents of the data memory addressed by register pair HL are equal to 4-bit
immediate data n4.
SKE A, @HL
Function: Skip if A = (HL)
Skips the next instruction if the contents of the A register are equal to the contents of the data memory addressed
by register pair HL.
SKE XA, @HL
Function: Skip if A = (HL) and X = (HL + 1)
Skips the next instruction if the contents of the A register are equal to the contents of the data memory addressed
by register pair HL and if the contents of the X register are equal to the contents of the next memory address.
However, if the contents of the L register are an odd number, the address is determined as if the least significant
bit had been zero.
SKE A, reg
Function: Skip if A = reg
Skips the next one instruction if the contents of the A register are equal to register reg (X, A, H, L, D, E, B, or C).
SKE XA, rp’
Function: Skip if XA = rp’
Skips the next one instruction if the contents of register pair XA are equal to the contents of register pair rp’ (XA,
HL, DE, BC, XA’, HL’, DE’, or BC’).
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11.4.8 Carry flag manipulation instructions
SET1 CY
Function: CY ← 1
Sets the carry flag.
CLR1 CY
Function: CY ← 0
Clears the carry flag.
SKT CY
Function: Skip if CY = 1
Skips the next one instruction if the carry flag is 1.
NOT1 CY
Function: CY ← CY
Inverts the carry flag. Therefore, sets the carry flag to 1 if it is 0, and clears the flag to 0 if it is 1.
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11.4.9 Memory bit manipulation instructions
SET1 mem.bit
Function: (mem.bit) ← 1
mem = D7-0: 00H-FFH, bit = B1-0: 0-3
Sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem.
SET1 fmem. bit
SET1 pmem. @L
SET1 @H+mem. bit
Function: (bit specified by operand) ← 1
Sets the bit of the data memory addressed in the bit manipulation addressing mode (fmem. bit, pmem. @L, or
@H+mem. bit).
CLR1 mem. bit
Function: (mem.bit) ← 0
mem = D7-0: 00H-FFH, bit = B1-0: 0-3
Clears the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem.
CLR1 fmem. bit
CLR1 pmem. @L
CLR1 @H+mem. bit
Function: (bit specified by operand) ← 0
Clears the bit of the data memory addressed in the bit manipulation addressing mode (fmem. bit, pmem. @L, or
@H+mem. bit).
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SKT mem.bit
Function: Skip if (mem. bit) = 1
mem = D7-0: 00H-FFH, bit = B1-0: 0-3
Skips the next instruction if the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate
data mem is 1.
SKT fmem. bit
SKT pmem. @L
SKT @H+mem. bit
Function: Skip if (bit specified by operand) = 1
Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode
(fmem. bit, pmem. @L, or @H+mem. bit) is 1.
SKF mem.bit
Function: Skip if (mem. bit) = 0
mem = D7-0: 00H-FFH, bit = B1-0: 0-3
Skips the next instruction if the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate
data mem is 0.
SKF fmem. bit
SKF pmem. @L
SKF @H+mem. bit
Function: Skip if (bit specified by operand) = 0
Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode
(fmem. bit, pmem. @L, or @H+mem. bit) is 0.
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SKTCLR fmem. bit
SKTCLR pmem. @L
SKTCLR @H+mem. bit
Function: Skip if (bit specified by operand) = 1; then clear
Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode
(fmem. bit, pmem. @L, or @H+mem. bit) is 1, and then clears the bit to “0”.
AND1 CY, fmem. bit
AND1 CY, pmem. @L
AND1 CY, @H+mem. bit
Function: CY ← CY (bit specified by operand)
ANDs the content of the carry flag with the contents of the data memory addressed in the bit manipulation
addressing mode (fmem. bit, pmem. @L, or @H+mem. bit), and sets the result to the carry flag.
OR1 CY, fmem. bit
OR1 CY, pmem. @L
OR1 CY, @H+mem. bit
Function: CY ← CY (bit specified by operand)
ORs the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing
mode (fmem. bit, pmem. @L, or @H+mem. bit), and sets the result to the carry flag.
XOR1 CY, fmem. bit
XOR1 CY, pmem. @L
XOR1 CY, @H+mem. bit
Function: CY ← CY (bit specified by operand)
Exclusive-ORs the content of the carry flag with the contents of the data memory addressed in the bit manipulation
addressing mode (fmem. bit, pmem. @L, or @H+mem. bit), and sets the result to the carry flag.
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11.4.10 Branch instructions
BR addr
Function: µPD753208 PC12-0 ←addr
addr = 0000H-1FFFH
Branches to an address specified by immediate data addr.
This instruction is an assembler pseudoinstruction and is replaced by the assembler at assembly time with the
optimum instruction from the BR !addr, BRCB !caddr, and BR $addr instructions.
II
BR addr1
Function: µPD753208 PC12-0 ←addr1
addr1 = 0000H-1FFFH
Branches to an address specified by immediate data addr1.
This instruction is an assembler pseudoinstruction and is replaced by the assembler at assembly time with the
optimum instruction from the BRA !addr1, BRCB !addr, BRCB !caddr, and BR $addr1 instructions.
II
BRA !addr1
Function: µPD753208 PC12-0 ← addr1
BR !addr
Function: µPD753208 PC12-0 ←addr
addr = 0000H-1FFFH
Transfers immediate data addr to the program counter (PC) and branches to the address specified by the PC.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
BR $addr
Function: µPD753208 PC12-0 ← addr
addr = (PC–15) to (PC–1), (PC+2) to (PC+16)
This is a relative branch instruction that has a branch range of (–15 to –1) and (+2 to +16) from the current address.
It is not affected by a page boundary or block boundary.
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II
BR $addr1
Function: µPD753208 PC12-0 ←addr1
addr1 = (PC–15) to (PC–1), (PC+2) to (PC+16)
This is a relative branch instruction that has a branch range of (–15 to–1) and (+2 to +16) from the current address.
It is not affected by a page boundary or block boundary.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
BRCB !caddr
Function: µPD753208 PC12-0 ← PC12 + caddr11-0
caddr = n000H-nFFFH
n = PC12 = 0, 1
Branches to an address specified by the low-order 12 bits of the program counter (PC11-0) replaced with 12-bit
immediate data caddr.
Caution
The BRCB !caddr instruction usually branches execution within the block where the instruction exists. If the first
byte of this instruction is at address 0FFEH or 0FFFH, however, execution does not branch to block 0 but to block
1.
Program memory
7
0
Block 0
0FFEH
0FFFH
1000H
a
b
Block 1
If the BRCB !caddr instruction is at position a or b in the figure above, execution branches to block 1, not block
0.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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BR PCDE
Function: µPD753208 PC12-0 ← PC12-8 + DE
PC7-4 ← D, PC3-0 ← E
Branches to the address specified by the low-order 8 bits of the program counter (PC7-0) replaced with the contents
of register pair DE. The high-order bits of the program counter are not affected.
Caution
The BR PCDE instruction usually branches execution within the page where the instruction exists. If the first byte
of the op code is at address ××FE or ××FFH, however, execution does not branch in that page, but to the next page.
Program memory
7
0
Page 2
02FEH
02FFH
0300H
a
b
Page 3
For example, if the BR PCDE instruction is at position a or b in the above figure, execution branches to the low-
order 8-bit address specified by the contents of register pair DE in page 3, not in page 2.
BR PCXA
Function: µPD753208 PC12-0 ← PC12-8 + XA
PC7-4 ← X, PC3-0 ← A
Branches to the address specified by the low-order 8 bits of the program counter (PC7-0) replaced with the contents
of register pair XA. The high-order bits of the program counter are not affected.
Caution
This instruction branches execution to the next page, not to the same page, if the first byte of the op code is at
address ××FEH or ××FFH, in the same manner as the BR PCDE instruction.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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BR BCDE
Function: µPD753208 PC12-0 ← B0 + CDE
Branches to the address specified by the contents of the program counter replaced with the contents of registers
B0, C, D, and E.
12
11
8 7
4 3
0
PC
0
3
0
3
0
3
0
B
C
D
E
BR BCXA
Function: µPD753208 PC12-0 ← B0 + CXA
Branches to the address specified by the contents of the program counter replaced with the contents of registers
B0, C, X, and A.
12
11
8 7
4 3
0
PC
0
3
0
3
0
3
0
B
C
X
A
TBR addr
Function:
This is an assembler pseudoinstruction for table definition by the GETI instruction. It is used to replace a 3-byte
BR !addr instruction with a 1-byte GETI instruction. Code the 12-bit address data as addr. For details, refer to the
RA75X Assembler Package User’s Manual – Language.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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11.4.11 Subroutine/stack control instructions
II
CALLA !addr1
Function: µPD753208
(SP–2) ← ×, ×, MBE, RBE, (SP–3) ← PC7-4
(SP–4) ← PC3-0, (SP–5) ← 0, 0, 0, PC12
(SP–6) ← PC11-8
PC12–0 ← addr1, SP ← SP–6
I/II
CALL !addr
Function: µPD753208
[MkI mode]
(SP–1) ← PC7-4, (SP–2) ← PC3-0
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) ← PC11-8, PC12-0 ← addr, SP ← SP–8
addr = 0000H–1FFFH
[MkII mode]
(SP–2) ← ×, ×, MBE, RBE
(SP–3) ← PC7-4, (SP–4) ← PC3-0
(SP–5) ← 0, 0, 0, PC12, (SP–6) ← PC11-8
PC12–0 ← addr, SP ← SP–6
addr = 0000H-1FFFH
Saves the contents of the program counter (return address), MBE, and RBE to the data memory (stack) addressed
by the stack pointer (SP), decrements the SP, and then branches to the address specified by 14-bit immediate data
addr.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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I/II
CALLF !faddr
Function: µPD753208
[MkI mode]
(SP–1) ← PC7-4, (SP–2) ← PC3-0
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) ← PC11–8, SP ← SP–4
PC12–0 ← 00+faddr
faddr = 0000H–07FFH
[MkII mode]
(SP–2) ← ×, ×, MBE, RBE
(SP–3) ← PC7-4, (SP–4) ← PC3-0
(SP–5) ← 0, 0, 0, PC12, (SP–6) ← PC11-8
SP ← SP–6
PC12–0 ← 00+faddr
faddr = 0000H–07FFH
Saves the contents of the program counter (return address), MBE, and RBE to the data memory (stack) addressed
by the stack pointer (SP), decrements the SP, and then branches to the address specified by 11-bit immediate data
faddr. The address range from which a subroutine can be called is limited to 0000H to 07FFH (0 to 2047).
TCALL !addr
Function
This is an assembler pseudoinstruction for table definition by the GETI instruction. It is used to replace a 3-byte
CALL !addr instruction with a 1-byte GETI instruction. Code 12-bit address data as addr. For details, refer to the
RA75X Assembler Package User’s Manual – Language.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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I/II
RET
Function: µPD753208
[MkI mode]
PC11-8 ← (SP), MBE, RBE, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3), SP ← SP+4
[MkII mode] PC11-8 ← (SP), MBE, 0, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter (PC),
memory bank enable flag (MBE), and register bank enable flag (RBE), and then increments the contents of the SP.
Caution
None of the flags of the program status word (PSW), other than MBE and RBE, are restored.
I/II
RETS
Function: µPD753208
[MkI mode]
PC11-8 ← (SP), MBE, 0, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3), SP ← SP+4
Then skip unconditionally
[MkII mode] PC11-8 ← (SP), 0, 0, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3)
×, ×, MBE, RBE ← (SP+4), SP ← SP+6
Then skip unconditionally
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter (PC),
memory bank enable flag (MBE), and register bank enable flag (RBE), increments the contents of the SP, and then
skips unconditionally.
Caution
None of the flags of the program status word (PSW), other than MBE and RBE, are restored.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
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I/II
RETI
Function: µPD753208
[MkI mode]
PC11-8 ← (SP), MBE, RBE, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3)
PSWL ← (SP+4), PSWH ← (SP+5)
SP ← SP+6
[MkII mode]
PC11-8 ← (SP), 0, 0, 0, PC12 ← (SP+1)
PC3-0 ← (SP+2), PC7-4 ← (SP+3)
PSWL ← (SP+4), PSWH ← (SP+5)
SP ← SP+6
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter (PC)
and program status word (PSW), and then increments the contents of the SP.
This instruction is used to return execution from an interrupt processing routine.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
PUSH rp
Function: (SP–1) ← rpH, (SP–2) ← rpL, SP ← SP–2
Saves the contents of register pair rp (XA, HL, DE, or BC) to the data memory (stack) addressed by the stack pointer
(SP), and then decrements the contents of the SP.
The high-order 4 bits of the register pair (rpH: X, H, D, or B) are saved to the stack addressed by (SP-1), and the
low-order 4 bits (rpL: A, L, E, or C) are saved to the stack addressed by (SP-2).
PUSH BS
Function: (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2
Saves the contents of the memory bank select register (MBS) and register bank select register (RBS) to the data
memory (stack) addressed by the stack pointer (SP), and then decrements the contents of the SP.
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POP rp
Function: rpL ← (SP), rpH ← (SP+1), SP ← SP+2
Restores the contents of the data memory addressed by the stack pointer (SP) to register pair rp (XA, HL, DE,
or BC), and then increments the contents of the stack pointer.
The contents of (SP) are restored to the low-order 4 bits of the register pair (rpL: A, L, E, or C), and the contents
of (SP+1) are restored to the high-order 4 bits (rpH: X, H, D, or B).
POP BS
Function: RBS ← (SP), MBS ← (SP+1), SP ← SP+2
Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the register bank select
register (RBS) and memory bank select register (MBS), and then increments the contents of the SP.
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11.4.12 Interrupt control instructions
EI
Function: IME (IPS.3) ← 1
Sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “1” to enable interrupts.
Acknowledging an interrupt is controlled by an interrupt enable flag corresponding to the interrupt.
EI IE×××
Function: IE××× ← 1
××× = N5, N2-0
Sets a specified interrupt enable flag (IE×××) to “1” to enable acknowledging the corresponding interrupt (××× =
BT, CSI, T0, T, T2, W, 0, 2, or 4).
DI
Function: IME (IPS.3) ← 0
Resets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “0” to disable all interrupts,
regardless of the contents of the respective interrupt enable flags.
DI IE×××
Function: IE××× ← 1
××× = N5, N2-0
Resets a specified interrupt enable flag (IE×××) to “0” to disable acknowledging the corresponding interrupt (×××
= BT, CSI, T0, T1, T2, W, 0, 2, or 4).
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11.4.13 Input/output instructions
IN A, PORTn
Function: A ← PORTn n = N3-0: 0-3, 5, 6, 8, or 9
Transfers the contents of a port specified by PORTn (n = 0-3, 5, 6, 8, or 9) to the A register.
Caution
When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15). n can be 0 to 3, 5, 6,
8, or 9.
The data of the output latch is loaded to the A register in the output mode, and the data of the port pins are loaded
to the register in the input mode.
IN XA, PORTn
Function: A ← PORTn, X ← PORTn+1
n = N3-0: 8
Transfers the contents of the port specified by PORTn (n = 8) to the A register, and transfers the contents of the
next port to the X register.
Caution
Only 8 can be specified as n. When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS
= 15).
The data of the output latch is loaded to the A and X registers in the output mode, and the data of the port pins
are loaded to the registers in the input mode.
OUT PORTn, A
Function: PORTn ← A n = N3-0: 2, 3, 5, 6, 8, or 9
Transfers the contents of the A register to the output latch of a port specified by PORTn (n = 2, 3, 5, 6, 8, or 9).
Caution
When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15).
Only 2, 3, 5, 6, 8, or 9 can be specified as n.
OUT PORTn, XA
Function: PORTn, ← A, PORTn+1 ← X
n = N3-0: 8
Transfers the contents of the A register to the output latch of a port specified by PORTn (n = 8), and the contents
of the X register to the output latch of the next port.
Caution
When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15).
Only 8 can be specified as n.
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11.4.14 CPU control instructions
HALT
Function: PCC.2 ← 1
Sets the HALT mode (this instruction sets bit 2 of the processor clock control register).
Caution
Make sure that a NOP instruction follows the HALT instruction.
STOP
Function: PCC.3 ← 1
Sets the STOP mode (this instruction sets bit 3 of the processor clock control register).
Caution
Make sure that a NOP instruction follows the STOP instruction.
NOP
Function: Does nothing but consumes 1 machine cycle.
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11.4.15 Special instructions
SEL RBn
Function: RBS ← n
n = N1-0: 0-3
Sets 2-bit immediate data n to the register bank select register (RBS).
SEL MBn
Function: MBS ← n
n = N3-0: 0, 1, 15
Transfers 4-bit immediate data n to the memory bank select register (MBS).
I/II
GETI taddr
Function: µPD753208
taddr = T5-0, 0: 20H-7FH
[MkI mode]
•
When a table defined by the TBR instruction is referenced
PC12-0 ← (taddr)4-0 + (taddr+1)
•
When a table defined by the TCALL instruction is referenced
(SP–1) ← PC7-4, (SP–2) ← PC3-0
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) ← PC11-8
PC12-0 ← (taddr)4-0 + (taddr+1)
SP ← SP–4
•
When a table defined by an instruction other than TBR or TCALL is referenced
Executes instruction with (taddr) (taddr+1) as op code
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
[MkII mode]
•
When a table defined by the TBR instruction is referencedNote
PC12-0 ← (taddr)4-0 + (taddr+1)
•
When a table defined by the TCALL instruction is referencedNote
(SP–2) ← ×, ×, MBE, RBE
(SP–3) ← PC7-4, (SP–4) ← PC3-0
(SP–5) ← 0, 0, 0, PC12, (SP–6) ← PC11-8
PC12-0 ← (taddr)4-0 + (taddr+1)
SP ← SP–6
•
When a table defined by an instruction other than TBR and TCALL is referenced
Executes instruction with (taddr) (taddr+1) as op code
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Note The address specified by the TBR and TCALL instructions is limited to 0000H to 3FFFH.
References the 2-byte data at the program memory address specified by (taddr), (taddr+1) and executes it as an
instruction.
The area of the reference table consists of addresses 0020H through 007FH. Data must be written to this area
in advance. When the data to be written is 1-byte or 2-byte instructions, code the mnemonics directly.
When a 3-byte call instruction or 3-byte branch instruction is used, data is written by using an assembler
pseudoinstruction (TCALL or TBR).
Only an even address can be specified by taddr.
Remark The function described here applies to the µPD753208, which has a 13-bit program counter and addr
= 0000H-1FFFH. The µPD753204 has a 12-bit program counter and addr = 000H-FFFH, and the
µPD753206 has a 13-bit program counter and addr = 0000H-17FFH. The µPD75P3216 has a 14-bit
program counter and addr = 0000H-3FFFH.
Caution
Only the 2-machine cycle instructions can be placed in the reference table as a 2-byte instructions (except the
BRCB and CALLF instructions). Two 1-byte instructions can be used only in the following combinations:
Instruction of 1st byte
Instruction of 2nd byte
MOV
MOV
XCH
A, @HL
@HL, A
A, @HL
INCS
DECS
INCS
DECS
INCS
L
L
H
H
HL
MOV
XCH
A, @DE
A, @DE
INCS
DECS
INCS
DECS
INCS
E
E
D
D
DE
MOV
XCH
A, @DL
A, @DL
INCS
DECS
INCS
L
L
D
DECS
D
The contents of the PC are not incremented while the GETI instruction is executed. Therefore, after the referenced
instruction has been executed, processing continues from the address following that of the GETI instruction.
If the instruction preceding the GETI instruction has a skip function, the GETI instruction is skipped in the same
manner as other 1-byte instructions. If the instruction referenced by the GETI instruction has a skip function, the
instruction that follows the GETI instruction is skipped.
If an instruction having a string effect is referenced by the GETI instruction, it is executed as follows:
•
•
If the instruction preceding the GETI instruction has the string effect in the same group as the referenced
instruction, the string effect is lost and the referenced instruction is not skipped when GETI is executed.
If the instruction next to GETI has the string effect in the same group as the referenced instruction, the string
effect by the referenced instruction is valid, and the instruction following that instruction is skipped.
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User’s Manual U10158EJ2V1UM00
CHAPTER 11 INSTRUCTION SET
Application example
MOV
MOV
HL, #00H
XA, #FFH
Replaced by GETI
CALL SUB1
BR
SUB2
ORG
MOV
20H
HL00:
HL, #00H
XA, #FFH
SUB1
XAFF:
MOV
TCALL
TBR
.
.
.
.
.
.
CSUB1:
BSUB2:
SUB2
GETI HL00
; MOV HL, #00H
; BR SUB2
.
.
.
.
.
.
GETI BSUB2
.
.
.
.
.
.
GETI CSUB1
; CALL SUB1
; MOV XA, #FFH
.
.
.
.
.
.
GETI XAFF
User’s Manual U10158EJ2V1UM00
414
APPENDIX A µPD753108, 753208 AND 75P3216 FUNCTION LIST
Parameter
Program memory
µPD753108
Mask ROM
µPD753208
µPD75P3216
One-time PROM
0000H-1FFFH
0000H-3FFFH
(8192 × 8 bits)
(16384 × 8 bits)
Data memory
CPU
000H-1FFH
(512 × 4 bits)
75XL CPU
Instruction
execution
time
When main system
clock is selected
•
•
0.95, 1.91, 3.81, 15.3 µs (4.19 MHz operation)
0.67, 1.33, 2.67, 10.7 µs (6.0 MHz operation)
When subsystem
clock is selected
122 µs (32.768 kHz operation) None
I/O port
CMOS input
8 (Connection to internal pull- 6 (Connection to internal pull-up resistor can be specified
up resistor can be specified
by software: 7)
by software: 5)
CMOS input/output
20 (Connection to internal pull-up resistor can be specified by software)
N-ch open-drain input/output
4 (Pull-up resistor can be connected by mask option, 13 V
withstand voltage)
4 (Mask option not provided,
13 V withstand voltage)
Total
32
30
LCD controller/driver
Segment selection: 16/20/24
(can be changed to CMOS
input/output port in 4 time-
unit; max. 8)
Segment selection: 4/8/12
(can be changed to CMOS input/output port in 4 time-unit;
max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
Split resistor for LCD driver can be connected by mask option. Split resistor for LCD driver
cannot be connected
Timer
5 channels
5 channels
• 8-bit timer/event counter:
3 channels
• Basic interval timer
/watchdog timer:1 channel
• Watch timer: 1 channel
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels
Can be used as 16-bit timer counter, career generator,
timer with gate.
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Clock output (PCL)
Buzzer output (BUZ)
• Φ, 524, 262, 65.5 kHz (Main system clock: 4.19 MHz operation)
• Φ, 750, 375, 93.8 kHz (Main system clock: 6.0 MHz operation)
• 2, 4, 32 kHz
• 2, 4, 32 kHz
(Main system clock:
4.19 MHz operation,
subsystem clock:
(Main system clock: 4.19 MHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: 6.0 MHz operation)
32.768 kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock:
6.0 MHz operation)
Serial interface
3 modes are available
• 3-wire serial I/O mode ... MSB/LSB can be selected for top bit
• 2-wire serial I/O mode
• SBI mode
SCC register
SOS register
Provided
Not provided
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User’s Manual U10158EJ2V1UM00
APPENDIX A µPD753108, 753208 AND 75P3216 FUNCTION LIST
Parameter
Vectored interrupt
µPD753108
External: 3, internal: 5
External: 1, internal: 1
µPD753208
µPD75P3216
External: 2, internal: 5
Test input
Supply voltage
Operating ambient temperature
Package
VDD = 1.8 to 5.5 V
TA = –40 to +85 °C
• 64-pin plastic QFP
(14 × 14 mm)
48-pin plastic shrink SOP
(375 mil, 0.65 mm pitch)
• 64-pin plastic QFP
(12 × 12 mm)
User’s Manual U10158EJ2V1UM00
416
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD753208.
In 75XL series, the relocatable assembler which is common to the series is used in combination with the device
file of each product.
Language processor
RA75X relocatable assembler
Part number
Host machine
(product name)
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOSTM
Ver. 3.30 to
µS5A13RA75X
µS5A10RA75X
Note
Ver. 6.2
IBM PC/ATTM and
compatible machines
Refer to
“OS for IBM PC”
3.5-inch 2HC
5-inch 2HC
µS7B13RA75X
µS7B10RA75X
Device file
PC-9800 series
MS-DOS
3.5-inch 2HD
5-inch 2HD
µS5A13DF753208
µS5A10DF753208
Ver. 3.30 to
Note
Ver. 6.2
3.5-inch 2HC
5-inch 2HC
µS7B13DF753208
µS7B10DF753208
IBM PC/AT and
compatible machines
Refer to
“OS for IBM PC”
Note Although Ver. 5.00 and later has a task swap function, this function cannot be used with this software.
Remark The operations of the assembler and device file are guaranteed only on the above host machines and
OSs.
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APPENDIX B DEVELOPMENT TOOLS
PROM write tools
Hardware
PG-1500
PG-1500 is a PROM programmer which enables you to program single-chip microcontroller
including PROM by stand-alone or host machine operation by connecting an attached board
and optional programmer adapter to PG-1500. It also enables you to program typical PROM
devices of 256K bits to 4M bits.
PA-75P3216GT
PROM programmer adapter for the µPD75P3216GT. Connect the programmer adapter to
PG-1500 for use.
Software
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500
is controlled on the host machine.
Part number
(product name)
Host machine
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOS
Ver. 3.30 to
µS5A13PG1500
µS5A10PG1500
Note
Ver. 6.2
3.5-inch 2HC
5-inch 2HC
µS7B13PG1500
µS7B10PG1500
IBM PC/AT and
compatible machines
Refer to
“OS for IBM PC”
Note Ver.5.00 and later have the task swap function, but it cannot be used for this software.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.
User’s Manual U10158EJ2V1UM00
418
APPENDIX B DEVELOPMENT TOOLS
Debugging tool
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
µPD753208.
The system configurations are described as follows.
Note 1
Hardware
IE-75000-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-
753208GT-R that are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging
can be made.
It contains the emulation board IE-75000-R-EM which is connected.
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-
753208GT-R which are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM
programmer.
IE-75300-R-EM
EP-753208GT-R
Emulation board for evaluating the application systems that use a µPD753208
subseries.
It must be used with the IE-75000-R or IE-75001-R.
Emulation probe for the µPD753208GT.
It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the flexible board adapter EV-9500GT-48 which facilitates
connection to a target system.
EV-9500GT-48
Software
IE control program
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix
I/F and controls the above hardware on a host machine.
Part No.
(product name)
Host machine
OS
Distribution media
3.5-inch 2HD
5-inch 2HD
PC-9800 series
MS-DOS
Ver. 3.30 to
µS5A13IE75X
µS5A10IE75X
Note 2
Ver. 6.2
3.5-inch 2HC
5-inch 2HC
µS7B13IE75X
µS7B10IE75X
IBM PC/AT and its
compatible machine
Refer to
“OS for IBM PC”
Notes 1. Maintenance parts
2. Although Ver. 5.00 and later have a task swap function, this function cannot be used with this software.
Remarks 1. The operation of the IE control program is guaranteed only on the above host machines and OSs.
2. The µPD753204, 753206, 753208, and 75P3216 are generally called the µPD753208 subseries.
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User’s Manual U10158EJ2V1UM00
APPENDIX B DEVELOPMENT TOOLS
OS for IBM PC
The following IBM PC OSs are supported.
OS
Version
TM
PC DOS
Ver. 5.02 to Ver. 6.3
Note
Note
J6.1/V
to J6.3/V
MS-DOS
IBM DOS
Ver. 5.0 to Ver. 6.22
Note
Note
5.0/V
to J6.2/V
TM
Note
J5.02/V
Note Only English version is supported.
Caution Although the Ver. 5.0 and later have a task swap function, this function cannot be used with
this software.
User’s Manual U10158EJ2V1UM00
420
Development Tool Configuration
In-circuit emulator
IE-75000-R or
IE-75001-R
Emulation probe
EP-753208GT-R
Centronics I/F
Emulation board
IE-75300-R-EM Note1
RS-232-C
IE
control program
Host machine
PC-9800 series
IBM PC/AT
Target system
Note 2
Symbolic
PG-1500
controller
debug enable
Internal PROM
version
PROM programmer
PG-1500
µ
PD75P3216GT
+
Relocatable
assembler
+
Programmer adapter
Notes 1. In-circuit emulator does not contain IE-75300-R-EM. (option)
2. EV-9500GT-48
PA-75P3216GT
Device file
[MEMO]
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User’s Manual U10158EJ2V1UM00
APPENDIX C ORDERING MASK ROMS
After your program has been developed, place an order for a mask ROM using the following procedure:
<1> Reservation for ordering mask ROM
Inform NEC of your schedule to place an order for the mask ROM (NEC’s response may be delayed if it is not
informed in advance).
<2> Preparation of ordering media
The following three media for ordering the mask ROM are available:
• UV-EPROMNote
• 3.5-inch IBM-format floppy disk (overseas only)
• 5-inch IBM-format floppy disk (overseas only)
Note Prepare three UV-EPROMs having the same contents.
For the product with mask option, write down the mask option data on the mask otion information sheet.
<3> Preparation of necessary documents
Fill out the following documents when ordering the mask ROM:
A. Mask ROM Ordering Sheet
B. Mask ROM Ordering Check Sheet
C. Mask Option Information Sheet (necessary for product with mask option)
<4> Ordering
Submit the media prepared in <2> and documents prepared in <3> to NEC by the reserved date.
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User’s Manual U10158EJ2V1UM00
[MEMO]
424
User’s Manual U10158EJ2V1UM00
APPENDIX D INSTRUCTION INDEX
D.1 Instruction Index (by function)
[Transfer instructions]
A, #n4 ··· 357, 376
MOV1
MOV1
pmem. @L, CY ··· 358, 386
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
@H+mem. bit, CY ··· 358, 386
reg1, #n4 ··· 357, 376
XA, #n8 ... 357, 376
HL, #n8 ... 357, 376
rp2, #n8 ... 357, 376
A, @HL ... 357, 377
A, @HL+ ... 357, 377
A, @HL– ... 357, 377
A, @rpa1 ··· 357, 377
XA, @HL ··· 357, 378
@HL, A ··· 357, 378
@HL, XA ··· 357, 378
A, mem ··· 357, 378
XA, mem ··· 357, 378
mem, A ··· 357, 379
mem, XA ··· 357, 379
A, reg ··· 357, 379
[Operation instructions]
ADDS
ADDS
ADDS
ADDS
ADDS
ADDC
ADDC
ADDC
SUBS
SUBS
SUBS
SUBC
SUBC
SUBC
AND
A, #n4 ··· 358, 387
XA, #n8 ··· 358, 387
A, @HL ··· 358, 387
XA, rp’ ··· 358, 387
rp’1, XA ··· 358, 387
A, @HL ··· 358, 388
XA, rp’ ··· 358, 388
rp’1, XA ··· 358, 388
A, @HL ··· 359, 388
XA, rp’ ··· 359, 389
rp’1, XA ··· 359, 389
A, @HL ··· 359, 389
XA, rp’ ··· 359, 389
rp’1, XA ··· 359, 390
A, #n4 ··· 359, 390
A, @HL ··· 359, 390
XA, rp’ ··· 359, 390
rp’1, XA ··· 359, 390
A, #n4 ··· 359, 391
A, @HL ··· 359, 391
XA, rp’ ··· 359, 391
rp’1, XA ··· 359, 391
A, #n4 ··· 359, 391
A, @HL ··· 359, 392
XA, rp’ ··· 359, 392
rp’1, XA ··· 359, 392
XA, rp’ ··· 357, 379
reg1, A ··· 357, 379
rp’1, XA ··· 357, 379
A, @HL ... 357, 380
A, @HL+ ... 357, 380
A, @HL– ... 357, 380
A, @rpa1 ··· 357, 380
XA, @HL ··· 357, 381
A, mem ··· 357, 381
XA, mem ··· 357, 381
A, reg1 ··· 357, 381
XA, rp’ ··· 357, 381
AND
AND
AND
OR
OR
OR
OR
XOR
XOR
XOR
XOR
[Table reference instructions]
[Accumulator manipulation instructions]
MOVT
MOVT
MOVT
MOVT
XA, @PCDE ··· 358, 382
XA, @PCXA ··· 358, 384
XA, @BCDE ··· 358, 384
XA, @BCXA ··· 358, 385
RORC
NOT
A ··· 359, 393
A ··· 359, 393
[Increment/decrement instructions]
INCS
INCS
INCS
INCS
DECS
DECS
reg ··· 359, 394
rp1 ··· 359, 394
@HL ··· 359, 394
mem ··· 359, 394
reg ··· 359, 394
rp’ ··· 359, 394
[Bit transfer instructions]
MOV1
MOV1
MOV1
MOV1
CY, fmem. bit ··· 358, 386
CY, pmem. @L ··· 358, 386
CY, @H+mem. bit ··· 358, 386
fmem. bit, CY ··· 358, 386
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User’s Manual U10158EJ2V1UM00
APPENDIX D INSTRUCTION INDEX
[Compare instructions]
BR
!addr ··· 361, 400
SKE
SKE
SKE
SKE
SKE
SKE
reg, #n4 ··· 359, 395
BR
$addr ··· 361, 400
$addr1 ··· 362, 401
!caddr ··· 363, 401
PCDE ··· 362, 402
PCXA ··· 362, 402
BCDE ··· 362, 403
BCXA ··· 362, 403
addr ··· 368, 403
@HL, #n4 ··· 359, 395
A, @HL ··· 359, 395
XA, @HL ··· 359, 395
A, reg ··· 359, 395
BR
BRCB
BR
BR
XA, rp’ ··· 359, 395
BR
BR
[Carry flag manipulation instructions]
TBR
SET1
CLR1
SKT
CY ··· 360, 396
CY ··· 360, 396
CY ··· 360, 396
CY ··· 360, 396
[Subroutine/stack control instructions]
CALLA !addr1 ··· 363, 404
NOT1
CALL
!addr ··· 363, 404
!faddr ··· 364, 405
CALLF
[Memory bit manipulation instructions]
TCALL !addr ··· 368, 405
RET ··· 364, 406
SET1
SET1
SET1
SET1
CLR1
CLR1
CLR1
CLR1
SKT
mem. bit ··· 360, 397
fmem. bit ··· 360, 397
pmem. @L ··· 360, 397
@H+mem. bit ··· 360, 397
mem. bit ··· 360, 397
fmem. bit ··· 360, 397
pmem. @L ··· 360, 397
@H+mem. bit ··· 360, 397
mem. bit ··· 360, 398
fmem. bit ··· 360, 398
pmem. @L ··· 360, 398
@H+mem. bit ··· 360, 398
mem. bit ··· 360, 398
fmem. bit ··· 360, 398
pmem. @L ··· 360, 398
@H+mem. bit ··· 360, 398
RETS ··· 365, 406
RETI ··· 366, 407
PUSH
PUSH
POP
rp ··· 366, 407
BS ··· 366, 407
rp ··· 366, 408
BS ··· 366, 408
POP
[Interrupt control instructions]
SKT
EI ··· 366, 409
SKT
EI
IE××× ··· 366, 409
SKT
DI ··· 366, 409
SKF
DI
IE××× ··· 366, 409
SKF
SKF
[Input/output instructions]
SKF
IN
A, PORTn ··· 367, 410
SKTCLR fmem. bit ··· 360, 399
SKTCLR pmem. @L ··· 360, 399
SKTCLR @H+mem. bit ··· 360, 399
IN
XA, PORTn ··· 367, 410
PORTn, A ··· 367, 410
PORTn, XA ··· 367, 410
OUT
OUT
AND1
AND1
AND1
OR1
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
[CPU control instructions]
HALT ··· 367, 411
STOP ··· 367, 411
OR1
NOP ··· 367, 411
OR1
XOR1
XOR1
XOR1
[Special instructions]
SEL
SEL
GETI
RBn ··· 367, 412
MBn ··· 367, 412
taddr ··· 367, 412
[Branch instructions]
BR
addr ··· 361, 400
BR
addr1 ··· 361, 400
!addr1 ··· 363, 400
BRA
User’s Manual U10158EJ2V1UM00
426
APPENDIX D INSTRUCTION INDEX
D.2 Instruction Index (alphabetical order)
[E]
EI ··· 366, 409
EI IE××× ··· 366, 409
[A]
ADDC
A, @HL ··· 358, 388
rp’1, XA ··· 358, 388
XA, rp’ ··· 358, 388
ADDC
ADDC
ADDS
ADDS
ADDS
ADDS
ADDS
AND
[G]
GETI
A, #n4 ··· 358, 387
taddr ··· 367, 412
A, @HL ··· 358, 387
rp’1, XA ··· 358, 387
XA, rp’ ··· 358, 387
[H]
HALT ··· 367, 412
XA, #nB ··· 358, 387
A, #n4 ··· 358, 390
[I]
AND
A, @HL ··· 358, 390
rp’1, XA ··· 358, 390
XA, rp’ ··· 358, 390
IN
A, PORTn ··· 367, 410
XA, PORTn ··· 367, 410
mem ··· 359, 394
reg ··· 359, 394
AND
IN
AND
INCS
INCS
INCS
INCS
AND1
AND1
AND1
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
rp1 ··· 359, 394
@HL ··· 359, 394
[B]
[M]
MOV
BR
addr ··· 361, 400
addr1 ··· 361, 400
BCDE ··· 361, 403
BCXA ··· 361, 403
PCDE ··· 361, 402
PCXA ··· 361, 402
!addr ··· 361, 400
$addr ··· 361, 400
$addr1 ··· 361, 401
!addr1 ··· 363, 400
!caddr ··· 363, 401
A, mem ··· 357, 378
A, reg ··· 357, 379
BR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVT
MOVT
MOVT
MOVT
MOV1
MOV1
BR
A, #n4 ··· 357, 376
BR
A, @HL ... 357, 377
A, @HL+ ... 357, 377
A, @HL– ... 357, 377
A, @rpa1 ··· 357, 377
HL, #n8 ... 357, 376
mem, A ··· 357, 379
mem, XA ··· 357, 379
reg1, A ··· 357, 379
BR
BR
BR
BR
BR
BRA
BRCB
reg1, #n4 ··· 357, 376
rp2, #n8 ... 357, 376
rp’1, XA ··· 357, 378
XA, mem ··· 357, 381
XA, rp’ ··· 357, 381
[C]
CALL
!addr ··· 363, 404
CALLA !addr1 ··· 363, 404
CALLF
CLR1
CLR1
CLR1
CLR1
CLR1
!faddr ··· 364, 405
CY ··· 360, 396
XA, @HL ··· 357, 381
@HL, A ··· 357, 378
@HL, XA ··· 357, 378
XA, #n8 ... 357, 376
XA, @BCDE ··· 358, 384
XA, @BCXA ··· 358, 385
XA, @PCDE ··· 358, 382
XA, @PCXA ··· 358, 384
CY, fmem. bit ··· 358, 386
CY, pmem. @L ··· 358, 386
fmem. bit ··· 360, 397
mem. bit ··· 360, 397
pmem. @L ··· 360, 397
@H+mem. bit ··· 360, 397
[D]
DECS
DECS
reg ··· 359, 394
rp’ ··· 359, 394
DI ··· 366, 409
DI IE××× ··· 366, 409
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User’s Manual U10158EJ2V1UM00
APPENDIX D INSTRUCTION INDEX
MOV1
MOV1
MOV1
MOV1
CY, @H+mem. bit ··· 358, 386
SKF
SKF
SKF
SKT
SKT
SKT
SKT
SKT
mem. bit ··· 360, 398
fmem. bit, CY ··· 358, 386
pmem. @L, CY ··· 358, 386
@H+mem. bit, CY ··· 358, 386
pmem. @L ··· 360, 398
@H+mem. bit ··· 360, 398
CY ··· 360, 398
fmem. bit ··· 360, 398
mem. bit ··· 360, 398
pmem. @L ··· 360, 398
@H+mem. bit ···· 360, 398
[N]
NOP ··· 367, 411
NOT
A ··· 359, 393
NOT1
CY ··· 360, 396
SKTCLR fmem. bit ··· 360, 399
SKTCLR pmem. @L ··· 360, 399
SKTCLR @H+mem. bit ··· 360, 399
STOP ··· 367, 412
[O]
OR
A, #n4 ··· 359, 391
OR
A, @HL ··· 359, 391
SUBC
SUBC
SUBC
SUBS
SUBS
SUBS
A, @HL ··· 359, 389
rp’1, XA ··· 359, 390
XA, rp’ ··· 359, 389
A, @HL ··· 359, 388
rp’1, XA ··· 359, 389
XA, rp’ ··· 359, 389
OR
rp’1, XA ··· 359, 391
OR
XA, rp’ ··· 359, 391
OR1
OR1
CR1
OUT
OUT
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
PORTn, A ··· 367, 410
PORTn, XA ··· 367, 410
[T]
TBR
addr ··· 368, 403
[P]
TCALL !addr ··· 368, 405
POP
BS ··· 366, 408
rp ··· 366, 408
BS ··· 366, 407
rp ··· 366, 407
POP
[X]
PUSH
PUSH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XOR
XOR
XOR
XOR
XOR1
XOR1
XOR1
A, mem ··· 357, 381
A, reg1 ··· 357, 381
XA, @HL ··· 357, 381
A, @HL+ ... 357, 380
A, @HL– ... 357, 380
A, @rpa1 ··· 357, 380
XA, mem ··· 357, 381
XA, rp’ ··· 357, 381
[R]
RET ··· 364, 406
RETI ··· 366, 407
RETS ··· 365, 406
RORC
A ··· 359, 393
A, #n4 ··· 359, 391
[S]
A, @HL ··· 359, 392
rp’1, XA ··· 359, 392
XA, rp’ ··· 359, 392
SEL
MBn ··· 367, 412
SEL
RBn ··· 367, 412
SET1
SET1
SET1
SET1
SET1
SKE
SKE
SKE
SKE
SKE
SKE
SKF
CY ··· 360, 396
CY, fmem. bit ··· 360, 399
CY, pmem. @L ··· 360, 399
CY, @H+mem. bit ··· 360, 399
fmem. bit ··· 360, 397
mem. bit ··· 360, 397
pmem. @L ··· 360, 397
@H+mem. bit ··· 360, 397
A, reg ··· 359, 395
A, @HL ··· 359, 395
reg, #n4 ··· 359, 395
XA, rp’ ··· 359, 395
XA, @HL ··· 359, 395
@HL, #n4 ··· 359, 395
fmem. bit ··· 360, 398
User’s Manual U10158EJ2V1UM00
428
APPENDIX E HARDWARE INDEX
[A]
ACKD ··· 206
IRQCSI ··· 299
IRQT0 ··· 299
IRQT1 ··· 299
IRQT2 ··· 299
IRQW ··· 322
ACKE ··· 206
ACKT ··· 206
[B]
IST0, IST1 ··· 306
BS ··· 97
BSB0-BSB3 ··· 292
BSYE ··· 206
BT ··· 132
[K]
KR0-KR3 ··· 323
BTM ··· 129
[L]
LCDC ··· 267
LCDM ··· 265
[C]
CLOM ··· 126
CMDD ··· 207
CMDT ··· 207
COI ··· 204
[M]
MBE ··· 96
MBS ··· 97
CSIE ··· 203
CSIM ··· 202
CY ··· 93
[N]
NRZ ··· 149
NRZB ··· 149
[I]
IE0 ··· 299
IE2 ··· 322
IE4 ··· 299
IEBT ··· 299
IECSI ··· 299
IET0 ··· 299
IET1 ··· 299
IET2 ··· 299
IEW ··· 322
IM0 ··· 305
IM2 ··· 325
IME ··· 301
INTA ··· 72
INTC ··· 72
INTE ··· 72
INTF ··· 72
INTG ··· 72
INTH ··· 72
IPS ··· 300
IRQ0 ··· 299
IRQ2 ··· 322
IRQ4 ··· 299
IRQBT ··· 299
[P]
PC ··· 77
PCC ··· 118
PMGA, PMGB, PMBC ··· 106
POGA, POGB ··· 113
PORT0-PORT9 ··· 99
PSW ··· 93
[R]
RBE ··· 96
RBS ··· 97
RELD ··· 207
RELT ··· 207
REMC ··· 149
[S]
SBIC ··· 205
SBS ··· 89
SIO ··· 208
SK0-SK2 ··· 94
SP ··· 89
SVA ··· 209
429
User’s Manual U10158EJ2V1UM00
APPENDIX E HARDWARE INDEX
[T]
T0 ··· 71
TGCE ··· 149
TM0, TM1, TM2 ··· 144
TMOD0, TMOD1, TMOD2 ··· 156
TMOD2H ··· 165
TOE0 ··· 148
TOE1 ··· 148
TOE2 ··· 149
[W]
WDTM ··· 131
WM ··· 139
WUP ··· 204
User’s Manual U10158EJ2V1UM00
430
APPENDIX F REVISION HISTORY
The revision history is described below. The “Applied to” column indicates the chapters in each edition.
Edition
Major Revisions from Previous Edition
Applied to
2nd edition
Change of µPD753204, 753206, 753208, and
75P3216 from “under development” to “have been
developed”.
Throughout
Change of input withstand voltage of ports 4 and 5
at N-ch open drain from 12 V to 13 V.
Addition of data bus pins (D0-D7).
Change of List of Recommended Connections for
Unused Pins.
CHAPTER 2 PIN FUNCTIONS
Change of Differences between Mk I Mode and Mk II
Mode.
CHAPTER 4 INTERNAL CPU FUNCTIONS
Addition of caution to Bus release signal (REL) and
Command signal (CMD).
CHAPTER 5 PERIPHERAL HARDWARE
FUNCTIONS
Addition of Mask Option Selection.
CHAPTER 7 STANDBY FUNCTIONS
CHAPTER 9 WRITING AND VERIFYING
PROM (PROGRAM MEMORY)
Change of Writing Program Memory.
Change of Reading Program Memory
Modification of the instruction list
CHAPTER 11 INSTRUCTION SET
APPENDIX C ORDERING MASK ROMS
Change of ordering media of ORDERING MASK ROMS.
431
User’s Manual U10158EJ2V1UM00
[MEMO]
432
User’s Manual U10158EJ2V1UM00
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CS 99.1
相关型号：
UPD75P3216GT-A
Microcontroller, 4-Bit, OTPROM, 6MHz, MOS, PDSO48, 0.375 INCH, 0.65 MM PITCH, LEAD FREE, PLASTIC, SSOP-48
NEC
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